3310C-1-202L - BOURNS - Datasheet.Live

Features

•High Performance, Low Power AVR® 8-Bit Microcontroller

•Advanced RISC Architecture

– 123 Powerful Instructions – Most Single Clo ck Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

•Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash

• Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes Intern al SRAM

– Data retention: 20 years at 85°C / 100 years at 25C

– Programming Lock for Self-Programming Flash Program & EEPROM Data Security

•Peripheral Features

– 8/16-bit Timer/Counter with Prescaler

– 8/10-bit High Speed Timer/Counter with Separate Prescaler

• 3 High Frequency PWM Outputs with Separate Output Compare Registers

• Programmable Dead Time Generator

– 10-bit ADC

• 11 Single-Ended Channels

• 16 Differential ADC Channel Pairs

• 15 Differential ADC Chan nel Pairs with Programmable Gain (1x, 8x, 20x, 32x)

– On-chip Analog Comparator

– Programmable Watchdog Timer with Separate On-chip Oscillator

– Universal Serial Interface with Start Condition Detector

•Spec ia l Micr oc ontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes

– Enhanced Power-on Reset Circuit

– Programmable Brow n-out Detection Circuit

– Internal Calibrated Oscillator

– On-chip Temperature Se ns or

•I/O and Packages

– 16 Programmable I/O Lines

– Available in 20-pin PDIP, 20-pin SOIC and 32-pad MLF

•Operating Voltage:

– 1.8 – 5.5V for ATtiny261V/461V/861V

– 2.7 – 5.5V for ATtiny261/461/861

•Speed Grade:

– ATtiny261V/461V/861V: 0 – 4 MHz @ 1.8 – 5.5V, 0 – 10 MHz @ 2.7 – 5.5V

– ATtiny261/461/861: 0 – 10 MHz @ 2.7 – 5.5V, 0 – 20 MHz @ 4.5 – 5.5V

•Industrial Temperature Range

•Low Power Consumption

– Active Mode (1 MHz System Clock): 300 µA @ 1.8V

– Power-Down Mode: 0.1 µA at 1.8V

8-bit

Microcontroller

with 2/4/8K

Bytes In-System

Programmable

Flash

ATtiny261/V*

ATtiny461/V

ATtiny861/V

*Mature

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1. Pin Configurations

Figure 1-1. Pinout ATtiny261/461/861 and ATtiny261V/461V/861V

Note: To ensure mechanical stability the center pad underneath the QFN/MLF package should be soldered to ground on the board.

(MOSI/DI/SDA/OC1A/PCINT8) PB0

(MISO/DO/OC1A/PCINT9) PB1

(SCK/USCK/SCL/OC1B/PCINT10) PB2

(OC1B/PCINT11) PB3

VCC

GND

(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4

(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5

(ADC9/INT0/T0/PCINT14) PB6

(ADC10/RESET/PCINT15) PB7

PA0 (ADC0/DI/SDA/PCINT0)

PA1 (ADC1/DO/PCINT1)

PA2 (ADC2/INT1/USCK/SCL/PCINT2)

PA3 (AREF/PCINT3)

AGND

AVCC

PA4 (ADC3/ICP0/PCINT4)

PA5 (ADC4/AIN2/PCINT5)

PA6 (ADC5/AIN0/PCINT6)

PA7 (ADC6/AIN1/PCINT7)

PDIP/SOIC

(OC1B/PCINT11) PB3

VCC

GND

(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4

(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5

PA2 (ADC2/INT1/USCK/SCL/PCINT2)

PA3 (AREF/PCINT3)

AGND

AVCC

PA4 (ADC3/ICP0/PCINT4)

(ADC9/INT0/T0/PCINT14) PB6

(ADC10/RESET/PCINT15) PB7

(ADC6/AIN1/PCINT7) PA7

(ADC5/AIN0/PCINT6) PA6

(ADC4/AIN2/PCINT5) PA5

PB2 (SCK/USCK/SCL/OC1B/PCINT10)

PB1 (MISO/DO/OC1A/PCINT9)

PB0 (MOSI/DI/SDA/OC1A/PCINT8)

PA0 (ADC0/DI/SDA/PCINT0)

PA1 (ADC1/DO/PCINT1)

QFN/MLF

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1.1 Pin Descriptions

1.1.1 VCC Supply voltage.

1.1.2 GND Ground.

1.1.3 AVCC Analog supply voltage. This is the supply voltage pin for the Analog-to-digital Converter (ADC),

the analog comparator, the Brown-Out Detector (BOD), the internal voltage reference and Port

A. It should be externally connected to VCC, even if some peripherals such as the ADC are not

used. If the ADC is used AVCC should be connected to VCC through a low-pass filter.

1.1.4 AGND Analog ground .

1.1.5 Port A (PA7:PA0)

An 8-bit, bi-directional I/O port with internal pull- up resistors, individually selectable for each bit.

Output buffers have symmetrical drive charac teristics with both high sink and source capability.

As inputs, port pins that are externally pulled low will source current if pull-up resistors have

been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port A also serves the functions of various special features of the device, as listed on page 63.

1.1.6 Port B (PB7:PB0)

An 8-bit, bi-directional I/O port with internal pull- up resistors, individually selectable for each bit.

Output buffers have symmetrical drive charac teristics with both high sink and source capability.

As inputs, port pins that are externally pulled low will source current if pull-up resistors have

been activated. Port pins are tri-stated when a reset condition becomes active, even if the clock

is not running.

Port B also serves the functions of various special features of the device, as listed on page 66.

1.1.7 RESET Reset input. A low level on this pin for longer than the minimum pulse length will gen erate a

reset, even if the clock is not runn ing and prov ided the reset pin has not be en disabled . The min-

imum pulse length is given in Table 19-4 on page 190. Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

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2. Overview ATtiny261/461/861 are low-power CMOS 8-bit microcontrollers based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the

ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus pr ocessing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achiev ing throughputs up to ten times faster than con-

ventional CISC microcontrollers.

PORT A (8)PORT B (8)

USI

Timer/Counter1

Timer/Counter0 A/D Conv.

Internal

Bandgap

Analog Comp.

SRAMFlash

EEPROM

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

Power

Supervision

POR / BOD &

RESET

VCC

GND

PROGRAM

LOGIC

debugWIRE

AGND

AREF

AVCC

D ATA BU S

PA[0..7]PB[0..7]

RESET

XTAL[1..2]

CPU

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The ATtiny261/461/861 provides the following featur es: 2/4/8K byte of In-System Programmable

Flash, 128/256/5 12 bytes EEPROM, 128/256/512 bytes SRAM, 16 general purp ose I/O lines, 32

general purpose working registers, an 8-bit Timer/Counter with compare modes, an 8-bit high

speed Timer/Counter, a Universal Serial Interface, Internal and External Interrupts, an 11-chan-

nel, 10-bit ADC, a programmable Watchdog Timer with internal oscillator, and four software

selectable power saving modes. Idle mode stops the CPU while allowing the SRAM,

Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. Power-

down mode saves the register contents, disabling all chip functi ons until the next Interrupt or

Hardware Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC,

to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator

oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined

with low power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny261/461/8 61 AVR is supported by a full suite of program and system development

tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Eval uation

kits.

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3. About

3.1 Resources A comprehensive set of drivers, applica tion note s, data sheets and description s on development

tools are available for download at http://www.atmel.com/avr.

3.2 Code Examples

This documentatio n contains simple co de examples that briefly show how to u se various parts of

the device. These code examp les assume that the part specific header file is included b efore

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handlin g in C is com piler d epend ent. Plea se confir m with th e C com piler d ocume n-

tation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically, this

means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all

AVR devices include an extended I/O map.

3.3 Data Retention

Reliability Qualification results show that the projected da ta retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

3.4 Disclaimer Typical values contained in this data sheet are based on simulations and characterization of

other AVR microcontrollers manufactured on the same process technology.

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4. CPU Core This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.1 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed w ith a sin gle le ve l pip e lining. While one instruc tion is being executed, the next instruc-

tion is pre-fetched from the Program memory. This concept enables instructions to be executed

in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

32 x 8

General

Purpose

Registrers

ALU

Status

and Control

I/O Lines

EEPROM

Data Bus 8-bit

Data

SRAM

Direct Addressing

Indirect Addressing

Interrupt

Unit

Watchdog

Timer

Analog

Comparator

I/O Module 2

I/O Module1

I/O Module n

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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Regi ster File, the op eration is exec uted,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficien t address calculations. One of the these addre ss pointers

can also be used as an address pointer for look up ta bles in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register , described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single r egister o perations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructio ns, ca pable o f

directly address ing the whole addre ss space. Most AVR instruction s have a single 16-bit word

format but 32-bit wide instructions also exist. The actual instruction set varies, as some devices

only implement a part of the instruction set.

During interrupts and subroutine ca lls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and r egular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O fun ctions. The I/O memory can be access ed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

4.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a registe r an d an immed iate ar e executed . Th e ALU opera tio ns are divided

into three main categories – arithmetic, logical, and bit-functions. Some im plementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

4.3 Status Register

The Status Register contai ns information a bout the r esult of th e most r ecently executed ari thme-

tic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Refe rence. This wil l in man y ca ses re move th e nee d for using the

dedicated compare instructions, resulting in faster and more compact code.

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The Status Register is neither autom atically stored when entering an interrupt routine, nor

restored when returning from an interrupt. This must be handled by software.

4.3.1 SREG – AVR Status Register

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a r egister in the Register File by th e

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N V

The S-bit is always an exclusive or betwee n the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

Bit 76543210

0x3F (0x5F) I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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4.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruc tion set. In order t o achieve

the required performance and flexibility, the following input/output schemes are supported by the

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 below shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organizati on provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.4.1 The X-register, Y-register, and Z-register

The registers R2 6:R31 have some added functions to their general pur pose usage. Th ese regis-

ters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3.

Figure 4-3. The X-, Y-, and Z-registers

7 0 Addr.

R0 0x00

R1 0x01

R2 0x02

…

R13 0x0D

General R14 0x0E

Purpose R15 0x0F

Working R16 0x10

Registers R17 0x11

…

R26 0x1A X-register Low Byte

R27 0x1B X-register High Byte

R28 0x1C Y-register Low Byte

R29 0x1D Y-register High Byte

R30 0x1E Z-register Low Byte

R31 0x1F Z-register High Byte

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

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In different addressing modes these address registers function as automatic increment and

automatic decrement (see the instruction set reference for details).

4.5 Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Sta ck is impl emented as gr owing from hig her memor y loca-

tions to lower memory locations. This implies that a Stack PUSH command decr ease s th e Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. T he Stack Pointer must be set to

point above 0x60. The Stack Pointer is decrement ed by one when data is push ed onto the Stack

with the PUSH instruction, and it is decremented by two when the return addre ss is p ushed on to

the Stack with subroutine call or interrupt. The Stack Pointer is incr emented by one when data is

popped from the Stack with the POP instruction, and it is incremente d by two when data is

popped from the Stack with retur n from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present

4.5.1 SPH and SPL — Stack Pointer Regist e r

4.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clkCPU, directly generated fro m the selected clock source for the

chip. No internal clock division is used.

Figure 4- 4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

Bit 1514131211109 8

0x3E (0x5E) SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND RAMEND

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Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

Figure 4-5 shows the internal timi ng con cept for the Reg ister File. In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 4-5. Single Cycle ALU Operation

4.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memo ry space. All interrupts are

assigned individual enable bits which must be writte n logic one togeth er with the Global Inter rupt

Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset a nd

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 50. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

When an interrupt occurs, the Glob al Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is au tomatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is v ect or ed t o th e actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears th e corresponding

Interrupt Flag. Interrupt Flag s can also be cleared by writing a logic one to the flag bit position(s)

clk

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

T1 T2 T3 T4

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

T1 T2 T3 T4

clkCPU

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to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. The se

interrupts do not necessarily have Interrupt Flags. If the interrup t condition disappears be fore the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is serve d.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupt s during the

timed EEPROM write sequence.

Note: See “Code Examples” on page 6 .

When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in the following examples.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending interrupt(s)

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Note: See “Code Examples” on page 6 .

4.7.1 Interrupt Response T ime

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the Program Vector address for the actual inter rupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased b y four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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5. Memories This section describes the different memorie s in the ATtiny261/461/861. The AVR archite cture

has two main me mory spaces, the Da ta memory and the Pr ogram memory s pace. In addition,

the ATtiny261/461/861 features an EEPROM Memory for data storage. All three memory

spaces are linear and regular.

5.1 In-System Re-programmable Flash Program Memory

The ATtiny261/461/861 contains 2/4/8K byte On-chip In-System Reprogrammable Flash mem-

ory for program storage. Since all AVR instructions are 16 or 32 bits wide, the F lash is orga nized

as 1024/2048/4096 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The

ATtiny261/461/861 Program Counter (PC) is 10/11/12 bits wide, thus capable of addressing the

1024/2048/4096 Program memory locations. “Memory Program ming” on page 170 contains a

detailed description on Flash data serial downloading using the SPI pins.

Constant tables ca n be allocated within the en tire address space of progra m memory (see the

LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 11.

Figure 5-1. Program Memory Map

5.2 SRAM Data Memory

Figure 5-2 on page 16 shows how the ATtiny261/4 61/861 SRAM Memory is organized.

The lower data memory locations address both the Register File, the I/O memory and the inter-

nal data SRAM. The first 32 locations address the Register File, the next 64 locations the

standard I/O memory, and the last 128/256/512 locations address the internal data SRAM.

The five different address ing modes for the Data memory cov er: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mo de reaches 63 addre ss locations from the base address given

by the Y- or Z-register.

0x0000

0x03FF/0x07FF/0x0FFF

Program Memory

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ATtiny261/461/861

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z ar e decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-

nal data SRAM in the ATtiny261/461/8 61 are all accessib le thro ugh all these addressing mo des.

The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memor y Map

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clkCPU cycles as illustrated in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

5.3 EEPROM Data Memo ry

The ATtiny261/461/861 contains 128/256/512 bytes of data EEPROM memory. It is organized

as a separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. Th e access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Re gisters, the EEPROM

Data Register, and the EEPROM Control Register. For a detailed description of Serial data

downloading to the EEPROM, see “Electrical Characteristics” on page 187.

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0000 - 0x001F

0x0020 - 0x005F

0x0DF/0x15F/0x25F

0x0060

Data Memory

clk

Data

Address Address valid

T1 T2 T3

Compute Address

Read Write

CPU

Memory Access Instruction Next Instruction

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ATtiny261/461/861

5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1 on page 22. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-

tered power supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the

device for some period of time to run at a voltage lower than specified as minimum for the clock

frequency used. See “Preventing EEPROM Co rruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to “Atomic Byte Programming” on pa ge 17 and “Split Byte Programming” on page 17 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2 Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPRO M, the

user must write the address into the EEARL Register and data into EEDR Register. If the

EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the

erase/write operation. Both the erase and write cycle are done in one operation and the total

programming time is given in Table 5-1 on page 22. The EEPE bit remains set until the erase

and write operations are completed. While the device is busy with progra mming, it is not possi-

ble to do any other EEPROM operations.

5.3.3 Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possib le to do the erase operations when th e system allows doing time-critical

operations (typically after Power-up).

5.3.4 Erase To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b0 1, writing the

EEPE within four cycles after EEMP E is written will trigger the erase operation only (program-

ming time is given in Table 5-1 on page 22). The EEPE bit remains set until the erase operation

completes. While the device is busy programming, it is not possible to do any other EEPROM

operations.

5.3.5 Write To write a location, the user must write the address into EEAR and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 5-1 on page 22). The EEPE bit

remains set until the write operation completes . If the loc ation to be written has not been erased

before write, the data that is stored must be considered as lost. While the device is bu sy with

programming, it is not possible to do any other EEPROM operations.

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ATtiny261/461/861

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator f re-

quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 32.

5.3.6 Program Examples

The following code exam ples sho w one asse mbly and one C function for erase, write, or atomic

write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling

interrupts globally) so that no interrupts will occur during execution of these functions.

Note: See “Code Examples” on page 6 .

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r19) to data register

out EEDR, r19

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0);

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Note: See “Code Examples” on page 6 .

5.3.7 Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPRO M to operate properly. These issues a re the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data co rrup tio n ca n b e caused by two situation s wh en th e vo ltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to opera te correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enab ling the intern al Brown-out De tector (BOD). If the detection level of the internal

BOD does not match the needed detectio n level, an e xternal low VCC reset protection circuit can

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

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ATtiny261/461/861

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the po wer supply voltage is sufficient.

5.4 I/O Memory The I/O space definition of the ATtiny261/461/861 is shown in “Register Summary” on page 223.

All ATtiny261/461/861 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed using the LD/LDS/LDD and ST/STS/STD instructions, enabling data transfer between

the 32 general purpose working registers and the I/O space. I/O Registers within the address

range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these regis-

ters, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the instruction set section for more details. When using the I/O specific commands IN and OUT,

the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space

using LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, the CBI and

SBI instructions will only operate on the specified bit, and can therefore be used on registers

containing such Status Flags. The CBI and SBI instructions work on registers in the address

range 0x00 to 0x1F, only.

The I/O and Periphera ls Control Registers are explained in later sections.

5.4.1 General Purpose I/O Registers

The ATtiny261/461/861 conta ins three General Purpose I/O Registers. These registers can be

used for st oring a ny info rmation , and they ar e particularly useful for storing global variables and

Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly

bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.5 Register Description

5.5.1 EEARH – EEPROM Address Register

• Bits 7:1 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 0 – EEAR8: EEPROM Address

This is the most significant EEPROM address bit of ATtiny861. In devices with less EEPROM,

i.e. ATtiny261/ATtiny461, this bit is reserved and will always read zero. The initial value of the

EEPROM Address Register (EEAR) is undefined and a proper value must therefore be written

before the EEPROM is accessed.

Bit 76543210

0x1F (0x3F) –––––––EEAR8EEARH

Read/Write RRRRRRRR/W

Initial Value 0 0 0 0 0 0 0 X/0

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5.5.2 EEARL – EEPROM Address Register

• Bit 7 – EEAR7: EEPROM Address

This is the most significant EEPROM address bit of ATtiny461. In devices with less EEPROM,

i.e. ATtiny261, this bit is reserved and will always read zero. The initial value of the EEPROM

Address Register (EEAR) is undefined and a proper value must therefore be written before the

EEPROM is accessed.

• Bits 6:0 – EEAR6:0: EEPROM Address

These are the (low) bits of the EEPROM Address Register. The EEPROM data bytes are

addressed linearly in the range 0...128/256/512. The initial value of EEAR is undefined and a

proper value must be therefore be written before the EEPROM may be accessed.

5.5.3 EEDR – EEPROM Data Register

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.5.4 EECR – EEPROM Control Register

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny261/461/861. For compati-

bility with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny261/461/861 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be

triggered when writing EEPE. It is possible to program data in one atomic ope ration (erase the

Bit 76543210

0x1E (0x3E) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value X/0 X X X X X X X

Bit 76543210

0x1D (0x3D) EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1C (0x3C) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial Value 0 0 X X 0 0 X 0

22 2588F–AVR–06/2013

ATtiny261/461/861

old value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 5-1.

When EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be

reset to 0b00 unless the EEPROM is busy programming.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-

rupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM a t the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.

When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.

The EEMPE bit must be written to one b efore a logical one is written to EEPE, otherwise no

EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared

by hardware. When EEPE has been set, the CPU is halted for two cycles before the next

instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-

rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed. The user should poll the EEPE bit before starting the read opera-

tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change

the EEAR Register.

5.5.5 GPIOR2 – General Purpo se I/O Regi st er 2

Table 5-1. EEPROM Mode Bits

EEPM1 EEPM0 Programming

Time Operation

0 0 3.4 ms Erase and Write in one operation (Atomic Operation)

0 1 1.8 ms Erase Only

1 0 1.8 ms Write Only

1 1 – Reserved for future use

Bit 76543210

0x0C (0x2C) MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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5.5.6 GPIOR1 – General Purpo se I/O Regi st er 1

5.5.7 GPIOR0 – General Purpo se I/O Regi st er 0

Bit 76543210

0x0B (0x2B) MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x0A (0x2A) MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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ATtiny261/461/861

6. Clock SystemFigure 6-1 presents the principal clock systems and their distribution in ATtiny261/461/861. All of

the clocks need not be active at a given time. In order to reduce power consumption, the clocks

to modules not being used can be ha lted by using differen t sle ep modes, as describe d in “Power

Management and Sleep Modes” on page 36.

Figure 6-1. Clock Distribution

6.1 Clock Subsystems

The clock subsystems are detailed in the sections below.

6.1.1 CPU Clock – clkCPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2 I/O Clock – clkI/O

The I/O clock is used by the majority o f the I/O modules, like T imer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

General I/O

Modules CPU Core RAM

clkI/O AVR Clock

Control Unit

clkCPU

Flash and

EEPROM

clkFLASH

Source clock

Watchdog Timer

Watchdog

Oscillator

Reset Logic

Clock

Multiplexer

Watchdog clock

Calibrated RC

Oscillator

Calibrated RC

Oscillator

ADC

clkADC

Crystal

Oscillator

Low-Frequency

Crystal Oscillator

System Clock

Prescaler

PLL

Oscillator

clkPCK

General I/O

Modules

External Clock

clkPLL

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6.1.3 Flash Clock – clkFLASH

The Flash clock controls oper ation of the Fl ash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

6.1.4 ADC Clock – clkADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

6.1.5 Fast Periphe ral Clo c k – clkPCK

Selected peripherals can be clocked at a frequency higher than the CPU core. The fast periph-

eral clock is generated by an on-chip PLL circuit.

6.1.6 PLL System Clock – clkADC

The PLL can also be used to generate a system clock. The clock signal can be prescaled to

avoid overclocking th e CPU.

6.2 Clock SourcesThe device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the se lected so urce is input to the AVR clock g enera to r, an d r oute d to the

appropriate modules.

Note: 1. For all fuses “1” means unprogrammed and “0” means programmed.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down or Power-save, the selected clock source is used to time the start-

up, ensuring stable oscillator operation before instruction execution starts. When the CPU starts

from reset, there is an additional delay allowing the power to reach a stable level before com-

Table 6-1. Device Clocking Options Select(1) vs. PB4 and PB5 Functionality

Device Clocking Option CKSEL3:0 PB4 PB5

External Clock (see page 26) 0000 XTAL1 I/O

High-Frequency PLL Clock (see page 26) 0001 I/O I/O

Calibrated Internal 8 MHz Oscillator (see page 28) 0010 I/O I/O

Internal 128 kHz Oscillator (see page 29) 0011 I/O I/O

Low-Frequency Crystal Oscillator (see page 29) 01xx XTAL1 XTAL2

Crystal Oscillator / Ceramic Resonator

0.4...0.9 MHz (see page 30)1000

1001 XTAL1 XTAL2

Crystal Oscillator / Ceramic Resonator

0.9...3.0 MHz (see page 30)1010

1011 XTAL1 XTAL2

Crystal Oscillator / Ceramic Resonator

3...8 MHz (see page 30)1100

1101 XTAL1 XTAL2

Crystal Oscillator / Ceramic Resonator

8...20 MHz (see pag e 30)1110

1111 XTAL1 XTAL2

26 2588F–AVR–06/2013

ATtiny261/461/861

mencing normal operation. The watchdog oscillator is used for timing this real-time part of the

start-up time. The number of WD oscillator cycles used for each time-out is shown in Table 6-2.

6.2.1 External ClockTo dr ive the device from a n exter nal cloc k source, CLKI should be driven as shown in Figure 6-

2. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

Figure 6-2. External Clock Drive Configuration

When this clock source is selected, start-up times are determi ned by the SUT Fuses as shown in

Table 6-3.

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the syste m clock presc aler c an be used to imp leme nt ru n-tim e chang es of the in tern al

clock frequency. See “System Clock Prescaler” on page 31 for details.

6.2.2 High-Frequency PLL Clock

The internal PLL generates a clock signal with a frequency eight times higher than the source

input. The PLL uses the output of the internal 8 MHz oscillator as source and the default setting

generates a fast peripheral clock signal of 64 MHz.

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out Number of Cycles

4 ms 512

64 ms 8K (8,192)

Table 6-3. Start-up Times for the External Clock Selection

SUT1:0 Start-up Time from Power-

down and Power-save Additional Delay from

Reset Recommended Usage

00 6 CK 14CK BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10 6 CK 14CK + 64 ms Slowly rising power

11 Reserved

EXTERNAL

CLOCK

SIGNAL

CLKI

GND

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ATtiny261/461/861

The fast peripheral clock, clkPCK, can be selected as the clock source for Timer/Counter1 and a

prescaled version of the PLL output, clkPLL, can be selected as sys tem clock . See Figure 6-3 for

a detailed illustration on the PLL clock system.

Figure 6-3. PCK Clocking System

The internal PLL is en abled when CKSEL fu se bits are pro grammed to ‘0001 ’and the PLLE bit of

PLLCSR is set. The internal oscillator and the PLL are switched off in power down and stand-by

sleep modes.

When the LSM bit of PLLCSR is set, the PLL switches from using the output of the internal 8

MHz oscillator to using the output divided by two. The frequency of the fast peripheral clock is

effectively divided by two , resu lting in a clock fre quency of 32 MHz. The LSM bit can no t be set if

PLLCLK is used as a system clock.

Since the PLL is locked to the output of the internal 8 MHz oscillator, adjusting the oscillator fre-

quency via the OSCCAL register a lso changes the frequency of the fast periphe ral clock. It is

possible to adjust the frequency of the internal oscillator to well above 8 MHz but the fast periph-

eral clock will saturate and remain oscillating at about 85 MHz. In this case the PLL is no longer

locked to the internal oscillator clock signal. Therefore, in order to keep the PLL in the correct

operating range, it is recommended to program the OSCCAL registers such that the oscillator

frequency does not exceed 8 MHz.

The PLOCK bit in PLLCSR is set when PLL is locked.

Programming CKSEL fuse bits to ‘0001’, the PLL output divided by four will be used as a system

clock, as shown in Table 6-4.

Table 6-4. PLLCK Operating Modes

CKSEL3:0 Nominal Frequency

0001 16 MHz

1/2

8 MHz

LSM

8 MHz

OSCILLATOR PLL

CKSEL3:0PLLEOSCCAL

4 MHz

1/4

LOCK

DETECTOR

PRESCALER

CLKPS3:0

clkPLL

PLOCK

clkPCK

OSCILLATORS

XTAL1

XTAL2

64 / 32 MHz

8 MHz

16 MHz

28 2588F–AVR–06/2013

ATtiny261/461/861

When the PLL output is selected as clock source, the start-up times are determined by SUT fuse

bits as shown in Table 6-5.

6.2.3 Calibrated Internal 8 MHz Oscillator

By default, the Internal Oscillator provides an approximately 8 MHz clock signal. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See Table

19-2 on page 189 and “Internal Oscillator Speed” on page 216 for more details. The device is

shipped with the CKDIV8 Fuse program med. See “System Clock Prescaler” on page 31 for

more details.

This clock may be sele ct ed as the syste m cl oc k by p rogr am m in g th e CKS E L Fus es a s sh own in

Table 6-6. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed ca libr ation value in to the OSCCAL Re gister a nd the reby automatica lly cal-

ibrates the RC Oscillator. The accurac y of this calibration is shown as Factory calibration in

Table 19-2 on page 189.

Notes: 1. The device is shipped with this option selected.

2. If the oscillator frequency exceeds the specification of the device (depends on VCC), the

CKDIV8 Fuse can be programmed to divide the internal frequency by 8.

When this oscillator is selected, start-up times are determined by SUT fuses as shown in Table

6-7.

Note: 1. If the RSTDISBL fuse is programmed, this st art -up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

2. The device is shipped with this option selected.

Table 6-5. Start-up Times for the PLLCK

SUT1:0 Start-up Time from

Power Down Additional Delay from

Power-On-Reset (VCC = 5.0V) Recommended

usage

00 14CK + 1K (1024) + 4 ms 4 ms BOD enabled

01 14CK + 16K (16384) + 4 ms 4 ms Fast rising power

10 14CK + 1K (1024) + 64 ms 4 ms Slowly rising power

11 14CK + 16K (16384) + 64 ms 4 ms Slowly rising power

Table 6-6. Internal Calibrated RC Oscillator Operating Modes

CKSEL3:0 Nominal Frequency

0010 (1) 8.0 MHz (2)

Table 6-7. Start-up Times for the Internal Calibrated RC Oscillator Clock Selection

SUT1:0 Start-up Time

from Power-down Additional Delay from

Reset (VCC = 5.0V) Recommended

Usage

00 6 CK 14CK(1) BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10(2) 6 CK 14CK + 64 ms Slowly rising power

11 Reserved

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It is possible to reach a higher accuracy than factory calibration by changing the OSCCAL regis-

ter from software. See “OSCCAL – Oscillator Calibration Register” on page 32. The accuracy of

this calibration is shown as User calibration in Table 19-2 on page 189.

When this oscillator is used as devi ce clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see section “Calibration Byte” on page 173.

6.2.4 Internal 128 kHz Oscillator

The 128 kHz internal oscillator is a low power oscillator providing a clock of 128 kHz. The fre-

quency depends on supply voltage, temperature and batch variations. This clock may be select

as the system clock by programming the CKSEL Fuses to “0011”.

When this clock source is selected, start-up times are determi ned by the SUT Fuses as shown in

Table 6-8.

Note: 1. If the RSTDISBL fuse is programmed, this st art -up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

6.2.5 Low-Frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency cryst al

oscillator must be selected by setting CKSEL fuses to ‘0100’. The crystal should be connected

as shown in Figure 6-4. To find suitable capacitors please consult the manufacturer’s datasheet.

When this oscillator is selected, start-up times are determined by t he SUT fuses as shown in

Table 6-9.

Notes: 1. These options should be used only if frequency stability at start-up is not important.

The Low-frequency Crystal Oscillator provides an internal load capacitance, see Table 6-10 at

each TOSC pin.

Table 6-8. Start-up Times for the 128 kHz Internal Oscillator

SUT1:0 Start-up Time from Power-

down and Power-save Additional Delay fro m

Reset Recommended Usage

00 6 CK 14CK (1) BOD enabled

01 6 CK 14CK + 4 ms Fast rising power

10 6 CK 14CK + 64 ms Slowly rising power

11 Reserved

Table 6-9. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

SUT1:0 Start-up Time

from Power Down Additional Delay

from Reset Recommended usage

00 1K (1024) CK(1) 4 ms Fast rising power or BOD enabled

01 1K (1024) CK(1) 64 ms Slowly rising power

10 32K (32768) CK 64 ms Stable frequency at start-up

11 Reserved

Table 6-10. Capacitance for Low-Frequency Crystal Oscillator

Device 32 kHz Osc. Type Cap (Xtal1/Tosc1) Cap (Xtal2/Tosc2)

ATtiny261/461/861 System Osc. 16 pF 6 pF

30 2588F–AVR–06/2013

ATtiny261/461/861

6.2.6 Crystal Oscillator / Ceramic Resonator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifie r which can be con-

figured for use as an O n-chip Oscillator, as shown in Figure 6-4. Either a quartz crystal or a

ceramic resonator may be used.

Figure 6-4. Crystal Oscillator Connections

C1 and C2 should always be equal for both crystals and resonators. T he optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Ta ble 6- 11. For ceramic resonators, the capacitor values given by

the manufacturer should be used.

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by fuses CKSEL3:1 as shown in Table 6-11.

The CKSEL0 Fuse together with the SUT1:0 Fuses select the start-up times as show n in Table

6-12.

Table 6-11. Crystal Oscillator Operating Modes

CKSEL3:1 Frequency Range (MHz) Recommended C1 and C2 Value (pF)

100(1) 0.4 - 0.9 –

101 0.9 - 3.0 12 - 22

110 3.0 - 8.0 12 - 22

111 8.0 - 12 - 22

Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection

CKSEL0 SUT1:0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

0 00 258 CK(1) 14CK + 4 ms Ceramic resonator,

fast rising power

0 01 258 CK(1) 14CK + 64 ms Ceramic resonator,

slowly rising power

0 10 1K (1024) CK(2) 14CK Ceramic resonator,

BOD enabled

XTAL2

XTAL1

GND

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Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application . Th ese

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

6.2.7 Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is therefore th e Internal Oscillator running at 8 MHz with longest sta rt-up

time and an initial system clock prescaling of 8. This default setting ensures that all users can

make thei r desired clock source setting using an In-System or High-voltage Programmer.

For low-voltage devices (ATtiny261V/461V/861V) it should be noted that unprogramming the

CKDIV8 fuse may result in overclocking. At low voltages (below 2.7V) the devices are rated for

maximum 4 MHz operation (see Sectio n 19.3 on page 18 8), but r outing the clock sign al from the

internal oscillator directly to the system clock line will run the device at 8 MHz.

6.3 System Clock Prescaler

The ATtiny261/461/861 system clock can be divided by setting the “CLKPR – Clock Prescale

requirement for processing power is low. This can be used with all clock source options, and it

will affect the clock frequency of the CP U and all synchronous peripherals. clkI/O, clkADC, clkCPU,

and clkFLASH are divided by a factor as sh ow n in Table 6-13 on page 34.

6.3.1 Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

0 11 1K (1024)CK(2) 14CK + 4 ms Ceramic resonator,

fast rising power

1 00 1K (1024)CK(2) 14 CK + 64 ms Ceramic resonator,

slowly rising power

1 01 16K (16384) CK 14CK Crystal Oscillator,

BOD enabled

1 10 16K (16384) CK 14CK + 4 ms Crystal Oscillator,

fast rising power

1 11 16K (16384) CK 14CK + 64 ms Crystal Oscillator,

slowly rising power

Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

CKSEL0 SUT1:0

Start-up Time from

Power-down and

Power-save

Additional Delay

from Reset

(VCC = 5.0V) Recommended Usage

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From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, two active clock edges are produced. Here, T1 is

the previous clock period, and T2 is the period corresponding to the new prescaler setting.

6.4 Clock Output Buffer

The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To

enable the output, the CKOUT Fuse has to be progr ammed. This mode is suita ble when the chip

clock is used to drive other circuits on the system. Note that the clock will not be output during

reset and the normal operation of I/O pin will be overridden when the fuse is programmed. Inter-

nal RC Oscillator, WDT Oscillator, PLL, and exter nal clock (CLKI) can be selected whe n the

clock is output on CLKO. Crystal oscillators (XTAL1, XTAL2) can not be used for clock output on

CLKO. If the System Clock Prescaler is used, it is the divided system cloc k tha t is out pu t.

6.5 Register Description

6.5.1 OSCCAL – Oscillator Calibration Register

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration v alue is

automatically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 19-2 on page 189. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 19-

2 on page 189. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write acc esses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives th e

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6:0 bits are used to tu ne the frequency within the selected range. A setting of 0x00

gives the lowest frequ ency in that range, a nd a setting of 0x7F gives the highest frequency in the

range.

6.5.2 CLKPR – Clock Prescale Register

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is

Bit 76543210

0x31 (0x51) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value Device Specific Calibration Value

Bit 76543210

0x28 (0x48) CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

Read/Write R/W R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

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cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

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• Bits 6:4 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divid er divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-13.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing presca ler setting to make sure the write procedure is

not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CK DIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of eight at start up. This featu re should be used if the selected

clock source has a higher frequency than the maximum frequency of the device at the present

operating conditions. Note that any value can be written to the CLKPS bits regardless of the

CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selcted clock source has a higher frequency than the maximum frequency of the

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse

programmed.

Table 6-13. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1

0001 2

0010 4

0011 8

0100 16

0101 32

0110 64

0111 128

1000 256

1001 Reserved

1010 Reserved

1011 Reserved

1100 Reserved

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1101 Reserved

1110 Reserved

1111 Reserved

Table 6-13. Clock Prescaler Select (Continued)

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

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7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an

ideal choise for low power applications. In addition, sleep modes enable the application to shut

down unused modules in the M CU, thereby saving power. The AVR provides various sleep

modes allowing the user to tailor the power consumption to the applica tion’s requirements.

7.1 Sleep Modes Figure 6-1 on page 24 presents the different clock systems and their distribution in

ATtiny261/461/861. T he figure is helpful in selecting an appropriate sleep m ode. Table 7-1

shows the different sleep modes and their wake up sources.

Note: 1. For INT0 and INT1, only level interrupt.

2. When PLL selected as system clock.

To enter any of the sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1:0 bits in the MCUCR Register select which sleep

mode (Idle, ADC Noise Reduction, Powe r-down, or Standby) will be activated by the SLEEP

instruction. See Table 7- 2 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes u p fr om sleep. If a r eset occurs d uring sleep mod e,

the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up the changed level must be held for

some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See

“External Interrupts” on page 51 for details.

7.1.1 Idle Mode When bits SM1:0 are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, Timer/Counter, Watchdog, and the

interrupt system to continue operating. This sleep mode basically ha lts clkCPU and clkFLASH, while

allowing the other clocks to run.

Table 7-1. Active Clock Domains and Wake-up Sources in Different Sleep Modes

Sleep Mode

Active Clock Domains Osc. Wake-up Sources

clkCPU

clkFLASH

clkIO

clkADC

clkPCK

clkPLL

Main Clock

Source Enabled

INT0, INT1 and

Pin Change

SPM/EEPROM

Ready Interrupt

ADC

Interrupt

USI

Interrupt

Other

I/O

Watchdog

Interrupt

Idle XXXX

(2) X XXXXXX

ADC Noise Reduct. X X(2) XX

(1) XXX X

Power-down X(1) XX

Standby X(1) XX

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Idle mode enables the MCU to wake up from external triggered inter rupts as well as internal

ones like the Timer Over flow. If wake-up from th e Analog Compa rator interrupt is not requ ired,

the Analog Com parator can be powe red down b y setting the ACD bit in the Analog Comparator

Control and Status Register – ACSR. This will reduce po wer consumption in Idle m ode. If the

ADC is enabled, a conversion starts automatically when this mode is entered.

7.1.2 ADC Noise Reduction Mode

When the SM1:0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode h alts clkI/O, clk CPU, and clkFLASH,

while allowing the other clocks to run.

This mode improves the noise environment for the ADC, enabling higher resolution measure-

ments. If the ADC is enabled, a conversion star ts automatically when this mode is entered. Apart

form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a

Brown-out Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin

change interrupt can wake up the MCU from ADC Noise Reduction mode.

7.1.3 Power-Down Mode

When the SM1:0 bits are written to 10 , the SLEEP instruction makes the MCU ente r Power-

down mode. In this mode, the Oscillator is stopped, while the external interrupts, and the Watch-

dog continue oper ating (if enabled). Only an External Reset, a Watchd og Reset, a Brown-out

Reset, an external level interrupt on INT0, or a pin change interrupt can wake up the MCU. This

sleep mode halts all generated clocks, allowing opera tion of asynchronous modules, only.

7.1.4 Standby Mode When the SM1:0 bits are written to 11 and an external crystal/resonator clock option is selected,

the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-

down with the exception that the Oscillator is kept running. From Standby mode, the device

wakes up in six clock cycles.

7.2 Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 39, pro-

vides a method to stop the clock to individual peripherals to reduce power consumption. The

current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, p uts th e mo dule in the sa me state a s befor e shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current

of I/O modules” on page 197 for examples. In all other sleep modes, the clock is already

stopped.

7.3 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possi ble of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

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ATtiny261/461/861

7.3.1 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is a utom atically disab led. H ow ever , if th e Ana log C omp arat or is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. Refer to “AC – Analog Comparator” on page 137 for details on how

to configure th e Ana log C om p ar at or .

7.3.2 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “ADC – Analog to Digital Converter” on

page 142 for details on ADC operation.

7.3.3 Brown-out Detector

If the Brown-out Detector is not needed in the ap plication, this module should be turned off. If the

Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,

and hence, always consume power. In the deeper sleep modes, this will contribute significantly

to the total current consumption. Refer to “Brown-out Detection” on page 43 for details on how to

configure the Brown-out Detector.

7.3.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modul es are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 44 for details on the start-up time.

7.3.5 W atchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” o n pa ge 44 fo r details o n ho w to configu re the Watchd og Timer.

7.3.6 Port Pins When entering a sleep mode, all port pins should be configured to use minimum po wer. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 59 for details on

which pins are enabled. If the input buffer is enab led and the inpu t sig nal is left floa ting or has an

analog signal level close to VCC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to VCC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR0, DIDR1).

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Refer to “DIDR0 – Digital Input Disable Register 0” on page 162 or “DIDR1 – Digital Input Dis-

able Register 1” on page 162 for details.

7.4 Register Description

7.4.1 MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sle ep mode unless it is the programmer ’s

purpose, it is recommended to write the Sleep Enab le (SE) bit to o ne just before the exec ution of

the SLEEP instruction and to clear it immediately after waking up.

• Bits 4, 3 – SM1:0: Sleep Mode Select Bits 2:0

These bits select between the three available sleep modes as shown in Table 7-2.

• Bit 2 – Res: Reserved Bit

This bit is reserved and will always read zero.

7.4.2 PRR – Power Reduction Register

The Power Reduction Register provides a method to reduce power consumption by allowing

peripheral clock signals to be disabled.

• Bits 7, 6, 5, 4 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 3 – PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

Bit 76543210

0x35 (0x55) –PUD SE SM1 SM0 — ISC01 ISC00 MCUCR

Read/Write R R/W R/W R/W R/W R R/W R/W

Initial Value00000000

Table 7-2. Sleep Mode Select

SM1 SM0 Sleep Mode

00Idle

0 1 ADC Noise Reduction

1 0 Power-down

1 1 Standby

Bit 76543 2 10

0x36 (0x56) – - - - PRTIM1 PRTIM0 PRUSI PRADC PRR

Read/WriteRRRRR/WR/WR/WR/W

Initial Value 0 0 0 0 0 0 0 0

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• Bit 2 – PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 1 – PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When

waking up the USI again, the USI should be r e initialized to ensure proper operation.

• Bit 0 – PRADC: Power Reduction ADC

Writing a logic one to this bit shuts do wn the ADC. The ADC mu st be disabled b efore shut down.

Also analog comparator needs this clock.

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8. System Control and Reset

8.0.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the

reset circuitry ar e giv en in Table 19-4 on page 190.

Figure 8-1. Reset Logic

The I/O ports of the AVR are im mediately reset to their initial state wh en a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 25.

MCU Status

Brown-out

Reset Circuit

BODLEVEL [1..0]

Delay Counters

CKSEL[1:0]

TIMEOUT

WDRF

BORF

EXTRF

PORF

DATA BU S

Clock

Generator

SPIKE

FILTER

Pull-up Resistor

Watchdog

Oscillator

SUT

[

1:0

]

Power-on Reset

Circuit

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ATtiny261/461/861

8.1 Reset SourcesThe ATtiny261/461/861 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (VPOT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Br own-out

Reset threshold (VBOT) and the Brown-out Detector is enabled.

8.1.1 Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in “System and Reset Characteristics” on page 190. The POR is activated whenever

VCC is below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

well as to detect a failure in supply voltage.

A Power-on Reset (POR) cir cuit ensures that the device is reset from Power-on. Reac hing the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after VCC rise. The RESET signal is activated again, without any delay,

when VCC decreases below the detection level.

Figure 8-2. MCU Start-up, RESET Tied to VCC

Figure 8-3. MCU Start-up, RESET Extended Externally

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

RESET

TIME-OUT

INTERNAL

RESET

TOUT

POT

RST

VCC

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8.1.2 External ResetAn External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer

than the minimum pulse width (see “System and Re se t Char acter istics” o n p age 190) will gener-

ate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a

reset. When the applied signal reaches the Reset Threshold Voltage – VRST – on its positive

edge, the delay counter starts the MCU after the Time-out period – tTOUT – has expired.

Figure 8-4. External Reset During Operation

8.1.3 Brown-out Detection

ATtiny261/461/861 has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC

level during operation by comparing it to a fixed trigger level. T he trigger level for the BOD can

be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the d etection level should be interpreted as VBOT+ =

VBOT + VHYST/2 and VBOT- = VBOT - VHYST/2.

When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT- in Figure

8-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger level

(VBOT+ in Figure 8-5), the delay counter starts the MCU after the Time-out period tTOUT has

expired.

The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-

ger than tBOD given in “System and Reset Characteristics” on page 190.

Figure 8-5. Brown-out Reset During Operation

VCC

RESET

TIME-OUT

INTERNAL

RESET

VBOT- VBOT+

tTOUT

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8.1.4 W atchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to

“Watchdo g T ime r” on pa g e 44 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

8.2 Internal Voltage Reference

ATtiny261/461/861 features an inte rnal bandgap re ference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC. The bandgap

voltage varies with supply voltage and temperature, as can be seen in Figure 20- 36 on page

216.

8.2.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time tha t may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 190. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse bits).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.3 Watchdog Timer

The Watchdog Timer is clocked from an on-chip oscillator, which runs at 128 kHz. By controlling

the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

8-3 on page 49. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a device reset occurs. Ten different

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the ATtiny261/461/861 resets and executes from the Reset

Vector. For timing details on the Watchdog Reset, refer to Table 8-3 on page 49.

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The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can

be very helpful when using the Watchdog to wake-up from Power-down.

To prevent uninte ntional disabling of the Wa tchdog or unintentional ch ange of time-out period ,

two different safety levels are selected by the fuse WDTON as shown in Table 8-1 Refer to

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for

details.

Figure 8-7. Watchdog Timer

8.3.1 Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changin g configura tion differ s slightly between the two safety levels. Separate

procedures are described for each level.

8.3.1.1 Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to one without any restriction. A timed sequence is needed when disabling an enabled Watch-

dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits

as desired, but with the WDCE bit cleared.

8.3.1.2 Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

Table 8-1. WDT Configuration as a Function of the Fuse Settings of WDTON

WDTON Safety

Level WDT Initial

State How to Disable the

WDT How to Change Time-

out

Unprogrammed 1 Disabled Timed sequence No limitations

Programmed 2 Enabled Always enabled Timed sequence

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

MCU RESET

WATCHDOG

PRESCALER

128 kHz

OSCILLATOR

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDP3

WDE

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1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same ope ration, write the WDP bi t s as desir ed,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

8.3.2 Code Examples

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrup ts are controlled (e.g., by disabling interrupts glob ally) so th at

no interrupts will occur during execution of these functions.

Note: See “Code Examples” on page 6 .

Assembly Code Example

WDT_off:

wdr

; Clear WDRF in MCUSR

ldi r16, (0<<WDRF)

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog Reset

in r16, WDTCSR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCSR, r16

ret

C Code Example

void WDT_off(void)

{

_WDR();

/* Clear WDRF in MCUSR */

MCUSR = 0x00

/* Write logical one to WDCE and WDE */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

}

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8.4 Register Description

8.4.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

• Bits 7:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny261/461/861 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read an d then reset

the MCUSR as ear ly as possible in the pr ogram. If the regi ster is cleared before an other reset

occurs, the source of the reset can be fo und by examining the Reset Flags.

8.4.2 WDTCR – Watchdog Timer Control Register

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Altern atively, WDIF is clear ed by writing a lo gic one to the flag. Whe n the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the

Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed

instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful

for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,

Bit 76543210

0x34 (0x54) – – – – WDRF BORF EXTRF PORF MCUSR

Read/Write R R R R R/W R/W R/W R/W

Initial Value 0 0 0 0 See Bit Description

Bit 76543210

0x21 (0x41) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCR

Read/WriteR/WR/WR/WR/WR/WR/WR/WR/W

Initial Value 0 0 0 0 X 0 0 0

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ATtiny261/461/861

the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after

each interrupt.

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic z ero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable pr ocedure. This bit must also be set when

changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 45.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is di sabled. WDE can on ly be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See “Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 45.

In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Regis-

ter” on page 47 for de scription of WDRF. This means tha t WDE is always set when WDRF is set.

To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure

described above. This feature ensures multiple resets during conditions causing failure, and a

safe start-up after the failure.

Note: If the watchdog timer is not going to be used in the application, it is important to go through a

watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally

enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which

in turn will lead to a new watchdog reset. To avoi d this situation, the application software should

always clear the WDRF flag and the WDE control bit in the initialization routine.

Table 8-2. Watchdog Timer Configuration

WDE WDIE Watchdog Timer State Action on Time-out

0 0 Stopped None

0 1 Running Interrupt

1 0 Running Reset

1 1 Running Interrupt

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• Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 8-3.

Notes: 1. If selected, one of the valid settings below 0b1010 will be used .

Table 8-3. Watchdog Timer Prescale Select

WDP3 WDP2 WDP1 WDP0 Number of WDT Oscillator

Cycles Typical Time-out at

VCC = 5.0V

0 0 0 0 2K (2048) cycles 16 ms

0 0 0 1 4K (4096) cycles 32 ms

0 0 1 0 8K (8192) cycles 64 ms

0 0 1 1 16K (16384) cycles 0.125 s

0 1 0 0 32K (32764) cycles 0.25 s

0 1 0 1 64K (65536) cycles 0.5 s

0 1 1 0 128K (131072) cycles 1.0 s

0 1 1 1 256K (262144) cycles 2.0 s

1 0 0 0 512K (524288) cycles 4.0 s

1 0 0 1 1024K (1048576) cycles 8.0 s

1010

Reserved(1)

1011

1100

1101

1110

1111

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ATtiny261/461/861

9. Interrupts This section describes the specifics of the interrupt handling as performe d in ATtiny261/461/861.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 12.

9.1 Interrupt Vectors

Interrupt vectors of ATtiny261/461/861 are described in Table 9-1 below.

If the program never e nables an inte rrupt sou rce, the Inter rupt Vector s ar e not used , and r egu lar

program code can be placed at these locations.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in

ATtiny261/461/861 is shown in the program example below.

Address Labels Code Comments

0x0000 rjmp RESET ; Reset Handler

0x0001 rjmp EXT_INT0 ; IRQ0 Handler

0x0002 rjmp PCINT ; PCINT Handler

Table 9-1. Reset and Interrupt Vectors

Vector

No. Program

Address Source Interrupt Definition

1 0x0000 RESET External Pin, Power-on Re set,

Brown-out Reset, Watchdog Reset

2 0x0001 I NT0 External Interrupt Request 0

3 0x0002 PCINT Pin Change Interrupt Request

4 0x0003 TIMER1_COMPA Timer/Counter1 Compare Match A

5 0x0004 TIMER1_COMPB Timer/Counter1 Compare Match B

6 0x0005 TIMER1_OVF Timer/Counter1 Overflow

7 0x0006 TIMER0_OVF Timer/Counter0 Overflow

8 0x0007 USI_START USI Start

9 0x0008 USI_OVF USI Overflow

10 0x0009 EE_RDY EEPROM Ready

11 0x000A ANA_COMP Analog Comparator

12 0x000B ADC ADC Conversion Complete

13 0x000C W DT Watchdog Time-out

14 0x000D INT1 External Interrupt Request 1

15 0x000E TIMER0_COMPA Timer/Counter0 Compare Match A

16 0x000F TIMER0_COMPB Timer/Counter0 Compare Match B

17 0x0010 TIMER0_CAPT Timer/Counter1 Capture Event

18 0x0011 TIMER1_COMPD Timer/Counter1 Compare Match D

19 0x0012 FAULT_PROTECTION Timer/Counter1 Fault Protection

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0x0003 rjmp TIM1_COMPA ; Timer1 CompareA Handler

0x0004 rjmp TIM1_COMPB ; Timer1 CompareB Handler

0x0005 rjmp TIM1_OVF ; Timer1 Overflow Handler

0x0006 rjmp TIM0_OVF ; Timer0 Overflow Handler

0x0007 rjmp USI_START ; USI Start Handler

0x0008 rjmp USI_OVF ; USI Overflow Handler

0x0009 rjmp EE_RDY ; EEPROM Ready Handler

0x000A rjmp ANA_COMP ; Analog Comparator Handler

0x000B rjmp ADC ; ADC Conversion Handler

0x000C rjmp WDT ; WDT Interrupt Handler

0x000D rjmp EXT_INT1 ; IRQ1 Handler

0x000E rjmp TIM0_COMPA ; Timer0 CompareA Handler

0x000F rjmp TIM0_COMPB ; Timer0 CompareB Handler

0x0010 rjmp TIM0_CAPT ; Timer0 Capture Event Handler

0x0011 rjmp TIM1_COMPD ; Timer1 CompareD Handler

0x0012 rjmp FAULT_PROTECTION ; Timer1 Fault Protection

0x0013 RESET: ldi r16, low(RAMEND) ; Main program start

0x0014 ldi r17, high(RAMEND); Tiny861 have also SPH

0x0015 out SPL, r16 ; Set Stack Pointer to top of RAM

0x0016 out SPH, r17 ; Tiny861 have also SPH

0x0017 sei ; Enable interrupts

0x0018 <instr>

... ...

9.2 External Interrupts

The External Interrupts are triggered by the INT0 or INT1 pin or any of the PCINT15:0 pins.

Observe that, if enabled, the interrupts will trigger even if the INT0, INT1 or PCINT15:0 pins are

configured as outputs. This feature provides a way of generating a software interrupt. Pin

change interrupts PCI will trigger if any enabled PCINT15:0 pin toggles. The PCMSK Regis ter

control which pins contribute to the pin cha nge interrupts. Pin change interrupts on PCINT15:0

are detected asynchronously. This implies that these interrupts can be used for waking the part

also from sleep modes other than Idle mode.

The INT0 and INT1 interrupts can be triggered by a falling o r rising edge or a low level. This is

set up as indicated in the specification for the MCU Control Register – MCUCR. When the INT0

interrupt is enabled and is configured as le vel triggered, the interrupt will trigger as long as the

pin is held low. Note that recognition of falling or rising edge interrupts on INT0 or INT1 requires

the presence of an I/O clock, described in “Clock Subsystems” on page 24.

9.2.1 Low Level Interrupt

A low level interrupt on INT0 is detected asynchronously. This mean s that the interrupt source

can be used for waking the part also from sleep modes other than Idle (the I/O clock is halted in

all sleep modes except Idle).

Note that if a level trigger ed interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete t he wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

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ATtiny261/461/861

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in “Clock System” on page 24.

If the low level on the interrupt pin is removed before the device has woken up then program

execution will not be diverted to the interrupt service routine but continue from the instruction fol-

lowing the SLEEP command.

9.3 Register Description

9.3.1 MCUCR – MCU Control Register

The MCU Register contains control bits for interrupt sense control.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 or INT1 if the SREG I-flag and the

corresponding interrupt mask are set. The level and edges on the external INT0 or INT1 pin that

activate the interrupt are defined in Table 9-2. The value on the INT0 or INT1 pin is sampled

before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one

clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-

rupt. If low level interrupt is selected, the low level must be held until the completion of the

currently executing instruction to generate an inter rupt.

9.3.2 GIMSK – General Interrupt Mask Register

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sens e Control0 b its 1/0 (ISC0 1 and ISC00) in the MCU

Control Register (MCUCR) define whether the external inter rupt is activa ted on r ising and/or fall-

ing edge of the INT1 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT1 is configured as an output. The corresponding interrupt of External Interrupt Request 1 is

executed from the INT1 Interrupt Vector.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sens e Control0 b its 1/0 (ISC0 1 and ISC00) in the MCU

Bit 76543210

0x35 (0x55) –PUD SE SM1 SM0 – ISC01 ISC00 MCUCR

Read/Write R R/W R/W R/W R/W R R/W R/W

Initial Value00000000

Table 9-2. Interrupt 0 Sense Control

ISC01 ISC00 Description

0 0 The low level of INT0 or INT1 generates an interrupt request.

0 1 Any logical change on INT0 or INT1 generate s an inte rrupt request.

1 0 The falling edge of INT0 or INT1 generates an interrupt request.

1 1 The rising edge of INT0 or INT1 gen erates an interrupt request.

Bit 76543210

0x3B (0x5B) INT1INT0PCIE1PCIE0––––GIMSK

Read/Write R/W R/W R/W R/w R R R R

Initial Value00000000

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Control Register (MCUCR) define whether the external inter rupt is activa ted on r ising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE1: Pin Change Interrupt Enable

When the PCIE1 bit is set (o ne) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT7:0 or PCINT15:12 pin will

cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed

from the PCI Interrupt Vector. PCINT7:0 and PCINT15:12 pins are enabled individually by the

PCMSK0 and PCMSK1 Register.

• Bit 4 – PCIE0: Pin Change Interrupt Enable

When the PCIE0 bit is set (o ne) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT11:8 pin will cause an interrupt.

The corres ponding in terrup t of Pin Chang e Interr upt Request is executed from the PCI Interrupt

Vector. PCINT11:8 pin s ar e en ab led ind ivid ua lly by th e PCM SK1 Regis te r.

• Bits 3:0 – Res: Reserved Bits

These bits are reserved and will always read as zero.

9.3.3 GIFR – General Interrupt Flag Register

• Bit 7 – INTF1: External Interrupt Flag 1

When an edge or logic change on the INT1 pin trigger s an interrup t request, INT F1 become s set

(one). If the I-bit in SREG and the INT1 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT1 is configured as a level interrupt.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin trigger s an interrup t request, INT F0 become s set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT15 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

• Bits 4:0 – Res: Reserved Bits

These bits are reserved and will always read as zero.

Bit 76543210

0x3A (0x5A) INT1INTF0PCIF–––––GIFR

Read/Write R/W R/W R/W R R R R R

Initial Value00000000

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ATtiny261/461/861

9.3.4 PCMSK0 – Pin Change Mask Register A

• Bits 7:0 – PCINT7:0: Pin Change Enable Mask 7:0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT7:0 is set and the PCIE1 bit in GIMSK is set, pin change interrupt is enabled on the co r-

responding I/O pin. If PCINT7:0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

9.3.5 PCMSK1 – Pin Change Mask Register B

• Bits 7:0 – PCINT15:8: Pin Change Enable Mask 15:8

Each PCINT15:8 bit selects whether pin change interrupt is enabled on the corresponding I/O

pin. If PCINT11:8 is set and the PCIE0 bit in GIMSK is set, pin change interrupt is enabled on

the corresponding I/O pin, and if PCINT15:12 is set and the PCIE1 bit in GIMSK is set, pin

change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is cleared, pin change

interrupt on the corresponding I/O pin is disabled.

Bit 76543210

0x23 (0x43) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/w R/W R/W R/W R/W

Initial Value11001000

Bit 76543210

0x22 (0x42) PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

Read/Write R/W R/W R/W R/w R/W R/W R/W R/W

Initial Value11111111

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10. I/O Ports All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configure d as output) or ena bling/disabling o f pull-up resistors ( if configur ed as

input). Each output buffer has symmetrical drive characteristics with both hig h sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both VCC and Gro und as in dicated in Figure 10-1. See “Electrical Character-

istics” on page 187 for a complete list of par ameters.

Figure 10-1. I/O Pin Equivalent Schematic

All registers and bit r eferences in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the p ort, and a lower case “ n” represents the bit number. Howeve r,

when using the register or bi t defines in a progr am, the precise form must be used. For example,

PORTB3 for bit no. 3 in Po rt B, her e docume nt ed ge nerally a s PORTxn . The physical I/O Regis-

ters and bit locations are listed in “Register Description” on page 69.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data R eg ist er a nd th e Da ta Dir ec tion R eg iste r ar e re ad /write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as G eneral Digital I/O is described in “Ports as General Digital I/O” on page

56. Most port pins are m ultiplexed with alternate func tions for the peripheral featur es on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 60. Refer to the individual module sectio ns for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

CPIN

Logic

RPU

See Figure

"General Digital I/O" for

Details

Pxn

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10.1 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 sho ws a func-

tional description of one I/O-port pin, here gener ically called Pxn.

Figure 10-2. General Digital I/O(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are common to all ports.

10.1.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description” on page 69, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the p in has to

clk

RPx

RRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

RESET

CLR

PORTxn

CLR

DDxn

PINxn

DATA BU S

SLEEP

SLEEP: SLEEP CONTROL

Pxn

I/O

WPx

WRx

WPx: WRITE PINx REGISTER

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be configured as an output p in. The p ort pi ns are tri-stated when reset condition becomes active,

even if no clocks are ru nnin g.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

The pull-up resistor is activated, if the PUExn is written logic one. To switch the pull-up resistor

off, PUExn has to be written logic zero.

10.1.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

10.1.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull- up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b10) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

10.1.4 Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in F igure 10- 2, the PINxn Register bit and the pre ceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduce s a delay. F igure 10-3 shows a timing dia-

gram of the synch ronization when reading an externa lly applied pin value. The maximum and

minimum prop a ga tio n dela ys ar e de no te d tpd,max and tpd,min respectively.

Table 10-1. Port Pin Configurations

DDxn PORTxn PUD

(in MCUCR) I/O Pull-up Comment

0 0 X Input No Tri-state (Hi-Z)

0 1 0 Input Yes Pxn will source current if ext. pulled low

0 1 1 Input No Tri-state (Hi-Z)

1 0 X Output No Output Low (Sink)

1 1 X Output No Output High (Source)

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Figure 10-3. Synchronization when Reading an Externally Applied Pin value

Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As in di-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is one system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

XXX in r17, PINx

0x00 0xFF

INSTRUCTIONS

SYNC LATCH

PINxn

r17

XXX

SYSTEM CLK

pd, max

pd, min

out PORTx, r16 nop in r17, PINx

0xFF

0x00 0xFF

SYSTEM CLK

r16

INSTRUCTIONS

SYNC LATCH

PINxn

r17

tpd

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10.1.5 Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital inpu t signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode , Power-save mode, and Stan dby mode to avoid high power co nsumption if

some input signals are left floating, or have an analog signal level close to VCC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 60.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge , Falling Edge, or Any Logic Change on Pin” while the external inter rupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

10.1.6 Unconnected Pins

If some pins are unused, it is reco mmended to ensur e that these pi ns have a defined le vel. Even

though most of the digital inputs are disabled in the deep sleep modes as described ab ove, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-u p or pulldown. Connecting unused pins

directly to VCC or GND is not recommended, since this ma y cause ex cessiv e currents if the pin is

accidentally configured as an output.

10.1.7 Program Examples

The following code examples show how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values

are read back again, but as previou sly discussed, a nop instruction is included to be able to r ead

back the value recently assigned to some of the pins.

Note: Two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1 and 4,

until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as

strong high drivers.

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

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Note: See “Code Examples” on page 6 .

10.2 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5

shows how the po rt pin control signals from the sim plified Figure 10-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

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Figure 10-5. Alternate Port Functions(1)

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

clk

RPx

RRx

WRx

RDx

WDx

PUD

SYNCHRONIZER

WDx: WRITE DDRx

WRx: WRITE PORTx

RRx: READ PORTx REGISTER

RPx: READ PORTx PIN

PUD: PULLUP DISABLE

clkI/O: I/O CLOCK

RDx: READ DDRx

SET

CLR

DIxn

AIOxn

DIEOExn

PVOVxn

PVOExn

DDOVxn

DDOExn

PUOExn

PUOVxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

DIxn: DIGITAL INPUT PIN n ON PORTx

AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

RESET

Q D

CLR

PINxn

PORTxn

DDxn

DATA BUS

DIEOVxn

SLEEP

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

SLEEP: SLEEP CONTROL

Pxn

I/O

PTOExn

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

WPx: WRITE PINx

WPx

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Table 10-2 summarizes the function of the overri ding signals. Th e pin an d port indexes from Fig-

ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

The following subsections shortly describe the alternate functions for each port, an d relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

PUOE Pull-up Override

Enable

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

PUOV Pull-up Override

Value

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

DDOE Data Direction

Override Enable

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Registe r bi t.

DDOV Data Direction

Override Value

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

PVOE Port Value

Override Enable

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

PVOV Port Value

Override Value If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PTOE Port Toggle

Override Enable If PTOE is set, the PORTxn Register bit is inverted.

DIEOE Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOV Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

DI Digital Input

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt-trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

AIO Analog

Input/Output

This is the Analog Input/Output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

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10.2.1 Alternate Functions of Port A

The Port A pins with alternate function are shown in Table 10-3.

• Port A, Bit 7 – ADC6/AIN0/PCINT7

• ADC6: Analog to Digital Converter, Channel 6.

• AIN0: Analog Comparator Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

• PCINT7: Pin Change Interrupt source 8.

• Port A, Bit 6 – ADC5/AIN1/PCINT6

• ADC5: Analog to Digital Converter, Channel 5.

• AIN1: Analog Comparator Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

• PCINT6: Pin Change Interrupt source 6.

Table 10-3. Port B Pins Alternate Functions

Port Pin Alternate Function

PA7 ADC6: ADC Input Channel 6

AIN0: Analog Comparator Input

PCINT7:Pin Change Interrupt 0, Source 7

PA6 ADC5: ADC Input Channel 5

AIN1: Analog Comparator Input

PCINT6:Pin Change Interrupt 0, Source 6

PA5 ADC4: ADC Input Channel 4

AIN2: Analog Comparator Input

PCINT5:Pin Change Interrupt 0, Source 5

PA4 ADC3: ADC Input Channel 3

ICP0: Timer/Counter0 Input Cap tu re Pin

PCINT4:Pin Change Interrupt 0, Source 4

PA3 AREF: External Analog Reference

PCINT3:Pin Change Interrupt 0, Source 3

PA2

ADC2: ADC Input Channel 2

INT1: External Interrupt 1 Input

USCK: USI Clock (Three Wire Mode)

SCL : USI Clock (Two Wire Mode)

PCINT2:Pin Change Interrupt 0, Source 2

PA1 ADC1: ADC Input Channel 1

DO: USI Data Output (Three Wire Mode)

PCINT1:Pin Change Interrupt 0, Source 1

PA0

ADC0: ADC Input Channel 0

DI: USI Data Input (Three Wire Mode)

SDA: USI Data Input (Two Wire Mode)

PCINT0:Pin Change Interrupt 0, Source 0

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• Port A, Bit 5 – ADC4/AIN2/PCINT5

• ADC4: Analog to Digital Converter, Channel 4.

• AIN2: Analog Comparator Input. Configure the port pin as input with the internal pull-up

switched off to avoid the digital port function from interfering with the function of the Analog

Comparator.

• PCINT5: Pin Change Interrupt source 5.

• Port A, Bit 4 – ADC3/ICP0/PCINT4

• ADC3: Analog to Digital Converter, Channel 3.

• ICP0: Timer/Counter0 Input Capture Pin.

• PCINT4: Pin Change Interrupt source 4.

• Port A, Bit 3 – AREF/PCINT3

• AREF: External analog referen ce for ADC. Pullup and output dr iver are disabled on PA3

when the pin is used as an external reference or internal volt age reference with external

capacitor at the AREF pin.

• PCINT3: Pin Change Interrupt source 3.

• Port A, Bit 2 – ADC2/INT1/USCK/SCL/PCINT2

• ADC2: Analog to Digital Converter, Channel 2.

• INT1: The PA2 pin can serve as an External Interrupt source 1.

• USCK: Three-wire mode Universal Serial Interface Clock.

• SCL: Two-wire mode Serial Clock for USI Two-wire mo de .

• PCINT2: Pin Change Interrupt source 2.

• Port A, Bit 1 – ADC1/DO/PCINT1

• ADC1: Analog to Digital Converter, Channel 1.

• DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output

overrides PORTA1 value and it is driven to the port when data direction bit DDA1 is set.

PORTA1 still enables the pull-up, if the direction is input and PORTA1 is set.

• PCINT1: Pin Change Interrupt source 1.

• Port A, Bit 0 – ADC0/DI/SDA/PC INT0

• ADC0: Analog to Digital Converter, Channel 0.

• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

• SDA: Two-wire mode Serial Interface Data.

• PCINT0: Pin Change Interrupt source 0.

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Table 10-4 and Table 10-5 relate the alternate functions of Port A to the overriding signals

shown in Figure 10-5 on page 61.

Table 10-4. Overriding Signals for Alternate Functions in PA7:PA4

Signal

Name PA7/ADC6/AIN0/

PCINT7 PA6/ADC5/AIN1/

PCINT6 PA5/ADC4/AIN2/

PCINT5 PA4/ADC3/ICP0/

PCINT4

PUOE0000

PUOV0000

DDOE0000

DDOV0000

PVOE0000

PVOV0000

PTOE0000

DIEOE PCINT7 • PCIE +

ADC6D PCINT6 • PCIE +

ADC5D PCINT5 • PC IE +

ADC4D PCINT4 • PCIE +

ADC3D

DIEOV ADC6D ADC5D ADC4D ADC3D

DI PCINT7 PCINT6 PCINT5 ICP0/PCINT4

AIO ADC6, AIN0 ADC5, AIN1 ADC4, AIN2 ADC3

Table 10-5. Overriding Signals for Alternate Functions in PA3:PA0

Signal

Name PA3/AREF/

PCINT3 PA2/ADC2/INT1/

USCK/SCL/PCINT2 PA1/ADC1/DO/

PCINT1 PA0/ADC0/DI/SDA/

PCINT0

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 USI_TWO_WIRE •

USIPOS 0USI_TWO_WIRE •

USIPOS

DDOV 0 (USI_SCL_HOLD +

PORTB2) • DDB2 •

USIPOS 0(SDA + PORTB0) •

DDRB0 • USIPOS

PVOE 0 USI_TWO_WIRE •

DDRB2 USI_THREE_WI

RE • USIPOS USI_TWO_WIRE •

DDRB0 • USIPOS

PVOV 0 0 DO • USIPOS 0

PTOE 0 USI_PTOE • USIPOS 0 0

DIEOE PCINT3 •

PCIE PCINT2 • PCIE + INT1 +

ADC2D + USISIE •

USIPOS

PCINT1 • PCIE +

ADC1D

PCINT0 • PCIE +

ADC0D + USISIE •

USIPOS

DIEOV 0 ADC2D ADC1D ADC0D

DI PCINT3 USCK/SCL/INT1/ PCINT2 PCINT1 DI/SDA/PCINT0

AIO AREF ADC2 ADC1 ADC0

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10.2.2 Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 10-6.

• Port B, Bit 7 – RESET/ dW/ ADC10/ PCINT15

• RESET, Reset pin: When the RSTDISBL Fuse is programmed, this pin functions as a normal

I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset as its reset

sources. When the RSTDISBL F use is unprogra mmed, th e reset circu itry is connected to the

pin, and the pin can not be used as an I/O pin.

• If PB7 is used as a reset pin, DDB7, PORTB7 and PINB7 will all read 0.

• dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are

unprogrammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional

I/O pin with pull-up enabled and becomes the communication gateway between target and

emulator.

Table 10-6. Port B Pins Alternate Functions

Port Pin Alternate Function

PB7

RESET: Reset pin

dW: debugWire I/O

ADC10: ADC Input Channel 10

PCINT15:Pin Change Interrupt 0, Source 15

PB6

ADC9: ADC Input Channel 9

T0: Timer/Counter0 Clock Source

INT0: External Interrupt 0 Input

PCINT14:Pin Change Interrupt 0, Source 14

PB5

XTAL2: Crystal Oscillator Output

CLKO: System Clock Output

OC1D: Timer/Counter1 Compare Match D Output

ADC8: ADC Input Channel 8

PCINT13:Pin Change Interrupt 0, Source 13

PB4

XTAL1: Cryst al Osci l lato r In pu t

CLKI: External Clock Input

OC1D: Inverted Timer/Counter1 Compare Match D Output

ADC7: ADC Input Channel 7

PCINT12:Pin Change Interrupt 0, Source 12

PB3 OC1B: Timer/Counter1 Compare Match B Output

PCINT11:Pin Change Interrupt 0, Source 11

PB2

USCK: USI Clock (Three Wire Mode)

SCL : USI Clock (Two Wire Mode)

OC1B: Inverted Timer/Counter1 Compare Match B Output

PCINT10:Pin Change Interrupt 0, Source 10

PB1 DO: USI Data Output (Three Wire Mode)

OC1A: Time r /Counter1 Compare Match A Output

PCINT9:Pin Change Interrupt 1, Source 9

PB0

DI: USI Data Input (Three Wire Mode)

SDA: USI Data Input (Two Wire Mode)

OC1A: Inverted Timer/Counter1 Compare Match A Output

PCINT8:Pin Change Interrupt 1, Source 8

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• ADC10: ADC input Channel 10. Note that ADC input channel 10 uses analog power.

• PCINT15: Pin Change Interrupt source 15.

• Port B, Bit 6 – ADC9/ T0/ INT0/ PCINT14

• ADC9: ADC input Channel 9. Note that ADC input channel 9 uses analog power.

• T0: Timer/Counter0 counter source.

• INT0: The PB6 pin can serve as an External Interrupt source 0.

• PCINT14: Pin Change Interrupt source 14.

• Port B, Bit 5 – XTAL2/ CLKO/ ADC8/ PCINT13

• XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency

crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

• CLKO: The divided system clock can be output on the PB5 pin, if the CKOUT Fuse is

programmed, regardless of the PORTB5 and DDB5 settings. It will also be output during

reset.

• OC1D Output Compare Match output: The PB5 pin can serve as an external output for the

T imer/Counter1 Compare Match D when configured as an output (DDA1 set). The OC1D pin

is also the output pin for the PWM mode timer function.

• ADC8: ADC input Channel 8. Note that ADC input channel 8 uses analog power.

• PCINT13: Pin Change Interrupt source 13.

• Port B, Bit 4 – XTAL1/ CLKI/ OC1B/ ADC7/ PCINT12

• XTAL1/CLKI: Chip clock Oscillator pin 1. Used for all chip clock sources except internal

calibrated RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

•OC1D

: Inverted Output Compare Match output: The PB4 pin can serve as an external output

for the Tim e r/C ou nt er 1 Co mpare Matc h D w he n configured as an outp ut (DDA0 set) . Th e

OC1D pin is also the inverted output pin for the PWM mode timer function.

• ADC7: ADC input Channel 7. Note that ADC input channel 7 uses analog power.

• PCINT12: Pin Change Interrupt source 12.

• Port B, Bit 3 – OC1B/ PCINT11

• OC1B, Out put Com pare Match output: The PB3 pi n can serve as an external output for the

Timer/Counter1 Compare Match B. The PB3 pin has to be configured as an output (DDB3

set (one)) to serve this function. The OC1B pin is also the output pin for the PWM mode timer

function.

• PCINT11: Pin Change Interrupt source 11.

• Port B, Bit 2 – SCK/ USCK/ SCL/ OC1B/ PCINT10

• USCK: Three-wire mode Universal Serial Interface Clock.

• SCL: Two-wire mode Serial Clock for USI Two-wire mo de .

•OC1B

: Inverted Output Comp are Match outpu t: The PB2 pin ca n serve as an exte rnal outp ut

for the Timer/Counter1 Compare Match B when configured as an output (DDB2 set). The

OC1B pin is also the inverted output pin for the PWM mode timer function.

• PCINT10: Pin Change Interrupt source 10.

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• Port B, Bit 1 – MISO/ DO/ OC1A/ PCINT9

• DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output

overrides POR TB1 value and it is driven to the po rt when dat a direction bit DDB1 is set (one).

PORTB1 still enables the pull-up, if the direction is input and POR TB1 is set (one).

• OC1A: Out put Com pare Match output: The PB1 pi n can serve as an external output for the

T imer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin

is also the output pin for the PWM mode timer function.

• PCINT9: Pin Change Interrupt source 9.

• Port B, Bit 0 – MOSI/ DI/ SDA/ OC1A/ PCINT8

• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

• SDA: Two-wire mode Serial Interface Data.

•OC1A

: Inverted Output Comp are Match outpu t: The PB0 pin ca n serve as an exte rnal outp ut

for the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The

OC1A pin is also the inverted output pin for the PWM mode timer function.

• PCINT8: Pin Change Interrupt source 8.

Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 61.

Note: 1. “1” when the Fuse is “0” (Programmed).

Table 10-7. Overriding Signals for Alternate Functions in PB7:PB4

Signal

Name

PB7/RESET/

dW/ADC10/

PCINT15 PB6/ADC9/T0/

INT0/PCINT14

PB5/XTAL2/CLKO/

OC1D/ADC8/

PCINT13(1)

PB4/XTAL1/

OC1D/ADC7/

PCINT12(1)

PUOE RSTDISBL(1) •

DWEN(1) 0 INTRC • EXTCLK INTRC

PUOV1000

DDOE RSTDISBL(1) •

DWEN(1) 0 INTRC • EXTCLK INTRC

DDOV debugWire Transmit 0 0 0

PVOE 0 0 OC1D Enable OC1D Enable

PVOV 0 0 OC1D OC1D

PTOE0000

DIEOE 0 RSTDISBL + (PCINT5

• PCIE + ADC9D)

INTRC • EXTCLK +

PCINT4 • PCIE +

ADC8D

INTRC + PCINT12 •

PCIE + ADC7D

DIEOV ADC10D ADC9D (INTRC • EXTCLK) +

ADC8D INTRC • ADC7D

DI PCINT15 T0/INT0/PCINT14 PCINT13 PCINT12

AIO RESET / ADC10 ADC9 XTAL2, ADC8 XTAL1, ADC7

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Note: 1. INTRC means that one of the internal RC Oscillators is selected (by the CKSEL fuses),

EXTCK means that external clock is selected (by the CKSEL fuses).

10.3 Register Description

10.3.1 MCUCR – MCU Control Register

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 56 for more details about this feature.

10.3.2 PORTA – Port A Data Register

10.3.3 DDRA – Port A Data Direction Register

Table 10-8. Overriding Signals for Alternate Functions in PB3:PB0

Signal

Name PB3/OC1B/

PCINT11 PB2/SCK/USCK/SCL/O

C1B/PCINT10 PB1/MISO/DO/OC1A/

PCINT9 PB0/MOSI/DI/SDA/

OC1A/PCINT8

PUOE 0 0 0 0

PUOV 0 0 0 0

DDOE 0 USI_TWO_WIRE •

USIPOS 0USI_TWO_WIRE •

USIPOS

DDOV 0 (USI_SCL_HOLD +

PORTB2) • DDB2 •

USIPOS 0(SDA + PORTB0) •

DDB0 • USIPOS

PVOE OC1B Enable OC1B Enable + USIPOS

• USI_TWO_WIRE •

DDB2

OC1A Enable +

USIPOS •

USI_THREE_WIRE

OC1A Enable +

(USI_TWO_WIRE •

DDB0 • USIPOS)

PVOV OC1B OC1B OC1A + (DO •

USIPOS)OC1A

PTOE 0 USITC • USIPOS 00

DIEOE PCINT11 • PCIE PCINT10 • PCIE +

USISIE • USIPOS PCINT9 • PCIE PCINT8 • PCIE +

(USISIE • USIPOS)

DIEOV 0 0 0 0

DI PCINT11 USCK/SCL/PCINT10 PCINT9 DI/SDA/PCINT8

AIO

Bit 7 6 5 4 3 2 1 0

0x35 (0x55) -PUDSE SM1 SM0 - ISC01 ISC00 MCUCR

Read/Write R R/W R/W R/W R/W R R R

Initial Value 0 0 0 0 0 0 0 0

Bit 76543210

0x1B (0x3B) PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 PORTA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x1A (0x3A) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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10.3.4 PINA – Port A Input Pins Address

10.3.5 PORTB – Port B Data Register

10.3.6 DDRB – Port B Data Direction Register

10.3.7 PINB – Port B Input Pins Address

Bit 76543210

0x19 (0x39) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

Bit 76543210

0x18 (0x38) PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x17 (0x37) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x16 (0x36) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

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11. Timer/Counter0

11.1 Features •Clear Timer on Compare Match (Auto Reload)

•One Input Capture unit

•Four Independent Interrupt Sources (TOV0, OCF0A, OCF0B, ICF0)

•8-bit Mode with Two Independent Output Compare Units

•16-bit Mode with One Independent Output Compare Unit

11.2 Overview Timer/Counter0 is a general purpose 8/16-bit Timer/Counter module, with two/one Output Com-

pare units and Inpu t Ca pt ur e fea tu r e.

The general operation of Timer/Counter0 is described in 8/16-bit mode. A simplified block dia-

gram of the 8/16-bit Timer/Counter is shown in Figure 11 -1. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold . For actual placement of I/O pins, refer to “Pin-

out ATtiny261/461/86 1 and ATtiny261V/461V/861 V” on page 2. Device-specific I/O Register and

bit locations are listed in the “Register Description” on page 84.

Figure 11-1. 8-/16-bit Timer/Counter Block Diagram

11.2.1 Registers The Timer/Counter0 Low Byte Register (TCNT0L) and Output Compare Registers (OCR0A and

OCR0B) are 8-bit r egisters. Inte rrupt r equest (abb revia ted Int.Req. in Figu re 11 -1) signals ar e all

Clock Select

Timer/Counter

DATA B U S

OCRnB

TCNTnL

Noise

Canceler

ICPn

Edge

Detector

Control Logic

TOP

Count

Clear

Direction

TOVn (Int. Req.)

OCnA (Int. Req.)

OCnB (Int. Req.)

ICFn (Int. Req.)

TCCRnA TCCRnB

( From Analog

Comparator Ouput )

Edge

Detector

( From Prescaler )

clk

OCRnA

TCNTnH

Fixed TOP value

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visible in the Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the

Timer Interrupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.

In 16-bit mode one more 8-bit register is available, the Timer/Counter0 High Byte Register

(TCNT0H). Also, in 16-bit mode, there is only one output compare unit as the two Output Com-

pare Registers, OCR0A and OCR0B, are combined to one, 16-bit Output Compare Register,

where OCR0A contains the low byte and OCR0B contains the high byte of the word. When

accessing 16-bit registers, special procedures described in section “Accessing Registers in 16-

bit Mode” on page 80 must be followed.

11.2.2 Definitions Many register and bit refer ences in this section are written in general for m. A lower case “n ”

replaces the Timer/Counter num ber, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e. TCNT0L for accessing

Timer/Counter0 counter value, and so on.

The definitions in Table 11-1 are also used exte nsively throughout the document.

11.3 Clock SourcesThe Timer/Counter can be clocked internally, via the prescaler, o r by an external clock sour ce on

the T0 pin. The Clock Select logic is controlled by the Clock Select (CS02:0) bits located in the

Timer/Counter Control Register 0 B (TCCR0B), and controls which clock source and edge the

Timer/Counte r uses to incremen t its value. T he Timer/C ounter is inactive wh en no clock s ource

is selected. The output from the Clock Select logic is referred to as the timer clock (clkT0).

11.3.1 Prescaler The Timer/Counter can be clocke d dir ectly by the system clock (by setting the CSn2:0 = 1). This

provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system

clock frequency (fCLK_I/O). Alternatively, one of four taps from the prescaler can be used as a

clock source.

See Figure 11-2 for an illustration of the prescaler unit.

Table 11-1. Definitions

Constant Description

BOTTOM The counter reaches BOTTOM when it becomes 0x00

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

TOP The counter reach es the TOP when it becomes equal to the highest value in th e count

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the

value stored in the OCR0A Register. The assignment depends on the mode of operation

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Figure 11-2. Prescaler for Timer/Counter0

Note: 1. The synchronization logic on the input pins (T0) is shown in Figure 11-3.

The prescaled clock has a frequency of fCLK_I/O/8, fCLK_I/O/64, fCLK_I/O/256, or fCLK_I/O/1024. See

Table 11-4 on page 85 for details.

11.3.1.1 Prescaler Reset

The prescaler is free running, i.e. it operates independently of the Clock Se lect logic of the

Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the stat e

of the prescaler will have implications for situations where a prescaled clock is used. One exam-

ple of prescaling artifa cts occurs when the timer is ena bled and clocked by the prescale r (6 >

CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the first count

occurs can be from 1 to N+1 system clock cycles, where N equals the pre scaler divisor (8, 64,

256, or 1024). It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to

program execution.

11 .3.2 External Clock Source

An external clock source applied to the T0 pin can be used as Timer/Counter clock (clkT0). The

T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 11-3 shows a functional

equivalent block diagram of the T0 synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clkI/O). The latch is transparent in the

high period of the internal system clock.

The edge detector gen erates one cl k T0 pulse for each positive (CSn2:0 = 7) or neg ative (CSn2 :0

= 6) edge it detects. See Table 11-4 on page 85 for details.

PSR0

Clear

clkT0

clkI/O

Synchronization

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Figure 11-3. T0 Pin Sampling

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pi n to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (fExtClk < fclk_I/O/2) give n a 50/50% duty cycle. Since th e edge detector use s

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (Nyquist sampling theorem). However, du e to variation of the system clock frequency

and duty cycle caused by Oscillator source (crystal, resonator, and capacitors) tolerances, it is

recommended that maximu m frequency of an external clock source is less than fclk_I/O/2.5.

An external clock source can not be pre sca le d.

11.4 Counter Unit The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-4 shows a block diagram of the counter and its surroundings.

Table 11-2. Counter Unit Block Diagram

Signal description (internal signals):

count Increment or decrement TCNT0 by 1.

clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T0 in the following.

top Signalize that TCNT0 has reache d maximum value.

The counter is incremented at each timer clock (clkT0) until it passes its TOP value and then

restarts from BOTTOM. The counting sequence is determined by the setting of the CTC0 bit

located in the Timer/Counter Control Register (TCCR0A). For more details about counting

sequences, see “Modes of Operation” on page 77. clkT0 can be generated from an external or

Tn_sync

(To Clock

Select Logic)

Edge DetectorSynchronization

DQDQ

clk

I/O

DATA BUS

TCNTn Control Logic

count

TOVn

(Int.Req.)

Clock Select

top

Edge

Detector

( From Prescaler )

clkTn

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internal clock source, selected by the Clock Select bits (CS02:0). When no clock source is

selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the

CPU, regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all

counter clear or count operations. The Timer/Counter Overflow Flag (TOV0) is set when the

counter reaches the maximum value and it can be used for generating a CPU interrupt.

11.5 Input Capture Unit

The Timer/Counter incorporates an Input Capture unit that can capture external events an d give

them a time-stamp indicating time of occurrence. The external signal indica ting an event, or mul-

tiple events, can be app lied via th e ICP0 pin or alter natively, via the analog-comp arator un it. The

time-stamps can then be used to calculate frequency, duty-cycle, and other features of the sig-

nal applied. Alternatively the time-stamps can be used for creating a log of the events.

The Input Capture unit is illustrated by the block diagram shown in Figure 11-4. The elements of

the block diagram that are not directly a part of the Input Capture unit are gr ay sha de d.

Figure 11-4. Input Capture Unit Block Diagram

The Output Compare Register OCR0A is a dual-purpose registe r that is also used as an 8-bit

Input Capture Register ICR0. In 16-bit Input Capture mode the Output Compare Register

OCR0B serves as the high byte of the Input Capture Register ICR0. In 8-bit Input Capture mode

the Output C ompar e Reg ister O CR0B is fr ee to be used as a n orm al Outpu t Com pare Re gister ,

but in 16-bit Inp ut Capture mo de the Output Co mpare Unit cannot be used as there are no free

Output Compare Register(s). Even though the Input Capture register is called ICR0 in this sec-

tion, it is refering to the Output Compare Register(s).

When a change of the logic level (a n event) occu rs on the Input Captur e pin (ICP0), altern atively

on the Analog Compar ator output (ACO), and this change confirms to the setting of the edge

detector, a capture will be triggered. When a capture is triggered, the value of the counter

(TCNT0) is written to the Input Capture Re gister (ICR0). The Input Capture Flag (ICF0) is set at

ICF0 (Int.Req.)

Analog

Comparator

WRITE ICR0 (16-bit Register)

OCR0B (8-bit)

Noise

Canceler

ICP0

Edge

Detector

TEMP (8-bit)

DATA BUS (8-bit)

OCR0A (8-bit)

TCNT0 (16-bit Counter)

TCNT0H (8-bit) TCNT0L (8-bit)

ACIC0* ICNC0 ICES0

ACO*

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the same system clock as the TCNT0 value is copied into Input Capture Register. If enabled

(TICIE0=1), the Input Capture Flag generates an Input Capture interrupt. The ICF0 flag is auto-

matically cleared when the interrupt is executed. Alternatively the ICF0 flag can be cleared by

software by writing a logical one to its I/O bit location.

11.5.1 Input Capture Trigger Source

The default trigger source for the Input Capture unit is the Input Capture pin (ICP0).

Timer/Counter0 can alternatively use the Analog Comparator output as trigger source for the

Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog

Comparator Input Capture Enable (ACIC0) bit in the Timer/Counter Control Register A

(TCCR0A). Be aware that changing trigger source can trigger a capture. The Input Capture Flag

must therefore be cleared after the cha nge.

Both the Input Capture pin (ICP0) and the Analog Comparator output (ACO) inputs are sampled

using the same technique as for the T0 pin (Figure 11-4 on page 85). The edge detector is also

identical. However, when the noise canceler is enabled, additional logic is inserted before the

edge detector, which increases the delay by four system clock cycles. An Input Capture ca n also

be triggered by software by controlling the port of the ICP0 pin.

11.5.2 Noise Canceler

The noise canceler improves noise immunity by using a simple digital filtering scheme. The

noise canceler input is monitored over four samples, and all four must be equal for changing the

output that in turn is used b y the edge detector.

The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC0) bit in

Timer/Counter Control Re gister B (TCCR0B). When enab led the noise canceler intr oduces addi-

tional four system clock cycles of delay from a change applied to the input, to the update of the

ICR0 Register. The noise canceler uses the system clock and is therefore not affected by the

prescaler.

11.5.3 Using the Input Capture Unit

The main challeng e when using the Inpu t Capture unit is to assign enoug h processor capacity

for handling the inco ming events. The time between two events is critica l. If the processor has

not read the captured value in the ICR0 Register before the next ev ent occurs, the ICR0 will be

overwritten with a new value. In this case the result of the capture will be incorrect.

When using the Input Capture interrupt, the ICR0 Register should be read as early in the inter-

rupt handler routine as possible. The maximum interrupt response time is dependent on the

maximum number of clock cycles it takes to handle any of the other interrupt requests.

Measurement of an external signal’s duty cycle requires that the trigger edge is changed after

each capture. Ch anging the edge sensing m ust be done as early as possible aft er the ICR0

cleared by software (writing a logical one to the I/O bit location). For measuring frequency only,

the trigger edge change is not required (if an interrupt handler is used).

11.6 Output Compare Unit

The comparator continuously compares Timer/Counter (TCNT0) with the Output Compare Reg-

isters (OCR0A and OCR0B), and whenever the Timer/Counter equals to the Output Compare

Regisers, the comparator signals a match. A match will set the Output Compare Flag at the next

timer clock cycle. In 8-bit mode the match can set either the Output Compare Flag OCF0A or

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OCF0B, but in 16-bit mode the match can set only the Output Compare Flag OCF0A as there is

only one Output Compare Unit. If the corresponding interrupt is enabled, the Output Compare

Flag generates an Output Compare interrupt. The Output Compare Flag is autom atically clear ed

when the interrup t is executed. Alter natively, the flag can be cleared by software by writing a log-

ical one to its I/O bit location. Figure 11-5 shows a block diagram of the Output Compare unit.

Figure 11-5. Output Compare Unit, Block Diagram

11 .6.1 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0H/L Regi ster will block any Compare Match that occur in

the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A/B to be

initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter

clock is enabled.

11.6.2 Using the Output Compare Unit

Since writing TCNT0H/L will block all Compare Matches for one timer clock cycle, there are risks

involved when changing TCNT0H/L when using the Output Compare Unit, independently of

whether the Timer/Counter is running or not. If the value written to TCNT0H/L equals the

OCR0A/B value, the Compare Match will be missed.

11.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the Timer/Counter Width (TCW0), Input Capture Enable (ICEN0) and Wave Genera-

tion Mode (CTC0) bits. See “TCCR0A – Timer/Counter0 Control Register A” on page 84.

Table 11-3 summarises the different modes of operation.

OCFnx (Int.Req.)

= (8/16-bit Comparator )

OCRnx

DATA BUS

TCNTn

Table 11-3. Modes of operation

Mode ICEN0 TCW0 CTC0 Mode of Operation TOP Update of OCRx at TOV Flag Set on

0000Normal, 8-bit Mode 0xFF Immediate MAX (0xFF)

1001CTC Mode, 8-bit OCR0A Immediate MAX (0xFF)

2 0 1 X Normal, 16-bit Mode 0xFFFF Immediate MAX (0xFFFF)

3 1 0 X Input Capture Mode, 8- bi t 0xFF Immediate MAX (0xFF)

4 1 1 X Input Capture Mode, 16 -b i t 0xFFFF Immediate MAX (0xFFFF)

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11.7.1 Normal, 8-bit Mode

In Normal 8-bit mode (see Table 11-3), the counter (TCNT0L) is incrementing until it overruns

when it passes its maximum 8-bit value (MAX = 0xFF) and then restarts from the botto m (0x00).

The Overflow Flag (TOV0) is set in the same timer clock cycle as when TCNT0L becomes zero.

The TOV0 Flag in this case behaves like a ninth bit, exce pt that it is only set, not cleared. How-

ever, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the

timer resolution can be increased by software. There are no special cases to consider in the

Normal 8-bit mode, a new counter value can be written anytime. The Output Compare Unit can

be used to generate interrupts at some given time.

11.7.2 Clear Timer on Compare Match (CTC) 8-bit Mode

In Clear Timer on Compare or CTC mode, see Table 11-3 on page 77, the OCR0A Re gister is

used to manipulate the counter resolution. In CTC mode the counter is cleared to zero when the

counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,

hence also its resolution. This mode allows greater control of the Compare Match output fre-

quency. It also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 11-6. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 11-6. CTC Mode, Timing Diagram

An interrupt ca n be gener ated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low pres caler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum valu e (0xFF) and wrap around s tarting at 0x00 before the Comp are Match can

occur. As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle

that the counter counts from MAX to 0x00.

11.7.3 Normal, 16-bit Mode

In 16-bit mode, see Tabl e 11-3 on page 77, the counter (TCNT0H/L) is a incremen ting until it

overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the

bottom (0x0000). The Overflow Flag (TOV0) will be set in the same timer clock cycle as the

TCNT0H/L becomes zero. The TOV0 Flag in this case behaves like a 17th bit, except that it is

only set, not cleared. However, combined with the timer overflow interrupt that automatically

clears the TOV0 Flag, the time r resolution can be increased by software. There are no spec ial

TCNTn

OCnx Interrupt Flag Set

1 4

Period 2 3

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cases to consider in the Normal mode, a new counter value can be written anytime. The Output

Compare Unit can be used to generate interrupts at some given time.

11.7.4 8-bit Input Capture Mode

The Timer/Counter0 can also be used in an 8-bit Input Capture mode, see Table 11-3 on page

77 for bit settings. For full description, see the section “Input Capture Unit” on page 75.

11.7.5 16-bit Input Capture Mode

The Timer/Counter0 can also be used in a 16-bit Input Capture mode, see Table 11-3 on page

77 for bit settings. For full description, see the section “Input Capture Unit” on page 75.

11.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clkT0) is therefore shown as a

clock enable sign al in the following figures. Th e figures include information on whe n Interrupt

Flags are set. Figure 11-7 co ntains timing data fo r basic Timer/Counter operation. The figur e

shows the count sequence close to the MAX value.

Figure 11-7. Timer/Counter Timing Diagram, no Prescaling

Figure 11-8 shows the same timing data, but with the prescaler enabled.

Figure 11-8. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)

Figure 11-9 on page 80 shows the settin g of OCF0A and OCF0B in Normal mode.

clkTn

(clkI/O/1)

TOVn

clkI/O

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

TOVn

TCNTn MAX - 1 MAX BOTTOM BOTTOM + 1

clkI/O

clkTn

(clkI/O/8)

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Figure 11-9. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (fclk_I/O/8)

Figure 11-10 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.

Figure 11-10. Timer/Co un te r T imin g Diagr am , CTC mode, with Prescaler (fclk_I/O/8)

11.9 Accessing Registers in 16-bit Mode

In 16-bit mode (the TCW0 bit is set to one) the TCNT0H/L and OCR0A/B or TCNT0L/H and

OCR0B/A are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The

16-bit register must be byte accessed using two read or write operations. The 16-bit

Timer/Counter has a single 8-bit register for temporary storing of the high byte of the 16-bit

access. The same temporary register is shared between all 16-bit registers. Accessing the low

byte triggers the 16-bit read or write o peration. When the low byte of a 16-bit register is written

by the CPU, the high byte sto red in the tempor ary reg ister, and the low byte written are both co p-

ied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is read

by the CPU, the high byte of the 16-bit registe r is copied into the tem por ary re giste r in the sam e

clock cycle as the low byte is read.

There is one exception in the temporary register usage. In the Output Compare mode the 16-bit

Output Compare Register OCR0A/B is read without the temporary register, because the Output

Compare Register contains a fixed value that is only changed by CPU access. However, in 16-

bit Input Capture mode the ICR0 register formed by the OCR0A and OCR0B registers must be

accessed with the temporary register.

To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low

byte must be read before the high byte.

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clkI/O

clkTn

(clk

I/O

/8)

OCFnx

OCRnx

TCNTn

(CTC)

TOP

TOP - 1 TOP BOTTOM BOTTOM + 1

clkPCK

clkTn

(clkPCK

/8)

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The following code examples show how to access the 16-bit tim er registers assuming that no

interrupts updates the temporary register. The same principle can be used directly for accessing

the OCR0A/B registers.

Note: See “Code Examples” on page 6 .

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 16-bit register, and the interrupt code

updates the tem por ary r egist er by ac cessin g th e sa me or any other of the 16-bit timer registers,

then the result of the access outsid e the interrupt will be corrupted. Therefore , when both the

main code and the interrupt code update the temporary register, the main code must disable the

interrupts du rin g the 16-b it access.

Assembly Code Example

...

; Set TCNT0 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TCNT0H,r17

out TCNT0L,r16

; Read TCNT0 into r17:r16

in r16,TCNT0L

in r17,TCNT0H

...

C Code Example

unsigned int i;

...

/* Set TCNT0 to 0x01FF */

TCNT0H = 0x01;

TCNT0L = 0xff;

/* Read TCNT0 into i */

i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8);

...

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The following code examples show how to do an atomic read of the TCNT0 register contents.

Reading any of the OCR0 register can be do n e by us ing the sam e pr inc i ple .

Note: See “Code Examples” on page 6 .

The assembly code example returns the TCNT0H/L value in the r17:r16 register pair.

Assembly Code Example

TIM0_ReadTCNT0:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT0 into r17:r16

in r16,TCNT0L

in r17,TCNT0H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example

unsigned int TIM0_ReadTCNT0( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT0 into i */

i = TCNT0L;

i |= ((unsigned int)TCNT0H << 8);

/* Restore global interrupt flag */

SREG = sreg;

return i;

}

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The following code examples show how to do an atomic write of the TCNT0H/L register con-

tents. Writing any of the OCR0A/B registers can be done by using the same principle.

Note: See “Code Examples” on page 6 .

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT0H/L.

11.9.1 Reusing the temporary high byte registe r

If writing to more than one 16-bit reg ister where the high byte is the same for all r egisters written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previou sly also ap plies in this case.

Assembly Code Example

TIM0_WriteTCNT0:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT0 to r17:r16

out TCNT0H,r17

out TCNT0L,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example

void TIM0_WriteTCNT0( unsigned int i )

{

unsigned char sreg;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT0 to i */

TCNT0H = (i >> 8);

TCNT0L = (unsigned char)i;

/* Restore global interrupt flag */

SREG = sreg;

}

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11.10 Register Description

11.10.1 TCCR0A – Timer/Counter0 Control Register A

• Bit 7 – TCW0: Timer/Counter0 Width

When this bit is written to one 16-bit mode is selected as described Figure 11-7 on page 79.

Timer/Counter0 width is set to 16-bits and the Output Com pare Registers OCR0A and OCR0B

are combined to form one 16-bit Output Compare Register. Because the 16-bit registers

TCNT0H/L and OCR0B/A are accessed by the AVR CPU via the 8-bit data bus, special proce-

dures must be followed. These procedures are described in section “Acces sing Registers in 16-

bit Mode” on page 80.

• Bit 6 – ICEN0: Input Capture Mode Ena ble

When this bit is written to onem, the Input Capture Mode is enabled.

• Bit 5 – ICNC0: Input Capture Noise Canceler

Setting this bit activates the Input Capture Noise Canceler. When the noise canceler is acti-

vated, the input from the Input Capture Pin (ICP0 ) is filtered. The filter function requires fo ur

successive equal v alued samples of the ICP0 pin for ch anging its output. The Input Ca pture is

therefore delayed by four System Clock cycles when the noise canceler is enabled.

• Bit 4 – ICES0: Input Capture Edge Select

This bit selects which edge on the In put Capture Pin (ICP0) that is used to trigger a captur e

event. When the ICES0 bit is written to zero, a falling (negative) edge is used as trigger, and

when the ICES0 bit is written to one, a rising (positive) edge will trigger the capture. When a cap-

ture is triggered according to the ICES0 setting, the counter value is copied into the Input

Capture Register. The event will also set the Input Capture Flag (ICF0), and this can be used to

cause an Input Capture Interrupt, if this interrupt is enabled.

• Bit 3 - ACIC0: Analog Comparator Input Capture Enable

When written logic one, this bit enables the input captur e function in Timer/Counte r0 to be trig-

gered by the Ana log Comp arator. The com parator o utput is in this case directly connected to the

input capture front-end logic, making the comparator utilize the noise canceler and edge select

features of the Timer/Cou nter0 Input Capture interrupt. Wh en written logic zero, no connection

between the Analog Comparator and the input capture function exists. To make the comparator

trigger the T imer/Counter0 Input Capture interrupt, the TICIE0 bit in the Timer Interrupt Mask

• Bits 2:1 – Res: Reserved Bits

These bits are reserved and will always read zero.

• Bit 0 – CTC0: Waveform Genera tion Mode

This bit controls the counting sequence of the counter, the source for maximum (TOP) cou nter

value, see Figur e 11-7 o n page 79. Mode s of opera tion supported by the Timer/ Counter unit ar e:

Normal mode (counter) and Clear Timer on Compare Match (CTC) mode (see “Modes of Oper-

ation” on page 77).

Bit 76543210

0x15 (0x35) TCW0 ICEN0 ICNC0 ICES0 ACIC0 – – CTC0 TCCR0A

Read/Write R/W R/W R/W R/W R/W R R R/W

Initial Value00000000

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11.10.2 TCCR0B – Timer/Counter0 Control Register B

• Bit 4 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the

value that is written to the PSR0 bit is kept, hence keeping the Prescaler Reset signal asserted.

This ensure s that the Timer/ Counte r is halte d and can be configured without the risk of advanc-

ing during configuration. When the TSM bit is written to zero, the PSR0 bit is cleared by

hardware, and the Timer/Counter start counting.

• Bit 3 – PSR0: Prescale r Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

• Bits 2:0 – CS02, CS01, CS00: Clock Select0, Bit 2, 1, and 0

The Clock Select0 bits 2, 1, and 0 de fine the prescaling source of Timer0.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

11.10.3 TCNT0L – Timer/Counter0 Register Low Byte

The Timer/Counter0 Register Low Byte, TCNT0L, gives direct access, both for read and write

operations, to the Timer/Counter unit 8-bit counter. Writing to the TCNT0L Register blocks (dis-

ables) the Compare Match on the following timer clock. Modifying the counter (TCNT0L) while

the counter is running, introduces a risk of missing a Compare Match between TCNT0L and the

OCR0x Registers. In 16-bit mode the TCNT0L register contains the lower part of the 16-bit

Timer/Counter0 Register.

Bit 76543210

0x33 (0x53) --- TSM PSR0 CS02 CS01 CS01 TCCR0B

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value00000000

Table 11-4. Clock Select Bit Description

CS02 CS01 CS00 Description

0 0 0 No clock source (Timer/Counter stopped)

001clk

I/O/(No prescaling)

010clk

I/O/8 (From prescaler)

011clk

I/O/64 (From prescaler)

100clk

I/O/256 (From prescaler)

101clk

I/O/1024 (From prescaler)

1 1 0 External clock source on T0 pin. Clock on falling edge.

1 1 1 External clock source on T0 pin. Clock on rising edge.

Bit 76543210

0x32 (0x52) TCNT0L[7:0] TCNT0L

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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11.10.4 TCNT0H – Timer/Counter0 Register High Byte

When 16-bit mode is selected (the TCW0 bit is set to one) the Timer/Counter Register TCNT0H

combined to the Timer/Counter Register TCNT0L gives direct access, both for read and write

operations , to the Time r/Coun ter unit 16-b it counte r. To ensure that both the high an d low bytes

are read and written simultaneously when the CPU accesses these registers, the access is per-

formed using an 8-bit temporary high byte register (TEMP). This temporary register is shared by

all the other 16-b it registers. See “Accessing Registers in 16-bit Mode” on page 80

11.10.5 OCR0A – Timer/Counter0 Output Compare Register A

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0L). A match can be used to generate an Output Compare interrupt.

In 16-bit mode the OCR0A registe r contains th e low byte of the 16- bit Output Compare Reg ister.

To ensure that both the high and the low bytes are written simultaneously when the CPU writes

to these registers, the access is performed using an 8-bit temporary high byte register (TEMP).

This temporary register is shared by all the other 16-bit registers. See “Accessing Regis ters in

16-bit Mode” on page 80.

11.10.6 OCR0B – Timer/Counter0 Output Compare Register B

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0L in 8-bit mode and TCNTH in 16-bit mode). A match can be used to gen-

erate an Output Compare interrupt.

In 16-bit mode the OCR0B register contains the high byte of the 16-bit Output Compare Regis-

ter. To ensure that both the high and the low bytes are written simultaneously when the CPU

writes to these registers, the access is performed using an 8-bit temporary high byte register

(TEMP). This tem po rar y re gis ter is sha r ed by a ll the ot he r 16- bit regi st er s. Se e “Accessing Reg-

isters in 16-bit Mode” on page 80.

11.10.7 TIMSK – Timer/Counter0 Interrupt Ma sk Register

• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Coun te r0 Compare M a tch A in te rr up t is en ab le d. T h e co rr esponding int er ru p t is e xe cu te d

Bit 76543210

0x14 (0x34) TCNT0H[7:0] TCNT0H

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x13 (0x33) OCR0A[7:0] OCR0A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x12 (0x32) OCR0B[7:0] OCR0B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x39 (0x59) OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R

Initial Value00000000

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if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrup t is enab led. The correspondin g interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

• Bit 0 – TICIE0: Timer/Counter0, Input Capture Interrupt Enable

When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally

enabled), th e Timer/Counter1 I nput Capture interru pt is enabled. The co rresponding Interrupt

Vector (See “Interrupts” on page 50.) is executed when the ICF0 flag, located in TIFR, is set.

11.10.8 TIFR – Timer/Counter0 Interrupt Flag Register

• Bit 4 – OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternativel y, OCF0A is cleared by writing a logic on e to

the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

The OCF0A is also set in 16-bit mode when a Compare Match occurs between the Timer/Coun-

ter and 16-bit data in OCR0B/A. The OCF0A is not set in Input Capture mode when the Output

Compare Register OCR0A is used as an Input Capture Register.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Ma tch occurs be tween the Timer/Counte r and the data in

OCR0B – Output Compare Register 0 B. OCF0B is cleared by hardwa re whe n executing the co r-

responding interrupt handling vector. Alternatively, OCF0B is cleare d by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

The OCF0B is not set in 16-bit Output Compare mode when the Output Compare Register

OCR0B is used as the high byte of the 16-bit Output Compare Register or in 16-bit Input Cap-

ture mode when the Output Compare Register OCR0B is used as the high b yte of the Input

Capture Register.

Bit 76543210

0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R

Initial Value00000000

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• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

• Bit 0 – ICF0: Timer/Counter0, Input Capture Flag

This flag is set when a capture event occurs on the ICP0 pin. When the Input Capture Register

(ICR0) is set to be used as the TOP value, the ICF0 flag is set when the counter re aches the

TOP value.

ICF0 is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,

ICF0 can be cleared by writing a logic one to its bit location.

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12. Timer/Counter1

12.1 Features •8/10-Bit Accuracy

•Three Indepen dent Output Compare Units

•Clear Timer on Compare Match (Auto Reload)

•Glitch Free, Phase and Fr equency Correct Pulse Width Modulator (PWM)

•Variable PWM Period

•High Spee d Asynchronous and Synchronou s Cloc k in g with Dedi ca te d Pres c al er

•Independent Dead Time Generators for Each PWM Channel

•Fault Protection Unit Can Disable PWM Outpu t Pins

•Five Independent Interrupt Sources (TOV1, OCF1A, OCD1B, OCF1D, FPF1)

12.2 Overview Timer/Counter1 is a general purpose high speed Timer/Counter module, with three independent

Output Compare Units, and with PWM suppor t.

The Timer/Counter1 features a hi gh resolution and a hig h accuracy usage with the lower pr esca-

ling opportunities. It can also support three accurate and high speed Pulse Width Modulators

using clock speeds up to 64 MHz. In PWM mode Timer/Counter1 and the output compare regis-

ters serve as triple stand-alone PWMs with non-overlapping non-inverted and inverted outputs.

Similarly, the high prescaling opportunities make this unit useful for lower speed functions or

exact timing functions with infrequent actions. A simplified block diagram of the Timer/Counter1

is shown in Figure 12-1.

Figure 12-1. Timer/Counter1 Block Diagram

8-BIT DATABUS

T/C INT. FLAG

10-BIT COMPARATOR

8-BIT OUTPUT COMPARE

T/C INT. MASK

TIMER/COUNTER1

(TCNT1)

DIRECTION

TIMER/COUNTER1 CONTROL LOGIC

OCF1B

TOV1

TOIE1

OCIE1B

OCIE1A

OCF1A

TOV1 OCF1B OC1AOCF1A

T/C CONTROL

COM1B1

PWM1A

PWM1B

COM1B0

FOC1A

FOC1B

10-BIT COMPARATOR

8-BIT OUTPUT COMPARE

COM1A1

COM1A0

T/C CONTROL

CS12

PSR1

CS11

CS10

CS13

OC1A OC1B OC1B

DEAD TIME GENERATOR DEAD TIME GENERATOR

10-BIT COMPARATOR

8-BIT OUTPUT COMPARE

10-BIT COMPARATOR

8-BIT OUTPUT COMPARE

COM1A1

PWM1D

COM1A0

FOC1D

T/C CONTROL

OCF1D

OCIE1D

OC1D OC1D

DEAD TIME GENERATOR

PSR1

OCW1A

OCW1B

OCW1D

2-BIT HIGH BYTE

WGM11

FPEN1

T/C CONTROL

COM1B1

COM1B0

COM1D1

COM1D0

FPNC1

FPES1

FPAC1

10-BIT OUTPUT

COMPARE REGISTER B

10-BIT OUTPUT

COMPARE REGISTER C

10-BIT OUTPUT

COMPARE REGISTER D

10-BIT OUTPUT

COMPARE REGISTER A

CLEAR

COUNT

CLK

T/C CONTROL

FAULT_PROTECTION

WGM10

FPIE1

FPF1

OC1OE5

OC1OE4

OC1OE3

OC1OE2

OC1OE1

OC1OE0

FPIE1

FPF1

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For actual placement of the I/O pins, refer to “Pinout ATtiny261/461/861 and

ATtiny261V/461V/861V” on page 2. The device-specific I/O register and bit locations are listed

in the “Register Description” on page 112.

12.2.1 Speed The maximum speed of the Timer/Counter1 is 64 MHz. However, if a supply voltage below 2.7

volts is used, it is recommended to use the Low Speed Mode (LSM), because the

Timer/Counter1 is not running fast enough on low vo ltage levels. In the Low Speed Mode the

fast peripheral clock is scaled down to 32 MHz. For more details about the Low Speed Mode,

see “PLLCSR – PLL Control and Status Register” on page 120.

12.2.2 Accuracy The Timer/Counter1 is a 10-bit Tim er/Count er module that can alternatively be used as an 8-bit

Timer/Counter. The Timer/Counter1 registers are basically 8-bit registers, but on top of that

there is a 2-bit High Byte Register (TC1H) that can be used as a common temporary buffer to

access the two MSBs of the 10-bit Timer/Counter1 registers by the AVR CPU via the 8-bit data

bus, if the 10-bit accuracy is used. Whereas, if the two MSBs of the 10-bit registers are written to

zero the Timer/Counter 1 is working as an 8-b it Time r/Counter. When readin g the low byte of any

8-bit register the two MSBs are written to the TC1H register, and when writing the low byte of

any 8-bit register the two MSBs are written from the TC1H register. Special procedures must be

followed when accessing the 10-bit Timer/Counter1 values via the 8-bit data bus. These proce-

dures are described in the section “Accessing 10-Bit Registers” on page 108.

12.2.3 Registers The Time r/Counter (TCNT1) and Output Compar e Registers (OCR1A, OCR1B, OCR1C and

OCR1D) are 8-bit registers that are used as a data source to be compared with the TCNT1 con-

tents. The OCR1A, OCR1B and OCR1D registers determine the action on the OC1A, OC1B and

OC1D pins and they can also generate the compare match interrupts. The OCR1C holds the

Timer/Coun ter TOP value, i.e. the clear on compare match value. Th e Timer/Counter1 High

Byte Register (TC1H) is a 2-bit re gister that is used as a common temporary bu ffer to acce ss the

MSB bits of the Timer/Counter1 registers, if the 10-bit accuracy is used.

Interrupt request (overflow TOV1, and compare matches OCF1A, OCF 1B, OCF1D and fault pro-

tection FPF1) signals are visible in the Timer Interrupt Flag Re gis te r (T IF R) an d Ti m er /Co u nt er1

Control Register D (TCCR1D). The interrup ts are individually masked with the Timer Interrupt

Mask Register (TIMSK) and the FPIE1 bit in the Timer/Counter1 Control Register D (TCCR1D).

Control signals are found in the Timer/Counter Control Registers TCCR1A, TCCR1B, TCCR1C,

TCCR1D and TCCR1E.

12.2.4 Synchronization

In asynchronous clocking mode the Timer/Counter1 and the prescale r allow running the CPU

from any clock source while th e pr es ca ler is o p era ting on the fast peripheral clock (PCK) having

frequency of 64 MHz (o r 32 MHz in Low Spee d Mode). T his is possible because there is a syn-

chronization boundary between the CPU clock domain and the fast peripheral clock domain.

Figure 12-2 shows Timer/Counter 1 synchronization register block diagram and describes syn-

chronization delays in between registers. Note that all clock gating details are not shown in the

figure.

The Timer/Counter1 register values go through the internal synchronization registers, which

cause the input synchronization delay, before affecting the counter operation. The registers

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TCCR1A, TCCR1B, TCCR1C, TCCR1D, OCR 1A, OCR1B, OCR1C and OCR1D can be read

back right after writing the register. The rea d back values are delayed for the Timer/Counter1

(TCNT1) register, Timer/Counter1 High Byte Register (TC1H) and flags (OCF1A, OCF1B,

OCF1D and TOV1), because of the input and output synchronization.

The system clock frequency m ust be lower than half of the PCK frequency, b ecause the syn-

chronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of the

PCK when the system clock is high. If the frequency of the system clock is too high, it is a risk

that data or control values are lost.

Figure 12-2. Timer/Counter1 Synchronization Register Block Diagram.

12.2.5 Definitions Many reg ister and bit references in this section are writte n in general form. A lower case “n”

replaces the Timer/Counter num ber, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A, B, C or D. However, when using the register or bit

defines in a program, the precise form must be used, i.e., TCNT1 for accessing Timer/Counter1

8-BIT DATABUS

OCR1A OCR1A_SI

TCNT1_SO

OCR1B OCR1B_SI

OCR1C OCR1C_SI

TCCR1A TCCR1A_SI

TCCR1B TCCR1B_SI

TCNT1 TCNT1_SI

OCF1A OCF1A_SI

OCF1B OCF1B_SI

TOV1 TOV1_SITOV1_SO

OCF1B_SO

OCF1A_SO

TCNT1

PCKE

PCK

IO-registersInput synchronization

registers

Timer/Counter1 Output synchronization

registers

SYNC

MODE

ASYNC

MODE

1 CK Delay 1/2 CK Delay

~1/2 CK Delay 1 PCK Delay 1 PCK Delay ~1 CK Delay

TCNT1

OCF1A

OCF1B

TOV1

1/2 CK Delay 1 CK Delay

OCR1D OCR1D_SI

TC1H TC1H_SI

TCCR1C TCCR1C_SI

TCCR1D

OCF1D OCF1D_SI

OCF1D_SO

OCF1D

TC1H_SO

TC1H

TCCR1D_SI

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counter value and so on. The definitions in Table 12-1 are used extensively throughout the

document.

12.3 Clock SourcesThe Timer/Counter is clocked internally, either from CK or PCK. See bits CSxx in Table 12-17 on

page 116 and bit PCKE in “PLLCSR – PLL Control and Status Register” on page 120.

12.3.1 Prescaler Figure 12-3 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-

nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses

the system clock (CK) as a clock timebase and asynchronous mode uses the fast peripheral

clock (PCK) as a clock time base. The PCKE bit from the PLLCSR register enables the asyn-

chronous mode when it is set (‘1’).

Figure 12-3. Timer/Counter1 Prescaler

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,

and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.

The clock options are illustrated in Figure 12-3 and desribed in “TCCR1B – Tim er/Counter1

Control Register B” on page 115.

The frequency of th e fast periphe ral clock is 64 MHz or 32 MHz in Low Speed mode (the LSM bit

in PLLCSR register is set to one). The Low Speed Mode is recommended to use when the sup-

ply voltage below 2.7 volts are used.

Table 12-1. Definitions

Constant Description

BOTTOM The counter reaches BOTTOM when it becomes 0x00

MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

TOP The counter reach es the TOP when it becomes equal to the highest value in th e count

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the

value stored in the OCR0A Register. The assignment depends on the mode of operation

TIMER/COUNTER1 COUNT ENABLE

PSR1

CS10

CS11

CS12

PCK 64/32 MHz

CS13

14-BIT

T/C PRESCALER

T1CK/2

T1CK

T1CK/4

T1CK/8

T1CK/16

T1CK/32

T1CK/64

T1CK/128

T1CK/256

T1CK/512

T1CK/1024

T1CK/2048

T1CK/4096

T1CK/8192

T1CK/16384

PCKE

T1CK

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12.3.1.1 Prescaler Reset

Setting the PSR1 bit in TCCR1B register resets the prescaler. It is possible to use the Prescaler

Reset for synchronizing the Timer/Counter to program execution.

12.3.1.2 Prescaler Initializ ation for Asynchronous Mode

To change Timer/Counter1 to the asynchronous mode follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

12.4 Counter Unit The main part of the Timer/Counter1 is the programmable bi-directional counter unit. Figure 12-

4 shows a block diagram of the counter and its surroundings.

Figure 12-4. Counter Unit Block Diagram

Signal description (internal signals):

count TCNT1 increment or decrement enable.

direction Select between increment and decrement.

clear Clear TCNT1 (set all bits to zero).

clkTnTimer/Co un te r clo ck, re fe rr ed to as clk T1 in the following.

top Signalize that TCNT1 has reached maximum value.

bottom Signalize that TCNT1 has reached minimum value (zero).

Depending on the mode of o peration used, the co unter is cleared , incr eme nted , or de crem ented

at each timer clock (clkT1). The timer clock is generated from an synchronous system clock or an

asynchronous PLL clock using the Clock Select bits (CS13:0) and the PCK Enable bit (PCKE).

When no clock source is selected (CS13 :0 = 0) the timer is stopp ed . However, the TCNT1 value

can be accessed by the CPU, regardless of whether clk T1 is present or not. A CPU write over -

rides (has priority over) all counter clear or count operations.

The counting sequence of the Timer/Counter1 is determined by bits WGM11:10, PWM1A and

PWM1B, loc ated in the Tim er/Counter1 C ontrol Registers (TCCR1A, TCCR1C and TCCR1D).

For more details about advanced counting sequences and waveform generation, see “Modes of

Operation” on page 99. The Timer/Counter Overflow Flag (TOV1) is set according to the mode

of operation and can be used for generating a CPU interrupt.

DATA BUS

TCNT1 Control Logic

count

TOV1

top

Timer/Counter1 Count Enable

( From Prescaler )

bottom

direction

clear PCK

PCKE

clkT1

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12.4.1 Counter Initialization for Asynchronous Mode

To set Timer/Counter1 to asynchronous mod e follow the procedure below:

1. Enable PLL.

2. Wait 100 µs for PLL to stabilize.

3. Poll the PLOCK bit until it is set.

4. Set the PCKE bit in the PLLCSR register which enables the asynchronous mode.

12.5 Output Compare Unit

The comparator continuously compares T CNT1 with the Output Compare Registers (OCR1A,

OCR1B, OCR1C and OCR1D). Whenever TCNT1 equals to the Output Compare Register, the

comparator signals a match. A match will set the Output Compare Flag (OCF1A, OCF1B or

OCF1D) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Com-

pare Flag generates an Output Compare interrupt. The O utput Compare Flag is automatically

cleared when the interrupt is executed. Alternatively, the flag can be cleared by softwa re by writ-

ing a logical one to its I/O bit location. The Waveform Generator uses the match signal to

generate an output according to operating mode set by bits PWM1A, PWM1B, WGM11:10 and

COM1x1:0. The top and bottom signals are used by the Waveform Generator for handling the

special cases of the extreme values in some modes of operation (See “Modes of Operation” on

page 99.). Figure 12-5 shows a block diagram of the Output Compare unit.

Figure 12-5. Output Compare Unit, Block Diagram

The OCR1x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal mode of operation, the double buffering is disabled. The double

buffering synchronizes the update of the OCR1x Compare Registers to either top or bottom of

the counting sequence. The synchronization prevents the occurrence of odd-length, non-sym-

OCFnx (Int.Req.)

= (10-bit Comparator )

8-BIT DATA BUS

TCNTn

WGM10

Waveform Generator

COMnX1:0

PWMnx

TCnH

OCWnx

10-BIT TCNTn10-BIT OCRnx

OCRnx

FOCn

TOP

BOTTOM

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metrical PWM pulses, thereby making the output glitch-free. See Figure 12-6 for an example.

During the time between the write and the update operation, a read from OCR1A, OCR1B,

OCR1C or OCR1D will read the contents of the temporary location. This means that the most

recently written value always will read out of OCR1A, OCR1B, OCR1C or OCR1D.

Figure 12-6. Effects of Unsynchronized OCR Latching

12.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC1x) bit. Forcing Compare Match will not set the

OCF1x Flag or reload/clear the timer, but the Waveform Output (OCW1x) will be updated as if a

real Compare Match had occurred (the COM1 x1:0 bits settings define whether th e Waveform

Output (OCW1x) is set, cleared or toggled).

12.5.2 Compare Match Blocking by TCNT1 Write

All CPU write operations to the TCNT1 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR1x to be initial-

ized to the same value as TCNT1 witho ut trigge ring an in terrupt whe n the Timer/Counte r clock is

enabled.

12.5.3 Using the Output Compare Unit

Since writing TCNT1 in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNT1 when using the Output Compare

Unit, independently of whether the Time r/Counter is ru nning or not. If the va lue written to TCNT1

equals the OCR1x value, the Compare Match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT1 value e qual to BOTTOM when the counter is

down-counting.

The setup of the Wa veform Output (OCW1x) sh ould be performe d before setting the Data Direc-

tion Register for the port pin to output. The easiest way of setting the OCW1x value is to use the

Force Output Compare (FOC1x) strobe bits in Normal mode. The O C1x keeps its value even

when changing between Waveform Generation modes.

Be aware that the COM1x1:0 bits are not double buffered together with the compare value.

Changing the COM1x1:0 bits will take effect immediately.

Output Compare

Waveform OCWnx

Output Compare

Wafeform OCWnx

Unsynchronized WFnx Latch

Synchronized WFnx Latch

Counter Value

Compare Value

Counter Value

Compare Value

Compare Value changes

Glitch

Compare Value changes

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12.6 Dead Time Generator

The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving

external power c ontrol switches safe ly. The Dead Time Generator is a separate b lock that can

be used to insert dead times (non-overlapping times) for the Timer/Counter1 complementary

output pairs OC1x and OC1x when th e PWM mo de is ena bled an d the COM1x1:0 bits a re set to

“01”. See Figure 12-7 below.

Figure 12-7. Block Diagram of Waveform Generator and Dead Time Generator.

The tasks are shared as follows: the Waveform Generator generates the output (OCW1x) and

the Dead Time Gen erator generates the non-overlapping PWM output pair from the output.

Three Dead Time Generators are provided, one for each PWM output. The non-overlap time is

adjustable and th e PWM output and it’s complementa ry output are adjusted sepa rately, and

independently for both PWM outputs.

The Dead Time Generation is based on 4-bit down counters that count the dead time, as shown

in Figure 12-8.

Figure 12-8. Dead Time Generator

There is a dedicated prescaler in front of the Dead Time Generator that can divide the

Timer/Coun ter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of dead times

that can be generated. The prescaler is controlled by two control bi ts DTPS11:10. The b lock has

also a rising and falling edge detector that is used to start the dead time counting period.

Depending on the edge, one of the tran sitions on the rising edges, O C1x or OC1x is delayed

until the co unter h as coun ted to ze ro. The co mpar ator is us ed to com pare t he coun ter with z ero

and stop the dead time insertion wh en zero has been reached . The counter is loa ded with a 4- bit

DT1H or DT1L value from DT1 I/O register, depending on the edge of the Waveform Output

(OCW1x) when the dead time insertion is started. The Ou tput Compare Output are delayed by

one timer clock cycle at minimum from the Waveform Output when the Dead Ti me is a djusted to

OCnx

WGM10

Waveform Generator

top

FOCn

COMnx

bottom

PWMnx

OCWnx Dead Time Generator OCnx

DTnH DTnL

DTPSn

CK OR PCK

CLOCK

OCnx

CLOCK CONTROL

OCnx

CK OR PCK

CLOCK

OCWnx

4-BIT COUNTER

COMPARATOR

DTnL

DTnH

DEAD TIME

PRE-SCALER

DTPSn

DTn I/O REGISTER

DATA BUS (8-bit)

TCCRnB REGISTER

PWM1X

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zero. The outputs OC1x and OC1x are inverted, if the PWM Inversion Mode bit PWM1X is set.

This will also cause both outputs to be high during the dead time.

The length of the counting period is user adjusta ble by select ing th e dead t ime pres caler settin g

by using the DTPS11:10 control bits, and selecting then the dead time value in I/O register DT1.

The DT1 register consists of two 4-bit fields, DT1H and DT1L that control the dead time periods

of the PWM output and its' complementary output separately in terms of the number of pres-

caled dead time generator clock cycles. Thus the rising edge of OC1x and OC1x can have

different dead time periods as the tno n-over lap / risin g edg e is a djusted by the 4-bit DT 1H value and the

tnon-overlap / falling edge is adjusted by the 4-bit DT1L value.

Figure 12-9. The Complementary Output Pair, COM1x1:0 = 1

12.7 Compare Match Output Unit

The Compare Output Mode (COM1x1:0) bits ha ve two functions. The Wavefor m Generator uses

the COM1x1:0 bits for defining the inverted or non-inverted Waveform Output (OCW1x) at the

next Compare Match. Also, the COM1x1:0 bits control the OC1 x and OC1x pin output source.

Figure 12-10 o n p age 98 shows a simp lifie d schematic of the logic affected by the COM1x1:0 bit

setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. On ly the parts of

the general I/O Port Control Registers (DDR and PORT) that are affected by the COM1x1:0 bits

are shown.

In Normal Mode (non-PWM) the Dead Time Generator is disabled and it is working like a syn-

chronizer: the Output Compare (OC1x) is delayed from the Waveform Output (OCW1x) by one

timer clock cycle. Whereas in Fast PWM Mode and in Phase and Frequency Correct PWM

Mode when the COM1x1:0 bits are set to “01” both the non-inverted and the inverted Output

Compare output are generated, and an user programmable Dead Time delay is inserted for

these complementary output pairs (OC1x a nd OC1x ). The functionality in PWM modes is similar

to Normal mode when any other COM1x1:0 bit setup is used. When referring to the OC1x state,

the reference is for the Output Compare output (OC1x) from the Dead Time Generator, not the

OC1x pin. If a system reset occur, the OC1x is reset to “0”.

OCnx

(COMnx = 1)

tnon-overlap / rising edge tnon-overlap / falling edge

OCnx

OCWnx

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Figure 12-10. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC1x / OC1x) from the

Dead Time Generator if either of the COM1x1:0 bits are set. However, the OC1x pin direction

(input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data

Direction Register bit for the OC1x and OC1x pins (DDR_OC1x and DDR_OC1x) must be set as

output before the OC1x and OC1x values are visible on the pin. The port override function is

independent of the Output Compare mode.

DATA B U S

PORTB0

DDRB0

DDRB1

PORTB1

clkI/O

PORTB2

DDRB2

DDRB3

PORTB3

PORTB4

DDRB4

DDRB5

PORTB5

OC1D

Dead Time

Generator D

OCW1D

clkTn OC1D

Output Compare

Pin Configuration

COM1D1:0

WGM11

OC1OE5:4

OC1B

Dead Time

Generator B

OCW1B

clkTn OC1B

Output Compare

Pin Configuration

COM1B1:0

WGM11

OC1OE3:2

OC1A

Dead Time

Generator A

OCW1A

clkTn OC1A

Output Compare

Pin Configuration

COM1A1:0

WGM11

OC1OE1:0

OC1A

OC1B

OC1D

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The design of the Output Compare Pin Configuration logic allows initializ ation of the OC1x state

before the output is enabled . Note tha t some COM1x1:0 bit settings are reserved for certain

modes of operation. For Output Compare Pin Configurations refer to Table 12-2 on page 100,

Table 12-3 on page 102, Table 12-4 on page 104, Table 12-5 on page 105, Table 12-6 on page

105, and Table 12-7 on page 106.

12.7.1 Compare Output Mode and Waveform Generation

The Waveform Ge ner ator use s the COM1 x1 :0 b its d i ffere ntly in No rma l m ode an d PWM mo des.

For all modes, setting the COM1x1:0 = 0 tells the Waveform Generator that no action on the

OCW1x Output is to be performed on the next Compare Match. For compare ou tput actions in

the non-PWM modes refer to Table 12-8 on page 112. For fast PWM mode, refer to Table 12-9

on page 112, and fo r th e Phase an d Frequ ency Corre ct PWM refer to Ta ble 12 -10 on pa ge 11 3.

A change of the COM1x1:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC1x strobe bits.

12.8 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of waveform generation mode bits (PWM1A, PWM1B, and

WGM11:10) and co mpare ou tput mo de bits ( COM1x1 :0). The Co mpare Output mode b its do n ot

affect the counting sequence , wh ile the Waveform Gene ration m ode bits do. The COM1 x1:0 bits

control whether the PWM output generated should be inverted, non-inverted or complementary.

For non-PWM modes the COM1x1:0 bits control whether the output should be set, cleared, or

toggled at a Compare Match.

12.8.1 Normal Mode The simplest mode of operation is Normal mode (PWM1A/PWM1B = 0), where the counter

counts from BOTTOM to TOP (defined as OCR1C) then restarts from BOTTOM. The OCR1C

defines the TOP value for the counter, hence also its resolution, and allows control of the Com-

pare Match output frequency. In toggle Compare Output Mode the Waveform Output (OCW1x)

is toggled at Compare Match between TCNT1 and OCR1x. In non-inverting Compare Output

Mode the Waveform Output is cleared on the Compare Match. In inverting Compare Output

Mode the Waveform Outp ut is set on Compare Match. The timing diagram for Nor mal mode is

shown in Figure 12-11.

Figure 12-11. Normal Mode, Timing Diagram

TCNTn

OCWnx

(COMnx=1)

OCnx Interrupt Flag Set

1 4

Period 2 3

TOVn Interrupt Flag Set

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The counter value (TCNT1) that is shown a s a histogr am in Fi gure 12-11 is incremented until the

counter value matches the TOP value. The counter is then cleared at the following clock cycle

The diagram includes the Waveform Output (OCW1x) in toggle Compare Mode. The small hori-

zontal line marks on the TCNT1 slopes represent Compare Matches between OCR1x and

TCNT1.

The Timer/Counter Overflo w Flag (TOV1) is set in the same clock cycle as the TCNT1 becom es

zero. The TOV1 Flag in this case behaves like a 11th bit, except that it is only set, not cleared.

However, combined with the timer overflow interrupt, that automatically clears the TOV1 Flag,

the timer resolution can be increased by software. There are no special cases to consider in the

Normal mode, a new counter value can be written anytime.

The Output Compa re Unit can be used to gene rate interrup ts at some given time. Using the Ou t-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too mu ch of the CPU tim e. For ge ner ating a wavefo rm, th e OCW1 x outp ut can be set to

toggle its logical level on each Compare Match by setting the Compare Output mode bits to tog-

gle mode (COM1x1 :0 = 1). The OC1x value will not be visible on the port pin unless the data

direction for the pin is set to output. The waveform generated will have a maximum frequency of

fOC1x = fclkT1/4 when OCR1C is set to zero. The waveform frequency is defined by the following

equation:

Resolution, RPWM, shows how many bit is required to express the value in the OCR1C register

and it can be calculated using the following equation:

The Output Compare Pin configurations in Normal Mode are described in Table 12-2.

12.8.2 Fast PWM Mode

The fast Pulse Width Modu lation or fast PWM mode (PWM1A/PWM1B = 1 and WGM11:10 = 00)

provides a high frequency PWM waveform generation option. The fast PWM differs from the

other PWM option by its single-slope operation. The counter coun ts from BOTTOM to TOP

(defined as OCR1C) then restarts from BOTTOM. In non-inverting Compare Output mode the

Waveform Output (OCW1x) is cleared on the Compare Match between TCNT1 and OCR1x and

set at BOTTOM. In inverting Compare Output mode, the Waveform Output is set on Compare

Match and cleared at BOTTOM. In comp lementary Compare Outpu t mode the Waveform Outp ut

is cleared on the Comp ar e M atc h an d set at BOTT O M.

Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice

as high as the Phase and Frequency Correct PWM m ode that use dual-slope op eration. This

high frequency makes the fast PWM mode well suited for power regulation, rectification, and

Table 12-2. Output Compare Pin Configurations in Normal Mode

COM1x1 COM1x0 OC1x Pin OC1x Pin

0 0 Disconnected Disconnected

0 1 Disconnected OC1x

1 0 Disconnected OC1x

1 1 Disconnected OC1x

fOC1x fclkT1

21OCR1C+

-------------------------------------------=

RPWM log2OCR1C 1+=

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DAC applications. High frequency allows physicall y small sized external components (coils,

capacitors), and therefore reduces total system cost.

The timing diagram for the fast PWM mode is shown in Figure 12-12. The counter is incre-

mented until the counter value matches the TOP value. The counter is then cleared at the

following timer clock cycle. The TCNT1 value is in the timing diagram shown as a histogram for

illustrating the single-slope operation. The diagram includes the Waveform Output in non-

inverted and inverted Com pare Output modes. The small horizontal line marks o n the TCNT1

slopes represent Compare Matches between OCR1x and TCNT1.

Figure 12-12. Fast PWM Mode, Timing Diagram

The Timer/Coun ter Over flo w Flag (TOV1) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows gen eration of PWM waveforms on the OC1x pins.

Setting the COM1x1:0 bits to two will produce a non-inverted PWM and setting the COM1x1:0 to

three will produce an inverted PWM output. Setting th e COM1x1:0 bits to on e will enable com-

plementary Compare Output mode and produce both the non-inverted (OC1x) and inverted

output (OC1x). The actual value will only be visible on the port pin if the data direction for the

port pin is set as output. The PWM waveform is generated by setting (or clearing) the Waveforn

Output (OCW1x) at the Compare M atch between OCR1x and TCNT1, and clearing (or setting)

the Waveform Output at the timer clock cycle the counter is cleared (changes from TOP to

BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the number of steps in single-slope operation. The value of N equals

either to the TOP value.

The extreme values for the OCR1C Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR1C is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR1C equal to MAX will result

TCNTn

OCRnx Update and

TOVn Interrupt Flag Set

Period

2 3

OCWnx

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCRnx Interrupt Flag Set

4 5 6 7

fOCnxPWM fclkT1

-------------=

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in a constantly high or low output (depending on the polarity of the output set by the COM1x1:0

bits.)

A frequency (with 50 % duty cycle) wavefo rm output in fast PWM mode can be achieved by set-

ting the Waveform Output (OCW1x) to toggle its logical level on each Compare Match

(COM1x1:0 = 1). The waveform generated will have a maximum frequency of fOC1 = fclkT1/4 when

OCR1C is set to three.

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator, if either of the COM1x1 :0 bits ar e se t an d th e Data Direction Register

bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the

actual value from the port register will be visible on the port pin. The Output Compare Pin config-

urations are described in Table 12-3.

12.8.3 Phase and Frequency Correct PWM Mode

The Phase and Frequ ency Correct PWM Mode (PWM1A/PWM1B = 1 and WGM11 :10 = 01) pro-

vides a high reso lution Phase and Frequency Correct PWM waveform generation option. Th e

Phase and Frequency Correct PWM mode is based on a dual-slope operation. The counter

counts repeatedly from BOTTOM to TOP (defined as OCR1C) and then from TOP to BOTTOM.

In non-inverting Compare Output Mode the Waveform Output (OCW1x) is cleared on the Com-

pare Match betwee n TCNT1 and OCR1x while upcou nting, and set o n the Compare M atch while

down-counting. In inverting Output Compare mode, the operation is inverted. In complementary

Compare Output Mode, the Waveform Ouput is cleared on the Compare Match and set at BOT-

TOM. The dual-slope operation has lower maximum operation frequency than single slope

operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes

are preferred for motor control applications.

The timing diagr am fo r th e Phase and Frequen cy Co rr e ct PWM mode is sh own on Figure 12-13

in which the TCNT1 value is shown as a histogram for illustrating the dual-slope operation. The

counter is incremented until the counter value matches TOP. When the counter reaches TOP, it

changes the count direction. The TCNT1 value will be equal to TOP for one timer clock cycle.

The diagram includes the Waveform Output (OCW1x) in non-inverted and inverted Compare

Output Mode. The small horizontal line marks on the TCNT1 slopes represent Compare

Matches between OCR1x and TCNT1.

Table 12-3. Output Compare Pin Configurations in Fast PWM Mode

COM1x1 COM1x0 OC1x Pin OC1x Pin

0 0 Disconnected Disconnected

0 1 OC1x OC1x

1 0 Disconnected OC1x

1 1 Disconnected OC1x

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Figure 12-13. Phase and Frequency Correct PWM Mode, Timing Diagram

The Timer/Counter Ove rflow Flag (TOV1) is set each time the counter reaches BOTTOM . The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In the Phase and Fre quency Correct PWM mode, the com pare unit allows generation of PW M

waveforms on the OC1x pins. Setting the COM1x1:0 bits to two will produce a non-inverted

PWM and setting the COM1x1:0 to three will produce an inverted PWM output. Setting the

COM1A1:0 bits to one will enable complementary Compare Ou tput mode and produce both the

non-inverted (OC1x) and inverte d output (OC1x). The actual values will only be visible on the

port pin if the data direction fo r th e port pin is set as ou tput. Th e PWM wa vefor m is gene ra te d by

clearing (or setting ) the Wavefor m Output (OCW1x) at th e Compar e Match betwe en OCR1 x and

TCNT1 when the counter incr ements, and setting (or clearing) the Waveform Output at Compare

Match when the counter decrements. The PWM frequency for the output when using the Phase

and Frequency Correct PWM can be calcu lated by the following equation:

The N variable represents the nu mber of steps in du al-slo pe oper ation . The value of N equals to

the TOP value.

The extreme values for the OCR1C Register represent special cases when generating a PWM

waveform output in the Phase and Frequency Correct PWM mode. If the OCR1C is set equal to

BOTTOM, the output will be continuously low and if set equal to MAX the output will be continu-

ously high for non-inve rted PWM mode. For inverted PWM the output will ha ve the opposite

logic values.

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator, if either of the COM1x1 :0 bits ar e se t an d th e Data Direction Register

bits for the OC1X and OC1X pins are set as an output. If the COM1x1:0 bits are cleared, the

TOVn Interrupt Flag Set

OCnx Interrupt Flag Set

1 2 3

TCNTn

Period

OCWnx

(COMnx = 2)

(COMnx = 3)

OCRnx Update

fOCnxPCPWM fclkT1

-------------=

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actual value from the port register will be visible on the port pin. The configurations of the Output

Compare Pins are descr ib ed in Table 12-4.

12.8.4 PWM6 Mode The PWM6 Mode (PWM1A = 1, WGM11:10 = 1X) provide PWM waveform generation option

e.g. for controlling Brushless DC (BLDC) motors. In the PW M6 Mode the OCR1A Register con-

trols all six Output Compare waveforms as the same Waveform Output (OCW1A) from the

Waform Generator is used for gene rating all waveforms. The PWM6 Mod e also prov ides an Out-

put Compare Override Enable Register (OC1OE) that can be used with an instant response for

disabling or enabling the Output Compare pins. If the Output Compare Override Enable bit is

cleared, the actual value from the port register will be visible on the port pin.

The PWM6 Mode provides two counter operation modes, a single-slope operation and a dual-

slope operation. If the single-slope operation is selected (the WGM10 bit is set to 0), the counter

counts from BOTTOM to TOP (defined as OCR1C) then restart from BOTT OM like in Fast PWM

Mode. The PWM waveform is generated by setting (or clearing) the Waveforn Output (OCW1A)

at the Compare Match between OCR1A and TCNT1, and clearing (or setting) th e Waveform

Output at the timer clock cycle the counter is cleared (changes from TOP to BO TTOM). The

Timer/Counter Overflow Flag (TOV1) is set each t ime the counter reac hes the TOP and, if the

interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

Whereas, if the dual-slope operation is selected (the WGM10 bit is set to 1), the counter counts

repeatedly from BOTTOM to TO P (defined as OCR1C) and then from TOP to BOTTOM like in

Phase and Frequency Correct PWM Mode. The PWM waveform is generated by setting (or

clearing) the Waveforn Output (OCW1A) at the Compare Match between OCR1A and TCNT1

when the counter increments, and clearing (or setting) the Waveform Output at the he Compare

Match between OCR1A and TCNT 1 when the coun ter decrements. The Time r/Counter Overflow

Flag (TOV1) is set each time the counter reaches the BOTTOM and, if the interrupt is enabled,

the interrupt handler routine can be used for updating the compare value.

The timing diagram for the PWM6 Mode in single-slope operation when the COM1A1:0 bits are

set to “10” is shown in Figure 1 2- 14. Th e counter is incremen ted until the co unter valu e match es

the TOP value. The counter is then cleared at the following timer clock cycle. The TCNT1 value

is in the timing diagram shown as a histogram for illustrating the single-slope operation. The tim-

ing diagram includes Output Compare pins OC1A and OC1A, and the corresponding Output

Compare Override Enable bits (OC1OE1:OC1OE0).

Table 12-4. Output Compare pin configura tions in Phase and Frequency Correct PWM Mode

COM1x1 COM1x0 OC1x Pin OC1x Pin

0 0 Disconnected Disconnected

0 1 OC1x OC1x

1 0 Disconnected OC1x

1 1 Disconnected OC1x

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Figure 12-14. PWM6 Mode, Single-slope Operation, Timing Diagram

The general I/O port function is overridden by the Output Compare value (OC1x / OC1x) from

the Dead Time Generator if either of the COM1x1:0 b its are set . The Output Compare p ins can

also be overriden by the Output Compare Override Enable bits OC1OE5:OC1O E0. If an Over-

ride Enable bit is cleared, the actual value from the port register will be visible on the port pin

and, if the Override Enable bit is set, the Output Compare pin is allowed to be connected on the

port pin. The Output Compare Pin configurations are described in Table 12-5, Tabl e 12-6 and

Table 12-7.

Table 12-5. Configuration of Output Compar e Pins OC1A and OC1A in PWM6 Mode

COM1A1 COM1A0 OC1A Pin (PB0) OC1A Pin (PB1)

0 0 Disconnected Disconnected

01OC1A • OC1OE0 OC1A • OC1OE1

10OC1A • OC1OE0 OC1A • OC1OE1

11OC1A • OC1OE0 OC1A • OC1OE1

Table 12-6. Configuration of Output Compar e Pins OC1B and OC1B in PWM6 Mode

COM1B1 COM1B0 OC1B Pin (PB2) OC1B Pin (PB3)

0 0 Disconnected Disconnected

01OC1A • OC1OE2 OC1A • OC1OE3

10OC1A • OC1OE2 OC1A • OC1OE3

11OC1A • OC1OE2 OC1A • OC1OE3

TCNT1

OC1A Pin

OC1B Pin

OC1D Pin

OC1OE0

OC1OE1

OC1OE2

OC1OE3

OC1OE4

OC1OE5

OCW1A

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12.9 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the tim er clock (clkT1) is therefore shown as a

clock enable sign al in the following figures. Th e figures include information on whe n Interrupt

Flags are set.

Figure 12-15 contains timing data for basic Timer/Counter operation. The figure shows the count

sequence close to the MAX value in all modes other than Phase and Frequency Correct PWM

Mode.

Figure 12-15. Timer/Counter Timing Diagram, no Prescaling

Figure 12-16 shows the same timing data, but with the prescaler enabled, in all modes other

than Phase and Frequ ency Correct PWM Mode.

Figure 12-16. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8)

Figure 12-17 shows the setting of OCF1A, OCF1B and OCF1D in all modes.

Table 12-7. Configuration of Output Compar e Pins OC1D and OC1D in PWM6 Mode

COM1D1 COM1D0 OC1D Pin (PB4) OC1D Pin (PB5)

0 0 Disconnected Disconnected

01OC1A • OC1OE4 OC1A • OC1OE5

10OC1A • OC1OE4 OC1A • OC1OE5

11OC1A • OC1OE4 OC1A • OC1OE5

clkTn

(clkPCK

/1)

TOVn

clkPCK

TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1

TOVn

TCNTn TOP - 1 TOP BOTTOM BOTTOM + 1

clkPCK

clkTn

(clk

PCK

/8)

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Figure 12-17. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (fclkT1/8)

Figure 12-18 shows the setting of TOV1 in Phase and Frequency Correct PWM Mode.

Figure 12-18. Timer/Counter Timing Diagram, with Prescaler (fclkT1/8)

12.10 Fault Protection Unit

The Timer/Counter1 incorporates a Fault Protection unit, which can be set to disable the PWM

output pins when an external event is triggered. The external signal indicating an event can be

applied via the external interrupt INT0 pin or, alternatively, via the analog-comparator unit. The

Fault Protection unit is illustrated in Figure 12-19. Th e elements of the block di agram that are not

directly a part of the Fault Protection unit are gray shaded.

Figure 12-19. Fault Protection Unit Block Diagram

Fault Protection mode is enabled by setting the Fault Protection Enable (FPEN1) bit and trig-

gered by a change in logic level at external interrupt pin (INT0). Alternatively, fault protection

mode can be triggered by the Analog Comparator Output (ACO).

When Fault Protection is triggered, the COM1 x bits are cleared, Output Co mparators are discon-

nected from the PWM output pins an d PORTB register bits are connected to the PWM output

OCFnx

OCRnx

TCNTn

OCRnx Value

OCRnx - 1 OCRnx OCRnx + 1 OCRnx + 2

clkPCK

clkTn

(clkPCK

/8)

TOVn

TCNTn BOTTOM + 1 BOTTOM + 1 BOTTOM BOTTOM + 1

clk

PCK

clk

(clkPCK

/8)

Analog

Comparator Noise

Canceler

INT0

Edge

Detector

FPAC1 FPNC1 FPES1

ACO* FPEN1

Timer/Counter1

FAULT_PROTECTION (Int. Req.)

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pins. The Fault Protection Enable (FPEN1) is automatically cleared at the same system clock as

the COM1nx bits are cleared.

If the Fault Protection Interrupt Ena ble bit (FPIE1) is set, a Fault Protection interrupt is generated

and the FPEN1 bit is cleared. Alternatively the FPEN1 bit can be polled by software to figure out

when the Timer/Counte r has entered to Fault Protection mode.

12.10.1 Fault Protection Trigger Source

The main trigger source for the Fault Protection unit is the external interrupt pin (INT0). Alterna-

tively the Analog Comparator output can be used as trigger source for the Fault Protection unit.

The Analog Comparator is selected as trigger source by setting the Fault Protection Analog

Comparator (FPAC1) bit in the Timer/Counter1 Control Register (TCCR1D). Be aware that

changing trigger source can trigger a Fault Protection mode. Therefore it is recommended to

clear the FPF1 flag after changing trigger source, setting edge detector or enabling the Fault

Protection.

Both the external interrupt pin (INT0) and the Analog Comparator output (ACO) inputs are sam-

pled using the same technique as with the T0 pin (see Figure 11-3 on page 74). The edge

detectors are also identical but when the noise can celer is enabled additional logic is a ctivated

before the edge de tector, increasing the propagation delay with four system clock cycles.

An Input Capture can also be triggered by software by controlling the port of the INT0 pin.

12.10.2 Noise Canceler

The noise canceler uses a simp le digital filter ing te chnique to improve noise immunity. Consecu-

tive samples are monitored in a pi peline four units de ep. The signal g oing to the ed ge detecter is

allowed to change only when all four samples are equal.

The noise cancele r is enabled by setting the F ault Protection Noise Canceler (FPNC1) bit in

Timer/Counter1 Control Register D (TCCR1D). Whe n enab led, the n oise cance ler introduces an

additional delay of four system clock cycles to a change applied to the input.

The noise canceler uses the system clock directly and is therefore not affected by the prescaler.

12.11 Accessing 10-Bit Registers

If 10-bit values are written to the TCNT1 and OCR1A/B/C/D registers, the 1 0-bit registers can be

byte accessed by the AVR CPU via the 8-bit data bus using two read or write operations. The

10-bit registers h ave a comm on 2- bit Timer/Cou nter1 High Byte Register (TC1H) that is used for

temporary storing of the two MSBs of the 10-bit access. The same TC1H register is shared

between all 10-bit registers. Accessing the low byte triggers the 10-bit read or write operation.

When the low byte of a 10-bit register is written by the CPU, the high byte stored in the TC1H

When the low byte of a 10-bit register is read by the CPU, the high byte of the 10-bit register is

copied into the TC1H register in the same clock cycle as the low byte is read.

To do a 10-bit write, the high byte must be written to the TC 1H register before the low byte is

written. For a 10-bit read, the low byte must be read before the high byte.

12.11.1 Reusing the temporary high byte register

If writing to more than one 10-bit reg ister where the high byte is the same for all r egisters written,

then the high byte only needs to be written once. However, note that the same rule of atomic

operation described previou sly also ap plies in this case.

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12.11.2 Code Examples

The following code examples show how to access the 10-bit tim er registers assuming that no

interrupts updates the TC1H register. The same principle can be used directly for accessing the

OCR1A/B/C/D registers.

Note: See “Code Examples” on page 6 .

The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.

It is important to notice that accessing 10-bit registers are atomic operations. If an interrupt

occurs between the two instructions accessing the 10-bit register, and the interrupt code

updates the TC1H reg ister by a ccessing th e sam e or a ny other o f the 1 0-bit tim er re giste rs, then

the result of the access outside the interrupt will be corrupted. Therefore, when both the main

code and the inte rrupt code upd ate the TC1 H regi ster, the ma in code must disable the interr upts

during the 16-bit access.

Assembly Code Example

...

; Set TCNT1 to 0x01FF

ldi r17,0x01

ldi r16,0xFF

out TC1H,r17

out TCNT1,r16

; Read TCNT1 into r17:r16

in r16,TCNT1

in r17,TC1H

...

C Code Example

unsigned int i;

...

/* Set TCNT1 to 0x01FF */

TC1H = 0x01;

TCNT1 = 0xFF;

/* Read TCNT1 into i */

i = TCNT1;

i |= ((unsigned int)TC1H << 8);

...

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The following code examples show how to do an atomic read of the TCNT1 register contents.

Reading any of the OCR 1A/ B/C/ D regi st er s can be do n e by us ing the sam e principle.

Note: See “Code Examples” on page 6 .

The assembly code examp le returns the TCNT1 value in the r17:r16 register pair.

Assembly Code Example

TIM1_ReadTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Read TCNT1 into r17:r16

in r16,TCNT1

in r17,TC1H

; Restore global interrupt flag

out SREG,r18

ret

C Code Example

unsigned int TIM1_ReadTCNT1( void )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Read TCNT1 into i */

i = TCNT1;

i |= ((unsigned int)TC1H << 8);

/* Restore global interrupt flag

SREG = sreg;

return i;

}

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The following code examples show how to do an atomic write of the TCNT1 register contents.

Writing any of the OCR1A/ B/C/ D registers can be done by using the same principle.

Note: See “Code Examples” on page 6 .

The assembly code example requires that the r17:r16 register pair contains the value to be writ-

ten to TCNT1.

Assembly Code Example

TIM1_WriteTCNT1:

; Save global interrupt flag

in r18,SREG

; Disable interrupts

cli

; Set TCNT1 to r17:r16

out TC1H,r17

out TCNT1,r16

; Restore global interrupt flag

out SREG,r18

ret

C Code Example

void TIM1_WriteTCNT1( unsigned int i )

{

unsigned char sreg;

unsigned int i;

/* Save global interrupt flag */

sreg = SREG;

/* Disable interrupts */

_CLI();

/* Set TCNT1 to i */

TC1H = (i >> 8);

TCNT1 = (unsigned char)i;

/* Restore global interrupt flag */

SREG = sreg;

}

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12.12 Register Description

12.12.1 TCCR1A – Timer/Counter1 Control Register A

• Bits 7,6 – COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1A) and the connection of the

Output Compare pin (OC1A). If one or both of the COM1A1:0 bits are set, the OC1A output

overrides the norm al port fun ctionality of the I/O pin it is connected to. The complementary

OC1B output is connected only in PWM modes when the COM1A1:0 bits are set to “01”. Note

that the Data Direction Register (DDR) bit co rresponding to the OC1A and OC1A pins must be

set in order to enable the output driver.

The function of the COM1A1:0 bits depends on the PWM1A, WGM10 and WGM11 bit settings.

Table 1 2-8 shows the COM1A1:0 bit functionality when the PWM1A bit is set to Normal Mode

(non-PWM).

Table 12-9 shows the COM1A1:0 bit functionality when the PWM1A, WGM10 and WGM11 bits

are set to fast PWM mode.

Bit 76543210

0x30 (0x50) COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B TCCR1A

Read/Write R/W R/W R/W R/W W W R/W R/W

Initial value00000000

Table 12-8. Compare Output Mode, Nor mal Mode (non-PWM)

COM1A1:0 OCW1A Behaviour OC1A Pin OC1A Pin

00 Normal port operation. Disconnected Disconnected

01 Toggle on Compare Match. Conn ected Disconnected

10 Clear on Compare Match. Connected Disconnected

11 Set on Compare Match. Connected Disconnected

Table 12-9. Compare Output Mode, Fast PWM Mode

COM1A1:0 OCW1A Behaviour OC1A OC1A

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match.

Set when TCNT1 = 0x000. Connected Connected

10 Cleared on Compare Match.

Set when TCNT1 = 0x000. Connected Disconnected

11 Set on Compare Match.

Cleared when TCNT1 = 0x000. Connected Disconnected

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Table 12-10 show s the COM1A1 :0 bi t func tiona lity wh en the PWM1A, WGM10 and WGM11 bits

are set to Phase and Frequency Correct PWM Mode.

Table 12-11 show s the COM1A1 :0 bi t func tiona lity wh en the PWM1A, WGM10 and WGM11 bits

are set to single-slope PWM6 Mode. In the PWM6 Mode the same Waveform Output (OCW1A)

is used for generating all waveforms and the Output Compare values OC1A and OC1A are con-

nected on thw all OC1x and OC1x pins as described below.

Table 12-12 show s the COM1A1 :0 bi t func tiona lity wh en the PWM1A, WGM10 and WGM11 bits

are set to dual-slope PWM6 Mode.I

Bits COM1A1 and COM1A0 are shadowed in TCCR1C. Writing to bits COM1A1 and COM1A0

will also change bits COM1A1S and COM1A0S in TCCR1C. Similary, changes written to bits

COM1A1S and COM1A0S in TCCR1C will show here. See “TCCR1C – Timer/Counter1 Control

Table 12-10. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1A1:0 OCW1A Behaviour OC1A Pin OC1A Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Connected

10 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Disconnected

11 Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting. Connected Disconnected

Table 12-11. Compare Output Mode, Single-Slope PWM6 Mode

COM1A1:0 OCW1A Behaviour OC1x Pin OC1x Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match.

Set when TCNT1 = 0x000. OC1A OC1A

10 Cleared on Compare Match.

Set when TCNT1 = 0x000. OC1A OC1A

11 Set on Compare Match.

Cleared when TCNT1 = 0x000. OC1A OC1A

Table 12-12. Compare Output Mode, Dual-Slope PWM6 Mode

COM1A1:0 OCW1A Behaviour OC1x Pin OC1x Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. OC1A OC1A

10 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. OC1A OC1A

11 Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting. OC1A OC1A

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• Bits 5,4 – COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1B) and the connection of the

Output Compare pin (OC1B). If one or both of the COM1B1:0 bits are set, the OC1B output

overrides the norm al port fun ctionality of the I/O pin it is connected to. The complementary

OC1B output is connected only in PWM modes when the COM1B1:0 bits are set to “01”. Note

that the Data Direction Register (DDR) bit corresponding to the OC1B pin must be set in order to

enable the output driver.

The function of the COM1B1:0 bits depends on the PWM1B and WGM11:10 bit settings. Table

12-13 shows the COM1B1:0 bit functionality when the PWM1B bit is set to Normal Mode (non-

PWM).

Table 1 2-14 shows the COM1B1:0 bit functionality when the PWM1B and WGM11:10 bits are

set to Fast PWM Mode.

Table 12-15 shows the COM1B1:0 bit functionality when the PWM1B and WGM11:10 bits are

set to Phase and Frequency Correct PWM Mode.

Bits COM1B1 and COM1B0 are shadowed in TCCR1C. Writing to bits COM1B1 and COM1B0

will also change bits COM1B1S and COM1B0S in TCCR1C. Similary, changes written to bits

Table 12-13. Compare Output Mode, Normal Mode (non-PWM)

COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin

00 Normal port operation. Disconnected Disconnected

01 Toggle on Compare Match. Connected Disconnected

10 Clear on Compare Match. Connected Disconnected

11 Set on Compare Match. Connected Disconnected

Table 12-14. Compare Output Mode, Fast PWM Mode

COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match.

Set when TCNT1 = 0x000. Connected Connected

10 Cleared on Compare Match.

Set when TCNT1 = 0x000. Connected Disconnected

11 Set on Compare Match.

Cleared when TCNT1 = 0x000. Connected Disconnected

Table 12-15. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1B1:0 OCW1B Behaviour OC1B Pin OC1B Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Connected

10 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Disconnected

11 Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting. Connected Disconnected

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COM1B1S and COM1B0S in TCCR1C will show here. See “TCCR1C – Timer/Counter1 Control

• Bit 3 – FOC1A: Force Output Compare Match 1A

The FOC1A bit is only active when the PWM1A bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1A) and the Out-

put Compare pin (OC1A) according to the values already set in COM1A1 an d COM1A0. If

COM1A1 and COM1A0 written in the same cycle as FOC1A, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

value. The automatic action progr ammed in COM1A1 and COM1A0 takes pla ce as if a compa re

match had occurred, but no interrupt is generated.

The FOC1A bit always reads zero.

• Bit 2 – FOC1B: Force Output Compare Match 1B

The FOC1B bit is only active when the PWM1B bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1B) and the Out-

put Compare pin (OC1B) according to the values already set in COM1B1 an d COM1B0. If

COM1B1 and COM1B0 written in the same cycle as FOC1B, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

value. The automatic action progr ammed in COM1B1 and COM1B0 takes pla ce as if a compa re

match had occurred, but no interrupt is generated.

The FOC1B bit always reads zero.

• Bit 1 – PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A

• Bit 0 – PWM1B: Pulse Width Modulator B Enable

When set (one) this bit enables PWM mode based on comparator OCR1B.

12.12.2 TCCR1B – Timer/Counter1 Control Register B

• Bit 7 – PWM1X : PWM Inversion Mode

When this bit is set (one), the PWM Inversion Mode is selected and the Dead Time Generator

outputs, OC1x and OC1x are inverted.

• Bit 6 – PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter1 prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

• Bits 5,4 – DTPS11, DTPS10: Dead Time Prescaler Bits

The Timer/Counter1 Control Register B is a 8-bit read/write register.

Bit 76543210

0x2F (0x4F) PWM1X PSR1 DTPS11 DTPS10 CS13 CS12 CS11 CS10 TCCR1B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the

Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can

be generated. The Dead Time prescaler is controlled by two bits DTPS11 and DTPS10 from the

Dead Time Prescaler register. These bits define the division factor of the Dead Time prescaler.

The division factors are given in Table 12-16.

• Bits 3:0 – CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

The Stop condition provides a Timer Enable/Disable function.

Table 12-16. Division factors of the Dead Time prescaler

DTPS11 DTPS10 Prescaler divides the T/C1 clock by

0 0 1x (no division)

012x

104x

118x

Table 12-17. Timer/Counter1 Prescaler Select

CS13 CS12 CS11 CS10 Asyn chron ous Cloc king Mode Synchronous Clocking Mode

0000T/C1 stopped T/C1 stopped

0001PCK CK

0010PCK/2 CK/2

0011PCK/4 CK/4

0100PCK/8 CK/8

0101PCK/16 CK/16

0110PCK/32 CK/32

0111PCK/64 CK/64

1000PCK/128 CK/128

1001PCK/256 CK/256

1010PCK/512 CK/512

1011PCK/1024 CK/1024

1100PCK/2048 CK/2048

1101PCK/4096 CK/4096

1110PCK/8192 CK/8192

1111PCK/16384 CK/16384

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12.12.3 TCCR1C – Timer/Counter1 Control Register C

• Bits 7,6 – COM1A1S, COM1A0S: Comparator A Output Mode, Shadow Bits 1 and 0

These are shadow bits of COM1A1 and COM1A0 in TCCR1A. Writing to bits COM1A1S and

COM1A0S will also change bits COM1A1 and COM1A0 in TCCR1A. Similary, changes written

to bits COM1A1 and COM1A0 in TCCR1A will show here.

See “TCCR1A – Timer/Counter1 Control Register A” on page 112 for information on bit usage.

• Bits 5,4 – COM1B1S, COM1B0S: Comparator B Output Mode, Shadow Bits 1 and 0

These are shadow bits of COM1B1 and COM1B0 in TCCR1A. Writing to bits COM1B1S and

COM1B0S will also change bits COM1B1 and COM1B0 in TCCR1A. Similary, changes written

to bits COM1B1 and COM1B0 in TCCR1A will show here.

See “TCCR1A – Timer/Counter1 Control Register A” on page 112 for information on bit usage.

• Bits 3,2 – COM1D1, COM1D0: Comparator D Output Mode, Bits 1 and 0

These bits control the behaviour of the Waveform Output (OCW1D) and the connection of the

Output Compare pin (OC1D). If on e or both of the COM1D1:0 bits are set, the OC1D output

overrides the norm al port fun ctionality of the I/O pin it is connected to. The complementary

OC1D output is connected only in PWM modes when the COM1D1 :0 bits are set to “01”. Note

that the Data Direction Register (DDR) bit corresponding to the OC1D pin m ust be se t in ord er to

enable the output driver.

The function of the COM1D1: 0 bits depends on the PWM1D and WGM11:10 bit settings. Table

12-18 shows the COM1D1 :0 bit functionality when the PWM1D bit is set to a Normal M ode (non-

PWM).

Table 12-19 shows the COM1D1:0 bit functionality when the PWM1D and WGM11:10 bits are

set to Fast PWM Mode.

Bit 76543210

0x27 (0x47) COM1A1

SCOM1A0

SCOM1B1

SCOM1B0

SCOM1D1 COM1D0 FOC1D PWM1D TCCR1C

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Table 12-18. Compare Output Mode, Normal Mode (non-PWM)

COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin

00 Normal port operation. Disconnected Disconnected

01 Toggle on Compare Match. Connected Disconnected

10 Clear on Compare Match. Connected Disconnected

11 Set on Compare Match. Connected Disconnected

Table 12-19. Compare Output Mode, Fast PWM Mode

COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match. Set when TCNT1=0x000. Connected Connected

10 Cleared on Compare Match. Set when TCNT1=0x000. Connected Disconnected

11 Set on Compare Match. Cleared when TCNT1=0x000. Connected Disconnected

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Table 12-20 shows the COM1D1:0 bit fu nctionality when the PWM 1D and WGM11:10 bits are

set to Phase and Frequency Correct PWM Mode.

• Bit 1 – FOC1D: Force Output Compare Match 1D

The FOC1D bit is only active when the PWM1D bit specify a non-PWM mode.

Writing a logical one to this bit forces a change in the Waveform Output (OCW1D) and the Out-

put Compare pin (OC1D) according to the values already set in COM1D1 and COM1D0. If

COM1D1 and COM1D0 written in the same cycle as FOC1D, the new settings will be used. The

Force Output Compare bit can be used to change the output pin value regardless of the timer

value. The automatic action prog rammed in COM1D1 an d COM1D0 takes place as if a compa re

match had occurred, but no interrupt is generated. The FOC1D bit is always read as zero.

• Bit 0 – PWM1D: Pulse Width Modulator D Enable

When set (one) this bit enables PWM mode based on comparator OCR1D.

12.12.4 TCCR1D – Timer/Counter1 Control Register D

• Bit 7 – FPIE1: Fault Protection Interrupt Enable

Setting this bit (to one) enables the Fault Protection Interrupt.

• Bit 6 – FPEN1: Fault Protection Mode Enable

Setting this bit (to one) activates the Fault Protection Mode.

• Bit 5 – FPNC1: Fault Protection Noise Canceler

Setting this bit activa tes the Fault Protection Noise Canceler. When the noise canceler is acti-

vated, the input from the Fault Protection Pin (INT0) is filtered. The filter function requires four

successive equal valued samples of the INT0 pin for changing its output. The Fa ult Protection is

therefore delayed by four Oscillator cycles when the noise canceler is enabled.

• Bit 4 – FPES1: Fault Protection Edge Select

This bit selects which edge on the Fault Protection pin (INT0) is used to trigger a fault event.

When the FPES1 bit is written to zero, a falling (negative) edge is used as trigger, and when the

FPES1 bit is written to one, a rising (positive) edge will trigger the fault.

Table 12-20. Compare Output Mode, Phase and Frequency Correct PWM Mode

COM1D1:0 OCW1D Behaviour OC1D Pin OC1D Pin

00 Normal port operation. Disconnected Disconnected

01 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Connected

10 Cleared on Compare Match when up-counting.

Set on Compare Match when down-counting. Connected Disconnected

11 Set on Compare Match when up-counting.

Cleared on Compare Match when down-counting. Connected Disconnected

Bit 76543210

0x26 (0x46) FPIE1 FPEN1 FPNC1 FPES1 FPAC1 FPF1 WGM11 WGM10 TCCR1D

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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• Bit 3 – FPAC1: Fault Protection Analog Comparator Enable

When written logic one, this bit enables the Fault Protection function in Timer/Counter1 to be

triggered by the Analog Comparator. The comparator output is in this case directly connected to

the Fault Protection front-end logic, making the comparator utilize the noise canceler and edge

select features of the Timer /Counter1 Fault Pr otection interrupt. When writte n logic zero, no con-

nection between the Analog Comparator and the Fault Pro tection function exists. To make the

comparator trigger the Timer/Counter1 Fault Protection interrupt, the FPIE1 bit in the

Timer/Counter1 Control Register D (TCCR1D) must be set.

• Bit 2 – FPF1: Fault Protection Interrupt Flag

When the FPIE1 bit is set (one), the Fault Protection Interrupt is enabled. Activity on the pin will

cause an interrupt request eve n, if the Fault Protection p in is conf igured as a n output. T he corr e-

sponding interrupt of F ault Protection Interrupt Request is exe cuted from the Fault Protection

Interrupt Vector. The bit FPF1 is cleared by hardwa re when executing the co rresponding inter-

rupt handling vector. Alternatively, FPF1 is cleared after a sy nchronization clo ck cycle by wr itin g

a logical one to the fla g. When the SREG I-bit, FPIE1 and FPF1 are se t, the Fault Interrupt is

executed.

• Bits 1:0 – WGM11, WGM10: Waveform Generation Mode Bits

These bits together with the PWM1A/PWM1B bits control the counting sequence of the counter

and the type of waveform generation to be used, as shown in Table 12-2 1. Modes of operation

supported by the Timer/Co unter1 ar e: Normal mode (coun ter), Fast PWM Mode, Phase and Fre-

quency Correct PWM and PWM6 Modes.

12.12.5 TCCR1E – Timer/Counter1 Control Register E

• Bits 7:6 – Res: Reserved Bits

These bits are reserved and always read zero.

• Bits 5:0 – OC1OE5:OC1OE0: Output Compare Override Enable Bits

These bits are th e Ouput Compare Override Enable bits that are used to connect or disconnect

the Output Compare Pins in PWM6 Modes with an instant response on the corresponding Out-

put Compare Pins. The actual value from the port register will be visible on the port pin, when

Table 12-21. Waveform Generation Mode Bit Description

PWM1A/

PWM1B WGM11:10 Timer/Counter

Mode of Operation TOP Update

OCR1x at Set TOV1

Flag at

0 XX Normal OCR1C Immediate TOP

1 00 Fast PWM OCR1C TOP TOP

1 01 Phase & Frequency Correct PWM OCR1C BOTTOM BOTTOM

1 10 PWM6 / Single-slope OCR1C TOP TOP

1 11 PWM6 / Dual-slope OCR1C BOTTOM BOTTOM

Bit 76543210

0x00 (0x20) - - OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 TCCR1E

Read/Write R R R/W R/W R/W R/W R/W R/W

Initial value00000000

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the Output Compare Override En able Bit is cleared. Table 12-22 shows the Ou tput Compare

Override Enable Bits and their corresponding Output Compare pins.

12.12.6 PLLCSR – PLL Control and Status Register

• Bit 7 – LSM: Low Speed Mode

The Low Speed mode is set, if the LSM bit is written to one. Then the fast peripheral clock is

scaled down to 32 MHz. The Low Speed Mode must be set, if the supply voltage is below 2.7

volts, because the Timer/Counter1 is not running fast enough on low voltage levels. It is recom-

mended that the Timer/Counter1 is stopped whenever the LSM bit is changed.

Note, that LSM can not be set if PLL CLK is used as a system clock.

• Bit 6:3 – Res : Reserved Bits

These bits are reserved and always read zero.

• Bit 2 – PCKE: PCK Enable

The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock

mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as a

Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and

system clock CK is used as Timer/Counter1 clock source. It is safe to set this bit only when the

PLL is locked i.e the PLOCK bit is 1. Note that the PCKE bit can be set only, if the PLL has been

enabled earlier. The PLL is enabled when the CKSEL fuse has been programmed to 0x0001

(the PLL clock mode is selected) or the PLLE bit has been set to one.

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL

reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be

ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,

before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is

recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.

Table 12-22. Outpu t C om p ar e Ov er rid e Ena b le Bits vs. Output Compare Pins

Output CompareOverride Enable Bit Output Compare Output Output Compare Pin

OC1OE0 OC1A PB0

OC1OE1 OC1A PB1

OC1OE2 OC1B PB2

OC1OE3 OC1B PB3

OC1OE4 OC1D PB4

OC1OE5 OC1D PB5

Bit 76543210

0x29 (0x49) LSM----PCKEPLLEPLOCKPLLCSR

Read/WriteR/WRRRRR/WR/WR

Initial value0000000/10

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12.12.7 TCNT1 – Timer/Counter1

This 8-bit register contains the value of Timer/Counter1.

The Timer/Counter1 is realized as a 10-bit up/down coun ter with read an d write access . Due to

synchronization of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one

and half CPU clock cycles in synchronous mode and at most one CPU clock cycles for asyn-

chronous mo de. When a 10-bit accu racy is preferred, sp ecial proced ures must be followe d for

accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures are

described in section “Accessing 10 -Bit Registers” on page 108 . Alternatively the Time r/Counte r1

can be used as an 8-bit Timer/Counter. Note that the Timer/Counter1 always starts counting up

after writing the TCNT1 register.

12.12.8 TC1H – Timer/Counter1 High Byte

The temporary Timer/Counter1 register is an 2-bit read/write register.

• Bits 7:2 – Res: Reserved Bits

These bits are reserved and always reads zero.

• Bits 1:0 – TC19, TC18: Two MSB bits of the 10-bit accesses

If 10-bit accuracy is used, the Timer/Counter1 High Byte Register (TC1H) is used for temporary

storing the MSB bits (TC19, TC18) of the 10-bit acceses. The same TC1H register is shared

between all 10-bit registers within the Timer/Counte r1. Note th at spe cial p rocedur es must be fol-

lowed when accessing the 10-bit TCNT1 register via the 8-bit AVR data bus. These procedures

are described in section “Accessing 10-Bit Registers” on page 108.

12.12.9 OCR1A – Timer/Counter1 Output Compare Register A

The output compare register A is an 8-bit read/write register.

The Timer/Counter Output Compare Register A contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does

only occur if Timer/Counter1 counts to the OCR1A value. A software writ e that sets TCN T1 a nd

OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-

ing the compar e event.

Note that, if 10-bit accuracy is used special proce dures must be followed when accessing the

internal 10-bit Ouput Compare Registers via the 8-bit AVR data bus. These procedures are

described in section “Accessing 10-Bit Registers” on page 108.

Bit 76543210

0x2E (0x4E) MSB LSB TCNT1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

0x25 (0x45) ------TC19TC18TC1H

Read/WriteRRRRRRR/WR/W

Initial value00000000

Bit 76543210

0x2D (0x4D) MSB LSB OCR1A

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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12.12.10 OCR1B – Timer/Counter1 Output Compare Regist er B

The output compare register B is an 8-bit read/write register.

The Timer/Counter Output Compare Register B contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1B value. A software writ e that sets TCN T1 a nd

OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-

ing the compar e event.

Note that, if 10-bit accuracy is used special proce dures must be followed when accessing the

internal 10-bit Outp ut Compare Registers via the 8-bit AVR data bus . These procedures are

described in section “Accessing 10-Bit Registers” on page 108.

12.12.11 OCR1C – Timer/Counter1 Output Compare Register C

The output compare register C is an 8-bit read/write register.

The Timer/Counter Output Comp ar e Register C contains data to be continuously compared with

Timer/Counter1, and a compare match will clear TCNT1. This register has the same function in

Normal mode and PWM modes.

Note that, if a smaller value than three is written to the Output Compare Register C, the value is

automatically replaced by three as it is a minumum value allowed to be written to this register.

Note that, if 10-bit accuracy is used special proce dures must be followed when accessing the

internal 10-bit Outp ut Compare Registers via the 8-bit AVR data bus . These procedures are

described in section “Accessing 10-Bit Registers” on page 108.

12.12.12 OCR1D – Timer/Counter1 Output Compare Regist er D

The output compare register D is an 8-bit read/write register.

The Timer/Counter Output Comp ar e Register D contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does

only occur if Timer/Counter1 counts to the OCR1D value. A software write that sets TCNT1 and

OCR1D to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1D after a synchronization delay follow-

ing the compar e event.

Bit 76543210

0x2C (0x4C) MSB LSB OCR1B

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

0x2B (0x4B) MSB LSB OCR1C

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value11111111

Bit 76543210

0x2A (0x4A) MSB LSB OCR1D

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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Note that, if 10-bit accuracy is used special proce dures must be followed when accessing the

internal 10-bit Outp ut Compare Registers via the 8-bit AVR data bus . These procedures are

described in section “Accessing 10-Bit Registers” on page 108.

12.12.13 TIMSK – Timer/Counter1 Interrupt Mask Register

• Bit 7 – OCIE1D: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1D bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchD, interrupt is enabled. The corresponding interrupt at vector

$010 is executed if a compare matchD o ccurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 6 – OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Count er1 Compare MatchA , interrupt is enabled. The corresponding interrupt at vector

$003 is executed if a compare matchA occur s. The Com pare Flag in Timer/Counter1 is se t (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 5 – OCIE1B: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Count er1 Compare MatchB , interrupt is enabled. The corresponding interrupt at vector

$009 is executed if a compare matchB occur s. The Com pare Flag in Timer/Counter1 is se t (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 2 – TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflo w interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer /Co un ter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

12.12.14 TIFR – Time r/Counter1 Interrupt Flag Register

• Bit 7 – OCF1D: Output Compare Flag 1D

The OCF1D bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1D - Output Compare Register 1D. OCF1D is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1D is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1D, and OCF1D

are set (one), the Timer/Counter1 D compare match interrupt is executed.

• Bit 6 – OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by ha rdwa re when executing

Bit 76543210

0x39 (0x59) OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 TIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

Bit 76543210

0x38 (0x58) OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 TIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 – OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by ha rdwa re when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 – TOV1: Timer/Counter1 Overflow Flag

In Normal Mode and Fast PWM Mode the TOV1 bit is set (one) each time the counter reaches

TOP at the same clock cycle when the counter is reset to BOTTOM. In Phase and Frequency

Correct PWM Mode the TO V1 bit is set (one) each time the counter rea ches BOTTOM at the

same clock cycle when zero is clocked to the coun te r.

The bit TOV1 is cleared by hardware when executing the corresponding interrupt handling vec-

tor. Alternatively, TOV1 is cleared, after synchronization clock cycle, by writing a logical one to

the flag. When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and

TOV1 are set (one), the Timer/Counter1 Overflow interrupt is executed.

12.12.15 DT1 – Timer /Counter1 Dead Time Value

The dead time value register is an 8-bit read/write register.

The dead time delay of all Timer/Counter1 channels are adjusted by the dead time value regis-

ter, DT1. The register consists of two fields, DT1H3:0 and DT1L3:0, one for each

complementary outp ut. Therefo re a different dead time delay can be a djusted for the rising edge

of OC1x and the rising edge of OC1x.

• Bits 7:4 – DT1H3:DT1H0: Dead Time Value for OC1x Output

The dead time value for the OC1x output. Th e dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

• Bits 3:0 – DT1L3:DT1L0: Dead Time Value for OC1x Output

The dead tim e value for the OC1x output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

Bit 76543210

0x24 (0x44) DT1H3 DT1H2 DT1H1 DT1H0 DT1L3 DT1L2 DT1L1 DT1L0 DT1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial value00000000

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13. USI – Universal Serial Interface

13.1 Features •Two-wire Synchronous Data Tra nsfer (Master or Slave)

•Three-wire Synchronous Data Transfer (Master or Slave)

•Data Received Interrupt

•Wakeup from Idle Mode

•In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode

•Two-wire Start Condition Detector with Interrupt Capability

13.2 Overview The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial

communication. Combined with a minimum of control software, the USI allows significantly

higher transfer rates and uses less code space than solutions based on software o nly. Interrupts

are included to minimize the processor load.

A simplified block diagram of the USI is shown in Figure 1 3-1 For actual placement of I/O pins

refer to “Pinout ATtiny261/461/861 and ATtiny261V/461V/861V” on page 2. Device-specific I/O

Figure 13-1. Universal Serial Interface, Block Diagram

The 8-bit USI Data Register (USIDR) is directly accessible via the data bus and contains the

incoming and outgoing data. The register has no buffe ring so the data must be read as quickly

as possible to ensure that no data is lost. The data register is a serial shift register where the

most significant bit is connected to o ne of two output pin s depending of the wire mode configura-

tion. A transparent latch between the output of the data register and the output pin delays the

change of data output to the opposite clock edge of the data input sampling. The serial input is

always sampled from the Data Input (DI) pin, regardless of the configuration.

DATA BUS

USIPF

USITC

USICLK

USICS0

USICS1

USIOIFUSIOIE

USIDC

USISIF

USIWM0

USIWM1

USISIE Bit7

Two-wire Clock

Control Unit

DO (Output only)

DI/SDA (Input/Open Drain)

USCK/SCL (Input/Open Drain)

4-bit Counter

USIDR

USISR

USICR

CLOCK

HOLD

TIM0 COMP

Bit0

[1]

USIDB

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The 4-bit counter can be both read and written via the data bus, and it can generate an overflow

interrupt. The data register and the counter are clocked simultaneously by the same clock

source, allowing the counter to co unt the number of bits r eceived or transm itted a nd gener ate an

interrupt when the transfer is complete. Note that when an external clock source is selected the

counter counts both clock edges. In this case the counter counts the number of edges, and not

the number of bits. The clock can be selected from three different source s: The USCK pin, the

Timer/Counter0 Compare Match or from software.

The Two-wire clock control unit can generate an interrupt when a start condition is detected on

the Two-wire bus. It can also generate wait states by holding the clock pin low after a start con-

dition is detected, or after the counter overflows.

13.3 Functional Descriptions

13.3.1 Three-wire Mode

The USI Three-wire mode is compliant to th e Se rial Periph eral Interf ace (SPI) mode 0 a nd 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software if necessary. Pin names used by this mode are: DI, DO, and USCK.

Figure 13-2. Three-wire Mode Operation, Simplified Diagram

Figure 13-2 shows two USI units operatin g in three-wire mode, one as Maste r and on e as Slave.

The two USI Data Register are interconnected in such way that after eight USCK clocks, the

data in each register are interchanged. The same clock also incre ments th e USI’s 4-bit counter.

The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine when a

transfer is completed. The clock is generated by the Master device software by toggling the

USCK pin via the PORT Re gis ter or by writing a one to the USITC bit in USICR.

SLAVE

MASTER

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

USCK

PORTxn

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Figure 13-3. Three-wire Mode, Timing Diagram

The Three-wire mode timing is sh own in Figure 1 3-3. At the top of the figure is a USCK cycle ref-

erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The

USCK timing is shown for both external clock mo des. In External Clo ck mode 0 (USICS0 = 0), DI

is sampled at positiv e edges, and DO is changed (Da ta Register is shifted by one) a t negative

edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0 are

used. In other words, data is sampled at negative and output is changed at positive edges. The

USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 13-3), a bus transfer involves the following steps:

1. The slave and master devices set up their da ta outputs and, depending on the protocol

used, enable their output drivers (mark A and B). The output is set up by writing the

data to be transmitted to the USI Data Register. The output is enab le d by se ttin g the

corresponding bit in the Data Direction Register of Port A. Note that there is not a pre-

ferred order of points A and B in the figure, but both must be at least one half USCK

cycle before point C, where the data is sampled. This is in order to ensure that the data

setup requirem e nt is sat isfie d. The 4-bit counter is reset to zero.

2. The master software generates a clock pulse by toggling the USCK line twice (C and

D). The bit values on the data input (DI) pins are sampled by the USI on the first edge

(C), and the data output is changed on the opposite edge (D). The 4-bit counter will

count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer has been completed. The data bytes transferred must now be processed

before a new transfer can be initiated. The overflow interrupt will wake up the processor

if it is set to Idle mode. Depend ing on the protocol used the sla ve device can now set it s

output to high impedance.

13.3.2 SPI Master Operation Example

The following code demonstrates how to use the USI module as a SPI Master:

SPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

ldi r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

MSB

654321LSB

1 2 3 4 5 6 7 8

654321LSB

USCK

DCBA E

CYCLE

( Reference )

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SPITransfer_loop:

sts USICR,r16

lds r16, USISR

sbrs r16, USIOIF

rjmp SPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (plus return). The code example

assumes that the DO and USCK pins have been enabled as outputs in DDRA. The value stored

in register r16 prior to the function is called is transferred to the slave device, and when the

transfer is completed the data received from the slave is stored back into the register r16.

The second and third instructions clear the USI Counter Overflow Flag and the USI counter

value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC

strobe, and toggle USCK. The loop is repeated 16 times.

The following code demonstrates ho w to use the USI as an SPI master with maximum speed

(fSCK = fCK/2):

SPITransfer_Fast:

out USIDR,r16

ldi r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

ldi r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

out USICR,r16 ; MSB

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16

out USICR,r17

out USICR,r16 ; LSB

out USICR,r17

in r16,USIDR

ret

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13.3.3 SPI Slave Operation Example

The following code demonstrates how to use the USI module as a SPI Slave:

init:

ldi r16,(1<<USIWM0)|(1<<USICS1)

sts USICR,r16

...

SlaveSPITransfer:

sts USIDR,r16

ldi r16,(1<<USIOIF)

sts USISR,r16

SlaveSPITransfer_loop:

lds r16, USISR

sbrs r16, USIOIF

rjmp SlaveSPITransfer_loop

lds r16,USIDR

ret

The code is size optimized using only eight instructions (+ ret). The code example assumes that

the DO is configured as output and USCK pin is configured as input in the DDR Register. The

value stored in register r16 prior to the function is called is transferred to the master device, and

when the transfer is completed the data received from the Master is stored back into the r16

Note that the first two instructions are for initialization, only, and need only be executed once.

These instructions set three-wire mode and positive edge clock. The loop is repeated until the

USI Counter Overflow Flag is set.

13.3.4 Two-wire ModeThe USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-

iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.

Figure 13-4 on page 130 shows two USI units operating in two-wire mode, one as master and

one as slave. It is only the physical layer that is shown since the system operation is highly

dependent of the communication sche me used. The main differences between the master and

slave operation at this level is the serial clock generation which is always done by the master.

Only the slave uses the clo ck con tr ol un it.

Clock generation must be implemented in software, but the shift operation is done automatically

in both devices. Note that clocking only on negative edges for shifting data is of practical use in

this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock

low. This means that the master must always check if the SCL line was actually released after it

has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that the

transfer is comple ted. The clock is generated by the ma ster by toggling the USCK pin via the

PORTA register.

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Figure 13-4. Two-wire Mode Operation, Simplified Diagram

The data direction is not given by the physical layer. A protocol, like the one used by the TWI-

bus, must be implemented to control the data flow.

Figure 13-5. Two-wire Mode, Typical Timing Diagram

Referring to the timing diagram (Figure 13-5), a bus transfer involves the following steps:

1. The start condition is generated by the master by forcing the SDA low line while keep-

ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the

USI Data Register, or by setting the corresponding bit in the PORTA register to zero.

Note that the Data Direction Register bit must be set to one for the output to be

enabled. The start detector logic of the slave device (see Figure 13-6 on page 131)

detect s the st a rt condition and set s the USISIF Flag . The flag can genera te an inte rrupt

if necessary.

2. In addition, the start detector will hold the SCL line low after the master has forced a

negative edge on this line (B). This allows the slave to wake up from sleep or complete

other ta sks before setting up the USI Data Register to receive the address. This is done

by clearing the start condition flag and resetting the counter.

MASTER

SLAVE

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SDA

SCL

Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

Two-wire Clock

Control Unit

HOLD

SCL

PORTxn

SDA

SCL

VCC

PS ADDRESS

1 - 7 8 9

R/W ACK ACK

1 - 8 9

DATA ACK

1 - 8 9

DATA

SDA

SCL

A B D EC F

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3. The master set the first bit to be transferred and releases the SCL line (C). The sl av e

samples the dat a and shift s it into the USI Data Register at the positive edge of the SCL

clock.

4. After eight bits containing slave address and data direction (read or write) have been

transferred, the slave counter overflows and the SCL line is forced low (D). If the slave

is not the one the master has addressed, it releases the SCL li ne and waits for a new

start condition.

5. When the slave is addressed, it holds the SDA line low during the acknowledgment

cycle before holding the SCL line lo w ag ain (i.e., the USI Counter Reg ister must be se t

to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave

enables its output. If the bi t is set, a master r ead operation is in progress (i.e., the sla ve

drives the SDA line) The slave can hold the SCL line low after the ackn owle d ge (E ).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is

given by the master (F), or a new start condition is given.

If the slave is not able to receive more data it does not acknowledge the data byte it has last

received. When the master does a read operation it must terminate the operation by forcing the

acknowledge bit low after the last byte transmitted.

13.3.5 Start Condition Detector

The start condition detector is shown in Figure 13-6. The SDA line is delayed (in the range of 50

to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled

in Two-wire mode.

Figure 13-6. Start Condition Detector, Logic Diagram

The start condition detector works asynchronously and can therefore wake up the processor

from power- down sleep mode. Ho wever, the protocol u sed might have re strictions on the SCL

hold time. Therefore, when using this feature in this case the Oscillator start-up time set by the

CKSEL Fuses (see “Clock System” on page 24) must also be taken into the consideration. Refer

to the USISIF bit description on page 133 for further details.

13.3.6 Clock speed consid erations

Maximum frequency for SCL and SCK is fCK / 2. This is also the maximum data transmit and

receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-

trol Unit will hold the SCL low until the slav e is ready to receive more data. This may reduce the

actual data rate in two-wire mode.

SDA

SCL

Write( USISIF)

CLOCK

HOLD

USISIF

CLR

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13.4 Alternative USI Usage

The flexible design of the USI allows it to be used for other tasks when serial communication is

not needed. Below are some exa mples.

13.4.1 Half-Duplex Asynchronous Data Transfer

Using the USI Data Register in three-wire mode it is possible to implement a more compact and

higher performance UART than by software, only.

13.4.2 4-Bit Counter The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will increment the counter value.

13.4.3 12-Bit Timer/Counter

Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.

13.4.4 Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

13.4.5 Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

13.5 Register Descriptions

13.5.1 USIDR – USI Data Register

The USI Data Register can be accessed directly.

Depending on the USICS1:0 bits of the USI Control Register a (left) shift operation may be per-

formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0

Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is performed.

Note that even when no wire mode is selected (USIWM1:0 = 0) both the external data input

(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to

the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input

is sampled and data output is changed on opposite clock edges. The latch is open (transparent)

during the first half of a serial clock cycle when an external clock source is selected (USICS1 =

1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB is written as long as the latch is open.

Note that the Data Direction Register bit corresponding to the output pin must be set to one in

order to enable data output from the USI Data Register.

Bit 76543210

0x0F (0x2F) MSB LSB USIDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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13.5.2 USIBR – USI Buffer Register

The content of the Serial Register is loaded to the USI Buffer Register when the trasfer is com-

pleted, and instead of accessing the USI Data Register (the Serial Register) the USI Data Buffer

can be accessed when the CPU reads the received data. This gives the CPU time to handle

other program tasks too as the co ntrolling of the USI is not so timing critical. The USI flags as set

same as when reading the USIDR register.

13.5.3 USISR – USI Status Register

The Status Register contains Interrupt Flags, line Status Flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is

detected. When output disable mode or Three-wire mode is selected and (USICSx = 0b11 &

USICLK = 0) or (USICS = 0b10 & USICLK = 0), any edge on the SCK pin sets the flag.

An interrupt will be generated when the flag is set while the USISIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the USISIF

bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at th e transition from 15 to 0). An

interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global

Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When Two-wire mode is selected, the USIPF Flag is set (one) when a stop con dition is detected.

The flag is cleared by wr iting a one to this bit. Note that this is not an Inte rrupt Flag. Thi s signal is

useful when implementing Two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when Two-wire mode is used. This signal is useful when im plementing Two-

wire bus master arbitration.

• Bits 3:0 – USICNT3:0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit coun ter value c an d ire ctly b e read or

written by the CPU.

Bit 76543210

0x10 (0x30) MSB LSB USIBR

Read/Write R R R R R R R R

Initial Value 0 0 0 0 0 0 0 0

Bit 76543 2 1 0

0x0E (0x2E) USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 USISR

Read/Write R/W R/W R/W R R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Com pare Match, or by software using USICLK or USITC strobe

bits. The clock source depends of the setting of the USICS1:0 bits. For external clock operation

a special feature is added that allows the clock to be generated by writing to the USITC strobe

bit. This feature is enabled by write a one to the USICLK bit while se tting an external clock

source (USICS1 = 1).

Note that even when no wire mode is selected (USIWM1:0 = 0) the external clock input

(USCK/SCL) are can still be used by the counter.

13.5.4 USICR – USI Control Register

The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,

and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enab les the Start Condition detecto r interrupt. If there is a pending inter-

rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately be

executed. Refer to the USISIF bit description on page 133 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables th e Counter Overflow inter rupt. If there is a pending interrupt when

the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be executed.

Refer to the USIOIF bit description on page 133 for further details.

• Bits 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used, as shown in Table 13-1 on page 134.

Basically, only the function of the outputs are affected by these bits. Data and clock inputs are

not affected by the mode selected and will always have the same function. The counter and USI

Data Register can therefore be clocked externally, and data input sampled, even when outputs

are disabled.

Bit 76543210

0x0D (0x2D) USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC USICR

Read/Write R/W R/W R/W R/W R/W R/W W W

Initial Value 0 0 0 0 0 0 0 0

Table 13-1. Relationship between USIWM1:0 and USI Operation

USIWM1 USIWM0 Description

Outputs, clock hold, and start detector disabled.

Port pins operate as no rmal.

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORTA

When the port pin is set as input the pin pull-up is controlled by the PORTA bit.

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port

operation. When opera ting as master, clock pulses are software generated by

toggling th e PORTA register, while the da ta direction is set to output. The

USITC bit in the USICR Register can be used for this purpose.

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Note: 1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

• Bits 3:2 – USICS1:0: Clock Source Select

These bits set the clock source for the USI Data Registerr and counter. The data ou tput latch

ensures that the output is changed at the opposite edge of the sampling of the data input

(DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and

therefore the output is changed immediately. Clearing the USICS1:0 bits enables software

strobe optio n. When using this option, writin g a one to the USICLK bit clocks both the USI Data

used as a strobe, but selects between external clocking and software clocking by the USITC

strobe bit.

Table 13-2 on page 135 sh ow s th e re la tion sh ip be tw ee n th e USICS1:0 and USICL K s et tin g a n d

clock source used for the USI Data Register and the 4-bit counter.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins (1).

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and

use open-collector output drives. The output drivers are enabled by setting the

corresponding bit for SDA and SCL in the DDRA register.

When the output driver is enabled for the SDA pin, the output driver will force

the line SDA low if the output of the USI Data Register or the corresponding

bit in the PORTA register is zero. Otherwise, the SDA line will not be driven (i.e.,

it is released). When the SCL pin output driver is enabled the SCL line will be

forced low if the corresponding bit in the PORTA regi st er i s ze ro, or by the start

detector. Otherwise the SCL line will not be driven.

The SCL line is held low when a start detector detects a start condition and the

output is enabled. Clearin g the Start Condition Flag (USISIF) releases the line .

The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on

the SDA and SCL port pin are disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

Same operation as in two-wire mode above, except that the SCL line is also

held low when a counter overflow occurs, and until the Counter Overflow Flag

(USIOIF) is cleared.

Table 13-2. Relations between the USICS1:0 and USICLK Setting

USICS1 USICS0 USICLK USI Data Register Clock

Source 4-bit Counter Cl ock Source

0 0 0 No Clock No Clock

001

Software clock strobe

(USICLK) Software clock strobe

(USICLK)

01X

Timer/Counter0 Compare

Match Timer/Counter0 Compare

Match

1 0 0 External, positive edge External, both edges

Table 13-1. Relationship between USIWM1:0 and USI Operation (Continued)

USIWM1 USIWM0 Description

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• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the USI Data Register to shift one step and the counter

to increment by one, provided that the USICS1:0 bits are s et to zero and by doing so the soft -

ware cloc k strobe option is selected. The output will change immediately when the clock strobe

is executed, i.e., in the same instruction cycle. The value shifted into the USI Data Register is

sampled the previous instruction cycle. The bit will be read as zero.

When an exter nal clock source is selected (USICS1 = 1), the USICLK function is changed from

a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the

USITC strobe bit as clock source for the 4-bit counter (see Table 13-2).

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.

The toggling is independe nt of the setting in the Data Direction Register, but if the PORT value is

to be shown on the pin the DDB2 must be set as output (to one). This feature allows easy clock

generation when implementing master devices. The bit will be read as zero.

When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-

ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of

when the transfer is done when operating as a master device.

13.5.5 USIPP – USI Pin Position

• Bits 7:1 – Res: Reserved Bits

These bits are reserved and will always read as zero.

• Bit 0 – USIPOS: USI Pin Position

Setting this bit to one changes the USI pin position. As default pins PB2:PB0 are used for the

USI pin functions, but when writing this bit to one the USIPOS bit is set the USI pin functions are

on pins PA2:PA0.

1 1 0 External, negativ e edge External, both edges

1 0 1 External, positive edge Software clock strobe (USITC)

1 1 1 External, negative edge Software clock strobe (USITC)

Table 13-2. Relations between the USICS1:0 and USICLK Setting (Continued)

USICS1 USICS0 USICLK USI Data Register Clock

Source 4-bit Counter Cl ock Source

Bit 76543210

0x11 (0x31) -------USIPOSUSIPP

Read/WriteRRRRRRRR/W

Initial Value00000000

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14. AC – Analog Comparator

The analog comparator compares the input values on the selectable positive pin (AIN0, AIN1 or

AIN2) and selectable negative pin (AIN0, AIN1 or AI N2 ). When the volt ag e on th e po sit i ve pin is

higher than the voltage on the ne gative pin, the Analog Comparator Output, ACO, is set. The

comparator can trigger a separate interrupt, exclusive to the analog comparator. The user can

select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the com-

parator and its sur rounding logic is shown in Figure 14-1.

Figure 14-1. Analog Comparator Block Diagram

Notes: 1. See Table 14-1 on page 137.

See Figure 1-1 on page 2 and Table 10-3 on page 63 for Analog Comparator pin placement.

14.1 Analog Comparator Multiplexed Input

When the Analog to Digital Converter (ADC) is configurated as single ended input channel, it is

possible to select any of the ADC10:0 pins to replace the negative input to the analog compara-

tor. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Mu ltiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX5:0 in ADMUX

select the input pin to replace the negative input to the analog comparator, as shown in Table

14-1. If ACME is cleared or ADEN is set, either AIN0, AIN1 or AIN2 is applied to the negative

input to the analog comparator.

ACBG

BANDGAP

REFERENCE

ADC MULTIPLEXER

OUTPUT

ACME

ADEN

(1)

MUX

AIN0

AIN1

AIN2

ACM2..1

HSEL

HLEV

Table 14-1. Analog Comparator Multiplexed Input

ACME ADEN MUX5:0 ACM2:0 Positive Input Negative Input

0 x xxxxxx 000 AIN0 AIN1

0 x xxxxxx 001 AIN0 AIN2

0 x xxxxxx 010 AIN1 AIN0

0 x xxxxxx 011 AIN1 AIN2

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0 x xxxxxx 100 AIN2 AIN0

0 x xxxxxx 101,110,111 AIN2 AIN1

1 1 xxxxxx 000 AIN0 AIN1

1 0 000000 000 AIN0 ADC0

1 0 000000 01x AIN1 ADC0

1 0 000000 1xx AIN2 ADC0

1 0 000001 000 AIN0 ADC1

1 0 000001 01x AIN1 ADC1

1 0 000001 1xx AIN2 ADC1

1 0 000010 000 AIN0 ADC2

1 0 000010 01x AIN1 ADC2

1 0 000010 1xx AIN2 ADC2

1 0 000011 000 AIN0 ADC3

1 0 000011 01x AIN1 ADC3

1 0 000011 1xx AIN2 ADC3

1 0 000100 000 AIN0 ADC4

1 0 000100 01x AIN1 ADC4

1 0 000100 1xx AIN2 ADC4

1 0 000101 000 AIN0 ADC5

1 0 000101 01x AIN1 ADC5

1 0 000101 1xx AIN2 ADC5

1 0 000110 000 AIN0 ADC6

1 0 000110 01x AIN1 ADC6

1 0 000110 1xx AIN2 ADC6

1 0 000111 000 AIN0 ADC7

1 0 000111 01x AIN1 ADC7

1 0 000111 1xx AIN2 ADC7

1 0 001000 000 AIN0 ADC8

1 0 001000 01x AIN1 ADC8

1 0 001000 1xx AIN2 ADC8

1 0 001001 000 AIN0 ADC9

1 0 001001 01x AIN1 ADC9

1 0 001001 1xx AIN2 ADC9

1 0 001010 000 AIN0 ADC10

1 0 001010 01x AIN1 ADC10

1 0 001010 1xx AIN2 ADC10

Table 14-1. Analog Comparator Multiplexed Input (Continued)

ACME ADEN MUX5:0 ACM2:0 Positive Input Negative Input

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14.2 Register Description

14.2.1 ACSRA – Analog Comparator Control and Status Register A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the analog comparator is switched off. This bit

can be set at any time to turn off the analog comparator, thus reducing power consumption in

Active and Idle mode. When changing the ACD bit, the analog co mparator Inter rupt must be dis-

abled by clearing the ACIE bit in ACSRA. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Selec t

When this bit is set an internal 1.1V reference voltage replaces the positive input to the analog

comparator. The selection of the internal voltage reference is done by writing the REFS2:0 bits

in ADCSRB and ADMUX registers. When this bit is cleared, AIN0, AIN1 or AIN2 depending on

the ACM2:0 bits is applied to the positive input of the analog comparator.

• Bit 5 – ACO: Analog Comparator Output

Enables output of analog comparator. The output of the analog comparator is synchronized and

then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the status re gister is set, the analog co m-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – ACME: Analog Co mparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the analog comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the analog comparator. For a detailed de scrip-

tion of this bit, see Table 14-1 on page 137.

Bit 76543210

0x08 (0x28) ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 ACSRA

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value00N/A00000

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• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which compar ator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 14-2.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an inter rupt can occur whe n the

bits are changed.

14.2.2 ACSRB – Analog Comparator Control and Status Register B

• Bit 7 – HSEL: Hysteresis Select

When this bit is written logic one, the hysteresis of the Analog Comparator is switched on. The

hysteresis level is selected by the HLEV bit.

• Bit 6 – HLEV: Hysteresis Level

When the hysteresis is enabled by the HSEL bit, the Hyster esis Level, HLEV, bit selects the hys-

teresis level that is either 20mV (HLEV=0) or 50mV (HLEV=1).

• Bits 2:0 – ACM2:ACM0: Analog Comparator Multiplexer

The Analog Comparator mu ltiplexer bits select th e positive and negative inpu t pins of the Analog

Comparator. The different settings are shown in Table 14-1.

14.2.3 DIDR0 – Digital Input Disable Register 0

• Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

• Bit 3 – AREFD: AREF Digital Input Disable

When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre-

sponding PIN register bit will always read as zero when this bit is set. When an analog signal is

Table 14-2. ACIS1/ACIS0 Settings

ACIS1 ACIS0 Interrupt Mode

0 0 Comparator Interrupt on Output Toggle.

01Reserved

1 0 Comparator Interrupt on Falling Output Edge.

1 1 Comparator Interrupt on Rising Output Edge.

Bit 76543210

0x09 (0x29) HSEL HLEV --- ACM2 ACM1 ACM0 ACSRB

Read/Write R/W R/W R R R R/W R/W R/W

Initial Value00N/A00000

Bit 76543210

0x01 (0x21) ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D DIDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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applied to the AREF pin and the digita l input from this pin is not need ed, this bit should be written

logic one to reduce power consump tion in the digital input buffer.

14.2.4 DIDR1 – Digital Input Disable Register 1

• Bits 7:4 – ADC10D:ADC7D: ADC10:7 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC10:7 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

Bit 76543210

0x02 (0x22) ADC10D ADC9D ADC8D ADC7D - DIDR1

Read/Write R/WR/WR/WR/W R R R R

Initial Value 0 0 0 0 0 0 0 0

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15. ADC – Analog to Digital Converter

15.1 Features •10-bit Resolution

•1.0 LSB Integral Non-linearity

•± 2 LSB Absolute Accuracy

•13µs Conversion Time

•15 kSPS at Maximum Resolution

•11 Multiplexed Single Ended Input Channels

•16 Differential input pairs

•15 Differential input pairs with selectable gain

•Temperature Sensor Input Channel

•Optional Left Adjustment for ADC Result Readout

•0 - VCC ADC Input Voltage Range

•Selectable 1.1V / 2.56V ADC Voltage Reference

•Free Running or Sin gle Conversion Mode

•ADC Start Conversion by Auto Triggering on Interrupt Sources

•Interrupt on ADC Conversion Complete

•Sleep Mode Noise Cancele

•Unipolar / Bipolar In pu t Mode

•Input Polarity Reversal Mode

15.2 Overview The ATtiny261/461/861 fe atures a 10-bit success ive approximation ADC. The ADC is connected

to a 11-channel Analog Multiplexer which allows 16 differential voltag e input combinations and

11 single-ended voltage inputs constructed from the pins PA7:PA0 or PB7:PB4. The differential

input is equipped with a programmable gain stage, providing amplificatio n steps of 1x, 8x, 20x or

32x on the differential input voltage before the A/D conversion. The single-ended voltage inputs

refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 15-1

on page 143.

Internal reference voltages of nominally 1.1V or 2.56V are pr ovided On-chip . The Internal refer -

ance voltage of 2.56V, ca n optionally be externally decoupled at the AREF (PA3) pin by a

capacitor, for better noise performance. Alternatively, VCC can be used as reference voltage for

single ended channels. There is also an option to use an external voltage reference and turn-off

the internal voltage refe rence. These options are selected usin g the REFS2:0 bits of the ADC-

SRB and ADMUX registers.

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Figure 15-1. Analog to Digital Converter Block Schematic

15.3 Operation The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

VCC, the voltage on the AREF pin or an internal 1.1V / 2.56V voltage reference.

The voltage reference for the ADC may be selected by writing to the REFS2:0 bits in ADCSRB

and ADMUX registers. The VCC supply, the AREF pin or an internal 1.1V / 2.56V voltage refer-

ence may be selected as the ADC voltage reference. Optionally the internal 1.1V / 2.56V voltage

ADC CONVERSION

COMPLETE IRQ

8-BIT DATA BUS

15 0

ADC MULTIPLEXER

SELECT (ADMUX)

ADC CTRL. & STATUS

ADC DATA REGISTER

(ADCH/ADCL)

MUX2

ADIE

ADATE

ADSC

ADEN

ADIF ADIF

MUX1

MUX0

ADPS0

ADPS1

ADPS2

MUX3

CONVERSION LOGIC

10-BIT DAC

SAMPLE & HOLD

COMPARATOR

MUX DECODER

MUX4

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

REFS0

REFS1

ADLAR

CHANNEL SELECTION

GAIN SELECTION

ADC[9:0]

ADC

MULTIPLEXER OUTPUT

GAIN

AMPLIFIER

INTERNAL 1.1V

REFERENCE

PRESCALER

SINGLE ENDED /

DIFFERENTIAL SELECTION

AGND

POS.

INPUT

MUX

NEG.

INPUT

MUX

ADC10

ADC9

ADC8

VCC

AREF

TEMPERATURE

SENSOR

INTERNAL 2.56/1.1V

REFERENCE

MUX

ADC CTRL. & STATUS

REFS2

GSEL

MUX5

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reference may be decoupled by an external capacitor at the AREF pin to improve noise

immunity.

The analog input channel and differential gain are selected by writing to the MUX5:0 bits in

ADMUX. Any of the 11 ADC input pins ADC10:0 can be selected as single ended inputs to the

ADC. The positive and negative inputs to the differentia l gain amplifier are described in Table

15-4.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input pair by the selected gain factor, 1x, 8x, 20x or 32x, according to the

setting of the MUX5:0 bits in ADMUX and the GSEL bit in ADCSRB. This amplified value then

becomes the analog input to the ADC. If single ended channels are used, the gain amplifier is

bypassed altogether.

If the same ADC input pin is selected as both the positive and neg ative input to the differential

gain amplifier, the remaining offset in the gain stage and conversion circuitry can be measured

directly as the result of the conversion. This figure can be subtracted from subsequent conver-

sions with the same gain setting to reduce offset error to below 1 LSW.

The on-chip temperature sensor is selected by writing the code “111111” to the MUX5:0 bits in

ADMUX register when the ADC11 channel is used as an ADC input.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltag e reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommende d to switch off the ADC before en tering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right ad justed, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left ad justed and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, th en ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered wh en a conversion comple tes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

15.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and w ill be cleared by hardware

when the conversion is com pleted. If a differe nt data channel is selected while a conver sion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigge r Select bits, ADTS in ADCSRB (see description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

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conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global In terrup t Enab le bit in SREG is cleared. A conversion can thus

be triggered without causing an inter rupt. However, th e Interrupt Flag must be clea red in order to

trigger a new conversion at the next interrupt event.

Figure 15-2. ADC Auto Trigger Logic

Using the ADC Interrupt Flag as a trigger sou rce makes the ADC start a new conver sion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and up dating the ADC Data Register . The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be us ed to determine if a conversion is in pr ogress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

15.5 Prescaling and Conversion Timing

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long a s the ADEN bit is set, and is co ntinuously

reset when ADEN is low.

See Figure 15-3 on page 146.

ADSC

ADIF

SOURCE 1

SOURCE n

ADTS[2:0]

CONVERSION

LOGIC

PRESCALER

START CLKADC

.EDGE

DETECTOR

ADATE

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Figure 15-3. ADC Prescaler

When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,

as shown in Figure 15-4 below.

Figure 15-4. ADC Timing Diagram, First Conversion ( Single Conversion Mode)

The actual sample-and -h old ta kes pla ce 1.5 ADC cl ock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. See Figure 15-5. When a

conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-

gle Conversion mode, ADSC is cleared sim ultaneously. The software ma y then set ADSC again,

and a new conversion will be initiated on the first rising ADC clock edge.

7-BIT ADC PRESCALER

ADC CLOCK SOURCE

ADPS0

ADPS1

ADPS2

CK/128

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

Reset

ADEN

START

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

Sample & Hold

ADIF

ADCH

ADCL

Cycle Number

ADEN

1212

13 14 15 16 17 18 19 20 21 22 23 24 25 1 2

First Conversion Next

Conversion

MUX and REFS

Update MUX and REFS

Update

Conversion

Complete

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Figure 15-5. ADC Timing Diagram, Single Conversion

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. See Figure

15-6. This assures a fixed delay from the trigger event to the start of conversion . In this mode,

the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger

source signal. Three additional CPU clock cycles are used for synchronization logic.

Figure 15-6. ADC Timing Diagram, Auto Triggere d Conversion

In Free Runnin g mo de (s ee Figure 15-7), a new conversion will be started immediately after the

conversion completes, while ADSC remains high.

123456789 10 11 12 13

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number 12

One Conversion Next Conversion

Sample & Hold

MUX and REFS

Update

Conversion

Complete MUX and REFS

Update

1 2 3 4 5 6 7 8 910 11 12 13

Sign and MSB of Result

LSB of Result

ADC Clock

Trigger

Source

ADIF

ADCH

ADCL

Cycle Number 12

One Conversion Next Conversion

Conversion

Complete

Prescaler

Reset

ADATE

Prescaler

Reset

Sample &

Hold

MUX and REFS

Update

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Figure 15-7. ADC Timing Diagram, Free Run ning Conversion

For a summary of conversion times, see Ta b le 15 -1.

15.6 Changing Channel or Reference Selection

The MUX5:0 and REFS2:0 bits in the ADCSRB and ADMUX registers are single buffered

through a temporary register to which the CPU has random access. This ensures that the chan-

nels and reference selection only takes place at a safe point during the conversion. T he channel

and reference selection is continuously updated until a conversion is started. Once the conver-

sion starts, the channel and reference se lection is locked to ensure a suffi cient sampling time for

the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion com-

pletes (ADIF in ADCSRA is set). Note that the conversion starts on the followin g rising ADC

clock edge after ADSC is written. The user is thus advise d n ot to write n ew chan nel o r refer ence

selection values to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot te ll if the next conversion is based

on the old or the new settings.

ADMUX can be safely updated in the following ways:

Table 15-1. ADC Conversion Time

Condition Sample & Hold

(Cycles from St art of Conversion) Total Conversion Time (Cycles)

First conversion 13.5 25

Normal conversions 1.5 13

Auto Triggered conversi ons 2 13.5

11 12 13

Sign and MSB of Result

LSB of Result

ADC Clock

ADSC

ADIF

ADCH

ADCL

Cycle Number 12

One Conversion Next Conversion

Conversion

Complete Sample & Hold

MUX and REFS

Update

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• When ADATE or ADEN is cleared.

• During conversion, minimum one ADC clock cycle after the trigger event.

• After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

15.6.1 ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the chann el before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wa it for the conver sion to complete before cha nging the ch annel selectio n.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the cha nnel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

15.6.2 ADC Voltage Reference

The voltage refere nce for the ADC (VREF) indicates the conversion range for the ADC. Single

ended channels that exceed VREF will result in code s close to 0x3FF. VREF can be selected as

either VCC, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC con-

version result after switching voltage reference source may be inaccurate, a nd the user is

advised to discar d this res ult .

15.7 ADC Noise Canceler

The ADC features a noise cance ler that enables conversion during sleep mode. This reduces

noise induced from the CPU core and other I/O peripherals. The noise canceler can be used

with ADC Noise Reduction and Idle mode. To make use of this feature, the following procedure

should be used:

• Make sure that the ADC is enable d and is not busy converting. Single Conversion mode must

be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the

CPU has been halted.

• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will

wake up the CPU and execute the ADC Conversion Complete inter rupt routine. If another

interrupt wakes up the CPU before the ADC conversion is complete, that interrupt will be

executed, and an ADC Conversion Complete interrupt request will be generated when the

ADC conversion completes. The CPU will remain in active mode until a new sleep command

is executed.

Note that the ADC will not automatically be turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

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15.8 Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 15-8 An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin , regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must dr ive the S/H capacitor th rough the series re sistance (combined re sistance in the

input path).

Figure 15-8. Analog Input Circuitry

The capacitor in Figure 15-8 depicts the total capacitance, includin g the sample/hold capacitor

and any stray or parasitic capacitance inside the device. The value given is worst case.

The ADC is optimized for analog signals with an output impedance of approximately 10 k or

less. If such a source is used, the sampling time will be neglig ible. If a sour ce with higher impe d-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components hig her than the Nyquist frequenc y (fADC/2) should not be prese nt to avoid

distortion from unpredictab le signal convolution. Th e user is advised to remove high frequency

components with a low-pass filter before applying the signals as inputs to the ADC.

15.9 Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. When conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run over the analog ground plane.

• Keep analog tracks well away from high-speed switching digital tracks.

• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.

• Place bypass capacitors as close to VCC and GND pins as possible.

Where high ADC accuracy is requir ed it is recommend ed to use ADC Noise Redu ction Mode , as

described in Se ction 15.7 on page 149. This is especially the case when system clock frequency

is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as

ADCn

IIH

1..100 kΩ

CS/H= 14 pF

VCC/2

IIL

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described in Section 15.12 on page 154. A good system design with properly placed, external

bypass capacitors does r educe the need for using ADC Noise Reduction Mode

15.10 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps

(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.

Several parameters describe the deviation from the ideal behavior:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value : 0 LSB.

Figure 15-9. Offset Error

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

Offset

Error

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• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 15-10. Gain Error

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

Figure 15-11. Integral Non-linearity (INL)

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

Gain

Error

Output Code

VREF Input Voltage

Ideal ADC

Actual ADC

INL

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• Differential Non-linearity (DNL): The maximu m deviation of the actual code width (the interval

between two adjacent transition s) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 15-12. Differential Non-linearity (DNL)

• Quantization Error: Due to the quantization of the input volt age into a fin ite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transitio n comp ared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.

15.11 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the

conversio as there are three types of conversions: single ended conversion, unipolar differential

conversion and bipolar differential conversion.

15.11.1 Single Ended Conversion

For single ended conversion, the result is

where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see

Table 15-3 on page 155 an d Table 15-4 on page 157). 0x 000 represents a nalog ground, and

Output Code

0x3FF

0x000

0VREF Input Voltage

DNL

1 LSB

ADC VIN 1024

VREF

--------------------------=

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0x3FF represents th e selected volta ge refe rence minu s one LSB. The result is presente d in one-

sided form, from 0x3FF to 0x000.

15.11.2 Unipolar Differential Conversion

If differential ch an ne ls an d an un ipo lar inpu t mo d e ar e us ed , the res ult is

where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and VREF the selected voltage reference (see Table 15-3 on page 155 and Table 15-4 on page

157). The voltage on the positive pin must always be larger than the voltage on the negative pin

or otherwise the voltage difference is saturated to zero. The result is presented in one-sided

form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x, 8x, 20x or 32x.

15.11.3 Bipolar Differential Conversion

As default the ADC converter opera tes in the unipolar input mode , but the bipolar input mode

can be selected by writting the BIN bit in the ADCSRB to one. In the bipolar input mode two-

sided voltage differences are allowed and thus the voltage on the negative input pin can also be

larger than the voltage on the positive input pin. If differential channels and a bipolar input mode

are used, the result is

where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and VREF the selecte d voltage referen ce. The result is presented in two’s complement form, from

0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). Th e GAI N is eithe r 1x , 8x, 20 x or 32x .

However, if the signal is not b ipolar by nature (9 bits + sign as the 10t h bit), this scheme loses

one bit of the conver ter dynamic range. Then, if th e user wants to perform the co nversion with

the maximum dynamic range, the user can perform a quick polarity check of the result and use

the unipolar differen tial conversion wi th selectable differential inpu t pair. When the polarity check

is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the

result is negative, and if this bit is zero, the result is positive.

15.12 Temperature Measurement

The temperature measurement is based on an on-chip temperature sensor that is coupled to a

single ended ADC11 channel. Selecting the ADC11 channel by writing the MUX5:0 bits in

ADMUX register to “111111” enables the temperature sensor. The internal 1.1V voltage refer-

ence must also be selected for the ADC voltage reference source in the temperature sensor

measurement. When the temperature sensor is enabled, the ADC converter can be used in sin-

gle conversion mode to measure the voltage over the temperature sensor.

The measured voltage has a linear relationship to the temperature as described in Table 15-2

The sensitivity is approximately 1 LSB / C and th e accuracy depends on the metho d of user cal-

ibration. Typically, the measurement accur acy after a single temperature calibration is ±10C,

ADC VPOS VNEG

–1024

VREF

--------------------------------------------------------GAIN=

ADC VPOS VNEG

–512

VREF

-----------------------------------------------------GAIN=

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assuming calibration at room temperature. Better accuracies are achieved by using two

temperature points for calibration.

The values described in Table 15- 2 are typical values. However, due to process variatio n the

temperature sensor output voltage varies from one chip to another. To be capable of achieving

more accurate results the temperature measurement can be calibrated in the application soft-

ware. The sofware calibration can be done using the formula:

T = k * [(ADCH << 8) | ADCL] + TOS

where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and TOS is

the temperat ure sensor offset. Typi cally, k is very close to 1.0 and in sing le-point ca libration the

coefficient may be omitted. Where higher accuracy is required the slope coefficient should be

evaluate d ba se d on me asurements at two temperatures.

15.13 Register Description

15.13.1 ADMUX – ADC Multiplexer Selection Register

• Bits 7:6 – REFS1:REFS0: Voltage Reference Selection Bits

These bits together with the REFS2 bit from the ADC Control and Status Regist er B (ADCSR B)

select the voltage reference for the ADC, as shown in Table 15-3.

If these bits are changed during a conversion, the change will not go in effect until this conver-

sion is complete (ADIF in ADCSR is set). Also note, that when these bits are changed, the next

conversion will take 25 ADC clock cycles.

Table 15-2. Temperature vs. Sensor Output Voltage (Typical Case)

Temperature -40 C+25 C+85 C

ADC 230 LSB 300 LSB 370 LSB

Bit 76543210

0x07 (0x27) REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 ADMUX

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 15-3. Voltage Reference Selections for ADC

REFS2 REFS1 REFS0 Voltage Reference Selection

X00

VCC used as voltage reference,

disconnected from AREF

X01

External voltage reference at AREF pin,

internal voltage reference turned off

0 1 0 I nternal 1.1V voltage reference

0 1 1 Reserved

110

Internal 2.56V voltage reference,

without external bypass capacitor,

disconnected from AREF

111

Internal 2.56V voltage reference,

with external bypass capacitor at AREF pin

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Special care should be taken when changing differential channels. Once a differential channel

has been selected the input stage may take a while to stabilize. It is therefore recommended to

force the ADC to perfor m a lo ng conver sio n wh en ch an ging mu ltip lexer o r volta ge re fere nce se t-

tings. This can be done by first turning off the ADC, then changing reference settings and then

turn on the ADC. Alternatively, the first conversion results after changing reference settings

should be discarded.

It is not recommended to use an external AREF higher than (VCC - 1V) for channels with differ-

ential gain, as this will affect ADC accuracy.

Internal voltage reference options may not be used if an external voltage is being applied to the

AREF pin.

• Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a comple te description of this bit, see “ADCL and ADCH – The ADC Data Register”

on page 160.

• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits

These bits and the MUX5 b it from the ADC Control and Status Register B (ADCSRB) select

which combination of analog inputs are connected to the ADC. In case of differential input, gain

selection is also m ade with these bits. Selecting the same pin as both inputs t o the differential

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gain stage enables offset measurements. Selecting the single-ended channel ADC11 enables

the temperature sensor. Refer to Table 15-4 for details.

Table 15-4. Input Channel Selections

MUX5:0 Single-Ended

Input

Differential Input

GainPositive Negative

000000 ADC0 (PA0)

NA NA NA

000001 ADC1 (PA1)

000010 ADC2 (PA2)

000011 ADC3 (PA4)

000100 ADC4 (PA5)

000101 ADC5 (PA6)

000110 ADC6 (PA7)

000111 ADC7 (PB4)

001000 ADC8 (PB5)

001001 ADC9 (PB6)

001010 ADC10 (PB7)

001011

ADC0 (PA0) ADC1 (PA1) 20x

001100 ADC0 (PA0) ADC1 (PA1) 1x

001101 ADC1 (PA1) ADC1 (PA1) 20x

001110 ADC2 (PA2) ADC1 (PA1) 20x

001111 ADC2 (PA2) ADC1 (PA1) 1x

010000

N/A

ADC2 (PA2) ADC3 (PA4) 1x

010001 ADC3 (PA4 ) ADC3 (PA4) 20x

010010 ADC4 (PA5 ) ADC3 (PA4) 20x

010011 ADC4 (PA5) A DC3 (PA4) 1x

010100

ADC4 (PA5) ADC5 (PA6) 20x

010101 ADC4 (PA5 ) ADC5 (PA6) 1x

010110 ADC5 (PA6) ADC5 (PA6) 20x

010111 ADC6 (PA7) ADC5 (PA6) 20x

011000 ADC6 (PA7) ADC5 (PA6) 1x

011001

ADC8 (PB5) ADC9 (PB6) 20x

011010 ADC8 (PB5) ADC9 (PB6) 1x

011011 ADC9 (PB6) ADC9 (PB6) 20x

011100 ADC10 (PB7) ADC9 (PB6) 20x

011101 ADC10 (PB7) ADC9 (PB6) 1x

011110 1.1V N/A N/A N/A

011111 0V

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Note: 1. Temperature sensor

100000

N/A

ADC0(PA0) ADC1(PA1) 20x/32x

100001 ADC0(PA0) ADC1(PA1) 1x/8x

100010 ADC1(PA1 ADC0(PA0) 20x/32x

100011 ADC1(PA1) ADC0(PA0) 1x/8x

100100

N/A

ADC1(PA1) ADC2(PA2) 20x/32x

100101 ADC1(PA1) ADC2(PA2) 1x/8x

100110 ADC2(PA2 ADC1(PA1) 20x/32x

100111 ADC2(PA2) ADC1(PA1) 1x/8x

101000

N/A

ADC2(PA2) ADC0(PA0) 20x/32x

101001 ADC2(PA2) ADC0(PA0) 1x/8x

101010 ADC0(PA0) ADC2(PA2) 20x/32x

101011 ADC0(PA0) ADC2(PA2) 1x/8x

101100

N/A

ADC4(PA5) ADC5(PA6) 20x/32x

101101 ADC4(PA5) ADC5(PA6) 1x/8x

101110 ADC5(PA6) ADC4(PA5) 20x/32x

101111 ADC5(PA6) ADC4(PA5) 1x/8x

110000

N/A

ADC5(PA6) ADC6(PA7) 20x/32x

110001 ADC5(PA6) ADC6(PA7) 1x/8x

110010 ADC6(PA7) ADC5(PA6) 20x/32x

110011 ADC6(PA7) ADC5(PA6) 1x/8x

110100

N/A

ADC6(PA7) ADC4(PA5) 20x/32x

110101 ADC6(PA7) ADC4(PA5) 1x/8x

110110 ADC4(PA5) ADC6(PA7) 20x/32x

110111 ADC4(PA5) ADC6(PA7) 1x/8x

111000

N/A

ADC0(PA0) ADC0(PA0) 20x/32x

111001 ADC0(PA0) ADC0(PA0) 1x/8x

111010 ADC1(PA1) ADC1(PA1) 20x/32x

111011 ADC2(PA2) ADC2(PA2) 20x/32x

111100

N/A

ADC4(PA5) ADC4(PA5) 20x/32x

111101 ADC5(PA6) ADC5(PA6) 20x/32x

111110 ADC6(PA7) ADC6(PA7) 20x/32x

111111 ADC11 (1) N/A N/A N/A

Table 15-4. Input Channel Selections (Continued)

MUX5:0 Single-Ended

Input

Differential Input

GainPositive Negative

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If these bits are changed during a conversion, the change will not go into effect until this conver-

sion is complete (ADIF in ADCSRA is set).

15.13.2 ADCSRA – ADC Control and Status Register A

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conve r sion

In Single Conversion mode, write this bit to one to start each conversion. In Free Ru nning mode,

write this bit to one to start th e first conversion. The first conversion after ADSC has been wr itten

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of th e selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set wh en an ADC conver sion comple tes and the data registers are upd ated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and th e inpu t clock

to the ADC.

Bit 76543210

0x06 (0x26) ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 ADCSRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Table 15-5. ADC Prescaler Selections

ADPS2 ADPS1 ADPS0 Division Factor

000 2

001 2

010 4

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15.13.3 ADCL and ADCH – The ADC Data Register

15.13.3.1 ADLAR = 0

15.13.3.2 ADLAR = 1

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (defau lt), the resu lt

is right adjusted.

• ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 153.

011 8

100 16

101 32

110 64

1 1 1 128

Table 15-5. ADC Prescaler Selections (Continued)

ADPS2 ADPS1 ADPS0 Division Factor

Bit 151413121110 9 8

0x05 (0x25) ––––––ADC9 ADC8 ADCH

0x04 (0x24) ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

Bit 151413121110 9 8

0x05 (0x25) ADC9 ADC8 ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADCH

0x04 (0x24) ADC1 ADC0 ––––––ADCL

76543210

Read/WriteRRRRRRRR

RRRRRRRR

Initial Value00000000

00000000

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15.13.4 ADCSRB – ADC Control and Status Register B

• Bit 7 – BIN: Bipolar Input Mode

The gain stag e is wo rking in the unip o lar m od e as de fa ult , b ut th e b ipo la r m o de ca n be se lec te d

by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions

are supported and the voltage on the positive input must always be larger than the voltage on

the negative input. Otherwise th e result is satu rated to the voltag e reference. In the bipolar mode

two-sided conversions are supported and the result is represented in the two’s complement

form. In the unipolar mode the resolutio n is 10 bits and the bip olar mode the re solution is 9 bits +

1 sign bit.

• Bit 6 – GSEL: Gain Select

The Gain Select bit selects the 32x gain in stead of the 20 x gain and the 8 x gain instead of the 1x

gain when the Gain Select bit is written to one.

• Bit 5 – Res: Reserved Bit

This bit is a reserv ed bit in the ATtiny261/461/861 and will always read as zero.

• Bit 4 – REFS2: Reference Selection Bit

These bit selec ts ei ther th e volt age r efer ence o f 1.1 V or 2. 56 V fo r the ADC, as shown in Table

15-3. If active channels are used, using AVCC or an external AREF higher than (AVCC - 1V) is

not recommended, as this will affect ADC accuracy. The internal voltage reference options may

not be used if an external voltage is being applied to the AREF pin.

• Bit 3 – MUX5: Analog Channel and Gain Selection Bit 5

The MUX5 bit is the MSB of the Analog Chan nel and Gain Selection bits. Refer to Table 1 5-4 for

details. If this bit is changed during a conver sion, the change will not go into effect until this

conversion is complete (ADIF in ADCSRA is set).

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Bit 76543210

0x03 (0x23) BIN GSEL - REFS2 MUX5 ADTS2 ADTS1 ADTS0 ADCSRB

Read/Write R/W R/W R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

Table 15-6. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

0 0 0 Free Running mode

0 0 1 Analog Comparator

0 1 0 External Interrupt Request 0

0 1 1 Timer/Counter0 Compare Match A

1 0 0 Timer/Counter0 Overflow

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15.13.5 DIDR0 – Digital Input Disable Register 0

• Bits 7:4,2:0 – ADC6D:ADC0D: ADC6:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

• Bit 3 – AREFD: AREF Digital Input Disable

When this bit is written logic one, the digital input buffer on the AREF pin is disabled. The corre-

sponding PIN register bit will always read as zero when this bit is set. When an analog signal is

applied to the AREF pin and the digita l input from this pin is not need ed, this bit should be written

logic one to reduce power consump tion in the digital input buffer.

15.13.6 DIDR1 – Digital Input Disable Register 1

• Bits 7:4 – ADC10D:ADC7D: ADC10:7 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC10:7 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

1 0 1 Timer/Counter0 Compare Match B

1 1 0 Timer/Counter1 Overflow

1 1 1 Watchdog Interrupt Request

Table 15-6. ADC Auto Trigger Source Selections

ADTS2 ADTS1 ADTS0 Trigger Source

Bit 76543210

0x01 (0x21) ADC6D ADC5D ADC4D ADC3D AREFD ADC2D ADC1D ADC0D DIDR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

Bit 76543210

0x02 (0x22) ADC10D ADC9D ADC8D ADC7D - DIDR1

Read/Write R/WR/WR/WR/W R R R R

Initial Value 0 0 0 0 0 0 0 0

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16. debugWIRE On-chip Debug System

16.1 Features •Complete Program Flow Control

•Emulates All On-chip Functions, Both Digit a l and Analog , except RESET Pin

•Real-time Operation

•Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

•Unlimited Number of Program Break Points (Using Software Break Points)

•Non-intrusive Operation

•Electrical Characteristics Id entical to Real Device

•Automatic Configuration System

•High-Speed Operation

•Programming of Non-volatile Memories

16.2 Overview The debugWIRE On-chip deb ug system uses a One-wire, bi-directional interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

16.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 16-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL Fuses.

Figure 16-1. The debugWIRE Setup

GND

dW(RESET)

VCC

1.8 - 5.5

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When designing a system where debugWIRE will be used, the following must be observed:

• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 k. However, the

pull-up resistor is optional.

• Connecting the RESET pin directly to VCC will not work.

• Capacitors inserted on the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

16.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio® will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-prog rammed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Falsh Data retention. Devices used fo r debugg ing purpose s should not b e shipped to

end customers.

16.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,

when the program in the CPU is running. When the CPU is stopped, care must be taken while

accessing some of the I/O Registers via the debugger (AVR Studio). See the debugWIRE docu-

mentation for detailed description of the limitations.

The debugWIRE interface is asynchronous, which means that the debugger needs to synchro-

nize to the system clock. If the system clock is changed by software (e.g. by writing CLKPS bits)

communication via debugWIRE may fail. Also, clock frequencies below 100 kHz may cause

communication problems.

A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWire is not used.

16.6 Register Description

The following section de scr ib es th e re gis te rs us ed with th e debu g Wire .

16.6.1 DWDR – debugWire Data Register

The DWDR Register provides a communicatio n channel from the running program in the MCU

to the debugger. This register is only acce ssible by the debugWIRE and can therefore not be

used as a general purpose register in the normal operations.

Bit 76543210

0x20 (0x40) DWDR[7:0] DWDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

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17. Self-Programming the Flash

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory. The SPM

instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse

(to “0”).

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the tempo rary page buffer, the page must be era sed. The temporary pag e buf-

fer is filled one word at a time using SPM and the buffer can be filled either before the Pag e

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,

the Boot Loader provides an effe ctive Read- Mod ify- Write fe atur e which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not p ossible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the

same page.

17.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Othe r bits in the Z-pointer will

be ignored during this operation.

Note: The CPU is halted during the Page Erase operation.

17.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. Th e

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

17.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

Note: The CPU is halted during the Page Write operation.

17.4 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Since the Flash is organized in pages (see Table 18-7 on page 173), the Program Counter can

be treated as having two differ ent sections. One section, cons isting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 17-1. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the software addresses the

same page in both the Page Erase and Page Write operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-b y-b yt e, also the LSB (bit Z0) of the Z-po in te r is used .

Figure 17-1. Addressing the Flash During SPM

Note: The different variables used in Figure 17-1 are listed in Table 18-7 on page 173 .

Bit 1514131211109 8

ZH (R31) Z15 Z 14 Z13 Z12 Z11 Z10 Z9 Z8

ZL (R30)Z7Z6Z5Z4Z3Z2Z1Z0

76543210

PROGRAM MEMORY

0115

Z - REGISTER

BIT

ZPAGEMSB

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

ZPCMSB

INSTRUCTION WORD

PA G E PCWORD[PAGEMSB:0]:

PAGEEND

PA G E

PCWORDPCPAGE

PCMSB PAGEMSB

PROGRAM

COUNTER

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17.5 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

17.6 Reading Fuse and Lock Bits from Software

It is possible for firmware to read device fuse and lock bits.

Note: Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-

grammed, will be read as one.

17.6.1 Reading Lock Bits from Firmware

Lock bit values are r etur ned in th e des tinatio n re gister afte r an L PM instr uctio n has been issu ed

within three CPU cycles after RFLB and SELFPRG EN bits have been set in SPMCSR. The

RFLB and SELFPRGEN bits autom atically clear upon completion of reading the lock bits, or if no

LPM instruction is executed within three CPU cycles, or if no SPM instruction is executed within

four CPU cycles. When RFLB and SELFPRGEN are cleared LPM functions normally.

To read the lock bits, follow the below procedure:

1. Load the Z-pointer with 0x0001.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issue an LPM instruction withi n three clock cycles.

4. Read the lock bits from the LPM destination register.

If successful, the contents of the destination register are as follows.

See section “Program And Data Memory Lock Bits” on page 170 for more information.

17.6.2 Reading Fuse Bits from Firmware

The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,

only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:

1. Load the Z-pointer with 0x0000.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issue an LPM instruction withi n three clock cycles.

4. Read the FLB from the LPM destination register.

If successful, the contents of the destination register are as follows.

Refer to Table 18-5 on page 172 for a detailed description and mapping of the Fuse Low Byte.

Bit 76543210

Rd ––––––LB2LB1

Bit 76543210

Rd FLB7 FLB6 FLB5 FLB4 FLB3 FLB2 FLB1 FLB0

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To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and

repeat the procedure above. If succe ssful, the contents of the destination re gister are as follo ws.

Refer to Table 18-4 on page 171 for detailed description and mapping of the Fuse High Byte.

To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and

repeat the previous procedu re. If successful, the contents of the destination register are as

follows.

Refer to Table 18-3 on page 171 for detailed description and mapping of the Fuse Extended

Byte.

17.7 Preventing Flash Corruption

During periods of low VCC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program co rr uptio n can be caus ed b y two situ atio ns when th e voltag e is too low. Fi rst, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (o ne is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling th e internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low VCC reset protection circuit

can be used. If a reset occurs while a write operation is in progr ess, the write operation

will be completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low VCC. This will pre-

vent the CPU from attemp ting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

17.8 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 17-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

Note: 1. Minimum and maximum programming time is per individual operation.

Bit 76543210

Rd FHB7 FHB6 FHB5 FHB4 FHB3 FHB2 FHB1 FHB0

Bit 76543210

Rd FEB7 FEB6 FEB5 FEB4 FEB3 FEB2 FEB1 FEB0

Table 17-1. SPM Programming Time(1)

Symbol Min Programming Time Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM) 3.7 ms 4 .5 ms

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17.9 Register Description

17.9.1 SPMCSR – Sto r e Program Memory Control and Status Register

The Store Program Me mory Control an d Status Regi ster contains the control bits n eeded to con-

trol the Program memory operations.

• Bits 7:5 – Res: Reserved Bits

These bits are reserved and always read as zero.

• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within thr ee cycles after RF LB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See “EEPROM Write Prevents Writing to SPMCSR” on page 167 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If written to one together with

either CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have a special

meaning, see descript ion above. If only SPMEN is written, the following SPM instru ction will

store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The LSB of

the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM instruction,

or if no SPM instruction is executed within fo ur cloc k cycles. During Page Erase and Page Write,

the SPMEN bit remains high until the operation is completed.

Writing any other combination than “10001”, “01001”, “00101”, “00011” or “00001” in the lower

five bits will have no effect.

Bit 76 54 3 210

0x37 (0x57) – – – CTPB RFLB PGWRT PGERS SPMEN SPMCSR

Read/Write R R R R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 0 0 0 0

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18. Memory Programming

This section describes the different methods for pr ogramming ATtiny261/461/861 memories.

18.1 Program And Data Memory Lock Bits

The ATtiny261/461/86 1 provides two lock bits which can be left unprogrammed (“1”) or can be

programmed (“0”) to obtain the additional security listed in Table 18-2. The lock bits can only be

erased to “1” with the Chip Erase command.

The device has no sepa rate boot loader section. The SPM inst ruction is enabled for the whol e

Flash, if the SELFPROGEN fuse is programmed (“0”), otherwise it is disabled.

Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro-

grammed, even if lock bits are set. Thus, when lock bit security is required, debugWIRE should

always be disabled by clearing the DWEN fuse.

Note: “1” means unprogrammed, “0” means programmed.

Notes: 1. Program fuse bits before programming LB1 and LB2.

2. “1” means unprogramme d, “0” means programme d.

Lock bits can also be read by device firmware. See section “Reading Fuse and Lo ck Bits from

Software” on page 167.

Table 18-1. Lock Bit Byte

Lock Bit Byte Bit No Description Default Value

7 – 1 (unprogrammed)

6 – 1 (unprogrammed)

5 – 1 (unprogrammed)

4 – 1 (unprogrammed)

3 – 1 (unprogrammed)

2 – 1 (unprogrammed)

LB2 1 Lock bit 1 (unprogrammed)

LB1 0 Lock bit 1 (unprogrammed)

Table 18-2. Lock Bit Protection Modes.

Memory Lock Bits (1) (2) Protection Type

LB Mode LB2 LB1

1 1 1 No memory lock features enabled.

210

Further programming of the Flash and EEPROM is disabled in

High-voltage and Serial Programming mode. The Fuse bits are

locked in both Serial and High-voltage Programmi ng mode.(1)

300

Further programming and verification of the Flash and EEPROM

is disabled in High-voltage and Serial Programming mode. The

Fuse bits are locked in both Serial and High-voltage

Programming mode.(1)

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18.2 Fuse Bytes The ATtiny261/461/861 have three fuse bytes. Table 18-3, Table 18-4 and Table 18-5 describe

briefly the functionality o f all the fuses and ho w they are mapped into the fuse byte s. Note that

the fuses are read as logical zero, “0”, if they are programmed.

Notes: 1. Enables SPM instruction. See “Se lf-Programming the Flash” on page 165 .

Notes: 1. See “Alternate Functio ns of Port B” on page 66 for description of RSTDISBL and DWEN

Fuses. After programming the RSTDISBL fuse, parallel programming must be used to change

fuses and allow further programming.

2. DWEN must be unprogrammed when Lock Bit security is required. See “Program And Data

Memory Lock Bits” on page 170.

3. The SPIEN Fuse is not accessible in SPI programming mode.

4. Programming this fues will disa ble the Watchdog Timer Interrupt. See “WDTCR – Watchdog

Timer Control Register” on page 47 for details.

5. See Table 19-6 on page 191 for BODLEVEL Fuse decoding.

Table 18-3. Fuse Extended Byte

Fuse High Byte B it No Description Default Value

7 - 1 (unprogrammed)

6 - 1 (unprogrammed)

5 - 1 (unprogrammed)

4 - 1 (unprogrammed)

3 - 1 (unprogrammed)

2 - 1 (unprogrammed)

1 - 1 (unprogrammed)

SELFPRGEN (1) 0 Self-Programming Enable 1 (unprogrammed)

Table 18-4. Fuse High Byte

Fuse High Byte Bit No Description Default Value

RSTDISBL (1) 7 External Reset disable 1 (unprogrammed)

DWEN (2) 6 DebugWIRE Enable 1 (unprogrammed)

SPIEN (3))6Enable Serial Program and Data

Downloading 0 (programmed, SPI prog.

enabled)

WDTON (4) 4 Watchdog Timer always on 1 (unprogrammed)

EESAVE 3 EEPROM memory is preserved

through the Chip Erase 1 (unprogrammed, EEPROM

not preserved)

BODLEVEL2 (5) 2 Brown-out Detector trigger level 1 (unprogrammed)

BODLEVEL1 (5) 1 Brown-out Detector trigger level 1 (unprogrammed)

BODLEVEL0 (5) 0 Brown-out Detector trigger level 1 (unprogrammed)

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Notes: 1. See “System Clock Prescaler” on pag e 31 for details.

2. Allows system clock to be output on pin. See “Clock Output Buffer” on page 32 for details.

3. The default value results in maximum start-up time for the default clock source. See Table 6-7

on page 28 for details.

4. The default setting resu lts in inte rnal RC Oscillator @ 8.0 MHz. See Table 6-6 on page 28 for

details.

Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro-

grammed before lock bits. The status of fuse bits is not affected by chip erase.

Fuse bits can also be read by device firmware. See section “Reading F use and Lock Bits fr om

Software” on page 167.

18.2.1 Latching of Fuses

Fuse values are latched when the device enters progra mming mode and ch anges to fuse values

have no effect until the par t leav es programming mode. This does not app ly to the EESAVE

Fuse which will take effect once it is programmed. Fuses are also latched on power-up.

18.3 Signature Bytes

All Atmel microcontrollers have a three- byte signature code which identifies the device. This

code can be read in both serial and High-voltage Programm ing mode, also when the de vice is

locked. The three bytes reside in a separate address space. The ATtiny261/461/861signature

bytes are given in Table 18-6 .

Table 18-5. Fuse Low Byte

Fuse Low Byte Bit No Description Default Value

CKDIV8 (1) 7 Divide clock by 8 0 (programmed)

CKOUT (2) 6 Clock Output Enable 1 (unprogrammed)

SUT1 5 Select start-up time 1 (unprogrammed) (3)

SUT0 4 Select start-up time 0 (programmed) (3)

CKSEL3 3 Select Clock source 0 (programmed) (4)

CKSEL2 2 Select Clock source 0 (programmed) (4)

CKSEL1 1 Select Clock source 1 (unprogrammed) (4)

CKSEL0 0 Select Clock source 0 (programmed) (4)

Table 18-6. Device ID

Parts

Signature Bytes Address

0x000 0x001 0x002

ATtiny261 0x1E 0x91 0x0C

ATtiny461 0x1E 0x92 0x08

ATtiny861 0x1E 0x93 0x0D

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18.4 Calibration Byte

Signature area of the ATtiny261/461/861 has one byte of calibration data for the internal RC

Oscillator. This byte resides in the high byte of address 0x000. During reset, this byte is auto-

matically written into the OSCCAL Register to ensure correct frequency of the calibrated RC

Oscillator.

18.5 Page Size

18.6 Serial Programming

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (inpu t) and MISO (out-

put). See Figure 18-1.

Figure 18-1. Serial Programming and Verify

Note: If the device is clocked by the internal Oscillator , there is no need to connect a clock source to the

CLKI pin.

Table 18-7. No. of Words in a Page and No. of Pages in the Flash

Device Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB

ATtiny261 1K words (2K bytes) 16 words PC[3:0] 64 PC[9:4] 9

ATtiny461 2K words (4K bytes) 32 words PC[4:0] 64 PC[10:5] 10

ATtiny861 4K words (8K bytes) 32 words PC[4:0] 128 PC[11:5] 11

Table 18-8. No. of Words in a Page and No. of Pages in the EEPROM

Device EEPROM

Size Page Size PCWORD No. of Pages PCPAGE EEAMSB

ATtiny261 128 bytes 4 bytes EEA[1:0] 32 EEA[6:2] 6

ATtiny461 256 bytes 4 bytes EEA[1:0] 64 EEA[7:2] 7

ATtiny861 512 bytes 4 bytes EEA[1:0] 128 EEA[8:2] 8

VCC

GND

SCK

MISO

MOSI

RESET

+1.8 - 5.5V

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After RESET is set low, the Prog ramming Enable in struction needs to be executed first before

program/erase operations can be executed.

Note: In Table 18-9, above, the pin mapping for SPI programming is listed. Not all parts use the SPI pins

dedicated for the internal SPI interface.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

• Low:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

• High:> 2 CPU clock cycles for fck < 12 MHz, 3 CPU clock cycles for fck >= 12 MHz

18.6.1 Serial Programming Algorithm

When writing serial data to the ATtiny261/461/861, data is clocked on the rising edge of SCK.

When reading, data is clocked on the falling edge of SCK. See Figure 19-4 and Figure 19-5 for

timing details.

To program and verify the ATtiny261/461/861 in the Serial Programming mode, the following

sequence is recomme nded (see four byte instruction formats in Table 18-11):

1. Power-up sequence:

Apply power between VCC and GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse after SCK has been set to '0'. The duration

of the pulse must be at least tRST (the minimum pulse width on RESET pin, see Table

19-4 on page 190) plus two CPU clock cycles.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Progr amming Enable instruction. Whethe r the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable comm and.

4. The Flash is programmed one page at a time. The memory pa ge is loaded one byte at

a time by supplying the 5 LSB of the addre ss and dat a together with the Load Progra m

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 6 MSB

of the address. If polling (RDY/BSY) is not used, the user must wait at least tWD_FLASH

before issuing the next page. (See Table 18-10.) Accessing the serial programming

Table 18-9. Pin Mapping Serial Programming

Symbol Pins I/O Description

MOSI PB0 I Serial Data in

MISO PB1 O Serial Data out

SCK PB2 I Serial Clock

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interface before the Fl ash write operation completes can result in incorrect

programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling (RDY/BSY) is not used,

the user must wait at least tWD_EEPROM before issuing the next byte. (See Table 18-10.)

In a chip erased device, no 0xFFs in the data file(s) need to be pr ogrammed.

B: The EEPROM array is programmed one page at a time. The Memory p age is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the

Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by

loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.

When using EEPROM page access only byte locations loaded with the Load EEPROM

Memory Page instruction is altered. The remaining locations remain unchanged. If poll-

ing (RDY/BSY) is not used, the used must wait at least tWD_EEPROM before issuing the

next page (Se e Table 18-8). In a chip erased device, no 0xFF in the data file(s) need to

be programmed.

6. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn VCC power off.

18.6.2 Serial Programming Instruction set

The instruction set is described in Table 18-11 on page 176 and Figure 18-2 on page 177.

Table 18-10. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol Minimum Wait Delay

tWD_FLASH 4.5 ms

tWD_EEPROM 4.0 ms

tWD_ERASE 9.0 ms

tWD_FUSE 4.5 ms

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Notes: 1. Not all instructions are applicable for all parts.

2. a = address

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure fu ture compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibratio n and Signature bytes and Page size.

6. Instructions accessing program memory use a word address. Th is address may be rando m within the page range.

7. See http://www.atmel.com/avr for Application Notes regarding programming and programmers.

Table 18-11. Serial Programming Instruction Set

Instruction/Operation

Instruction Format

Byte 1 Byte 2 Byte 3 Byte4

Programming Enable $AC $53 $00 $00

Chip Erase (Program Memory/EEPROM) $AC $80 $00 $00

Poll RDY/BSY $F0 $00 $00 data byte out

Load Instructions

Load Extended Address byte(1) $4D $00 Extended adr $00

Load Program Memory Page, High byte $48 adr MSB adr LSB high data byte in

Load Program Memory Page, Low byte $40 adr MSB adr LSB low data byte in

Load EEPROM Memory Pag e (page access) $C1 $00 0000 000aa data byte in

Read Instructions

Read Progra m Memory, High byte $28 adr MSB adr LSB high data byt e out

Read Program Memory, Low byte $20 adr MSB adr LSB low data byte out

Read EEPROM Memory $A0 $00 00aa aaaa data byte out

Read Lock bits $58 $00 $00 data byte out

Read Signature Byte $30 $00 0000 000aa data byte out

Read Fuse bits $50 $00 $00 data byte out

Read Fuse High bits $58 $08 $00 data byte out

Read Extended Fuse Bits $50 $08 $00 data byte out

Read Calibration Byte $38 $00 $00 data byte out

Writ e Instru cti on s(6)

Write Program Memory Page $4C adr MSB adr LSB $00

Write EEPROM Memory $C0 $00 00aa aaaa data byte in

Write EEPROM Memory Page (page access) $C2 $00 00aa aa00 $00

Write Lock bits $AC $E0 $00 data byte in

Write Fuse bits $AC $A0 $00 data byte in

Write Fuse High bits $AC $A8 $00 data byte in

Write Extended Fuse Bits $AC $A4 $00 data byte in

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Figure 18-2. Serial Programming Instruction example

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 18-2 on page

177.

18.7 Parallel Programming

This section describes how to parallel program and verify Flash Program memory, EEPROM

Data memory, Memo ry Lock bits, and Fuse bits. Pulses are assumed to be at lea st 250 ns in

length, unless otherwise noted.

18.7.1 Signal Names In this section, some pins are referenced by signal names describing their functionality during

parallel programming, see Figure 18-3 and Table 18-12. Pins not described in the fo llowing table

are referenced by pin names.

Byte 1 Byte 2 Byte 3 Byte 4

Adr MSB Adr LSB

Bit 15 B 0

Serial Programming Instruction

Program Memory/

EEPROM Memory

Page 0

Page 1

Page 2

Page N-1

Page Buffer

Write Program Memory Page/

Write EEPROM Memory Page

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Byte 1 Byte 2 Byte 3 Byte 4

Bit 15 B 0

Adr MSB Adr LSB

Page Offset

Page Number

Adr

dr M

r MS

Adr

dr LS

LSB

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Figure 18-3. Parallel Programming.

Table 18-12. Pin Name Mapping

Signal Name in

Programming Mode Pin

Name I/O Function

WR PB0 I W rite Pulse (Active low).

XA0 PB1 I XTAL Action Bit 0

XA1/BS2 PB2 I XTAL Action Bit 1. Byte Select 2 (“0” selects low byte, “1”

selects 2’nd high byte).

PAGEL/BS1 PB3 I Byte Select 1 (“0” selects low byte, “1” selects high byte).

Program Memory and EEPROM Data Page Load.

OE PB5 I Output Enable (Active low).

RDY/BSY PB6 O 0: Device is busy programming, 1: Device is ready for new

command.

DATA I/O PA7-PA0 I/O Bi-directional Data bus (Output when OE is low).

VCC

+5V

GND

XTAL1/PB4

PB6

PB5

PB0

PB3

PB1

PB2

PA7 - PA0 DATA

RESET

+12 V

PAGEL/BS1

XA0

XA1/BS2

RDY/BSY

AVCC

+5V

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The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive pulse.

The bit coding is shown in Table 18-14 .

When pulsing WR or OE, the com mand loaded determines the action executed. The different

Commands are shown in Table 18-15.

18.7.2 Entering Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V be twe e n V CC and GND.

2. Set RESET to “0” and toggle XTAL1 at least six times.

3. Set Prog_enable pins listed in Table 18-13 o n page 179 to “0000” and wait at least 100

ns.

4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after

+12V has been applied to RESET, will cause the device to fail entering programming

mode.

5. Wait at least 50 µs before sending a new command.

Table 18-13. Pin Values Used to Enter Programming Mode

Pin Symbol Value

PAGEL/BS1 Prog_enable[3] 0

XA1/BS2 Prog_enable[2] 0

XA0 Prog_enable[1] 0

WR Prog_enable[0] 0

Table 18-14. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

0 0 Load Flash or EEPROM Address (High or low address by te determined by BS1).

0 1 Load Data (High or Low data byte for Flash determined by BS1).

1 0 Load Command

1 1 No Action, Idle

Table 18-15. Command Byte Bit Coding

Command Byte Command Executed

1000 0000 Chip Erase

0100 0000 Write Fuse bits

0010 0000 Write Lock bits

0001 0000 Write Flash

0001 0001 Write EEPROM

0000 1000 Read Signature Bytes and Calibration byte

0000 0100 Read Fu se and Lock bits

0000 0010 Read Flash

0000 0011 Read EEPROM

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18.7.3 Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered:

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address high byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

18.7.4 Chip Erase The Chip Erase will erase the Flash and EEPROM memories plus lock bits. The Lock bits are

not reset until the program memory has been completely erased. The Fuse bits are not

changed. A Chip Erase must be performed before the Flash and/or EEPROM are

reprogrammed.

1. Load Command “Chip Erase”:

a. Set XA1, XA0 to “10”. This enab les command loading.

b. Set BS1 to “0”.

c. Set DATA to “1000 0000”. This is the command for Chip Erase.

d. Give XTAL1 a positive pulse. This loads the command.

e. Give WR a negative pulse . Th is starts the Chip Erase. RDY/BSY goes low.

f. Wait until RDY/BSY goes high before loading a new command.

Note: The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

18.7.5 Programming the Flash

The Flash is organized in pages, see Table 18-7 on page 173. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory (see Figure 18-5 for signal waveforms):

1. Load Command “Write Flash”:

a. Set XA1, XA0 to “10”. This enab les command loading.

b. Set BS1 to “0”.

c. Set DATA to “0001 0000”. This is the command for Write Flash.

d. Give XTAL1 a positive pulse. This loads the command.

2. Load Address Low byte:

a. Set XA1, XA0 to “00”. This enables address loading.

b. Keep BS1 at “0”. This selects low address.

c. Set DATA = Address low byte (0x00 - 0xFF).

d. Give XTAL1 a positive pulse. This loads the ad dress low byte.

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3. Load Data Low Byte:

a. Set XA1, XA0 to “01”. This enables data loading.

b. Set DATA = Data low byte (0x00 - 0xFF).

c. Give XTAL1 a positive pulse. This loads the data byte.

4. Load Data High Byte:

a. Set BS1 to “1”. This selects high data byte.

b. Keep XA1, XA0 at “01”. This en ables data loading.

c. Set DATA = Data high byte (0x00 - 0xFF).

d. Give XTAL1 a positive pulse. This loads the data byte.

5. Repeat steps 2 to 4 until the entire buffer is filled or until all data within the page is

loaded.

6. Load Address High byte:

a. Set XA1, XA0 to “00”. This enables address loading.

b. Set BS1 to “1”. This select s high address.

c. Set DATA = Address high byte (0x00 - 0xFF).

d. Give XTAL1 a positive pulse. This loads the ad dress high byte.

7. Program Page:

a. Give WR a negative pulse . This s tarts programming of the entire page of data.

RDY/BSY goes low.

b. Wait until RDY/BSY goes high.

8. Repeat steps 2 to 7 until the entire Flash is programmed or until all data has been

programmed.

9. End Page Programming:

a. Set XA1, XA0 to “10”. This enab les command loading.

b. Set DATA to “0000 0000”. This is the command for No Operation.

c. Give XTAL1 a positive pulse. This loads the command, and the internal write sig-

nals are reset.

While the lower bits in the add ress a re mapped to words within th e page, th e highe r bits addr ess

the pages within the FLASH. This is illustrated in Figure 18-4. Note that if less than eight bits are

required to addre ss words in the page (pagesize < 256), the most significant bi t(s) in the address

low byte are used to address the page when pe rforming a Page Write.

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Figure 18-4. Addressing the Flash Which is Organized in Pages

Note: PCPAGE and PCWORD are listed in Table 18-7 on pag e 173 .

In the figure below, “XX” means don’t care. The numbers in the figure refer to the programming

description above.

Figure 18-5. Flash Progra mm in g Wav ef or m s

18.7.6 Programming the EEPROM

The EEPROM is organized in pages, see Table 18-8 on page 173. When programming the

EEPROM, the program data is latched into a page buffer. This allows one page of data to be

PROGRAM MEMORY

WORD ADDRESS

WITHIN A PAGE

PAGE ADDRESS

WITHIN THE FLASH

INSTRUCTION WORD

PA G E PCWORD[PAGEMSB:0]:

PAGEEND

PA G E

PCWORDPCPAGE

PCMSBPAGEMSB

PROGRAM

COUNTER

0x10 ADDR. LOW DATA LOW ADDR. HIGHDATA HIGHDATA LOWADDR. LOWDATA HIGHDATA

XA1 / BS2

XA0

PAGEL / BS1

XTAL1

RDY / BSY

RESET +12V

XXX

STEP

6432432

0x00

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programmed simultaneously. The programming algorithm for the EEPROM data memory is as

follows (refer to “Programming the F lash” on page 180 for details o n Command, Address and

Data loading):

1. A: Load Command “0001 0001”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. C: Load Data (0x00 - 0xFF).

5. E: Latch data (give PAGEL a positive pulse).

6. K: Repeat 3 through 5 until the entire buffer is filled.

7. L: Program EEPROM pa ge

a. Set BS to “0”.

b. Give WR a negative pulse. This starts programming of the EEPROM page.

RDY/BSY goes low.

c. Wait until to RDY/BSY goes high before programming the next page (See Figure

18-6 for signal waveforms).

Figure 18-6. Programming the EEPROM Waveforms

18.7.7 Reading the Flash

The algorithm for reading the Flash m emory is as follows (refer to “Programming the Flash” on

page 180 for details on Command and Address loading):

1. A: Load Command “0000 0010”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.

5. Set BS to “1”. The Flash word high byte can now be read at DATA.

6. Set OE to “1”.

RDY/BSY

RESET +12V

0x11 ADDR. HIGH

DATA ADDR. LOW DATA ADDR. LOW DATA XX

XA1/BS2

XA0

PAGEL/BS1

XTAL1

AGBCEB C EL

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18.7.8 Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to “Programming the Flash”

on page 180 for details on Command and Address loading):

1. A: Load Command “0000 0011”.

2. G: Load Address High Byte (0x00 - 0xFF).

3. B: Load Address Low Byte (0x00 - 0xFF).

4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.

5. Set OE to “1”.

18.7.9 Programming the Fuse Low Bits

The algorith m for program ming the Fu se Lo w bits is as follows (refer to “Progra mming the Flash”

on page 180 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Give WR a negative pulse and wait for RDY/BS Y to go high.

18.7.10 Programming the Fuse High Bits

The algorithm for programming the Fuse High bits is as follows (refer to “Programming the

Flash” on page 180 for details on Command and Data loading):

1. A: Load Command “0100 0000”.

2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. Set BS1 to “1” and BS2 to “0”. This select s high data byte.

4. Give WR a negative pulse and wait for RDY/BS Y to go high.

5. Set BS1 to “0”. This selects low data byte.

18.7.11 Programming the Extended Fuse Bits

The algorithm for programming the Extended Fuse bits is as follows (refer to “Progr amming th e

Flash” on page 180 for details on Command and Data loading):

1. 1. A: Load Command “0100 0000”.

2. 2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

3. 3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.

4. 4. Give WR a negative pulse and wait for RDY/BSY to go high.

5. 5. Set BS2 to “0”. This selects low data byte.

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Figure 18-7. Programming the FUSES Waveforms

18.7.12 Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on

page 180 for details on Command and Data loading):

1. A: Load Command “0010 0000”.

2. C: Load Dat a Low Byte. Bit n = “ 0” pr og rams th e L ock bit. If L B mode 3 is pr ogram med

(LB1 and LB2 is programmed), it is no t possible to program the Boot Lock bits by any

External Programming mode.

3. Give WR a negative pulse and wait for RDY/BS Y to go high.

The Lock bits can only be cleared by executing Chip Erase.

18.7.13 Reading the Fuse and Lock Bits

The algorithm for readin g the Fuse and Lock bits is as follows (refer to “Programming the Flash”

on page 180 for details on Command loading):

1. A: Load Command “0000 0100”.

2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be

read at DATA (“0” means programmed).

3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be

read at DATA (“0” means programmed).

4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The sta tus of the Extended Fuse bits can now

be read at DATA (“0” means programmed).

5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The st atus of the Lock bits can now be read at

DATA (“0” means programmed).

6. Set OE to “1”.

RDY/BSY

RESET +12V

0x40

DATA DATA XX

XA1/BS2

XA0

PAGEL/BS1

XTAL1

0x40 DATA XX

Write Fuse Low byte Write Fuse high byte

0x40 DATA XX

Write Extended Fuse byte

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Figure 18-8. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read

18.7.14 Reading the Signature Bytes

The algorithm for reading the Signature bytes is as follows (refer to “Programm i ng t he F lash” on

page 180 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte (0x00 - 0x02).

3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.

4. Set OE to “1”.

18.7.15 Reading the Calibration Byte

The algorithm for reading the Calibration byte is as follows (refer to “Progr am ming the F las h” o n

page 180 for details on Command and Address loading):

1. A: Load Command “0000 1000”.

2. B: Load Address Low Byte, 0x00.

3. Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.

4. Set OE to “1”.

Lock Bits 0

BS2

Fuse High Byte

BS1

DATA

Fuse Low Byte 0

BS2

Extended Fuse Byte

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19. Electrical Characteristics

19.1 Absolute Maximum Ratings*

19.2 DC Characteristics

Operating Temperature...... ... ......................... -55C to +125C*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to VCC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin............................................... 40.0 mA

DC Current VCC and GND Pins................................ 200.0 mA

Table 19-1. DC Characteristics. TA = -40C to +85C, VCC = 1.8V to 5.5V (unless otherwise noted).

Symbol Parameter Condition Min Typ (1) Max Units

VIL Input Low-voltage

Except XTAL1 and

RESET pins -0.5 0.2VCC(3) V

XTAL1 pin ,

External Clock Selected -0.5 0.1VCC(3) V

RESET pin -0.5 0.2VCC(3) V

RESET pin as I/O -0.5 0.2VCC(3) V

VIH Input High-voltage

Except XTAL1 and

RESET pins 0.7VCC(2) VCC +0.5 V

XTAL1 pin ,

External Clock Selected 0.8VCC(2) VCC +0.5 V

RESET pin 0.9VCC(2) VCC +0.5 V

RESET pin as I/O 0.7VCC(2) VCC +0.5 V

VOL Output Low Voltage (4)

(Except Reset pin) (6) IOL = 10 mA, VCC = 5V

IOL = 5 mA, VCC = 3V 0.6

0.5 V

VOH Output High-voltage (5)

(Except Reset pin) (6) IOH = -10 mA, VCC = 5V

IOH = -5 mA, VCC = 3V 4.3

2.5 V

IIL Input Leakage

Current I/O Pin Vcc = 5.5V, pin low

(absolute value) < 0.05 1 µA

IIH Input Leakage

Current I/O Pin Vcc = 5.5V, pin high

(absolute value) < 0.05 1 µA

RRST Reset Pull-up Resistor 30 60 k

RPU I/O Pin Pull-up Resistor 20 50 k

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Notes: 1. Typical values at +25C.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. “Max” means the highest value where the pin is guaranteed to be read as low.

4. Although each I/O port can sink more than the test cond itions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state

conditions (non-transient), the sum of all IOL (for all ports) should not exceed 60 mA. If IOL exceeds the test conditions, VOL

may exceed the related specification. Pins are not gua ranteed to sink current greater than the listed test condition.

5. Although each I/O port can source more than the test conditions (10 mA at VCC = 5V, 5 mA at VCC = 3V) under steady state

conditions (non-transient), the sum of all IOH (for all ports) should not exceed 60 mA. If IOH exceeds the test condition, VOH

may exceed the related specification. Pins are no t guaranteed to source current greater than the listed test condition.

6. The RESET pin must tolerate high voltages when enterin g and operating in programming modes and, as a consequence,

has a weak drive strength as compared to regular I/O pins. See Figure 20-23, Figure 20-24, Figure 20-25, and Figure 20-26

(starting on page 209).

7. Values are with external clock using methods described in “Minimizing Power Consumption” on page 37. Power Reduction

is enabled (PRR = 0xFF) and there is no I/O drive.

8. BOD Disabled.

19.3 Speed The maximum operating frequency of the device depends on VCC. As shown in Figure 19-1 and

Figure 19 -2, the maximum frequency vs. VCC relationship is linear between 1.8V < VCC < 2.7V

and between 2.7V < VCC < 4.5V.

Figure 19-1. Maximum Frequency vs. VCC (ATtiny261V/461V/861V)

ICC

Power Supply Current (7)

Active 1MHz, VCC = 2V 0.4 0.6 mA

Active 4MHz, VCC = 3V 2 3 mA

Active 8MHz, VCC = 5V 6 9 mA

Idle 1MHz, VCC = 2V 0.1 0.3 mA

Idle 4MHz, VCC = 3V 0.4 1 mA

Idle 8MHz, VCC = 5V 1.5 3 mA

Power-down mode (8) WDT enabled, VCC = 3V 4 10 µA

WDT disabled, VCC = 3V 0.15 2 µA

Table 19-1. DC Characteristics. TA = -40C to +85C, VCC = 1.8V to 5.5V (unless otherwise noted).

Symbol Parameter Condition Min Typ (1) Max Units

10 MHz

4 MHz

1.8V 2.7V 5.5V

Safe Operating Area

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Figure 19-2. Maximum Frequency vs. VCC (ATtiny261/461/861)

19.4 Clock Characteristics

It is possible to manually calibrate the internal oscillator to be more accurate than default factory

calibration. Note that the oscillator frequency depends on temperature and voltage. Voltage and

temperature characteristics can be found in Figure 20-38 on page 217 and Figure 20-39 on

page 217.

Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).

2. Voltage range for ATtiny261V/461V/86 1V.

3. Voltage range for ATtiny261/461/861.

Figure 19-3. External Clock Drive Waveforms

20 MHz

10 MHz

2.7V 4.5V 5.5V

Safe Operating Area

Table 19-2. Calibration Accuracy of Internal RC Oscillator

Calibration

Method Target Frequency VCC Temperature Accuracy at give n

voltage & temperature (1)

Factory

Calibration 8.0 MHz 3V 25C±10%

User

Calibration

Fixed frequency

within:

7.3 - 8.1 MHz

Fixed voltage within:

1.8 - 5.5V(2)

2.7 - 5.5V(3)

Fixed temperature

within:

-40C to +85C±1%

VIL1

VIH1

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19.5 System and Reset Characteristics

Note: 1. Values are guidelines, only.

19.5.1 Power-On Reset

Notes: 1. Values are guidelines, only.

2. Threshold where device is released from reset whe n voltage is rising

3. The power-on reset will not work unless the supply voltage has been below VPOA

Table 19-3. External Clock Drive Characteristics

Symbol Parameter

VCC = 1.8 - 5.5V VCC = 2.7 - 5.5V VCC = 4.5 - 5.5V

UnitsMin. Max. Min. Max. Min. Max.

1/tCLCL Clock Frequency 0 4 0 10 0 20 MHz

tCLCL Clock Period 250 100 50 ns

tCHCX High Time 100 40 20 ns

tCLCX Low Time 100 40 20 ns

tCLCH Rise Time 2.0 1.6 0.5 s

tCHCL Fall Time 2.0 1.6 0.5 s

tCLCL Change in period from one clock cycle to the next 2 2 2 %

Table 19-4. Reset, Brown-out, and Internal Voltage Characteristics

Symbol Parameter Condition Min Typ Max Units

VRST RESET Pin Threshold V oltage (1) 0.2 VCC 0.9 VCC V

tRST Minimum pulse width on

RESET Pin (1) VCC = 3V 2.5 µs

VHYST Brown-out Detector Hysteresis (1) 50 mV

tBOD Min Pulse Width on

Brown-out Reset (1) 2µs

VBG Internal bandgap reference

voltage VCC = 2.7V

TA= 25°C 1.0 1.1 1.2 V

tBG Internal bandgap reference

start-up time (1) VCC = 5V

TA= 25°C 40 70 µs

IBG Internal bandgap reference

current consumption (1) VCC = 5V

TA= 25°C 15 µA

Table 19-5. Characteristics of Power-On Reset. TA = -40 to +85C

Symbol Parameter Min(1) Typ(1) Max(1) Units

VPOR Release threshold of power-on reset (2) 0.7 1.0 1.4 V

VPOA Activation threshold of power-on reset (3) 0.05 0.9 1.3 V

SRON Power-on slope rate 0.01 4.5 V/ms

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19.5.2 Brown-Out Detection

Note: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to VCC = VBOT during the production test. This guar-

antees that a Brown-out Reset will occur before VCC drops to a voltage where correct

operation of the microcontroller is no longer guaranteed.

Table 19-6. BODLEVEL Fuse Coding(1)

BODLEVEL[2:0] Fuses Min VBOT Typ VBOT Max VBOT Units

111 BOD Disabled

110 1.7 1.8 2.0

V101 2.5 2.7 2.9

100 4.1 4.3 4.5

0XX Reserved

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19.6 ADC Characteristics

Note: 1. Values are guidelines, only.

2. VDIFF must be below VREF.

Table 19-7. ADC Characteristics, Single Ended Channels. T = -40C to +85C

Symbol Parameter Condition Min(1) Typ(1) Max(1) Units

Resolution 10 Bits

Absolute accuracy

(Including INL, DNL, and

Quantization, Gain and Offset

Errors)

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2LSB

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz 3LSB

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz

Noise Reduction Mode 1.5 LSB

VREF = 4V, VCC = 4V,

ADC clock = 1 MHz

Noise Reduction Mode 2.5 LSB

Integral Non-Linearity (INL)

(Accuracy after Offset and

Gain Calibration)

VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 1LSB

Differential Non-linearity (DNL) VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 0.5 LSB

Gain Error VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 2.5 LSB

Offset Error VREF = 4V, VCC = 4V,

ADC clock = 200 kHz 1.5 LSB

Conversion Time Free Running Conversion 13 260 µs

Clock Frequency 50 1000 kHz

AVCC Analog Supply Voltage VCC - 0.3 VCC + 0.3 V

AREF External Voltage Reference Single Ended Conversions 2.0 AVCC V

Differential Conversions 2.0 AVCC - 1.0 V

VIN Input Voltage Single Ended Conversions GND VREF

Differential Conversions 0 AVCC (2) V

Input Bandwidth Single Ended Conversions 38.5 kHz

Differential Conversions 4

VINT Internal 1.1V Reference 1.0 1.1 1.2 V

Internal 2.56V Reference (2) 2.3 2.56 2.8 V

RREF Reference Input Resistance 35 k

RAIN Analog Input Resistance 100 M

ADC Conversion Output 0 1023 LSB

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19.7 Serial Programming Characteristics

Figure 19-4. Serial Programming Waveforms

Figure 19-5. Serial Programming Timing

Note: 1. 2 tCLCL for fck < 12 MHz, 3 tCLCL for fck >= 12 MHz

Table 19-8. Serial Programming Characteristics, TA = -40C to +85C, VCC = 1.8 - 5.5V

(Unless Otherwise Noted)

Symbol Parameter Min Typ Max Units

1/tCLCL Oscillator Frequency (ATtiny261V/461V/861V) 0 4 M Hz

tCLCL Oscillator Period (ATtiny261V/461V/861V) 250 ns

1/tCLCL Oscillator Frequency

(ATtiny261/461/861, VCC = 4.5 - 5.5V) 020MHz

tCLCL Oscillator Period

(ATtiny261/461/861, VCC = 4.5 - 5.5V) 50 ns

tSHSL SCK Pulse Width High 2 tCLCL(1) ns

tSLSH SCK Pulse Width Low 2 tCLCL(1) ns

tOVSH MOSI Setup to SCK High tCLCL ns

tSHOX MOSI Hold after SCK High 2 tCLCL ns

tSLIV SCK Low to MISO Valid 100 ns

MSB

LSB

SERIAL CLOCK INPUT

(SCK)

SERIAL DATA INPUT

(MOSI)

(MISO)

SAMPLE

SERIAL DATA OUTPUT

MOSI

MISO

SCK

tOVSH

tSHSL

tSLSH

tSHOX

tSLIV

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19.8 Parallel Programming Characteristics

Figure 19-6. Parallel Programming Timing, Including some General Timing Requirements

Figure 19-7. Parallel Programming Timing, Loading Sequence with Timing Requirements

Note: The timing requirements shown in Figure 19-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to loading operation.

Data & Contol

(DATA, XA0, XA1/BS2, PAGEL/BS1)

XTAL1

tXHXL

tWLWH

tDVXH tXLDX

tPLWL

tWLRH

RDY/BSY

tPLBX

tBVPH

tXLWL

tWLBX

tBVWL

WLRL

XTAL1

XLXH

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

PAGEL/BS1

XA0

XA1/BS2

LOAD ADDRESS

(LOW BYTE) LOAD DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

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Figure 19-8. Parallel Programming Timing, Reading Sequence (within the Same Page) with Timing Requirements

Note: The timing requirements shown in Figure 19-6 (i.e., tDVXH, tXHXL, and tXLDX) also apply to reading operation.

XTAL1

ADDR0 (Low Byte) DATA (Low Byte) DATA (High Byte) ADDR1 (Low Byte)

DATA

PAGEL/BS1

XA0

XA1/BS2

LOAD ADDRESS

(LOW BYTE) READ DATA

(HIGH BYTE) LOAD ADDRESS

(LOW BYTE)

tBVDV

tOLDV

tXLOL

tOHDZ

Table 19-9. Parallel Programming Characteristics, VCC = 5V ± 10%

Symbol Parameter Min Typ Max Units

VPP Programming Enable Voltage 11.5 12.5 V

IPP Programming Enable Current 250 µA

tDVXH Data and Control Valid before XTAL1 High 67 ns

tXLXH XTAL1 Low to XTAL1 High 200 ns

tXHXL XTAL1 Pulse Width High 150 ns

tXLDX Data and Control Hold after XTAL1 Low 67 ns

tXLWL XTAL1 Low to WR Low 0 ns

tBVPH BS1 Valid before PAGEL High 67 ns

tPHPL PAGEL Pulse Width High 150 ns

tPLBX BS1 Hold after PAGEL Low 67 ns

tWLBX BS2/1 Hold after WR Low 67 ns

tPLWL PAGEL Low to WR Low 67 ns

tBVWL BS1 Valid to WR Low 67 ns

tWLWH WR Pulse Width Low 150 ns

tWLRL WR Low to RDY/BSY Low 0 1 µs

tWLRH WR Low to RDY/BSY High(1) 3.7 4.5 ms

tWLRH_CE WR Low to RDY/BSY High for Chip Erase(2) 7.5 9 ms

tXLOL XTAL1 Low to OE Low 0 ns

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Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits

commands.

2. tWLRH_CE is valid for the Chip Erase command.

tBVDV BS1 Valid to DATA valid 0 250 ns

tOLDV OE Low to DATA Valid 250 ns

tOHDZ OE High to DATA Tri-stated 250 ns

Table 19-9. Parallel Programming Characteristics, VCC = 5V ± 10% (Continued)

Symbol Parameter Min Typ Max Units

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20. Typical Characteristics

The data contained in this section is largely based on simulations and characterization of similar

devices in the same process and design methods. Thus, the data should be treated as indica-

tions of how the part will behave.

The following charts show typical behavior. These figures are not tested during manufacturing.

During characterisation devices are operated at frequencies higher than test limits but they are

not guarante ed to function properly at frequencies higher than the ordering code indicates.

All current con sumption m easur ement s are per formed with all I/O pins configured as inputs and

with internal p ull-ups enabled . Curren t consump tion is a function o f several factor s such as oper-

ating voltage, operating frequency, loading of I/O pins, switching rate of I/O pins, code executed

and ambient temperature. The dominating factors are operating voltage and frequency.

A sine wave generator with rail-to-rail output is used as clock source but current consumption in

Power-Down mode is independent of clock selection. The difference be twee n curr ent co nsum p-

tion in Power-Down mode with Watchdog Timer enabled and Power-Down mode with Wa tchdog

Timer disabled represents the differential current drawn by the Watchdog Timer.

The current dr awn from pins with a capacitive load may be estimated (for one pin) as follows:

where VCC = operating voltage, CL = load capacitance and fSW = average switching frequency of

I/O pin.

20.1 Supply Current of I/O modules

The tables and formulas below can b e used to calculate the additional current consumptio n for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by t he Power Reduction Register. See “PRR – Pow er Reduction Register” on

page 39 for details.

Table 20-2 below can be used for calculating typical current consumption for other supply volt-

ages and frequencies than those mentioned in the Table 20-1 above.

ICP VCC CLf SW



Table 20-1. Additional Current Co nsumption for the different I/O modules (absolute values).

PRR bit

Typical numbers

VCC = 2V, f = 1MHz VCC = 3V, f = 4MHz VCC = 5V, f = 8MHz

PRTIM1 65 µA 423 µA 1787 µA

PRTIM0 7 µA 39 µA 165 µA

PRUSI 5 µA 25 µA 457 µA

PRADC 18 µA 111 µA 102 µA

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It is possible to calculate the typical current consumption based on the numbers from Table 20 -1

for other VCC and frequency settings than listed in Table 20-2.

20.1.0.1 Example Calculate the expected current consumption in idle mode with TIMER0, ADC, and USI enabled

at VCC = 2.0V and F = 1MHz. From Table 20-2, third column, we see that we need to add 10%

for the TIMER0, 27.3 % for the ADC, an d 6.5 % for the USI module. Reading from Figure 20-6

on page 201, we find that the idle curren t consumption is ~0,085 m A at VCC = 2.0V and F=1MHz.

The total current consumption in idle mode with TIMER0, ADC, and USI en ab le d, gives:

20.2 Active Supply Current

Figure 20-1. Active Supply Current vs. Low Frequency (0.1 - 1.0 MHz)

Table 20-2. Additional Current Consumption (percentage) in Active and Idle mode.

PRR bit

Additional Current consumption

compared to Active with external

clock (see Fi gure 20-1 on page

198 and Figure 20 -2 on pa ge 199)

Additional Current consumption

compared to Idle with external

clock (see Figure 20-6 on page

201 and Figure 20-7 on page 201)

PRTIM1 26.9 % 103.7 %

PRTIM0 2.6 % 10.0 %

PRUSI 1.7 % 6.5 %

PRADC 7.1 % 27.3 %

ICCtotal 0.085mA 1 0.10 0.273 0.065++ +0.122mA

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHZ

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0,2

0,4

0,6

0,8

1,2

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

Frequency (MHz)

(mA)

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Figure 20-2. Active Supply Current vs. Frequency (1 - 20 MHz)

Figure 20-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

0 2 4 6 8 101214161820

Frequency (MHz)

ICC

(mA)

1.8 V

2.7 V

3.3 V 4.0 V

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 ˚C

25 ˚C

-40 ˚C

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(mA)

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Figure 20-4. Active Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

Figure 20-5. Active Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)

ACTIVE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 ˚C

25 ˚C

-40 ˚C

0,2

0,4

0,6

0,8

1,2

1,4

1,6

1,5 2 2,5 3 3,5 4 4,5 5 5,5

(V)

ICC

(mA)

ACTIVE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 128 kHz

85 ˚C

25 ˚C

-40 ˚C

0,05

0,1

0,15

0,2

0,25

0,3

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(mA)

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20.3 Idle Supply Current

Figure 20-6. Idle Supply Current vs. Low Frequency (0.1 - 1.0 MHz)

Figure 20-7. Idle Supply Current vs. Fr eq ue n cy (1 - 20 MH z )

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0,05

0,1

0,15

0,2

0,25

0,3

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

Frequency (MHz)

ICC

(mA)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

5.5 V

5.0 V

4.5 V

0,5

1,5

2,5

3,5

4,5

0 2 4 6 8 101214161820

Frequency (MHz)

(mA)

1.8 V

2.7 V

3.3 V

4.0 V

202 2588F–AVR–06/2013

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Figure 20-8. Idle Supply Current vs. VCC (Internal RC Oscillator, 8 MHz)

Figure 20-9. Idle Supply Current vs. VCC (Internal RC Oscillator, 1 MHz)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 8 MHz

85 ˚C

25 ˚C

-40 ˚C

0,5

1,5

2,5

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(mA)

IDLE SUPPLY CURRENT vs. V

INTERNAL RC OSCILLATOR, 1 MHz

85 ˚C

25 ˚C

-40 ˚C

0,1

0,2

0,3

0,4

0,5

0,6

0,7

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(mA)

203

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Figure 20-10. Idle Supply Current vs. VCC (Internal RC Oscillator, 128 kHz)

20.4 Power-down Supply Current

Figure 20-11. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)

IDLE SUPPLY CURRENT vs. VCC

INTERNAL RC OSCILLATOR, 128 kHz

85 ˚C

25 ˚C

-40 ˚C

0,02

0,04

0,06

0,08

0,1

0,12

0,14

0,16

0,18

0,2

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(mA)

POWER-DOWN SUPPLY CURRENT vs. VCC

WATCHDOG TIMER DISABLED

85 ˚C

25 ˚C

-40 ˚C

0,2

0,4

0,6

0,8

1,2

1,4

1,6

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(uA)

204 2588F–AVR–06/2013

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Figure 20-12. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)

20.5 Pin Pull-up

Figure 20-13. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 1.8V)

POWER-DOWN SUPPLY CURRENT vs. V

WATCHDOG TIMER ENABLED

85 ˚C

25 ˚C

-40 ˚C

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(uA)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

VCC = 1.8V

85 ˚C

25 ˚C

-40 ˚C

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

VOP (V)

(uA)

205

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Figure 20-14. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)

Figure 20-15. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

= 2.7V

85 ˚C

25 ˚C

-40 ˚C

0 0,5 1 1,5 2 2,5 3

(V)

IOP

(uA)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

VCC = 5V

85 ˚C

25 ˚C

-40 ˚C

100

120

140

160

0123456

VOP (V)

(uA)

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Figure 20-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 1.8V)

Figure 20-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

= 1.8V

85 ˚C

25 ˚C

-40 ˚C

0 0,2 0,4 0,6 0,8 1 1,2 1,4 1,6 1,8 2

RESET

(V)

IRESET

(uA)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

= 2.7V

85 ˚C

25 ˚C

-40 ˚C

0 0,5 1 1,5 2 2,5 3

VRESET

(V)

IRESET

(uA)

207

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Figure 20-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)

20.6 Pin Driver Streng th

Figure 20-19. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

VCC = 5V

85 ˚C

25 ˚C

-40 ˚C

100

120

0123456

VRESET

(V)

IRESET

(uA)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

VCC = 3V

85 ˚C

25 ˚C

-40 ˚C

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

0 5 10 15 20 25

IOL (mA)

(V)

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Figure 20-20. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)

Figure 20-21. I/O Pin Output Voltage vs. Source Current (VCC = 3V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

VCC = 5V

85 ˚C

25 ˚C

-40 ˚C

0,1

0,2

0,3

0,4

0,5

0,6

0 5 10 15 20 25

IOL (mA)

(V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

VCC = 3V

85 ˚C

25 ˚C

-40 ˚C

1,5

1,7

1,9

2,1

2,3

2,5

2,7

2,9

3,1

0 5 10 15 20 25

IOH (mA)

(V)

209

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Figure 20-22. I/O Pin Output Voltage vs. Source Current (VCC = 5V)

Figure 20-23. Reset Pin Output Voltage vs. Sink Current (VCC = 3V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

VCC = 5V

85 ˚C

25 ˚C

-40 ˚C

4,2

4,4

4,6

4,8

0 5 10 15 20 25

IOH (mA)

VOH

(V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

VCC = 3V

-45 °C

0 °C

85 °C

0.5

1.5

0 0.5 1 1.5 2 2.5 3

IOL (mA)

VOL (V)

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Figure 20-24. Reset Pin Output Voltage vs. Sink Current (VCC = 5V)

Figure 20-25. Reset Pin Output Voltage vs. Source Current (VCC = 3V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

VCC = 5V

-45 °C

0 °C

85 °C

0.2

0.4

0.6

0.8

0 0.5 1 1.5 2 2.5 3

(mA)

(V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

= 3V

-45 °C

25 °C

85 °C

0.5

1.5

2.5

3.5

00.511.52

IOH (mA)

VOH (V)

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Figure 20-26. Reset Pin Output Voltage vs. Source Current (VCC = 5V)

20.7 Pin Threshold and Hysteresis

Figure 20-27. I/O Pin Input Threshold Voltage vs. VCC (VIH, I/O Pin Read as ‘1’)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

= 5V

-45 °C

25 °C

85 °C

2.5

3.5

4.5

0 0.5 1 1.5 2

(mA)

(V)

I/O PIN INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'

85 ˚C

25 ˚C

-40 ˚C

0,5

1,5

2,5

3,5

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

Threshold (V)

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Figure 20-28. I/O Pin Input Threshold Voltage vs. VCC (VIL, I/O Pin Read as ‘0’)

Figure 20-29. I/O Pin Input Hysteresis vs. VCC

I/O PIN INPUT THRESHOLD VOLTAGE vs. V

VIL, IO PIN READ AS '0'

85 ˚C

25 ˚C

-40 ˚C

0,5

1,5

2,5

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

Threshold (V)

I/O PIN INPUT HYST ERESIS vs . V

85 °C

25 °C

-40 °C

0,1

0,2

0,3

0,4

0,5

0,6

0,7

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V )

Input Hys teresis (V )

213

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Figure 20-30. Reset Input Threshold Voltage vs. VCC (VIH, Reset Read as ‘1’)

Figure 20-31. Reset Input Threshold Voltage vs. VCC (VIL, Reset Read as ‘0’)

RESET INPUT THRESHOLD VOLTAGE vs. V

VIH, RESET READ AS '1' 85 ˚C

25 ˚C

-40 ˚C

0,5

1,5

2,5

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

Threshold (V)

RESET PIN AS I/O THRESHOLD VOLTAGE vs. V

VIL, RESET READ AS '0'

85 ˚C

25 ˚C

-40 ˚C

0,5

1,5

2,5

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

Threshold (V)

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Figure 20-32. Reset Pin input Hysteresis vs. VCC

20.8 BOD and Bandgap

Figure 20-33. BOD Threshold vs. Temperatur e (BOD Level is 4.3V)

R ES ET PIN INPUT HYSTERESIS vs. V

85 °C

25 °C

-40 °C

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1,5 2 2,5 3 3,5 4 4,5 5 5,5

(V )

Input Hys teresis (V )

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 4.3V

Rising V

Falling V

4,1

4,15

4,2

4,25

4,3

4,35

4,4

4,45

4,5

-60 -40 -20 0 20 40 60 80 100

Temperature (C)

Threshold (V)

215

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Figure 20-34. BOD Threshold vs. Temperatur e (BOD Level is 2.7V)

Figure 20-35. BOD Threshold vs. Temperatur e (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 2.7V

Falling VCC

Rising VCC

2,5

2,55

2,6

2,65

2,7

2,75

2,8

2,85

2,9

-60 -40 -20 0 20 40 60 80 100

Temperature (C)

Threshold (V)

BOD THRESHOLDS vs. TEMPERATURE

BODLEVEL is 1.8V

Rising V

Falling V

1,6

1,65

1,7

1,75

1,8

1,85

1,9

1,95

-60 -40 -20 0 20 40 60 80 100

Temperature (C)

Threshold (V)

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Figure 20-36. Bandgap Voltage vs. Supply Voltage (VCC).

20.9 Internal Oscillator Speed

Figure 20-37. Watchdog Oscillator Frequency vs. VCC

BANDGAP VOLTAGE vs. VCC

85 °C

25 °C

-40 °C

1.04

1.05

1.06

1.07

1.08

1.5 2 2.5 3 3.5 4 4.5 5 5.5

VCC ( V )

Bandgap Voltage ( V )

WATCHDOG OSCILLATOR FREQUENCY vs. V

85 ˚C

25 ˚C

-40 ˚C

0,118

0,12

0,122

0,124

0,126

0,128

0,13

0,132

0,134

0,136

0,138

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

FRC

(MHz)

217

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Figure 20-38. Calibrated 8.0 MHz RC Oscillator Frequency vs. VCC

Figure 20-39. Calibrated 8.0 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. V

85 ˚C

25 ˚C

-40 ˚C

7,2

7,4

7,6

7,8

8,2

8,4

8,6

8,8

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(MHz)

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

5.0 V

3.0 V

7,2

7,4

7,6

7,8

8,2

8,4

8,6

8,8

-60 -40 -20 0 20 40 60 80 100

Temperature

(MHz)

218 2588F–AVR–06/2013

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Figure 20-40. Calibrated 8.0 MHz RC Oscillator Frequency vs. OSCCAL Value

20.10 Current Consumption of Peripheral Units

Figure 20-41. ADC Current vs. VCC (AREF = AVCC)

CALIBRATED 8.0 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

85 ˚C

25 ˚C

-40 ˚C

0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256

OSCCAL (X1)

(MHz)

ADC CURRENT vs. V

AREF = AVCC

100

200

300

400

500

600

700

800

900

1000

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(uA)

25 ˚C

219

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Figure 20-42. AREF External Reference Curr en t vs. V CC

Figure 20-43. Analog Comparator vs. VCC

AREF EXTERNAL REFERENCE CURRENT vs. V

25 ˚C

120

150

180

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(uA)

ANALOG COMPARATOR vs. V

25 ˚C

100

120

140

160

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(uA)

220 2588F–AVR–06/2013

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Figure 20-44. Brownout Detector Current vs. VCC

Figure 20-45. Programming Current vs. VCC

BROWNOUT DETECTOR CURRENT vs. V

85 ˚C

25 ˚C

-40 ˚C

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

(uA)

PROGRAMMING CURRENT vs. V

25 ˚C

2000

4000

6000

8000

10000

12000

14000

16000

1,5 2 2,5 3 3,5 4 4,5 5 5,5

(V)

(uA)

221

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Figure 20-46. Watchdog Timer Current vs. VCC

20.11 Current Consumption in Reset and Reset Pulsewidth

Figure 20-47. Reset Supply Current vs. Low Frequency (0.1 - 1.0 MHz, Excluding Current

Through the Res et Pull-u p)

WATCHDOG TIMER CURRENT vs. VCC

85 ˚C

25 ˚C

-40 ˚C

1,5 2 2,5 3 3,5 4 4,5 5 5,5

VCC (V)

ICC

(uA)

RESET SUPPLY CURRENT vs. Low Frequency

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULL-UP

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0,02

0,04

0,06

0,08

0,1

0,12

0,14

0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1

Frequency (MHz)

(mA)

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Figure 20-48. Reset Supply Current vs. Frequen cy (1 - 20 MHz, Excluding Current Thr ough the

Reset Pull-up)

Figure 20-49. Minimum Reset Pulse Width vs. VCC

RESET SUPPLY CURRENT vs. V

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

5.5 V

5.0 V

4.5 V

0,5

1,5

2,5

0 2 4 6 8 101214161820

Frequency (MHz)

(mA)

1.8 V

2.7 V

3.3 V

4.0 V

MINIMUM RESET PULSE WIDTH vs. VCC

85 ˚C

25 ˚C

-40 ˚C

500

1000

1500

2000

2500

1,5 2 2,5 3 3,5 4 4,5 5 5,5

(V)

Pulsewidth (ns)

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21. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x3F (0x5F) SREG I T H S V N Z C page 8

0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 page 11

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 11

0x3C (0x5C) Reserved –

0x3B (0x5B) GIMSK INT1 INT0 PCIE1 PCIE0 – – – – page 52

0x3A (0x5A) GIFR INTF1 INTF0 PCIF – – – – – page 53

0x39 (0x59) TIMSK OCIE1D OCIE1A OCIE1B OCIE0A OCIE0B TOIE1 TOIE0 TICIE0 page 86, page 123

0x38 (0x58) TIFR OCF1D OCF1A OCF1B OCF0A OCF0B TOV1 TOV0 ICF0 page 87, page 123

0x37 (0x57) SPMCSR – – – CTPB RFLB PGWRT PGERS SPMEN page 169

0x36 (0x56) PRR PRTIM1 PRTIM0 PRUSI PRADC page 37

0x35 (0x55) MCUCR –PUDSESM1SM0–ISC01ISC00page 39, page 69, page 52

0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF page 47,

0x33 (0x53) TCCR0B – – – TSM PSR0 CS02 CS01 CS00 page 85

0x32 (0x52) TCNT0L Timer/Counter0 Counter Register Low Byte page 85

0x31 (0x51) OSCCAL Oscillator Calibration Register page 32

0x30 (0x50) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 FOC1A FOC1B PWM1A PWM1B page 112

0x2F (0x4F) TCCR1B PWM1X PSR1 DTPS11 DTPS10 CS13 CS12 CS11 CS10 page 169

0x2E (0x4E) TCNT1 Timer/Counter1 Counter Register page 121

0x2D (0x4D) OCR1A Timer/Counter1 Output Compare Register A page 121

0x2C (0x4C) OCR1B Timer/Counter1 Output Compare Register B page 122

0x2B (0x4B) OCR1C Timer/Counter1 Output Compare Register C page 122

0x2A (0x4A) OCR1D Timer/Counter1 Output Compare Register D page 122

0x29 (0x49) PLLCSR LSM PCKE PLLE PLOCK page 120

0x28 (0x48) CLKPR CLKPCE CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 32

0x27 (0x47) TCCR1C COM1A1S COM1A0S COM1B1S COM1B0S COM1D1 COM1D0 FOC1D PWM1D page 117

0x26 (0x46) TCCR1D FPIE1 FPEN1 FPNC1 FPES1 FPAC1 FPF1 WGM11 WGM10 page 118

0x25 (0x45) TC1H TC19 TC18 page 121

0x24 (0x44) DT1 DT1H3 DT1H2 DT1H1 DT1H0 DT1L3 DT1L2 DT1L1 DT1L0 page 124

0x23 (0x43) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 page 54

0x22 (0x42) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 page 54

0x21 (0x41) WDTCR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 47

0x20 (0x40) DWDR DWDR[7:0] page 37

0x1F (0x3F) EEARH EEAR8 page 20

0x1E (0x3E) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 21

0x1D (0x3D) EEDR EEPROM Data Register page 21

0x1C (0x3C) EECR –– EEPM1 EEPM0 EERIE EEMPE EEPE EERE page 21

0x1B (0x3B) PORTA PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0 page 69

0x1A (0x3A) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 page 69

0x19 (0x39) PINA PINA7 PINA6 PINA 5 PIN A4 PINA3 PINA2 PINA1 PIN A0 page 70

0x18 (0x38) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 70

0x17 (0x37) DD RB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 70

0x16 (0x36) PINB PINB7 PINB6 PINB 5 PIN B4 PINB3 PINB2 PINB1 PIN B0 page 70

0x15 (0x35) TCCR0A TCW0 ICEN0 ICNC0 ICE S0 ACIC0 CTC0 page 84

0x14 (0x34) TCNT0H Timer/Counter0 Counter Register High Byte page 86

0x13 (0x33) OCR0A Timer/Counter0 Output Compare Register A page 86

0x12 (0x32) OCR0B Timer/Counter0 Output Compare Register B page 86

0x11 (0x31) USIPP USIPOS page 136

0x10 (0x30) USIBR USI Buffer Register page 133

0x0F (0x2F) USIDR USI Data Register page 132

0x0E (0x2E) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 page 133

0x0D (0x2D) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC page 134

0x0C (0x2C) GPIOR2 General Purpose I/O Register 2 page 22

0x0B (0x2B) GPIOR1 General Purpose I/O Register 1 page 23

0x0A (0x2A) GPIOR0 General Purpose I/O Register 0 page 23

0x09 (0x29) ACSRB HSEL HLEV ACM2 ACM1 ACM0 page 140

0x08 (0x28) ACSRA ACD ACBG ACO ACI ACIE ACME ACIS1 ACIS0 page 139

0x07 (0x27) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 page 155

0x06 (0x26) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 159

0x05 (0x25) ADCH ADC Data Register High Byte page 160

0x04 (0x24) ADCL ADC Data Registe r Low Byte page 160

0x03 (0x23) ADCSRB BIN GSEL REFS2MUX5ADTS2ADTS1ADTS0 page 161

0x02 (0x22) DIDR1 ADC10D ADC9D ADC8D ADC7D page 162

0x01 (0x21) DIDR0 ADC6D ADC5D ADC4D ADC3D AREFD A DC2D ADC1D ADC0D page 162

0x00 (0x20) TCCR1E –- OC1OE5 OC1OE4 OC1OE3 OC1OE2 OC1OE1 OC1OE0 page 119

224 2588F–AVR–06/2013

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Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

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22. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd  Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd  Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immedia te to Word Rdh:Rdl  Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd  Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd  Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd  Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constan t from Re g. Rd  Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediat e from Word Rdh:Rdl  Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd Rd  Rr Z,N, V 1

ANDI Rd, K Logical AND Register and Constant Rd  Rd K Z,N,V 1

OR Rd, Rr Log ical OR Registers Rd  Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd  Rd  Rr Z,N,V 1

COM Rd One’s Complement Rd  0xFF  Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd  0x00  Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd  Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd  Rd  (0xFF - K) Z,N,V 1

INC Rd Increment Rd  Rd + 1 Z,N,V 1

DEC Rd Decrement Rd  Rd  1 Z,N,V 1

TST Rd Test for Zero or Minus Rd  Rd  Rd Z,N,V 1

CLR Rd Clear Register Rd  Rd  Rd Z,N,V 1

SER Rd Set Register Rd  0xFF None 1

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC PC + k + 1 Non e 2

IJMP Indirect Jump to (Z) PC  Z None 2

RCALL k Relativ e Subrouti ne Call PC  PC + k + 1 None 3

ICALL Indirect Call to (Z) PC  ZNone3

RET Subroutine Return PC  STACK None 4

RETI Interrupt Return PC  STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) P C PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd  Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd  Rr  C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd  K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC  PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC  PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC  PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC  PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PCPC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PCPC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC  PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC  PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC  PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC  PC + k + 1 None 1 /2

BRSH k Branch if Same or Higher if (C = 0) then PC  PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC  PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC  PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC  PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N  V= 0) then PC  PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N  V= 1) then PC  PC + k + 1 None 1 /2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC  PC + k + 1 None 1/2

BRHC k Branch if Half Car ry Flag Cleared if (H = 0) then PC  PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC  PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC  PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC  PC + k + 1 None 1/2

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC  PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC  PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC  PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b)  1None2

CBI P,b Clear Bit in I/O Register I/O(P,b)  0None2

LSL Rd Logical Shift Left Rd(n+1)  Rd(n), Rd(0)  0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n)  Rd(n+1), Rd(7)  0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)C,Rd(n+1) Rd(n),CRd(7) Z,C,N,V 1

ROR Rd Rotate Righ t Th rough Carry Rd(7)C,Rd(n) Rd(n+1),CRd(0) Z,C,N,V 1

226 2588F–AVR–06/2013

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ASR Rd Arithmetic Shift Right Rd(n)  Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) None 1

BSET s Flag Set SREG(s)  1 SREG(s) 1

BCLR s Flag Clear SREG(s)  0 SREG(s) 1

BST Rr, b Bit Store from Register to T T  Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b)  TNone1

SEC Set Carry C  1C1

CLC Clear Carry C  0 C 1

SEN Set Negative Flag N  1N1

CLN Clear Negative Flag N  0 N 1

SEZ Set Zero Flag Z  1Z1

CLZ Clear Zero Flag Z  0 Z 1

SEI Global Interrupt Enable I  1I1

CLI Global Interrupt Disable I 0 I 1

SES Set Signed Test Flag S  1S1

CLS Clear Signed Test Flag S  0 S 1

SEV Set Twos Complement Overflow. V  1V1

CLV Clear Twos Compl ement Overflow V  0 V 1

SET Set T in SREG T  1T1

CLT Clear T in SREG T  0 T 1

SEH Set Hal f Carry Flag in SREG H  1H1

CLH Clear Half Carry Flag in SRE G H  0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd  Rr None 1

MOVW Rd, Rr Copy Register Word Rd+1:Rd  Rr+1:Rr None 1

LDI Rd, K Load Immediate Rd  KNone1

LD Rd, X Load Indirect Rd  (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd  (X), X  X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X  X - 1, Rd  (X) None 2

LD Rd, Y Load Indirect Rd  (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd  (Y), Y  Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y  Y - 1, Rd  (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd  (Y + q) None 2

LD Rd, Z Load Indirect Rd  (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd  (Z), Z  Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z  Z - 1, Rd  (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd  (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd  (k) N one 2

ST X, Rr Store Indirect (X) Rr N one 2

ST X+, Rr Store Indirect and Post-Inc. (X) Rr, X  X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X  X - 1, (X)  Rr None 2

ST Y, Rr Store Indirect (Y)  Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y)  Rr, Y  Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y  Y - 1, (Y)  Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q)  Rr None 2

ST Z, Rr Store Indirect (Z)  Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z)  Rr, Z  Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z  Z - 1, (Z)  Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q)  Rr None 2

STS k, Rr Store Direct to SRAM (k)  Rr None 2

LPM Lo ad Program Memory R0  (Z) None 3

LPM Rd, Z Load Program Memory Rd  (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd  (Z), Z  Z+1 None 3

SPM Store Program Memory (z)  R1:R0 None

IN Rd, P In Port Rd  PNone1

OUT P, Rr Out Port P  Rr None 1

PUSH Rr Push Register on Stack STACK  Rr None 2

POP Rd Pop Register from Stack Rd  STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/Timer) None 1

BREAK Break For On-chip Debug Only None N/A

Mnemonics Operands Description Operation Flags #Clocks

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23. Ordering Information

Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. For Speed vs. VCC, see Figure 19.3 on page 188.

4. Code indicators: – U: matte tin

– R: tape & reel

5. Mature devices, replaced by ATtiny261A.

23.1 ATtiny261 - Mature

Speed (MHz)(3) Power Supply (V) Ordering Code(4)(5) Package(2) Operational Range

10 1.8 - 5.5

ATtiny261V-10MU

ATtiny261V-10MUR

ATtiny261V-10PU

ATtiny261V-10SU

ATtiny261V-10SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

20 2.7 - 5.5

ATtiny261-20MU

ATtiny261-20MUR

ATtiny261-20PU

ATtiny261-20SU

ATtiny261-20SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

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Package Type

32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

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Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. For Speed vs. VCC, see Figure 19.3 on page 188.

4. Code indicators: – U: matte tin

– R: tape & reel

23.2 ATtiny461

Speed (MHz)(3) Power Supply (V) Ordering Code(4) Package(2) Operational Range

10 1.8 - 5.5

ATtiny461V-10MU

ATtiny461V-10MUR

ATtiny461V-10PU

ATtiny461V-10SU

ATtiny461V-10SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

20 2.7 - 5.5

ATtiny461-20MU

ATtiny461-20MUR

ATtiny461-20PU

ATtiny461-20SU

ATtiny461-20SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

Package Type

32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

230 2588F–AVR–06/2013

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Notes: 1. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-

tion and minimum quantities.

2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-

ous Substances (RoHS).

3. For Speed vs. VCC, see Figure 19.3 on page 188.

4. Code indicators: – U: matte tin

– R: tape & reel

23.3 ATtiny861

Speed (MHz)(3) Power Supply (V) Ordering Code(4) Package(2) Operational Range

10 1.8 - 5.5

ATtiny861V-10MU

ATtiny861V-10MUR

ATtiny861V-10PU

ATtiny861V-10SU

ATtiny861V-10SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

20 2.7 - 5.5

ATtiny861-20MU

ATtiny861-20MUR

ATtiny861-20PU

ATtiny861-20SU

ATtiny861-20SUR

32M1-A

20P3

20S2

Industrial

(-40C to +85C)(1)

Package Type

32M1-A 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)

20P3 20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20S2 20-lead, 0.300" Wide, Plastic Gull Wing Smal Outline Package (SOIC)

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24. Packaging Information

24.1 32M1-A

2325 Orchard Parkway

San Jose, CA 95131

TITLE DRAWING NO.

REV.

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, D

32M1-A

8/19/04

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

COMMON DIMENSIONS

(Unit of Measure = mm)

SYMBOL MIN NOM MAX NOTE

E1 E

0.08 C

A 0.80 0.90 1.00

A1 – 0.02 0.05

A2 – 0.65 1.00

A3 0.20 REF

b 0.18 0.23 0.30

D 5.00 BSC

D1 4.75 BSC

D2 2.95 3.10 3.25

E 5.00 BSC

E1 4.75BSC

E2 2.95 3.10 3.25

e 0.50 BSC

L 0.30 0.40 0.50

P – – 0.60

– – 12o

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Pin 1 ID

Pin #1 Notch

(0.20 R)

K 0.20 – –

232 2588F–AVR–06/2013

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24.2 20P3

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24.3 20S2

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25. Errata

25.1 Errata ATtiny261

The revision letter in this section refers to the revision of the ATtiny261 device.

25.1.1 Rev A No known errata.

25.2 Errata ATtiny461

The revision letter in this section refers to the revision of the ATtiny461 device.

25.2.1 Rev B Yield improvement. No known errata.

25.2.2 Rev A No known errata.

25.3 Errata ATtiny861

The revision letter in this section refers to the revision of the ATtiny861 device.

25.3.1 Rev B No known errata.

25.3.2 Rev A Not sampled.

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26. Datasheet Revision History

Please note that the referring page numbers in this section refer to the complete document.

26.1 Rev. 2588F – 06/13

1. ATtiny261 changed status to “Mature”.

26.2 Rev. 2588E – 08/10

1. Added tape and reel in “Ordering Information” on page 227.

2. Clarified Section 6.4 “Clock Output Buffer” on page 32.

3. Removed text "Not recommended for new designs" from cover page.

26.3 Rev. 2588D – 06/10

1. Removed “Preliminary” from cover page.

2. Added clarification before Table 6-10, “Capacitance for Low-Frequency Crystal Oscilla-

tor,” on page 29.

3. Updated Figure 15-1 “Analog to Digital Converter Block Schematic” on page 143 ,

changed INTERNAL 1.18V REFERENCE to 1.1V.

4. Updated Table 18-8, “No. of Words in a Page and No. of Pages in the EEPROM,” on

page 173, No. of Pages from 64 to 32 for ATtiny261.

5. Adjusted notes in Tabl e 19-1, “DC Characteristics. TA = -40 °C to +85°C, VCC = 1.8V to

5.5V (unless otherwise noted).,” on page 187.

26.4 Rev. 2588C – 10/09

1. Updated document template. Re-a rranged some sections.

2. Changed device status to "Not Recommended for New Designs".

3. Added Sections:

–“Data Retention” on page 6

–“Clock Sources” on page 25

–“Low Level Interrupt” on page 51

–“Prescaling and Conversion Timing” on page 145

–“Clock speed considerations” on page 131

4. Updated Sections:

–“Code Examples” on page 6

–“High-Frequency PLL Clock” on page 26

–“Normal Mode” on page 99

–“Features” on page 142

–“Temperature Mea surement” on page 154

–“Limitations of debugWIRE” on page 164

–Step 1. on page 174

–“Programming th e Flash” on page 180

–“System and Reset Characteristics” on page 190

5. Added Figures:

–“Flash Programming Waveforms” on page 182

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–“Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 209

–“Bandgap Volt ag e vs. Supp ly Volt ag e (VC C ). ” on page 21 6

6. Updated Figures:

–“Block Diagram” on page 4

–“Clock Distribution” on page 24

7. Added Table:

–“Capacitance for Low-Frequency Crystal Oscillator” on page 29

8. Updated Tables:

–“Start-up Times for the Internal Calibrated RC Oscillator Clock Selection” on page 28

–“Start-up Times for the 128 kHz Internal Oscillator” on page 29

–“Active Clock Domains and Wake-up Sources in Different Sleep Mo des” on page 36

–“Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 - 5.5V

(Unless Otherwise Noted)” on page 193

9. Updated Register Descriptions:

–“TCCR1A – Timer/Counter1 Control Register A” on page 112

–“TCCR1C – Timer/Counter1 Control Register C” on page 117

–“ADMUX – ADC Multiplexer Selection Register” on page 155

10. Updated assembly program example in section “Write” on page 17.

11. Updated “DC Characteristics. TA = -40°C to +85°C, VCC = 1.8V to 5.5V (unless other-

wise noted).” on page 187.

26.5 Rev. 2588B – 11/06

1. Updated “Ordering Information” on page 227.

2. Updated “Packaging Information” on page 231.

26.6 Rev. 2588A – 10/06

1. Initial Revision.

2588F–AVR–06/2013

ATtiny261/461/861

Table of Contents

Features..................................................................................................... 1

1 Pin Configurations ................................................................................... 2

1.1 Pin Descriptions .................................................................................................3

2 Overview ................................................................................................... 4

2.1 Block Diagram ... .... ... ................... .................................... ................... ...............4

3 About ......................................................................................................... 6

3.1 Resources .........................................................................................................6

3.2 Code Examples .................................................................................................6

3.3 Data Retention ...................................................................................................6

3.4 Disclaimer ..........................................................................................................6

4CPU Core .................................................................................................. 7

4.1 Architectural Overview .......................................................................................7

4.2 ALU – Arithmetic Logic Unit ...............................................................................8

4.3 Status Regist er ......... ... ... .... ... ... ... .... ... ................ ... ... .... ... ... ... ... .... ... ... ...............8

4.4 General Purpose Register File ........................................................................10

4.5 Stack Pointer ...................................................................................................11

4.6 Inst ruction Execution Timing ....................... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ...11

4.7 Reset and Interrupt Handling ...........................................................................12

5 Memories ................................................................................................ 15

5.1 In-System Re-programmable Flash Program Memory ....................................15

5.2 SRAM Data Memory ....... .................................... ................... .................... ......15

5.3 EEPROM Data Memory ..................................................................................16

5.4 I/ O Memory ........ .... ... ... ................ .... ... ... ... ... .... ... ... ... .... ................ ... ... ... .... ... ...20

5.5 Register Des cription .... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... .... ... ................20

6 Clock System ......................................................................................... 24

6.1 Clock Subsy stems .......... .... ... ................... ... .... ................... ... .................... ... ...24

6.2 Clock Sources ....................... ... ... .... ... ... ... ... .... ... ... ................... .... ... ................25

6.3 Sys tem Clock P rescaler ........................ ... ... .... ... ... ... .... ... ... ................... .... ... ...31

6.4 Clock Output Buffer ..... ... .... ... ... ... .... ... ... ... ... .... ... ... ................... .... ... ................32

6.5 Register Des cription .... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ...................32

7 Power Management and Sleep Modes ................................................. 36

7.1 Sleep Modes ....................................................................................................36

ii 2588F–AVR–06/2013

ATtiny261/461/861

7.2 Power Reduction Register ...............................................................................37

7.3 Minimizing Power Consumption ......................................................................37

7.4 Register Des cription .... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... .... ... ................39

8 System Control and Reset .................................................................... 41

8.1 Reset Sources .................................................................................................42

8.2 Internal Voltage Reference ..............................................................................44

8.3 Watchdog Timer ..............................................................................................44

8.4 Register Des cription .... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... .... ... ................47

9 Interrupts ................................................................................................ 50

9.1 Interrupt Vec tors .......... ... .................... ................... ................... .................... ...50

9.2 External Interrupts ...........................................................................................51

9.3 Register Des cription .... ... .... ... ... ... .... ... ... ... .................... ... ... ... ... .... ... ................52

10 I/O Ports .................................................................................................. 55

10.1 Ports as General Digital I/O .............................................................................56

10.2 Alternate Port Functions ..................................................................................60

10.3 Register Des cription .... ... .... ... ... ... .... ... ................... ... .... ... ... ... .................... ... ...69

11 Timer/Counter0 ...................................................................................... 71

11.1 Features ..........................................................................................................71

11.2 O verview ...... ...... ....... ... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ......71

11.3 Clock Sources ....................... ... ... .... ... ... ................... .... ... ................... ... .... ......72

11.4 Counter Unit ....................................................................................................74

11.5 Input Capture Unit ...........................................................................................75

11.6 Output Compare Unit .......................................................................................76

11.7 Modes of Operation .........................................................................................77

11.8 Timer/Counter Timing Diagrams .....................................................................79

11.9 Accessing Registers in 16-bit Mode ................................................................80

11.10 Register Description .............. ... ... .... ... ... ... ... .................... ... ... ... .... ... ... .............84

12 Timer/Counter1 ...................................................................................... 89

12.1 Features ..........................................................................................................89

12.2 O verview ...... ...... ....... ... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ...... ....... ......89

12.3 Clock Sources ....................... ... ... .... ... ... ................... .... ... ................... ... .... ......92

12.4 Counter Unit ....................................................................................................93

12.5 Output Compare Unit .......................................................................................94

12.6 Dead Time Generator ......................................................................................96

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12.7 Compare Match Output Unit ............................................................................97

12.8 Modes of Operation .........................................................................................99

12.9 Timer/Counter Timing Diagrams ...................................................................106

12.10 Fault Protection Unit ....... .... ... ... ... .... ... ... ................... .... ... ... ... ... .................... .107

12.11 Accessing 10-Bit Registers ............................................................................108

12.12 Register Description .............. ... ... .... ... ... ... ... .................... ... ... ... .... ... ... ...........112

13 USI – Universal Serial Interface .......................................................... 125

13.1 Features ........................................................................................................125

13.2 O verview ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ... ....... ....125

13.3 Funct ional Descript ions ................... ... ... ... ... .... ................... ... ... .... ... ... ... ........126

13.4 Alternative USI Usage ...................................................................................132

13.5 Register Des criptions ...................... ... ... ... ... .... ... ... ................... .... ... ... ... .... ... .132

14 AC – Analog Comparator .................................................................... 137

14.1 Analog Comparator Multiplexed Input ...........................................................137

14.2 Register Des cription .... ... .... ... ... ... .... ... ................... ... .... ... ... ... .................... ... .139

15 ADC – Analog to Digital Converter ..................................................... 142

15.1 Features ........................................................................................................142

15.2 O verview ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ... ....... ....142

15.3 Operation .......................................................................................................143

15.4 Starting a Conversion ....................................................................................144

15.5 Prescaling and Conversion Timing ................................................................145

15.6 Changing Channel or Reference Selection ...................................................148

15.7 ADC Noise Canceler .....................................................................................149

15.8 Analog Input Circuitry ....................................................................................150

15.9 Noise Canceling Techniques .........................................................................150

15.10 ADC Accuracy Definitions .............................................................................151

15.11 ADC Conversion Result .................................................................................153

15.12 Temperature Measurement ...........................................................................154

15.13 Register Description .............. ... ... .... ... ... ... ... .................... ... ... ... .... ... ... ...........155

16 debugWIRE On-chip Debug System .................................................. 163

16.1 Features ........................................................................................................163

16.2 O verview ...... ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ... ....... ....163

16.3 Physic al Int erface ..... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... ........163

16.4 Softw are Break Points .... .... ... ... ... .... ................... ... ................... .... .................164

16.5 Limitations of debugWIRE .............................................................................164

iv 2588F–AVR–06/2013

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16.6 Register Des cription .... ... .... ... ... ... .... ... ................... ... .... ... ... ... .................... ... .164

17 Self-Programming the Flash ............................................................... 165

17.1 Performing Page Erase by SPM ....................................................................165

17.2 Filling the Temporary Buffer (Page Loading) .................................................165

17.3 Performing a Page Write ...............................................................................166

17.4 Addressing the Flash During Self-Programming ...........................................166

17.5 EEPROM Write Prevents Writing to SPMCSR ..............................................167

17.6 Reading Fuse and Lock Bits from Software ..................................................167

17.7 Prev enting Flash Corruption ........ .... ... ... ... ... .... ... ... ... .................... ... ... ... .... ... .168

17.8 Programming Time for Flash when Using SPM ............................................168

17.9 Register Des cription .... ... .... ... ... ... .... ... ................... ... .... ... ... ... .................... ... .169

18 Memory Programming ......................................................................... 170

18.1 Program And Data Memory Lock Bits ... ... ... .... ... ... ... .... ... ................... ... .... ....170

18.2 Fus e Bytes ... ... ... .... ... ................... .... ................... ................... .................... ....171

18.3 Signature Bytes .............................................................................................172

18.4 Calibration Byte .............................................................................................173

18.5 Page Size ......................................................................................................173

18.6 Serial Programming .......................................................................................173

18.7 Parallel Programming ......... ... ... ... .................... ... ... ... .... ... ... ................... .... ... .177

19 Electrical Characteristics .................................................................... 187

19.1 Absolute Maximum Ratings* .........................................................................187

19.2 DC Characteristics .........................................................................................187

19.3 Speed ............................................................................................................188

19.4 Clock Charac terist ics ... ... .... ... ... ... .... ... ... ... ... .... ................... ... .................... ... .189

19.5 System and Reset Characteristics ................................................................190

19.6 ADC Characteristics ......................................................................................192

19.7 Serial Programming Characteristics ..............................................................193

19.8 Parallel Programming Charac teristics ...........................................................194

20 Typical Characteristics ........................................................................ 197

20.1 Supply Current of I/O modules .... .... ... ... ... ... .... ... ... ... .... ... ... ... ... .... ... ... ... .... ... .197

20.2 Active Supply Current ....................................................................................198

20.3 Idle Supply Current ........................................................................................201

20.4 Power-down Supply Current .................. ...... ....... ...... ....... ...... ....... ...... ....... ....203

20.5 Pin Pull-up .....................................................................................................204

20.6 Pin Driver Strength ........................................................................................207

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20.7 Pin Threshold and Hysteresis ........................................................................211

20.8 BOD and Bandgap ........................................................................................214

20.9 Internal Oscillator Speed ...............................................................................216

20.10 Current Consumption of Peripheral Units ........................ ... ... ... .... ... ... ... .... ... .218

20.11 Current Consumption in Reset and Reset Pulsewidth ..................................221

21 Register Summary ............................................................................... 223

22 Instruction Set Summary .................................................................... 225

23 Ordering Information ........................................................................... 227

23.1 ATtiny261 - Mature ........................................................................................227

23.2 ATtiny461 ......................................................................................................229

23.3 ATtiny861 ......................................................................................................230

24 Packaging Information ........................................................................ 231

24.1 32M1-A ..........................................................................................................231

24.2 20P3 ..............................................................................................................232

24.3 20S2 ..............................................................................................................233

25 Errata ..................................................................................................... 234

25.1 Errata ATtiny261 ............................................................................................234

25.2 Errata ATtiny461 ............................................................................................234

25.3 Errata ATtiny861 ............................................................................................234

26 Datasheet Revision History ................................................................ 235

26.1 Rev. 2588F – 06/13 .......................................................................................235

26.2 Rev. 2588E – 08/10 ............ ... ... ... .................... ... ... ................... .... ... ..............235

26.3 Rev. 2588D – 06/10 .......................................................................................235

26.4 Rev. 2588C – 10/09 .......................................................................................235

26.5 Rev. 2588B – 11/06 ............ ... ... ... .................... ... ... ................... .... ... ..............236

26.6 Rev. 2588A – 10/06 ............ ... ... ... .................... ... ... ................... .... ... ..............236

Table of Contents....................................................................................... i

2588F–AVR–06/2013

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