Datasheet
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S124 Microcontroller Group
Datasheet
Renesas Synergy™ Platform
Synergy Microcontrollers
S1 Series
Feb 2018Rev.1.30
All information contained in these materials, including products and product specifications,
represents information on the product at the time of publication and is subject to change by
Renesas Electronics Corp. without notice. Please review the latest information published by
Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.
website (http://www.renesas.com).
Cover
R01DS0264EU0130 Rev.1.30 Page 2 of 104
Feb 5, 2018
Features
■ Arm Cortex-M0+ Core
Armv6-M architecture
Maximum operating frequ e ncy: 32 MHz
Debug and Trace: DWT, BPU, CoreSight™ MTB-M0+
CoreSight Debug Port: SW-DP
■ Memory
128-KB code flash memory
4-KB data flash memory (100,000 erase/write cycles)
Up to 16-KB SRAM
128-bit unique ID
■ Connectivity
USB 2.0 Full-Speed Module (USBFS)
- On-chip transceiver with voltage regulator
- Compliant with USB Battery Charging Specification 1.2
Serial Communications Interface (SCI) × 3
- UART
- Simple IIC
- Simple SPI
Serial Peripheral Interface (SPI) × 2
I2C bus interface (IIC) × 2
CAN module (CAN)
■ Analog
14-Bit A/D Converter (ADC14)
12-Bit D/A Converter (DAC12)
Low-Power Analog Comparator (ACMPLP) × 2
Temperature Sensor (TSN)
■ Timers
General PWM Timer 32-Bit (GPT32)
General PWM Timer 16-Bit (GPT16) × 6
Asynchronous Genera l-Pu rp ose Tim er (AGT) × 2
Watchdog Timer (WDT)
■ Safety
SRAM Parity Error Check
Flash Area Protection
ADC self-diagnosis function
Clock Frequency Accuracy Measurement Circuit (CAC)
Cyclic Redundancy Check (CRC) Calculator
Data Operation Circuit (DOC)
Port Output Enable for GPT (POEG)
Independent Watchdog Timer (IWDT)
GPIO Readback Level Detection
Register Write Protection
Main Oscillator Stop Detection
■ System and Power Management
Low-power modes
Realtime Clock (RTC)
Event Link Controller (ELC)
Data Transfer Controller (DTC)
Key Interrupt Function (KINT)
Power-on reset
Low Voltage Detection with voltage settings
■ Security and Encryption
AES128/256
True Random Number Gen erato r (T RNG)
■ Human Machine Interface (HMI)
Capacitive Touch Sensing Unit (CTSU)
■ Multiple Clock Sources
Main clock oscillator (MOSC)
(1 to 20 MHz when VCC = 2.4 to 5.5 V)
(1 to 8 MHz when VCC = 1.8 to 5.5 V)
(1 to 4 MHz when VCC = 1.6 to 5.5 V)
Sub-clock oscillator (SOSC) (32.768 kHz)
High-speed on-chip oscillator (HOCO)
(24, 32, 48, 64 MHz when VCC = 2.4 to 5.5 V)
(24, 32, 48 MHz when VCC = 1.8 to 5.5 V)
(24, 32 MHz when VCC = 1.6 to 5.5 V)
Middle-speed on-chip oscillator (MOCO) (8 MHz)
Low-speed on-chip oscillator (LOCO) (32.768 kHz)
Independent watchdog timer OCO (15 kHz)
Clock trim function for HOCO/MOCO/LOCO
Clock out support
■ General Purpose I/O Ports
Up to 51 input/output pins
- Up to 3 CMOS input
- Up to 48 CMOS input/output
- Up to 6 input/output 5 V tolerant
- Up to 16 pins high current (20 mA)
■ Operating Voltage
VCC: 1.6 to 5.5 V
■ Operating Temperature and Packages
Ta = –40°C to +85°C
- 36-pin LGA (4 mm × 4 mm, 0.5 mm pitch)
Ta = –40°C to +105°C
- 64-pin LQFP (10 mm × 10 mm, 0.5 mm pitch)
- 48-pin LQFP (7 mm × 7 mm, 0. 5 mm pitch)
- 64-pin QFN (8 mm × 8 mm, 0.4 mm pitch)
- 48-pin QFN (7 mm × 7 mm, 0.5 mm pitch)
- 40-pin QFN (6 mm × 6 mm, 0.5 mm pitch)
Ultra-low power 32-MHz Arm® Cortex®-M0+ microcontroller, 128-KB code flash memory, 16-KB SRAM, Capacitive
Touch Sensing Unit, 14-bit A/D Converter, 12-bit D/A Converter, security and safety features.
Features
S124 Microcontroller Group
Datasheet
Features
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S124 Datasheet 1. Overview
1. Overview
The MCU integrates multiple series of software- and pin-compatible Arm®-based 32-bit MCUs that share a common set
of Renesas peripherals to facilitate design scalability and efficient platform-based product development.
Based on the energy-efficient Arm Cortex®-M0+ core, the MCU is particularly well suited for cost-sensitive and low-
power applications with the following features:
128-KB code flash me mory
16-KB SRAM
Capacitive Touch Sensing Unit (CTSU)
14-bit A/D Converter (ADC14)
12-bit D/A Converter (DAC12)
Security features.
1.1 Function Outline
Table 1.1 Arm core
Feature Functional description
Arm Cortex-M0+ Maximum operating frequency: up to 32 MHz
Arm Cortex-M0+:
- Revision: r0p1-00rel0
- Armv6-M architecture profile
- Single-cycle integer multiplier.
SysTick timer
- Driven by SYSTICCLK (LOCO) or ICLK.
Table 1.2 Memory
Feature Functional description
Code flash memory Maximum 128 KB code flash memory. See section 37, Flash Memory in User’s Manual.
Data flash memory 4 KB data flash memory. See section 37, Flash Memory in User’s Manual.
Option-setting memory The option-setting memory determines the state of the MCU after a reset. See section 6,
Option-Setting Memory in User’s Manual.
SRAM On-chip high-speed SRAM with even parity bit. See section 36, SRAM in User’s Manual.
Table 1.3 System (1 of 2)
Feature Functional description
Operating mode Two operating modes:
Single-chip mode
SCI boot mode.
See section 3, Operating Modes in User’s Manual.
Reset 9 types of resets:
RES pin reset
Power-on reset
Independent watchdog timer reset
Watchdog timer reset
Voltage monitor 0 reset
Voltage monitor 1 reset
Voltage monitor 2 reset
SRAM parity error reset
Software reset.
See section 5, Resets in User’s Manual.
Low Voltage Detection (LVD) The Low Voltage Detection (LVD) monitors the voltage level input to the VCC pin and the
detection level can be selected using a software program. See section 7, Low Voltage
Detection (LVD) in User’s Manual.
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S124 Datasheet 1. Overview
Clock Main clock oscillator (MOSC)
Sub-clock oscillator (SOSC)
High-speed on-chip oscillator (HOCO)
Middle-speed on-chip oscillator (MOCO)
Low-speed on-chip oscillator (LOCO)
Independent watchdog timer on-chip oscillator
Clock out support.
See section 8, Clock Generation Circuit in User’s Manual.
Clock Frequency Accuracy
Measurement Circuit (CAC)
The Clock Frequency Accuracy Measurement Circuit (CAC) is used to check the system clock
frequency with a reference clock signal by counting the number of pulses of the system clock
to be measured. The reference clock can be provided externally through a CACREF pin or
internally from various on-chip oscillators.
Event signals can be generated when the clock does not match or measurement ends.
This feature is particularly useful in implementing a fail-safe mechanism for home and
industrial automation applications.
See section 9, Clock Frequency Accuracy Measurement Circuit (CAC) in User’s Manual.
Interrupt Controller Unit (ICU) The Interrupt Controller Unit (ICU) controls which event signals are linked to the NVIC/DTC
module and DMAC module. The ICU also controls NMI interrupts. See section 12, Interrupt
Controller Unit (ICU) in User’s Manual.
Key interrupt function (KINT) A key interrupt can be generated by setting the Key Return Mode register (KRM) and inputting
a rising or falling edge to the key interrupt input pins. See section 17, Key Interrupt Function
(KINT) in User’s Manual.
Low Power Mode Power consumption can be reduced in multiple ways, including setting clock dividers, stopping
modules, selecting power control mode in normal operation, and transitioning to low power
modes. See section 10, Low Power Modes in User’s Manual.
Register Write Protection The Register Write Protection function protects important registers from being overwritten due
to software errors. See section 11, Register Write Protection in User’s Manual.
Watchdog Timer (WDT) The Watchdog Timer (WDT) is a 14-bit down-counter. It can be used to reset the MCU when
the counter underflows because the system has run out of control and is unable to refresh the
WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The
refresh-permitted period can be set to refresh the counter and used as the condition to detect
when the system runs out of control. See section 22, Watchdog Timer (WDT) in User’s
Manual.
Independent Watchdog Timer (IWDT) The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be
serviced periodically to prevent counter underflow. The IWDT provides functionality to reset
the MCU or to generate a non-maskable interrupt/interrupt for a timer underflow. Because the
timer operates with an independent, dedicated clock source, it is particularly useful in returning
the MCU to a known state as a fail safe mechanism when the system runs out of control. The
watchdog timer can be triggered automatically on reset, underflow, or refresh error, or by a
refresh of the count value in the registers. See section 23, Independent Watchdog Timer
(IWDT) in User’s Manual.
Table 1.4 Event Link
Feature Functional description
Event Link Controller (ELC) The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral
modules as event signals to connect them to different modules, enabling direct interaction
between the modules without CPU intervention. See section 15, Event Link Controller (ELC) in
User’s Manual.
Table 1.5 Direct memory access
Feature Functional description
Data Transfer Controller (DTC) The MCU incorporates a Data Transfer Controller (DTC) that performs data transfers when
activated by an interrupt request. See section 14, Data Transfer Controller (DTC) in User’s
Manual.
Table 1.3 System (2 of 2)
Feature Functional description
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S124 Datasheet 1. Overview
Table 1.6 Timers
Feature Functional description
General PWM Timer (GPT) The General PWM Timer (GPT) is a 32-bit timer with 1 channel and a 16-bit timer with 6
channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or
the up- and down-counter. In addition, PWM waveforms for controlling brushless DC motors
can be generated. The GPT can also be used as a general-purpose timer. See section 19,
General PWM Timer (GPT) in User’s Manual.
Port Output Enable for GPT (POEG) Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)
output pins in the output disable state. See section 18, Port Output Enable for GPT (POEG) in
User’s Manual.
Asynchronous General Purpose
Timer (AGT)
The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse
output, external pulse width or period measurement, and counting external events.
This 16-bit timer consists of a reload register and a down-counter. The reload register and the
down-counter are allocated to the same address, and they can be accessed with the AGT
register. See section 20, Asynchronous General Purpose Timer (AGT) in User’s Manual.
Realtime Clock (RTC) The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count
mode, that are used by switching register settings.
For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and
automatically adjusts dates for leap years.
For binary count mode, the RTC counts seconds and retains the information as a serial value.
Binary count mode can be used for calendars other than the Gregorian (Western) calendar.
See section 21, Realtime Clock (RTC) in User’s Manual.
Table 1.7 Communication interfaces (1 of 2)
Feature Functional description
Serial Communications Interface
(SCI)
The Serial Communication Interface (SCI) is configurable to five asynchronous and
synchronous serial interfaces:
Asynchronous interfaces (UART and asynchronous communications interface adapter
(ACIA))
8-bit clock synchronous interface
Simple IIC (master-only)
Simple SPI
Smart card interface
The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and
transmission protocol.
SCI0 has FIFO buffers to enable continuous and full-duplex communication, and the data
transfer speed can be configured independently using an on-chip baud rate generator. See
section 25, Serial Communications Interface (SCI) in User’s Manual.
I2C Bus interface (IIC) The MCU has a two-channel I2C bus interface (IIC).
The IIC module conforms with and provides a subset of the NXP I2C bus (Inter-Integrated
Circuit bus) interface functions. See section 26, I2C Bus Interface (IIC) in User’s Manual.
Serial Peripheral Interface (SPI) The MCU includes two independent channels of the Serial Peripheral Interface (SPI). The SPI
channels are capable of high-speed, full-duplex synchronous serial communications with
multiple processors and peripheral devices. See section 28, Serial Peripheral Interface (SPI) in
User’s Manual.
Controller Area Network (CAN)
Module
The Controller Area Network (CAN) module provides functionality to receive and transmit data
using a message-based protocol between multiple slaves and masters in electromagnetically
noisy applications.
The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports
up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox
and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are
supported. See section 27, Controller Area Network (CAN) Module in User’s Manual.
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S124 Datasheet 1. Overview
USB 2.0 Full-Speed Module (USBFS) The MCU incorporates a USB 2.0 Full-Speed module (USBFS). The USBFS is a USB
controller that is equipped to operate as a device controller. The module supports full-speed
and low-speed transfer as defined in the Universal Serial Bus Specification 2.0. The module
has an internal USB transceiver and supports all of the transfer types defined in the Universal
Serial Bus Specification 2.0.
The USB has buffer memory for data transfer, providing a maximum of 5 pipes. PIPE0 and
PIPE4 to PIPE7 can be assigned any endpoint number based on the peripheral devices used
for communication or based on the user system.
The MCU supports revision 1.2 of the battery charging specification. Because the MCU can be
powered at 5 V, the USB LDO regulator provides the internal USB transceiver power supply
3.3 V. See section 24, USB 2.0 Full-Speed Module (USBFS) in User’s Manual.
Table 1.8 Analog
Feature Functional description
14-bit A/D Converter (ADC14) The MCU incorporates up to one unit of a 14-bit successive approximation A/D converter. Up
to 18 analog input channels are selectable. Temperature sensor output and internal reference
voltage are selectable for conversion. The A/D conversion accuracy is selectable from 12-bit
and 14-bit conversion making it possible to optimize the tradeoff between speed and resolution
in generating a digital value. See section 30, 14-Bit A/D Converter (ADC14) in User’s Manual.
12-bit D/A Converter (DAC12) The MCU includes a 12-bit D/A converter with an output amplifier. See section 31, 12-Bit D/A
Converter (DAC12) in User’s Manual.
Temperature Sensor (TSN) The on-chip Temperature Sensor can be used to determine and monitor the die temperature
for reliable operation of the device. The sensor outputs a voltage directly proportional to the die
temperature, and the relationship between the die temperature and the output voltage is linear.
The output voltage is provided to the ADC14 for conversion and can be further used by the end
application. See section 32, Temperature Sensor (TSN) in User’s Manual.
Low-Power Analog Comparator
(ACMPLP)
Analog comparators can be used to compare a reference input voltage and analog input
voltage. The comparison result can be read by software and also be output externally. The
reference input voltage can be selected from either an input to the CMPREFi (i = 0, 1) pin or
from the internal reference voltage (Vref) generated internally in the MCU.
The ACMPLP response speed can be set before starting an operation. Setting high-speed
mode decreases the response delay time, but increases current consumption. Setting low-
speed mode increases the response delay time, but decreases current consumption. See
section 33, Low-Power Analog Comparator (ACMPLP) in User’s Manual.
Table 1.9 Human machine interfaces
Feature Functional description
Capacitive Touch Sensing Unit
(CTSU)
The Capacitive Touch Sensing Unit (CTSU) measures the electrostatic capacitance of the
touch sensor. Changes in the electrostatic capacitance are determined by software, which
enables the CTSU to detect whether a finger is in contact with the touch sensor. The electrode
surface of the touch sensor is usually enclosed with an electrical insulator so that a finger does
not come into direct contact with the electrode. See section 34, Capacitive Touch Sensing Unit
(CTSU) in User’s Manual.
Table 1.10 Data processing
Feature Functional description
Cyclic Redundancy Check (CRC)
Calculator
The Cyclic Redundancy Check (CRC) calculator generates CRC codes to detect errors in the
data. The bit order of CRC calculation results can be switched for LSB first or MSB first
communication. Additionally, various CRC generation polynomials are available. The snoop
function allows monitoring reads from and writes to specific addresses. This function is useful
in applications that require CRC code to be generated automatically in certain events, such as
monitoring writes to the serial transmit buffer and reads from the serial receive buffer. See
section 29, Cyclic Redundancy Check (CRC) Calculator in User’s Manual.
Data Operation Circuit (DOC) The Data Operation Circuit (DOC) is used to compare, add, and subtract 16-bit data. See
section 35, Data Operation Circuit (DOC) in User’s Manual.
Table 1.7 Communication interfaces (2 of 2)
Feature Functional description
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S124 Datasheet 1. Overview
1.2 Block Diagram
Figure 1.1 shows the block diagram of the MCU superset. Individual devices within the group ma y have a subset of the
features.
Figure 1.1 Block diagram
1.3 Part Numbering
Figure 1.2 shows how to read the product part number, memory capacity, and package types. Table 1.12 shows a list of
products.
Table 1.11 Security
Feature Functional description
AES See section 38, AES Engine in User’s Manual
True Random Number Generator
(TRNG)
See section 39, True Random Number Generator (TRNG) in User’s Manual
Memories
128/64 KB Code
Flash
4 KB Data Flash
16 KB SRAM
DMA
System
Mode Control
Power Control
Interrupt
Controller Unit
MOSC/SOSC
Clocks
(H/M/L) OCO
GPT32 × 1
GPT16 × 6
Timers
AGT × 2
RTC
CTSU
KINT
Arm Cortex-M0+
NVIC
System Timer
Test and DBG I/F
DTC
WDT/IWDT
CAC
POR/LVD
Reset
Human Machine Interfaces
ELC
Event Link
AES + TRNG
Security
Analogs
CRC
Data Processing
DOC
Communication Interfaces
IIC × 2
SPI × 2 CAN × 1
USBFS
with BC1.2
SCI × 3
TSN
DAC12 ACMPLP × 2
ADC14
Register Write
Protection
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S124 Datasheet 1. Overview
Figure 1.2 Part numbering scheme
Note: Earlier products with orderable part number suffix AA0 and AC0 have a restriction in AES functions. If AES
functions are required for your application, refer to the products with orderable part number suffix AA1 or AC1.
For details on the differences of AES functions between AA0/AC0 and AA1/AC1 products, see Technical Update
(TN-SY*-A024A/E). Contact your Renesas sales representative for additional information.
Table 1.12 Product list
Product part number Orderable part number Package code Code flash Data flash SRAM
Operating
temperature
R7FS124773A01CFM R7FS124773A01CFM#AA1 PLQP0064KB-C 128 KB 4 KB 16 KB –40 to +105°C
R7FS124773A01CNB R7FS124773A01CNB#AC1 PWQN0064LA-A –40 to +105°C
R7FS124773A01CFL R7FS124773A01CFL#AA1 PLQP0048KB-B –40 to +105°C
R7FS124773A01CNE R7FS124773A01CNE#AC1 PWQN0048KB-A –40 to +105°C
R7FS124773A01CNF R7FS124773A01CNF#AC1 PWQN0040KC-A –40 to +105°C
R7FS124772A01CLM R7FS124772A01CLM#AC1 PWLG0036KA-A –40 to +85°C
R7FS124763A01CFM R7FS124763A01CFM#AA1 PLQP0064KB-C 64 KB –40 to +105°C
R7FS124763A01CFL R7FS124763A01CFL#AA1 PLQP0048KB-B –40 to +105°C
R7FS124762A01CLM R7FS124762A01CLM#AC1 PWLG0036KA-A –40 to +85°C
7 3 A 0 1 C F M # A A 1
Package type
FM: LQFP 64 pins
FL: LQFP 48 pins
LM: LGA 36 pins
NB: QFN 64 pins
NE: QFN 48 pins
NF: QFN 40 pins
Quality ID
Software ID
Operating temperature
2: -40° C to 85° C
3: -40° C to 105° C
Code flash memory size
6: 64 KB
7: 128 KB
Feature set
7: Superset
Group name
24: S124 Group, Arm Cortex-M0+, 32 MHz
Series name
1: Ultra low power
Renesas Synergy family
Flash memory
Renesas microcontroller
Renesas
R 7 F S 1 2 4 7
Product identification code
Packing, terminal material (Pb-free)
#AA: Tray/Sn (Tin) only
#AC: Tray/others
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S124 Datasheet 1. Overview
1.4 Function Comparison
Table 1.13 Function comparison
Parts number
R7FS124773A01CFM/
R7FS124763A01CFM/
R7FS124773A01CNB/
R7FS124773A01CFL/
R7FS124763A01CFL/
R7FS124773A01CNE R7FS124773A01CNF
R7FS124772A01CLM/
R7FS124762A01CLM
Pin count 64 48 40 36
Package LQFP/QFN LQFP/QFN QFN LGA
Code flash memory 128/64 KB
Data flash memory 4 KB
SRAM 16 KB
Parity 4 KB
System CPU clock 32 MHz
ICU Yes
KINT8 554
Event link ELC Yes
DMA DTC Yes
Timers GPT32 1
GPT166 644
AGT2 222
RTC Yes
WDT/IWDT Yes
Communication SCI 3
IIC 2
SPI 2
CAN Yes
USBFS Yes
Analog ADC14 18 14 12 11
DAC12 1
ACMPLP 2
TSN Yes
HMICTSU31 231713
KINT8 554
Data processing CRC Yes
DOC Yes
Security AES and TRNG
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S124 Datasheet 1. Overview
1.5 Pin Functions
Table 1.14 Pin functions (1 of 3)
Function Signal I/O Description
Power supply VCC Input Power supply pin. Connect it to the system power supply. Connect this pin
to VSS by a 0.1-μF capacitor. The capacitor should be placed close to the
pin.
VCL Input Connect this pin to the VSS pin by the smoothing capacitor used to stabilize
the internal power supply. Place the capacitor close to the pin.
VSS Input Ground pin. Connect it to the system power supply (0 V).
Clock XTAL Output Pins for a crystal resonator. An external clock signal can be input through
the EXTAL pin.
EXTAL Input
XCIN Input Input/output pins for the sub-clock oscillator. Connect a crystal resonator
between XCOUT and XCIN.
XCOUT Output
CLKOUT Output Clock output pin.
Operating mode control MD Input Pins for setting the operating mode. The signal levels on these pins must
not be changed during operation mode transition at the time of release from
the reset state.
System control RES Input Reset signal input pin. The MCU enters the reset state when this signal
goes low.
CAC CACREF Input Measurement reference clock input pin.
On-chip debug SWDIO I/O Serial Wire debug Data Input/Output pin.
SWCLK Input Serial Wire Clock pin.
Interrupt NMI Input Non-maskable interrupt request pin.
IRQ0 to IRQ7 Input Maskable interrupt request pins.
GPT GTETRGA,
GTETRGB
Input External trigger input pin.
GTIOC0A to
GTIOC6A,
GTIOC0B to
GTIOC6B
I/O Input capture, Output Compare, or PWM output pin.
GTIU Input Hall sensor input pin U.
GTIV Input Hall sensor input pin V.
GTIW Input Hall sensor input pin W.
GTOUUP Output Three-phase PWM output for BLDC motor control (positive U phase).
GTOULO Output Three-phase PWM output for BLDC motor control (negative U phase).
GTOVUP Output Three-phase PWM output for BLDC motor control (positive V phase).
GTOVLO Output Three-phase PWM output for BLDC motor control (negative V phase).
GTOWUP Output Three-phase PWM output for BLDC motor control (positive W phase).
GTOWLO Output Three-phase PWM output for BLDC motor control (negative W phase).
AGT AGTEE0,
AGTEE1
Input External event input enable.
AGTIO0, AGTIO1 I/O External event input and pulse output.
AGTO0, AGTO1 Output Pulse output.
AGTOA0,
AGTOA1
Output Output compare match A output.
AGTOB0,
AGTOB1
Output Output compare match B output.
RTC RTCOUT Output Output pin for 1-Hz/64-Hz clock.
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S124 Datasheet 1. Overview
SCI SCK0, SCK1,
SCK9
I/O Input/output pins for the clock (clock synchronous mode).
RXD0, RXD1,
RXD9
Input Input pins for received data (asynchronous mode/clock synchronous
mode).
TXD0, TXD1,
TXD9
Output Output pins for transmitted data (asynchronous mode/clock synchronous
mode).
CTS0_RTS0,
CTS1_RTS1,
CTS9_RTS9
I/O Input/Output pins for controlling the start of transmission and reception
(asynchronous mode/clock synchronous mode), active-low.
SCL0, SCL1,
SCL9
I/O Input/output pins for the IIC clock (simple IIC).
SDA0, SDA1,
SDA9
I/O Input/output pins for the IIC data (simple IIC).
SCK0, SCK1,
SCK9
I/O Input/output pins for the clock (simple SPI).
MISO0, MISO1,
MISO9
I/O Input/output pins for slave transmission of data (simple SPI).
MOSI0, MOSI1,
MOSI9
I/O Input/output pins for master transmission of data (simple SPI).
SS0, SS1, SS9 Input Chip-select input pins (simple SPI), active-low.
IIC SCL0, SCL1 I/O Input/output pins for clock.
SDA0, SDA1 I/O Input/output pins for data.
SPI RSPCKA,
RSPCKB
I/O Clock input/output pin.
MOSIA, MOSIB I/O Inputs or outputs data output from the master.
MISOA, MISOB I/O Inputs or outputs data output from the slave.
SSLA0, SSLB0 I/O Input or output pin for slave selection.
SSLA1 to SSLA3,
SSLB1 to SSLB3
Output Output pin for slave selection.
CAN CRX0 Input Receive data.
CTX0 Output Transmit data.
USBFS VSS_USB Input Ground pins.
VCC_USB_LDO Input Power supply pin for USB LDO regulator.
VCC_USB I/O Input: Power supply pin for USB transceiver.
Output: USB LDO regulator output pin. This pin should be connected to an
external capacitor.
USB_DP I/O D+ I/O pin of the USB on-chip transceiver. This pin should be connected to
the D+ pin of the USB bus.
USB_DM I/O D– I/O pin of the USB on-chip transceiver. This pin should be connected to
the D– pin of the USB bus.
USB_VBUS Input USB cable connection monitor pin. This pin should be connected to VBUS
of the USB bus. The VBUS pin status (connected or disconnected) can be
detected when the USB module is operating as a function controller.
Analog power supply AVCC0 Input Analog block power supply pin
AVSS0 Input Analog block power supply ground pin
VREFH0 Input Reference power supply pin
VREFL0 Input Reference power supply ground pin
ADC14 AN000 to AN010,
AN016 to AN022
Input Input pins for the analog signals to be processed by the A/D converter.
ADTRG0 Input Input pins for the external trigger signals that start the A/D conversion,
active-low.
DAC12 DA0 Output Output pins for the analog signals to be processed by the D/A converter.
Table 1.14 Pin functions (2 of 3)
Function Signal I/O Description
R01DS0264EU0130 Rev.1.30 Page 12 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
ACMPLP VCOUT Output Comparator output pin.
CMPREF0,
CMPREF1
Input Reference voltage input pins.
CMPIN0,
CMPIN1
Input Analog voltage input pins.
CTSU TS00 to TS28,
TS30, TS31
Input Capacitive touch detection pins (touch pins).
TSCAP - Secondary power supply pin for the touch driver.
KINT KR00 to KR07 Input Key interrupt input pins.
I/O ports P000 to P004,
P010 to P015
I/O General-purpose input/output pins.
P100 to P113 I/O General-purpose input/output pins.
P200 Input General-purpose input pin.
P201, P204 to
P206, P212,
P213
I/O General-purpose input/output pins.
P214, P215 Input General-purpose input pins.
P300 to P304 I/O General-purpose input/output pins.
P400 to P403,
P407 to P411
I/O General-purpose input/output pins.
P500 to P502 I/O General-purpose input/output pins.
Table 1.14 Pin functions (3 of 3)
Function Signal I/O Description
R01DS0264EU0130 Rev.1.30 Page 13 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
1.6 Pin Assignments
Figure 1.3 to Figure 1.8 show the pin assignments.
Figure 1.3 Pin assignment for LQFP 64-pin (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
P501
P502
P015
P014
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P004
P003
P002
P001
P013
P300/SWCLK
P301
P302
P303
P304
P201/MD
RES
P204
P205
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
VSS_USB
P200
P100
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P108/SWDIO
P101
P109
P400
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P408
P407
P401
P409
P000
R7FS1247x3A01CFM
P500
R01DS0264EU0130 Rev.1.30 Page 14 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
Figure 1.4 Pin assignment for QFN 64-pin (top view)
P300/SWCLK
P301
P302
P303
P304
P201/MD
RES
P204
P205
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
VSS_USB
P200
P100
P102
P103
P104
P105
P106
P107
VSS
VCC
P113
P112
P111
P110
P108/SWDIO
P101
P109
P400
P402
P403
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P411
P410
P408
P407
P401
P409
R7FS1247x3A01CNB
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49P500
P501
P502
P015
P014
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P004
P003
P002
P001
P000
P013
R01DS0264EU0130 Rev.1.30 Page 15 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
Figure 1.5 Pin assignment for LQFP 48-pin (top view)
Figure 1.6 Pin assignment for QFN 48-pin (top view)
1
2
3
4
5
6
7
8
9
10
11
12
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
37
38
39
40
41
42
43
44
45
46
47
48
P500
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P002
P001
P015
P300/SWCLK
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
VSS_USB
P301
P100
P101
P102
P103
P104
VSS
VCC
P112
P111
P110
P108/SWDIO
P109
P400
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
P401
P409
P000
R7FS1247x3A01CFL
P300/SWCLK
P302
P200
P201/MD
RES
P206
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
VSS_USB
P301
P100
P102
P103
P104
VSS
VCC
P112
P111
P110
P109
P108/SWDIO
P101
P400
VCL
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P409
P408
P407
P401
R7FS1247x3A01CNE
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
P500
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P002
P001
P000
P015
R01DS0264EU0130 Rev.1.30 Page 16 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
Figure 1.7 Pin assignment for QFN 40-pin (top view)
Figure 1.8 Pin assignment for LGA 36-pin (top view, pad side down)
P300/SWCLK
P301
P200
P201/MD
RES
VCC_USB_LDO
VCC_USB
USB_DP
USB_DM
VSS_USB
P100
P102
P103
P104
P112
P111
P110
P109
P108/SWDIO
P101
P400
P215/XCIN
P214/XCOUT
VSS
P213/XTAL
P212/EXTAL
VCC
P408
P407
VCL
R7FS1247x3A01CNF
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
10
9
8
7
6
5
4
3
2
1
40
39
38
37
36
35
34
33
32
31
P015
P014
P013
P012
AVCC0
AVSS0
P011/VREFL0
P010/VREFH0
P001
P000
AVSS0
AVCC0
P014
P015
P011
/VREFL0
P012
P013
P100
P214
/XCOUT
P400
P103
P102
P101
P112
VSS
P212
/EXTAL
P213
/XTAL
P109
P110
P111
VCC
P407
RES
P201/MD
P200
P108
/SWDIO
VSS_USB
USB_DM
USB_DP
VCC_USB
VCC_USB
_LDO
P300
/SWCLK
P000
P215
/XCIN
VCL
P010
/VREFH0
R7FS1247x2A01CLM
6
5
4
3
2
1
6
5
4
3
2
1
D E FA B C
D E FA B C
R01DS0264EU0130 Rev.1.30 Page 17 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
1.7 Pin Lists
Pin number
Power, System,
Clock, Debug,
CAC
I/O ports
Timers Communication Interfaces Analogs HMI
LQFP64, QFN64
LQFP48
QFN48
QFN40
LGA36
AGT
GPT_OPS, POEG
GPT
RTC
USBFS,CAN
SCI
IIC
SPI
ADC14
DAC12, ACMPLP
CTSU
Interrupt
1111C2CACREF_
C
P400 AGTIO1_
D
GTIOC6A
_A
SCK0_B/
SCK1_B
SCL0_A TS20 IRQ0
222- - P401 GTETRG
A_B
GTIOC6B
_A
CTX0_B CTS0_RT
S0_B/
SS0_B/
TXD1_B/
MOSI1_B/
SDA1_B
SDA0_A TS19 IRQ5
3 - - - - P402 CRX0_B RXD1_B/
MISO1_B/
SCL1_B
TS18 IRQ4
4---- P403 GTIOC3A
_B
CTS1_RT
S1_B/
SS1_B
TS17
5332A1VCL
6443B1XCINP215
7 5 5 4 C1 XCOUT P214
8665D1VSS
9776D3XTALP213 GTETRG
A_D
TXD1_A/
MOSI1_A/
SDA1_A
IRQ2
10 8 8 7 D2 EXTAL P212 AGTEE1 GTETRG
B_D
RXD1_A/
MISO1_A/
SCL1_A
IRQ3
11 9 9 8 E1 VC C
12 - - - - P411 AGTOA1 GTOVUP
_B
GTIOC6A
_B
TXD0_B/
MOSI0_B/
SDA0_B
MOSIA_B TS07 IRQ4
13 - - - - P410 AGTOB1 GTOVLO
_B
GTIOC6B
_B
RXD0_B/
MISO0_B/
SCL0_B
MISOA_B TS06 IRQ5
14 10 10 - - P409 GTOWUP
_B
GTIOC5A
_B
TXD9_A/
MOSI9_A/
SDA9_A
TS05 IRQ6
15 11 11 9 - P408 GTOWLO
_B
GTIOC5B
_B
RXD9_A/
MISO9_A/
SCL9_A
TS04 IRQ7
16 12 12 10 E2 P407 RTCOUT USB_VBU
S
CTS0_RT
S0_D/
SS0_D
SDA0_B SSLB3_A ADTRG0_
B
TS03
17 13 13 11 F1 VSS_USB
18 14 14 12 F2 USB_DM
19 15 15 13 F3 USB_DP
20 16 16 14 F4 VCC_US
B
21 17 17 15 F5 VCC_US
B_LDO
22 18 18 - - P206 GTIU_A RXD0_D/
MISO0_D/
SCL0_D
SDA1_A SSLB1_A TS01 IRQ0
23 - - - - CLKOUT_
A
P205 AGTO1 GTIV_A GTIOC4A
_B
TXD0_D/
MOSI0_D/
SDA0_D/
CTS9_RT
S9_A/
SS9_A
SCL1_A SSLB0_A TSCAP_A IRQ1
24----CACREF_
A
P204 AGTIO1_
A
GTIW_A GTIOC4B
_B
SCK0_D/
SCK9_A
SCL0_B RSPCKB_
A
TS00
25 19 19 16 E3 RES
26 20 20 17 E4 MD P201
27 21 21 18 E5 P200 NMI
28 - - - - P304 GTIOC1A
_B
29 - - - - P303 GTIOC1B
_B
TS02
30 22 22 - - P302 GTOUUP
_A
GTIOC4A
_A
SSLB3_B TS08 IRQ5
31 23 23 19 - P301 GTOULO
_A
GTIOC4B
_A
SSLB2_B TS09 IRQ6
32 24 24 20 F6 SWCLK P300 GTOUUP
_C
GTIOC0A
_A
SSLB1_B
33 25 25 21 E6 SWDIO P108 GTOULO
_C
GTIOC0B
_A
CTS9_RT
S9_B/
SS9_B
SSLB0_B
34 26 26 22 D4 CLKOUT_
B
P109 GTOVUP
_A
GTIOC1A
_A
CTX0_A TXD9_B/
MOSI9_B/
SDA9_B
MOSIB_B TS10
R01DS0264EU0130 Rev.1.30 Page 18 of 104
Feb 5, 2018
S124 Datasheet 1. Overview
Note: Several pin names have the added suffix of _A, _B, _C, and _D. The suffix can be ignored when assigning
functionality.
35 27 27 23 D5 P110 GTOVLO
_A
GTIOC1B
_A
CRX0_A CTS0_RT
S0_C/
SS0_C/
RXD9_B/
MISO9_B/
SCL9_B
MISOB_B VCOUT TS11 IRQ3
36 28 28 24 D6 P111 GTIOC3A
_A
SCK0_C/
SCK9_B
RSPCKB_
B
TS12 IRQ4
37 29 29 25 C6 P112 GTIOC3B
_A
TXD0_C/
MOSI0_C/
SDA0_C
TSCAP_C
38---- P113
39 30 30 - - VCC
40 31 31 - - VSS
41 - - - - P107 GTIOC0A
_B
KR07
42 - - - - P106 GTIOC0B
_B
SSLA3_A KR06
43 - - - - P105 GTETRG
A_C
SSLA2_A KR05/
IRQ0
44 32 32 26 - P104 GTETRG
B_B
RXD0_C/
MISO0_C/
SCL0_C
SSLA1_A TS13 KR04/
IRQ1
45 33 33 27 C3 P103 GTOWUP
_A
GTIOC2A
_A
CTX0_C CTS0_RT
S0_A/
SS0_A
SSLA0_A AN019 CMPREF
1
TS14 KR03
46 34 34 28 C4 P102 AGTO0 GTOWLO
_A
GTIOC2B
_A
CRX0_C SCK0_A RSPCKA_
A
AN020/
ADTRG0_
A
CMPIN1 TS15 KR02
47 35 35 29 C5 P101 AGTEE0 GTETRG
B_A
GTIOC5A
_A
TXD0_A/
MOSI0_A/
SDA0_A/
CTS1_RT
S1_A/
SS1_A
SDA1_B MOSIA_A AN021 CMPREF
0
TS16 KR01/
IRQ1
48 36 36 30 B6 P100 AGTIO0_
A
GTETRG
A_A
GTIOC5B
_A
RXD0_A/
MISO0_A/
SCL0_A/
SCK1_A
SCL1_B MISOA_A AN022 CMPIN0 TS26 KR00/
IRQ2
49 37 37 - - P500 AGTOA0 GTIU_B GTIOC2A
_B
AN016 TS27
50 - - - - P501 AGTOB0 GTIV_B GTIOC2B
_B
AN017
51 - - - - P502 GTIW_B GTIOC3B
_B
AN018
52 38 38 31 A6 P015 AN010 TS28 IRQ7
53 39 39 32 A5 P014 AN009 DA0
54 40 40 33 B5 P013 AN008
55 41 41 34 B4 P012 AN007
56 42 42 35 A4 AVCC0
57 43 43 36 A3 AVSS0
58 44 44 37 B3 VREFL0 P011 AN006 TS31
59 45 45 38 A2 VREFH0 P010 AN005 TS30
60 - - - - P004 AN004 TS25 IRQ3
61 - - - - P003 AN003 TS24
62 46 46 - - P002 AN002 TS23 IRQ2
63 47 47 39 - P001 AN001 TS22 IRQ7
64 48 48 40 B2 P000 AN000 TS21 IRQ6
Pin number
Power, System,
Clock, Debug,
CAC
I/O ports
Timers Communication Interfaces Analogs HMI
LQFP64, QFN64
LQFP48
QFN48
QFN40
LGA36
AGT
GPT_OPS, POEG
GPT
RTC
USBFS,CAN
SCI
IIC
SPI
ADC14
DAC12, ACMPLP
CTSU
Interrupt
R01DS0264EU0130 Rev.1.30 Page 19 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2. Electrical Characteristics
Unless otherwise specified, the electrical characteristics of the MCU are defined under the following conditions:
VCC*1 = AVCC0 = VCC_USB*2 = VCC_USB_LDO*2 = 1.6 to 5.5V, VREFH0 = 1.6 to AVCC0,
VSS = AVSS0 = VREFL0 = VSS_USB = 0 V, Ta = Topr
Note 1. The typical condition is set to VCC = 3.3V.
Note 2. When USBFS is not used.
Figure 2.1 shows the timing conditions.
Figure 2.1 Input or output timing measurement conditions
The measurement conditions of timing specification in each peripherals are recommended for the best peripheral
operation. However, make sure to adjust driving abilities of each pins to meet your conditions.
Each function pin used for the same function must select the same drive ability. If I/O drive ability of each function is
mixed, the AC spec ification of the function is not guaranteed.
For example P100
C
VOH = VCC × 0.7, VOL = VCC × 0.3
VIH = VCC × 0.7, VIL = VCC × 0.3
Load capacitance C = 30pF
R01DS0264EU0130 Rev.1.30 Page 20 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Note: See the Total Operating Time (TOT) Utility located at http://www.renesas.com. This utility is provided for
educational and evaluation purposes only and is subject to the accompanying disclaimer.
Note 1. Ports P205, P206, P400, P401, and P407 are 5V-tolerant.
Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that
results from input of such a signal or I/O pull-up might cause malfunction and the abnormal current that passes in
the device at this time might cause degradation of internal elements.
Note 2. See section 2.2.1, Tj/Ta Definition.
Note 3. The upper limit of the operating temperature is 85°C or 105°C, depending on the product. For details, see section
1, Part Numbering
Caution: Permanent damage to the MCU may result if absolute maximum ratings are exceeded.
To preclude any malfunctions due to noise interference, insert capacitors of high frequency
characteristics between the VCC and VSS pins, between the AVCC0 and AVSS0 pins, between the
VCC_USB and VSS_USB pins, and between the VREFH0 and VREFL0 pins. Place capacitors of about
0.1 μF as close as possible to every power supply pin and use the shortest and heaviest possible
traces. Also, connect capacitors as stabilization capacitance.
Connect the VCL pin to a VSS pin by a 4.7-µF capacitor. The capacitor must be placed close to the
pin.
Table 2.1 Absolute maximum ratings
Parameter Symbol Value Unit
Power supply voltage VCC –0.5 to +6.5 V
Input voltage 5V-tolerant ports*1Vin –0.3 to +6.5 V
P000 to P004
P010 to P015
Vin –0.3 to AVCC0 + 0.3 V
Others Vin –0.3 to VCC + 0.3 V
Reference power supply voltage VREFH0 –0.3 to +6.5 V
Analog power supply voltage AVCC0 –0.5 to +6.5 V
USB power supply voltage VCC_USB –0.5 to +6.5 V
VCC_USB_LDO –0.5 to +6.5 V
Analog input voltage When AN000 to AN010 are
used
VAN –0.3 to AVCC0 + 0.3 V
When AN016 to AN022 are
used
–0.3 to VCC + 0.3 V
Operating temperature*2 *3Topr –40 to +85
–40 to +105
°C
Storage temperature Tstg –55 to +125 °C
R01DS0264EU0130 Rev.1.30 Page 21 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Use AVCC0 and VCC under the following conditions:
AVCC0 and VCC can be set individually within the operating range when VCC ≥ 2.2 V and AVCC0 ≥ 2.2 V
AVCC0 = VCC when VCC < 2.2 V or AVCC0 < 2.2 V.
Note 2. When powering on the VCC and AVCC0 pins, power them on at the same time or the VCC pin first and then the
AVCC0 pin.
Table 2.2 Recommended operating conditions
Parameter Symbol Value Min Typ Max Unit
Power supply voltages VCC*1, *2 When USBFS is not
used
1.6 - 5.5 V
When USBFS is used
USB Regulator
Disable
VCC_USB - 3.6 V
When USBFS is used
USB Regulator
Enable
VCC_USB
_LDO
-5.5V
VSS -0-V
USB power supply voltages VCC_USB When USBFS is not
used
-VCC-V
When USBFS is used
USB Regulator
Disable
(Input)
3.0 3.3 3.6 V
VCC_USB_LDO When USBFS is not
used
-VCC-V
When USBFS is used
USB Regulator
Enable
3.8 - 5.5 V
When USBFS is used
USB Regulator
Disable
-VCC-V
VSS_USB - 0 - V
Analog power supply voltages AVCC0*1, *2 1.6 - 5.5 V
AVSS0 - 0 - V
VREFH0 When used as
ADC14 Reference
1.6 - AVCC0 V
VREFL0 - 0 - V
R01DS0264EU0130 Rev.1.30 Page 22 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2 DC Characteristics
2.2.1 Tj/Ta Definition
Note: Make sure that Tj = Ta + θja × total power consumption (W), where total power consumption = (VCC – VOH) ×
ΣIOH + VOL × ΣIOL + ICCmax × VCC.
Note 1. The upper limit of operating temperature is 85°C or 105°C, depending on the product. For details, see section
1.3, Part Numbering. If the part number shows the operation temperature at 85°C, then the maximum value of Tj
is 105°C, otherwise, it is 125°C.
2.2.2 I/O VIH, VIL
Note 1. SCL0_A, SDA0_A, SDA0_B, SCL1_A, SDA1_A (total 5 pins)
Note 2. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins)
Note 3. P205, P206, P400, P401, P407 (total 5pins)
Table 2.3 DC characteristics
Conditions: Products with operating temperature (Ta) –40 to +105°C
Parameter Symbol Typ Max Unit Test conditions
Permissible junction temperature Tj - 125 °C High-speed mode
Middle-speed mode
Low-voltage mode
Low-speed mode
Subosc-speed mode
105*1
Table 2.4 I/O VIH, VIL (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter Symbol Min Typ Max Unit
Test
Conditions
Schmitt trigger
input voltage
IIC (except for SMBus)*1VIH VCC × 0.7 - 5.8 V -
VIL - - VCC × 0.3
∆VTVCC × 0.05 - -
RES, NMI
Other peripheral input pins
excluding IIC
VIH VCC × 0.8 - -
VIL - - VCC × 0.2
∆VTVCC × 0.1 - -
Input voltage
(except for
Schmitt trigger
input pin)
IIC (SMBus)*2VIH 2.2 - - VCC = 3.6 to
5.5 V
VIH 2.0 - - VCC =2.7 to
3.6 V
VIL --0.8 -
5V-tolerant ports*3VIH VCC × 0.8 - 5.8
VIL - - VCC × 0.2
P000 to P004
P010 to P015
VIH AVCC0 × 0.8 - -
VIL - - AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015
VIH VCC × 0.8 - -
VIL - - VCC × 0.2
R01DS0264EU0130 Rev.1.30 Page 23 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. P205, P206, P400, P401, P407 (total 5pins)
Table 2.5 I/O VIH, VIL (2)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Parameter Symbol Min Typ Max Unit
Test
Conditions
Schmitt trigger
input voltage
RES, NMI
Peripheral input pins
VIH VCC × 0.8 - - V -
VIL - - VCC × 0.2
∆VTVCC × 0.01 - -
Input voltage
(except for
Schmitt trigger
input pin)
5V-tolerant ports*1VIH VCC × 0.8 - 5.8
VIL - - VCC × 0.2
P000 to P004
P010 to P015
VIH AVCC0 × 0.8 - -
VIL - - AVCC0 × 0.2
EXTAL
Input ports pins except for
P000 to P004, P010 to P015
VIH VCC × 0.8 - -
VIL - - VCC × 0.2
R01DS0264EU0130 Rev.1.30 Page 24 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.3 I/O IOH, IOL
Caution: To protect the reliability of the MCU, the output current values should not exceed the values in this
table. The average output current indicates the average value of current measured during 100 μs.
Note 1. This is the value when low driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the register.
Note 3. Except for Ports P200, P214, P215, which are input ports.
Table 2.6 I/O IOH, IOL
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit
Permissible output current
(average value per pin)
Ports P000 to P004,
P010 to P015, P212, P213
-IOH --–4.0mA
IOL --4.0mA
Ports P408, P409 Low drive*1IOH --–4.0mA
IOL --4.0mA
Middle drive*2
VCC = 2.7 to 3.0 V
IOH --–8.0mA
IOL --8.0mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH --–20.0mA
IOL --20.0mA
Other output pins*3 Low drive*1IOH --–4.0mA
IOL --4.0mA
Middle drive*2IOH --–8.0mA
IOL --8.0mA
Permissible output current
(max value per pin)
Ports P000 to P004,
P010 to P015, P212, P213
-IOH --–4.0mA
IOL --4.0mA
Ports P408, P409 Low drive*1IOH --–4.0mA
IOL --4.0mA
Middle drive*2
VCC = 2.7 to 3.0 V
IOH --–8.0mA
IOL --8.0mA
Middle drive*2
VCC = 3.0 to 5.5 V
IOH --–20.0mA
IOL --20.0mA
Other output pins*3 Low drive*1IOH --–4.0mA
IOL --4.0mA
Middle drive*2IOH --–8.0mA
IOL --8.0mA
Permissible output current
(max value total pins)
Total of ports P000 to P004, P010 to P015 ΣIOH (max) --–30mA
ΣIOL (max) --30mA
Total of all output pin ΣIOH (max) --–60mA
ΣIOL (max) --60mA
R01DS0264EU0130 Rev.1.30 Page 25 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.4 I/O VOH, VOL, and Other Characteristics
Note 1. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins).
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Based on characterization data, not tested in production.
Note 4. Except for Ports P200, P214, and P215, which are input ports.
Note 5. Except for P212, P213.
Note 1. SCL0_A, SDA0_A, SCL0_B, SDA0_B, SCL1_A, SDA1_A, SCL1_B, SDA1_B (total 8 pins).
Note 2. This is the value when middle driving ability is selected with the Port Drive Capability bit in the PmnPFS register.
Note 3. Based on characterization data, not tested in production.
Note 4. Except for Ports P200, P214, P215, which are input ports.
Note 5. Except for P212, P213.
Table 2.7 I/O VOH, VOL (1)
Conditions: VCC = AVCC0 = 4.0 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
Output voltage IIC*1, *2VOL --0.4VI
OL = 3.0 mA
VOL --0.6 I
OL = 6.0 mA
Ports P408, P409*2, *3VOH VCC – 1.0 - - IOH = –20 mA
VOL --1.0 I
OL = 20 mA
Ports P000 to P004
P010 to P015
Low drive VOH AVCC0 –
0.8
-I
OH = –2.0 mA
VOL --0.8 I
OL = 2.0 mA
Middle drive VOH AVCC0 –
0.8
-I
OH = –4.0 mA
VOL --0.8 I
OL = 4.0 mA
Other output pins*4Low drive VOH VCC – 0.8 - - IOH = –2.0 mA
VOL --0.8 I
OL = 2.0 mA
Middle
drive*5
VOH VCC – 0.8 - - IOH = –4.0 mA
VOL --0.8 I
OL = 4.0 mA
Table 2.8 I/O VOH, VOL (2)
Conditions: VCC = AVCC0 = 2.7 to 4.0 V
Parameter Symbol Min Typ Max Unit Test conditions
Output voltage IIC*1, *2VOL --0.4VI
OL = 3.0 mA
VOL --0.6 I
OL = 6.0 mA
Ports P408, P409*2, *3VOH VCC – 1.0 - - IOH = –20 mA
VCC = 3.3 V
VOL --1.0 I
OL = 20 mA
VCC = 3.3 V
Ports P000 to P004
P010 to P015
Low drive VOH AVCC0 –
0.5
-- I
OH = –1.0 mA
VOL --0.5 I
OL = 1.0 mA
Middle drive VOH AVCC0 –
0.5
-- I
OH = –2.0 mA
VOL --0.5 I
OL = 2.0 mA
Other output pins*4Low drive VOH VCC – 0.5 - - IOH = –1.0 mA
VOL --0.5 I
OL = 1.0 mA
Middle
drive*5
VOH VCC – 0.5 - - IOH = –2.0 mA
VOL --0.5 I
OL = 2.0 mA
R01DS0264EU0130 Rev.1.30 Page 26 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Except for Ports P200, P214, P215, which are input ports.
Note 2. Except for P212, P213.
Table 2.9 I/O VOH, VOL (3)
Conditions: VCC = AVCC0 = 1.6 to 2.7 V
Parameter Symbol Min Typ Max Unit Test conditions
Output voltage Ports P000 to P004
P010 to P015
Low drive VOH AVCC0 –
0.3
-- I
OH = –0.5 mA
VOL --0.3 I
OL = 0.5 mA
Middle drive VOH AVCC0 –
0.3
-- I
OH = –1.0 mA
VOL --0.3 I
OL = 1.0 mA
Other output pins*1Low drive VOH VCC – 0.3 - - V IOH = –0.5 mA
VOL --0.3 I
OL = 0.5 mA
Middle drive*2VOH VCC – 0.3 - - IOH = –1.0 mA
VOL --0.3 I
OL = 1.0 mA
Table 2.10 I/O other characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
Input leakage current RES, Ports P200, P214, P215 | Iin | - - 1.0 μAV
in = 0 V
Vin = VCC
Three-state leakage
current (off state)
5V-tolerant ports | ITSI | - - 1.0 μAV
in = 0 V
Vin = 5.8 V
Other ports - - 1.0 Vin = 0 V
Vin = VCC
Input pull-up resistor All ports
(except for P200, P214, P215)
RU10 20 50 kΩVin = 0 V
Input capacitance USB_DP, USB_DM, P200 Cin - - 30 pF Vin = 0 V
f = 1 MHz
Ta = 25°C
Other input pins - - 15
R01DS0264EU0130 Rev.1.30 Page 27 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.5 I/O Pin Output Characteristics of Low Drive Capacity
Figure 2.2 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when low drive output is selected
(reference data)
Figure 2.3 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when low drive output is selected
(reference data)
0123456
-60
-50
-40
-30
-20
-10
0
10
20
30
40
50
60
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-3
-2
-1
0
1
2
3
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 28 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.4 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when low drive output is selected
(reference data)
Figure 2.5 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when low drive output is selected
(reference data)
0 0.5 1 1.5 2 2.5 3
-20
-15
-10
-5
0
5
10
15
20
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
00.511.522.533.5
-30
-20
-10
0
10
20
30
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 29 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.6 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when low drive output is selected
(reference data)
2.2.6 I/O Pin Output Characteristics of Middle Drive Capacity
Figure 2.7 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
0123456
-60
-40
-20
0
20
40
60
IOH/IOL vs VOH/VOL
VOH/VOL [V]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
IOH/IOL [mA]
0123456
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 1.6 V
VCC = 1.6 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
R01DS0264EU0130 Rev.1.30 Page 30 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.8 VOH/VOL and IOH/IOL temperature characteristics at VCC = 1.6 V when middle drive output is
selected (reference data)
Figure 2.9 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
-6
-4
-2
0
2
4
6
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
00.511.522.53
-40
-30
-20
-10
0
10
20
30
40
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 31 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.10 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
Figure 2.11 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
00.511.522.533.5
-60
-40
-20
0
20
40
60
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
0123456
-140
-120
-100
-80
-60
-40
-20
0
20
40
60
80
100
120
140
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 32 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.7 P408, P409 I/O Pin Output Characteristics of Middle Drive Capacity
Figure 2.12 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C when middle drive output is selected
(reference data)
Figure 2.13 VOH/VOL and IOH/IOL temperature characteristics at VCC = 2.7 V when middle drive output is
selected (reference data)
0123456
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
VCC = 5.5 V
VCC = 3.3 V
VCC = 2.7 V
VCC = 2.7 V
VCC = 3.3 V
VCC = 5.5 V
-140
-120
-100
-80
-60
-40
-20
20
40
60
80
100
120
140
200
180
160
0
-160
-180
-200
0 0.5 1 1.5 2 2.5 3
-60
-40
-20
0
20
40
60
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 33 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.14 VOH/VOL and IOH/IOL temperature characteristics at VCC = 3.3 V when middle drive output is
selected (reference data)
Figure 2.15 VOH/VOL and IOH/IOL temperature characteristics at VCC = 5.5 V when middle drive output is
selected (reference data)
0 0.5 1 1.5 2 2.5 3 3.5
-100
-80
-60
-40
-20
0
20
40
60
80
100
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
0123456
-220
-180
-140
-100
-60
-20
20
60
100
140
180
220
IOH/IOL vs VOH/VOL
VOH/VOL [V]
IOH/IOL [mA]
Ta = -40°C
Ta = 105°C
Ta = 25°C
Ta = 105°C
Ta = -40°C
Ta = 25°C
R01DS0264EU0130 Rev.1.30 Page 34 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.8 IIC I/O Pin Output Characteristics
Figure 2.16 VOH/VOL and IOH/IOL voltage characteristics at Ta = 25°C
0123456
0
10
20
30
40
50
60
70
80
90
100
110
120
IOL vs VOL
VOL [V]
IOL [mA]
VCC = 2.7V (Low drive)
VCC = 3.3V (Low drive)
VCC = 5.5V (Low drive)
VCC = 5.5 V (Middle drive)
VCC = 3.3V (Middle drive)
VCC = 2.7V (Middle drive)
R01DS0264EU0130 Rev.1.30 Page 35 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.9 Operating and Standby Current
Table 2.11 Operating and standby current (1) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Typ*9Max Unit
Test
Conditions
Supply
current*1
High-speed
mode*2
Normal mode All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 32 MHz ICC 3.6 - mA *7
ICLK = 16 MHz 2.4 -
ICLK = 8 MHz 1.7 -
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 32 MHz 5.6 -
ICLK = 16 MHz 3.5 -
ICLK = 8 MHz 2.4 -
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 32 MHz 9.5 - *8
ICLK = 16 MHz 5.4 -
ICLK = 8 MHz 3.3 -
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32 MHz - 21.0
Sleep mode All peripheral clock
disabled*5
ICLK = 32 MHz 1.5 - *7
ICLK = 16 MHz 1.1 -
ICLK = 8 MHz 0.9 -
All peripheral clock
enabled*5
ICLK = 32 MHz 7.2 - *8
ICLK = 16 MHz 4.0 -
ICLK = 8 MHz 2.4 -
Increase during BGO operation*62.5 - -
Middle-speed
mode*2
Normal mode All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 12 MHz ICC 1.7 - mA *7
ICLK = 8 MHz 1.5 -
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 12 MHz 2.7 -
ICLK = 8 MHz 1.9 -
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 12 MHz 3.9 - *8
ICLK = 8 MHz 3.0 -
All peripheral clock
enabled, code executing
from flash*5
ICLK = 12 MHz - 8.0
Sleep mode All peripheral clock
disabled*5
ICLK = 12 MHz 0.8 - *7
ICLK = 8 MHz 0.8 -
All peripheral clock
enabled*5
ICLK = 12 MHz 2.9 - *8
ICLK = 8 MHz 2.2 -
Increase during BGO operation*62.5 - -
Low-speed
mode*3
Normal mode All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 1 MHz ICC 0.2 - mA *7
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 1 MHz 0.3 -
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 1 MHz 0.4 - *8
All peripheral clock
enabled, code executing
from flash*5
ICLK = 1 MHz - 2.0
Sleep mode All peripheral clock
disabled*5
ICLK = 1 MHz 0.2 - *7
All peripheral clock
enabled*5
ICLK = 1 MHz 0.3 - *8
R01DS0264EU0130 Rev.1.30 Page 36 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOSs are in the off state.
Note 2. The clock source is HOCO.
Note 3. The clock source is MOCO.
Note 4. The clock source is the sub-clock oscillator.
Note 5. This does not include BGO operation.
Note 6. This is the increase for programming or erasure of the flash memory for data storage during program execution.
Note 7. PCLKB and PCLKD are set to divided by 64.
Note 8. PCLKB and PCLKD are the same frequency as that of ICLK.
Note 9. VCC = 3.3 V.
Supply
current*1
Low-voltage
mode*3
Normal mode All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 4 MHz ICC 1.4 - mA *7
All peripheral clock
disabled, CoreMark code
executing from flash*5
ICLK = 4 MHz 1.4 -
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 4 MHz 2.1 - *8
All peripheral clock
enabled, code executing
from flash*5
ICLK = 4 MHz - 4.0
Sleep mode All peripheral clock
disabled*5
ICLK = 4 MHz 0.9 - *7
All peripheral clock
enabled*5
ICLK = 4 MHz 1.6 - *8
Subosc-
speed
mode*4
Normal mode All peripheral clock
disabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz ICC 5.9 - μA*
7
All peripheral clock
enabled, while (1) code
executing from flash*5
ICLK = 32.768 kHz 13.0 - *8
All peripheral clock
enabled, code executing
from flash*5
ICLK = 32.768 kHz - 55.0
Sleep mode All peripheral clock
disabled*5
ICLK = 32.768 kHz 3.2 - *7
All peripheral clock
enabled*5
ICLK = 32.768 kHz 10.0 - *8
Table 2.11 Operating and standby current (1) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Typ*9Max Unit
Test
Conditions
R01DS0264EU0130 Rev.1.30 Page 37 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.17 Voltage dependency in high-speed operating mode (reference data)
Figure 2.18 Voltage dependency in middle-speed operating mode (reference data)
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
R01DS0264EU0130 Rev.1.30 Page 38 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.19 Voltage dependency in low-speed operating mode (reference data)
Figure 2.20 Voltage dependency in low-voltage operating mode (reference data)
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
R01DS0264EU0130 Rev.1.30 Page 39 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.21 Voltage dependency in subosc-speed operating mode (reference data)
Note 1. Supply current values do not include output charge/discharge current from all pins. The values apply when
internal pull-up MOS transistors are in the off state.
Note 2. The IWDT and LVD are not operating.
Note 3. VCC = 3.3 V.
Note 4. Includes the current of low-speed on-chip oscillator or sub-oscillation circuit.
Table 2.12 Operating and standby current (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Typ*3Max Unit Test conditions
Supply
current*1
Software Standby
mode*2
Ta = 25°C ICC 0.4 1.5 μA-
Ta = 55°C 0.6 5.5
Ta = 85°C 1.2 10.0
Ta = 105°C 2.6 40.0
Increment for RTC operation with
low-speed on-chip oscillator*4
0.4 - -
Increment for RTC operation with
sub-clock oscillator*4
0.5 - SOMCR.SODRV[1:0] are 11b
(Low power mode 3)
1.3 - SOMCR.SODRV[1:0] are 00b
(normal mode)
Note 1. All peripheral operations except any BGO operation are operating normally. This is the average
of the actual measurements of the sample cores during product evaluation.
Note 2. All peripheral operations except any BGO operation are operating at maximum. This is the
average of the actual measurements for the upper limit samples during product evaluation.
Note 3. MOCO and DAC are stopped.
R01DS0264EU0130 Rev.1.30 Page 40 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.22 Temperature dependency in Software Standby mode (reference data)
Figure 2.23 Temperature dependency of RTC operation (reference data)
Table 2.13 Operating and standby current (3) (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit
Test
conditions
Analog power
supply current
During A/D conversion (at high-speed conversion) IAVCC -- 3.0mA-
During A/D conversion (at low-power conversion) - - 1.0 mA -
During D/A conversion*1-0.4 0.8mA-
Waiting for A/D and D/A conversion (all units)*5-- 1.0μA-
Reference
power supply
current
During A/D conversion IREFH0 - - 150 μA-
Waiting for A/D conversion (all units) - - 60 nA -
Temperature sensor ITNS -75 - μA-
R01DS0264EU0130 Rev.1.30 Page 41 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. The reference power supply current is included in the power supply current value for D/A conversion.
Note 2. Current is consumed only by the USBFS.
Note 3. Includes the current supplied from the pull-up resistor of the USB_DP pin to the pull-down resistor of the host
device, in addition to the current consumed by the MCU in the suspended state.
Note 4. When VCC = VCC_USB = 3.3 V.
Note 5. When the MSTPCRD.MSTPD16 (ADC140 module-stop bit) is in the module-stop state.
Low-power
analog
comparator
(ACMPLP)
operating
current
Window mode ICMPLP -15 - μA-
Comparator high-speed mode - 10 - μA-
Comparator low-speed mode - 2 - μA-
USB operating
current
During USB communication under the following
settings and conditions:
Function controller is in Full-Speed mode and
- Bulk OUT transfer is (64 bytes) × 1
- Bulk IN transfer is (64 bytes) × 1
Host device is connected by a 1-meter USB cable
from the USB port.
IUSBF*2- 3.6 (VCC)
1.1 (VCC_USB)*4
-mA-
During suspended state under the following setting
and conditions:
Function controller is in Full-Speed mode (the
USB_DP pin is pulled up)
Software Standby mode
Host device is connected by a 1-meter USB cable
from the USB port.
ISUSP*3- 0.35 (VCC)
170 (VCC_USB)*4
-μA-
Table 2.13 Operating and standby current (3) (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Typ Max Unit
Test
conditions
R01DS0264EU0130 Rev.1.30 Page 42 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.2.10 VCC Rise and Fall Gradient and Ripple Frequency
Note 1. When OFS1.LVDAS = 0.
Note 2. At boot mode, the reset from voltage monitor 0 is disabled regardless of the value of OFS1.LVDAS bit.
Figure 2.24 Ripple waveform
Table 2.14 Rise and fall gradient characteristics
Conditions: VCC = AVCC0 = 0 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
Power-on VCC
rising gradient
Voltage monitor 0 reset disabled at startup SrVCC 0.02 -2ms/V-
Voltage monitor 0 reset enabled at startup*1, *2 0.02 --
SCI Boot mode*20.02 -2
Table 2.15 Rising and falling gradient and ripple frequency characteristics
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
The ripple voltage must meet the allowable ripple frequency fr(VCC) within the range between the VCC upper limit (5.5 V) and lower limit
(1.6 V).
When the VCC change exceeds VCC ±10%, the allowable voltage change rising and falling gradient dt/dVCC must be met.
Parameter Symbol Min Typ Max Unit Test conditions
Allowable ripple frequency fr (VCC) --10 kHz Figure 2.24
Vr (VCC) ≤ VCC × 0.2
--1MHz Figure 2.24
Vr (VCC) ≤ VCC × 0.08
--10 MHz Figure 2.24
Vr (VCC) ≤ VCC × 0.06
Allowable voltage change rising and
falling gradient
dt/dVCC 1.0 - - ms/V When VCC change exceeds VCC ±10%
Vr(VCC)
VCC
1/fr(VCC)
R01DS0264EU0130 Rev.1.30 Page 43 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3 AC Characteristics
2.3.1 Frequency
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Table 2.16 Operation frequency in high-speed operating mode
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter Symbol Min Typ Max*5Unit
Operation
frequency
System clock (ICLK)*1, *2, *42.7 to 5.5 V f 0.032768 - 32 MHz
2.4 to 2.7 V 0.032768 - 16
Peripheral module clock (PCLKB)*42.7 to 5.5 V - - 32
2.4 to 2.7 V - - 16
Peripheral module clock (PCLKD)*3, *42.7 to 5.5 V - - 64
2.4 to 2.7 V - - 16
Table 2.17 Operation frequency in middle-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter Symbol Min Typ Max*5Unit
Operation
frequency
System clock (ICLK)*1, *2, *42.7 to 5.5 V f 0.032768 - 12 MHz
2.4 to 2.7 V 0.032768 - 12
1.8 to 2.4 V 0.032768 - 8
Peripheral module clock (PCLKB)*42.7 to 5.5 V - - 12
2.4 to 2.7 V - - 12
1.8 to 2.4 V - - 8
Peripheral module clock (PCLKD)*3, *42.7 to 5.5 V - - 12
2.4 to 2.7 V - - 12
1.8 to 2.4 V - - 8
R01DS0264EU0130 Rev.1.30 Page 44 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 1 MHz when the A/D converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Note 1. The lower-limit frequency of ICLK is 1 MHz while programming or erasing the flash memory. When using ICLK for
programming or erasing the flash memory at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz.
A non-integer frequency such as 1.5 MHz cannot be set.
Note 2. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 3. The lower-limit frequency of PCLKD is 4 MHz at 2.4 V or above and 1 MHz at below 2.4 V when the 14-bit A/D
converter is in use.
Note 4. See section 8, Clock Generation Circuit in User’s Manual for the relationship of frequencies between ICLK,
PCLKB, and PCLKD.
Note 5. The maximum value of operation frequency does not include internal oscillator errors. For details on the range of
guaranteed operation, see Table 2.21, Clock timing.
Note 1. Programming and erasing the flash memory is not possible.
Note 2. The 14-bit A/D converter cannot be used.
Note 3. See section 8, Clock Generation Circuit in User’s Manual for the relationship between ICLK, PCLKB, and PCLKD
frequencies.
Table 2.18 Operation frequency in low-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter Symbol Min Typ Max*5Unit
Operation
frequency
System clock (ICLK)*1, *2, *41.8 to 5.5 V f 0.032768 - 1 MHz
Peripheral module clock (PCLKB)*41.8 to 5.5 V - - 1
Peripheral module clock (PCLKD)*3, *41.8 to 5.5 V - - 1
Table 2.19 Operation frequency in low-voltage mode
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Typ Max*5Unit
Operation
frequency
System clock (ICLK)*1, *2, *41.6 to 5.5 V f 0.032768 - 4 MHz
Peripheral module clock (PCLKB)*41.6 to 5.5 V - - 4
Peripheral module clock (PCLKD)*3, *41.6 to 5.5 V - - 4
Table 2.20 Operation frequency in Subosc-speed mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter Symbol Min Typ Max Unit
Operation
frequency
System clock (ICLK)*1, *31.8 to 5.5 V f 27.8528 32.768 37.6832 kHz
Peripheral module clock (PCLKB)*31.8 to 5.5 V - - 37.6832
Peripheral module clock (PCLKD)*2, *31.8 to 5.5 V - - 37.6832
R01DS0264EU0130 Rev.1.30 Page 45 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.2 Clock Timing
Table 2.21 Clock timing (1 of 2)
Parameter Symbol Min Typ Max Unit Test conditions
EXTAL external clock input cycle time tXcyc 50 - - ns Figure 2.25
EXTAL external clock input high pulse width tXH 20 - - ns
EXTAL external clock input low pulse width tXL 20 - - ns
EXTAL external clock rising time tXr --5ns
EXTAL external clock falling time tXf --5ns
EXTAL external clock input wait time*1tEXWT 0.3 - - μs-
EXTAL external clock input frequency fEXTAL --20MHz2.4 ≤ VCC ≤ 5.5
--8 1.8 ≤ VCC < 2.4
--1 1.6 ≤ VCC < 1.8
Main clock oscillator oscillation frequency fMAIN 1- 20MHz
2.4 ≤ VCC ≤ 5.5
1- 8 1.8 ≤ VCC < 2.4
1- 4 1.6 ≤ VCC < 1.8
LOCO clock oscillation frequency fLOCO 27.8528 32.768 37.6832 kHz -
LOCO clock oscillation stabilization time tLOCO - - 100 μsFigure 2.26
IWDT-dedicated clock oscillation frequency fILOCO 12.75 15 17.25 kHz -
MOCO clock oscillation frequency fMOCO 6.8 8 9.2 MHz -
MOCO clock oscillation stabilization time tMOCO --1μs-
HOCO clock oscillation frequency fHOCO24 23.64 24 24.36 MHz Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
22.68 24 25.32 Ta = –40 to 85°C
1.6 ≤ VCC < 1.8
23.76 24 24.24 Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
23.52 24 24.48 Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
fHOCO32 31.52 32 32.48 Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
30.24 32 33.76 Ta = –40 to 85°C
1.6 ≤ VCC < 1.8
31.68 32 32.32 Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
31.36 32 32.64 Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
fHOCO48*347.28 48 48.72 Ta = –40 to –20°C
1.8 ≤ VCC ≤ 5.5
47.52 48 48.48 Ta = –20 to 85°C
1.8 ≤ VCC ≤ 5.5
47.04 48 48.96 Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
fHOCO64*463.04 64 64.96 Ta = –40 to –20°C
2.4 ≤ VCC ≤ 5.5
63.36 64 64.64 Ta = –20 to 85°C
2.4 ≤ VCC ≤ 5.5
62.72 64 65.28 Ta = 85 to 105°C
2.4 ≤ VCC ≤ 5.5
HOCO clock oscillation
stabilization time*5, *6Except low-
voltage mode
tHOCO24
tHOCO32
- - 37.1 μsFigure 2.27
tHOCO48 - - 43.3
tHOCO64 - - 80.6
Low-voltage
mode
tHOCO24
tHOCO32
tHOCO48
tHOCO64
- - 100.9
Sub-clock oscillator oscillation frequency fSUB - 32.768 - kHz -
R01DS0264EU0130 Rev.1.30 Page 46 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Time until the clock can be used after the main clock oscillator stop bit (MOSCCR.MOSTP) is set to 0 (operating)
when the external clock is stable.
Note 2. After changing the setting of the SOSCCR.SOSTP bit to start sub-clock oscillator operation, only start using the
sub-clock oscillator after the sub-clock oscillation stabilization wait time elapsed. Use the oscillator wait time
value recommended by the oscillator manufacturer.
Note 3. The 48-MHz HOCO can be used within a VCC range of 1.8 V to 5.5 V.
Note 4. The 64-MHz HOCO can be used within a VCC range of 2.4 V to 5.5 V.
Note 5. This is a characteristic when the HOCOCR.HCSTP bit is cleared to 0 (oscillation) in the MOCO stop state.
When the HOCOCR.HCSTP bit is cleared to 0 (oscillation) during MOCO oscillation, this specification is
shortened by 1 μs.
Note 6. Check OSCSF.HOCOSF to confirm whether stabilization time has elapsed.
Figure 2.25 EXTAL external clock input timing
Figure 2.26 LOCO clock oscillation start timing
Figure 2.27 HOCO clock oscillation start timing (started by setting the HOCOCR.HCSTP bit)
Figure 2.28 Sub-clock oscillation start timing
Sub-clock oscillation stabilization time*2 t
SUBOSC -0.5-sFigure 2.28
Table 2.21 Clock timing (2 of 2)
Parameter Symbol Min Typ Max Unit Test conditions
tXH
tXcyc
EXTAL external clock input VCC × 0.5
tXL
tXr tXf
LOCO clock oscillator output
LOCOCR.LCSTP
tLOCO
Note 1. x = 24, 32, 48, 64
HOCO clock
HOCOCR.HCSTP
tHOCOx
*1
Sub-clock oscillator output
SOSCCR.SOSTP
tSUBOSC
R01DS0264EU0130 Rev.1.30 Page 47 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.3 Reset Timing
Note 1. When OFS1.LVDAS = 0.
Note 2. When OFS1.LVDAS = 1.
Figure 2.29 Reset input timing at power-on
Figure 2.30 Reset input timing (1)
Table 2.22 Reset timing
Parameter Symbol Min Typ Max Unit
Test
conditions
RES pulse width At power-on tRESWP 3- - msFigure 2.29
Not at power-on tRESW 30 - - μsFigure 2.30
Wait time after RES cancellation
(at power-on)
LVD0 enabled*1tRESWT -0.7-msFigure 2.29
LVD0 disabled*2-0.3-
Wait time after RES cancellation
(during powered-on state)
LVD0 enabled*1tRESWT2 -0.5-msFigure 2.30
LVD0 disabled*2-0.05-
Internal reset cancellation time (Watchdog
timer reset, SRAM parity error reset,
Software reset)
LVD0 enabled*1tRESWT3 -0.6-ms
LVD0 disabled*2-0.15-
VCC
RES
tRESWP
Internal reset
tRESWT
RES
Internal reset
tRESWT2
tRESW
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.4 Wakeup Time
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The HOCO clock wait control register (HOCOWTCR) is set to 05h.
Note 5. The HOCO clock wait control register (HOCOWTCR) is set to 06h.
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 4. The system clock is 12 MHz.
Table 2.23 Timing of recovery from low power modes (1)
Parameter Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
High-speed
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(20 MHz)*2
tSBYMC -2 3msFigure 2.31
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(20 MHz)*3
tSBYEX -1425 μs
System clock source is HOCO*4
(HOCO clock is 32 MHz)
tSBYHO -43 52 μs
System clock source is HOCO*4
(HOCO clock is 48 MHz)
tSBYHO -44 52 μs
System clock source is HOCO*5
(HOCO clock is 64 MHz)
tSBYHO -82 110 μs
System clock source is MOCO tSBYMO -16 25 μs
Table 2.24 Timing of recovery from low power modes (2)
Parameter Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
Middle-speed
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(12 MHz)*2
tSBYMC -23 msFigure 2.31
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(12 MHz)*3
tSBYEX -2.9 10 μs
System clock source is HOCO*4tSBYHO -38 50 μs
System clock source is MOCO tSBYMO -3.5 5.5 μs
R01DS0264EU0130 Rev.1.30 Page 49 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 1. The division ratio of ICK and PCKx is the minimum division ratio within the allowable frequency range. The
recovery time is determined by the system clock source.
Note 2. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 05h.
Note 3. The Main Clock Oscillator Wait Control Register (MOSCWTCR) is set to 00h.
Note 1. The sub-clock oscillator or LOCO itself continues oscillating in Software Standby mode during Subosc-speed
mode.
Table 2.25 Timing of recovery from low power modes (3)
Parameter Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
Low-speed
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(1 MHz)*2
tSBYMC -23msFigure 2.31
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(1 MHz)*3
tSBYEX -28 50 μs
System clock source is MOCO tSBYMO -25 35 μs
Table 2.26 Timing of recovery from low power modes (4)
Parameter Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
Low-voltage
mode
Crystal
resonator
connected to
main clock
oscillator
System clock source is
main clock oscillator
(4 MHz)*2
tSBYMC -23msFigure 2.31
External clock
input to main
clock oscillator
System clock source is
main clock oscillator
(4 MHz)*3
tSBYEX -108 130 μs
System clock source is HOCO tSBYHO -108 130 μs
Table 2.27 Timing of recovery from low power modes (5)
Parameter Symbol Min Typ Max Unit
Test
conditions
Recovery time
from Software
Standby mode*1
SubOSC-speed mode System clock source is sub-clock
oscillator (32.768 kHz)
tSBYSC -0.851msFigure 2.31
System clock source is LOCO
(32.768 kHz)
tSBYLO - 0.85 1.2 ms
R01DS0264EU0130 Rev.1.30 Page 50 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.31 Software Standby mode cancellation timing
Figure 2.32 Recovery timing from Software Standby mode to Snooze mode
Table 2.28 Timing of recovery from low power modes (6)
Parameter Symbol Min Typ Max Unit Test conditions
Recovery time from
Software Standby
mode to Snooze
mode
High-speed mode
System clock source is HOCO
tSNZ -3645μsFigure 2.32
Middle-speed mode
System clock source is MOCO
tSNZ -1.33.6μs
Low-speed mode
System clock source is MOCO
tSNZ -1013μs
Low-voltage mode
System clock source is HOCO
tSNZ -87110μs
Oscillator
ICLK
IRQ
Software Standby mode
tSBYSC, tSBYLO
Oscillator
ICLK
IRQ
Software Standby mode
tSBYMC, tSBYEX,
tSBYMO, tSBYHO
Note 1. When SNZCR.SNZDTCEN is set to 1, ICLK is supplied to DTC and SRAM.
tSNZ
IRQ
ICLK (to DTC, SRAM)*1 PCLK
ICLK (except DTC, SRAM)
Oscillator
Software Standby mode Snooze mode
R01DS0264EU0130 Rev.1.30 Page 51 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.5 NMI and IRQ Noise Filter
Note: 200 ns minimum in Software Standby mode.
Note 1. tPcyc indicates the PCLKB cycle.
Note 2. tNMICK indicates the cycle of the NMI digital filter sampling clock.
Note 3. tIRQCK indicates the cycle of the IRQi digital filter sampling clock (i = 0 to 7).
Figure 2.33 NMI interrupt input timing
Figure 2.34 IRQ interrupt input timing
Table 2.29 NMI and IRQ noise filter
Parameter Symbol Min Typ Max Unit Test conditions
NMI pulse width tNMIW 200 --ns NMI digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1-- tPcyc × 2 > 200 ns
200 -- NMI digital filter enabled tNMICK × 3 ≤ 200 ns
tNMICK × 3.5*2-- tNMICK × 3 > 200 ns
IRQ pulse width tIRQW 200 --ns IRQ digital filter disabled tPcyc × 2 ≤ 200 ns
tPcyc × 2*1-- tPcyc × 2 > 200 ns
200 -- IRQ digital filter enabled tIRQCK × 3 ≤ 200 ns
tIRQCK × 3.5*3-- tIRQCK × 3 > 200 ns
tNMIW
NMI
tIRQW
IRQ
R01DS0264EU0130 Rev.1.30 Page 52 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.6 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 Trigger Timing
Note: tPcyc: PCLKB cycle, tPDcyc: PCLKD cycle.
Note 1. Constraints on AGTIO input: tPcyc × 2 (tPcyc: PCLKB cycle) < tACYC.
Figure 2.35 I/O ports input timing
Figure 2.36 POEG input trigger timing
Table 2.30 I/O Ports, POEG, GPT, AGT, KINT, and ADC14 trigger timing
Parameter Symbol Min Max Unit
Test
conditions
I/O Ports Input data pulse width tPRW 1.5 -tPcyc Figure 2.35
POEG POEG input trigger pulse width tPOEW 3-tPcyc Figure 2.36
GPT Input capture pulse width Single edge tGTICW 1.5 -tPDcyc Figure 2.37
Dual edge 2.5 -
AGT AGTIO, AGTEE input cycle 2.7 V ≤ VCC ≤ 5.5 V tACYC*1250 - ns Figure 2.38
2.4 V ≤ VCC < 2.7 V 500 - ns
1.8 V ≤ VCC < 2.4 V 1000 - ns
1.6 V ≤ VCC < 1.8 V 2000 - ns
AGTIO, AGTEE input high level
width, low-level width
2.7 V ≤ VCC ≤ 5.5 V tACKWH,
tACKWL
100 - ns
2.4 V ≤ VCC < 2.7 V 200 - ns
1.8 V ≤ VCC < 2.4 V 400 - ns
1.6 V ≤ VCC < 1.8 V 800 - ns
AGTIO, AGTO, AGTOA, AGTOB
output cycle
2.7 V ≤ VCC ≤ 5.5 V tACYC2 62.5 -ns Figure 2.38
2.4 V ≤ VCC < 2.7 V 125 -ns
1.8 V ≤ VCC < 2.4 V 250 -ns
1.6 V ≤ VCC < 1.8 V 500 -ns
ADC14 14-bit A/D converter trigger input pulse width tTRGW 1.5 -tPcyc Figure 2.39
KINT KRn (n = 00 to 07) pulse width tKR 250 -ns Figure 2.40
Port
tPRW
POEG input trigger
tPOEW
R01DS0264EU0130 Rev.1.30 Page 53 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.37 GPT input capture timing
Figure 2.38 AGT I/O timing
Figure 2.39 ADC14 trigger input timing
Figure 2.40 Key interrupt input timing
2.3.7 CAC Timing
Note 1. tPBcyc: PCLKB cycle.
Table 2.31 CAC timing
Parameter Symbol Min Typ Max Unit
Test
conditions
CAC CACREF input pulse width tPBcyc ≤ tcac*2tCACREF 4.5 × tcac + 3 × tPBcyc --ns -
tPBcyc > tcac*25 × tcac + 6.5 × tPBcyc --ns
Input capture
tGTICW
tACYC2
AGTIO, AGTEE
(input)
tACYC
tACKWL tACKWH
AGTIO, AGTO,
AGTOA, AGTOB
(output)
ADTRG0
tTRGW
KR00 to KR07
tKR
R01DS0264EU0130 Rev.1.30 Page 54 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 2. tcac: CAC count clock source cycle.
2.3.8 SCI Timing
Note 1. tPcyc: PCLKB cycle.
Table 2.32 SCI timing (1)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Max Unit*1 Test conditions
SCI Input clock cycle Asynchronous tScyc 4-tPcyc Figure 2.41
Clock synchronous 6 -
Input clock pulse width tSCKW 0.4 0.6 tScyc
Input clock rise time tSCKr -20ns
Input clock fall time tSCKf -20ns
Output clock cycle Asynchronous tScyc 6-tPcyc
Clock synchronous 4 -
Output clock pulse width tSCKW 0.4 0.6 tScyc
Output clock rise time 1.8V or above tSCKr -20ns
1.6V or above - 30
Output clock fall time 1.8V or above tSCKf -20ns
1.6V or above - 30
Transmit data delay
(master)
Clock
synchro
nous
1.8V or above tTXD -40nsFigure 2.42
1.6V or above - 45
Transmit data delay
(slave)
Clock
synchro
nous
2.7V or above - 55 ns
2.4V or above - 60
1.8V or above - 100
1.6V or above - 125
Receive data setup
time (master)
Clock
synchro
nous
2.7V or above tRXS 45 -ns
2.4V or above 55 -
1.8V or above 90 -
1.6V or above 110 -
Receive data setup
time (slave)
Clock
synchro
nous
2.7V or above 40 -ns
1.6V or above 45 -
Receive data hold
time (master)
Clock synchronous tRXH 5-ns
Receive data hold
time (slave)
Clock synchronous tRXH 40 -ns
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. tPcyc: PCLKB cycle
Table 2.33 SCI timing (2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V
Parameter Symbol Min Max Unit*1Test conditions
Simple
SPI
SCK clock cycle output (master) tSPcyc 4 65536 tPcyc Figure 2.43
SCK clock cycle input (slave) 6 65536
SCK clock high pulse width tSPCKWH 0.4 0.6 tSPcyc
SCK clock low pulse width tSPCKWL 0.4 0.6 tSPcyc
SCK clock rise and fall time 1.8V or above tSPCKr,
tSPCKf
-20ns
1.6V or above -30
Data input setup
time
Master 2.7V or above tSU 45 - ns Figure 2.44 to
Figure 2.47
2.4V or above 55 -
1.8V or above 80 -
1.6V or above 110 -
Slave 2.7V or above 40 -
1.6V or above 45 -
Data input hold time Master tH33.3 - ns
Slave 40 -
SS input setup time tLEAD 1- t
SPcyc
SS input hold time tLAG 1- t
SPcyc
Data output delay Master 1.8V or above tOD -40ns
1.6V or above - 50
Slave 2.4V or above - 65
1.8V or above - 100
1.6V or above - 125
Data output hold
time
Master 2.7V or above tOH –10 - ns
2.4V or above –20 -
1.8V or above –30 -
1.6V or above –40 -
Slave –10 -
Data rise and fall
time
Master 1.8V or above tDr, tDf -20ns
1.6V or above - 30
Slave 1.8V or above - 20
1.6V or above - 30
Simple
SPI
Slave access time tSA -6 t
Pcyc Figure 2.47
Slave output release time tREL -6 t
Pcyc
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.43 SCI simple SPI mode clock timing
Figure 2.44 SCI simple SPI mode timing (master, CKPH = 1)
tSPCKWH
VOH VOH
VOL VOL
VOH VOH
tSPCKWL
tSPCKr tSPCKf
VOL
tSPcyc
tSPCKWH
VIH VIH
VIL VIL
VIH VIH
tSPCKWL
tSPCKr tSPCKf
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
(n = 0, 1, 9)
SCKn
master select
output
SCKn
slave select input
tDr, tDf
tSU tH
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SCKn
CKPOL = 0
output
SCKn
CKPOL = 1
output
MISOn
input
MOSIn
output
(n = 0, 1, 9)
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.45 SCI simple SPI mode timing (master, CKPH = 0)
Figure 2.46 SCI simple SPI mode timing (slave, CKPH = 1)
tSU tH
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SCKn
CKPOL = 1
output
SCKn
CKPOL = 0
output
MISOn
input
MOSIn
output
(n = 0, 1, 9)
tDr, tDf
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSA
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB IN MSB OUT
tOH tOD tREL
SSn
input
SCKn
CKPOL = 0
input
SCKn
CKPOL = 1
input
MISOn
output
MOSIn
input
(n = 0, 1, 9)
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S124 Datasheet 2. Electrical Characteristics
Figure 2.47 SCI simple SPI mode timing (slave, CKPH = 0)
Note: tIICcyc: Clock cycle selected by the SMR.CKS[1:0] bits.
Note 1. Cb indicates the total capacity of the bus line.
Note 2. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Table 2.34 SCI timing (3)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter Symbol Min Max Unit Test conditions
Simple IIC
(Standard mode)
SDA input rise time tSr -1000 ns Figure 2.48
SDA input fall time tSf -300 ns
SDA input spike pulse removal time tSP 04 × t
IICcyc ns
Data input setup time tSDAS 250 -ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb*1-400 pF
Simple IIC*2
(Fast mode)
SDA input rise time tSr -300 ns Figure 2.48
SDA input fall time tSf -300 ns
SDA input spike pulse removal time tSP 04 × t
IICcyc ns
Data input setup time tSDAS 100 -ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb*1- 400 pF
tDr, tDf
tSA tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data) DATA MSB OUT
MSB IN DATA LSB IN MSB IN
LSB OUT
tSU
tOD tREL
MSB OUT
SSn
input
SCKn
CKPOL = 1
input
SCKn
CKPOL = 0
input
MISOn
output
MOSIn
input
(n = 0, 1, 9)
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.48 SCI simple IIC mode timing
SDAn
SCLn
VIH
VIL
P*1S*1
tSf
tSr
tSDAH tSDAS
tSP
P*1
Test conditions:
VIH = VCC × 0.7, VIL = VCC × 0.3
VOL = 0.6 V, IOL = 6 mA
Sr*1
Note 1. S, P, and Sr indicate the following:
S: Start condition
P: Stop condition
Sr: Restart condition
(n = 0,1,9)
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.9 SPI Timing
Table 2.35 SPI timing (1 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit*1 Test conditions
SPI RSPCK clock cycle Master tSPcyc 2 4096 tPcyc Figure 2.49
C = 30PF
Slave 6 4096
RSPCK clock high
pulse width
Master tSPCKWH (tSPcyc –
tSPCKr
– tSPCKf) / 2
– 3
-ns
Slave 3 × tPcyc -
RSPCK clock low
pulse width
Master tSPCKWL (tSPcyc –
tSPCKr
– tSPCKf) / 2
– 3
-ns
Slave 3 × tPcyc -
RSPCK clock rise
and fall time
Output 2.7V or above tSPCKr,
tSPCKf
-10ns
2.4V or above - 15
1.8V or above - 20
1.6V or above - 30
Input - 1 µs
Data input setup
time
Master tSU 10 - ns Figure 2.50 to
Figure 2.55
C = 30PF
Slave 2.4V or above 10 -
1.8V or above 15 -
1.6V or above 20 -
Data input hold time Master
(RSPCK is PCLKB/2)
tHF 0-ns
Master
(RSPCK is not PCLKB/2)
tHtPcyc -
Slave tH20 -
SSL setup time Master tLEAD – 30 + N x
tSpcyc*2
-ns
Slave 6 x tPcyc -ns
SSL hold time Master tLAG – 30 + N x
tSpcyc*3
-ns
Slave 6 x tPcyc -ns
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. tPcyc: PCLKB cycle.
Note 2. N is set as an integer from 1 to 8 by the SPCKD register.
Note 3. N is set as an integer from 1 to 8 by the SSLND register.
SPI Data output delay Master 2.7V or above tOD -14 ns Figure 2.50 to
Figure 2.55
C = 30PF
2.4V or above -20
1.8V or above -25
1.6V or above -30
Slave 2.7V or above -50
2.4V or above -60
1.8V or above -85
1.6V or above -110
Data output hold
time
Master tOH 0- ns
Slave 0 -
Successive
transmission delay
Master tTD tSPcyc + 2 ×
tPcyc
8 × tSPcyc
+ 2 × tPcyc
ns
Slave 6 × tPcyc -
MOSI and MISO
rise and fall time
Output 2.7V or above tDr, tDf -10 ns
2.4V or above -15
1.8V or above -20
1.6V or above -30
Input -1µs
SSL rise and fall
time
Output 2.7V or above tSSLr, tSSLf -10 ns
2.4V or above - 15
1.8V or above -20
1.6V or above -30
Input - 1 µs
Slave access time 2.4V or above tSA -2 × tPcyc
+100
ns Figure 2.54 and
Figure 2.55
C = 30PF
1.8V or above -2 × tPcyc
+140
1.6V or above -2 × tPcyc
+180
Slave output release time 2.4V or above tREL -2 × tPcyc
+100
ns
1.8V or above -2 × tPcyc
+140
1.6V or above -2 × tPcyc
+180
Table 2.35 SPI timing (2 of 2)
Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Parameter Symbol Min Max Unit*1 Test conditions
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.49 SPI clock timing
Figure 2.50 SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to any value other than 1/2)
RSPCKn
master select
output
RSPCKn
slave select input
tSPCKWH
VOH VOH
VOL VOL
VOH VOH
tSPCKWL
tSPCKr tSPCKf
VOL
tSPcyc
tSPCKWH
VIH VIH
VIL VIL
VIH VIH
tSPCKWL
tSPCKr tSPCKf
VIL
tSPcyc
VOH = 0.7 × VCC, VOL = 0.3 × VCC, VIH = 0.7 × VCC, VIL = 0.3 × VCC
n = A or B
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLn0 to
SSLn3
output
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
MISOn
input
MOSIn
output
n = A or B
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.51 SPI timing (master, CPHA = 0) (bit rate: PCLKB division ratio is set to 1/2)
Figure 2.52 SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to any value other than 1/2)
SSLn0 to
SSLn3
output
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
MISOn
input
MOSIn
output
LSB IN
tDr, tDf
tSU tHF
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
MSB IN DATA
tHF
n = A or B
tSU tH
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLn0 to
SSLn3
output
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
MISOn
input
MOSIn
output
tDr, tDf
n = A or B
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.53 SPI timing (master, CPHA = 1) (bit rate: PCLKB division ratio is set to 1/2)
Figure 2.54 SPI timing (slave, CPHA = 0)
tSU tHF
tLEAD
tTD
tLAG
tSSLr, tSSLf
tOH tOD
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT IDLE MSB OUT
SSLn0 to
SSLn3
output
RSPCKn
CPOL = 0
output
RSPCKn
CPOL = 1
output
MISOn
input
MOSIn
output
tDr, tDf
tH
n = A or B
tDr, tDf
tSU tH
tLEAD
tTD
tLAG
tSA
MSB IN DATA LSB IN MSB IN
MSB OUT DATA LSB OUT MSB IN MSB OUT
tOH tOD tREL
SSLn0
input
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
MISOn
output
MOSIn
input
n = A or B
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.55 SPI timing (slave, CPHA = 1)
SSLn0
input
RSPCKn
CPOL = 0
input
RSPCKn
CPOL = 1
input
MISOn
output
MOSIn
input
tDr, tDf
tSA tOH
tLEAD
tTD
tLAG
tH
LSB OUT
(Last data) DATA MSB OUT
MSB IN DATA LSB IN MSB IN
LSB OUT
tSU
tOD tREL
MSB OUT
n = A or B
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.10 IIC Timing
Note: tIICcyc: IIC internal reference clock (IICφ) cycle, tPcyc: PCLKB cycle
Note 1. Values in parentheses apply when ICMR3.NF[1:0] is set to 11b while the digital filter is enabled with ICFER.NFE
set to 1.
Note 2. Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register.
Table 2.36 IIC timing
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter Symbol Min*1Max Unit
Test
conditions
IIC
(standard mode,
SMBus)
SCL input cycle time tSCL 6 (12) × tIICcyc + 1300 -ns Figure 2.56
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 -ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 - ns
SCL, SDA input rise time tSr - 1000 ns
SCL, SDA input fall time tSf - 300 ns
SCL, SDA input spike pulse removal
time
tSP 0 1 (4) × tIICcyc ns
SDA input bus free time
(When wakeup function is disabled)
tBUF 3 (6) × tIICcyc + 300 -ns
SDA input bus free time
(When wakeup function is enabled)
tBUF 3 (6) × tIICcyc + 4 × tPcyc
+ 300
-ns
START condition input hold time
(When wakeup function is disabled)
tSTAH tIICcyc + 300 -ns
START condition input hold time
(When wakeup function is enabled)
tSTAH 1 (5) × tIICcyc + tPcyc +
300
-ns
Repeated START condition input
setup time
tSTAS 1000 -ns
STOP condition input setup time tSTOS 1000 -ns
Data input setup time tSDAS tIICcyc + 50 -ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb- 400 pF
IIC*2
(Fast mode)
SCL input cycle time tSCL 6 (12) × tIICcyc + 600 -ns Figure 2.56
SCL input high pulse width tSCLH 3 (6) × tIICcyc + 300 -ns
SCL input low pulse width tSCLL 3 (6) × tIICcyc + 300 -ns
SCL, SDA input rise time tSr - 300 ns
SCL, SDA input fall time tSf - 300 ns
SCL, SDA input spike pulse removal
time
tSP 0 1 (4) × tIICcyc ns
SDA input bus free time
(When wakeup function is disabled)
tBUF 3 (6) × tIICcyc + 300 -ns
SDA input bus free time
(When wakeup function is enabled)
tBUF 3 (6) × tIICcyc + 4 × tPcyc
+ 300
-ns
START condition input hold time
(When wakeup function is disabled)
tSTAH tIICcyc + 300 -ns
START condition input hold time
(When wakeup function is enabled)
tSTAH 1(5) × tIICcyc + tPcyc +
300
-ns
Repeated START condition input
setup time
tSTAS 300 -ns
STOP condition input setup time tSTOS 300 -ns
Data input setup time tSDAS tIICcyc + 50 -ns
Data input hold time tSDAH 0-ns
SCL, SDA capacitive load Cb- 400 pF
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.56 I2C bus interface input/output timing
SDA0 and SDA1
SCL0 and SCL1
VIH
VIL
tSTAH
tSCLH
tSCLL
P*1S*1
tSf tSr
tSCL tSDAH
tSDAS
tSTAS tSP tSTOS
P*1
tBUF
Sr*1
Note 1. S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Restart condition
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.3.11 CLKOUT Timing
Note 1. When the EXTAL external clock input or an oscillator is used with division by 1 (the CKOCR.CKOSEL[2:0] bits are 011b and
the CKOCR.CKODIV[2:0] bits are 000b) to output from CLKOUT, the above should be satisfied with an input duty cycle of 45 to
55%.
Note 2. When the MOCO is selected as the clock output source (the CKOCR.CKOSEL[2:0] bits are 001b), set the clock output division
ratio selection to be divided by 2 (the CKOCR.CKODIV[2:0] bits are 001b).
Figure 2.57 CLKOUT output timing
Table 2.37 CLKOUT timing
Parameter Symbol Min Max Unit*1Test conditions
CLKOUT CLKOUT pin output cycle*1 VCC = 2.7 V or above tCcyc 62.5 - ns Figure 2.57
VCC = 1.8 V or above 125 -
VCC = 1.6 V or above 250 -
CLKOUT pin high pulse width*2 VCC = 2.7 V or above tCH 15 - ns
VCC = 1.8 V or above 30 -
VCC = 1.6 V or above 150 -
CLKOUT pin low pulse width*2 VCC = 2.7 V or above tCL 15 - ns
VCC = 1.8 V or above 30 -
VCC = 1.6 V or above 150 -
CLKOUT pin output rise time VCC = 2.7 V or above tCr -12ns
VCC = 1.8 V or above - 25
VCC = 1.6 V or above - 50
CLKOUT pin output fall time VCC = 2.7 V or above tCf -12ns
VCC = 1.8 V or above - 25
VCC = 1.6 V or above - 50
tCf
tCH
tCcyc
tCr
tCL
CLKOUT pin output
Test conditions: VOH = VCC × 0.7, VOL = VCC × 0.3, IOH = -1.0 mA, IOL = 1.0 mA, C = 30 pF
R01DS0264EU0130 Rev.1.30 Page 70 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.4 USB Characteristics
2.4.1 USBFS Timing
Figure 2.58 USB_DP and USB_DM output timing
Table 2.38 USB characteristics
Conditions: VCC = AVCC0 = VCC_USB = 3.0 to 3.6V, Ta = –20 to +85°C
Parameter Symbol Min Max Unit Test conditions
Input
characteristics
Input high level voltage VIH 2.0 - V -
Input low level voltage VIL -0.8V-
Differential input sensitivity VDI 0.2 - V | USB_DP – USB_DM |
Differential common mode
range
VCM 0.8 2.5 V -
Output
characteristics
Output high level voltage VOH 2.8 VCC_USB V IOH = –200 μA
Output low level voltage VOL 0.0 0.3 V IOL= 2 mA
Cross-over voltage VCRS 1.3 2.0 V Figure 2.58,
Figure 2.59,
Figure 2.60
Rise time FS tr420ns
LS 75 300
Fall time FS tf420ns
LS 75 300
Rise/fall time ratio FS tr/tf90 111.11 %
LS 80 125
Output resistance ZDRV 28 44 Ω(Adjusting the resistance
of external elements is not
necessary.)
VBUS
characteristics
VBUS input voltage VIH VCC × 0.8 - V -
VIL -VCC × 0.2V-
Pull-up,
pull-down
Pull-down resistor RPD 14.25 24.80 kΩ-
Pull-up resistor RPUI 0.9 1.575 kΩDuring idle state
RPUA 1.425 3.09 kΩDuring reception
Battery Charging
Specification
Ver 1.2
D + sink current IDP_SINK 25 175 μA-
D – sink current IDM_SINK 25 175 μA-
DCD source current IDP_SRC 713μA-
Data detection voltage VDAT_REF 0.25 0.4 V -
D + source voltage VDP_SRC 0.5 0.7 V Output current = 250 μA
D – source voltage VDM_SRC 0.5 0.7 V Output current = 250 μA
USB_DP,
USB_DM
tf
tr
90%
10%10%
90%
VCRS
R01DS0264EU0130 Rev.1.30 Page 71 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.59 Test circuit for Full-Speed (FS) connection
Figure 2.60 Test circuit for Low-Speed (LS) connection
2.4.2 USB External Supply
Table 2.39 USB regulator
Parameter Min Typ Max Unit Test conditions
VCC_USB supply current VCC_USB_LDO ≥ 3.8V --50 mA -
VCC_USB_LDO ≥ 4.5V --100 mA -
VCC_USB supply voltage 3.0 - 3.6 V -
Observation
point
50 pF
USB_DP
USB_DM
50 pF
Observation
point
200 pF to
600 pF
USB_DP
USB_DM
200 pF to
600 pF
1.5 K
3.6 V
Observation
point
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.5 ADC14 Characteristics
Figure 2.61 AVCC0 to VREFH0 voltage range
Table 2.40 A/D conversion characteristics (1) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 64 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 2.5*3kΩHigh-precision channel
--6.7*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
0.70 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.13 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±0.5 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Full-scale error - ±0.75 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel
±8.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
VREFH0
5.0
4.0
3.0
2.0
1.0
1.0 2.0 3.0 4.0 5.0
A/D Conversion
Characteristics (2)
ADCSR.ADHSC = 0
5.5
2.7
2.4
2.4 2.7 5.5 AVCC0
VREFH0
5.0
4.0
3.0
2.0
1.0
1.0 2.0 3.0 4.0 5.0
ADCSR.ADHSC = 1
5.5
2.7
2.4
2.4 2.7 5.5 AVCC0
1.8
1.8
A/D Conversion
Characteristics (1)
A/D Conversion
Characteristics (3)
A/D Conversion
Characteristics (4)
A/D Conversion
Characteristics (5)
A/D Conversion
Characteristics (6)
A/D Conversion
Characteristics (7)
1.6
1.6
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Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Conversion time*1
(Operation at
PCLKD = 64 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
0.80 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.22 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±2.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Full-scale error - ±3.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±5.0 ±20 LSB High-precision channel
±32.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.41 A/D conversion characteristics (2) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 48 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 2.5*3kΩHigh-precision channel
--6.7*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
0.94 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.50 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±0.5 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Full-scale error - ±0.75 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel
±8.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
Table 2.40 A/D conversion characteristics (1) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 4.5 to 5.5 V, VREFH0 = 4.5 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 74 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 48 MHz)
Permissible signal
source impedance
Max. = 0.3 kΩ
1.06 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
1.63 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±2.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Full-scale error - ±3.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±5.0 ±20 LSB High-precision channel
±32.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.42 A/D conversion characteristics (3) in high-speed A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 32 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 2.5*3kΩHigh-precision channel
--6.7*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
1.41 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.25 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±0.5 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Full-scale error - ±0.75 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel
±8.0 LSB Other than above
Table 2.41 A/D conversion characteristics (2) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 75 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 32 MHz)
Permissible signal
source impedance
Max. = 1.3 kΩ
1.59 - - μs High-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 0Dh
2.44 - - μs Normal-precision channel
ADCSR.ADHSC = 0
ADSSTRn.SST[7:0] = 28h
Offset error - ±2.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Full-scale error - ±3.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±5.0 ±20 LSB High-precision channel
±32.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.43 A/D conversion characteristics (4) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 24 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 2.5*3kΩHigh-precision channel
--6.7*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
2.25 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.38 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±0.5 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Full-scale error - ±0.75 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Table 2.42 A/D conversion characteristics (3) in high-speed A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 76 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel
±8.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 24 MHz)
Permissible signal
source impedance
Max. = 1.1 kΩ
2.50 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
3.63 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±2.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Full-scale error - ±3.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±5.0 ±20 LSB High-precision channel
±32.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.44 A/D conversion characteristics (5) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 16 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 2.5*3kΩHigh-precision channel
--6.7*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
3.38 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.06 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±0.5 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Table 2.43 A/D conversion characteristics (4) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VREFH0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 77 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Full-scale error - ±0.75 ±4.5 LSB High-precision channel
±6.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±1.25 ±5.0 LSB High-precision channel
±8.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 16 MHz)
Permissible signal
source impedance
Max. = 2.2 kΩ
3.75 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
5.44 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±2.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Full-scale error - ±3.0 ±18 LSB High-precision channel
±24.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±5.0 ±20 LSB High-precision channel
±32.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.45 A/D conversion characteristics (6) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 8 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 3.8*3kΩHigh-precision channel
--8.2*
3kΩNormal-precision channel
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Table 2.44 A/D conversion characteristics (5) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V, VREFH0 = 2.4 to 5.5 V, VSS = AVSS0 = VREFL0 = 0V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 78 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Conversion time*1
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
6.75 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.13 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±1.0 ±7.5 LSB High-precision channel
±10.0 LSB Other than above
Full-scale error - ±1.5 ±7.5 LSB High-precision channel
±10.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel
±12.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 8 MHz)
Permissible signal
source impedance
Max. = 5 kΩ
7.50 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
10.88 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±4.0 ±30.0 LSB High-precision channel
±40.0 LSB Other than above
Full-scale error - ±6.0 ±30.0 LSB High-precision channel
±40.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel
±48.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.46 A/D conversion characteristics (7) in low-power A/D conversion mode (1 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
Frequency 1 - 4 MHz -
Analog input capacitance*2Cs - - 8*3pF High-precision channel
--9*
3pF Normal-precision channel
Analog input resistance Rs - - 13.1*3kΩHigh-precision channel
- - 14.3*3kΩNormal-precision channel
Table 2.45 A/D conversion characteristics (6) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.8 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.8 to 5.5 V, VSS = AVSS0 = VREFL0 = 0 V
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 79 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note: The characteristics apply when no pin functions other than 14-bit A/D converter input are used. Absolute
accuracy does not include quantization errors. Offset error, full-scale error, DNL differential nonlinearity error,
and INL integral nonlinearity error do not include quantization errors.
Note 1. The conversion time is the sum of the sampling time and the comparison time. The number of sampling states is
indicated for the test conditions.
Note 2. Except for I/O input capacitance (Cin), see section 2.2.4, I/O VOH, VOL, and Other Characteristics.
Note 3. Reference data.
Analog input voltage range Ain 0 - VREFH0 V -
12-bit mode
Resolution - - 12 Bit -
Conversion time*1
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
13.5 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
20.25 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±1.0 ±7.5 LSB High-precision channel
±10.0 LSB Other than above
Full-scale error - ±1.5 ±7.5 LSB High-precision channel
±10.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±3.0 ±8.0 LSB High-precision channel
±12.0 LSB Other than above
DNL differential nonlinearity error - ±1.0 - LSB -
INL integral nonlinearity error - ±1.0 ±3.0 LSB -
14-bit mode
Resolution - - 14 Bit -
Conversion time*1
(Operation at
PCLKD = 4 MHz)
Permissible signal
source impedance
Max. = 9.9 kΩ
15.0 - - μs High-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 0Dh
21.75 - - μs Normal-precision channel
ADCSR.ADHSC = 1
ADSSTRn.SST[7:0] = 28h
Offset error - ±4.0 ±30.0 LSB High-precision channel
±40.0 LSB Other than above
Full-scale error - ±6.0 ±30.0 LSB High-precision channel
±40.0 LSB Other than above
Quantization error - ±0.5 - LSB -
Absolute accuracy - ±12.0 ±32.0 LSB High-precision channel
±48.0 LSB Other than above
DNL differential nonlinearity error - ±4.0 - LSB -
INL integral nonlinearity error - ±4.0 ±12.0 LSB -
Table 2.46 A/D conversion characteristics (7) in low-power A/D conversion mode (2 of 2)
Conditions: VCC = AVCC0 = 1.6 to 5.5 V (AVCC0 = VCC when VCC < 2.0 V), VREFH0 = 1.6 to 5.5 V, VSS = AVSS0 = VREFL0 = 0
Reference voltage range applied to the VREFH0 and VREFL0.
Parameter Min Typ Max Unit Test Conditions
R01DS0264EU0130 Rev.1.30 Page 80 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.62 Equivalent circuit for analog input
Note 1. The internal reference voltage cannot be selected for input channels when AVCC0 < 2.0 V.
Note 2. The 14-bit A/D internal reference voltage indicates the voltage when the internal reference voltage is input to the
14-bit A/D converter.
Table 2.47 14-bit A/D converter channel classification
Classification Channel Conditions Remarks
High-precision channel AN000 to AN010 AVCC0 = 1.6 to 5.5 V Pins AN000 to AN010 cannot be used
as general I/O, TS transmission,
when the A/D converter is in use.
Normal-precision channel AN016 to AN022
Internal reference voltage
input channel
Internal reference voltage AVCC0 = 2.0 to 5.5 V -
Temperature sensor input
channel
Temperature sensor output AVCC0 = 2.0 to 5.5 V -
Table 2.48 A/D internal reference voltage characteristics
Conditions: VCC = AVCC0 = VREFH0 = 2.0 to 5.5 V*1
Parameter Min Typ Max Unit Test conditions
Internal reference voltage input
channel*2
1.36 1.43 1.50 V -
Frequency 1 - 2 MHz -
Sampling time 5.0 - - μs-
R01DS0264EU0130 Rev.1.30 Page 81 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.63 Illustration of 14-bit A/D converter characteristic terms
Absolute accuracy
Absolute accuracy is the difference between output code based on the theoretical A/D conversion characteristics, and the
actual A/D conversion result. When measuring absolute accuracy, the voltage at the midpoint of the width of the analog
input voltage (1-LSB width), which can meet the expectat ion of outputt ing an equal code based on the theoretical A/D
conversion characteristics, is used as the analog input voltage. For example, if 12-bit resolution is used and the reference
voltage VREFH0 = 3.072 V, then 1-LSB width becomes 0.75 mV, and 0 mV, 0.75 mV, and 1.5 mV are used as the analog
input voltages. If analog input voltage is 6 mV, an absolute accuracy of ±5 LSB means that the actual A/D conversion
result is in the range of 003h to 00Dh, though an output code of 008h can be expected from the theoretical A/ D
conversion characteristics.
Integral nonlinearity error (INL)
Integral nonl inearity error is the maximum deviation between the ideal line when the measured offset and full-scale
errors are zeroed, and the actual output code.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB width based on the ideal A/D conversion characteristics
and the width of the actual output code.
Offset error
Offs et error is the dif ference between the transition point of the ideal first output code and the actual first output code.
Full-scale error
Full-scale error is the difference between the transition point of the ideal last output code and the actual last output code.
Integral nonlinearity
error (INL)
Actual A/D conversion
characteristic
Ideal A/D conversion
characteristic
Analog input voltage
Offset error
Absolute accuracy
Differential non-linearity error (DNL)
Full-scale error
3FFFh
0000h
0
Ideal line of actual A/D
conversion characteristic
1-LSB width for ideal A/D
conversion characteristic
Differential non-linearity error
(DNL)
1-LSB width for ideal A/D
conversion characteristic
VREFH0
(full scale)
A/D converter
output code
R01DS0264EU0130 Rev.1.30 Page 82 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.6 DAC12 Characteristics
Figure 2.64 Illustration of D/A converter characteristic terms
Integral nonlinearity error (INL)
Integral nonl inearity error is the maximum deviation between the ideal output voltage based on the ideal conversion
characteristic when the measured offset and full-scale errors are zeroed, and the actual output voltage.
Differential nonlinearity error (DNL)
Differential nonlinearity error is the difference between 1-LSB voltage width based on the ideal D/A conversion
characteristics and the width of the actual output voltage.
Table 2.49 D/A conversion characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Reference voltage = AVCC0 or AVSS0 selected
Parameter Min Typ Max Unit Test conditions
Resolution - - 12 bit -
Resistive load 30 - - kΩ-
Capacitive load - - 50 pF -
Output voltage range 0.35 - AVCC0 – 0.47 V -
DNL differential nonlinearity error -±0.5 ±2.0 LSB -
INL integral nonlinearity error -±2.0 ±8.0 LSB -
Offset error --±30mV-
Full-scale error --±30mV-
Output impedance -5- Ω-
Conversion time --30 μs-
000h D/A converter input code
FFFh
Output analog voltage
Upper output limit
Lower output limit
Offset error
Ideal output voltage
1-LSB width for ideal D/A conversion
characteristic
Differential nonlinearity error
(DNL)
Actual D/A conversion characteristic
*1
Integral nonlinearity error (INL)
Full-scale error Gain error
Offset error
Ideal output voltage
Note 1. Ideal D/A conversion output voltage that is adjusted so that offset and full scale errors are zeroed.
R01DS0264EU0130 Rev.1.30 Page 83 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Offset error
Offs et error is the dif ference between the high est actua l out put voltage that falls below the lower output limit and the
ideal output voltage based on the input code.
Full-scale error
Full-scale error is the difference between the lowest actual output voltage that exceeds the upper output limit and the
ideal output voltage based on the input code.
2.7 TSN Characteristics
2.8 OSC Stop Detect Characteristics
Figure 2.65 Oscillation stop detection timing
Table 2.50 TSN characteristics
Conditions: VCC = AVCC0 = 2.0 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
Relative accuracy - -±1.5 -°C 2.4 V or above
-±2.0 -°C Below 2.4 V
Temperature slope --–3.65 -mV/°C -
Output voltage (at 25°C) --1.05 -V VCC = 3.3 V
Temperature sensor start time tSTART --5μs-
Sampling time - 5 --μs
Table 2.51 Oscillation stop detection circuit characteristics
Parameter Symbol Min Typ Max Unit Test conditions
Detection time tdr --1msFigure 2.65
tdr
Main clock
OSTDSR.OSTDF
MOCO clock
ICLK
R01DS0264EU0130 Rev.1.30 Page 84 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.9 POR and LVD Characteristics
Note 1. These characteristics apply when noise is not superimposed on the power supply. When a setting causes this
voltage detection level to overlap with that of the voltage detection circuit, it cannot be specified whether LVD1 or
LVD2 is used for voltage detection.
Note 2. # in the symbol Vdet0_# denotes the value of the OFS1.VDSEL1[2:0] bits.
Note 3. # in the symbol Vdet1_# denotes the value of the LVDLVLR.LVD1LVL[4:0] bits.
Note 4. # in the symbol Vdet2_# denotes the value of the LVDLVLR.LVD2LVL[2:0] bits.
Table 2.52 Power-on reset circuit and voltage detection circuit characteristics (1)
Parameter Symbol Min Typ Max Unit Test Conditions
Voltage detection
level*1
Power-on reset (POR) VPOR 1.27 1.42 1.57 V Figure 2.66,
Figure 2.67
Voltage detection circuit (LVD0)*2Vdet0_0 3.68 3.85 4.00 V Figure 2.68
At falling edge
VCC
Vdet0_1 2.68 2.85 2.96
Vdet0_2 2.38 2.53 2.64
Vdet0_3 1.78 1.90 2.02
Vdet0_4 1.60 1.69 1.82
Voltage detection circuit (LVD1)*3Vdet1_0 4.13 4.29 4.45 V Figure 2.69
At falling edge
VCC
Vdet1_1 3.98 4.16 4.30
Vdet1_2 3.86 4.03 4.18
Vdet1_3 3.68 3.86 4.00
Vdet1_4 2.98 3.10 3.22
Vdet1_5 2.89 3.00 3.11
Vdet1_6 2.79 2.90 3.01
Vdet1_7 2.68 2.79 2.90
Vdet1_8 2.58 2.68 2.78
Vdet1_9 2.48 2.58 2.68
Vdet1_A 2.38 2.48 2.58
Vdet1_B 2.10 2.20 2.30
Vdet1_C 1.84 1.96 2.05
Vdet1_D 1.74 1.86 1.95
Vdet1_E 1.63 1.75 1.84
Vdet1_F 1.60 1.65 1.73
Voltage detection circuit (LVD2)*4Vdet2_0 4.11 4.31 4.48 V Figure 2.70
At falling edge
VCC
Vdet2_1 3.97 4.17 4.34
Vdet2_2 3.83 4.03 4.20
Vdet2_3 3.64 3.84 4.01
Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (2) (1 of 2)
Parameter Symbol Min Typ Max Unit Test Conditions
Wait time after power-on
Reset cancellation
LVD0:enable tPOR -1.7-ms -
LVD0:disable tPOR -1.3-ms -
Wait time after voltage
monitor 0,1,2 reset
cancellation
LVD0:enable*1tLVD0,1,2 -0.6-ms -
LVD0:disable*2tLVD1,2 -0.2-ms -
Response delay*3tdet --350μsFigure 2.66, Figure 2.67
Minimum VCC down time tVOFF 450 - - μsFigure 2.66,
VCC = 1.0 V or above
R01DS0264EU0130 Rev.1.30 Page 85 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. When OFS1.LVDAS = 0
Note 2. When OFS1.LVDAS = 1
Note 3. The minimum VCC down time indicates the time when VCC is below the minimum value of voltage detection
levels VPOR, Vdet0, Vdet1, and Vdet2 for the POR/LVD.
Figure 2.66 Voltage detection reset timing
Figure 2.67 Power-on reset timing
Power-on reset enable time tW (POR) 1--ms Figure 2.67,
VCC = below 1.0 V
LVD operation stabilization time (after LVD is
enabled)
Td (E-A) --300μsFigure 2.69,
Figure 2.70
Hysteresis width (POR) VPORH -110-mV -
Hysteresis width (LVD0, LVD1, and LVD2) VLVH - 60 - mV LVD0 selected
- 100 - Vdet1_0 to Vdet1_2 selected.
-60- V
det1_3 to Vdet1_9 selected.
-50- V
det1_A to Vdet1_B
selected.
-40- V
det1_C to Vdet1_F
selected.
- 60 - LVD2 selected
Table 2.53 Power-on reset circuit and voltage detection circuit characteristics (2) (2 of 2)
Parameter Symbol Min Typ Max Unit Test Conditions
Internal reset signal
(active-low)
VCC
tVOFF
tPOR
tdet
VPOR
tdet
1.0 V
Note: tW(POR) is the time required for a power-on reset to be enabled while the external power VCC is
being held below the valid voltage (1.0 V).
When VCC turns on, maintain tW(POR) for 1.0 ms or more.
Internal reset signal
(active-low)
VCC
tPOR
VPOR
1.0 V
tw(POR)
*1
tdet
R01DS0264EU0130 Rev.1.30 Page 86 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.68 Voltage detection circuit timing (Vdet0)
Figure 2.69 Voltage detection circuit timing (Vdet1)
tVOFF
tLVD0
tdet
Vdet0
VCC
Internal reset signal
(active-low)
tdet
VLVH
tVOFF
Vdet1
VCC
tdet
tdet
tLVD1
Td(E-A)
LVCMPCR.LVD1E
LVD1
Comparator output
LVD1CR0.CMPE
LVD1SR.MON
Internal reset signal
(active-low)
When LVD1CR0.RN = 0
When LVD1CR0.RN = 1
VLVH
tLVD1
R01DS0264EU0130 Rev.1.30 Page 87 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Figure 2.70 Voltage detection circuit timing (Vdet2)
2.10 CTSU Characteristics
Table 2.54 CTSU characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
External capacitance connected to TSCAP pin Ctscap 91011nF-
TS pin capacitive load Cbase --50pF-
Permissible output high current ΣIoH - - -24 mA When the mutual
capacitance method
is applied
tVOFF
Vdet2
VCC
tdet
tdet
tLVD2
Td(E-A)
LVCMPCR.LVD2E
LVD2
Comparator output
LVD2CR0.CMPE
LVD2SR.MON
Internal reset signal
(active-low)
When LVD2CR0.RN = 0
When LVD2CR0.RN = 1
VLVH
tLVD2
R01DS0264EU0130 Rev.1.30 Page 88 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.11 Comparator Characteristics
Table 2.55 ACMPLP characteristics
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, VSS = AVSS0 = 0 V
Parameter Symbol Min Typ Max Unit Test conditions
Reference voltage range VREF 0- VCC
–1.4
V-
Input voltage range VI0-VCC V -
Internal reference voltage - 1.36 1.44 1.50 V -
Output delay High-speed mode Td-- 1.2 μs VCC = 3.0
Slew rate of input
signal > 50 mV/μs
Low-speed mode -- 5μs
Window mode - -2μs
Offset voltage High-speed mode - - - 50 mV -
Low-speed mode - - - 40 mV -
Window mode - - - 60 mV -
Internal reference voltage for window mode VRFH -0.76 ×
VCC
-V-
VRFL -0.24 ×
VCC
-V-
Operation stabilization wait time Tcmp 100 - - μs-
R01DS0264EU0130 Rev.1.30 Page 89 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.12 Flash Memory Characteristics
2.12.1 Code Flash Memory Characteristics
Note 1. The reprogram/erase cycle is the number of erasures for each block. When the reprogram/erase cycle is n times
(n = 1,000), erasing can be performed n times for each block. For instance, when 4-byte programming is
performed 256 times for different addresses in 1-KB blocks, and then the entire block is erased, the reprogram/
erase cycle is counted as 1. However, programming the same address for several times as one erasure is not
enabled. (overwriting is prohibited.)
Note 2. Characteristic when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. This result is obtained from reliability testing.
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Table 2.56 Code flash characteristics (1)
Parameter Symbol Min Typ Max Unit Conditions
Reprogramming/erasure cycle*1NPEC 1000 --Times -
Data hold time After 1000 times NPEC tDRP 20*2, *3--Year Ta = +85°C
Table 2.57 Code flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter Symbol
ICLK = 1 MHz ICLK = 32 MHz
UnitMin Typ Max Min Typ Max
Programming time 4-byte tP4 -116 998 -54 506 μs
Erasure time 1-KB tE1K -9.03 287 -5.67 222 ms
Blank check time 4-byte tBC4 --56.8 --16.6 μs
1-KB tBC1K --1899 --140 μs
Erase suspended time tSED --22.5 --10.7 μs
Startup area switching setting time tSAS -21.9 585 -12.1 447 ms
Access window time tAWS -21.9 585 -12.1 447 ms
OCD/serial programmer ID setting time tOSIS -21.9 585 -12.1 447 ms
Flash memory mode transition wait
time 1
tDIS 2--2--μs
Flash memory mode transition wait
time 2
tMS 5--5--μs
R01DS0264EU0130 Rev.1.30 Page 90 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
2.12.2 Data Flash Memory Characteristics
Note 1. The reprogram/erase cycle is the number of erasure for each block. When the reprogram/erase cycle is n times
(n = 100,000), erasing can be performed n times for each block. For instance, when 1-byte programming is
performed 1,000 times for different addresses in 1-byte blocks, and then the entire block is erased, the
reprogram/erase cycle is counted as 1. However, programming the same address for several times as one
erasure is not enabled. (overwriting is prohibited.)
Note 2. Characteristics when using the flash memory programmer and the self-programming library provided by Renesas
Electronics.
Note 3. These results are obtained from reliability testing.
Table 2.58 Code flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
Parameter Symbol
ICLK = 1 MHz ICLK = 8 MHz
UnitMin Typ Max Min Typ Max
Programming time 4-byte tP4 -157 1411 -101 966 μs
Erasure time 1-KB tE1K -9.10 289 -6.10 228 ms
Blank check time 2-byte tBC4 --87.7 --52.5 μs
1-KB tBC1K --1930 --414 μs
Erase suspended time tSED --32.7 --21.6 μs
Startup area switching setting time tSAS -22.8 592 -14.2 465 ms
Access window time tAWS -22.8 592 -14.2 465 ms
OCD/serial programmer ID setting time tOSIS -22.8 592 -14.2 465 ms
Flash memory mode transition wait
time 1
tDIS 2--2--μs
Flash memory mode transition wait
time 2
tMS 720 --720 --ns
Table 2.59 Data flash characteristics (1)
Parameter Symbol Min Typ Max Unit Conditions
Reprogramming/erasure cycle*1NDPEC 100000 1000000 -Times -
Data hold time After 10000 times of NDPEC tDDRP 20*2, *3--Year Ta = +85°C
After 100000 times of NDPEC 5*2, *3--Year
After 1000000 times of NDPEC -1*
2, *3-Year Ta = +25°C
R01DS0264EU0130 Rev.1.30 Page 91 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Note 1. Does not include the time until each operation of the flash memory is started after instructions are executed by
the software.
Note 2. The lower-limit frequency of ICLK is 1 MHz during programming or erasing the flash memory. When using ICLK
at below 4 MHz, the frequency can be set to 1 MHz, 2 MHz, or 3 MHz. A non-integer frequency such as 1.5 MHz
cannot be set.
Note 3. The frequency accuracy of ICLK must be ±3.5% while programming or erasing the flash memory. Confirm the
frequency accuracy of the clock source.
Table 2.60 Data flash characteristics (2)
High-speed operating mode
Conditions: VCC = AVCC0 = 2.7 to 5.5 V
Parameter Symbol
ICLK = 4 MHz ICLK = 32 MHz
UnitMin Typ Max Min Typ Max
Programming time 1-byte tDP1 -52.4 463 -42.1 387 μs
Erasure time 1-KB tDE1K -8.98 286 -6.42 237 ms
Blank check time 1-byte tDBC1 --24.3 --16.6 μs
1-KB tDBC1K --1872 --512 μs
Suspended time during erasing tDSED --13.0 --10.7 μs
Data flash STOP recovery time tDSTOP 5--5
--μs
Table 2.61 Data flash characteristics (3)
Middle-speed operating mode
Conditions: VCC = AVCC0 = 1.8 to 5.5 V, Ta = -40 to +85°C
Parameter Symbol
ICLK = 4 MHz ICLK = 8 MHz
UnitMin Typ Max Min Typ Max
Programming time 1-byte tDP1 -94.7 886 -89.3 849 μs
Erasure time 1-KB tDE1K -9.59 299 -8.29 273 ms
Blank check time 1-byte tDBC1 --56.2 --52.5 μs
1-KB tDBC1K --2.17 --1.51 ms
Suspended time during erasing tDSED --23.0 --21.7 μs
Data flash STOP recovery time tDSTOP 720 --720
--ns
R01DS0264EU0130 Rev.1.30 Page 92 of 104
Feb 5, 2018
S124 Datasheet 2. Electrical Characteristics
2.12.3 Serial Wire Debug (SWD)
Figure 2.71 SWD SWCLK timing
Table 2.62 SWD characteristics (1)
Conditions: VCC = AVCC0 = 2.4 to 5.5 V
Parameter Symbol Min Typ Max Unit Test conditions
SWCLK clock cycle time tSWCKcyc 80 - - ns Figure 2.71
SWCLK clock high pulse width tSWCKH 35 - - ns
SWCLK clock low pulse width tSWCKL 35 - - ns
SWCLK clock rise time tSWCKr -- 5 ns
SWCLK clock fall time tSWCKf -- 5 ns
SWDIO setup time tSWDS 16 - - ns Figure 2.72
SWDIO hold time tSWDH 16 - - ns
SWDIO data delay time tSWDD 2 - 70 ns
Table 2.63 SWD characteristics (2)
Conditions: VCC = AVCC0 = 1.6 to 2.4 V
Parameter Symbol Min Typ Max Unit Test conditions
SWCLK clock cycle time tSWCKcyc 250 - - ns Figure 2.71
SWCLK clock high pulse width tSWCKH 120 - - ns
SWCLK clock low pulse width tSWCKL 120 - - ns
SWCLK clock rise time tSWCKr -- 5 ns
SWCLK clock fall time tSWCKf -- 5 ns
SWDIO setup time tSWDS 50 - - ns Figure 2.72
SWDIO hold time tSWDH 50 - - ns
SWDIO data delay time tSWDD 2 - 150 ns
SWCLK
tSWCKcyc
tSWCKH
tSWCKf
tSWCKr
tSWCKL
R01DS0264EU0130 Rev.1.30 Page 94 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Appendix 1. Package Dimensions
Information on the latest version of th e package dimensions or mountings is displayed in “Packages” on the Renesas
Electronics Corporation website.
Figure 1.1 LQFP 64-pin
MASS (Typ) [g]
0.3
Unit: mm
Previous CodeRENESAS Code
PLQP0064KB-C —
JEITA Package Code
P-LFQFP64-10x10-0.50
© 2015 Renesas Electronics Corporation. All rights reserved.
D
E
A2
HD
HE
A
A1
bp
c
T
e
x
y
Lp
L1
9.9
9.9
11.8
11.8
0.05
0.15
0.09
0q
0.45
Min Nom
Dimensions in millimeters
Reference
Symbol Max
10.0
10.0
1.4
12.0
12.0
0.20
3.5q
0.5
0.6
1.0
10.1
10.1
12.2
12.2
1.7
0.15
0.27
0.20
8q
0.08
0.08
0.75
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
HD
A2
A1
Lp
L1
Detail F
A
c
0.25
D
48 33
3249
17
161
64
F
NOTE 4
NOTE 3
Index area
*1
HE
E
*2
*3bp
e
yS
S
M
T
R01DS0264EU0130 Rev.1.30 Page 95 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Figure 1.2 LQFP 48-pin
MASS (Typ) [g]
0.2
Unit: mm
Previous CodeRENESAS Code
PLQP0048KB-B —
JEITA Package Code
P-LFQFP48-7x7-0.50
© 2015 Renesas Electronics Corporation. All rights reserved.
D
E
A2
HD
HE
A
A1
bp
c
T
e
x
y
Lp
L1
6.9
6.9
8.8
8.8
0.05
0.17
0.09
0q
0.45
Min Nom
Dimensions in millimeters
Reference
Symbol Max
7.0
7.0
1.4
9.0
9.0
0.20
3.5q
0.5
0.6
1.0
7.1
7.1
9.2
9.2
1.7
0.15
0.27
0.20
8q
0.08
0.08
0.75
NOTE)
1. DIMENSIONS “*1” AND “*2” DO NOT INCLUDE MOLD FLASH.
2. DIMENSION “*3” DOES NOT INCLUDE TRIM OFFSET.
3. PIN 1 VISUAL INDEX FEATURE MAY VARY, BUT MUST BE
LOCATED WITHIN THE HATCHED AREA.
4. CHAMFERS AT CORNERS ARE OPTIONAL, SIZE MAY VARY.
HD
A2
A1
Lp
L1
Detail F
A
c
0.25
HE
D
E
36 2525
24
13
37
48
112
F
NOTE 4
NOTE 3
Index area
*1
*2
*3
bp
e
yS
S
M
T
R01DS0264EU0130 Rev.1.30 Page 96 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Figure 1.3 LGA 36-pin
JEITA Package Code RENESAS Code Previous Code MASS (TYP.) [g]
P-WFLGA36-4x4-0.50 PWLG0036KA-A P36FC-50-AA4-2 0.023
ITEM DIMENSIONS
D
E
w
e
A
b
x
y
y1
ZD
ZE
4.00±0.10
4.00±0.10
0.05
0.20
0.69±0.07
0.08
0.50
0.24±0.05
(UNIT:mm)
0.20
0.75
0.75
S
y1 S A
S
y
Sx32x b A B
M
e
SwB
ZD
ZE
INDEX MARK
B
C
A
SwA
D
E
E
1
2
E
FDCBA
3
4
5
6
CDDETAIL DETAIL EDETAIL
b
0.34±0.05 0.55
0.70 ±0.05
0.55 ±0.05
0.70 ±0.05
0.55 ±0.05
0.75
φ
φ
0.75
0.55 0.55
R0.17±0.05 R0.17 ±0.05
R0.12 ±0.05 R0.12 ±0.05
R0.275±0.05
R0.35±0.05
0.75
0.55±0.05
0.70±0.05
0.55
0.75
0.55±0.05
0.70±0.05
(LAND PAD)
(APERTURE OF
SOLDER RESIST)
D
2.90
2.90
2012 Renesas Electronics Corporation. All rights reserved.
R01DS0264EU0130 Rev.1.30 Page 97 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Figure 1.4 QFN 64-pin
2013 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
48
32
33
16
17
1
64
A
S
B
A
D
E
49
DETAIL OF A PART
EXPOSED DIE PAD
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-HWQFN64-8x8-0.40 PWQN0064LA-A 0.16
16
1
17
32
49
64
INDEX AREA
2
2
D
A
Lp
0.20
6.50
0.40
8.00
8.00
6.50
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.23
0.30 0.50
b0.17
x
A0.80
y0.05
0.00
0.20
e
Z
Z
c
D
E
1
D
E
2
2
2
E
0.40
0.05
1.00
1.00
0.15 0.25
A1c2
8.05
7.95
8.05
7.95
Z
Z
D
E
33
48
P64K8-40-9B5-3
R01DS0264EU0130 Rev.1.30 Page 98 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Figure 1.5 QFN 48-pin
2013 Renesas Electronics Corporation. All rights reserved.
S
y
e
Lp
SxbA B
M
A
D
E
36
24
25
12
13
1
48
A
S
B
A
D
E
37
DETAIL OF A PART
EXPOSED DIE PAD
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-HWQFN48-7x7-0.50 PWQN0048KB-A 48PJN-A 0.13
12
1
13
24
37
48
INDEX AREA
2
2
D
A
Lp
0.20
5.50
0.40
7.00
7.00
5.50
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.30
0.30 0.50
b0.18
x
A0.80
y0.05
0.00
0.25
e
Z
Z
c
D
E
1
D
E
2
2
2
E
0.50
0.05
0.75
0.75
0.15 0.25
A1c2
7.05
6.95
7.05
6.95
Z
Z
D
E
25
36
P48K8-50-5B4-6
R01DS0264EU0130 Rev.1.30 Page 99 of 104
Feb 5, 2018
S124 Datasheet Appendix 1. Package Dimensions
Figure 1.6 QFN 40-pin
S
y
e
Lp
SxbA B
M
A
D
E
30
20
21
10
11
1
40
A
S
B
A
D
E
31
DETAIL OF A PART
EXPOSED DIE PAD
JEITA Package code RENESAS code Previous code MASS(TYP.)[g]
P-HWQFN40-6x6-0.50 PWQN0040KC-A P40K8-50-4B4-5 0.09
10
1
11
20
31
40
INDEX AREA
2
2
D
A
Lp
0.20
4.50
0.40
6.00
6.00
4.50
Referance
Symbol Min Nom Max
Dimension in Millimeters
0.30
0.30 0.50
b0.18
x
A0.80
y0.05
0.00
0.25
e
Z
Z
c
D
E
1
D
E
2
2
2
E
0.50
0.05
0.75
0.75
0.15 0.25
A1c2
6.05
5.95
6.05
5.95
Z
Z
D
E
21
30
S124 Microcontroller Group Datasheet
Proprietary Notice
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Rev. Date Summary
1.00 May 19, 2016 1st release
1.01 Oct 3, 2016 2nd release
1.30 Feb 5, 2018 3rd release
Revision History
S124 Microcontroller Group Datasheet
Publication Date: Rev.1.30 Feb 5, 2018
Published by: Renesas Electronics Corporation
Colophon
Address List General Precautions
1. Precaution against Electrostatic Discharge (ESD)
A strong electrical field, when exposed to a CMOS device, can cause destruction of the gate oxide and ultimately
degrade the device operation. Steps must be taken to stop the generation of st atic electricity as much as possible, and
quickly dissipate it when it occurs. Environmental control must be adequate. When it is dry, a humidifier should be used.
This is recommended to avoid using insulators that can easily build up static electricity. Semiconductor devices must be
stored and transported in an anti-static container, static shielding bag or condu ctive material. All test and measurement
tools including work benches and floors must be grounded. The operator must also be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions must be taken for printed circuit
boards with mounted semiconductor devices.
2. Processing at power-on
The state of the product is undefined at the time when power is supplied. The states of internal circuits in the LSI are
indeterminate and the states of register settings and pins are undefined at the time when power is supplied. In a finished
product where the reset signal is applied to the external reset pin, the states of pins are not guaranteed from the time
when power is supplied until the reset process is completed. In a similar way, the states of pins in a product that is reset
by an on-chip power-on reset function are not guaranteed from the time when power is supplied until the power reaches
the level at which resetting is specified.
3. Input of signal during power-off state
Do not input signals or an I/O pull-up power supply while the device is powered off. The current injection that results
from input of such a signal or I/O pull-up po wer supply may cause malfunction and the abnormal current that passes in
the device at this time may cause degradation of internal elements. Follow the guideline for input signal during power-
off state as described in your product documentation.
4. Handling of unused pins
Handle unused pins in accordance with the directions given under handling of unused pins in the manual. The input pins
of CMOS products are generally in the high-impedance state. In operation with an unused pin in the open-circuit state,
extra electromagnetic noise is induced in the vicinity of the LSI, an associated shoot-through current flows internally,
and malfunctions occur due to the false recognition of the pin state as an input signal become possible.
5. Clock signals
After applying a reset, only release the reset line after the operating clock signal becomes stable. When switching the
clock signal during program execution, wait until the target clock signal is stabilized. When the clock signal is generated
with an external resonator or from an external oscillator during a reset, ensure that the reset line is only released after full
stabilization of the clock signal. Additionally, when switching to a clock signal produced with an external resonator or
by an external oscillator while program execution is in progress, wait until the target clock signal is stable.
6. Voltage application waveform at input pin
Waveform distortion due to input noise or a reflected wave may cause malfu nction. If the input of the CMOS device
stays in the area between VIL (Max.) and VIH (Min.) due to noise, for example, th e device may malfunction. Take care to
prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the
input level passes through the area between VIL (Max.) and V IH (Min.).
7. Prohibition of access to reserved addresses
Access to reserved addresses is prohibited. The reserved addresses are provided for possible future expansion of
functions. Do not access these addresses as the correct operation of the LSI is not guaranteed.
8. Dif f erences between products
Before changing from one product to another, for example to a product with a different part number, confirm that the
change will not lead to problems. The characteristics of a microprocessing unit or microcontroller unit products in the
same group but having a different part number might differ in terms of internal memory capacity, layout pattern, and
other factors, which can affect the ranges of electrical characteristics, such as characteristic values, operating margins,
immunity to noise, and amount of radiated noise. When changing to a product with a different part number, implement a
system-evaluation test for the giv en product.
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Renesas Synergy™ Platform
S124 Microcontroller Group
R01DS0264EU0130
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