Enpirion® Power Datasheet
EN5365QI 6A Pow er SoC
Volt age M ode Synchr onous Buck PWM
DC-DC Conver t er wit h I nt egr at ed Inductor
3-Pin VI D O ut put Volt age Selec t
Description
This Altera Enpirion solution is a Power System
on a Chip (PowerSoC). It is specifically designed
to meet the precise voltage and fast transient
requirements of present and future high-
performance, low-power processor, DSP, FPGA,
ASIC, memory boards and system level
applications in a distributed power architecture.
Advanced circuit techniques, ultra high switching
frequency, and very advanced, high-density,
integrated circuit and proprietary inductor
technology deliver high-quality, ultra compact,
non-isolated DC-DC conversion. Operating this
converter requires as few as three external
components that include small value input and
output ceramic capacitors and a soft-start
capacitor.
The Altera Enpirion integrated inductor solution
significantly helps in low noise system design
and productivity by offering greatly simplified
board design, layout and manufacturing
requirements.
All Altera Enpirion products are RoHS compliant
and lead-free manufacturing environment
compatible.
Typical Application Circuit
VID Output
Voltage Select
V
OUT
V
IN
VSENSE
47µF
47µF
15nF
VOUT
VS0
VS1
VS2
ENABLE
PGNDAGND
SS
PVIN
AVIN
PGND
1Ω
Figure 1. Simple Schematic
Features
•Integrated INDUCTOR, MOSFETS, Controller
•Footprint 1/3rd that of c om peting s olutions .
•Low Par t Count: only 3 MLCC Capacitors.
•Up to 20W c ontinuous output pow er.
•Low output impedance optimized for ≤ 90 nm
•Master/slave configuration for paralleling.
•5MHz operating frequency.
•High efficiency, up to 93%.
•Wide input voltage range of 2.375V to 5.5V.
•3-pin VID output voltage select to choos e one
of 7 pre-pr ogram m ed O utput Voltages .
•Output enable pin and Power OK signal.
•Programmable soft-start time.
•O ptim iz ed for low nois e/EMI des ign.
•Ther m al s hutdown, over c urr ent, s hort c ir c uit,
over-voltage and under -voltage protection.
•RoHS compliant, MSL level 3, 260C reflow.
Applications
•Point of load r egulation for low -power
processors, network processors, DSPs,
FPGAs , and ASIC s
•≤ 90 nm advanced process loads
•Notebook computers, servers, workstations
•Broadband, networking, LAN/WAN, optical
•Low voltage, dis tributed pow er arc hitec tures
with 2.5V, 3.3V or 5V rails
•DSL, STB, D VR, D TV, Industrial PC
•Ripple s ens itive applic ations
Ordering Information
Part Num ber
Te m p Ra ting
(°C)
Package
EN5365QI
-40 to +85
58-pi n QF N T&R
EVB-EN5365QI
QF N E valuati on B oard
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Pin Configuration
Bel ow i s a top vi e w di agra m of the EN5365Q pa ckage.
NOTE: N C pins are not to be electrically conn ected to each other or to a ny e xternal signal , ground, or voltage.
However, they must be soldered to the PCB. Fai l ure to foll ow thi s gui del i ne m ay re sult in part m al functi on or
damage.
Figure 2. Pin Diagram , top view .
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Pin Descriptions
PIN
NAME
FUNCTION
1-3 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
4-5 NC(SW)
NO CONNECT – These pins are internall y conn ect ed to the com m on drain outpu t of
the internal M OS FETs. NC(SW) pins are not to be electrically connected to any
external signal , ground, or voltag e. However, they m ust be sol dered to the P CB .
Failure to follow this guideline m ay result in part m alfunction or dam age.
6-13 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
14-20 VOUT
Regulated converte r outp ut. Decouple w ith output filter capaci tor to PGND. Refer to
layout section for specific layout requ irem en ts
21-22 NC(SW)
NO CONNECT – These pins are internall y conn ect ed to the com m on drain outpu t of
the internal M OS FETs. NC(SW) pins are not to be electrically connected to any
external signal , ground, or voltag e. However, they m ust be sol dered to the P CB .
Failure to follow this guideline m ay result in part m alfunction or dam age.
23 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
24-29
PGND
Output power ground. Refer to layout section for specifi c layout requir em ents.
30-35 PVIN
I nput power supply. Connect to input pow er suppl y. Decouple w i th input capacitor to
PGND. Refer to layout section for speci fic layout requ irem en ts
36-37 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connected
internally.
38 ROCP
Optional Over Current P rotection adjust pin. U sed for diagnostic purpo ses only. Place
10kΩ resistor between this pin and A GND (pin 40) to raise the over current trip point
to approx i mately 200% of m ax i mum rated current.
39 AVIN
Analog voltage input for the contro ller circuits .
Connect this pin to PVI N using a 1 Ohm resistor.
40
AGND
Analog ground for the contro ller ci rcu its.
41-42 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
43
VS2
Voltage select line 2 input. S ee Table 1. This pin has internal pul l-up
44
VS1
Voltage select line 1 input. S ee Table 1. This pin has internal pul l-up
45
VS0
Voltage select line 0 input. S ee Table 1. This pin has internal pul l-up
46 POK
Power OK is an open drain transistor for power system state indi cat ion. POK is a
logic hi gh w hen VOU T is with -10% to +20% of VOUT nominal. Size pull-up resistor
to lim it current to 4m A when POK is low.
47 VSENSE
Output V oltage Sense. Connect to output voltage im m ediately dow nstre am from the
output fi lter capacitors.
48 SS
Soft-Start node. The soft-star t capacito r is connected between this pin and A GN D .
The value of this capacitor determ ine s the startu p tim ing.
49
EAIN
Optional E rror Am plifier input. Allows for custom ization of the control loop.
50
EAOUT
Optional E rror Am plifier output. Allows for custom iz ation of the control loop.
51
COMP
Optional E rror Am plifier Buffer output . Allows for custom ization of the control loop.
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PIN
NAME
FUNCTION
52 ENABLE
I nput E nable. Applying a logic high, enables the output and ini tiates a soft-sta rt.
Applying a l ogic low disables the output.
53 PWM
PWM input/output. U sed for optional m aster/slave configur atio n. When M /S pin is
asserted “low”, PWM will output the gate-drive P WM waveform . When the M /S pin is
asserted “high”, the P WM pi n is configured as an input for PWM signal from the
“m aster” device. PWM pin can drive up to 3 slave devices.
NOTE: Leave this pin open w hen not using parallel m ode.
54 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
55 M/S
Optional M aster/Slave select pi n. Assertin g pin “low” places device in M aster M ode
for current sharing. PW M pin (53) w ill output PWM drive signal. Asserting pin “high”
will place the device in Slave M ode. PWM pin (53) will be
confi gured to input (rec ei ve )
PWM drive signal from “M aster” device.
NOT E: Leave this pin open when not using parallel m ode.
56-58 NC
NO CONNECT: These pins should not be electrically conn ecte d to each other or to
any external signal, voltage, or groun d. One or m ore of these pins m ay be connecte d
internally.
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Block Diagram
(+)
(-)
Error
Amp
V
OUT
P-Drive
N-Drive
UVLO
Thermal Limit
Over Voltage
So ft Start
Sawtooth
Generator
(+)
(-)PWM
Comp
PVIN
ENABLE
Compensation
Bandgap
Reference
PGND
AVINEAOUT
SS Reference
Voltage
selector
Current Limit
EAIN AGND
Power
Good
Logic
V
OUT
POK
ROCP
Voltage
Selector
VS0
VS1
VS2
VSENSE
COMP
Figure 3. Syste m bl ock diagra m .
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Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods m ay affec t devic e reliability.
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Supply Voltage
VIN
-0.5
7.0
V
Voltages on: ENABLE , VSENSE, VS2-VS0, M/S (Note 1)
-0.5
VIN
V
Voltages on: EAIN , EAO U T , COMP
-0.5
2.5
V
Voltages on: SS, PWM
-0.5
3.0
V
Voltages on: POK
-0.5
VIN + 0.3
V
Storage T emperature Range
TSTG
-65
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
NOTES:
1. VS0, VS1 and VS2 pins have an internal pull-up resistor, only ground potentials should be placed on them as
required.
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
VIN
2.375
5.5
V
Output Voltage Range
VOUT
0.75
3.3
V
Operating Ambient T emperature
TA
-40
+85
°C
Operating Junction T emperature
TJ
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient (0 LFM) (Note 2)
θJA
20
°C/W
T hermal Resistance: Junction to Cas e (0 LFM)
θJC
1.5
°C/W
T hermal Overload T rip Point
TJ-TP
+150
°C
T hermal Overload T rip Point Hysteresis
20
°C
NOTES:
2. Based on a four-layer board and proper thermal design in line with JEDEC EIJ /JESD 51 Standar ds.
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Electrical Characteristics
NO TE: VIN=5.5V over operating temper ature r ange unles s otherw is e noted.
Typic al values are at TA = 25°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
I nput V oltage
VIN
2.375
5.5
V
Output Regulation
Initial Accuracy VOUT
2.375V ≤ V
IN
≤ 5.5V,
ILOAD = 1A; TA = 25°C
VI D Output V oltage S etting (V):
1.2, 1.25, 1.5, 1.8, 2.5, 3.3
0.8
-2.0
-3.0 +2.0
+3.0
%
Variati on due to all
causes VOUT
2.375V ≤ V
IN
≤ 5.5V,
0A ≤ ILOAD ≤ 6A
-40°C ≤ TA ≤ +85°C
VI D Output V oltage S etting (V):
1.2, 1.25, 1.5, 1.8, 2.5, 3.3
-3.0
+3.0
%
2.375V ≤ V
IN
≤ 5.5V,
0A ≤ ILOAD ≤ 6A
-40°C ≤ TA ≤ +85°C
VI D Output V oltage S etting (V): 0.8
-4.0 +4.0 %
Transient Response (IOUT = 0% to 100% or 100% to 0% o f Rated L oad)
Peak Deviation ∆VOUT
V
IN
= 5V, 1.2V < V
OUT
< 3.3V,
COUT = 50μF
3 %
Under Volta ge L ockou t
Under Voltage Lock
out threshold
VUVLO
V
IN
Increasing
VIN Decreasing
2.2
2.1
V
S witching Fr equ en cy
Switching
Frequency
FSWITCH 5 MHz
L oad Character is tic s
Maximum
Continuous Output
Current
IOUT (N ote 3) 6 A
Current Lim it
Threshold
IOCP_TH 9 A
S upply Current
Shut-Dow n S upply
Current
IS ENABLE=0V 50 µA
Enabl e Operation
Disabl e Threshold VDISABLE
M ax voltage to ensure the
converter is disabled
0.8 V
Enable Threshold
VENABLE
2.375V ≤ VIN ≤ 5.5V
1.8
V
Enable P in Current
IEN
VIN = 5.5V
50
µA
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03816 October 11, 2013 Rev G
EN5365QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Voltage Select Operation
Logic Low
Threshold
VSX-Low Threshold voltage for Logic Low 0.8 V
Logic High
Threshold VSX-High
Threshold voltage for Logic High
(internally pulled high; can be left
floating to achieve logic high)
1.8 VIN V
VSx Pin Current IVSX
VIN = 5.5V
VSx = GND
VSx = VIN
VSx = Open
50
0
0
µA
Power OK Ope ra tion (Open Drai n)
POK threshold High
Percentage of V OUT Nominal
120
%
POK threshold low
Percentage of V OUT Nominal
90
%
POK Low Voltage
IPOK = 4 mA (Max sink Current)
0.4
V
POK High Voltage
VIN
%
Output Rise T ime
VOUT Rise Time
Accuracy ∆TRISE
T
RISE
= C
ss
* 75KΩ;
10nF ≤ CSS ≤30nF
(Note 4)
-25 +25 %
Parallel Operation
Current Balance ∆IOUT
With 2 – 4 converters in parallel,
the difference between any 2 par ts .
∆VIN < 50m V ; RTRACE < 10m Ω.
+/-10 %
NOTES:
3. Maximum output current may need to be de-rated, base d on oper ating condit ion, to meet T J requirements.
4. Parameter not production tested but is guaranteed by design. Rise tim e begins when AVIN > VUVLO and
Enable=HIGH.
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Typical Performance Characteristics
Eff iciency vs. Load, VIN = 3.3V.; Load = 0-6A. Eff iciency vs. Load, VIN = 5.0V.; Load = 0-6A.
Ripple Voltage, 5.0VIN/1.2VOUT, I OUT=6A, Ripple Voltage, 3.3VIN/1.2VOUT, I OUT=6A,
COUT = 3x22uF. COUT = 3x22uF.
T ransient Response 5.5VIN/1.2VOUT, 0 -6A, 10A/u S. T ransient Response 5.5VIN/3.3VOUT, 0 -6A, 10A/u S.
COUT = 50uF COUT = 50uF
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 44.5 55.5
Load Current (A)
Efficiency (%)
V
IN
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 44.5 55.5
Load Current (A)
Efficiency (%)
V
IN
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 44.5 55.5
Load Current (A)
Efficiency (%)
V
IN
=5.0V
V
OUT
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
50
55
60
65
70
75
80
85
90
95
00.5 11.5 22.5 33.5 44.5 55.5
Load Current (A)
Efficiency (%)
V
IN
=5.0V
V
OUT
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
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Theory of Operation
Synchr onous Buck Conver ter
The EN5365QI is a synchronous, pin
programmable power supply with integrated
power MOSFET switches and integrated
inductor. The nominal input voltage range is
2.375-5.5V. The output can be set to common
pre-set voltages by connecting appropriate
combinations of 3 voltage selection pins to
ground. The feedback control loop is a type III
voltage-mode and the part uses a low-noise
PWM topology. Up to 6A of output c ur rent c an be
drawn from this converter. The 5MHz operating
frequency enables the use of small-size output
capacitors.
The power supply has the following protection
features:
• Programmable over-current protection (to
protec t the IC fr om exc es s ive load c ur rent)
• Thermal shutdown with hysteresis.
• Over-voltage protection
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Additional features inc lude:
• Soft-start circuit, limiting the in-rush
c urrent w hen the c onverter is pow ered up.
• Power good circuit indicating whether the
output voltage is within 90%-120% of the
program m ed voltage.
Output Voltage Programming
The EN5365QI output voltage is programmed
using a 3-pin voltage-ID or VID selector. Three
binary VID pins allow the user to choose one of
seven pre-set voltages. Refer to table 1 for the
proper VID pin s ettings to pr ogram VOUT.
The voltage select pins, VS0, VS1, and VS2, are
pulled-up internally and so will default to a logic
high, or “1”, if left “open”. Connecting the voltage
s elec t pin to ground w ill res ult in a logic “0”. For a
device capable of external output voltage
adjus tm ent, r efer to the E N5366Q I datas heet.
Table 1: Output Voltage Select Table
VS2* VS1* VS0*
Out put Voltage
0
0
0
3.3V
0
0
1
2.5V
0
1
0
1.8V
0
1
1
1.5V
1
0
0
1.25V
1
0
1
1.2V
1
1
0
0.8V
1
1
1
Reserved
Inpu t Cap acitor S election
The EN5365QI requires about 40-50uF of input
capacitance. Low ESR ceramic capacitors are
required with X5R or X7R dielectric formulation.
Y5V or equivalent dielectric formulations must
not be used as they lose capacitance with
frequenc y, tem peratur e and bias voltage.
In some applications, lower value ceramic
capacitors maybe needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
Table 2. Recommended input capacitors.
Description
MFG
P/N
22uF, 10V,
X5R, 1206
Murata GRM31CR61A226ME19L
( 2 capacitor s needed )
Taiyo Yuden
LMK316BJ226ML-T
47uF, 10V,
X5R, 1210
Murata
GRM32ER61A476KE20L
(1 capacitor needed) Taiyo Yuden LMK325BJ476MM-T
Output C apacitor Selectio n
The EN5365QI has been optimized for use with
approximately 50μF of output capacitance. Low
ESR c eram ic c apac itors are required w ith X5R or
X7R dielectric formulation. Y5V or equivalent
dielec tr ic form ulations m us t not be us ed as thes e
lose capacitance with frequency, temperature
and bias voltage.
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03816 October 11, 2013 Rev G
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Table 3. Recommended output capacitors.
Description
MFG
P/N
22uF, 6.3V, 10%
X5R, 1206
(3 capacitors needed)
Murata
T aiyo Yuden
GRM31CR60J226KE19L
JMK316BJ226KL-T
47uF, 10V, 10%
X5R, 1210
47uF, 6.3V, 10%
X5R, 1210
(1 capacitor needed)
Murata
AVX
GRM32ER61A476KE20L
12106D476KAT2
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 5MHz switching frequency output impedance,
denoted as Z, is comprised mainly of effective
series resistance, ESR, and effective series
inductance, ESL:
Z = ESR + ESL.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal
ZZZZ 1
...
111
21
+++=
Typical ripple versus capacitor arrangement is
given below:
Output Capacitor
Configuration
Typical Out put Ri ppl e (mV p-p)
(as measur ed o n EN5365QI
Eva l uation Boa rd)
1 x 47u F
30
3 x 22 u F
15
Compensation
The EN5365 is internally compensated through
the use of a type 3 compensation network and is
optimized for use with about 50μF of output
capacitance and will provide excellent loop
bandwidth and transient performance for most
applications. Voltage mode operation provides
high noise immunity at light load. Further,
Voltage mode control provides superior
impedance matching to sub 90nm loads.
In s om e c as es m odific ations to the c om pens ation
may be required. The EN5365QI provides the
capability to modify the control loop to allow for
customization for a given application. For more
information, contact Altera Power Applications
support.
En able Operation
The ENABLE pin provides a means to shut down
the device, or enable normal operation. A logic
low will dis able the c onverter and c aus e it to s hut
down. A logic high will enable the converter into
normal operation. When the ENABLE pin is
asserted high, the device will undergo a normal
soft start.
Soft-Start Operation
The SS pin in conjunction with a small capacitor
between this pin and AGND provides the soft
start function to limit the in-rush current during
start-up. During start-up of the converter the
reference voltage to the error amplifier is
gradually increased to its final level by an internal
current source of typically 10uA charging the soft
start capacitor. The typical soft-start time for the
output to reach regulation voltage, from when
AVIN > VUVLO and Enable crosses its logic high
threshold, is given by:
TSS = CSS * 75KΩ (seconds)
Where the soft-start time TSS is in seconds and
the soft-start capacitance CSS is in Farads.
Typically, a capacitor of around 15 nF is
recommended.
During the soft-start cycle, when the soft-start
capacitor reaches 0.75V, the output has reached
its programmed regulation range. Note that the
soft-start current source will continue to operate,
and during normal operation, the soft-start
c apac itor will c har ge up to a final value of 2.5V.
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03816 October 11, 2013 Rev G
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Power-Up/Down Sequencing
During power-up, ENABLE should not be
asserted before PVIN, and PVIN should not be
asserted before AVIN. The PVIN should never
be powered when AVIN is off. During power
down, the AVIN should not be powered down
before the PVIN. Tying PVIN and AVIN or all
three pins (AVIN, PVIN, ENABLE) together
during power up or power down meets these
requirements.
Pre-Bias Start-up
The EN5365QI does not support startup into a
pre-biased condition. Be sure the output
capacitors are not charged or the output of the
EN5365QI is not pre-biased when the EN5365QI
is first enabled.
P OK Op e r a tio n
The POK signal is an open drain signal from the
converter indicating the output voltage is within
the specified range. The POK signal will be a
logic high when the output voltage is within 90% -
120% of the programmed output voltage. If the
output voltage goes outside of this range, the
POK signal will be a logic low until the output
voltage has returned to within this range. In the
event of an over-voltage condition the POK
signal will go low and will remain in this condition
until the output voltage has dropped to 95% of
the programmed output voltage before returning
to the high s tate.
The internal POK FET is designed to tolerate up
to 4mA. The pull-up resistor value should be
chosen to limit the current from exceeding this
value when POK is logic low.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through a sense P-MOSFET.
When the sensed current exceeds the current
limit, both NFET and PFET switches are turned
off. If the over-current condition is removed, the
over-current protection circuit will re-enable the
PWM operation. If the over-current condition
persists, the circuit will continue to protect the
load.
The OCP trip point is nominally set to 150% of
maximum rated load. For diagnos tic purpos es , it
is possible to increase the OCP trip point to
approximately 200% of the maximum rated load
by connecting a 10kΩ resistor between the
ROCP pin (pin 38) and AGND (pin 39). This is
intended for troubleshooting purposes only and
the specification is not guaranteed.
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
PO K returns to its high s tate.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 20ºC, the converter will re-start with a
norm al s oft-start.
Input Under-Voltage Lock-Out
Cir c uitry is provided to ens ur e that w hen the
input voltage is below the required voltage level
(VUVLO) for norm al operation, the c onverter w ill
not s tart-up. C irc uits for hys teres is and input de-
glitc h ar e inc luded to ens ure high nois e im m unity
and to pr event fals e tripping.
Parallel D evice Operation
The EN5365QI is c apable of par alleling up to a
total of four c onverters to provide up to 24A of
continuous current. Pleas e c ons ult Paralleling
Cir c uit Des ign w ith EN5365/66 for more details
and rec om m endations .
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03816 October 11, 2013 Rev G
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Layout Recommendations
Fi gure 5. Layout of power a nd ground coppe r. Fi gure 6. Use of the rm al & noi se suppressi on vi as.
Recommendation 1: Input and output filter
capacitors should be placed as close to the
EN5365QI package as possible to reduce EMI
from input and output loop currents. This
reduces the physical area of the Input and
O utput AC c urrent loops .
Recommendation 2: Place a slit in the
input/output capacitor ground copper starting
just below the common connection point of the
devic e GND pins as s hown in figures 5 and 6.
Recommendation 3: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible. The drill diameter of the vias
s hould be les s than 0.33m m , and the vias m us t
have at least 1 oz. copper plating on the inside
wall, making the finished hole size around
0.26mm. This connection provides the path for
heat dissipation from the converter. Please see
figur es 6, 7, and 8.
Recommendation 4: Multiple small vias
should be used to connect ground terminal of
the input capacitor and output capacitors to the
system ground plane as shown in figure 6.
These vias can be the same size as the
therm al vias dis c us s ed in rec om m endation 3.
Recommendation 5: The system ground
plane referred to in recommendations 3 and 4
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output capacitors
shown in figure 6.
Recommendation 6: As with any switch-mode
DC /D C c onverter , do not r un s ens itive s ignal or
control lines underneath the converter
package.
Pleas e refer to the Gerber files and
summarized layout notes available at
www.altera.com/enpirion for more layout
details.
NOTE: Figures 5 and 6 show only the c ritic al
components and traces for a minimum footprint
layout. ENABLE, Vout-programming, and
other s m all s ignal pins need to be c onnec ted
and routed ac c or ding to the s pec ific
application.
Slit separating
input local ground
from output
local ground
V
OUT
(+)
Copper V
IN
(+)
Copper
Local
Ground
Copper Slit separating
input local ground
from output
local ground
V
OUT
(+)
Copper V
IN
(+)
Copper
Local
Ground
Copper
Compensation
Test Points
AGND
Test
Points
Thermal Pad
Vias and
Soldermask
Opening
High-Frequency
Noise Suppression
Vias
Vout
PGND
Copper
Slit
Vin
Compensation
Test Points
AGND
Test
Points
Thermal Pad
Vias and
Soldermask
Opening
High-Frequency
Noise Suppression
Vias
Vout
PGND
Copper
Slit
Vin
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03816 October 11, 2013 Rev G
EN5365QI
Design Considerations for Lead-Frame Based Modules
Exp osed Metal on Bottom Of P ackage
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, ,
and in overall foot pr int. How ever , they do require s om e s pec ial c ons ider ations .
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This r es ults in s everal s m all pads being expos ed on the bottom of the pac kage.
Only the large thermal pad and the perimeter pads are to be mechanic ally or elec tr ic ally c onnec ted to
the PC board. The PCB top layer under the EN5365QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 7 represents the area that should be clear of any
m etal ( trac es , vias , or planes ), on the top layer of the P CB .
Figure 8 demonstrates the recommended PCB footprint for the EN5365QI. Figure 9 shows the shape
and loc ation of the expos ed m etal pads as w ell as the m ec hanic al dim ens ion of the lar ge therm al pad
and the pins .
Figure 7. Lead-Frame expos ed metal. Grey ar ea high ligh ts expo s ed metal that is not to be mech anic ally or
electrically con nected to the PCB.
Ground copper my exten d under this pad.
However, DO NOT CONNECT (NC)
Ground copper my exten d under this pad.
However, DO NOT CONNECT (NC)
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03816 October 11, 2013 Rev G
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Contact Information
Altera Corporation
101 Innovation Dr ive
San Jos e, C A 95134
Phone: 408-544-7000
www.altera.com
© 2013 Alter a C or por ati on —Confidential. All rights reserved. ALTERA, ARRIA, CYCLONE, ENPI RION, HARDCOPY, MAX, MEGACORE, NIOS,
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18 www.altera.com/enpirion
03816 October 11, 2013 Rev G
