Rev. 0.1 12/11 Copyright © 2011 by Silicon Labs Si52144-EVB
Si52144-EVB
Si52144 EVALUATION BOARD USER’S GUIDE
Description
The Si52144 is a four port PCIe clock generator
compliant with the PCIe Gen1, Gen2 and Gen3
standards. The Si52144 is a 24-pin QFN device that
operates on a 3.3 V power supply and can be contr olled
using SMBus signals along with hardware control input
pins. The differential outputs support spread spectrum
and can be controlled through SSON input pin. The
Si52144 needs a crystal or clock input of 25 MHz. The
connections are described in this document.
EVB Features
This document is intended to be used in conjunction
with the Si52144 device and data sheet for the followin g
tests:
PCIe Gen1, Gen2, Gen3 compliancy
Power consumption test
Jitter performance
Testing out I2C code for signal tuning
In-system validation where SMA connectors are
present
Si52144
SRC3
connection
for
application
SRC2
connection
for
application
SRC1
connection for
application
VDD = 3.3 V
power supply
GND
SDATA
GND
SCLK
SRC0
connection for
application
Spre ad Sele c tion
DIFF3 Output Enable
DIFF1 Output Enable
DIFF2 Output Enable
DIFF0 Output Enable
Power connectors
External Clock Input
Si52144-EVB
2 Rev. 0.1
1. Front Panel
Figure 1. Evaluation Module Front Panel
Table 1. Input Jumper Settings
Jumper Label Type Description
OE0 I OE0, 3.3 V Input for Enabling DIFF0 Clock Output.
1 = DIFF0 enabled, 0 = DIFF0 disabled.
OE1 I OE1, 3.3 V Input for Enabling DIFF1 Clock Output.
1 = DIFF1 enabled, 0 = DIFF1 disabled.
OE2 I OE2, 3.3 V Input for Enabling DIFF2 Clock Output.
1 = DIFF2 enabled, 0 = DIFF2 disabled.
OE3 I OE3, 3.3 V Input for Enabling DIFF3 Clock Output.
1 = DIFF3 enabled, 0 = DIFF3 disabled.
SSON I SSON Input, 3.3 V-Tolerant Active Input for Spread Selection.
Internal 100 k pulldown. Refer to Table 2.
SDATA I/O SMBus-Compatible SDATA.
SCLK I SMBus-Compatible SCLOCK.
External Clock Input for
Si52144-EVB only
3.3 V Power Supply Connector
GND Connector
VDD Connectors
OE1 Hardware Input
Control for DIFF1 Output
SSON Spread Select Input
OE2 Hardware Input
Control for DIFF2 Output
OE0 Hardware Input
Control for DIFF0 Output
Si52144 Device Mount DIFF0 Differential Output
DIFF1 Differential Output
DIFF2 Differential Output
DIFF3 Differential Output
OE_DIFF3 Hardware Input
Control for DIFF3 Output
I2C Connect for I2C Read and
Write. In sequence SData,
GND, SCLK from left to right.
Si52144-EVB
Rev. 0.1 3
1.1. Generating DIFF Outputs from the Si52144
If the input pins are left floating upon power-on of the device, by default all DIFF outputs DIFF[0:3] are ON with
100 MHz and with spread spectrum disabled. The input pin headers have clear indication of jumper settings for
setting logic LOW (0) and HIGH (1) as shown below. The jumper placed on the middle and left pin will set input
OE0 to LOW; the jumper placed on the middle and right pin will set input OE0 to HIGH.
The output enable pins can be changed on the fly to observe outputs stopped cleanly. To enable the spread
spectrum, the SSON input needs to change from a logic level low to high. Input functionality is explained in detail
below.
1.1.1. SSON Input
Apply the appropriate logic level to SSON input to achieve clock frequency selection. When the SSON is HIGH,
–0.5% down spread is enabled on all differential outputs with a saw-tooth spread profile. When the SSON is LOW,
spread profile is disabled.
1.1.2. OE [0:3] Input
The output enable pins can change on the fly when the device is on. Deasserting (valid low) results in
corresponding DIFF output to be stopped after their next transition with final state low/low. Asserting (valid high)
results in corresponding output that was stopped are to resume normal operation in a glitch-free manner.
Each of the hardware OE [0:3] pins are mapped via I2C to control bit in Control register. The hardware pin and the
Register Control Bit both need to be high to enable the output. Both of these form an “AND” function to disable or
enable the DIFF output. The DIFF outputs and their corresponding I2C control bits and hardware pins are listed in
Table 3.
Table 2. Spread Selection
SSON Frequency
(MHz) Spread
(%) Note
0 100.00 OFF Default Value for SSON=0
1 100.00 –0.5
Table 3. Output Enable Control
I2C Control Bit Output Hardware Control Input
Byte1 [bit 2] DIFF0 OE0
Byte1 [bit 0] DIFF1 OE1
Byte2 [bit 7] DIFF2 OE2
Byte2 [bit 6] DIFF3 OE3
Si52144-EVB
4 Rev. 0.1
2. Schematics
Figure 2. QFN-24 Device Connection
Figure 3. Device Power Supply
DUTGND
DUTGND
XTL P/N:
ECS-250-20-5PXDU-F-TR
Use SMD footprint
DUTGND
NI
NI
For Si52144,R10 open
For Si53154,R11 open
VDD1
VDD6
VDD12
VDD17
VDD21
DIFF0
DIFF0#
DIFF1
DIFF1#
DIFF2
DIFF2#
DIFF3
DIFF3#
SCLK
SDATA
OE2
OE0
OE3
OE1
SSON
XOUT_DIFFIN
XIN_DIFFIN#
VDD1
YC2
20pF
YC2
20pF
YC1
20pF
YC1
20pF
R4R4
R3
0
R3
0
R11 10KR11 10K
C5
0.1uF
C5
0.1uF
R2
0
R2
0
C4
0.1uF
C4
0.1uF
R1R1
C3
0.1uF
C3
0.1uF
C2
0.1uF
C2
0.1uF
C1
0.1uF
C1
0.1uF
U2
Si52144
U2
Si52144
EPAD
25
DIFF2 14
OE1
2
XOUT/DIFFIN 22
SSON
3
OE2
5
OE3
18
OE0
7
DIFF1# 11
DIFF1 10
DIFF0# 9
DIFF0 8
VDD21
21 VDD17
17 VDD12
12 VDD6
6VDD1
1
VSS4
4
XIN/DIFFIN# 23
SCLK
19
SDA
20
VSS24
24
DIFF3# 15
DIFF3 16
DIFF2# 13
R10
NI
R10
NI Y1
25MHz
Y1
25MHz
DUTGNDDUTGND DUTGND DUTGND DUTGND
DUTGND
DUTGND
DUTGND
VDD_3.3V
VDD_3.3V
VDD1
VDD21
VDD6
VDD12
VDD17
C7
0.1uF
C7
0.1uF
+
C9
10uF
+
C9
10uF
JP4
JUMPER
JP4
JUMPER
+
C8
10uF
+
C8
10uF
C16
1uF
C16
1uF
GND1
HEADER 1x1
GND1
HEADER 1x1
1
L6L6
TP4
GND
TP4
GND
JP3
JUMPER
JP3
JUMPER
C15
1uF
C15
1uF
C14
1uF
C14
1uF
L5L5
VDD_3V31
HEADER 1x1
VDD_3V31
HEADER 1x1
1
C17
1uF
C17
1uF
L4L4
C13
1uF
C13
1uF
L3L3
JP2
JUMPER
JP2
JUMPER
R9
0
R9
0
L2L2
R8
0
R8
0
TP5
GND
TP5
GND
JP1
JUMPER
JP1
JUMPER
R7
0
R7
0
TP1
GND
TP1
GND
TP2
GND
TP2
GND
R6
0
R6
0
R5
0
R5
0
+
C12
10uF
+
C12
10uF
+
C11
10uF
+
C11
10uF
JP5
JUMPER
JP5
JUMPER
L1L1
+
C6
10uF
+
C6
10uF
TP3
GND
TP3
GND
+
C10
10uF
+
C10
10uF
Si52144-EVB
Rev. 0.1 5
Figure 4. Clock and Control Signals
Figure 5. Differential Clock Signals
SCLK/SDATA
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
VDD
GND
DUTGND
OE2
OE0
OE3
OE1
SSON
DUTGND
DUTGND
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
VDD_3.3V
OE2
OE0
OE3
OE1
SSON
SCLK
SDATA
XIN_DIFFIN#
XOUT_DIFFIN
XOUT_DIFFIN1
SMA
XOUT_DIFFIN1
SMA
R24
10K
R24
10K
P4
HEADER 1x3
P4
HEADER 1x3
1
2
3
R17
10K
R17
10K
P2
HEADER 1x3
P2
HEADER 1x3
1
2
3
R20
10K
R20
10K
R23
10K
R23
10K
XIN_DIFFIN#1
SMA
XIN_DIFFIN#1
SMA
P1
HEADER 1x3
P1
HEADER 1x3
1
2
3
P3
HEADER 1x3
P3
HEADER 1x3
1
2
3
R15
10K
R15
10K
P6
HEADER 1x3
P6
HEADER 1x3
1
2
3
R16
10K
R16
10K
P5
HEADER 1x3
P5
HEADER 1x3
1
2
3
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
L1 SHOULD BE
SHORT AS POSSIBLE
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DUTGND
DIFF0
DIFF0#
DIFF1#
DIFF1
DIFF2#
DIFF2
DIFF3#
DIFF3
C28
2.0pF
C28
2.0pF
DIFF2_1
SMA
DIFF2_1
SMA
DIFF1#_1
SMA
DIFF1#_1
SMA
DIFF0#_1
SMA
DIFF0#_1
SMA
DIFF2#_1
SMA
DIFF2#_1
SMA
C33
2.0pF
C33
2.0pF
C31
2.0pF
C31
2.0pF
DIFF3_1
SMA
DIFF3_1
SMA
C27
2.0pF
C27
2.0pF
DIFF3#_1
SMA
DIFF3#_1
SMA
C29
2.0pF
C29
2.0pF
DIFF0_1
SMA
DIFF0_1
SMA
C34
2.0pF
C34
2.0pF
C32
2.0pF
C32
2.0pF
C30
2.0pF
C30
2.0pF
DIFF1_1
SMA
DIFF1_1
SMA
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