S3C9644/C9648/P9648 PRODUCT OVERVIEW
1-1
1PRODUCT OVERVIEW
SAM87RI PRODUCT FAMILY
Samsung's SAM87RI family of 8-bit single-chip CMOS microcontrollers offers a fast and efficient CPU, a wide
range of integrated peripherals, and various mask-programmable ROM sizes.
A dual address/data bus architecture and a large number of bit- or nibble-configurable I/O ports provide a flexible
programming environment for applications with varied memory and I/O requirements. Timer/counters with
selectable operating modes are included to support real-time operations. Many SAM87RI microcontrollers have
an external interface that provides access to external memory and other peripheral devices.
S3C9644/C9648/P9648 Microcontroller
The S3C9644/C9648/P9648 single-chip 8-bit microcontroller is fabricated using an advanced CMOS process. It is
built around the powerful SAM87RI CPU core.
Stop and Idle power-down modes were implemented to reduce power consumption. To increase on-chip register
space, the size of the internal register file was logically expanded. The S3C9644 has 4K-bytes of program
memory on-chip and S3C9648 has 8K-bytes.
Using the SAM87RI design approach, the following peripherals were integrated with the SAM87RI core:
—Five configurable I/O ports (32 pins)
—20 bit-programmable pins for external interrupts
—8-bit timer/counter with three operating modes
—Low speed USB function
The S3C9644/C9648/P9648 is a versatile microcontroller that can be used in a wide range of low speed USB
support general purpose applications. It is especially suitable for use as a keyboard controller and is available in
a 42-pin SDIP and a 44-pin QFP package.
OTP
The S3C9644/C9648 microcontroller is also available in OTP (One Time Programmable) version, S3P9648.
S3P9648 microcontroller has an on-chip 8K-byte one-time-programmable EPROM instead of masked ROM. The
S3P9648 is comparable to S3C9644/C9648, both in function and in pin configuration.
PRODUCT OVERVIEW S3C9644/C9648/P9648
1-2
FEATURES
CPU
•SAM87RI CPU core
Memory
•4/8K-byte internal program memory (ROM)
•208-byte RAM
Instruction Set
•41 instructions
•IDLE and STOP instructions added for power-
down modes
Instruction Execution Time
•1.0 µs at 6 MHz fOSC
Interrupts
•25 interrupt sources with one vector, each
source has its pending bit
•One level, one vector interrupt structure
Oscillation Circuit
•6 MHz crystal/ceramic oscillator
•External clock source (6 MHz)
General I/O
•Bit programmable five I/O ports (34 pins total)
—(D+/PS2, D-/PS2 Included)
Timer/Counter
•One 8-bit basic timer for watchdog function and
programmable oscillation stabilization interval
generation function
•One 8-bit timer/counter with Compare/Overflow
USB Serial Bus
•Compatible to USB low speed (1.5 Mbps) device
1.0 specification.
•1 Control endpoint and 2 Data endpoint
•Serial bus interface engine (SIE)
—Packet decoding/generation
—CRC generation and checking
—NRZI encoding/decoding and bit-stuffing
•8 bytes each receive/transmit USB buffer
Operating Temperature Range
•– 40 _C to + 85 _C
Operating Voltage Range
•4.0 V to 5.25 V
Package Types
•42-pin SDIP
•44-pin QFP
S3C9644/C9648/P9648 PRODUCT OVERVIEW
1-3
BLOCK DIAGRAM
Port 0
Port 3
SAM87RI CPU
P0.0-P0.7/INT2
4/8-KB ROM
P3.0
P3.1
P3.2
P3.3/CLO
OSC
208-Byte
Register
Port 4
P4.0 / INT1
P4.1 / INT1
P4.2 / INT1
P4.3 / INT1
TIMER 0
Port 1 Port 2
P2.0-P2.7 / INT0
P1.0-P1.7
XIN
XOUT
SAM87RI BUS
Basic
Timer
I/O Port And
Interrupt Control
USB D+/PS2
D-/PS2
3.3 VOUT
16 bytes
USB
Buffer
Figure 1-1. Block Diagram
PRODUCT OVERVIEW S3C9644/C9648/P9648
1-4
PIN ASSIGNMENTS
P3.1
P3.0
INT0 / P2.0
INT0 / P2.1
INT0 / P2.2
INT0 / P2.3
INT0 / P2.4
INT0 / P2.5
INT0 / P2.6
INT0 / P2.7
VDD
VSS
XOUT
XIN
TEST
INT1 / P4.0
INT1 / P4.1
RESET
INT1 / P4.2
INT1 / P4.3
P1/7
S3C9644
S3C9648
42-SDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P3.2
P3.3/CLO
D+/PS2
D-/PS2
3.3 VOUT
NC
P0.0 / INT
P0.1 / INT
P0.2 / INT
P0.3 / INT
P0.4 / INT
P0.5 / INT
P0.6 / INT
P0.7 / INT
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Figure 1-2. Pin Assignment Diagram (42-Pin SDIP Package)
S3C9644/C9648/P9648 PRODUCT OVERVIEW
1-5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P4.3/INT1
P4.2/INT1
RESET
3.3 VOUT
D-/PS2
D+/PS2
P3.3/CLO
P3.2
P3.1
P3.0
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
NC
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4 /INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
INT0 / P2.4
INT0 / P2.5
INT0 / P2.6
INT0 / P2.7
VDD
VSS
XOUT
XIN
TEST
P4.0/INT1
P4.1/INT1
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
S3C9644
S3C9648
44-QFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
Figure 1-3. Pin Assignment Diagram (44-Pin QFP Package)
PRODUCT OVERVIEW S3C9644/C9648/P9648
1-6
PIN DESCRIPTIONS
Table 1-1. S3C9644/C9648/P6408 Pin Descriptions
Pin
Names Pin
Type Pin
Description Circuit
Number Pin
Numbers Share
Pins
P0.0-P0.7 I/O Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Port0 can be individually
configured as external interrupt inputs. Pull-up
resistors are assignable by software.
B36-29
(30-23) INT2
P1.0-P1.7 I/O Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Pull-up resistors are
assignable by software.
B28-21
(22-15) –
P2.0-P2.7 I/O Bit-programmable I/O port for Schmitt trigger input
or open-drain output. Port2 can be individually
configured as external interrupt inputs. Pull-up
resistors are assignable by software.
B3-10
(41-44, 1-4) INT0
P3.0-P3.3 I/O Bit-programmable I/O port for Schmitt trigger input,
open-drain or push-pull output. P3.3 can be used to
system clock output(CLO) pin.
C2, 1, 42, 41
(40-37) P3.3/CL
O
P4.0-P4.3 I/O Bit-programmable I/O port for Schmitt trigger input
or open-drain output or push-pull output. Port4 can
be individually configured as external interrupt
inputs. In output mode, pull-up resistors are
assignable by software. But in input mode, pull-up
resistors are fixed.
D16, 17, 19, 20
(10, 11, 13,
14)
INT1
D+/PS2
D-/PS2 I/O Programmable port for USB
interface or PS2 interface. –40-39 (36-35) –
3.3 VOUT –3.3 V output from internal voltage regulator –38 (34) –
XIN, XOUT –System clock input and output pin (crystal/ceramic
oscillator, or external clock source) –14, 13
(8, 7) –
INT0
INT1
INT2
IExternal interrupt for bit-programmable port0, port2
and port4 pins when set to input mode. –3-10, 16,17,
19, 20, 29-36
(30-23, 41-44,
1-4, 10, 11,
13, 14)
PORT2/
PORT4/
PORT0
RESET IRESET signal input pin. Input with internal pull-up
resistor. A18 (12) –
TEST ITest signal input pin (for factory use only;
connected to VSS)–15 (9) –
VDD –Power input pin –11 (5) –
VSS –Ground input pin –12, (6) –
NC –No connection – 37
(31,32, 33) –
NOTE: Pin numbers shown in parenthesis '( )' are for the 44-QFP package; others are for the 42-SDIP package.
S3C9644/C9648/P9648 PRODUCT OVERVIEW
1-7
PIN CIRCUITS
Table 1-2. Pin Circuit Assignments for the S3C9644/C9648/P6408
Circuit Number Circuit Type S3C9644/C9648/P6408 Assignments
AIRESET signal input
BI/O Ports 0, 1, and 2
CI/O Port 3
DI/O Port 4
VDD
PULL-UP
RESISTOR
IN Noise
Filter
Figure 1-4. Pin Circuit Type A (RESET)
Output
Disable
Input
Data MUX D0
D1
Mode Input Data
Input
Output D0
D1
I/O
Pull-Up Enable
VSS
VDD
Pull-Up
Resistor
Output
Data
Figure 1-5. Pin Circuit Type B (Ports 0, 1 and 2)
PRODUCT OVERVIEW S3C9644/C9648/P9648
1-8
VDD
Open
Drain
Output
Disable
Input
Data
Mode Input Data
Input
Output D0
D1
I/O
Output
Data
VSS
MUX D0
D1
Figure 1-6. Pin Circuit Type C (Port 3)
S3C9644/C9648/P9648 PRODUCT OVERVIEW
1-9
VDD
Open
Drain
Output
Disable
Input
Data
Mode Input Data
Input
Output D0
D1
I/O
Output
Data
VSS
Pull-Up
Enable
VDD
Pull-Up
Resistor
MUX D0
D1
Figure 1-7. Pin Circuit Type D (Port 4)
PRODUCT OVERVIEW S3C9644/C9648/P9648
1-10
APPLICATION CIRCUIT
XOUT
KEYBOARD
MATRIX
0
1
2
3
15
0
1
2
3
7
XIN
VSS1
VDD
5V
Port 3
Port 0Port 1Port 2
RESET
H
O
S
T
DP
DM
S3C9644
S3C9648
S3P9648
5V
Port 4
D+/PS2
D-/PS2
NOTE: Port4 can use expend keyboard MATRIX.
D+/PS2, D-/PS2 can use PS2 keyboard interface (see PS2CONINT, page 4-25).
Port 4.2, 4.3 can use PS2 mouse interface.
Port 3 can use LED direct drive.
Figure 1-8. Keyboard Application Circuit Diagram
S3C9644/C9648/P9648 ELECTRICAL DATA
12-1
12 ELECTRICAL DATA
OVERVIEW
In this section, the following S3C9644/C9648/P9648 electrical characteristics are presented in tables and graphs:
—Absolute maximum ratings
—D.C. electrical characteristics
—Input/Output capacitance
—A.C. electrical characteristics
—Input timing for external interrupt (Ports 0, 2 and 4) D+/PS2, D-/PS2 : PS2 Mode Only
—Input timing for RESET
—Oscillator characteristics
—Oscillation stabilization time
—Clock timing measurement points at XIN
—Data retention supply voltage in Stop mode
—Stop mode release timing when initiated by a reset
—Stop mode release timing when initiated by an external interrupt
—Characteristic curves
ELECTRICAL DATA S3C9644/C9648/P9648
12-2
Table 12-1. Absolute Maximum Ratings
(TA = 25°C)
Parameter Symbol Conditions Rating Unit
Supply Voltage VDD –– 0.3 to + 6.5 V
Input Voltage VIN All input ports – 0.3 to VDD + 0.3 V
Output Voltage VOAll output ports – 0.3 to VDD + 0.3 V
Output Current High IOH One I/O pin active – 18 mA
All I/O pins active – 60
Output Current Low IOL One I/O pin active + 30 mA
Total pin current for ports 3 + 100
Total pin current for ports 0, 1, 2, 4 + 100
Operating
Temperature TA–– 40 to + 85 °C
Storage
Temperature TSTG –– 65 to + 150 °C
S3C9644/C9648/P9648 ELECTRICAL DATA
12-3
Table 12-2. D.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter Symbol Conditions Min Typ Max Unit
Operating Voltage VDD fOSC = 6 MHz
(instruction clock = 1 MHz) 4.0 5.0 5.25 V
Input High Voltage VIH1 All input pins except VIH2 0.8 VDD –VDD V
VIH2 XIN VDD – 0.5 VDD
VIH3 RESET 0.5VDD
Input Low Voltage VIL1 All input pins except VIL2 – – 0.2 VDD V
VIL2 XIN 0.4
VIL2 RESET 0.5VDD
Output High
Voltage VOH IOH = – 200 µA; All output
ports except ports 0, 1 and 2,
D+, D–
VDD – 1.0 – – V
Output Low Voltage VOL IOL = 1 mA
All output port except D+, D– – – 0.4 V
Output Low Current IOL VOL = 3V
Port 3 only
8 15 23 mA
Input High
Leakage Current ILIH1 (3) VIN = VDD
All inputs except ILIH2
except D+, D–
––3µA
ILIH2 (3) VIN = VDD
XIN, XOUT, RESET – – 20 µA
Input Low
Leakage Current ILIL1 (3) VIN = 0 V
All inputs except ILIL2
except D+, D–
– – – 3 µA
ILIL2 (3) VIN = 0 V
XIN, XOUT, RESET – – – 20 µA
ELECTRICAL DATA S3C9644/C9648/P9648
12-4
Table 12-2. D.C. Electrical Characteristics (continued)
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter Symbol Conditions Min Typ Max Unit
Output High
Leakage Current ILOH (1) VOUT = VDD
All I/O pins and output pins
except D+, D–
––3µA
Output Low
Leakage Current ILOL (1) VOUT = 0 V
All I/O pins and output pins
except D+, D–
– – – 3 µA
Pull-up Resistors RL1 VIN = 0 V
Ports 0, 1, 2, 4.2-3, Reset 25 50 100 kΩ
RL2 VIN = 0 V; P4.0-1 2.4
Supply Current (2) IDD1 Normal operation mode
6 MHz CPU clock –5.5 12 mA
IDD2 Idle mode; 6 MHz oscillator 2.2 5mA
IDD3 Stop mode 180 300 µA
NOTES:
1. Except XIN and XOUT.
2. Supply current does not include current drawn through internal pull-up resistors or external output current loads.
3. When USB Mode Only in 4.2 V to 5.25 V, D+ and D– satisfy the USB spec 1.0.
S3C9644/C9648/P9648 ELECTRICAL DATA
12-5
Table 12-3. Input/Output Capacitance
(TA = – 40 °C to + 85 °C, VDD = 0 V)
Parameter Symbol Conditions Min Typ Max Unit
Input
Capacitance CIN f = 1 MHz; Unmeasured pins
are connected to VSS
– – 10 pF
Output
Capacitance COUT
I/O Capacitance CIO
Table 12-4. A.C. Electrical Characteristics
(TA = – 40 °C to + 85 °C, VDD = 4.0 V to 5.25 V)
Parameter Symbol Conditions Min Typ Max Unit
Interrupt Input
High, Low Width tINTH, tINTL P0, P2 and P4 – 200 – ns
RESET Input
Low Width tRSL RESET 10 – – µs
tINTL tINTH
0.8 VDD
0.2 VDD
Figure 12-1. Input timing for external interrupt (Ports 0, 2, and 4)
RESET
tRSL
0.5VDD
Figure 12-2. Input Timing for RESET
ELECTRICAL DATA S3C9644/C9648/P9648
12-6
Table 12-5. Oscillator Characteristics
(TA = – 40°C + 85°C, VDD = 4.0 V to 5.25 V)
Oscillator Clock Circuit Test Condition Min Typ Max Unit
Main crystal Main
ceramic (fOSC)
C2
XIN
XOUT
C1
Oscillation frequency –6.0 –MHz
External clock XIN
XOUT
Oscillation frequency –6.0 –
Table 12-6. Oscillation Stabilization Time
(TA = – 40°C + 85°C, VDD = 4.0 V to 5.25 V)
Oscillator Test Condition Min Typ Max Unit
Main Crystal fOSC = 6.0 MHz – – 10 ms
Main Ceramic (Oscillation stabilization occurs when VDD is equal to
the minimum oscillator voltage range.)
Oscillator
Stabilization Wait
Time
tWAIT stop mode release time by a reset –216/
fOSC
–
tWAIT stop mode release time by an interrupt –(note) –
NOTE: The oscillator stabilization wait time, tWAIT, is determined by the setting in the basic timer control register, BTCON.
S3C9644/C9648/P9648 ELECTRICAL DATA
12-7
Table 12-7. Data Retention Supply Voltage in Stop Mode
(TA = – 40°C to + 85°C)
Parameter Symbol Conditions Min Typ Max Unit
Data Retention
Supply Voltage VDDDR Stop mode 2.0 – 6 V
Data Retention
Supply Current IDDDR Stop mode; VDDDR = 2.0 V – – 300 µA
tXL tXH
VDD 0.5V
0.4V
XIN
1/fOSC
Figure 12-3. Clock Timing Measurement Points at XIN
ELECTRICAL DATA S3C9644/C9648/P9648
12-8
tWAIT
VDD
RESET
Execution Of
Stop Instruction
VDDDR
Data Retention
Mode
Stop Mode
Internal Reset
Operation Idle Mode
(Basic Timer
Active)
0.5 VDD
0.5 VDD
Normal
Operating
Mode
∼
∼
∼
∼
∼
∼
∼
∼
Figure 12-4. Stop Mode Release Timing When Initiated by a Reset
tWAIT
VDD
External
Interrupt
Execution Of
Stop Instruction
VDDDR
Data Retention Mode
Stop Mode
Idle Mode
(Basic Timer
Active)
0.8 VDD
0.2 VDD
Normal
Operating
Mode
∼
∼
∼
∼
∼
∼
∼
∼
Figure 12-5. Stop Mode Release Timing When Initiated by an External Interrupt
S3C9644/C9648/P9648 ELECTRICAL DATA
12-9
Table 12-8. Low Speed USB Electrical Characteristics
(TA = – 40°C to + 85°C, Voltage Regulator Output V33out = 2.8 V to 3.5 V, typ 3,3 V)
Parameter Symbol Conditions Min Max Unit
Transition Time:
Rise Time Tr CL = 50 pF 75 – ns
CL = 350 pF – 300
Fall Time Tf CL = 50 pF 75 –
CL = 350 pF – 300
Rise/Fall Time Matching Trfm (Tr/Tf) CL = 50 pF 80 120 %
Output Signal Crossover Voltage Vcrs CL = 50 pF 1.3 2.0 V
Voltage Regulator Output Voltage V33OUT with V33OUT to GND 0.1 µF
capacitor 2.8 3.5 V
Measurement
Points
90% 90%
Tr Tf
10%
D.U.T R1
S/W
2.8VTest
Point
CL
R1 = 15 K Ω
R2 = 1.5 K Ω
CL = 50pF-350pF
DM: S/W ON
DP: S/W OFF
R2 10%
Figure 12-6. USB Data Signal Rise and Fall Time
Vcrs MAX: 2.0 V
MIN: 1.3 V
3.3 V
0 V
DP
DM
Figure 12-7. USB Output Signal Crossover Point Voltage
S3C9644/C9648/P9648 MECHANICAL DATA
13-1
13 MECHANICAL DATA
OVERVIEW
The S3C9644/C9648/P9648 is available in a 42-pin SDIP package (Samsung: 42-SDIP-600) and a 44-pin QFP
package (44-QFP-1010B). Package dimensions are shown in Figures 13-1 and 13-2.
0-15 °
15.24
0.25 +0.1
– 0.05
0.51MIN 3.50 ± 0.2
3.30 ± 0.3 5.08MAX
39.10 ± 0.2
39.50 MAX
1.00 ± 0.1
0.50 ± 0.1
(1.77) 1.778
14.00 ³ 0.2
#1 #21
#42 #22
40-SDIP-600
Figure 13-1. 42-Pin SDIP Package Mechanical Data (42-SDIP-600 )
MECHANICAL DATA S3C9644/C9648/P9648
13-2
NOTE: Dimensions are in millimeters.
44-QFP-1010B
13.20 ± 0.3
#44
(1.00)
#1
13.20 ± 0.3
10.00 ± 0.2
0.35 +0.10
- 0.05
0.10 MAX
0.15+0.10
- 0.05
0−8°
0.05 MIN
2.05 ± 0.10
2.30 MAX
0.80±0.20
0.80
10.00 ± 0.2
Figure 13-2. 44-Pin QFP Package Mechanical Data (44-QFP-1010B)
S3C9644/C9648/P9648 S3P9648 OTP
14-1
14 S3P9648 OTP
OVERVIEW
The S3P9648 single-chip CMOS microcontroller is the OTP (One Time Programmable) version of the
S3C9644/C9648 microcontroller. It has an on-chip OTP ROM instead of masked ROM. The EPROM is accessed
by serial data format.
The S3P9648 is fully compatible with the S3C9644/C9648, both in function and in pin configuration. Because of
its simple programming requirements, the S3P9648 is ideal for use as an evaluation chip for the
S3C9644/C9648.
P3.1
P3.0
INT0 / P2.0
INT0 / P2.1
INT0 / P2.2
INT0 / P2.3
INT0 / P2.4
INT0 / P2.5
SDAT/INT0 / P2.6
SCLK /INT0 / P2.7
VDD/VDD
VSS /VSS
XOUT/XOUT
XIN /XIN
TEST/TEST
INT1 / P4.0
INT1 / P4.1
RESETRESET / RESET
INT1 / P4.2
INT1 / P4.3
P1/7
S3P9648
42-SDIP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
P3.2
P3.3/CLO
D+
D-
3.3 VOUT
NC
P0.0 / INT2
P0.1 / INT2
P0.2 / INT2
P0.3 / INT2
P0.4 / INT2
P0.5 / INT2
P0.6 / INT2
P0.7 / INT2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
Figure 14-1. S3P9648 Pin Assignments (42-SDIP Package)
S3P9648 OTP S3C9644/C9648/P9648
14-2
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P4.3/INT1
P4.2/INT1
RESET/RESETRESET
3.3 VOUT
D-/PS2
D+/PS2
P3.3/CLO
P3.2
P3.1
P3.0
P2.0/INT0
P2.1/INT0
P2.2/INT0
P2.3/INT0
NC
NC
NC
P0.0/INT2
P0.1/INT2
P0.2/INT2
P0.3/INT2
P0.4 /INT2
P0.5/INT2
P0.6/INT2
P0.7/INT2
P2.4/INT0
P2.5/INT0
P2.6/INT0/SDAT
P2.7/INT0/SCLK
VDD/VDD
VSS/VSS
XOUT/XOUT
XIN/XIN
TEST/TEST
P4.0/INT1
P4.1/INT1
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
S3C9648
44-QFP
(Top View)
1
2
3
4
5
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
Figure 14-2. S3P9648 Pin Assignments (44-QFP Package)
S3C9644/C9648/P9648 S3P9648 OTP
14-3
Table 14-1. Descriptions of Pins Used to Read/Write the EPROM
Main Chip During Programming
Pin Name Pin Name Pin No. I/O Function
P2.6 SDAT 9 (3) I/O Serial DATa Pin (Output when reading, Input
when writing) Input and Push-pull Output Port
can be assigned
P2.7 SCLK 10 (4) I/O Serial CLocK Pin (Input Only Pin)
TEST TEST 15 (9) IChip Initialization and EPROM Cell Writing
Power Supply Pin (Indicates OTP Mode
Entering) When writing 12.5 V is applied and
when reading.
RESET RESET 18 (12) I0 V: OTP write and test mode
5 V: Operating mode
VDD / VSS VDD / VSS 11(5)/12(6) –Logic Power Supply Pin.
NOTE: ( ) means 44 QFP package.
Table 14-2. Comparison of S3P9648 and S3C9644/C9648 Features
Characteristic S3P9648 S3C9644/C9648
Program Memory 8-Kbyte EPROM 8-Kbyte mask ROM
Operating Voltage (VDD)4.0 V to 5.25 V 4.0 V to 5.25 V
OTP Programming Mode VDD = 5 V, VPP (RESET) = 12.5 V
Pin Configuration 42 SDIP/44 QFP 42 SDIP/44 QFP
EPROM Programmability User Program 1 time Programmed at the factory
OPERATING MODE CHARACTERISTICS
When 12.5 V is supplied to the VPP (RESET) pin of the S3P9648, the EPROM programming mode is entered.
The operating mode (read, write, or read protection) is selected according to the input signals to the pins listed in
Table 14-3 below.
Table 14-3. Operating Mode Selection Criteria
VDD VPP
(RESET)REG/
MEM ADDRESS
(A15-A0) R/WMODE
5 V 5 V 00000H 1EPROM read
12.5 V 00000H 0EPROM program
12.5 V 00000H 1EPROM verify
12.5 V 10E3FH 0EPROM read protection
NOTE: "0" means Low level; "1" means High level.
S3P9648 OTP S3C9644/C9648/P9648
14-4
START
Address= First Location
VDD=5V, VPP=12.5V
x = 0
Program One 1ms Pulse
Increment X
x = 10
Verify 1 Byte
Last Address
VDD = VPP= 5 V
Compare All Byte
Device Passed
Increment Address
Verify Byte
Device Failed
PASS
FAIL
NO
FAIL
YES
FAIL
NO
Figure 14-3. OTP Programming Algorithm
S3C9644/C9648/P9648 S3P9648 OTP
14-5
Table 14-4. D.C. Electrical Characteristics
(TA = – 40_C to + 85_C, VDD = 4.0 V to 5.25 V)
Parameter Symbol Conditions Min Typ Max Unit
Supply Current
(note) IDD1 Normal mode;
6 MHz CPU clock –5.5 12 mA
IDD2 Idle mode;
6 MHz CPU clock 2.2 5
IDD3 Stop mode 180 300 µA
NOTE: Supply current does not include current drawn through internal pull-up resistors or external output current loads.
