Revised July 2003 DM93S41 4-Bit Arithmetic Logic Unit General Description The DM93S41 4-bit arithmetic logic units can perform all the possible 16 logic operations on two variables and a variety of arithmetic operations; the Add and Subtract modes are the most important. Ordering Code: Order Number Package Number DM93S41N N24A Package Description 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Logic Symbols Connection Diagram Active LOW Operands Pin Descriptions Active HIGH Operands Pin Name A0-A3, B0-B3 (c) 2003 Fairchild Semiconductor Corporation DS009805 Description Operand Inputs (Active LOW) S0-S3 Function Select Inputs M Mode Control Input Cn Carry Input F0-F3 Function Outputs (Active LOW) A=B Comparator Output G Carry Generate Output (Active LOW) P Carry Propagate Output (Active LOW) Cn+4 Carry Output www.fairchildsemi.com DM93S41 4-Bit Arithmetic Logic Unit October 1988 DM93S41 Functional Description The A = B output from the DM93S41 goes HIGH when all four Fn outputs are HIGH and can be used to indicate logic equivalence over four bits when the unit is in the subtract mode. The A = B output is open-collector and can be wiredAND with the other A = B outputs to give a comparison for more than four bits. The A = B signal can also be used with the Cn+4 signal to indicate A > B and A < B. The DM93S41 is a 4-bit high speed parallel arithmetic logic unit (ALU). Controlled by the four Function Select inputs (S0-S3) and the Mode Control input (M), it can perform all the 16 possible operations or 16 different arithmetic operations on active HIGH or active LOW operands. The Function Table below lists these operations. When the Mode Control input (M) is HIGH, all internal carries are inhibited and the device performs logic operations on the individual bits as listed. When the Mode Control input is LOW, the carries are enabled and the device performs arithmetic operations on the two 4-bit words. The device incorporates full internal carry lookahead and provides for either ripple carry between devices using the Cn+4 output, or for carry lookahead between packages using the signals P (Carry Propagate) and G (Carry Generate). P and G are not affected by carry in. When speed requirements are not stringent, the DM93S41 can be used in a simple ripple carry mode by connecting the Carry output (Cn+4) signal to the Carry input (Cn) of the next unit. For super high speed operation the Schottky DM93S41 should be used in conjunction with the '42 carry lookahead circuit. The Function Table lists the arithmetic operations that are performed without a carry in. An incoming carry adds a one to each operation. Thus select code LHHL generates A minus B minus 1 (2s complement notation) without a carry in and generates A minus B when a carry is applied. Because subtraction is actually performed by complementary addition (1s complement), a carry out means borrow; thus a carry is generated when there is no underflow and no carry is generated when there is underflow. As indicated the '41 can be used with either active LOW inputs producing active LOW outputs or with active HIGH inputs producing active HIGH outputs. For either case the table lists the operations that are performed to the operands labeled inside the logic symbol. Function Table S3 Mode Select Active LOW Inputs Inputs & Outputs & Outputs Logic Arithmetic (Note 2) Logic Arithmetic (Note 2) S2 S1 (M = H) S0 Active HIGH Inputs (M = L) (Cn = L) (M = H) (M = L) (Cn = H) L L L L A A minus 1 A A L L L H AB AB minus 1 A+B A+B L L H L A+B AB minus 1 AB A+B L L H H Logic 1 minus 1 Logic 0 minus 1 L H L L A+B A plus (A + B) AB A plus AB L H L H B AB plus (A + B) B (A +B) plus AB L H H L AB A minus B minus 1 AB A minus B minus 1 L H H H A+B A+B AB AB minus 1 A plus AB H L L L AB A plus (A + B) A+B H L L H AB A plus B AB A plus B H L H L B AB plus (A + B) B (A + B) plus AB H L H H A+B A+B AB AB minus 1 H H L L Logic 0 A plus A (Note 1) Logic 1 A plus A (Note 1) H H L H AB AB plus A A+B (A + B) plus A H H H L AB AB minus A A+B (A + B) plus A H H H H A A A A minus 1 H = HIGH Voltage Level L = LOW Voltage Level Note 1: Each bit is shifted to the next more significant position Note 2: Arithmetic operations expressed in 2s complement notation www.fairchildsemi.com 2 Symbol Other Input Same Bit Other Data Input Output Under Apply Apply Apply Apply Under Test 4.5V GND 4.5V GND Test Fi tPLH, tPHL Ai Bi None Remaining A to B Cn tPLH, tPHL Bi Ai None Remaining A to B Cn Fi tPLH, tPHL Ai Bi None Cn Remaining A and B Fi + 1 tPLH, tPHL Bi Ai None Cn Remaining A and B Fi + 1 tPLH, tPHL A B None None Remaining A and B, Cn P tPLH, tPHL B A None None Remaining A and B, Cn P tPLH, tPHL A None B Remaining B Remaining A, Cn G tPLH, tPHL B None A Remaining B Remaining A, Cn G tPLH, tPHL A None B Remaining B Remaining A, Cn Cn + 4 tPLH, tPHL B None A Remaining B Remaining A, Cn Cn + 4 tPLH, tPHL Cn None None All A All B Any F or Cn + 4 TABLE 2. DIFF MODE TEST Function Inputs: S1 = S2 = 4.5V,S0 = S3 = M = 0V Input Symbol tPLH, tPHL Other Input Same Bit Other Data Inputs Output Under Apply Apply Apply Apply Under Test 4.5V GND 4.5V GND Test A None B Remaining A Remaining B, Cn Fi tPLH, tPHL B A None Remaining A Remaining B, Cn Fi tPLH, tPHL Ai None Bi Remaining B, Cn Remaining A Fi + 1 tPLH, tPHL Bi Ai None Remaining B, Cn Remaining A Fi + 1 tPLH, tPHL A None B None Remaining A and B, Cn P tPLH, tPHL B A None None Remaining A and B, Cn P tPLH, tPHL A B None None Remaining A and B, Cn G tPLH, tPHL B None A None Remaining A and B, Cn G tPLH, tPHL A None B Remaining A Remaining B, Cn A=B tPLH, tPHL B A None Remaining A Remaining B, Cn A=B tPLH, tPHL A B None None Remaining A and B, Cn Cn + 4 tPLH, tPHL B None A None Remaining A and B, Cn Cn + 4 tPLH, tPHL Cn None None All A and B None Cn + 4 TABLE 3. LOGIC MODE TEST Function Inputs: S1 = S2 = M = 4.5V, S0 = S3 = 0V Input Symbol Other Input Same Bit Other Data Inputs Output Under Apply Apply Apply Apply Under Test 4.5V GND 4.5V GND Test tPLH, tPHL A B None None Remaining A and B, Cn Any F tPLH, tPHL B A None None Remaining A and B, Cn Any F 3 www.fairchildsemi.com DM93S41 TABLE 1. SUM MODE TEST Function Inputs: S0 = S3 = 4.5V, S1 = S2 = M = 0V Input DM93S41 Logic Diagram www.fairchildsemi.com 4 Supply Voltage Note 3: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation. 7V Input Voltage: 5.5V 0C to +70C Operating Free Air Temperature Range -65C to +150C Storage Temperature Range Recommended Operating Conditions Symbol Parameter Min Nom Max 4.75 5 5.25 Units VCC Supply Voltage VIH HIGH Level Input Voltage VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current -1 mA IOL LOW Level Output Current 20 mA TA Free Air Operating Temperature 70 C V 2 V 0 Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted) Symbol Parameter Conditions VI Input Clamp Voltage VCC = Min, II = - 18 mA VOH HIGH Level VCC = Min, IOH = Max Output Voltage VIL = Max LOW Level VCC = Min, IOL = Max VOL Output Voltage VIH = Min II Input Current @ Max Input Voltage VCC = Max, VI = 5.5V Min 2.7 Typ (Note 4) Max Units -1.2 V 3.4 0.35 V 0.5 V 1 mA IIH HIGH Level Input Current VCC = Max, VI = 2.7V 50 A IIL LOW Level Input Current VCC = Max, VI = 0.5V -1.6 mA IOS Short Circuit Output Current VCC = Max (Note 5) -100 mA ICCL Supply Current VCC = Max 150 mA 140 mA -40 M, S0-S3 = 4.5V All Other Inputs = 0V ICCH Supply Current VCC = Max Cn, B0-B3 = GND All Other Inputs = 4.5V Note 4: All typicals are at VCC = 5V, TA = 25C. Note 5: Not more than one output should be shorted at a time, and the duration should not exceed one second. 5 www.fairchildsemi.com DM93S41 Absolute Maximum Ratings(Note 3) DM93S41 Switching Characteristics VCC = +5.0V, TA = +25C CL = 15 pF Symbol Parameter Conditions RL = 280 Min M = GND tPLH Propagation Delay tPHL Cn to Cn + 4 12 tPLH Propagation Delay tPHL Cn to F tPLH Propagation Delay M, S1, S2 = GND 14 tPHL An or Bn to G S0, S3 = 4.5V 14 tPLH Propagation Delay M, S0, S3 = GND 15 tPHL An or Bn to G S1, S2 = 4.5V 15 tPLH Propagation Delay M, S1, S2 = GND 14 tPHL An or Bn to P S0, S3 = 4.5V 14 tPLH Propagation Delay M, S0, S3 = GND 15 tPHL An or Bn to P S1, S2 = 4.5V 15 tPLH Propagation Delay M, S1, S3 = GND 20 tPHL Ai or Bi to Fi S0, S3 = 4.5V 20 tPLH Propagation Delay M, S0, S3 = GND 21 tPHL Ai or Bi to Fi S1, S2 = 4.5V 21 tPLH Propagation Delay M, S1, S2 = GND 24 tPHL Ai or Bi to Fi + 1 S0, S3 = 4.5V 24 tPLH Propagation Delay M, S0, S3 = GND 25 tPHL Ai or Bi to Fi + 1 S1, S2 = 4.5V 25 tPLH Propagation Delay M = 4.5V 20 tPHL An or Bn to F tPLH Propagation Delay M, S1, S2 = GND 18.5 tPHL An or Bn to Cn + 1 S0, S3 = 4.5V 18.5 tPLH Propagation Delay M, S0, S3 = GND 23 tPHL An or Bn to Cn + 1 S1, S2 = 4.5V 23 tPLH Propagation Delay M, S0, S3 = GND 23 tPHL An or Bn to A = B S1, S2 = 4.5V 23 12 M = GND 12 12 20 RL = 400 to 5.0V www.fairchildsemi.com 6 Units Max ns ns ns ns ns ns ns ns ns ns ns ns ns ns DM93S41 4-Bit Arithmetic Logic Unit Physical Dimensions inches (millimeters) unless otherwise noted 24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-011, 0.600" Wide Package Number N24A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. 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