1
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
MX29GL256E DATASHEET
The MX29GL256E product family is not recommended for new designs, while MX29GL256F
family is suggested to replace it. Please refer to MX29GL256F datasheet for specications
and ordering information, or contact your local sales representative for additional support.
2
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FEATURES
GENERAL FEATURES
• Power Supply Operation
- 2.7 to 3.6 volt for read, erase, and program operations
- MX29GL256E H/L: VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC
- MX29GL256E U/D: VI/O=1.65V~3.6V for Input/Output
• Byte/Word mode switchable
- 33,554,432 x 8 / 16,777,216 x 16
• 64KW/128KB uniform sector architecture
- 256 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security
- Features factory locked and identiable, and customer lockable
• Advanced sector protection function (Solid and Password Protect)
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit : Vcc ≤ VLKO
• Compatible with JEDEC standard
- Pinout and software compatible to single power supply Flash
• Deep power down mode
PERFORMANCE
• High Performance
- Fast access time:
- MX29GL256E H/L: 100ns (VCC=2.7~3.6V), 90ns (VCC=3.0~3.6V)
- MX29GL256E U/D: 110ns (VCC=2.7~3.6V, V I/O=1.65 to Vcc)
- Page access time:
- MX29GL256E H/L: 25ns
- MX29GL256E U/D: 30ns
- Fast program time: 11us/word
- Fast erase time: 0.6s/sector
• Low Power Consumption
- Low active read current: 30mA (typical) at 5MHz
- Low standby current: 30uA (typical)
• Typical 100,000 erase/program cycle
• 20 years data retention
SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being
erased
- Suspends sector program operation to read data from another sector which is not being program
• Status Reply
- Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface (CFI)
HARDWARE FEATURES
• Ready/Busy# (RY/BY#) Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset (RESET#) Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability
SINGLE VOLTAGE 3V ONLY FLASH MEMORY
The MX29GL256E product family is not recommended for new designs, while MX29GL256F
family is suggested to replace it. Please refer to MX29GL256F datasheet for specications
and ordering information, or contact your local sales representative for additional support.
3
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
PIN CONFIGURATION
56 TSOP
64 FBGA/64 LFBGA
A B C D E F G H
NC
8
7
6
5
4
3
2
1
A22 A23 VIO NCNC NC
A13 A12 A14 A15 A16 BYTE# Q15/
A-1
A9 A8 A10 A11 Q7 Q14 Q13 Q6
WE# A21 A19
RES-
ET# Q5 Q12 VCC Q4
WP#/
ACC A18 A20 Q2 Q10 Q11
RY/
BY#
A7 A17 A6 A5 Q0 Q8 Q9 Q1
Q3
A3 A4 A2 A1 A0 CE# OE# GND
GND
GND
NC NC NC NC NC VIO NC NC
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
A21
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NC
NC
A16
BYTE#
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
V
CC
Q11
Q3
Q10
Q2
Q9
Q1
Q8
Q0
OE#
GND
CE#
A0
NC
V
I/O
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
PACKAGE
• 56-Pin TSOP
• 64-Ball FBGA (10mm x 13mm)
• 64-Ball LFBGA (11mm x 13mm)
• 70-Pin SSOP
• All devices are RoHS Compliant
4
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
70 SSOP
PIN DESCRIPTION
SYMBOL PIN NAME
A0~A23 Address Input
Q0~Q14 Data Inputs/Outputs
Q15/A-1 Q15(Word Mode)/LSB addr(Byte Mode)
CE# Chip Enable Input
WE# Write Enable Input
OE# Output Enable Input
RESET# Hardware Reset Pin, Active Low
WP#/ACC* Hardware Write Protect/Programming
Acceleration input
RY/BY# Ready/Busy Output
BYTE# Selects 8 bits or 16 bits mode
VCC +3.0V single power supply
GND Device Ground
NC Pin Not Connected Internally
VI/O Power Supply for Input/Output
LOGIC SYMBOL
16 or 8
Q0-Q15
(A-1)
RY/BY#
A0-A23
CE#
OE#
WE#
RESET#
WP#/ACC
BYTE#
VI/O
24
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
A20
A21
A18
A17
OE#
A6
A5
A4
A3
A2
A1
A0
BYTE#
GND
NC
NC
NC
NC
NC
NC
GND
NC
CE#
GND
NC
A7
Q0
Q8
Q1
Q9
Q2
Q10
Q3
Q11
NC
A19
A8
A15
A10
A11
A12
A13
A14
A9
A16
WE#
NC
A22
A23
GND
NC
NC
WP#/ACC
NC
NC
NC
GND
RESET#
GND
GND
Q15/A-1
Q7
Q14
Q6
Q13
Q5
Q12
Q4
VCC
VCC
Notes:
1. WP#/ACC has internal pull up.
2. For MX29GL256E H/L VI/O voltage must tight with VCC.
VI/O = VCC =2.7V~3.6V.
5
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
BLOCK DIAGRAM
CONTROL
INPUT
LOGIC
PROGRAM/ERASE
HIGH VOLTAGE
WRITE
STATE
MACHINE
(WSM)
STATE
REGISTER
FLASH
ARRAY
X-DECODER
ADDRESS
LATCH
AND
BUFFER Y-PASS GATE
Y-DECODER
ARRAY
SOURCE
HV
COMMAND
DATA
DECODER
COMMAND
DATA LATCH
I/O BUFFER
PGM
DATA
HV
PROGRAM
DATA LATCH
SENSE
AMPLIFIER
Q0-Q15/A-1
A0-AM
AM: MSB address
CE#
OE#
WE#
RESET#
BYTE#
WP#/ACC
6
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
BLOCK DIAGRAM DESCRIPTION
The block diagram on Page 5 illustrates a simplied architecture of this device. Each block in the block diagram
represents one or more circuit modules in the real chip used to access, erase, program, and read the memory
array.
The "CONTROL INPUT LOGIC" block receives input pins CE#, OE#, WE#, RESET#, BYTE#, and WP#/ACC.
It creates internal timing control signals according to the input pins and outputs to the "ADDRESS LATCH AND
BUFFER" to latch the external address pins A0-AM(A23). The internal addresses are output from this block to
the main array and decoders composed of "X-DECODER", "Y-DECODER", "Y-PASS GATE", AND "FLASH AR-
RAY". The X-DECODER decodes the word-lines of the ash array, while the Y-DECODER decodes the bit-lines
of the ash array. The bit lines are electrically connected to the "SENSE AMPLIFIER" and "PGM DATA HV" se-
lectively through the Y-PASS GATES. SENSE AMPLIFIERS are used to read out the contents of the ash memo-
ry, while the "PGM DATA HV" block is used to selectively deliver high power to bit-lines during programming. The
"I/O BUFFER" controls the input and output on the Q0-Q15/A-1 pads. During read operation, the I/O BUFFER
receives data from SENSE AMPLIFIERS and drives the output pads accordingly. In the last cycle of program
command, the I/O BUFFER transmits the data on Q0-Q15/A-1 to "PROGRAM DATA LATCH", which controls the
high power drivers in "PGM DATA HV" to selectively program the bits in a word or byte according to the user in-
put pattern.
The "PROGRAM/ERASE HIGH VOLTAGE" block comprises the circuits to generate and deliver the necessary
high voltage to the X-DECODER, FLASH ARRAY, and "PGM DATA HV" blocks. The logic control module com-
prises of the "WRITE STATE MACHINE, WSM", "STATE REGISTER", "COMMAND DATA DECODER", and
"COMMAND DATA LATCH". When the user issues a command by toggling WE#, the command on Q0-Q15/A-1
is latched in the COMMAND DATA LATCH and is decoded by the COMMAND DATA DECODER. The STATE
REGISTER receives the command and records the current state of the device. The WSM implements the in-
ternal algorithms for program or erase according to the current command state by controlling each block in the
block diagram.
ARRAY ARCHITECTURE
The main ash memory array can be organized as Byte mode (x8) or Word mode (x16). The details of the ad-
dress ranges and the corresponding sector addresses are shown in Table 1.
7
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Table 1. MX29GL256E SECTOR ARCHITECTURE
BLOCK STRUCTURE
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA0 00000000 000000h-00FFFFh
128 64 SA1 00000001 010000h-01FFFFh
128 64 SA2 00000010 020000h-02FFFFh
128 64 SA3 00000011 030000h-03FFFFh
128 64 SA4 00000100 040000h-04FFFFh
128 64 SA5 00000101 050000h-05FFFFh
128 64 SA6 00000110 060000h-06FFFFh
128 64 SA7 00000111 070000h-07FFFFh
128 64 SA8 00001000 080000h-08FFFFh
128 64 SA9 00001001 090000h-09FFFFh
128 64 SA10 00001010 0A0000h-0AFFFFh
128 64 SA11 00001011 0B0000h-0BFFFFh
128 64 SA12 00001100 0C0000h-0CFFFFh
128 64 SA13 00001101 0D0000h-0DFFFFh
128 64 SA14 00001110 0E0000h-0EFFFFh
128 64 SA15 00001111 0F0000h-0FFFFFh
128 64 SA16 00010000 100000h-10FFFFh
128 64 SA17 00010001 110000h-11FFFFh
128 64 SA18 00010010 120000h-12FFFFh
128 64 SA19 00010011 130000h-13FFFFh
128 64 SA20 00010100 140000h-14FFFFh
128 64 SA21 00010101 150000h-15FFFFh
128 64 SA22 00010110 160000h-16FFFFh
128 64 SA23 00010111 170000h-17FFFFh
128 64 SA24 00011000 180000h-18FFFFh
128 64 SA25 00011001 190000h-19FFFFh
128 64 SA26 00011010 1A0000h-1AFFFFh
128 64 SA27 00011011 1B0000h-1BFFFFh
128 64 SA28 00011100 1C0000h-1CFFFFh
128 64 SA29 00011101 1D0000h-1DFFFFh
128 64 SA30 00011110 1E0000h-1EFFFFh
128 64 SA31 00011111 1F0000h-1FFFFFh
128 64 SA32 00100000 200000h-20FFFFh
128 64 SA33 00100001 210000h-21FFFFh
128 64 SA34 00100010 220000h-22FFFFh
128 64 SA35 00100011 230000h-23FFFFh
128 64 SA36 00100100 240000h-24FFFFh
128 64 SA37 00100101 250000h-25FFFFh
128 64 SA38 00100110 260000h-26FFFFh
128 64 SA39 00100111 270000h-27FFFFh
8
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA40 00101000 280000h-28FFFFh
128 64 SA41 00101001 290000h-29FFFFh
128 64 SA42 00101010 2A0000h-2AFFFFh
128 64 SA43 00101011 2B0000h-2BFFFFh
128 64 SA44 00101100 2C0000h-2CFFFFh
128 64 SA45 00101101 2D0000h-2DFFFFh
128 64 SA46 00101110 2E0000h-2EFFFFh
128 64 SA47 00101111 2F0000h-2FFFFFh
128 64 SA48 00110000 300000h-30FFFFh
128 64 SA49 00110001 310000h-31FFFFh
128 64 SA50 00110010 320000h-32FFFFh
128 64 SA51 00110011 330000h-33FFFFh
128 64 SA52 00110100 340000h-34FFFFh
128 64 SA53 00110101 350000h-35FFFFh
128 64 SA54 00110110 360000h-36FFFFh
128 64 SA55 00110111 370000h-37FFFFh
128 64 SA56 00111000 380000h-38FFFFh
128 64 SA57 00111001 390000h-39FFFFh
128 64 SA58 00111010 3A0000h-3AFFFFh
128 64 SA59 00111011 3B0000h-3BFFFFh
128 64 SA60 00111100 3C0000h-3CFFFFh
128 64 SA61 00111101 3D0000h-3DFFFFh
128 64 SA62 00111110 3E0000h-3EFFFFh
128 64 SA63 00111111 3F0000h-3FFFFFh
128 64 SA64 01000000 400000h-40FFFFh
128 64 SA65 01000001 410000h-41FFFFh
128 64 SA66 01000010 420000h-42FFFFh
128 64 SA67 01000011 430000h-43FFFFh
128 64 SA68 01000100 440000h-44FFFFh
128 64 SA69 01000101 450000h-45FFFFh
128 64 SA70 01000110 460000h-46FFFFh
128 64 SA71 01000111 470000h-47FFFFh
128 64 SA72 01001000 480000h-48FFFFh
128 64 SA73 01001001 490000h-49FFFFh
128 64 SA74 01001010 4A0000h-4AFFFFh
128 64 SA75 01001011 4B0000h-4BFFFFh
128 64 SA76 01001100 4C0000h-4CFFFFh
128 64 SA77 01001101 4D0000h-4DFFFFh
128 64 SA78 01001110 4E0000h-4EFFFFh
128 64 SA79 01001111 4F0000h-4FFFFFh
128 64 SA80 01010000 500000h-50FFFFh
128 64 SA81 01010001 510000h-51FFFFh
9
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA82 01010010 520000h-52FFFFh
128 64 SA83 01010011 530000h-53FFFFh
128 64 SA84 01010100 540000h-54FFFFh
128 64 SA85 01010101 550000h-55FFFFh
128 64 SA86 01010110 560000h-56FFFFh
128 64 SA87 01010111 570000h-57FFFFh
128 64 SA88 01011000 580000h-58FFFFh
128 64 SA89 01011001 590000h-59FFFFh
128 64 SA90 01011010 5A0000h-5AFFFFh
128 64 SA91 01011011 5B0000h-5BFFFFh
128 64 SA92 01011100 5C0000h-5CFFFFh
128 64 SA93 01011101 5D0000h-5DFFFFh
128 64 SA94 01011110 5E0000h-5EFFFFh
128 64 SA95 01011111 5F0000h-5FFFFFh
128 64 SA96 01100000 600000h-60FFFFh
128 64 SA97 01100001 610000h-61FFFFh
128 64 SA98 01100010 620000h-62FFFFh
128 64 SA99 01100011 630000h-63FFFFh
128 64 SA100 01100100 640000h-64FFFFh
128 64 SA101 01100101 650000h-65FFFFh
128 64 SA102 01100110 660000h-66FFFFh
128 64 SA103 01100111 670000h-67FFFFh
128 64 SA104 01101000 680000h-68FFFFh
128 64 SA105 01101001 690000h-69FFFFh
128 64 SA106 01101010 6A0000h-6AFFFFh
128 64 SA107 01101011 6B0000h-6BFFFFh
128 64 SA108 01101100 6C0000h-6CFFFFh
128 64 SA109 01101101 6D0000h-6DFFFFh
128 64 SA110 01101110 6E0000h-6EFFFFh
128 64 SA111 01101111 6F0000h-6FFFFFh
128 64 SA112 01110000 700000h-70FFFFh
128 64 SA113 01110001 710000h-71FFFFh
128 64 SA114 01110010 720000h-72FFFFh
128 64 SA115 01110011 730000h-73FFFFh
128 64 SA116 01110100 740000h-74FFFFh
128 64 SA117 01110101 750000h-75FFFFh
128 64 SA118 01110110 760000h-76FFFFh
128 64 SA119 01110111 770000h-77FFFFh
128 64 SA120 01111000 780000h-78FFFFh
128 64 SA121 01111001 790000h-79FFFFh
128 64 SA122 01111010 7A0000h-7AFFFFh
128 64 SA123 01111011 7B0000h-7BFFFFh
10
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA124 01111100 7C0000h-7CFFFFh
128 64 SA125 01111101 7D0000h-7DFFFFh
128 64 SA126 01111110 7E0000h-7EFFFFh
128 64 SA127 01111111 7F0000h-7FFFFFh
128 64 SA128 10000000 800000h-80FFFFh
128 64 SA129 10000001 810000h-81FFFFh
128 64 SA130 10000010 820000h-82FFFFh
128 64 SA131 10000011 830000h-83FFFFh
128 64 SA132 10000100 840000h-84FFFFh
128 64 SA133 10000101 850000h-85FFFFh
128 64 SA134 10000110 860000h-86FFFFh
128 64 SA135 10000111 870000h-87FFFFh
128 64 SA136 10001000 880000h-88FFFFh
128 64 SA137 10001001 890000h-89FFFFh
128 64 SA138 10001010 8A0000h-8AFFFFh
128 64 SA139 10001011 8B0000h-8BFFFFh
128 64 SA140 10001100 8C0000h-8CFFFFh
128 64 SA141 10001101 8D0000h-8DFFFFh
128 64 SA142 10001110 8E0000h-8EFFFFh
128 64 SA143 10001111 8F0000h-8FFFFFh
128 64 SA144 10010000 900000h-90FFFFh
128 64 SA145 10010001 910000h-91FFFFh
128 64 SA146 10010010 920000h-92FFFFh
128 64 SA147 10010011 930000h-93FFFFh
128 64 SA148 10010100 940000h-94FFFFh
128 64 SA149 10010101 950000h-95FFFFh
128 64 SA150 10010110 960000h-96FFFFh
128 64 SA151 10010111 970000h-97FFFFh
128 64 SA152 10011000 980000h-98FFFFh
128 64 SA153 10011001 990000h-99FFFFh
128 64 SA154 10011010 9A0000h-9AFFFFh
128 64 SA155 10011011 9B0000h-9BFFFFh
128 64 SA156 10011100 9C0000h-9CFFFFh
128 64 SA157 10011101 9D0000h-9DFFFFh
128 64 SA158 10011110 9E0000h-9EFFFFh
128 64 SA159 10011111 9F0000h-9FFFFFh
128 64 SA160 10100000 A00000h-A0FFFFh
128 64 SA161 10100001 A10000h-A1FFFFh
128 64 SA162 10100010 A20000h-A2FFFFh
128 64 SA163 10100011 A30000h-A3FFFFh
128 64 SA164 10100100 A40000h-A4FFFFh
128 64 SA165 10100101 A50000h-A5FFFFh
11
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA166 10100110 A60000h-A6FFFFh
128 64 SA167 10100111 A70000h-A7FFFFh
128 64 SA168 10101000 A80000h-A8FFFFh
128 64 SA169 10101001 A90000h-A9FFFFh
128 64 SA170 10101010 AA0000h-AAFFFFh
128 64 SA171 10101011 AB0000h-ABFFFFh
128 64 SA172 10101100 AC0000h-ACFFFFh
128 64 SA173 10101101 AD0000h-ADFFFFh
128 64 SA174 10101110 AE0000h-AEFFFFh
128 64 SA175 10101111 AF0000h-AFFFFFh
128 64 SA176 10110000 B00000h-B0FFFFh
128 64 SA177 10110001 B10000h-B1FFFFh
128 64 SA178 10110010 B20000h-B2FFFFh
128 64 SA179 10110011 B30000h-B3FFFFh
128 64 SA180 10110100 B40000h-B4FFFFh
128 64 SA181 10110101 B50000h-B5FFFFh
128 64 SA182 10110110 B60000h-B6FFFFh
128 64 SA183 10110111 B70000h-B7FFFFh
128 64 SA184 10111000 B80000h-B8FFFFh
128 64 SA185 10111001 B90000h-B9FFFFh
128 64 SA186 10111010 BA0000h-BAFFFFh
128 64 SA187 10111011 BB0000h-BBFFFFh
128 64 SA188 10111100 BC0000h-BCFFFFh
128 64 SA189 10111101 BD0000h-BDFFFFh
128 64 SA190 10111110 BE0000h-BEFFFFh
128 64 SA191 10111111 BF0000h-BFFFFFh
128 64 SA192 11000000 C00000h-C0FFFFh
128 64 SA193 11000001 C10000h-C1FFFFh
128 64 SA194 11000010 C20000h-C2FFFFh
128 64 SA195 11000011 C30000h-C3FFFFh
128 64 SA196 11000100 C40000h-C4FFFFh
128 64 SA197 11000101 C50000h-C5FFFFh
128 64 SA198 11000110 C60000h-C6FFFFh
128 64 SA199 11000111 C70000h-C7FFFFh
128 64 SA200 11001000 C80000h-C8FFFFh
128 64 SA201 11001001 C90000h-C9FFFFh
128 64 SA202 11001010 CA0000h-CAFFFFh
128 64 SA203 11001011 CB0000h-CBFFFFh
128 64 SA204 11001100 CC0000h-CCFFFFh
128 64 SA205 11001101 CD0000h-CDFFFFh
128 64 SA206 11001110 CE0000h-CEFFFFh
128 64 SA207 11001111 CF0000h-CFFFFFh
12
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA208 11010000 D00000h-D0FFFFh
128 64 SA209 11010001 D10000h-D1FFFFh
128 64 SA210 11010010 D20000h-D2FFFFh
128 64 SA211 11010011 D30000h-D3FFFFh
128 64 SA212 11010100 D40000h-D4FFFFh
128 64 SA213 11010101 D50000h-D5FFFFh
128 64 SA214 11010110 D60000h-D6FFFFh
128 64 SA215 11010111 D70000h-D7FFFFh
128 64 SA216 11011000 D80000h-D8FFFFh
128 64 SA217 11011001 D90000h-D9FFFFh
128 64 SA218 11011010 DA0000h-DAFFFFh
128 64 SA219 11011011 DB0000h-DBFFFFh
128 64 SA220 11011100 DC0000h-DCFFFFh
128 64 SA221 11011101 DD0000h-DDFFFFh
128 64 SA222 11011110 DE0000h-DEFFFFh
128 64 SA223 11011111 DF0000h-DFFFFFh
128 64 SA224 11100000 E00000h-E0FFFFh
128 64 SA225 11100001 E10000h-E1FFFFh
128 64 SA226 11100010 E20000h-E2FFFFh
128 64 SA227 11100011 E30000h-E3FFFFh
128 64 SA228 11100100 E40000h-E4FFFFh
128 64 SA229 11100101 E50000h-E5FFFFh
128 64 SA230 11100110 E60000h-E6FFFFh
128 64 SA231 11100111 E70000h-E7FFFFh
128 64 SA232 11101000 E80000h-E8FFFFh
128 64 SA233 11101001 E90000h-E9FFFFh
128 64 SA234 11101010 EA0000h-EAFFFFh
128 64 SA235 11101011 EB0000h-EBFFFFh
128 64 SA236 11101100 EC0000h-ECFFFFh
128 64 SA237 11101101 ED0000h-EDFFFFh
128 64 SA238 11101110 EE0000h-EEFFFFh
128 64 SA239 11101111 EF0000h-EFFFFFh
128 64 SA240 11110000 F00000h-F0FFFFh
128 64 SA241 11110001 F10000h-F1FFFFh
128 64 SA242 11110010 F20000h-F2FFFFh
128 64 SA243 11110011 F30000h-F3FFFFh
128 64 SA244 11110100 F40000h-F4FFFFh
128 64 SA245 11110101 F50000h-F5FFFFh
128 64 SA246 11110110 F60000h-F6FFFFh
128 64 SA247 11110111 F70000h-F7FFFFh
128 64 SA248 11111000 F80000h-F8FFFFh
128 64 SA249 11111001 F90000h-F9FFFFh
13
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Size Sector Sector Address
A23-A16
(x16)
Address Range
Kbytes Kwords
128 64 SA250 11111010 FA0000h-FAFFFFh
128 64 SA251 11111011 FB0000h-FBFFFFh
128 64 SA252 11111100 FC0000h-FCFFFFh
128 64 SA253 11111101 FD0000h-FDFFFFh
128 64 SA254 11111110 FE0000h-FEFFFFh
128 64 SA255 11111111 FF0000h-FFFFFFh
14
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Table 2-1. BUS OPERATION
Notes:
1. The rst or last sector was protected if WP#/ACC=Vil.
2. When WP#/ACC = Vih, the protection conditions of the outmost sector depends on previous protection condi-
tions. Refer to the advanced protect feature.
3. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector pro-
tection, or data polling algorithm.
4. In Word Mode (Byte#=Vih), the addresses are AM to A0, AM: MSB of address.
In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15), AM: MSB of address.
Mode Select RE-
SET# CE# WE# OE# Address
(Note4)
Data
I/O
Q7~Q0
Byte#
WP#/
ACC
Vil Vih
Data (I/O)
Q15~Q8
Device Reset L X X X X HighZ HighZ HighZ L/H
Standby Mode Vcc ±
0.3V
Vcc±
0.3V X X X HighZ HighZ HighZ H
Output Disable H L H H X HighZ HighZ HighZ L/H
Read Mode H L H L AIN DOUT Q8-Q14=
HighZ,
Q15=A-1
DOUT L/H
Write H L L H AIN DIN DIN Note1,2
Accelerate Program H L L H AIN DIN DIN Vhv
BUS OPERATION
15
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Notes:
1. Sector unprotected code:00h. Sector protected code:01h.
2. Factory locked code: WP# protects high address sector: 99h.
WP# protects low address sector: 89h
Factory unlocked code: WP# protects high address sector: 19h.
WP# protects low address sector: 09h
3. AM: MSB of address.
Table 2-2. BUS OPERATION
Item
Control Input AM
to
A12
A11
to
A10
A9
A8
to
A7
A6
A5
to
A4
A3
to
A2
A1 A0 Q7 ~ Q0 Q15 ~ Q8
CE# WE# OE#
Sector Lock Status
Verication L H L SA X Vhv X L X L H L
01h or
00h
(Note 1)
X
Read Silicon ID
Manufacturer
Code
L H L X X Vhv X L X L L L C2H X
Read Silicon ID -- MX29GL256E
Cycle 1 L H L X X Vhv X L X L L H 7EH 22H(Word),
XXH(Byte)
Cycle 2 L H L X X Vhv X L X H H L 22H 22H(Word),
XXH(Byte)
Cycle 3 L H L X X Vhv X L X H H H 01H 22H(Word),
XXH(Byte)
16
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FUNCTIONAL OPERATION DESCRIPTION
READ OPERATION
To perform a read operation, the system addresses the desired memory array or status register location by pro-
viding its address on the address pins and simultaneously enabling the chip by driving CE# & OE# LOW, and
WE# HIGH. After the Tce and Toe timing requirements have been met, the system can read the contents of the
addressed location by reading the Data (I/O) pins. If either the CE# or OE# is held HIGH, the outputs will remain
tri-stated and no data will appear on the output pins.
PAGE READ
This device is able to conduct MXIC MaskROM compatible high performance page read. Page size is 16 bytes
or 8 words. The higher address Amax ~ A3 select the certain page, while A2~A0 for word mode, A2~A-1 for
byte mode select the particular word or byte in a page. The page access time is Taa or Tce, following by Tpa for
the rest of the page read time. When CE# toggles, access time is Taa or Tce. Page mode can be turned on by
keeping "page-read address" constant and changing the "intra-read page" addresses.
WRITE OPERATION
To perform a write operation, the system provides the desired address on the address pins, enables the chip by
asserting CE# LOW, and disables the Data (I/O) pins by holding OE# HIGH. The system then places data to be
written on the Data (I/O) pins and pulses WE# LOW. The device captures the address information on the falling
edge of WE# and the data on the rising edge of WE#. To see an example, please refer to the timing diagram in
Figure 1. The system is not allowed to write invalid commands (commands not dened in this datasheet) to the
device. Writing an invalid command may put the device in an undened state.
DEVICE RESET
Driving the RESET# pin LOW for a period of Trp or more will return the device to Read mode. If the device is in
the middle of a program or erase operation, the reset operation will take at most a period of Tready1 before the
device returns to Read mode. Until the device does returns to Read mode, the RY/BY# pin will remain Low (Busy
Status).
When the RESET# pin is held at GND±0.3V, the device only consumes standby (Isbr) current. However, the de-
vice draws larger current if the RESET# pin is held at a voltage greater than GND+0.3V and less than or equal to
Vil.
It is recommended to tie the system reset signal to the RESET# pin of the ash memory. This allows the device
to be reset with the system and puts it in a state where the system can immediately begin reading boot code
from it.
STANDBY MODE
The device enters Standby mode whenever the RESET# and CE# pins are both held High except in the embed-
ded mode. While in this mode, WE# and OE# will be ignored, all Data Output pins will be in a high impedance
state, and the device will draw minimal (Isb) current.
17
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
OUTPUT DISABLE
While in active mode (RESET# HIGH and CE# LOW), the OE# pin controls the state of the output pins. If OE# is
held HIGH, all Data (I/O) pins will remain tri-stated. If held LOW, the Byte or Word Data (I/O) pins will drive data.
BYTE/WORD SELECTION
The BYTE# input pin is used to select the organization of the array data and how the data is input/output on the
Data (I/O) pins. If the BYTE# pin is held HIGH, Word mode will be selected and all 16 data lines (Q0 to Q15) will
be active.
If BYTE# is forced LOW, Byte mode will be active and only data lines Q0 to Q7 will be active. Data lines Q8 to
Q14 will remain in a high impedance state and Q15 becomes the A-1 address input pin.
HARDWARE WRITE PROTECT
By driving the WP#/ACC pin LOW. The highest or lowest was protected from all erase/program operations. If
WP#/ACC is held HIGH (Vih to VCC), these sectors revert to their previously protected/unprotected status.
ACCELERATED PROGRAMMING OPERATION
By applying high voltage (Vhv) to the WP#/ACC pin, the device will enter the Accelerated Programming mode.
This mode permits the system to skip the normal command unlock sequences and program byte/word locations
directly. During accelerated programming, the current drawn from the WP#/ACC pin is no more than ICP1.
WRITE BUFFER PROGRAMMING OPERATION
Programs 64bytes/32words in a programming operation. To trigger the Write Buffer Programming, start by the
rst two unlock cycles, then third cycle writes the Write Buffer Load command at the destined programming Sec-
tor Address. The forth cycle writes the "word locations subtract one" number.
Following above operations, system starts to write the mingling of address and data. After the programming of
the rst address or data, the "write-buffer-page" is selected. The following data should be within the above men-
tioned page.
The "write-buffer-page" is selected by choosing address Amax-A5.
"Write-Buffer-Page" address has to be the same for all address/ data write into the write buffer. If not, operation
will ABORT.
To program the content of the write buffer page this command must be followed by a write to buffer Program con-
rm command.
The operation of write-buffer can be suspended or resumed by the standard commands, once the write buffer
programming operation is nished, it’ll return to normal READ mode.
18
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
WRITE BUFFER PROGRAMMING OPERATION (cont'd)
ABORT will be executed for the Write Buffer Programming Sequence if following condition occurs:
• The value loaded is bigger than the page buffer size during "Number of Locations to Program"
• Address written in a sector is not the same as the one assigned during the Write-Buffer-Load command.
• Address/ Data pair written to a different write-buffer-page than the one assigned by the "Starting Address"
during the "write buffer data loading" operation.
• Writing not "Conrm Command" after the assigned number of "data load" cycles.
At Write Buffer Abort mode, the status register will be Q1=1, Q7=DATA# (last address written), Q6=toggle.
A Write-to-Buffer-Abort Reset command sequence has to be written to reset the device for the next operation.
Write buffer programming can be conducted in any sequence. However the CFI functions, autoselect, Secured
Silicon sector are not functional when program operation is in progress. Multiple write buffer programming opera-
tions on the same write buffer address range without intervening erases is available. Any bit in a write buffer ad-
dress range can’t be programmed from 0 back to 1.
SECTOR PROTECT OPERATION
The device provides user programmable protection operations for selected sectors. Please refer to Table 1 which
show all Sector assignments.
During the protection operation, the sector address of any sector may be used to specify the Sector being pro-
tected.
AUTOMATIC SELECT BUS OPERATIONS
The following ve bus operations require A9 to be raised to Vhv. Please see AUTOMATIC SELECT COMMAND
SEQUENCE in the COMMAND OPERATIONS section for details of equivalent command operations that do not
require the use of Vhv.
SECTOR LOCK STATUS VERIFICATION
To determine the protected state of any sector using bus operations, the system performs a READ OPERATION
with A9 raised to Vhv, the sector address applied to address pins A23 to A12, address pins A6, A3, A2 & A0 held
LOW, and address pin A1 held HIGH. If data bit Q0 is LOW, the sector is not protected, and if Q0 is HIGH, the
sector is protected.
19
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
READ SILICON ID MANUFACTURER CODE
To determine the Silicon ID Manufacturer Code, the system performs a READ OPERATION with A9 raised to
Vhv and address pins A6, A3, A2, A1, & A0 held LOW. The Macronix ID code of C2h should be present on data
bits Q7 to Q0.
READ INDICATOR BIT (Q7) FOR SECURITY SECTOR
To determine if the Security Sector has been locked at the factory, the system performs a READ OPERATION
with A9 raised to Vhv, address pin A6, A3 & A2 held LOW, and address pins A1 & A0 held HIGH. If the Security
Sector has been locked at the factory, the code 99h(H)/89h(L) will be present on data bits Q7 to Q0. Otherwise,
the factory unlocked code of 19h(H)/09h(L) will be present.
INHERENT DATA PROTECTION
To avoid accidental erasure or programming of the device, the device is automatically reset to Read mode during
power up. Additionally, the following design features protect the device from unintended data corruption.
COMMAND COMPLETION
Only after the successful completion of the specied command sets will the device begin its erase or program
operation. The failure in observing valid command sets will result in the memory returning to read mode.
LOW VCC WRITE INHIBIT
The device refuses to accept any write command when Vcc is less than VLKO. This prevents data from
spuriously being altered during power-up, power-down, or temporary power interruptions. The device
automatically resets itself when Vcc is lower than VLKO and write cycles are ignored until Vcc is greater than
VLKO. The system must provide proper signals on control pins after Vcc rises above VLKO to avoid unintentional
program or erase operations.
WRITE PULSE "GLITCH" PROTECTION
CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write
cycle.
LOGICAL INHIBIT
A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at
Vih, WE# at Vih, or OE# at Vil.
20
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
FUNCTIONAL OPERATION DESCRIPTION (cont'd)
POWER-UP SEQUENCE
Upon power up, the device is placed in Read mode. Furthermore, program or erase operation will begin only
after successful completion of specied command sequences.
POWER-UP WRITE INHIBIT
When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the rst command on
the rising edge of WE#.
POWER SUPPLY DECOUPLING
A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
21
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
COMMAND OPERATIONS
READING THE MEMORY ARRAY
Read mode is the default state after power up or after a reset operation. To perform a read operation, please re-
fer to READ OPERATION in the BUS OPERATIONS section above.
If the device receives an Erase Suspend command while in the Sector Erase state, the erase operation will
pause (after a time delay not exceeding 20us) and the device will enter Erase-Suspended Read mode. While in
the Erase-Suspended Read mode, data can be programmed or read from any sector not being erased. Reading
from addresses within sector (s) being erased will only return the contents of the status register, which is in fact
how the current status of the device can be determined.
If a program command is issued to any inactive (not currently being erased) sector during Erase-Suspended
Read mode, the device will perform the program operation and automatically return to Erase-Suspended Read
mode after the program operation completes successfully.
While in Erase-Suspended Read mode, an Erase Resume command must be issued by the system to reactivate
the erase operation. The erase operation will resume from where is was suspended and will continue until it
completes successfully or another Erase Suspend command is received.
After the memory device completes an embedded operation (automatic Chip Erase, Sector Erase, or Program)
successfully, it will automatically return to Read mode and data can be read from any address in the array. If the
embedded operation fails to complete, as indicated by status register bit Q5 (exceeds time limit ag) going HIGH
during the operations, the system must perform a reset operation to return the device to Read mode.
There are several states that require a reset operation to return to Read mode:
1. A program or erase failure--indicated by status register bit Q5 going HIGH during the operation. Failures dur-
ing either of these states will prevent the device from automatically returning to Read mode.
2. The device is in Auto Select mode or CFI mode. These two states remain active until they are terminated by a
reset operation.
In the two situations above, if a reset operation (either hardware reset or software reset command) is not per-
formed, the device will not return to Read mode and the system will not be able to read array data.
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY
The device provides the user the ability to program the memory array in Byte mode or Word mode. As long as
the users enters the correct cycle dened in the Table 3 (including 2 unlock cycles and the A0H program com-
mand), any byte or word data provided on the data lines by the system will automatically be programmed into the
array at the specied location.
After the program command sequence has been executed, the internal write state machine (WSM) automatically
executes the algorithms and timings necessary for programming and verication, which includes generating suit-
able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do
not pass verication or have low margins. The internal controller protects cells that do pass verication and mar-
gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells
continue to be programmed.
With the internal WSM automatically controlling the programming process, the user only needs to enter the pro-
gram command and data once.
22
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
COMMAND OPERATIONS (cont'd)
AUTOMATIC PROGRAMMING OF THE MEMORY ARRAY (cont'd)
Programming will only change the bit status from "1" to "0". It is not possible to change the bit status from "0" to
"1" by programming. This can only be done by an erase operation. Furthermore, the internal write verication
only checks and detects errors in cases where a "1" is not successfully programmed to "0".
Any commands written to the device during programming will be ignored except hardware reset or program sus-
pend. Hardware reset will terminate the program operation after a period of time no more than 10us. When the
embedded program algorithm is complete or the program operation is terminated by a hardware reset, the de-
vice will return to Read mode. Program suspend ready, the device will enter program suspend read mode.
After the embedded program operation has begun, the user can check for completion by reading the following
bits in the status register:
Note: RY/BY# is an open drain output pin and should be connected to VCC through a high value pull-up resistor.
ERASING THE MEMORY ARRAY
There are two types of erase operations performed on the memory array -- Sector Erase and Chip Erase. In
the Sector Erase operation, one or more selected sectors may be erased simultaneously. In the Chip Erase
operation, the complete memory array is erased except for any protected sectors. More details of the protected
sectors are explained in Section Advanced Sector Protection/Un-protection.
SECTOR ERASE
The sector erase operation is used to clear data within a sector by returning all of its memory locations to the
"1" state. It requires six command cycles to initiate the erase operation. The rst two cycles are "unlock cycles",
the third is a conguration cycle, the fourth and fth are also "unlock cycles", and the sixth cycle is the Sector
Erase command. After the sector erase command sequence has been issued, an internal 50us time-out counter
is started. Until this counter reaches zero, additional sector addresses and Sector Erase commands may be is-
sued thus allowing multiple sectors to be selected and erased simultaneously. After the 50us time-out counter
has expired, no new commands will be accepted and the embedded sector erase operation will begin. Note that
the 50us timer-out counter is restarted after every erase command sequence. If the user enters any command
other than Sector Erase or Erase Suspend during the time-out period, the erase operation will abort and the de-
vice will return to Read mode.
After the embedded sector erase operation begins, all commands except Erase Suspend will be ignored. The
only way to interrupt the operation is with an Erase Suspend command or with a hardware reset. The hardware
reset will completely abort the operation and return the device to Read mode.
Status Q7*1 Q6*1 Q5 Q1 RY/BY# (Note)
In progress Q7# Toggling 0 0 0
Exceed time limit Q7# Toggling 1 N/A 0
23
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
COMMAND OPERATIONS (cont'd)
SECTOR ERASE (cont'd)
The system can determine the status of the embedded sector erase operation by the following methods:
CHIP ERASE
The Chip Erase operation is used erase all the data within the memory array. All memory cells containing a "0"
will be returned to the erased state of "1". This operation requires 6 write cycles to initiate the action. The rst
two cycles are "unlock" cycles, the third is a conguration cycle, the fourth and fth are also "unlock" cycles, and
the sixth cycle initiates the chip erase operation.
During the chip erase operation, no other software commands will be accepted, but if a hardware reset is re-
ceived or the working voltage is too low, that chip erase will be terminated. After Chip Erase, the chip will auto-
matically return to Read mode.
The system can determine the status of the embedded chip erase operation by the following methods:
*1: RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
Notes:
1. The Q3 status bit is the 50us time-out indicator. When Q3=0, the 50us time-out counter has not yet reached
zero and a new Sector Erase command may be issued to specify the address of another sector to be erased.
When Q3=1, the 50us time-out counter has expired and the Sector Erase operation has already begun. Erase
Suspend is the only valid command that may be issued once the embedded erase operation is underway.
2. RY/BY# is open drain output pin and should be connected to VCC through a high value pull-up resistor.
3. When an attempt is made to erase only protected sector (s), the erase operation will abort thus preventing any
data changes in the protected sector (s). Q7 will output "0" and Q6 will toggle briey (100us or less) before
aborting and returning the device to Read mode. If unprotected sectors are also specied, however, they will
be erased normally and the protected sector (s) will remain unchanged.
4. Q2 is a localized indicator showing a specied sector is undergoing erase operation or not. Q2 toggles when
user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase
suspend mode).
Status Q7 Q6 Q5 Q3*1 Q2 RY/BY#*2
Time-out period 0 Toggling 0 0 Toggling 0
In progress 0 Toggling 0 1 Toggling 0
Exceeded time limit 0 Toggling 1 1 Toggling 0
Status Q7 Q6 Q5 Q2 RY/BY#*1
In progress 0 Toggling 0 Toggling 0
Exceed time limit 0 Toggling 1 Toggling 0
24
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
After beginning a sector erase operation, Erase Suspend is the only valid command that may be issued. If sys-
tem issues an Erase Suspend command during the 50us time-out period following a Sector Erase command, the
time-out period will terminate immediately and the device will enter Erase-Suspended Read mode. If the system
issues an Erase Suspend command after the sector erase operation has already begun, the device will not enter
Erase-Suspended Read mode until 20us time has elapsed. The system can determine if the device has entered
the Erase-Suspended Read mode through Q6, Q7, and RY/BY#.
After the device has entered Erase-Suspended Read mode, the system can read or program any sector (s) ex-
cept those being erased by the suspended erase operation. Reading any sector being erased or programmed
will return the contents of the status register. Whenever a suspend command is issued, user must issue a re-
sume command and check Q6 toggle bit status, before issue another erase command. The system can use the
status register bits shown in the following table to determine the current state of the device:
COMMAND OPERATIONS (cont'd)
ERASE SUSPEND/RESUME
When the device has suspended erasing, user can execute the command sets except sector erase and chip
erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME
The sector Erase Resume command is valid only when the device is in Erase-Suspended Read mode. After
erase resumes, the user can issue another Ease Suspend command, but there should be a 400us interval be-
tween Ease Resume and the next Erase Suspend command.
Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#
Erase suspend read in erase suspended sector 1 No toggle 0 N/A toggle N/A 1
Erase suspend read in non-erase suspended sector Data Data Data Data Data Data 1
Erase suspend program in non-erase suspended sector Q7# Toggle 0 N/A N/A N/A 0
25
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
COMMAND OPERATIONS (cont'd)
PROGRAM SUSPEND/RESUME
When the device has Program/Erase suspended, user can execute read array, auto-select, read CFI, read secu-
rity silicon.
PROGRAM RESUME
The Program Resume command is valid only when the device is in Program-Suspended mode. After program
resumes, the user can issue another Program Suspend command, but there should be a 5us interval between
Program Resume and the next Program Suspend command.
Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#
Program suspend read in program suspended sector Invalid 1
Program suspend read in non-program suspended
sector Data Data Data Data Data Data 1
BUFFER WRITE ABORT
Q1 is the indicator of Buffer Write Abort. When Q1=1, the device will abort from buffer write and go back to read
status register shown as following table:
Status Q7 Q6 Q5 Q3 Q2 Q1 RY/BY#
Buffer Write Busy Q7# Toggle 0 N/A N/A 0 0
Buffer Write Abort Q7# Toggle 0 N/A N/A 1 0
Buffer Write Exceeded Time Limit Q7# Toggle 1 N/A N/A 0 0
After beginning a program operation, Program Suspend is the only valid command that may be issued. The sys-
tem can determine if the device has entered the Program-Suspended Read mode through Q6 and RY/BY#.
After the device has entered Program-Suspended mode, the system can read any sector (s) except those be-
ing programmed by the suspended program operation. Reading the sector being program suspended is invalid.
Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status,
before issue another program command. The system can use the status register bits shown in the following table
to determine the current state of the device:
26
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
AUTOMATIC SELECT OPERATIONS
When the device is in Read mode, Program Suspended mode, Erase-Suspended Read mode, or CFI mode, the
user can issue the Automatic Select command shown in Table 3 (two unlock cycles followed by the Automatic
Select command 90h) to enter Automatic Select mode. After entering Automatic Select mode, the user can query
the Manufacturer ID, Device ID, Security Sector locked status, or Sector protected status multiple times without
issuing a new Automatic Select command.
While In Automatic Select mode, issuing a Reset command (F0h) will return the device to Read mode (or Ease-
Suspended Read mode if Erase-Suspend was active) or Program Suspended Read mode if Program Suspend
was active.
Another way to enter Automatic Select mode is to use one of the bus operations shown in Table 2-2. BUS OP-
ERATION. After the high voltage (Vhv) is removed from the A9 pin, the device will automatically return to Read
mode or Erase-Suspended Read mode.
AUTOMATIC SELECT COMMAND SEQUENCE
Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured
silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles.
The rst two are unlock cycles, and followed by a specic command. The fourth cycle is a normal read cycle,
and user can read at any address any number of times without entering another command sequence. The Reset
command is necessary to exit the Automatic Select mode and back to read array. The following table shows the
identication code with corresponding address.
After entering automatic select mode, no other commands are allowed except the reset command.
COMMAND OPERATIONS (cont'd)
Address Data (Hex) Representation
Manufacturer ID Word X00 C2
Byte X00 C2
Device ID MX29GL256E
Word X01/0E/0F 227E/2222/2201
Byte X02/1C/1E 7E/22/01
Secured Silicon
Word X03 99/19 (H) Factory locked/unlocked
89/09 (L)
Byte X06 99/19 (H) Factory locked/unlocked
89/09 (L)
Sector Protect Verify Word (Sector address) X 02 00/01 Unprotected/protected
Byte (Sector address) X 04 00/01 Unprotected/protected
27
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
READ MANUFACTURER ID OR DEVICE ID
The Manufacturer ID (identication) is a unique hexadecimal number assigned to each manufacturer by the JE-
DEC committee. Each company has its own manufacturer ID, which is different from the ID of all other compa-
nies. The number assigned to Macronix is C2h.
After entering Automatic Select mode, performing a read operation with A1 & A0 held LOW will cause the device
to output the Manufacturer ID on the Data I/O (Q7 to Q0) pins.
RESET
In the following situations, executing reset command will reset device back to Read mode:
• Among erase command sequence (before the full command set is completed)
• Sector erase time-out period
• Erase fail (while Q5 is high)
• Among program command sequence (before the full command set is completed, erase-suspended program
included)
• Program fail (while Q5 is high, and erase-suspended program fail is included)
• Auto-select mode
• CFI mode
While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset
device back to read array mode. While the device is in Auto-Select mode or CFI mode, user must issue reset
command to reset device back to read array mode.
When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig-
nore reset command.
COMMAND OPERATIONS (cont'd)
28
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Start
Q1=0 Q2=0
Password Protection Mode
To choose
protection mode
set lock register bit
(Q1/Q2)
Set
SPB Lock Bit
SPB = 0
SPB = 1
SPB Lock bit Unlocked
SPB is changeable
Solid Write Protect bit (SPB)
SPB=0 sector protect
SPB=1 sector unprotect
Temporary Unprotect
SPB bit (USPB)
USPB=0 Temp. Unprotect
SPB bit, SPB changeable
USPB=1 SPB bit can not
changeable
USPB 0
USPB 1
USPB 2
:
:
USPB N-1
USPB N
SPB 0
SPB 1
SPB 2
:
:
SPB N-1
SPB N
SA 0
SA 1
SA 2
:
:
SA N-1
SA N
DPB 0
DPB 1
DPB 2
:
:
DPB N-1
DPB N
SPB Lock bit locked
All SPB can not changeable
Solid Protection Mode
Set 64 bit Password
Sector Array
Dynamic Write Protect bit
(DPB)
DPB=0 sector protect
DPB=1 sector unprotect
Advanced Sector Protection/Un-protection
There are two ways to implement software Advanced Sector Protection on this device: Password method or
Solid methods. Through these two protection method, user can disable or enable the programming or erasing
operation to any individual sector or whole chip. The gure below helps describe an overview of these methods.
The device is default to the Solid mode and all sectors are unprotected when shipped from factory.
Shows the detail algorithm of advance sector protecting.
Advance Sector Protection/Unprotection SPB Program Algorithm :
29
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
1. Lock Register
User can choose favorite sector protecting method via setting Lock Register bits Q1 and Q2. Lock Register is
a 16-bit one-time programmable register. Once programming either Q1 or Q2, they will be locked in that mode
and the others will be disabled permanently. Q1 and Q2 can not be programmed at the same time, otherwise the
device will abort the operation.
If user selects Password Protection mode, the password setting is required. User can set password by issuing
password program command.
After the Lock Register Bits Command Set Entry command sequence is issued, the read and write operations for
normal sectors are disabled until this mode exits.
A Lock Register allows the memory sectors and extended memory sector protection to be congured.
Lock Register bits
Q15-Q3 Q2 Q1 Q0
Don't care Password Protection Mode
Lock Bit
Solid Protection Mode
Lock Bit
Secured Silicon Sector
Protection Bit
Please refer to the command for Lock Register command set to read and program the Lock register.
Lock Register Program Algorithm :
START
Pass
Exit Lock Register
command
Done YES
YES
NO
Q5 = 1
NO
Write Data AAH, Address 555H
Lock register command set Entry
Write Data 55H, Address 2AAH
Write Data 40H, Address 555H
Write Data A0H,
Address don’t care
Write Program Data,
Address don’t care
Data # Polling Algorithm
Fail
Reset command
Lock register data program
30
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
2. Solid write (non-volatile) protection Mode
2.1 Solid write Protection Bits (SPB)
The Solid write Protection bit (SPB) is a nonvolatile bit with the same endurances as the Flash memory. It
is assigned to each sector individually. The SPB is Preprogramming, and its verication prior to erasure are
managed by the device, so system monitoring is not necessary.
When a SPB is set to “0”, the associated sector is protected, preventing any program or erase operation on this
sector. The SPB bits are set individually by SPB program command. However, it cannot be cleared individually.
Issuing the All SPB Erase command will erase all SPB in the same time. During SPB programming period, the
read and write operations are disabled for normal sector until this mode exits.
If one of the protected sector need to be unprotected (corresponding SPB set to “1”), a few more steps are
required. First, the SPB Lock Bit must be cleared by either putting the device through a power-cycle, or hardware
reset. The SPBs can then be changed to reect the desired settings. Setting the SPB Lock Bit once again locks
the SPBs, and the device operates normally again.
To verify the programming state of the SPB for a given sector, issuing a SPB Status Read Command to the
device is required. Refer to the ow chart below for details of SPB Program Algorithm.
Notes
1. The Read actions within that sector will bring the SPB status back for that sector. All Read actions must be
executed by read mode. The specic sector address is written as the program command at the same time.
2.Once SPB Lock Bit is set, its Program or erase command will not be executed and times-out without
programming or erasing the SPB.
3. Always issue exit command after the execution of resetting the device to read mode and re-enables read and
write actions for normal array.
4. To achieve the best effect of protection, it is recommended to execute the SPB Lock Bit Set command early
in the boot code and protect the boot code by holding WP#/ACC = VIL. Note that the SPB and DPB bits have
the same function when WP#/ACC = VHH, and it is same when ACC =VIH.
2.2 Dynamic Protection Bits (DPBS)
The Dynamic Protection allows the software application to easily protect sectors against inadvertent change.
However, the protection can be easily disabled when changes are necessary.
All Dynamic Protection bit (DPB) are volatile and assigned to each sector. It can be modify individual. DPBs
provide the protection scheme only for unprotected sectors that have their SPBs cleared (erase can be
individually modied d to “1”).To modify the DPB status by issuing the DPB Set (programmed to “0”) or DPB
Clear (erased to “1”)commands, then placing each sector in the protected or unprotected state seperately. After
the DPB Clear command is issued(erased to “1”), the sector may be modied depending on the SPB state of that
sector
When the parts are rst shipped, the SPBs are cleared (erased to “1”) and upon power up or reset, the DPBs can
be set or cleared depending upon the ordering option chosen.
31
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
2.3 Temporary Un-protect Solid write protect bit (USPB)
Temporary Un-protect Solid write Protect Bits are volatile and unique for each sector and can be individually
modied. By issuing the USPB Set or Clear command sequences, the USPBs are set (programmed to “0”) or
cleared (erased to “1”), thus mask each sector's solid write protect bit property. This feature allows software to
temp unprotect write protect sectors despite of SPB's property when DPBs are cleared.
Notes:
1. The USPBs can be set (programmed to “0”) or cleared (erased to “1”) as often as needed. The USPBs are
cleared (all 1s) upon power up. Hardware reset won”t change USPBs/DPBs status. The sectors SPBs would
be in effective state after power up is chosen.
2. However, if there is a need to write a solid protect bit protect sector status, user don't have to clear all SPB
bits. They just use software to set corresponding USPB to 0, which guarantees that corresponding DPB status
is clear, and original solid protect bit protected sectors can be temporary written.
3. SPBLK should be cleared to modify USPB status.
Q6 Toggle ?
Q6 Toggle ?
Q5 = 1 ?
NO
NO
YES
NO
NO
SPB command
set entry
Program SPB
Read Q7~Q0
Twice
Read Q7~Q0
Twice
Read Q7~Q0
Twice
YES
YES
YES
Wait 500 s
Program Fail
Write Reset CMD
Pass
Q0=
'1' (Erase)
'0' (Program)
SPB command
set Exit
Note: SPB program/ erase status polling owchart: check Q6 toggle, when Q6 stop toggle, the read status is
00H /01H (00H for program/ 01H for erase), otherwise the status is “fail” and “exit”.
SPB Program Algorithm :
32
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
4. Password Protection Method
The security level of Password Protection Method is higher then the Solid protection mode. The 64 bit password
is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock
bit is set “0”, after a power-up cycle or Reset Command.
A correct password is required for password Unlock command, to unlock the SPB lock bit. Await 2us is necessary
to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The
Password Unlock command are issued slower then 2 μs every time,. to prevent hacker from trying all the 64-bit
password combinations.
To place the device in password protection mode, a few more steps are required. First, prior to entering the
password protection mode, it is necessary to set a 64-bit password to verify it. Password verication is only
allowed during the password programming operation. Second, the password protection mode is then activated
by programming the password the Password Protection Mode Lock Bit to”0”. This operation is not reversible.
Once the bit is programmed, it cannot be erased, and the device remains permanently in password protection
mode, and the 64-bit password can neither be retrieved nor reprogrammed. Moreover, all commands to the
address where the password is stored are disabled.
The password is all “1”s when shipped from the factory, it is only capable to programming "0"s under password
program command. All 64-bit password combinations are valid as a password. No special address is required
for programming the password. In order to prevent access, the Password Mode Locking Bit must be set after
the Password is programmed and veried. Once the Password Mode Lock Bit is set, prevents reading 64-bits
password on the data bus and any future modication. There is no means to verify what the password is after it
is set.
Entry command sequence will cause the read and write operation to be disabled for normal sector until this mode
exits. Once sector under protected status, device will ignores the program/erase command, enable status polling
and returns to read mode without contents change. The DPB, SPB,USPB and SPB lock bit status of each sector
can be veried by issue status read commands.
3. Solid Protection Bit Lock Bit
The Solid Protection Bit Lock Bit (SPB) is assign to control all SPB status. It is a unique and volatile. When
SPB=0 (set), all SPBs are locked and can not be changed. When SPB=1 (cleared), all SPBs are unlock and
allows to be changed.
There is no software command sequence requested to unlocks this bit, unless the device is in the password
protection mode. To clear the SPB lock bit, just take the device through a hardware reset or a power-up cycle. In
order to prevent moied, the SPB Lock Bit must be set (SPB=0) after all SPBs are setting the desired status.
33
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Sector Protection Status Table
Protection Bit Status Sector Status
DPB SPBLK SPB USPB
clear clear clear clear unprotect, DPB/SPB/USPB are changeable
clear clear clear set unprotect, DPB/SPB/USPB are changeable
clear clear set clear protect, DPB/SPB/USPB are changeable
clear clear set set unprotect, DPB/SPB/USPB are changeable
clear set clear clear unprotect, DPB/USPB are changeable
clear set clear set unprotect, DPB/USPB are changeable
clear set set clear protect, DPB/USPB are changeable
clear set set set unprotect, DPB/USPB are changeable
set clear clear clear protect, DPB/SPB/USPB are changeable
set clear clear set protect, DPB/SPB/USPB are changeable
set clear set clear protect, DPB/SPB/USPB are changeable
set clear set set protect, DPB/SPB/USPB are changeable
set set clear clear protect, DPB/USPB are changeable
set set clear set protect, DPB/USPB are changeable
set set set clear protect, DPB/USPB are changeable
set set set set protect, DPB/USPB are changeable
34
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Secured Silicon Sector
Address Range Standard Factory Locked Express Flash
Factory Locked Customer Lockable
000000h-000007h ESN ESN or Determined by
Customer Determined by Customer
000008h-00007Fh Unavailable Determined by Customer
Customer Lockable: Security Sector NOT Programmed or Protected at the Factory
When the security feature is not required, the security region can act as an extra memory space.
Security silicon sector can also be protected by two methods. Note that once the security silicon sector is pro-
tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered.
After the security silicon is locked and veried, system must write Exit Security Sector Region, go through a pow-
er cycle, or issue a hardware reset to return the device to read normal array mode.
SECURITY SECTOR FLASH MEMORY REGION
The Security Sector region is an extra OTP memory space of 128 words in length. The security sector can be
locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security
Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device.
In factory-locked device, security sector region is protected when shipped from factory and the security silicon
sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped
from factory and the security silicon indicator bit is set to "0".
Factory Locked: Security Sector Programmed and Protected at the Factory
In a factory locked device, the Security Sector is permanently locked before shipping from the factory. The de-
vice will have a 16-byte (8-word) ESN in the security region. The ESN occupies addresses 000000h to 00000Fh
in byte mode or 000000h to 000007h in word mode.
35
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
TABLE 3. COMMAND DEFINITIONS
WA= Write Address
WD= Write Data
SA= Sector Address
N-1= Word Count
WBL= Write Buffer Location
PWD= Password
PWDn=Password word 0, word 1, word n
ID1/ID2/ID3: Refer to Table 2-2 for detail ID.
Comm-
and
Read
Mode
Reset
Mode
Automatic Select Security
Sector
Region
Exit Security
Sector
Silicon ID Device ID Factory Protect
Verify
Sector Protect Verify
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1st Bus
Cycle
Addr Addr XXX 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA
Data Data F0 AA AA AA AA AA AA AA AA AA AA AA AA
2nd Bus
Cycle
Addr 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555
Data 55 55 55 55 55 55 55 55 55 55 55 55
3rd Bus
Cycle
Addr 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA 555 AAA
Data 90 90 90 90 90 90 90 90 88 88 90 90
4th Bus
Cycle
Addr X00 X00 X01 X02 X03 X06 (Sector)
X02
(Sector)
X04 XXX XXX
Data C2h C2h ID1 ID1 99/19(H)
89/09(L) 00/01 00/01 00 00
5th Bus
Cycle
Addr X0E X1C
Data ID2 ID2
6th Bus
Cycle
Addr X0F X1E
Data ID3 ID3
Comm-
and
Program
Write to
Buffer
Program
Write to
Buffer
Program
Abort Reset
Write to
Buffer
Program
conrm
Chip Erase Sector
Erase CFI Read
Program/
Erase
Suspend
Program/
Erase
Resume
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1st Bus
Cycle
Addr 555 AAA 555 AAA 555 AAA SA SA 555 AAA 555 AAA 55 AA xxx xxx xxx xxx
Data AA AA AA AA AA AA 29 29 AA AA AA AA 98 98 B0 B0 30 30
2nd Bus
Cycle
Addr 2AA 555 2AA 555 2AA 555 2AA 555 2AA 555
Data 55 55 55 55 55 55 55 55 55 55
3rd Bus
Cycle
Addr 555 AAA SA SA 555 AAA 555 AAA 555 AAA
Data A0 A0 25 25 F0 F0 80 80 80 80
4th Bus
Cycle
Addr Addr Addr SA SA 555 AAA 555 AAA
Data Data Data N-1 N-1 AA AA AA AA
5th Bus
Cycle
Addr WA WA 2AA 555 2AA 555
Data WD WD 55 55 55 55
6th Bus
Cycle
Addr WBL WBL 555 AAA Sec-
tor
Sec-
tor
Data WD WD 10 10 30 30
36
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Command
Deep Power Down Password Protection
Enter Exit
Password
Command Set
Entry
Password
Program
Password
Read
Password
Unlock
Password
Command Set
Exit
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1st Bus
Cycle
Addr 555 AAA XXX XXX 555 AAA XXX XXX X00 X00 00 00 XXX XXX
Data AA AA AB AB AA AA A0 A0 PWD0 PWD0 25 25 90 90
2nd Bus
Cycle
Addr 2AA 555 2AA 555 PWA PWA X01 X01 00 00 XXX XXX
Data 55 55 55 55 PWD PWD PWD1 PWD1 03 03 00 00
3rd Bus
Cycle
Addr XXX XXX 555 AAA X02 X02 X00 X00
Data B9 B9 60 60 PWD2 PWD2 PWD0 PWD0
4th Bus
Cycle
Addr X03 X03 X01 X01
Data PWD3 PWD3 PWD1 PWD1
5th Bus
Cycle
Addr X04 X02 X02
Data PWD4 PWD2 PWD2
6th Bus
Cycle
Addr X05 X03 X03
Data PWD5 PWD3 PWD3
7th Bus
Cycle
Addr X06 00 X04
Data PWD6 29 PWD4
8th Bus
Cycle
Addr X07 X05
Data PWD7 PWD5
9th Bus
Cycle
Addr X06
Data PWD6
10th Bus
Cycle
Addr X07
Data PWD7
11th Bus
Cycle
Addr 00
Data 29
37
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Command
Lock Register Global Non-Volatile
Lock register
Command
Set Entry
Program Read
Lock register
Command
Set Exit
SPB
Command
Set Entry
SPB
Program
All SPB
Erase
SPB Status
Read
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1st Bus
Cycle
Addr 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX SA SA
Data AA AA A0 A0 DATA DATA 90 90 AA AA A0 A0 80 80 00/01 00/01
2nd Bus
Cycle
Addr 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA 00 00
Data 55 55 Data Data 00 00 55 55 00 00 30 30
3rd Bus
Cycle
Addr 555 AAA 555 AAA
Data 40 40 C0 C0
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
Command
Global Non-
Volatile Global Volatile Freeze Volatile
SPB
Command
Set Exit
SPB Lock
Command
Set Entry
SPB Lock
Set
SPB Lock
Status Read
SPB Lock
Command
Set Exit
DPB
Command
Set Entry
DPB Set DPB Clear
Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte Word Byte
1st Bus
Cycle
Addr XXX XXX 555 AAA XXX XXX XXX XXX XXX XXX 555 AAA XXX XXX XXX XXX
Data 90 90 AA AA A0 A0 00/01 00/01 90 90 AA AA A0 A0 A0 A0
2nd Bus
Cycle
Addr XXX XXX 2AA 555 XXX XXX XXX XXX 2AA 555 SA SA SA SA
Data 00 00 55 55 00 00 00 00 55 55 00 00 01 01
3rd Bus
Cycle
Addr 555 AAA 555 AAA
Data 50 50 E0 E0
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
Command
Volatile
DPB Status
Read
DPB Command
Set Exit
Word Byte Word Byte
1st Bus
Cycle
Addr SA SA XXX XXX
Data 00/01 00/01 90 90
2nd Bus
Cycle
Addr XXX XXX
Data 00 00
3rd Bus
Cycle
Addr
Data
4th Bus
Cycle
Addr
Data
5th Bus
Cycle
Addr
Data
Notes:
* It is not recommended to adopt any other code not in the command denition table which will potentially enter
the hidden mode.
* For the SPB Lock and DPB Status Read "00" means lock (protect), "01" means unlock (unprotect).
38
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Table 4-1. CFI mode: Identication Data Values
(All values in these tables are in hexadecimal)
Table 4-2. CFI mode: System Interface Data Values
COMMON FLASH MEMORY INTERFACE (CFI) MODE
QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE (CFI) MODE
The device features CFI mode. Host system can retrieve the operating characteristics, structure and vendor-
specied information such as identifying information, memory size, byte/word conguration, operating voltages
and timing information of this device by CFI mode. If the system writes the CFI Query command "98h", to ad-
dress "55h"/"AAh" (depending on Word/Byte mode), the device will enter the CFI Query Mode, any time the de-
vice is ready to read array data. The system can read CFI information at the addresses given in Table 4.
Once user enters CFI query mode, user can issue reset command to exit CFI mode and return to read array
mode. The unused CFI area is reserved by Macronix.
Description Address (h)
(Word Mode)
Address (h)
(Byte Mode) Data (h)
Vcc supply minimum program/erase voltage 1B 36 0027
Vcc supply maximum program/erase voltage 1C 38 0036
VPP supply minimum program/erase voltage 1D 3A 0000
VPP supply maximum program/erase voltage 1E 3C 0000
Typical timeout per single word/byte write, 2n us 1F 3E 0003
Typical timeout for maximum-size buffer write, 2n us (00h, not
support) 20 40 0006
Typical timeout per individual block erase, 2n ms 21 42 0009
Typical timeout for full chip erase, 2n ms (00h, not support) 22 44 0013
Maximum timeout for word/byte write, 2n times typical 23 46 0003
Maximum timeout for buffer write, 2n times typical 24 48 0005
Maximum timeout per individual block erase, 2n times typical 25 4A 0003
Maximum timeout for chip erase, 2n times typical (00h, not
support) 26 4C 0002
Description Address (h)
(Word Mode)
Address (h)
(Byte Mode) Data (h)
Query-unique ASCII string "QRY"
10 20 0051
11 22 0052
12 24 0059
Primary vendor command set and control interface ID code 13 26 0002
14 28 0000
Address for primary algorithm extended query table 15 2A 0040
16 2C 0000
Alternate vendor command set and control interface ID code 17 2E 0000
18 30 0000
Address for alternate algorithm extended query table 19 32 0000
1A 34 0000
39
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Table 4-3. CFI mode: Device Geometry Data Values
Description Address (h)
(Word Mode)
Address (h)
(Byte Mode) Data (h)
Device size = 2n in number of bytes 27 4E 0019
Flash device interface description (02=asynchronous x8/x16) 28 50 0002
29 52 0000
Maximum number of bytes in buffer write = 2n (00h, not support) 2A 54 0006
2B 56 0000
Number of erase regions within device (01h:uniform, 02h:boot) 2C 58 0001
Index for Erase Bank Area 1:
[2E,2D] = # of same-size sectors in region 1-1
[30, 2F] = sector size in multiples of 256K-bytes
2D 5A 00FF
2E 5C 0000
2F 5E 0000
30 60 0002
Index for Erase Bank Area 2
31 62 0000
32 64 0000
33 66 0000
34 68 0000
Index for Erase Bank Area 3
35 6A 0000
36 6C 0000
37 6E 0000
38 70 0000
Index for Erase Bank Area 4
39 72 0000
3A 74 0000
3B 76 0000
3C 78 0000
40
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Table 4-4. CFI mode: Primary Vendor-Specic Extended Query Data Values
Description Address (h)
(Word Mode)
Address (h)
(Byte Mode) Data (h)
Query - Primary extended table, unique ASCII string, PRI
40 80 0050
41 82 0052
42 84 0049
Major version number, ASCII 43 86 0031
Minor version number, ASCII 44 88 0033
Unlock recognizes address (0= recognize, 1= don't recognize) 45 8A 0014
Erase suspend (2= to both read and program) 46 8C 0002
Sector protect (N= # of sectors/group) 47 8E 0001
Temporary sector unprotect (1=supported) 48 90 0000
Sector protect/Chip unprotect scheme 49 92 0008
Simultaneous R/W operation (0=not supported) 4A 94 0000
Burst mode (0=not supported) 4B 96 0000
Page mode (0=not supported, 01 = 4 word page, 02 = 8 word
page) 4C 98 0002
Minimum ACC(acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV 4D 9A 0095
Maximum ACC(acceleration) supply (0= not supported), [D7:D4]
for volt, [D3:D0] for 100mV 4E 9C 00A5
WP# Protection
04=Uniform sectors bottom WP# protect
05=Uniform sectors top WP# protect
4F 9E 0004/
0005
Program Suspend (0=not supported, 1=supported) 50 A0 0001
41
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
ABSOLUTE MAXIMUM STRESS RATINGS
OPERATING TEMPERATURE AND VOLTAGE
ELECTRICAL CHARACTERISTICS
Surrounding Temperature with Bias -65°C to +125°C
Storage Temperature -65°C to +150°C
Voltage Range
VCC -0.5V to +4.0 V
VI/O -0.5V to +4.0 V
A9 , WP#/ACC -0.5V to +10.5 V
The other pins. -0.5V to Vcc +0.5V
Output Short Circuit Current (less than one second) 200 mA
Industrial (I) Grade Surrounding Temperature (TA )-40°C to +85°C
VCC Supply Voltages
Full VCC range +2.7 V to 3.6 V
Regulated VCC range +3.0 V to 3.6 V
VI/O range 1.65V to VCC
NOTICE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage
to the device. This is stress rating only and functional operational sections of this specication is not implied.
Exposure to absolute maximum rating conditions for extended period may affect reliability.
2. Specications contained within the following tables are subject to change.
3. During voltage transitions, all pins may overshoot GND to -2.0V and Vcc to +2.0V for periods up to 20ns, see
Figures below.
Maximum Negative Overshoot Waveform Maximum Positive Overshoot Waveform
GND
GND - 2.0V
20ns 20ns
20ns
Vcc + 2.0V
Vcc
20ns 20ns
20ns
42
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
DC CHARACTERISTICS
Symbol Description Min Typ Max Remark
Iilk Input Leak ±2.0uA
Iilk9 A9 Leak 35uA A9=10.5V
Iolk Output Leak ±1.0uA
Icr1 Read Current
6mA 20mA
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=1MHz, Byte Mode
30mA 50mA
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=5MHz, Byte Mode
60mA 100mA
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=10MHz
Icr2 VCC Page Read Current
2mA 10mA
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=10MHz
5mA 20mA
CE#=Vil, OE#=Vih,
Vcc=Vccmax;
f=33MHz
Iio VIO non-active current 0.2mA 10mA
Icw Write Current 26mA 30mA CE#=Vil, OE#=Vih,
WE#=Vil
Isb Standby Current 30uA 100uA Vcc=Vcc max, other
pin disable
Isbr Reset Current 30uA 100uA
Vcc=Vccmax,
RESET# enable,
other pin disable
Isbs Sleep Mode Current 30uA 100uA
Idpd Vcc deep power down current 10uA
Icp1 Accelerated Pgm Current, WP#/Acc
pin(Word/Byte) 5mA 10mA CE#=Vil, OE#=Vih
Icp2 Accelerated Pgm Current, Vcc pin,
(Word/Byte) 20mA 30mA CE#=Vil, OE#=Vih
Vil Input Low Voltage -0.1V 0.3xVI/O
Vih Input High Voltage 0.7xVI/O VI/O+0.3V
Vhv Very High Voltage for Auto Select/
Accelerated Program 9.5V 10.5V
Vol Output Low Voltage 0.45V Iol=100uA
Voh Ouput High Voltage 0.85xVI/O Ioh=-100uA
Vlko Low Vcc Lock-out voltage 2.3V 2.5V
Note: Sleep mode enables the lower power when address remain stable for taa+30ns.
43
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
SWITCHING TEST CIRCUITS
SWITCHING TEST WAVEFORMS
Test Condition
Output Load Capacitance, CL : 1TTL gate, 30pF
Rise/Fall Times : 5ns
Input Pulse levels :0.0 ~ VI/O
In/Out reference levels :0.5VI/O
Test Points
VI/O
VI/O / 2VI/O / 2
0.0V
OUTPUT
INPUT
DEVICE UNDER
TEST
CL
3.3V
6.2KΩ
2.7KΩ
44
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
AC CHARACTERISTICS
Symbol Description
29GL256E
(VCC=2.7V~3.6V)
29GL256E
(VCC=3.0V~3.6V) Unit
Min. Typ. Max. Min. Typ. Max.
Taa Valid data output after address VI/O=VCC 100 90 ns
VI/O=1.65 toVCC 110 110 ns
Tpa Page access time VI/O=VCC 25 25 ns
VI/O=1.65 toVCC 30 30 ns
Tce Valid data output after CE# low VI/O=VCC 100 90 ns
VI/O=1.65 toVCC 110 110 ns
Toe Valid data output after OE# low VI/O=VCC 25 25 ns
VI/O=1.65 toVCC 30 30 ns
Tdf Data output oating after OE# high or CE# high 20 20 ns
Tsrw Latency between read and write operation (Note) 35 35 ns
Toh Output hold time from the earliest rising edge of
address, CE#, OE# 0 0 ns
Trc Read period time 100 90 ns
Twc Write period time 100 90 ns
Tcwc Command write period time 100 90 ns
Tas Address setup time 0 0 ns
Taso Address setup time to OE# low during toggle bit
polling 15 15 ns
Tah Address hold time 45 45 ns
Taht Address hold time from CE# or OE# high during
toggle bit polling 0 0 ns
Tds Data setup time 30 30 ns
Tdh Data hold time 0 0 ns
Tvcs Vcc setup time 500 500 us
Tcs Chip enable Setup time 0 0 ns
Tch Chip enable hold time 0 0 ns
Toes Output enable setup time 0 0 ns
Toeh Output enable hold time
Read 0 0 ns
Toggle & Data#
Polling 10 10 ns
Tws WE# setup time 0 0 ns
Twh WE# hold time 0 0 ns
Tcepw CE# pulse width 35 35 ns
Tcepwh CE# pulse width high 30 30 ns
Twp WE# pulse width 35 35 ns
Twph WE# pulse width high 30 30 ns
Tbusy Program/Erase active time by
RY/BY#
VI/O=VCC 100 90 ns
VI/O=1.65 toVCC 110 110 ns
Tghwl Read recover time before write 0 0 ns
Tghel Read recover time before write 0 0 ns
45
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Symbol Description
29GL256E
(VCC=2.7V~3.6V)
29GL256E
(VCC=3.0V~3.6V) Unit
Min. Typ. Max. Min. Typ. Max.
Twhwh1 Program operation Byte 11 11 us
Twhwh1 Program operation Word 11 11 us
Twhwh1 Acc program operation (Word/Byte) 11 11 us
Twhwh2 Sector erase operation 0.6 5 0.6 5 sec
Tbal Sector add hold time 50 50 us
Trdp Release from deep power down mode 200 200 us
Note : Not 100% tested.
46
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 1. COMMAND WRITE OPERATION
Addresses
CE#
OE#
WE#
DIN
Tds
Tah
Data
Tdh
Tcs Tch
Tcwc
Twph
Twp
Toes
Tas
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
VA
VA: Valid Address
47
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Addresses
CE#
OE#
Taa
WE#
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh
Vol
HIGH Z HIGH Z
DATA Valid
Toe
Toeh Tdf
Tce
Trc
Outputs
Toh
ADD Valid
Tsrw
48
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 3. RESET# TIMING WAVEFORM
Trh
Trb1
Trp2
Trp1
Tready2
Tready1
RY/BY#
CE#, OE#
RESET#
Reset Timing NOT during Automatic Algorithms
Reset Timing during Automatic Algorithms
RY/BY#
CE#, OE#
Trb2
WE#
RESET#
AC CHARACTERISTICS
Item Description Setup Speed Unit
Trp1 RESET# Pulse Width (During Automatic Algorithms) MIN 10 us
Trp2 RESET# Pulse Width (NOT During Automatic Algorithms) MIN 500 ns
Trh RESET# High Time Before Read MIN 200 ns
Trb1 RY/BY# Recovery Time (to CE#, OE# go low) MIN 0 ns
Trb2 RY/BY# Recovery Time (to WE# go low) MIN 50 ns
Tready1 RESET# PIN Low (During Automatic Algorithms) to Read or Write MAX 20 us
Tready2 RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns
49
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
Twc
Address
OE#
CE#
55h
2AAh 555h
10h
In
Progress Complete
VA VA
Tas Ta h
Tghwl
Tch
Twp
Tds Tdh
Twhwh2
Read Status
Last 2 Erase Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
50
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
YES
NO Data=FFh ?
Write Data 10H Address 555H
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Chip Erase Completed
51
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Twc
Address
OE#
CE#
55h
2AAh Sector
Address 1
Sector
Address 0
30h
In
Progress Complete
VA VA
30h
Sector
Address n
Tas
Tah
Tbal
Tghwl
Tch
Twp
Tds Tdh
Twhwh2
Read Status
Last 2 Erase Command Cycle
Tbusy
Trb
Tcs Twph
WE#
Data
RY/BY#
30h
52
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data AAH Address 555H
Write Data 80H Address 555H
Write Data 30H Sector Address
Write Data 55H Address 2AAH
Data# Polling Algorithm or
Toggle Bit Algorithm
Auto Sector Erase Completed
NO
Last Sector
to Erase
YES
YES
NO
Data=FFh
53
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
Toggle Bit checking Q6
not toggled
ERASE SUSPEND
YES
NO
Write Data 30H
Continue Erase
Reading or
Programming End
Read Array or
Program
Another
Erase Suspend ? NO
YES
YES
NO
ERASE RESUME
54
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
Figure 10. ACCELERATED PROGRAM TIMING DIAGRAM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Tah
Tghwl
Tch
Twp
Tds Tdh
Twhwh1
Last 2 Read Status CycleLast 2 Program Command Cycle
Tbusy Trb
Tcs Twph
WE#
Data
RY/BY#
WP#/ACC
Vcc
250ns 250ns
Vhv (9.5V ~ 10.5V)
Vil or Vih Vil or Vih
Tvcs
Vcc (min)
GND
55
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM
Address
OE#
CE#
A0h
555h PA
PD Status DOUT
VA VA
Tas Ta h
Tghwl
Tcepw
Tds Tdh
Twhwh1 or Twhwh2
Tbusy
Tcepwh
WE#
Data
RY/BY#
56
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Program Data/Address
Write Data A0H Address 555H
YES
Read Again Data:
Program Data?
YES
Auto Program Completed
Data# Polling Algorithm or
Toggle Bit Algorithm
next address
Last Word to be
Programed
No
No
57
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 13. SILICON ID READ TIMING WAVEFORM
Ta a Ta a Taa Ta a
Tce
To e
To h Toh Toh To h
Tdf
DATA OUT
Manufacturer ID Device ID
Cycle 1
Device ID
Cycle 2
Device ID
Cycle 3
Vhv
Vih
Vil
ADD
A9
ADD
CE#
A1
OE#
WE#
ADD
A0
DATA OUT DATA OUT DATA OUT
DATA
Q15~Q0
VCC 3V
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
A2
Disable
Enable
58
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
WRITE OPERATION STATUS
Figure 14. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tdf
Tce
Tch
Toe
Toeh
Toh
CE#
OE#
WE#
Q7
Q6~Q0
RY/BY#
Tbusy
Status Data Status Data
ComplementComplement True Valid Data
Taa
Trc
Address VAVA
High Z
High Z
Valid DataTrue
59
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
Read Q7~Q0 at valid address
(Note 1)
Read Q7~Q0 at valid address
Start
Q7 = Data# ?
Q5 = 1 ?
Q7 = Data# ?
(Note 2)
FAIL Pass
No
No
No
Yes
Yes
Yes
Figure 15. STATUS POLLING FOR WORD PROGRAM/ERASE
60
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 16. STATUS POLLING FOR WRITE BUFFER PROGRAM
Read Q7~Q0 at last write
address (Note 1)
Start
Q7 = Data# ?
Q1=1 ?
Only for write
buffer program
Q7 = Data# ?
(Note 2)
FAIL Pass
Write Buffer Abort
No
No
No
No
No
Yes
Yes
Q5=1 ?
Yes
Yes
Yes
Read Q7~Q0 at last write
address (Note 1)
Q7 = Data# ?
(Note 2)
Read Q7~Q0 at last write
address (Note 1)
Notes:
1. For programming, valid address means program address.
For erasing, valid address means erase sectors address.
2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
61
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 17. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tdf
Taht Taso
Tce
Tch
Toe
Toeh
Taa
Trc
Toh
Address
CE#
OE#
WE#
Q6/Q2
RY/BY#
Tbusy
Valid Status
(first read)
Valid Status
(second read) (stops toggling)
Valid Data
VA VA
VA
VA : Valid Address
VA
Valid Data
62
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 18. TOGGLE BIT ALGORITHM
Notes:
1. Read toggle bit twice to determine whether or not it is toggling.
2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
Read Q7-Q0 Twice
Q5 = 1?
Read Q7~Q0 Twice
PGM/ERS fail
Write Reset CMD PGM/ERS Complete
Q6 Toggle ?
Q6 Toggle ?
NO
(Note 1)
YES
NO
NO
YES
YES
Start
63
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 19. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to
word mode)
AC CHARACTERISTICS
WORD/BYTE CONFIGURATION (BYTE#)
Parameter Description Test
Setup All Speed Options Unit
Tel/Telfh CE# to BYTE# from L/H Max. 5 ns
Tqz BYTE# from L to Output Hiz Max. 30 ns
Tfhqv BYTE# from H to Output Active Min. 90 ns
Figure 20. PAGE READ TIMING WAVEFORM
Tfhqv
Telfh
DOUT
(Q0-Q7)
DOUT
(Q0-Q14)
VA DOUT
(Q15)
CE#
OE#
BYTE#
Q0~Q14
Q15/A-1
Amax:A3
(A-1),A0,A1,A2
DATA
CE#/OE#
Note: CE#, OE# are enable.
Page size is 8 words in Word mode, 16 bytes in Byte mode.
Address are A2~A0 for Word mode, A2~A-1 for Byte mode.
VALID ADD
Data 1 Data 2 Data 3
1'st ADD 2'nd ADD
tpa
taa
3'rd ADD
tpa
64
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 21. DEEP POWER DOWN MODE WAVEFORM
CEB
WEB
ADD
DATA
XX
B9
2AA55
tDP
XX (don't care)
AB
Standby mode
AA 55
Deep power down mode
tRDP
Standby mode
ITEM TYP MAX
WEB high to release from deep power down mode tRDP 100us 200us
WEB high to deep power down mode tDP 10us 20us
AC CHARACTERISTICS
65
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
Figure 22. WRITE BUFFER PROGRAM FLOWCHART
Write CMD: Data=AAh, Addr=555h
Write CMD: Data=55h, Addr=2AAh
Write CMD: Data=25h, Addr=SA
SA: Sector Address of to be Programmed page
Write CMD: Data=PWC, Addr=SA
PWC: Program Word Count
Write CMD:
Data=PGM_data, Addr=PGM_addr
PWC =0?
Write CMD: Data=29h, Addr=SA
Polling Status
Yes
Pass
No
No
Write Buffer Abort
Write reset CMD
to return to read Mode
PWC=PWC-1No
Fail
Yes
Want to Abort ?
Yes
No
No
Yes
Return to read Mode
Write Abort reset CMD
to return to read Mode
Write a different sector
address to cause Abort
Yes
66
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
RECOMMENDED OPERATING CONDITIONS
At Device Power-Up
AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-
up (e.g. Vcc and CE# ramp up simultaneously). If the timing in the gure is ignored, the device may not operate
correctly.
Figure A. AC Timing at Device Power-Up
Vcc
ADDRESS
CE#
WE#
OE#
DATA
Tvr
Taa
Tr or Tf Tr or Tf
Tce
Tf
Vcc(min)
GND
VIO
VIO(min)
GND
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Vih
Vil
Voh High Z
Vol
WP#/ACC
Valid
Ouput
Valid
Address
Tvcs
Tvr Tvios
Tr
Toe
Tf Tr
Symbol Parameter Min. Max. Unit
Tvr Vcc Rise Time 20 500000 us/V
Tr Input Signal Rise Time 20 us/V
Tf Input Signal Fall Time 20 us/V
Tvcs Vcc Setup Time 500 us
Tvios VIO Setup Time 500 us
Notes:
1. Not test 100%.
2. VIO<VCC+200mV.
67
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
LATCH-UP CHARACTERISTICS
ERASE AND PROGRAMMING PERFORMANCE
PIN CAPACITANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0V VCC. Programming specica-
tions assume checkboard data pattern.
2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and
including 100,000 program/erase cycles.
3. Erase/Program cycles comply with JEDEC JESD-47 & 22-A117 standard.
4. Exclude 00h program before erase operation.
Parameter Symbol Parameter Description Test Set TYP MAX UNIT
CIN2 Control Pin Capacitance VIN=0 7.5 17 pF
COUT Output Capacitance VOUT=0 8.5 12 pF
CIN Input Capacitance VIN=0 6 7.5 pF
MIN. MAX.
Input Voltage voltage difference with GND on WP#/ACC and A9 pins -1.0V 10.5V
Input Voltage voltage difference with GND on all normal pins input -1.0V 1.5Vcc
Vcc Current -100mA +100mA
All pins included except Vcc. Test conditions: Vcc = 3.0V, one pin per testing
PARAMETER LIMITS UNITS
MIN. TYP. (1) MAX. (2)
Chip Erase Time 128 300 sec
Sector Erase Time 0.6 5 sec
Chip Programming Time 100 350 sec
Word Program Time 11 360 us
Total Write Buffer Time 200 us
ACC Total Write Buffer Time 100 us
Erase/Program Cycles 100,000 Cycles
DATA RETENTION
PARAMETER Condition Min. Max. UNIT
Data retention 55˚C 20 years
68
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
ORDERING INFORMATION
PART NO. ACCESS TIME (ns) PACKAGE Remark
MX29GL256EHMC-90Q * 90 70 Pin SSOP VI/O=VCC
MX29GL256EHXFI-90Q 90 64 LFBGA VI/O=VCC
MX29GL256ELXFI-90Q 90 64 LFBGA VI/O=VCC
MX29GL256EHXCI-90Q 90 64 FBGA VI/O=VCC
MX29GL256ELXCI-90Q 90 64 FBGA VI/O=VCC
MX29GL256EHT2I-90Q 90 56 Pin TSOP VI/O=VCC
MX29GL256ELT2I-90Q 90 56 Pin TSOP VI/O=VCC
MX29GL256EUXFI-11G 110 64 LFBGA VI/O=1.65 to VCC
MX29GL256EDXFI-11G 110 64 LFBGA VI/O=1.65 to VCC
MX29GL256EUT2I-11G 110 56 Pin TSOP VI/O=1.65 to VCC
MX29GL256EDT2I-11G 110 56 Pin TSOP VI/O=1.65 to VCC
Note :
* 70-pin SSOP only for Pachinko Socket.
69
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
PART NAME DESCRIPTION
MX 29 GL 90
E H T2 I Q
OPTION:
Q: RoHS compliant with restricted Vcc: 3.0V~3.6V (Note 1)
G: RoHS compliant with Vcc: 2.7V~3.6V
SPEED:
90: 90ns
11: 110ns
TEMPERATURE RANGE:
I: Industrial (-40° C to 85° C)
PACKAGE:
PRODUCT TYPE (Protection when WP#=VIL):
H: VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected
L: VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected
U: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected
D: VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected
REVISION:
E
DENSITY & MODE:
256: 256Mb x8/x16 Architecture
GL: 3V Page Mode
TYPE:
DEVICE:
29:Flash
256
T2: 56-TSOP
M: 70SSOP
XF: LFBGA (11mm x 13mm)
XC: FBGA (10mm x 13mm)
Note 1: 90Q covers 2.7V~3.6V for 100ns and 3.0V~3.6V for 90ns
70
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
PACKAGE INFORMATION
71
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
72
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
73
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
74
P/N:PM1499 REV. 1.4, JUL. 26, 2011
MX29GL256E
REVISION HISTORY
Revision No. Description Page Date
1.0 1. Revised 70-SSOP ground pin congurations P4 APR/28/2009
2. Added overshoot & undershoot specications P41
3. Removed "Preliminary" P2
4. Changed data retention from 10 years to 20 years P2,65
5. Modied Tdf (max.) = 20ns P44
1.1 1. Added 1.8V VI/O information P2,41,44 JUN/29/2009
P68,69
2. Modied Tsrw (min.) = 35ns P44
3. Added Icr2 parameter and "status Polling for write buffer program" P42,60
owchart; revised Voh remark
4. Added notes P45,68
5. Content correction P18,43
6. Modifed the title of Figure 16 as write buffer and added notes P60
1.2 1. Added unused CFI area reservation notice. P38 NOV/22/2010
2. Added wording "e.g. Vcc and CE# ramp up simultaneously" P66
3. Modied Figure A. AC Timing at Device Power-Up P66
4. Modied Timing waveform at Figure 10 and Figure 14 P54, 58
5. Modied "PIN CAPACITANCE" table P67
6. Modied environmental hazzardous substance wording P2,69
7. Modied Figure 2. READ TIMING WAVEFORMS P47
1.3 1. Modied Figure 16. Status Polling For Write Buffer Program P60 JUN/03/2011
2. Announced "Not recommended for new designs" P1,2
3. Modied the description of Write Buffer Programming Operation P18
1.4 1. Added Tdf spec for CE# high P44 JUL/26/2011
2. Added the parameter for VIO setup up time P66
75
MX29GL256E
MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specications without notice.
Except for customized products which has been expressly identied in the applicable agreement, Macronix's
products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or
household applications only, and not for use in any applications which may, directly or indirectly, cause death,
personal injury, or severe property damages. In the event Macronix products are used in contradicted to their
target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualied for its
actual use in accordance with the applicable laws and regulations; and Macronix as well as it’s suppliers and/or
distributors shall be released from any and all liability arisen therefrom.
Copyright© Macronix International Co., Ltd. 2008~2011. All rights reserved.
Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash,
XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered
trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identication
purposes only and may be claimed as the property of the respective companies.
For the contact and order information, please visit Macronix’s Web site at: http://www.macronix.com
