Spread Aware™, Zero Delay Buf f er
W162
Cypress Semiconductor Corporation •3901 North First Street •San Jose •CA 95134 •408-943-2600
Document #: 38-07150 Rev. *A Revised December 14, 02
Features
• Spread Aware™—designed to work with SSFTG
reference signals
• Two banks of four outputs, plus the fed back output
• Outputs may be three-stated
• Available in 16-pin SOIC or SSOP package
• Extra strength output drive available (-19 version)
• Internal feedback
Key Specificati ons
Operati ng Voltage: ........................... ...... ...... ..... ... 3.3V±10%
Operating Range: ................................ 15 < fOUT < 133 MHz
Cycle-to -Cyc le Jit ter: .............................. ...... ..... ...... ... 25 0 ps
Output to Output Ske w: ................... ...... ...... ..... ...... ... 15 0 ps
Propagati on Dela y:...................... ..... ...... ...... .............. 15 0 ps
Table 1. Input Logic
SEL1 SEL0 QA0:3 QB0:3 PLL QFB
00Three-
State Three-
State Shutdown Active
01ActiveThree-
State Active,
Utilized Active
1 0 Active Active Shutdown,
Bypassed Active
1 1 Active Active Active,
Utilized Active
Spread Aware is a trademark of Cypress Semiconductor Corporation.
Block Diagram Pin Configuration
PLL
REF MUX
QA1
QA2
QA3
QB0
QB1
SEL0
QB2
QB3
SEL1
QFB
QA3
QA2
VDD
GND
QB3
QB2
SEL0
16
15
14
13
12
11
10
9
REF
QA0
QA1
VDD
GND
QB0
QB1
SEL1
1
2
3
4
5
6
7
8
QFB
QA0
W162
Document #: 38-07150 Rev. *A Page 2 of 7
Overview
The W162 products are nine-output zero delay buffers. A
Phase-Locked Loop (PLL) is used to take a time-varying signal
and provide eight copies of that same signal out.
Internal feedback is used to maximize the number of output
signals provided in the 16-pin package.
Spread Aware
Many s ystem s bei ng des igned n ow ut ilize a te chnol ogy ca lled
Spread Spe ctrum Frequen cy T iming Ge neration. Cypre ss has
been one of the pioneer s of SSFTG deve lopment, an d we de-
signed this product so as not to filter off the Spread Spectrum
feature of the Reference input, assuming it exists. When a
zero delay buffer is not designed to pass the SS feature
through, the result is a significant amount of tracking skew
which m ay cau se p r ob lem s in s y ste ms re qu irin g synchron iz a-
tion.
For more details on Spread Spectrum timing technology,
please see the Cyp ress App licat ion not e titled , “EMI Sup pres-
sion Techniques with Spread Spectrum Frequency Timing
Generator (SSFTG) ICs.”
Functional Description
Logic inp uts prov id e the us er th e abi lity to turn of f on e or bo th
banks of cl ocks when no t in use, as de scrib ed in Table 1. Dis-
abling a bank of unused outputs will reduce jitter and power
consumption, and will also reduce the amount of EMI gener-
ated by the W162.
These same inputs allow the user to bypass the PLL entirely
if so desired. When this is done, the device no longer acts as
a zero dela y bu ffer, it simply reve rts to a standard nine-output
clock drive r.
Pin Definitions
Pin Name Pin No. Pin
Type Pin Description
REF 1 I Reference Input: The output signals QA0:3 through QB0:3 will be synchro-
nized to this signal unless the device is programmed to bypass the PLL.
QFB 16 O Feedback Output: Thi s signal is us ed as the fee dback inter nal ly to e stabl ish
the propagation delay of nearly 0.
QA0:3 2, 3, 14, 15 O Outputs from Bank A: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
QB0:3 6, 7, 10, 11 O Outputs from Bank B: The frequency of the signals provided by these pins
is equal to the signal connected to REF.
VDD 4, 13 P Power Connections: Connect to 3.3V . Use ferrite beads to help reduce noise
for optimal jitter performance.
GND 5, 12 P Ground Connections: Connect all grounds to the common system ground
plane.
SEL0:1 9, 8 I Function Select Inputs: Tie to VDD (HIGH, 1) or GND (LOW, 0) as desired
per Table 1.
W162
Document #: 38-07150 Rev. *A Page 3 of 7
Absolute Maximum Ratings[1]
Stresses greater than those lis ted in this ta ble may c ause per-
manent damage to the device. These represent a stress rating
only. Operation of the device at these or any other conditions
above those specifie d i n the operati ng se ct ions of t his s pe cif i-
cation is not implied. Maximum conditions for extended peri-
ods ma y af fe ct r eli abi li ty
.
Parameter Description Rating Unit
VDD, VIN Voltage on any pin with respect to GND –0.5 to +7.0 V
TSTG Storage Temperature –65 to +150 °C
TAOperating Temperature 0 to +70 °C
TBAmbient Temperature under Bias –55 to +125 °C
PDPower Dissipation 0.5 W
DC Electrical Characteristics: TA =0°C to 70°C, VDD = 3.3V ±10%
Parameter Description Test Condition Min Typ Max Unit
IDD Supply Current Unloaded, 100 MHz 40 mA
VIL Input Low Voltage 0.8 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 12 mA (-19)
IOL = 8 mA (-9) 0.4 V
VOH Output High Voltage IOL = 12 mA (-19)
IOL = 8 mA (-9) 2.4 V
IIL Input Low Current VIN = 0V –500 µA
IIH Input High Current VIN = VDD 10 µA
AC Electrical Characteristics: TA = 0°C to +70°C, VDD = 3.3V ±10%
Parameter Description Test Condition Min Typ Max Unit
fIN Input Frequency 15 133 MHz
fOUT Output Freq uen cy 15-pF load[6] 15 133 MHz
tROutput Rise Time (-09)[2] 2.0 to 0.8V, 15-pF load 2 2.5 ns
Output Rise Time (-19)[2] 2.0 to 0.8V, 20-pF load 1.5 ns
tFOutput Fal l Time (-09)[2] 2.0 to 0.8V, 15-pF load 2 2.5 ns
Output Rise Time (-19)[2] 2.0 to 0.8V, 20-pF load 1.5 ns
tPD FBIN to REF Skew[3, 4] Measured at VDD/2 150 ps
tSK Output to Output Skew All outputs loaded equally 150 ps
tDDuty Cycle 15-pF load[5] 45 50 55 %
tLOCK PLL Lock Time Power supply stable 1.0 ms
tJC Jitter, Cycle-to-Cycle 250 ps
Notes:
1. Multip le Sup pli es: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
2. Long input rise and fall time will degrade skew and jitter performance.
3. All AC specifications are measured with a 50Ω tra nsm issi on line, l oad termin ate d with 50Ω to 1.4V.
4. Skew is measured at VDD/2 on rising edges.
5. Duty cycle is measured at VDD/2
6. For the higher drive -19, the load is 20 pF.
W162
Document #: 38-07150 Rev. *A Page 4 of 7
Schematic
Ordering Information
Ordering Code Option Package
Name Package Type
W162 - 09, -19 G
H16-pin Plastic SOIC (150-mil)
16-pin Plastic SSOP (150-mil)
9
2
3
1
4
7
6
8
5
16
13
14
15
10
11
12
V
DD
V
DD
10
µ
F
0.1
µ
F
Ferrite
Bead
Ferrite
Bead
V
DD
or GND (for desired operation mode)V
DD
or GND (for desired operation mode)
Output
OutputOutput
Output
Ground
PowerPower
OutputRef In
Output
Output
Output
Output
Logic In Logic In
Ground
10
µ
F
0.1
µ
F
W162
Document #: 38-07150 Rev. *A Page 5 of 7
Package Diagrams
16-pin SSOP Small Shrunk Outline Package (SSOP, 150-mil)
W162
Document #: 38-07150 Rev. *A Page 6 of 7
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagrams (continued)
16-Pin Small Outlined Integrated Circuit (SOIC, 150-mil)
W162
Document #: 38-07150 Rev. *A Page 7 of 7
Document Title: W162 Spread Aware™. Zero Delay Buffer
Document Number: 38-07150
REV. ECN NO. Issue
Date Orig. of
Change Description of Change
** 110590 12/19/01 DSG Change from Spec number: 38-00788 to 38-07150
*A 122799 12/14/02 RBI Add Power up Requirements to Operating Conditions Information
