1
Features
•32-Mbit DataFlash and 4-Mbit SRAM
•Single 62-ball (8 mm x 12 mm x 1.2 mm) CBGA Package
•2.7V to 3.3V Operating Voltage
DataFlash
•Single 2.7V to 3.3V Supply
•Serial Peripheral Interface (SPI) Compatible
•20 MHz Max Clock Frequency
•Page Program Operation
– Single Cycle Reprogram (Erase and Program)
– 8192 Pages (528 Bytes/Page) Main Memory
•Supports Page and Block Erase Operations
•Two 528-byte SRAM Data Buffers – Allows Receiving of Data
while Reprogramming of Nonvolatile Memory
•Continuous Read Capability through Entire Array
– Ideal for Code Shadowing Applications
•Low Power Dissipation
– 4 mA Active Read Current Typical
– 2 µA CMOS Standby Current Typical
•Hardware Data Protection Feature
•Industrial Temperature Range
SRAM
•4-megabit (256K x 16)
•2.7V to 3.3V VCC
•70 ns Access Time
•Fully Static Operation and Tri-state Output
•1.2V (Min) Data Retention
•Industrial Temperature Range
32-megabit
DataFlash®
+ 4-megabit
SRAM
Stack Memory
AT45BR3214B
Rev. 3356B–DFLASH–10/04
2AT45BR3214B
3356B–DFLASH–10/04
Pin Configuration
AT45BR3214B
(Top View)
Pin Name Function
CS Chip Select
SCK Serial Clock
SI Serial Input
SO Serial Output
WP Write Protect
RESET Reset
RDY/BUSY READY BUSY
VCC Flash Power Supply
GND Flash Ground
A0 - A17 SRAM Address Input
I/O0 - I/O15 SRAM Data Inputs/Outputs
SLB SRAM Lower Byte
SUB SRAM Upper Byte
SVCC SRAM Power
SGND SRAM Ground
SCS1 SRAM Chip Select 1
SCS2 SRAM Chip Select 2
SWE SRAM Write Enable
SOE SRAM Output Enable
NC No Connect
A
B
C
D
E
F
G
H
12345678910
NC
NC
SI
A16
WP
SGND
NC
SLB
SO
NC
A11
A8
RDY/BUSY
RESET
NC
SUB
A17
A5
A15
A10
NC
SOE
A7
A4
A14
A9
I/O11
A6
A0
A13
I/O15
I/O13
I/O12
I/O9
A3
CS
A12
SWE
I/O6
SCS2
I/O10
I/O8
A2
GND
GND
I/O14
I/O4
SVCC
I/O2
I/O0
A1
SCK
NC
I/O7
I/O5
VCC
I/O3
I/O1
SCS1
NC
NC
NC
3
AT45BR3214B
3356B–DFLASH–10/04
Block Diagram
Description The AT45BR3214B combines a 32-megabit DataFlash (32M x 1) and a 4-megabit
SRAM (organized as 256K x 16) in a stacked 62-ball CBGA package. The stacked mod-
ule operates at 2.7V to 3.3V in the industrial temperature range.
32-Mbit
DataFlash
4-Mbit
SRAM
ADDRESS
DATA (I/O0 - I/O15)
RESET
CS
SCK
RDY/BUSY
SCS1
SCS2
WP SWESOESI
SO
Absolute Maximum Ratings
Temperature under Bias .................................. -40°C to +85°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -55°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground .....................................-0.2V to +3.3V
All Output Voltages
with Respect to Ground .....................................-0.2V to +0.2V
DC and AC Operating Range
AT45BR3214B
Operating Temperature (Case) Industrial -40°C - 85°C
VCC Power Supply 2.7V to 3.3V
4AT45BR3214B
3356B–DFLASH–10/04
32-Mbit DataFlash
Description
The 32-Mbit DataFlash is a 2.7-volt only, serial interface Flash memory ideally suited for
a wide variety of digital voice-, image-, program code- and data-storage applications.
Its 34,603,008 bits of memory are organized as 8192 pages of 528 bytes each. In addi-
tion to the main memory, the 32-Mbit DataFlash also contains two SRAM data buffers of
528 bytes each. The buffers allow receiving of data while a page in the main memory is
being reprogrammed, as well as reading or writing a continuous data-stream. EEPROM
emulation (bit or byte alterability) is easily handled with a self-contained three step
Read-Modify-Write operation. Unlike conventional Flash memories that are accessed
randomly with multiple address lines and a parallel interface, the DataFlash uses a SPI
serial interface to sequentially access its data. DataFlash supports SPI mode 0 and
mode 3. The simple serial interface facilitates hardware layout, increases system reli-
ability, minimizes switching noise, and reduces package size and active pin count. The
device is optimized for use in many commercial and industrial applications where high
density, low pin count, low voltage, and low power are essential. The device operates at
clock frequencies up to 20 MHz with a typical active read current consumption of 4 mA.
To allow for simple in-system reprogrammability, the 32-Mbit DataFlash does not
require high input voltages for programming. The device operates from a single power
supply, 2.7V to 3.3V, for both the program and read operations. The 32-Mbit DataFlash
is enabled through the chip select pin (CS) and accessed via a three-wire interface con-
sisting of the Serial Input (SI), Serial Output (SO), and the Serial Clock (SCK).
All programming cycles are self-timed, and no separate erase cycle is required before
programming. When the device is shipped from Atmel, the most significant page of the
memory array may not be erased. In other words, the contents of the last page may not
be filled with FFH.
DataFlash
Block Diagram
Memory Array To provide optimal flexibility, the memory array of the 32-Mbit DataFlash is divided into
three levels of granularity comprising of sectors, blocks, and pages. The Memory Archi-
tecture Diagram illustrates the breakdown of each level and details the number of pages
per sector and block. All program operations to the DataFlash occur on a page-by-page
basis; however, the optional erase operations can be performed at the block or page
level.
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)BUFFER 1 (528 BYTES)
I/O INTERFACE
SCK
CS
RESET
VCC
GND
RDY/BUSY
WP
SOSI
5
AT45BR3214B
3356B–DFLASH–10/04
Memory Architecture Diagram
Device Operation The device operation is controlled by instructions from the host processor. The list of
instructions and their associated opcodes are contained in Tables 1 through 4. A valid
instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode
and the desired buffer or main memory address location. While the CS pin is low, tog-
gling the SCK pin controls the loading of the opcode and the desired buffer or main
memory address location through the SI (serial input) pin. All instructions, addresses
and data are transferred with the most significant bit (MSB) first.
Buffer addressing is referenced in the datasheet using the terminology BFA9 - BFA0 to
denote the ten address bits required to designate a byte address within a buffer. Main
memory addressing is referenced using the terminology PA12 - PA0 and BA9 - BA0
where PA12 - PA0 denotes the 13 address bits required to designate a page address
and BA9 - BA0 denotes the ten address bits required to designate a byte address within
the page.
Read Commands By specifying the appropriate opcode, data can be read from the main memory or from
either one of the two data buffers. The DataFlash supports two categories of read
modes in relation to the SCK signal. The differences between the modes are in respect
to the inactive state of the SCK signal as well as which clock cycle data will begin to be
output. The two categories, which are comprised of four modes total, are defined as
Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0 or SPI
Mode 3. A separate opcode (refer to Table 1 on page 11 for a complete list) is used to
select which category will be used for reading. Please refer to the “Detailed Bit-level
Read Timing” diagrams in this datasheet for details on the clock cycle sequences for
each mode.
CONTINUOUS ARRAY READ: By supplying an initial starting address for the main
memory array, the Continuous Array Read command can be utilized to sequentially
read a continuous stream of data from the device by simply providing a clock signal; no
additional addressing information or control signals need to be provided. The DataFlash
incorporates an internal address counter that will automatically increment on every clock
SECTOR 0 = 4224 bytes (4K + 128)
SECTOR 1 = 266,112 bytes (252K + 8064)
SECTOR 15 = 270,336 bytes (256K + 8K)
Block = 4224 bytes
(4K + 128)
8 Pages
SECTOR 0
SECTOR 1
Page = 528 bytes
(512 + 16)
PAGE 0
PAGE 1
PAGE 6
PAGE 7
PAGE 8
PAGE 9
PAGE 8190
PAGE 8191
BLOCK 0
PAGE 14
PAGE 15
PAGE 16
PAGE 17
PAGE 18
PAGE 8189
BLOCK 1
SECTOR ARCHITECTURE BLOCK ARCHITECTURE PAGE ARCHITECTURE
BLOCK 0
BLOCK 1
BLOCK 62
BLOCK 63
BLOCK 64
BLOCK 65
BLOCK 1022
BLOCK 1023
BLOCK 126
BLOCK 127
BLOCK 128
BLOCK 129
SECTOR 2
SECTOR 2 = 270,336 bytes (256K + 8K)
SECTOR 16 = 270,336 bytes (256K + 8K)
BLOCK 2
6AT45BR3214B
3356B–DFLASH–10/04
cycle, allowing one continuous read operation without the need of additional address
sequences. To perform a continuous read, an opcode of 68H or E8H must be clocked
into the device followed by 24 address bits and 32 don’t care bits. The first bit of the
24-bit address sequence is reserved for upward and downward compatibility to larger
and smaller density devices (see Notes under “Command Sequence for Read/Write
Operations” diagram). The next 13 address bits (PA12 - PA0) specify which page of the
main memory array to read, and the last ten bits (BA9 - BA0) of the 24-bit address
sequence specify the starting byte address within the page. The 32 don’t care bits that
follow the 24 address bits are needed to initialize the read operation. Following the 32
don’t care bits, additional clock pulses on the SCK pin will result in serial data being out-
put on the SO (serial output) pin.
The CS pin must remain low during the loading of the opcode, the address bits, the don’t
care bits, and the reading of data. When the end of a page in main memory is reached
during a Continuous Array Read, the device will continue reading at the beginning of the
next page with no delays incurred during the page boundary crossover (the crossover
from the end of one page to the beginning of the next page). When the last bit in the
main memory array has been read, the device will continue reading back at the begin-
ning of the first page of memory. As with crossing over page boundaries, no delays will
be incurred when wrapping around from the end of the array to the beginning of the
array.
A low-to-high transition on the CS pin will terminate the read operation and tri-state the
SO pin. The maximum SCK frequency allowable for the Continuous Array Read is
defined by the fCAR specification. The Continuous Array Read bypasses both data buff-
ers and leaves the contents of the buffers unchanged.
MAIN MEMORY PAGE READ: A Main Memory Page Read allows the user to read data
directly from any one of the 8192 pages in the main memory, bypassing both of the data
buffers and leaving the contents of the buffers unchanged. To start a page read, an
opcode of 52H or D2H must be clocked into the device followed by 24 address bits and
32 don’t care bits. The first bit of the 24-bit address sequence is a reserved bit, the next
13 address bits (PA12 - PA0) specify the page address, and the next ten address bits
(BA9 - BA0) specify the starting byte address within the page. The 32 don’t care bits
which follow the 24 address bits are sent to initialize the read operation. Following the
32 don’t care bits, additional pulses on SCK result in serial data being output on the SO
(serial output) pin. The CS pin must remain low during the loading of the opcode, the
address bits, the don’t care bits, and the reading of data. When the end of a page in
main memory is reached during a Main Memory Page Read, the device will continue
reading at the beginning of the same page. A low-to-high transition on the CS pin will
terminate the read operation and tri-state the SO pin.
BUFFER READ: Data can be read from either one of the two buffers, using different
opcodes to specify which buffer to read from. An opcode of 54H or D4H is used to read
data from buffer 1, and an opcode of 56H or D6H is used to read data from buffer 2. To
perform a Buffer Read, the eight bits of the opcode must be followed by 14 don’t care
bits, ten address bits, and eight don’t care bits. Since the buffer size is 528 bytes, ten
address bits (BFA9 - BFA0) are required to specify the first byte of data to be read from
the buffer. The CS pin must remain low during the loading of the opcode, the address
bits, the don’t care bits, and the reading of data. When the end of a buffer is reached,
the device will continue reading back at the beginning of the buffer. A low-to-high transi-
tion on the CS pin will terminate the read operation and tri-state the SO pin.
STATUS REGISTER READ: The status register can be used to determine the device’s
Ready/Busy status, the result of a Main Memory Page to Buffer Compare operation, or
the device density. To read the status register, an opcode of 57H or D7H must be
7
AT45BR3214B
3356B–DFLASH–10/04
loaded into the device. After the last bit of the opcode is shifted in, the eight bits of the
status register, starting with the MSB (bit 7), will be shifted out on the SO pin during the
next eight clock cycles. The five most significant bits of the status register will contain
device information, while the remaining three least-significant bits are reserved for future
use and will have undefined values. After bit 0 of the status register has been shifted
out, the sequence will repeat itself (as long as CS remains low and SCK is being tog-
gled) starting again with bit 7. The data in the status register is constantly updated, so
each repeating sequence will output new data.
Ready/Busy status is indicated using bit 7 of the status register. If bit 7 is a 1, then the
device is not busy and is ready to accept the next command. If bit 7 is a 0, then the
device is in a busy state. The user can continuously poll bit 7 of the status register by
stopping SCK at a low level once bit 7 has been output. The status of bit 7 will continue
to be output on the SO pin, and once the device is no longer busy, the state of SO will
change from 0 to 1. There are eight operations which can cause the device to be in a
busy state: Main Memory Page to Buffer Transfer, Main Memory Page to Buffer Com-
pare, Buffer to Main Memory Page Program with Built-in Erase, Buffer to Main Memory
Page Program without Built-in Erase, Page Erase, Block Erase, Main Memory Page
Program, and Auto Page Rewrite.
The result of the most recent Main Memory Page to Buffer Compare operation is indi-
cated using bit 6 of the status register. If bit 6 is a 0, then the data in the main memory
page matches the data in the buffer. If bit 6 is a 1, then at least one bit of the data in the
main memory page does not match the data in the buffer.
The device density is indicated using bits 5, 4, 3 and 2 of the status register. For the 32-
Mbit DataFlash, the four bits are 1, 1, 0 and 1. The decimal value of these four binary
bits does not equate to the device density; the four bits represent a combinational code
relating to differing densities of Serial DataFlash devices, allowing a total of sixteen dif-
ferent density configurations.
Program and Erase
Commands
BUFFER WRITE: Data can be shifted in from the SI pin into either buffer 1 or buffer 2.
To load data into either buffer, an 8-bit opcode, 84H for buffer 1 or 87H for buffer 2, must
be followed by 14 don’t care bits and ten address bits (BFA9 - BFA0). The ten address
bits specify the first byte in the buffer to be written. The data is entered following the
address bits. If the end of the data buffer is reached, the device will wrap around back to
the beginning of the buffer. Data will continue to be loaded into the buffer until a low-to-
high transition is detected on the CS pin.
BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT-IN ERASE: Data written
into either buffer 1 or buffer 2 can be programmed into the main memory. To start the
operation, an 8-bit opcode, 83H for buffer 1 or 86H for buffer 2, must be followed by one
reserved bit, 13 address bits (PA12 - PA0) that specify the page in the main memory to
be written, and ten additional don’t care bits. When a low-to-high transition occurs on the
CS pin, the part will first erase the selected page in main memory to all 1s and then pro-
gram the data stored in the buffer into the specified page in the main memory. Both the
erase and the programming of the page are internally self-timed and should take place
in a maximum time of tEP. During this time, the status register will indicate that the part is
busy.
Status Register Format
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RDY/BUSY COMP1101XX
8AT45BR3214B
3356B–DFLASH–10/04
BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE: A
previously erased page within main memory can be programmed with the contents of
either buffer 1 or buffer 2. To start the operation, an 8-bit opcode, 88H for buffer 1 or
89H for buffer 2, must be followed by the one reserved bit, 13 address bits (PA12 - PA0)
that specify the page in the main memory to be written, and ten additional don’t care
bits. When a low-to-high transition occurs on the CS pin, the part will program the data
stored in the buffer into the specified page in the main memory. It is necessary that the
page in main memory that is being programmed has been previously erased. The pro-
gramming of the page is internally self-timed and should take place in a maximum time
of tP. During this time, the status register will indicate that the part is busy.
Successive page programming operations without doing a page erase are not recom-
mended. In other words, changing bytes within a page from a “1” to a “0” during multiple
page programming operations without erasing that page is not recommended.
PAGE ERASE: The optional Page Erase command can be used to individually erase
any page in the main memory array allowing the Buffer to Main Memory Page Program
without Built-in Erase command to be utilized at a later time. To perform a Page Erase,
an opcode of 81H must be loaded into the device, followed by one reserved bit,
13 address bits (PA12 - PA0), and ten don’t care bits. The 13 address bits are used to
specify which page of the memory array is to be erased. When a low-to-high transition
occurs on the CS pin, the part will erase the selected page to 1s. The erase operation is
internally self-timed and should take place in a maximum time of tPE. During this time,
the status register will indicate that the part is busy.
BLOCK ERASE: A block of eight pages can be erased at one time allowing the Buffer
to Main Memory Page Program without Built-in Erase command to be utilized to reduce
programming times when writing large amounts of data to the device. To perform a
Block Erase, an opcode of 50H must be loaded into the device, followed by one
reserved bit, ten address bits (PA12 - PA3), and 13 don’t care bits. The ten address bits
are used to specify which block of eight pages is to be erased. When a low-to-high tran-
sition occurs on the CS pin, the part will erase the selected block of eight pages to 1s.
The erase operation is internally self-timed and should take place in a maximum time of
tBE. During this time, the status register will indicate that the part is busy.
Block Erase Addressing
PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Block
0 0 0 0000000XXX 0
0 0 0 0000001XXX 1
0 0 0 0000010XXX 2
0 0 0 0000011XXX 3
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1 1 1 1111100XXX1020
1 1 1 1111101XXX1021
1 1 1 1111110XXX1022
1 1 1 1111111XXX1023
9
AT45BR3214B
3356B–DFLASH–10/04
MAIN MEMORY PAGE PROGRAM THROUGH BUFFER: This operation is a combina-
tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase
operations. Data is first shifted into buffer 1 or buffer 2 from the SI pin and then pro-
grammed into a specified page in the main memory. To initiate the operation, an 8-bit
opcode, 82H for buffer 1 or 85H for buffer 2, must be followed by one reserved bit and
23 address bits. The 13 most significant address bits (PA12 - PA0) select the page in
the main memory where data is to be written, and the next ten address bits
(BFA9 - BFA0) select the first byte in the buffer to be written. After all address bits are
shifted in, the part will take data from the SI pin and store it in one of the data buffers. If
the end of the buffer is reached, the device will wrap around back to the beginning of the
buffer. When there is a low-to-high transition on the CS pin, the part will first erase the
selected page in main memory to all 1s and then program the data stored in the buffer
into the specified page in the main memory. Both the erase and the programming of the
page are internally self-timed and should take place in a maximum of time tEP. During
this time, the status register will indicate that the part is busy.
Additional Commands MAIN MEMORY PAGE TO BUFFER TRANSFER: A page of data can be transferred
from the main memory to either buffer 1 or buffer 2. To start the operation, an 8-bit
opcode, 53H for buffer 1 and 55H for buffer 2, must be followed by one reserved bit, 13
address bits (PA12 - PA0) which specify the page in main memory that is to be trans-
ferred, and ten don’t care bits. The CS pin must be low while toggling the SCK pin to
load the opcode, the address bits, and the don’t care bits from the SI pin. The transfer of
the page of data from the main memory to the buffer will begin when the CS pin transi-
tions from a low to a high state. During the transfer of a page of data (tXFR), the status
register can be read to determine whether the transfer has been completed or not.
MAIN MEMORY PAGE TO BUFFER COMPARE: A page of data in main memory can
be compared to the data in buffer 1 or buffer 2. To initiate the operation, an 8-bit opcode,
60H for buffer 1 and 61H for buffer 2, must be followed by 24 address bits consisting of
one reserved bit, 13 address bits (PA12 - PA0) which specify the page in the main mem-
ory that is to be compared to the buffer, and ten don’t care bits. The CS pin must be low
while toggling the SCK pin to load the opcode, the address bits, and the don’t care bits
from the SI pin. On the low-to-high transition of the CS pin, the 528 bytes in the selected
main memory page will be compared with the 528 bytes in buffer 1 or buffer 2. During
this time (tXFR), the status register will indicate that the part is busy. On completion of the
compare operation, bit 6 of the status register is updated with the result of the compare.
AUTO PAGE REWRITE: This mode is only needed if multiple bytes within a page or
multiple pages of data are modified in a random fashion. This mode is a combination of
two operations: Main Memory Page to Buffer Transfer and Buffer to Main Memory Page
Program with Built-in Erase. A page of data is first transferred from the main memory to
buffer 1 or buffer 2, and then the same data (from buffer 1 or buffer 2) is programmed
back into its original page of main memory. To start the rewrite operation, an 8-bit
opcode, 58H for buffer 1 or 59H for buffer 2, must be followed by one reserved bit, 13
address bits (PA12 - PA0) that specify the page in main memory to be rewritten, and ten
additional don’t care bits. When a low-to-high transition occurs on the CS pin, the part
will first transfer data from the page in main memory to a buffer and then program the
data from the buffer back into same page of main memory. The operation is internally
self-timed and should take place in a maximum time of tEP. During this time, the status
register will indicate that the part is busy.
10 AT45BR3214B
3356B–DFLASH–10/04
If a sector is programmed or reprogrammed sequentially page-by-page, then the pro-
gramming algorithm shown in Figure 1 on page 28 is recommended. Otherwise, if
multiple bytes in a page or several pages are programmed randomly in a sector, then
the programming algorithm shown in Figure 2 on page 29 is recommended. Each page
within a sector must be updated/rewritten at least once within every 10,000 cumulative
page erase/program operations in that sector.
Operation Mode
Summary
The modes described can be separated into two groups – modes which make use of the
Flash memory array (Group A) and modes which do not make use of the Flash memory
array (Group B).
Group A modes consist of:
1. Main Memory Page Read
2. Main Memory Page to Buffer 1 (or 2) Transfer
3. Main Memory Page to Buffer 1 (or 2) Compare
4. Buffer 1 (or 2) to Main Memory Page Program with Built-in Erase
5. Buffer 1 (or 2) to Main Memory Page Program without Built-in Erase
6. Page Erase
7. Block Erase
8. Main Memory Page Program through Buffer
9. Auto Page Rewrite
Group B modes consist of:
1. Buffer 1 (or 2) Read
2. Buffer 1 (or 2) Write
3. Status Register Read
If a Group A mode is in progress (not fully completed) then another mode in Group A
should not be started. However, during this time in which a Group A mode is in
progress, modes in Group B can be started.
This gives the Serial DataFlash the ability to virtually accommodate a continuous data-
stream. While data is being programmed into main memory from buffer 1, data can be
loaded into buffer 2 (or vice versa). See application note AN-4 (“Using Atmel’s Serial
DataFlash”) for more details.
Pin Descriptions SERIAL INPUT (SI): The SI pin is an input-only pin and is used to shift data into the
device. The SI pin is used for all data input including opcodes and address sequences.
SERIAL OUTPUT (SO): The SO pin is an output-only pin and is used to shift data out
from the device.
SERIAL CLOCK (SCK): The SCK pin is an input-only pin and is used to control the flow
of data to and from the DataFlash. Data is always clocked into the device on the rising
edge of SCK and clocked out of the device on the falling edge of SCK.
CHIP SELECT (CS): The DataFlash is selected when the CS pin is low. When the
device is not selected, data will not be accepted on the SI pin, and the SO pin will
remain in a high-impedance state. A high-to-low transition on the CS pin is required to
start an operation, and a low-to-high transition on the CS pin is required to end an
operation.
11
AT45BR3214B
3356B–DFLASH–10/04
WRITE PROTECT: If the WP pin is held low, the first 256 pages of the main memory
cannot be reprogrammed. The only way to reprogram the first 256 pages is to first drive
the protect pin high and then use the program commands previously mentioned. If this
pin and feature are not utilized it is recommended that the WP pin be driven high
externally.
RESET: A low state on the reset pin (RESET) will terminate the operation in progress
and reset the internal state machine to an idle state. The device will remain in the reset
condition as long as a low level is present on the RESET pin. Normal operation can
resume once the RESET pin is brought back to a high level.
The device incorporates an internal power-on reset circuit, so there are no restrictions
on the RESET pin during power-on sequences. If this pin and feature are not utilized it is
recommended that the RESET pin be driven high externally.
READY/BUSY: This open drain output pin will be driven low when the device is busy in
an internally self-timed operation. This pin, which is normally in a high state (through
a1kΩ external pull-up resistor), will be pulled low during programming operations, com-
pare operations, and during page-to-buffer transfers.
The busy status indicates that the Flash memory array and one of the buffers cannot be
accessed; read and write operations to the other buffer can still be performed.
Power-on/Reset State When power is first applied to the device, or when recovering from a reset condition, the
device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance
state, and a high-to-low transition on the CS pin will be required to start a valid instruc-
tion. The SPI mode will be automatically selected on every falling edge of CS by
sampling the inactive clock state. After power is applied and Vcc is at the minimum
datasheet value, the system should wait 20 ms before an operational mode is started.
Table 1. Read Commands
Command SCK Mode Opcode
Continuous Array Read Inactive Clock Polarity Low or High 68H
SPI Mode 0 or 3 E8H
Main Memory Page Read Inactive Clock Polarity Low or High 52H
SPI Mode 0 or 3 D2H
Buffer 1 Read Inactive Clock Polarity Low or High 54H
SPI Mode 0 or 3 D4H
Buffer 2 Read Inactive Clock Polarity Low or High 56H
SPI Mode 0 or 3 D6H
Status Register Read Inactive Clock Polarity Low or High 57H
SPI Mode 0 or 3 D7H
12 AT45BR3214B
3356B–DFLASH–10/04
Note: In Tables 2 and 3, an SCK mode designation of “Any” denotes any one of the four modes of operation (Inactive Clock Polarity
Low, Inactive Clock Polarity High, SPI Mode 0, or SPI Mode 3).
Table 2. Program and Erase Commands
Command SCK Mode Opcode
Buffer 1 Write Any 84H
Buffer 2 Write Any 87H
Buffer 1 to Main Memory Page Program with Built-in Erase Any 83H
Buffer 2 to Main Memory Page Program with Built-in Erase Any 86H
Buffer 1 to Main Memory Page Program without Built-in Erase Any 88H
Buffer 2 to Main Memory Page Program without Built-in Erase Any 89H
Page Erase Any 81H
Block Erase Any 50H
Main Memory Page Program through Buffer 1 Any 82H
Main Memory Page Program through Buffer 2 Any 85H
Table 3. Additional Commands
Command SCK Mode Opcode
Main Memory Page to Buffer 1 Transfer Any 53H
Main Memory Page to Buffer 2 Transfer Any 55H
Main Memory Page to Buffer 1 Compare Any 60H
Main Memory Page to Buffer 2 Compare Any 61H
Auto Page Rewrite through Buffer 1 Any 58H
Auto Page Rewrite through Buffer 2 Any 59H
13
AT45BR3214B
3356B–DFLASH–10/04
Note: r = Reserved Bit
P = Page Address Bit
B = Byte/Buffer Address Bit
x = Don’t Care
Table 4. Detailed Bit-level Addressing Sequence
Opcode Opcode
Address Byte Address Byte Address Byte
Additional
Don’t Care
Bytes
Required
50H 01010000r PPPPPPPPPPxxxxxxxxxxxxx N/A
52H 01010010r PPPPPPPPPPPPPBBBBBBBBBB 4 Bytes
53H 01010011r PPPPPPPPPPPPPxxxxxxxxxx N/A
54H 01010100xxxxxxxxxxxxxxBBBBBBBBBB 1 Byte
55H 01010101r PPPPPPPPPPPPPxxxxxxxxxx N/A
56H 01010110xxxxxxxxxxxxxxBBBBBBBBBB 1 Byte
57H 01010111 N/A N/A N/A N/A
58H 01011000r PPPPPPPPPPPPPxxxxxxxxxx N/A
59H 01011001r PPPPPPPPPPPPPxxxxxxxxxx N/A
60H 01100000r PPPPPPPPPPPPPxxxxxxxxxx N/A
61H 01100001r PPPPPPPPPPPPPxxxxxxxxxx N/A
68H 01101000r PPPPPPPPPPPPPBBBBBBBBBB 4 Bytes
81H 10000001r PPPPPPPPPPPPPxxxxxxxxxx N/A
82H 10000010r PPPPPPPPPPPPPBBBBBBBBBB N/A
83H 10000011r PPPPPPPPPPPPPxxxxxxxxxx N/A
84H 10000100xxxxxxxxxxxxxxBBBBBBBBBB N/A
85H 10000101r PPPPPPPPPPPPPBBBBBBBBBB N/A
86H 10000110r PPPPPPPPPPPPPxxxxxxxxxx N/A
87H 10000111xxxxxxxxxxxxxxBBBBBBBBBB N/A
88H 10001000r PPPPPPPPPPPPPxxxxxxxxxx N/A
89H 10001001r PPPPPPPPPPPPPxxxxxxxxxx N/A
D2H 11010010r PPPPPPPPPPPPPBBBBBBBBBB 4 Bytes
D4H 11010100xxxxxxxxxxxxxxBBBBBBBBBB 1 Byte
D6H 11010110xxxxxxxxxxxxxxBBBBBBBBBB 1 Byte
D7H 11010111 N/A N/A N/A N/A
E8H 11101000r PPPPPPPPPPPPPBBBBBBBBBB 4 Bytes
R
eserve
d
PA12
PA
11
PA
10
PA
9
PA8
PA
7
PA6
PA
5
PA
4
PA3
PA2
PA1
PA
0
BA
9
BA
8
BA
7
BA6
BA
5
BA
4
BA
3
BA2
BA1
BA0
14 AT45BR3214B
3356B–DFLASH–10/04
Note: 1. After power is applied and VCC is at the minimum specified datasheet value, the system should wait 20 ms before an opera-
tional mode is started.
Note: 1. Icc1 during a buffer read is 20mA maximum.
Absolute Maximum Ratings*
Temperature under Bias ................................ -55°C to +125°C*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Storage Temperature..................................... -65°C to +150°C
All Input Voltages
(including NC Pins)
with Respect to Ground ...................................-0.6V to +6.25V
All Output Voltages
with Respect to Ground .............................-0.6V to VCC + 0.6V
DC and AC Operating Range
32-Mbit DataFlash
Operating Temperature (Case) Com. 0°C to 70°C
Ind. -40°C to 85°C
VCC Power Supply(1) 2.7V to 3.3V
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
ISB Standby Current CS, RESET, WP = VCC, all inputs
at CMOS levels
210µA
ICC1(1) Active Current, Read
Operation
f = 20 MHz; IOUT = 0 mA;
VCC = 3.3V
410mA
ICC2 Active Current,
Program/Erase Operation
VCC = 3.3V 15 35 mA
ILI Input Load Current VIN = CMOS levels 1 µA
ILO Output Leakage Current VI/O = CMOS levels 1 µA
VIL Input Low Voltage 0.6 V
VIH Input High Voltage 2.0 V
VOL Output Low Voltage IOL = 1.6 mA; VCC = 2.7V 0.4 V
VOH Output High Voltage IOH = -100 µA VCC - 0.2V V
15
AT45BR3214B
3356B–DFLASH–10/04
AC Characteristics
Symbol Parameter
32-Mbit DataFlash
UnitsMin Max
fSCK SCK Frequency 20 MHz
fCAR SCK Frequency for Continuous Array Read 20 MHz
tWH SCK High Time 22 ns
tWL SCK Low Time 22 ns
tCS Minimum CS High Time 250 ns
tCSS CS Setup Time 250 ns
tCSH CS Hold Time 250 ns
tCSB CS High to RDY/BUSY Low 200 ns
tSU Data In Setup Time 5 ns
tHData In Hold Time 10 ns
tHO Output Hold Time 0 ns
tDIS Output Disable Time 18 ns
tVOutput Valid 20 ns
tXFR Page to Buffer Transfer/Compare Time 250 µs
tEP Page Erase and Programming Time 20 ms
tPPage Programming Time 14 ms
tPE Page Erase Time 8ms
tBE Block Erase Time 12 ms
tRST RESET Pulse Width 10 µs
tREC RESET Recovery Time 1 µs
16 AT45BR3214B
3356B–DFLASH–10/04
Input Test Waveforms and Measurement Levels
tR, tF < 3 ns (10% to 90%)
Output Test Load
AC Waveforms Two different timing diagrams are shown below. Waveform 1 shows the SCK signal
being low when CS makes a high-to-low transition, and Waveform 2 shows the SCK sig-
nal being high when CS makes a high-to-low transition. Both waveforms show valid
timing diagrams. The setup and hold times for the SI signal are referenced to the low-to-
high transition on the SCK signal.
Waveform 1 shows timing that is also compatible with SPI Mode 0, and Waveform 2
shows timing that is compatible with SPI Mode 3.
Waveform 1 – Inactive Clock Polarity Low and SPI Mode 0
Waveform 2 – Inactive Clock Polarity High and SPI Mode 3
AC
DRIVING
LEVELS
AC
MEASUREMENT
LEVEL
0.45V
2.0
0.8
2.4V
DEVICE
UNDER
TEST
30 pF
CS
SCK
SI
SO
tCSS
VALID IN
tH
tSU
tWH tWL tCSH
tCS
tV
HIGH IMPEDANCE VALID OUT
tHO tDIS
HIGH IMPEDANCE
CS
SCK
SI
SO
tCSS
VALID IN
tH
tSU
tWL tWH tCSH
tCS
tV
HIGH Z VALID OUT
tHO tDIS
HIGH IMPEDANCE
17
AT45BR3214B
3356B–DFLASH–10/04
Reset Timing (Inactive Clock Polarity Low Shown)
Note: The CS signal should be in the high state before the RESET signal is deasserted.
Command Sequence for Read/Write Operations (except Status Register Read)
Notes: 1. “r” designates bits reserved for larger densities.
2. It is recommended that “r” be a logical “0” for densities of 32M bits or smaller.
3. For densities larger than 32M bits, the “r” bits become the most significant Page Address bit for the appropriate density.
CS
SCK
RESET
SO HIGH IMPEDANCE HIGH IMPEDANCE
SI
tRST
tREC tCSS
SI CMD 8 bits 8 bits 8 bits
MSB
Reserved for
larger densities
Page Address
(PA12-PA0)
Byte/Buffer Address
(BA9-BA0/BFA9-BFA0)
LSBr X X X X X X X X X X X X X X X X X X X X X X X
18 AT45BR3214B
3356B–DFLASH–10/04
Write Operations The following block diagram and waveforms illustrate the various write sequences
available.
Main Memory Page Program through Buffers
Buffer Write
Buffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)BUFFER 1 (528 BYTES)
I/O INTERFACE
SI
BUFFER 1 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY
PAGE PROGRAM
THROUGH BUFFER 2
BUFFER 2 TO
MAIN MEMORY
PAGE PROGRAM
MAIN MEMORY PAGE
PROGRAM THROUGH
BUFFER 1
BUFFER 1
WRITE
BUFFER 2
WRITE
SI
CMD n n+1 Last Byte
· Completes writing into selected buffer
· Starts self-timed erase/program operation
CS
r , PA12-6 PA5-0, BFA9-8 BFA7-0
SI CMD X X···X, BFA9-8 BFA7-0 nn+1 Last Byte
· Completes writing into selected buffer
CS
SI CMD PA5-0, XX X
CS
Starts self-timed erase/program operation
r , PA12-6
Each transition represents
8 bits and 8 clock cycles
n = 1st byte read
n+1 = 2nd byte read
19
AT45BR3214B
3356B–DFLASH–10/04
Read Operations The following block diagram and waveforms illustrate the various read sequences
available.
Main Memory Page Read
Main Memory Page to Buffer Transfer (Data from Flash Page Read into Buffer)
Buffer Read
FLASH MEMORY ARRAY
PAGE (528 BYTES)
BUFFER 2 (528 BYTES)BUFFER 1 (528 BYTES)
I/O INTERFACE
MAIN MEMORY
PAGE TO
BUFFER 1
MAIN MEMORY
PAGE TO
BUFFER 2
MAIN MEMORY
PAGE READ
BUFFER 1
READ
BUFFER 2
READ
SO
SI
CMD PA5-0, BA9-8 BA7-0 X XXX
CS
n n+1
SO
r , PA12-6
SI
CMD PA5-0, XX X
Starts reading page data into buffer
CS
SO
r , PA12-6
SI
CMD XX···X, BFA9-8 BFA7-0
CS
n n+1
SO
X
E
ach transition represents
8 bits and 8 clock cycles
n = 1st byte read
n+1 = 2nd byte read
20 AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity Low
Continuous Array Read (Opcode: 68H)
Main Memory Page Read (Opcode: 52H)
SI 01XX
CS
SO
SCK 12 63 64 65 66 67 68
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 4223
OF
PAGE n
LSB MSB
tSU
tV
SI
01010 XXX
CS
SO
SCK
12345 60 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
21
AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity Low (Continued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: 57H)
SI
01010 XXX
CS
SO
SCK
12345 36 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
SI 01010111
CS
SO
SCK 12345 7891011 12 16 17
HIGH-IMPEDANCE D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
D1D0D7
LSB MSB
22 AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity High
Continuous Array Read (Opcode: 68H)
Main Memory Page Read (Opcode: 52H)
SI 01XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 4223
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI
01010 XXX
CS
SO
SCK
12345 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
68
23
AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – Inactive Clock Polarity High (Continued)
Buffer Read (Opcode: 54H or 56H)
Status Register Read (Opcode: 57H)
SI
01010 XXX
CS
SO
SCK
12345 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
tSU
tV
D4
44
SI 01010111
CS
SO
SCK 12345 7891011 12 17 18
HIGH-IMPEDANCE D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
D4D0D7
LSB MSB
D6
24 AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 0
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
SI 11XXX
CS
SO
SCK 12 62 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
DATA OUT
BIT 0
OF
PAGE n+1
BIT 4223
OF
PAGE n
LSB MSB
tSU
tV
SI
11010 XXX
CS
SO
SCK
12345 60 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE
D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
25
AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 0 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
SI 11010 XXX
CS
SO
SCK 12345 36 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE
COMMAND OPCODE
t
SU
D7D6D5
DATA OUT
MSB
t
V
D4
SI 11010111
CS
SO
SCK 12345 7891011 12 16 17
HIGH-IMPEDANCE STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
t
SU
6
D1D0D7
LSB MSB
D7D6D5
t
V
D4
26 AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 3
Continuous Array Read (Opcode: E8H)
Main Memory Page Read (Opcode: D2H)
SI 11XXX
CS
SO
SCK 12 63 64 65 66 67
HIGH-IMPEDANCE D7D6D5D2D1D0D7D6D5
BIT 0
OF
PAGE n+1
BIT 4223
OF
PAGE n
LSB MSB
tSU
tVDATA OUT
SI 11010 XXX
CS
SO
SCK 12345 61 62 63 64 65 66 67
XX
HIGH-IMPEDANCE D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
68
27
AT45BR3214B
3356B–DFLASH–10/04
Detailed Bit-level Read Timing – SPI Mode 3 (Continued)
Buffer Read (Opcode: D4H or D6H)
Status Register Read (Opcode: D7H)
SI 11010 XXX
CS
SO
SCK 12345 37 38 39 40 41 42 43
XX
HIGH-IMPEDANCE D7D6D5
DATA OUT
COMMAND OPCODE
MSB
t
SU
t
V
D4
44
SI 11010111
CS
SO
SCK 12345 7891011 12 17 18
HIGH-IMPEDANCE D7D6D5
STATUS REGISTER OUTPUT
COMMAND OPCODE
MSB
tSU
tV
6
D4D0D7
LSB MSB
D6
28 AT45BR3214B
3356B–DFLASH–10/04
Figure 1. Algorithm for Sequentially Programming or Reprogramming the Entire Array
Notes: 1. This type of algorithm is used for applications in which the entire array is programmed sequentially, filling the array page-by-
page.
2. A page can be written using either a Main Memory Page Program operation or a Buffer Write operation followed by a Buffer
to Main Memory Page Program operation.
3. The algorithm above shows the programming of a single page. The algorithm will be repeated sequentially for each page
within the entire array.
START
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
END
provide address
and data
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
29
AT45BR3214B
3356B–DFLASH–10/04
Figure 2. Algorithm for Randomly Modifying Data
Notes: 1. To preserve data integrity, each page of a DataFlash sector must be updated/rewritten at least once within every 10,000
cumulative page erase/program operations.
2. A Page Address Pointer must be maintained to indicate which page is to be rewritten. The Auto Page Rewrite command
must use the address specified by the Page Address Pointer.
3. Other algorithms can be used to rewrite portions of the Flash array. Low-power applications may choose to wait until 10,000
cumulative page erase/program operations have accumulated before rewriting all pages of the sector. See application note
AN-4 (“Using Atmel’s Serial DataFlash”) for more details.
Sector Addressing
PA12 PA11 PA10 PA9 PA8 PA7 PA6 PA5 PA4 PA3 Sector
0 0 0 0000000 0
0 0 0 0XXXXXX 1
0 0 0 1XXXXXX 2
0 0 1 0XXXXXX 3
• • • ••••••• •
• • • ••••••• •
• • • ••••••• •
1 1 0 0XXXXXX 13
1 1 0 1XXXXXX 14
1 1 1 0XXXXXX 15
1 1 1 1XXXXXX 16
START
MAIN MEMORY PAGE
TO BUFFER TRANSFER
(53H, 55H)
INCREMENT PAGE
ADDRESS POINTER
(2)
AUTO PAGE REWRITE
(2)
(58H, 59H)
END
provide address of
page to modify
If planning to modify multiple
bytes currently stored within
a page of the Flash array
MAIN MEMORY PAGE PROGRAM
THROUGH BUFFER
(82H, 85H)
BUFFER WRITE
(84H, 87H)
BUFFER TO MAIN
MEMORY PAGE PROGRAM
(83H, 86H)
30 AT45BR3214B
3356B–DFLASH–10/04
4-megabit SRAM
Description
The 4-megabit SRAM is a high-speed, super low-power CMOS SRAM organized as
256K words by 16 bits. The SRAM uses high-performance full CMOS process technol-
ogy and is designed for high-speed and low-power circuit technology. It is particularly
well-suited for the high-density low-power system application. This device has a data
retention mode that guarantees data to remain valid at a minimum power supply voltage
of 1.2V.
Features
•Fully Static Operation and Tri-state Output
•TTL Compatible Inputs and Outputs
•Battery Backup
– 1.2V (Min) Data Retention
Block Diagram
Voltage (V) Speed (ns)
Operation
Current/ICC (mA)
(Max)
Standby
Current (µA)
(Max)
Temperature
(°C)
2.7 - 3.3 70 3 10 -40 - 85
MEMORY ARRAY
256K X 16
I/O0
SUB
SLB
SOE
SCS2
SCS1
SWE
DATA I/O BUFFER
SENSE AMP WRITE DRIVER
I/O7
I/O8
I/O15
ROW DECODER
COLUMN
DECODER
BLOCK
DECODER
PRE DECODER
ADD INPUT BUFFER
A0
A17
31
AT45BR3214B
3356B–DFLASH–10/04
Note: 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is
stress rating only and the functional operation of the device under these or any other conditions above those indicated in the
operation of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect reliability.
Notes: 1. H = VIH, L = VIL, X = Don't Care (VIL or VIH)
2. SUB, SLB (Upper, Lower Byte Enable). These active LOW inputs allow individual bytes to be written or read. When SLB is
LOW, data is written or read to the lower byte, I/O0 - I/O7. When SUB is LOW, data is written or read to the upper byte, I/O8
- I/O15.
Note: 1. Undershoot: VIL = -1.5V for pulse width less than 30 ns. Undershoot is sampled, not 100% tested.
Absolute Maximum Ratings(1)
Symbol Parameter Rating Unit
VIN, VOUT Input/Output Voltage -0.3 to 3.6 V
VCC Power Supply -0.3 to 3.6 V
TAOperating Temperature -40 to 85 °C
TSTG Storage Temperature -55 to 150 °C
PDPower Dissipation 1.0 W
Truth Table
SCS1 SCS2 SWE SOE SLB(2) SUB(2) Mode
I/O Pin
PowerI/O0 - I/O7 I/O8 - I/O15
H(1) X
XXXXDeselected High-Z High-Z StandbyX(1) L
XX HH
L(1) HHH
LH
Output Disabled High-Z High-Z ActiveHL
LL
LHLX
LH
Write
DIN High-Z
ActiveH L High-Z DIN
LL D
IN DIN
LHHL
LH
Read
DOUT High-Z
ActiveH L High-Z DOUT
LL D
OUT DOUT
Recommended DC Operating Condition
Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 2.7 3.0 3.3 V
VSS Ground 0 0 0 V
VIH Input High Voltage 2.2 VCC + 0.3 V
VIL(1) Input Low Voltage -0.3(1) 0.6 V
32 AT45BR3214B
3356B–DFLASH–10/04
Note: 1. These parameters are sampled and not 100% tested.
DC Electrical Characteristics
TA = -40°C to 85°C
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current VSS < VIN < VCC -1 1 µA
ILO Output Leakage Current VSS < VOUT < VCC,
SCS1 = VIH or SCS2=VIL or
SOE = VIH or SWE = VIL or
SUB = VIH, SLB = VIH
-1 1 µA
ICC Operating Power Supply Current SCS1 = VIL, SCS2=VIH,
VIN = VIH or VIL, II/O = 0 mA
3mA
ICC1 Average Operating Current SCS1 = VIL, SCS2 = VIH,
VIN = VIH or VIL, Cycle Time = Min
100% Duty, II/O = 0 mA
15 mA
SCS1 < 0.2V, SCS2 > VCC - 0.2V
VIN < 0.2V or VIN > VCC - 0.2V,
Cycle Time = 1 µs
100% Duty, II/O = 0 mA
2mA
ISB Standby Current (TTL Input) SCS1 = VIH or SCS2 = VIL or
SUB, SLB = VIH
VIN = VIH or VIL
300 µA
ISB1 Standby Current (CMOS Input) SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
10 µA
VOL Output Low IOL = 2.1 mA 0.4 V
VOH Output High IOH = -1.0 mA 2.4 V
Capacitance(1)
(Temp = 25°C, f = 1.0 MHz)
Symbol Parameter Condition Max Unit
CIN Input Capacitance (Add, SCS1,
SCS2, SLB, SUB, SWE, SOE)
VIN = 0 V 8 pF
COUT Output Capacitance (I/O) VI/O = 0 V 10 pF
33
AT45BR3214B
3356B–DFLASH–10/04
AC Characteristics
TA = -40°C to 85°C, Unless Otherwise Specified
# Symbol Parameter
70 ns
UnitMin Max
1t
RC Read Cycle Time 70 ns
2t
AA Address Access Time 70 ns
3t
ACS Chip Select Access Time 70 ns
4t
OE Output Enable to Output Valid 35 ns
5t
BA SLB, SUB Access Time 70 ns
6t
CLZ Chip Select to Output in Low Z 10 ns
7t
OLZ Output Enable to Output in Low Z 5 ns
8t
BLZ SLB, SUB Enable to Output in Low Z 10 ns
9t
CHZ Chip Deselection to Output in High Z 0 25 ns
10 tOHZ Out Disable to Output in High Z 0 25 ns
11 tBHZ SLB, SUB Disable to Output in High Z 0 25 ns
12 tOH Output Hold from Address Change 10 ns
13 tWC Write Cycle Time 30 ns
14 tCW Chip Selection to End of Write 30 ns
15 tAW Address Valid to End of Write 30 ns
16 tBW SLB, SUB Valid to End of Write 30 ns
17 tAS Address Setup Time 0 ns
18 tWP Write Pulse Width 30 ns
19 tWR Write Recovery Time 0 ns
20 tWHZ Write to Output in High Z 0 5 ns
21 tDW Data to Write Time Overlap 25 ns
22 tDH Data Hold from Write Time 0 ns
23 tOW Output Active from End of Write 5 ns
AC Test Conditions
TA = -40°C to 85°C, Unless Otherwise Specified
Parameter Value
Input Pulse Level 0.4V to 2.2V
Input Rise and Fall Time 5 ns
Input and Output Timing Reference Level 1.5V
Output Load tCLZ, tOLZ, tBLZ, tCHZ, tOHZ, tBHZ, tWHZ, tOW CL = 5 pF + 1 TTL Load
Others CL = 30 pF + 1 TTL Load
34 AT45BR3214B
3356B–DFLASH–10/04
AC Test Loads
Note: Including jig and scope capacitance.
DOUT
1728 Ohm
CL
1029 Ohm
VTM = 2.8V
(1)
35
AT45BR3214B
3356B–DFLASH–10/04
Timing Diagrams
Read Cycle 1(1),(4)
Read Cycle 2(1),(2),(4)
Read Cycle 3(1),(2),(4)
Note: 1. Read Cycle occurs whenever a high on the SWE and SOE is low, while SUB and/or SLB and SCS1 and SCS2 are in active
status.
2. SOE = VIL.
3. Transition is measured ± 200 mV from steady state voltage. This parameter is sampled and not 100% tested.
4. SCS1 in high for the standby, low for active. SCS2 in low for the standby, high for active. SUB and SLB in high for the
standby, low for active.
ADDRESS
SOE
SUB, SLB
SCS1
SCS2
DATA OUT HIGH-Z DATA VALID
tAA
tRC
tBA
tACS
tOE
tOLZ
tBLZ
tCLZ
tBHZ
tCHZ
tOH
tOHZ
(3)
(3)
(3)
(3)
(3)
(3)
DATA OUT
ADDRESS
t
AA
PREVIOUS DATA
t
OH
DATA VALID
t
OH
t
RC
SUB, SLB
SCS1
SCS2
DATA OUT
t
ACS
t
CLZ
(3)
DATA VALID
t
CHZ
(3)
36 AT45BR3214B
3356B–DFLASH–10/04
Write Cycle 1 (SWE Controlled)(1),(4),(8)
Write Cycle 2 (SCS1, SCS2 Controlled)(1),(4),(8)
Notes: 1. A write occurs during the overlap of a low SWE, a low SCS1, a high SCS2 and a low SUB and/or SLB.
2. tWR is measured from the earlier of SCS1, SLB, SUB, or SWE going high or SCS2 going low to the end of write cycle.
3. During this period, I/O pins are in the output state so that the input signals of opposite phase to the output must not be
applied.
4. If the SCS1, SLB and SUB low transition and SCS2 high transition occur simultaneously with the SWE low transition or after
the SWE transition, outputs remain in a high impedance state.
5. Q (data out) is the same phase with the write data of this write cycle.
6. Q (data out) is the read data of the next address.
7. Transition is measured ± 200 mV from steady state. This parameter is sampled and not 100% tested.
8. SCS1 in high for the standby, low for active SCS2 in low for the standby, high for active. SUB and SLB in high for the standby,
low for active.
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
t
WC
t
CW
t
AW
t
BW
t
WP
t
AS
t
WHZ
t
WR
t
DW
t
DH
t
OW
DATA VALID
HIGH-Z
t
AS
(2)
(5) (5)
(3)(7)
ADDRESS
SWE
SUB, SLB
DATA IN
SCS1
SCS2
DATA OUT
tWC
tCW
tAW
tBW
tWP
tAS tWR
tDW tDH
DATA VALID
HIGH-Z
(2)
HIGH-Z
37
AT45BR3214B
3356B–DFLASH–10/04
Notes: 1. Typical values are under the condition of TA = 25°C. Typical values are sampled and not 100% tested.
2. tRC is read cycle time.
Data Retention Timing Diagram 1
Data Retention Timing Diagram 2
Data Retention Electric Characteristic
TA = -40°C to 85°C
Symbol Parameter Test Condition Min Typ Max Unit
VDR VCC for Data Retention SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
1.2 3.3 V
ICCDR Data Retention Current Vcc=1.5V,
SCS1 > VCC - 0.2V or
SCS2 < VSS + 0.2V or
SUB, SLB > VCC - 0.2V
VIN > VCC - 0.2V or
VIN < VSS + 0.2V
0.2 6 µA
tCDR Chip Deselect to Data
Retention Time
See Data Retention Timing Diagram 0 ns
tROperating Recovery Time tRC ns
DATA RETENTION MODE
tR
tCDR
VCC
SCS1 > VCC - 0.2V
2.7V
IH
VDR
SCS1
VSS
VCC
2.7V
VDR
SCS2
VSS
0.4V
DATA RETENTION MODE
tR
tCDR
SCS2 < 0.2V
38 AT45BR3214B
3356B–DFLASH–10/04
Ordering Information
DataFlash
fSCK (MHz)
SRAM
tACC(ns) Ordering Code DataFlash SRAM Package Operation Range
20 70 AT45BR3214B-C1 32M x 1 256k x 16 62C1 Industrial
(-40°C to 85°C)
Package Type
62C1 62-ball, Plastic Chip-scale Ball Grid Array (CBGA)
39
AT45BR3214B
3356B–DFLASH–10/04
Packaging Information
62C1 – CBGA
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
62C1, 62-ball (10 x 8 Array), 12 x 8 x 1.2 mm Body, 0.8 mm Ball
Plastic Chip-scale Ball Grid Array Package (CBGA) A
62C1
05/12/03
Side View
Top View
Bottom View
A
B
C
D
E
F
G
H
1
2
3
4
5
6
7
89
1.20 REF
2.40 REF
10
Marked A1 Identifier
D
E
D1
E1
e
e
Øb
A
A1
0.12
Seating Plane
C
C
A1 Ball Corner
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – – 1.20
A1 0.25 – –
D 11.90 12.00 12.10
D1 7.20 TYP
E 7.90 8.00 8.10
E1 5.60 TYP
e 0.80 TYP
Ø
b 0.40 TYP
Printed on recycled paper.
3356B–DFLASH–10/04 /xM
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any
intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-
TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY
WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-
TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT
OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications
and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Atmel’s products are not
intended, authorized, or warranted for use as components in applications intended to support or sustain life.
Atmel Corporation Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Regional Headquarters
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Asia
Room 1219
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Memory
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Microcontrollers
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: 1(719) 576-3300
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
Fax: (33) 4-76-58-34-80
Literature Requests
www.atmel.com/literature
© Atmel Corporation 2004. All rights reserved. Atmel®, logo and combinations thereof, and DataFlash® are registered trademarks, and Every-
where You AreSM is the trademark of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.
