INTEGRATED CIRCUITS DATA SHEET For 4 complete data sheet, bisase also download: es The iOO8 7ahC/NCT/NCU/NCMOS Logic Farnly Specifications | s The [006 74NC/CTYMCLYHCMOS Logic Package Information | | s The IC08 T4HC/HCT/NCLYHCMOS Logic Package Quilines | 74HC/HCT174 Hex D-type flip-flop with reset; positive-edge trigger Product specification 1998 Jul 08 Supersedes data of September 1993 File under Integrated Circuits, ICO6 CAE ctor & PHILIPSPhilips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 FEATURES Six edge-triggered D-type flip-flops Asynchronous master reset Output capability: standard leg category: MSI GENERAL DESCRIPTION The 74HG/HCT1 74 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEG standard no. 7A. QUICK REFERENCE DATA GND =0 V; Tamp= 25 C; t, = ty = 6 ns The 74HC/HCT 174 have six edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one set-up time prior to the LOW-to-HIGH clock transition, is transferred to the corresponding output of the flip-flop. A LOW level on the MR input forces all outputs LOW, independently of clock or data inputs. The device is useful for applications requiring true outputs only and clock and master reset inputs that are common to all storage elements. TYPICAL SYMBOL PARAMETER CONDITIONS UNIT HC HCT teHe/ tpLy propagation delay C_=15 pF; Veg = 5 V CP to Q, 17 18 ns MR to Q, 13 17 ns Fax maximum clock frequency 99 69 MHz C| input capacitance 3.5 3.5 pF Cpp power dissipation notes 1 and 2 17 17 oF capacitance per flip-flop Notes 1. Cpp is used to determine the dynamic power dissipation (Pp in wW): Pp = Cep x Voc? x ff +E (CL x Voc? xf.) where: fj = input frequency in MHz fo = output frequency in MHz E (CL Veco? x f) = sum of outputs C_ = output load capacitance in pF Voc = supply voltage in V For HC the condition is V; = GND to Vee For HCT the condition is Vj = GND to Veg1.5V ha 1998 Jul 08Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 ORDERING INFORMATION TYPE PACKAGE NUMBER NAME DESCRIPTION VERSION 74HC174N; DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 74HCT174N 74HC174D; $016 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1 74HOT1740 74HC174DB; SSOP16 | plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 74HGT174DB 74HCO174PW; TSSOP16 | plastic thin shrink small outline package; 16 leads; body width 4.4mm | SOT403-1 74HOT174PW PIN DESCRIPTION PIN NO. SYMBOL NAME AND FUNCTION 1 MR asynchronous master reset (active LOW) 2,5,7,10, 12,15 Qp to O5 flip-flop outputs 3,4,6, 11,13, 14 Dg to Ds data inputs 8 GND ground (0 V) 9 cP clock input (LOW-to-HIGH, edge-triggered} 16 Voc positive supply voltage mae [7 U ie] Yee GQ, 15/Q na = 3 4 6 41 130 18 Dy Dy 28 Qy By O, Or fa] 174 ia] 4 : 9 Oy O27 Dy Og Og ! b2[4| Be Gp O, Gy Gy a4 O aE pa] *s 7203687 2 5 FF #W 12 16 ano [a | pe] cp 7293650 FZGIGHS Fig.1 Pin configuration. Fig.2 Fig.3 IEG logic symbol. 1998 Jul 08 3Philips Semiconductors Hex D-type flip-flop with reset; positive-edge trigger Product specification 74HC/HCT1 74 a 4 [8 n 13 14 Dg Dy FF Dy Q%4 Og Lo ah Up oh Yo of Yo ob Yo ob Yo r] cP fF cp FF cp F cp F icp F op F Rp Ap | Ap Ro Rp Ry aloo | t 1 t t i _l I | T I I 1] MR Og a a2 a3 oq Os 7z94961 2 5 7 10 12 15| Fig.4 Functional diagram. FUNCTION TABLE INPUTS OUTPUTS OPERATING MODES MR cP Dn Qn reset (clear) L x L load 1 H tT h H load 0 H t | L Note 1. H=HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH CP transition L = LOW voltage level | = LOW voltage level one set-up time prior to the LOW-to-HIGH CP transition X = don't care T= LOW-to-HIGH CP transition 7 nm FF FF FF cry o> cry aH ah al Ag Ap Ap Ay o a ? B-Def>s TZO3660 FF cP 4 pi J Td o 2 u oo a J _t a ig al? Fig.5 Logic diagram. a5 1998 Jul 08 4Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 DC CHARACTERISTICS FOR 74HC For the DC characteristics see 744I0HC PAMCUAICMOS Lowe Farviy Soecticagtons Output capability: standard log category: MS! AC CHARACTERISTICS FOR 74HC GND =0V; t, =f =6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS 74HC SYMBOL | PARAMETER UNIT Voc WAVEFORMS +25 40 to +85 | 40 to +125 (V) min. | typ. | max. | min. | max. | min. | max. tpu/ tpLy | propagation delay 55 165 205 250 ns 2.0 |Fig.6 CP to Qh 20 |33 At 50 45 16 28 35 43 6.0 tPHL propagation delay 44 150 190 225 | ns 2.0 |Fig.7 MR to Qn 16 |30 38 45 45 13 26 33 38 6.0 trac triy | output transition time 19 75 95 110 ns 2.0 |Fig.6 7 15 19 22 45 6 13 16 19 6.0 tw clock pulse width 80 17 100 120 ns 20 |Fig6 HIGH or LOW 16 |6 20 24 45 14 5 17 20 6.0 tw master reset pulse 80 12 100 120 ns 2.0 | Fig.7 width, LOW 16 |4 20 24 45 14 3 17 20 6.0 trem removal time 5 11 5 5 ns 2.0 |Fig.7 MR to CP 5 4 5 5 45 5 3 5 5 6.0 tsu set-up time 60 6 75 90 ns 2.0 | Fig.2 Dn to CP 12 |2 15 18 45 10 2 13 15 6.0 th hold time 3 6 3 3 ns 2.0 | Fig.8 D, to CP 3 2 3 3 4.5 3 2 3 3 6.0 Fax maximum clock pulse 6 30 5 4 MHz |2.0 | Fig.6 frequency 30 |90 24 20 45 35 107 28 24 6.0 1998 Jul 08 5Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 DC CHARACTERISTICS FOR 74HCT Output capability: standard log category: MS! Note to HCT types we i For the DC characteristics see YS HQVNCTAOUS SPR RES 8 aie OL. Stee C3 yag hpi oe act HOMOS Lowe Faruly Soectications. The value of additional quiescent supply current (Alec) for a unit load of 1 is given in the family specifications. To determine Alcc per input, multiply this value by the unit load coefficient shown in the table below. INPUT | UNIT LOAD COEFFICIENT Dn 0.25 cP 1.30 MR 1.25 AC CHARACTERISTICS FOR 74HCT GND =0V; t,==6 ns; C_ = 50 pF Tamb (C) TEST CONDITIONS 74HCT SYMBOL | PARAMETER UNIT | y WAVEFORMS +25 40 to +85 | 40 to +125 (vy min. | typ. | max. | min. | max. | min. | max. tpH/ tpLy | propagation delay 21 35 44 53 ns 45 |Fig.6 CP to Q, tPHL propagation delay 20 135 44 53 ns 45 | Fig? MR to Q, troc/triy | output transition time 7 15 19 22 ns 45 Fig.6 tw clock pulse width 16 |7 20 24 ns 45 |Fig.6 HIGH or LOW ty master reset pulse 20 |7 25 30 ns A5 | Fig.7 width; LOW trem removal time MRtoCP |12 |-3 16 18 ns 45 |Fig.7 tsu set-up time Dy, to CP 16 4 20 24 ns 45 Fig.8 th hold time D, to CP 5 3 5 5 ns 45 Fig.8 Frmax maximum clock pulse 30 63 24 20 MHz |45 |Fig.6 frequency 1998 Jul 08 6Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 AC WAVEFORMS MAR INPUT cP INPUT cP INPUT 4, OUTPUT rzaseeo a, OUTPUT vult 7283059 (1) HG : Vy = 50%; Vj = GND to Veo. (1) HC : Vy = 50%; V) = GND to Voc. HCT : Vy =1.3V; V) = GND to 3 . HCT : Vy = 1.2 V; Vv) = GND to 3 V. Fig.6 Waveforms showing the clock (GP) to output Fig.7 Waveforms showing the master reset (MR) (Q,) propagation delays, the clock pulse pulse width, the master reset to output (Q,) width, the output transition times and the propagation delays and the master reset to maximum clock pulses frequency. clock (CP) removal time. CP INPUT Vg UE 0, iNPUT | Ui Uy, Wi} Q,, OUTPUT Vy (1) HG : Vy = 50%; V| = GND to Voc. HOT : Vy =1.3 V; ; = GND to 3 V. 7293162 The shaded areas indicate when the input is permitted to change for predictable output performance Fig.8 Waveforms showing the data set-up and hold times for the data input (D,). 1998 Jul 08 7Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 PACKAGE OUTLINES DIP 16: plastic dual in-line package; 16 leads (300 mil); long body SOT38-1 ai. B = | seating plane 1 1 I I 1 4 od | < i? pin 1 index 1 8 0 5 10mm daa scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A Ay Ao 43 1} zy UNIT | ay | omin. | mie b by c pi E! e e L Me | My w ex. 140 | 053 | 0.32 | 21.8 | 648 39 8.25 95 mm 47) O51 37 | 444 | o38 | o23 | 214 | 620 | 254 | 782 | 34 | 790 | 33 | 0754 |) 22 . 0.055 | 0.021 | 0.013 | o86 | o26 015 | 0.32 | 0.37 inches | 0.19 | 0.020] 0.15 | Kare | gois | ooog | os4 | ona | 219 | 939 | ys | ost | ggg | 201 | 0.087 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT36-1 050G09 MO-001 AE on seat 1998 Jul 08 8Philips Semiconductors Hex D-type flip-flop with reset; positive-edge trigger $016: plastic small outline package; 16 leads; body width 3.9 mm Product specification 74HC/HCT1 74 $SOT109-1 |? 16 AAA AA Pp YN Ue _| _ _ _ _ __ | Ap | pin 1 index t { | Ly 7 et OL p Aa H f f | H H H H. Le el [e) ool Spe p 0 2.5 5mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) A UNIT | wax. | MH Az | As bp c pM) | EM) | e He L Lp Q v w y | Zz) ao 0.25 | 1.45 0.49 | 0.25 | 10.0 | 4.0 6.2 1.0 | 07 0.7 mm 1-75) gig | 12519 | oss} o19| a8 | 38 | 17 | 58) 1] o4 | o6 | 975) 975) 91 | 3 | go . 0.010 | 0.057 0.019 |0.0100] 0.39 | 0.16 0.244. 0.039 | 0.028 0.028] inches | 0.069 | 9 494] 0.049] 9-9! | 9.014 |0.0075| 0.38 | 0.15 | 295} 0.228 | 9-41 | pois | 0.020 | 9:9! | 9.01 | 9.004) 9 g15 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. REFERENCES VERSION pRouecTion | 'SSUE DATE IEC JEDEC EIAJ -95-01-23- SOT109-1 076E07S MS-012AC E} or one 9 1998 Jul 08Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1 Jet _ E al [A] Us sD == | 7 . U3 fT av , He +} V1] a 7 16 | g PITAL { | > f----}+----} Ad \ ft (Ag) * pin 1 indo Ly Us t 1 8 or | wi lp _' f -at | ] 4 | hwo a (oc 0 2.5 5mm scale DIMENSIONS (mm are the original dimensions) A 1 1 1 UNIT | wax, | 41 | Az | As | bp | c | DM | EM | e | He | L | Lp | @ v w y | z@) 29 0.21 | 1.80 0.38 | 0.20 | 64 | 54 79 1.03 | 09 1.00 | 8 mm | 20 | gos | 1.65/97 | 025) oo9| 60 52 | 28) 76] 178] oss | o7 | OF | O18) OT | oss | oe Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION PROJECTION ISSUE DATE IEC JEDEC ElAJ BAO SOT338-1 MO-150AC -} ono Od 1998 Jul 08 10Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm $OT403-1 . D ~ -t E +>[a] | Z a _ (HER re ay + ie AAAAR AAR | f {|} ha FS yr Ho TS, | | Loe I << | 1 1 8 detail X le | ewe . Qo 2.5 5mm La | scale DIMENSIONS (mm are the original dimensions) A UNIT | way. | Ar | Az | As | Bp e pM) | 2) | He L Lp Qa v w y Z| 49 015 | 0.95 0.30 0.2 5.1 45 66 0.75 o4 0.40 & mm 1.10 0.05 | 0.80 0.25 0.19 o4 4.9 43 0.65 6.2 1.0 0.50 0.3 0.2 0.13 o4 0.06 a Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. REFERENCES VERSION pRovecTION | 'SSUE DATE IEC JEDEC EIAJ SOT403-1 MO-153 Et 95-04-04 1998 Jul 08 11Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook 1C26; Integrated Circuit Packages (order code 9398 652 90011). DIP SOLDERING BY DIPPING OR BY WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T sig max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. REPAIRING SOLDERED JOINTS Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. SO, SSOP and TSSOP REFLOW SOLDERING Reflow soldering techniques are suitable for all SO, SSOP and TSSOP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. 1998 Jul 08 Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. WAVE SOLDERING Wave soldering can be used for all SO packages. Wave soldering is not recommended for SSOP and TSSOP packages, because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. If wave soldering is used - and cannot be avoided for SSOP and TSSOP packages - the following conditions must be observed: A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. The longitudinal axis of the package footprint must be parallel to the solder flow and must incorporate solder thieves at the downstream end. Even with these conditions: Only consider wave soldering SSOP packages that have a body width of 4.4 mm, that is SSOP16 (SOT369-1) or SSOP20 (SOT266-1). * Do not consider wave soldering TSSOP packages with 48 leads or more, that is TSSOP48 (SOT362-1) and TSSOP56 (SOT364-1). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications.Philips Semiconductors Product specification Hex D-type flip-flop with reset; positive-edge trigger 74HC/HCT1 74 REPAIRING SOLDERED JOINTS Fix the component by first soldering two diagonally- opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1998 Jul 08 13