R0201-BS62LV2001 Revision 2.5
April 2002
1
PIN CONFIGURATIONS
A17
Very Low Power/Voltage CMOS SRAM
256K X 8 bit
• Wide Vcc operation voltage : 2.4V ~ 5.5V
• Very low power consumption :
Vcc = 3.0V C-grade : 20mA (Max.) operating current
I- grade : 25mA (Max.) operating current
0.1uA (Typ.) CMOS standby current
Vcc = 5.0V C-grade : 35mA (Max.) operating current
I- grade : 40mA (Max.) operating current
0.6uA (Typ.) CMOS standby current
• High speed access time :
-70 70ns(Max.) at Vcc = 3.0V
-10 100ns(Max.) at Vcc = 3.0V
• Automatic power down when chip is deselected
• Three state outputs and TTL compatible
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE2, CE1, and OE options
• All I/O pins are 3V/5V tolerant
FEATURES
The BS62LV2001 is a high performance, very low power CMOS
Static Random Access Memory organized as 262,144 words by 8 bits
and operates in a wide range of 2.4V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
0.1uA and maximum access time of 70ns in 3V operation.
Easy memory expansion is provided by an active LOW chip
enable (CE1), an active HIGH chip enable (CE2), and active LOW
output enable (OE) and three-state output drivers.
The BS62LV2001 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV2001 is available in DICE form, JEDEC standard 32 pin
450mil Plastic SOP, 8mmx13.4mm STSOP, and 8mmx20mm TSOP.
DESCRIPTION
BLOCK DIAGRAM
PRODUCT FAMILY
Brilliance Semiconductor Inc.reserves the right to modify document contents without notice.
Address
Input
Buffer
Row
Decoder
Memory Array
1024 x 2048
Column I/O
Sense Amp
Write Driver
Column Decoder
Data
Buffer
Output
Address Input Buffer
A8 A3 A2 A1 A10
Data
Buffer
Input
Control
Gnd
Vdd
OE
DQ7
DQ6
DQ5
DQ4
A16
A6
A7
A15
8
8
8
8
DQ3
DQ2
DQ1
DQ0
A5
A4
A13
16
256
2048
1024
20
A14
A12
A9
BS62LV2001
A11 A0
OE
WE
CE1
CE2
BSI
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
A11
A9
A8
A13
WE
CE2
A15
VCC
A17
A16
A14
A12
A7
A6
A5
A4
•
BS62LV2001TC
BS62LV2001STC
BS62LV2001TI
BS62LV2001STI
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
DQ7
DQ6
DQ5
DQ4
DQ3
•
BS62LV2001SC
BS62LV2001SI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
R0201-BS62LV2001 Revision 2.5
April 2002
2
R0201-BS62LV2001
Name Function
A0-A17 Address Input These 18 address inputs select one of the 262,144 x 8-bit words in the RAM
CE1 Chip Enable 1 Input
CE2 Chip Enable 2 Input
CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when
data read from or write to the device. If either chip enable is not active, the device is
deselected and is in a standby power mode. The DQ pins will be in the high
impedance state when the device is deselected.
WE Write Enable Input The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0 – DQ7 Data Input/Output
Ports
These 8 bi-directional ports are used to read data from or write data into the RAM.
Vcc Power Supply
Gnd Ground
TRUTH TABLE
PIN DESCRIPTIONS
BSI BS62LV2001
CIN Input
Capacitance VIN=0V 6 pF
CDQ Input/Output
Capacitance VI/O=0V 8 pF
RANGE AMBIENT
TEMPERATURE Vcc
Commercial 0 O C to +70 O C2.4V ~ 5.5V
Industrial -40 O C to +85 O C2.4V ~ 5.5V
ABSOLUTE MAXIMUM RATINGS(1) OPERATING RANGE
CAPACITANCE (1) (TA = 25oC, f = 1.0 MHz)
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
1. This parameter is guaranteed and not tested.
SYMBOL PARAMETER RATING UNITS
VTERM Terminal Voltage with
Respect to GND
-0.5 to
Vcc+0.5 V
TBIAS Temperature Under Bias C-40 to +125 O
TSTG Storage Temperature C-60 to +150 O
PTPower Dissipation 1.0 W
IOUT DC Output Current mA20
MODE WE CE1 CE2 OE I/O OPERATION Vcc CURRENT
XHXX
Not selected
(Power Down) ICCSB, I CCSB1
XXLX High Z
Output Disabled H L H H High Z ICC
Read H L H L DOUT ICC
Write L L H X DIN ICC
SYMBOL PARAMETER CONDITIONS MAX. UNIT
R0201-BS62LV2001 Revision 2.5
April 2002
3
BSI BS62LV2001
SYMBOL PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
VDR Vcc for Data Retention CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V 1.5 -- -- V
ICCDR Data Retention Current CE1 Њ Vcc - 0.2V, CE2 Љ 0.2V,
VIN Њ Vcc - 0.2V or VIN Љ 0.2V -- 0.01 0.5 uA
tCDR
Chip Deselect to Data
Retention Time 0 -- -- ns
tROperation Recovery Time
See Retention Waveform
TRC
(2) -- -- ns
PARAMETER
NAME PARAMETER TEST CONDITIONS MIN. TYP. (1) MAX. UNITS
Vcc=3.0V
V
IL Guaranteed Input Low
Voltage(2) Vcc=5.0V -0.5 -- 0.8 V
Vcc=3.0V 2.0
V
IH Guaranteed Input High
Voltage(2) Vcc=5.0V 2.2 -- Vcc+0.2 V
I
IL Input Leakage Current Vcc = Max, VIN = 0V to Vcc -- -- 1 uA
I
OL Output Leakage Current Vcc = Max, CE1= VIH, CE2= VIL, or
OE = VIH, VI/O = 0V to Vcc -- -- 1 uA
Vcc=3.0V
V
OL Output Low Voltage Vcc = Max, IOL = 2mA Vcc=5.0V -- -- 0.4 V
Vcc=3.0V
V
OH Output High Voltage Vcc = Min, IOH = -1mA Vcc=5.0V 2.4 -- -- V
Vcc=3.0V -- -- 20
I
CC Operating Power Supply
Current
CE1 = VIL, or CE2 = VIH,
IDQ = 0mA, F = Fmax(3)
Vcc=5.0V -- -- 35 mA
Vcc=3.0V -- -- 1
I
CCSB Standby Current-TTL CE1 = VIH, or CE2 = VIL,
IDQ = 0mA, F = Fmax(3)
Vcc=5.0V -- -- 2 mA
Vcc=3.0V -- 0.1 0.7
I
CCSB1 Standby Current-CMOS
CE1ЊVcc-0.2V, CE2Љ0.2V,
VINЊVcc-0.2V or VINЉ0.2V Vcc=5.0V -- 0.6 6 uA
1. Typical characteristics are at TA = 25oC.
3. Fmax = 1/tRC .
2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
DATA RETENTION CHARACTERISTICS ( TA = 0oC to + 70oC )
1. Vcc = 1.5V, TA= + 25OC
2. tRC = Read Cycle Time
DC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC )
LOW VCC DATA RETENTION WAVEFORM (1) ( CE1 Controlled )
CE1
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIHVIH
Vcc VDR 1.5V
≥
CE1 Vcc - 0.2V
≥
LOW VCC DATA RETENTION WAVEFORM (2) ( CE2 Controlled )
CE2
Data Retention Mode
Vcc
tCDR
Vcc
tR
VIL
VIL
Vcc VDR Њ1.5V
CE2 Љ0.2V
R0201-BS62LV2001 Revision 2.5
April 2002
4
R0201-BS62LV2001
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS62LV2001-70
MIN. TYP. MAX.
BS62LV2001-10
MIN. TYP. MAX. UNIT
tAVAX tRC Read Cycle Time 70 -- -- 100 -- -- ns
tAVQV tAA Address Access Time -- -- 70 -- -- 100 ns
tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 70 -- -- 100 ns
tE2HOV tACS2 Chip Select Access Time (CE2) -- -- 70 -- -- 100 ns
tGLQV tOE Output Enable to Output Valid -- -- 35 -- -- 50 ns
tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 15 -- -- ns
tE2HOX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 15 -- -- ns
tGLQX tOLZ Output Enable to Output in Low Z 10 -- -- 15 -- -- ns
tE1HQZ tCHZ1 Chip Deselect to Output in High Z (CE1) 0--350--40ns
tE2HQZ tCHZ1 Chip Deselect to Output in High Z (CE2) 0--350--40ns
tGHQZ tOHZ Output Disable to Output in High Z 0--300--35ns
tAXOX tOH Output Disable to Output Address Change 10 -- -- 15 -- -- ns
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Vcc/0V
5ns
0.5Vcc
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
READ CYCLE
AC TEST CONDITIONS
AC TEST LOADS AND WAVEFORMS
KEY TO SWITCHING WAVEFORMS
WAVEFORM INPUTS OUTPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
DON T CAR
ANY CHANG
PERMITTED
E: CHANGE :
E STATE
DOES NOT
APPLY
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
MAY CHANGE
FROM L TO H
WILL BE
CHANGE
FROM L TO H
,
BSI BS62LV2001
Ω667
THEVENIN EQUIVALENT
ALL INPUT PULSES
→
10% 90%
←
Vcc
GND
→←5ns
90% 10%
1.73V
OUTPUT
FIGURE 2
3.3V
OUTPUT
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
1404
5PF
FIGURE 1B
3.3V
INCLUDING
JIG AND
SCOPE
Ω
1269
Ω
100PF
FIGURE 1A
1404
OUTPUT
R0201-BS62LV2001 Revision 2.5
April 2002
5
R0201-BS62LV2001
NOTES:
1. WE is high for read Cycle.
2. Device is continuously selected when CE1 = VIL and CE2= VIH.
3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high.
4. OE = VIL .
5. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B.
The parameter is guaranteed but not 100% tested.
±
BSI BS62LV2001
READ CYCLE3 (1,4)
READ CYCLE2 (1,3,4)
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1 (1,2,4)
tRC
tOH
tAA
DOUT
ADDRESS
tOH
tCLZ
(5)
DOUT
CE2
CE1
(5)
tACS2
tACS1
tOH
tRC
tOE
tCLZ2
tCHZ2
(2,5)
DOUT
CE2
CE1
OE
ADDRESS
(5)
tCLZ1
(5) tACS1
tACS2
tCHZ1
(1,5)
tOHZ (5)
tOLZ
tAA
tCHZ1, t CHZ2
R0201-BS62LV2001 Revision 2.5
April 2002
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R0201-BS62LV2001
JEDEC
PARAMETER
NAME
PARAMETER
NAME DESCRIPTION BS62LV2001-70
MIN. TYP. MAX.
BS62LV2001-10
MIN. TYP. MAX. UNIT
tAVAX tWC Write Cycle Time 70 -- -- 100 -- -- ns
tE1LWH tCW Chip Select to End of Write 70 -- -- 100 -- -- ns
tAVWL tAS Address Set up Time 0 -- -- 0 -- -- ns
tAVWH tAW Address Valid to End of Write 70 -- -- 100 -- -- ns
tWLWH tWP Write Pulse Width 35 -- -- 50 -- -- ns
tWHAX tWR1 Write Recovery Time (CE1 , WE) 0 -- -- 0 -- -- ns
tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns
tWLOZ tWHZ Write to Output in High Z 0--300--40 ns
tDVWH tDW Data to Write Time Overlap 30 -- -- 40 -- -- ns
tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns
tGHOZ tOHZ Output Disable to Output in High Z 0--300--40 ns
tWHQX tOW End of Write to Output Active 5----10---- ns
AC ELECTRICAL CHARACTERISTICS ( TA = 0oC to + 70oC, Vcc = 3.0V )
WRITE CYCLE
SWITCHING WAVEFORMS (WRITE CYCLE)
BSI BS62LV2001
WRITE CYCLE1 (1)
tWR1
tWC
(3)
tCW
(11)
(11)
tCW
(2)
tWP
tAW
tOHZ
(4,10)
tAS
tWR2
(3)
tDH
tDW
DIN
DOUT
WE
CE2
CE1
OE
ADDRESS
(5)
(5)
R0201-BS62LV2001 Revision 2.5
April 2002
7
BSI BS62LV2001
WRITE CYCLE2 (1,6)
tWC
tCW
(11)
(11)
tCW
(2)
tWP
tAW
tWHZ
(4,10)
tAS
tWR2
(3)
tDH
tDW
DIN
DOUT
WE
CE2
CE1
ADDRESS
(5)
(5)
tDH
(7) (8)
(8,9)
NOTES:
1. WE must be high during address transitions.
2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low.
All signals must be active to initiate a write and any one signal can terminate a write by going
inactive. The data input setup and hold timing should be referenced to the second transition edge
of the signal that terminates the write.
3. TWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write
cycle.
4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the
outputs must not be applied.
5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low
transitions or after the WE transition, output remain in a high impedance state.
6. OE is continuously low (OE = VIL ).
7. DOUT is the same phase of write data of this write cycle.
8. DOUT is the read data of next address.
9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input
signals of opposite phase to the outputs must not be applied to them.
10. Transition is measured 500mV from steady state with CL= 5pF as shown in Figure 1B. The
parameter is guaranteed but not 100% tested.
11. TCW is measured from the later of CE1 going low or CE2 going high to the end of write.
±
R0201-BS62LV2001 Revision 2.5
April 2002
8
BSI BS62LV2001
PACKAGE
T: TSOP (8mm x 20mm)
ST: Small TSOP (8mm x 13.4mm)
S: SOP
D: DICE
ORDERING INFORMATION
BS62LV2001 X X ˀˀ Y Y
GRADE
C: +0oC ~ +70oC
I: -40oC ~ +85oC
SPEED
70: 70ns
10: 100ns
STSOP - 32
R0201-BS62LV2001 Revision 2.5
April 2002
9
BSI BS62LV2001
PACKAGE DIMENSIONS (continued)
TSOP - 32
BASE METAL
WITH PLATING
cc1
SECTION A-A
b1
b
SOP -32
R0201-BS62LV2001 Revision 2.5
April 2002
10
BSI
R0201-BS62LV2001
REVISION HISTORY
Revision Description Date Note
2.2 2001 Data Sheet release Apr. 15, 2001
2.3 Modify Standby Current (Typ. and
Max.)
Jun. 29, 2001
2.4 To add DICE form March 06,2002
2.5 Modify some AC parameters.
Modify 5V ICCSB1_Max(I-grade)
from 10uA to 25uA.
April,11,2002
BS62LV2001
