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Bluegiga Technologies assumes no responsibility for any errors which may appear in this

manual. Furthermore, Bluegiga Technologies reserves the right to alter the hardware, software,

and/or specifications detailed here at any time without notice and does not make any

commitment to update the information contained here. Bluegiga’s products are not authorized

for use as critical components in life support devices or systems.

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11 Electrical Characteristics ........................................................................................ 45

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15 Moisture Sensitivity Level (MSL) classification ........................................................... 55

16 Contact Information .............................................................................................. 56

capable of running the Bluetooth

 Piconet and Scatternet Support

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 A-law/µ-law/linear voice data (from host)

all supported. The features are configured in firmware.

Any of the PIO lines can be configured as interrupt request lines or as wake-up lines from sleep

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WT21 uses an internal 26 MHz crystal as a Bluetooth reference clock. All WT21 internal digital

PSKEY_DEEP_SLEEP_EXTERNAL_CLOCK_SOURCE.

The CLK_32K pad is in the VDD_PADS domain with all the other digital I/O pads and is driven

between levels specified in Section 11.3.4.

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Data may be written or read one word at a time or the auto increment feature may be used to

access blocks.

5.2 Instruction Cycle

WT21 is the slave and receives commands on SPI_MOSI and outputs data on SPI_MISO. Table

SPI_CLK. The master provides the clock on SPI_CLK. The transaction is terminated by taking

SPI_CS# high.

Sending a command word and the address of a register for every time it is to be read or written

is a significant overhead, especially when large amounts of data are to be transferred. To

overcome this WT21 offers increased data transfer efficiency via an auto increment operation.

To invoke auto increment, SPI_CS# is kept low, which auto increments the address, while

providing an extra 16 clock cycles for each extra word to be written or read.

To write to WT21, the 8-bit write command (00000010) is sent first (C[7:0]) followed by a 16-

bit address (A[15:0]). The next 16-bits (D[15:0]) clocked in on SPI_MOSI are written to the

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Reading from WT21 is similar to writing to it. An 8-bit read command (00000011) is sent first

(C [7:0]), followed by the address of the location to be read (A[15:0]). WT21 then outputs on

SPI_MISO a check word during T[15:0] followed by the 16-bit contents of the addressed

location during bits D[15:0].

The check word is composed of {command, address [15:8]}. The check word may be used to

confirm a read operation to a memory location. This overcomes the problems encountered with

typical serial peripheral interface slaves, whereby it is impossible to determine whether the data

returned by a read operation is valid data or the result of the slave device not responding.

If SPI_CS# is kept low, data from consecutive locations is read out on SPI_MISO for each

subsequent 16 clocks, until the transaction terminates when SPI_CS# is taken high.

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If in UART mode, the MCU selects the UART transfer protocol automatically using the unused

SDIO pins shown in Table 9

Table 9: SDIO_CLK and SDIO_CMD transfer Protocols

6.2 UART Interface

Figure 7: Universal Asynchronous Receiver

Four signals implement the UART function, as shown in Figure 8. When WT21 is connected to

another digital device, UART_RX and UART_TX transfer data between the two devices. The

remaining two signals, UART_CTS and UART_RTS, can be used to implement RS232 hardware

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Note:

Baud rate is the measure of symbol rate i.e. , the number of distinct symbol changes (signaling events)

made to transmission medium per second in a digitally modulated signal.

The UART interface is capable of resetting WT21 on reception of a break signal. A break is

identified by a continuous logic low (0V) on the UART_RX terminal, as shown in Figure 9. If

tBRKis longer than the value, defined by the PSKEY_HOSTIO_UART_RESET_TIMEOUT, (0x1a4),

a reset occurs. This feature allows a host to initialise the system to a known state. Also, WT21

can emit a break character that may be used to wake the host. By default this feature is

disabled and it is recommended to enable it by setting PSKEY_HOSTIO_UART_RESET_TIMEOUT.

Figure 8: Break Signal

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Table 11: Standard Baud Rates

The UART interface for WT21 is tri-state while the chip is being held in reset. This allows the

user to daisy chain devices onto the physical UART bus. The constraint on this method is that

any devices connected to this bus must tri-state when WT21 reset is de-asserted and the

firmware begins to run.

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The CSPI is a host interface which shares pins with the SDIO. It has been defined by CSR with

Note:

The CSPI is entirely separated from the debug Serial Peripheral Interface

The CSPI allows access to the following:

MMU buffers are accessed using burst read/writes. The command and address fields are used to

access fails. This interrupt line is shared with the SDIO functions.

Table 12 shows the mapping of SDIO pins onto the CSPI functions when CSPI is enabled.

Table 12: SDIO Mapping to CSPI Functions

The CSPI Interface is an extension of the basic SPI Interface, with the access type determined

by the following fields:

 8-bit command

 24-bit address

 16-bit burst length (optional). Only applicable for burst transfers into or out of the

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The command and address are locked into the slave, followed by 16bits of write data. An Error

Byte is returned on the MISO signal indicating whether or not the transfer has been successful.

Figure 9: CSPI Register Write Cycle

The command and address field are clocked into the slave, the slave then returns the following:

 16-bits of read data

Figure 10: CSPI Register Read Cycle

As with a register access, the command and address fields are transferred first. There is an

optional length field transferred after the address. The use of the length field is controlled by

the LengthFieldPresent bit in the Function 0 registers, which is cleared on reset.

Figure 11: CSPI Burst Write Cycle

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Burst reads have a programmable amount of padding data that is returned by the slave. 0-15

bytes are returned as defined in the BurstPadding register. Following this the Error byte is

returned followed by the data. Once the transfer has started, no further padding is needed.

A FIFO within SDIO_TOP will pre-fetch the data. The address is not retransmitted, and is auto-

updated within the slave.

The length field is transmitted if LengthFieldPresentin the Function 0 registers is set. In the

absence of a length field the CSB signal is used to indicate the end of the burst.

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Figure 21: PCM Master Timing Long Frame Sync

Figure 22: PCM Master Timing Short Frame Sync

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Table 13: PCM Slave Timing

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When in this mode and with long frame sync, the length of PCM_SYNC can be either 8 or 16

cycles of PCM_CLK, determined by LONG_LENGTH_SYNC_EN in PSKEY_PCM_CONFIG32.

Equation XXX describes PCM_CLK frequency when being generated using the internal 48MHz

clock:

CNT_RATE, CNT_LIMIT and SYNC_LIMIT are set using PSKEY_PCM_LOW_JITTER_CONFIG. As

an example, to generate PCM_CLK at 512kHz with PCM_SYNC at 8kHz, set

PSKEY_PCM_LOW_JITTER_CONFIG to 0x08080177.

The PCM configuration is set using the PS Keys, PSKEY_PCM_CONFIG32 described in Table 14,

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8.2 Digital Audio Interface (I2S)

The digital audio interface supports the industry standard formats for I2S, left-justified (LJ) or

right-justified(RJ). The interface shares the same pins as the PCM interface, which means each

audio bus is mutually exclusive in its usage. Table 17 lists these alternative functions. Figure 26

shows the timing diagram.

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Figure 25: Digital Audio Interface Modes

The internal representation of audio samples within BlueCore6-ROM (QFN) is 16-bit and data on

SD_OUT is limited to 16-bit per channel.

Table 19: Digital Audio Interface Slave Timing

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Table 20: Digital Audio Interface Master Timing

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The module can be powered from a high-voltage rail through both regulators and the output of

Figure 28: Voltage Regulator Configuration

9.2 VREG_ENABLE

The regulator enable pin VREGENABLE is used to enable the WT21. VREGENABLE enables both

9.3 RST#

The RST# pin is an active low reset and is internally filtered using the internal low frequency

clock oscillator. A reset is performed between 1.5 and 4.0ms following RST# being active. It is

recommended that RST# be applied for a period greater than 5ms.

The power on reset occurs when the core supply falls below typically 1.24V and is released

when core voltage rises above typically 1.31V. At reset the digital I/O pins are set to inputs for

a reset, WT21 assumes the maximum XTAL frequency, which ensures that the internal clocks

run at a safe (low) frequency until WT21 is configured for the actual XTAL frequency.