Features High speed tg, = 12 os CMOS for optimum speed/power e Low active power PRELIMINARY CY7C107A Functional Description The CY7CI107A is a high-performance CMOS static RAM organized as 1,048,576 words by 1 bit. Easy memory expansion is provided by an active LOW chip enable (CE) and three-state drivers. The device IM x 1 Static RAM Reading from the device is accomplished by taking chip enable (CE) LOW while write enable (WE) remains HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the data output $25 mW hasan automatic power-down feature that (Pout) pin. Low standby power reduces power consumption by more than 275 mW 65% when deselected. The output pin (DouT) is placed in a high- ; ; Writing to the device is accomplished by impedance state when the device is dese- ow (optional) taking chip enable (CE) and write enable lected (CE HIGH) or during awrite opera- ae (WE) inputs LOW. Data on the input pin tion (CE and WE LOW). e Automatic power-down when (Dyn) is written into the memory location deselected specified on the address pins (Ag through The CY7CI07A is available in standard e TTL-compatible inputs and outputs Ayj9). 400-mil-wide DIPs and SOJs, Logic Block Diagram Pin Configuration a DIP/SOJ SJ Din Top View Voc Ag Ag INPUT BUFFER A; ty > x A oa oc ab Ag Ag Oo a NC 18 S Ag Amy EN 512x 2048 << Ao aS ARRAY o hs D A ems > OUT Ao Aye wW Ow Ma z . CE 1074-2 COLUMN DOWN ne DECODER - CE TEETER ERTS OrnNO TH ORD OH Terre rere WE 107A-1 Selection Guide 7C1O7TA12 7C1IOTA-15 7C107A-20 =| 7C1O7A25 7C1O7TA35 Maximum Access Time (ns} 12 1s 20 28 35 Maximum Operating Commercial 150 135 125 120 110 Current (mA Military 145 135 130 120 Maximum Standby Commercial 50 40 30 30 25 Current (mA) Military 40 30 30 25 Cypress Semiconductor Corporation 3901 North First Street @ SanJose @ CA95134 @ 408-943-2600 December 1992 Revised April 1995PRELIMINARY _CY7C107A Maximum Ratings (Above which the useful life maybe impaired. Foruser guidelines, Latch-Up Current ................. 200s eee ee >200 mA not tested.) Storage Temperature ..............0005 65C to +150C Operating Range Ambient Temperature with Ambient Power Applicd .......secsseeeeseeees -55C to #125C Range Temperature! Vee Supply Voltage on Vcc Relative to GNDU] . -0.5V to +7.0V Commercial 0C to +70C SV + 10% DC Voltage Applied to Outputs Military 55C to +125C SV + 10% in High Z Statel] .... 0... -0.5V to Voc +0.5V Nols otes: be Input Voltagel!] ee es -0.5V to Vec +0.5V 1 Vin (min.) = 2,0V for pulse durations of less than 20 ns. Current into Outputs (LOW) .................005 20mA 2. Ty isthe instant on case temperature. Static Discharge Voltage ...............000000 ee >2001V (per MIL-STD-883, Method 3015} Electrical Characteristics Over the Operating Rangel?) FCIOTA-12 7CIO7TA15 TC1O7A20 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vcc = Min., Jog = -4.0 mA 24 24 24 Vv Voltage VoL Output LOW Vec = Min., Io, = 8.0mA 0.4 0.4 0.4 Vv Voltage Vin Input HIGH 22 | Vcect | 22 | Vecot | 22 | Voct | V Voltage 0.3 0.3 0.3 VIL Input LOW -03 0.8 03 0.8 03 0.8 Vv Voltagel] Ikx Input Load Current | GND < Vj < Vcc -1 +1 -1 +1 -1 +1 pA loz Output Leakage GND < V] < Veo -5 +5 -5 +5 -5 +5 pA Current Output Disabled Ios Output Short Vcc = Max., Vout = GND 300 300 -300 | mA Circuit Currentl4 Icc sce Dperating Vcc = Max., Com! 150 135 125 | mA upply Current Iout = OmA, - f = fax = I/trc Mil 145 135 Ispi Automatic CE Max.. Vcc, Com! 50 40 30 mA Power-Down CE > Vin, Current Vin = Vin or - TIL Inputs VIN < VIL Mil 40 30 =I MAX Isp2 Automatic CE Max. Vcc, Com! 2 2 2 mA Power-Down CE > Vcc 0.3V, Current Vin = Veco 0.3V or ag 3 2 CMOS Inputs Vin = 0.39, f=0PRELIMINARY _CY7C107A Electrical Characteristics Over the Operating Rangel] (continued) TC1IOTA25 FCIOTA35 Parameter Description Test Conditions Min. Max. Min. Max. Unit Vou Output HIGH Vcc = Min., Io = - 4.0 mA 24 24 Vv Voltage VoL Output LOW Voltage | Vcc = Min., Io, = 8.0 mA 0.4 0.4 Vv Vi Input HIGH Voltage 2.2 Vect 03 2.2 Vect 0.3 Vv VIL Input LOW Voltagel!] -03 0.8 -03 0.8 Vv Ix Input Load Current GND < V] < Vcc -1 +1 -1 +1 pA loz Output Leakage GND < V|< Vcc, -5 +5 -5 +5 pA Current Output Disabled Tos Output Short Vcc = Max., Vout = GND 300 300 mA Circuit Currentl4] Iec voc Operating Voc = Max., Com'l 120 110 mA upply Current Tout = OmA, - f = fax = Ltrc Mil 130 120 Ign Automatic CE Max.. Vcc, Com! 30 25 mA Power-Down. CE > Vm, Current VIN =VIH or - TIL Inputs Vin < VIL Mil 30 25 f =f wax Ispe Automatic CE Max. Voc, Com! 2 2 mA Power-Down CE > Vcc 0.3V, Current Vin = Vcc 0.3V or Mil 2 3 CMOS Inputs Vn < 0.39, f=0 Capacitance] Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF - Voc = 5.0V Cin: Controls 10 pF CouT Output Capacitance 10 pF Notes: 3. See the last page of this specification for Group A subgroup testing in- formation. these parameters. 4, Notmore than 1 output should beshorted at one time. Duration of the short circuit should not exceed 30 seconds. 5. Tested initially and after any design or process changes that may affectPRELIMINARY _CY7C107A Ri 4802 R1 4802 SV ow SV or ALL INPUT PULSES OUTPUT OUTPUT , __ 30 pF $ Re 5 pF = Re [ + 2550 | 7 2550 INCLUDING - ek INCLUDING e JGAND = = JGAND = = toma SCOPE (a) SCOPE (b) 107A-3 Equivalent to: THEVENIN EQUIVALENT 167Q2 OUTPUT $vv0 1.73 Switching Characteristics: 6] Over the Operating Range FCIOTA-12 | 7C1O7A15 | 7CIO7TA20 | TCIO7TA25 | 7C107A35 Parameter Description Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 35 ns tad Address to Data Valid 12 15 20 25 35 ns toHA Pata a from Address 3 3 3 3 3 ns tacE CE LOW to Data Valid 12 15 20 25 35 ns tLZcE CE LOW to Low Zl] 3 3 3 3 3 ns tHzcE CE HIGH to High ZI7. 3) 6 7 8 10 10 ns teu CE LOW to Power-Up 0 0 0 0 0 ns tpp CE HIGH to Power-Down 12 15 20 25 35 ns WRITE CYCLE! twe Write Cycle Time 12 1s 20 25 35 ns tsce CE LOW to Write End 10 12 15 20 25 ns taw Adaress Set-Up to Write 10 12 15 20 5 ns tHA fades Hold from Write 0 0 0 0 0 ns tsa Address Set-Up to Write 0 0 0 0 0 ns tPpWE WE Pulse Width 10 12 15 20 25 ns tsp Data Set-Up to Write End 7 8 10 15 20 ns typ Data Holdfrom Write End | 0 0 0 0 0 ns tLZWE WE HIGH to Low 771 3 3 3 3 3 ns tHZWE WE LOW to High ZU ) 6 7 8 10 10 | as Notes: __ 6, Test conditions assume signal transition time of 3 nsorless,timingref- 9, The internal write time of the memory is defined by the overlap of CE erence levels of L.SV., inputpulse levels of 0 to 3.0. and output loading LOW and WE LOW. CE and WE must be LOW to initiate awrite. and of the specified Ip. /Ipy and 30-pF load capacitance. the transition ofany of these signals can terminate the write. The input 7. Atany given temperature and voltage condition. tyzcp is less than data set-up and hold timing should be referenced to the leading edge tizce and tyzwe is less than tuzwe for any given device. of the signal that terminates the write. 8 tyzcr and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage.PRELIMINARY _CY7C107A Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!) Min. | Max. | Min. | Max. | Unit Vpr Vcc for Data Retention 2.0 2.0 Vv Iccpr Data Retention Current Vcc = Vopr = 2.09, 50 70 pA tcprl) Chip Deselect to Data Retention Time Va Wenn dor 0 0 ns tpP] Operation Recovery Time Vin 5. 0.3V tre tre ns Note: 10. No input may exceed Voc + 05V. Data Retention Waveform DATA RETENTION MODE + Yoo 4.5V Vpp > 2V /\ 45 + topra tk 107A-5 Switching Waveforms Read Cycle No. 1[11, 12] i tao | ADDRESS * a tan | H$ tons, ___ DATA OUT PREVIOUS DATA VALID KXXKK DATA VALID 1O7A-6 Read Cycle No, 212, 13] ADDRESS xX Y tre / bwt tL7cE t tHZcE HIGH CE \ f\ & ' tace HIGH IMPEDANCE 7 IMPEDANCE DATA OUT N DATA VALID _ tpy p {pp SuPPiS \ Icc 50% 50% AE CURRENT VK ISB 107A-7 Notes: __ __ 11. Device is continuously selected, CE = Vj,. 13. Address valid prior to or coincident with CE transition LOW. 12. WE is HIGH for read cycle.PRELIMINARY _CY7C107A Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)l4) at two ADDRESS Y YY to tsa a tsce > CE Ze N / at taw at tus cr NO IW we S N Z a tsp = typ DATA IN DATA VALID DATA OUT HIGH IMPEDANCE 107A-8 Write Cycle No. 2 (WE Controlled)!4) ADDRESS tsp typ DATA IN DATA VALID tuzwe =| tLzwe | HIGH IMPEDANCE DATA OUT DATA UNDEFINED FX 107A-9 Note: 14. 1fCEgoes HIGH simultaneously with WE going HIGH, the output re- mains in a high-impedance state. Truth Table CE | WE Dour Mode Power H | X | Highz Power-Down Standby (Isp) L | H | Data Out Read Active (Icc} L | L | HighZ Write Active cc}PRELIMINARY _CY7C107A Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7TC1IO7TA12PC P41 28-Lead (400-Mil) Molded DIP | Commercial CY7TC1IO7FA-12VC V28 28-Lead (400-Mil) Molded SOJ 15 CY7CIO7TA15PC P41 28-Lead (400-Mil) Molded DIP | Commercial CY7TC1IOFTA-15VC V28 28-Lead (400-Mil) Molded SOJ CY7C107A15DMB D42 28-Lead (400-Mil} CerDIP Military 20 CY7C1O7A20PC P41 28-Lead (400-Mil) Molded DIP | Commercial CY7TC1O7A20VC V28 28-Lead (400-Mil) Molded SOJ CY7C107A-20DMB D42 28-Lead (400-Mil} CerDIP Military 25 CY7TC1IO7TA25PC P41 28-Lead (400-Mil) Molded DIP | Commercial CYTC1IOFA25VC V28 28-Lead (400-Mil) Molded SOJ CY7C107A25DMB p42 28-Lead (400-Mil} CerDIP Military 35 CY7TC1IO7TA35PC P41 28-Lead (400-Mil) Molded DIP | Commercial CY7TCIOTA35VC V28 28-Lead (400-Mil) Molded SOJ CY7C107A35DMB p42 28-Lead (400-Mil} CerDIP Military Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter Subgroups Vou 1, 2,3 READ CYCLE VoL 1, 2,3 tre 7, 8,9, 10, 11 Vin 1, 2,3 tAa 7, 8, 9, 10, 11 Vit Max. 1,2,3 toHA 7, 8, 9, 10, 11 Ix 1, 2,3 tack 7, 8,9, 10, 11 loz 1, 2,3 WRITE CYCLE Tec 1, 2,3 twc 7, 8, 9, 10, 11 Isp1 1, 2,3 tscE 7, 8, 9, 10, 11 Isp 1, 2,3 taw 7, 8, 9, 10, 11 tHA 7, 8,9, 10, 11 Document #: 38-00232-A tsa 7, 8, 9, 10, 11 tpwE 7, 8, 9, 10, 11 tsp 7, 8, 9, 10, 11 typ 7, 8, 9, 10, 11PRELIMINARY _CY7C107A Package Diagrams 28-Lead (400-Mil) CerDIP D42 PIN 1. DIMENSIONS IM IMCHES Oifiritr it) | } MIM. ; MAS, _ LL sts 05 MIh, ~ Le BATE PLANE as - Ldza so9 * eo oot) ES no O15) SEATING PLANE 20 28-Lead (400-Mil) Molded DIP P41 PIN 1 yey MT gM en on To th, _ DIMENSIONS IM INCHET MIM, MAS, O340 390 warner L o.u0 a) 1350 4,330 1420 1425 SEATING PLANE 14 O2l0 Mas, O.008 3 OMIM, pas OLS MIN. ToS fet 0.100 045. 485 TIP. OWS a4 HOzSPRELIMINARY _CY7C107A Package Diagrams (continued) 28-Lead (400-Mil) Molded SOJ V28 DIMEM2IOM2 IN INCHES MIM. DETAIL A May. FIN 1 LD EXTEPHAL LEAD DETIGH NHANOHOOAAAOAOD UDUUUYUUCUYUUY Ut OPTION et MIM, Cypress Semiconductor Corporation, 1992. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied ina Cypress Semiconductor Corporation product. Nor does it convey or imply any license under patent or otherrights. Cypress Semicon- ductor does not authorize its products for use as critical components in lifa support systems where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life support systems applications implies that the manufacturer assumes all risk of such use and in so doing indemnifies Cypress Semiconductor against all damages.