FAN3213 / FAN3214 Dual-4 A, High-Speed, Low-Side Gate Drivers Features Description Industry-Standard Pin Out 4.5 to 18 V Operating Range 5 A Peak Sink/Source at VDD = 12 V 4.3 A Sink / 2.8 A Source at VOUT = 6 V TTL Input Thresholds Two Versions of Dual Independent Drivers: - Dual Inverting (FAN3213) Dual Non-Inverting (FAN3214) Internal Resistors Turn Driver Off If No Inputs Typical Propagation Delay Under 20 ns Matched within 1 ns to the Other Channel Double Current Capability by Paralleling Channels MillerDriveTM Technology 12 ns / 9 ns Typical Rise/Fall Times with 2.2 nF Load Standard SOIC-8 Package Rated from -40C to +125C Ambient Automotive Qualified to AEC-Q100 (F085 Version) Applications The FAN3213 and FAN3214 dual 4 A gate drivers are designed to drive N-channel enhancement-mode MOSFETs in low-side switching applications by providing high peak current pulses during the short switching intervals. They are both available with TTL input thresholds. Internal circuitry provides an undervoltage lockout function by holding the output LOW until the supply voltage is within the operating range. In addition, the drivers feature matched internal propagation delays between A and B channels for applications requiring dual gate drives with critical timing, such as synchronous rectifiers. This also enables connecting two drivers in parallel to effectively double the current capability driving a single MOSFET. The FAN3213/14 drivers incorporate MillerDriveTM architecture for the final output stage. This bipolarMOSFET combination provides high current during the Miller plateau stage of the MOSFET turn-on / turn-off process to minimize switching loss, while providing railto-rail voltage swing and reverse current capability. The FAN3213 offers two inverting drivers and the FAN3214 offers two non-inverting drivers. Both are offered in a standard 8-pin SOIC package. Related Resources Switch-Mode Power Supplies AN-6069 -- Application Review and Comparative Evaluation of Low-Side Gate Drivers High-Efficiency MOSFET Switching Synchronous Rectifier Circuits DC-to-DC Converters Motor Control Automotive-Qualified Systems (F085 version) NC 1 INA 2 A GND 3 INB 4 B 8 NC NC 1 7 OUTA INA 2 6 VDD GND 3 5 OUTB INB 4 FAN3213 8 NC A 7 OUTA 6 VDD B 5 OUTB FAN3214 Figure 1. Pin Configurations (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers September 2015 Part Number Logic FAN3213TMX Dual Inverting Channels FAN3214TMX Dual Non-Inverting Channels FAN3213TMX_F085(1) Dual Inverting Channels FAN3214TMX_F085(1) Dual Non-Inverting Channels Input Threshold Package Packing Method Quantity per Reel TTL SOIC-8 Tape & Reel 2,500 Note: 1. Qualified to AEC-Q100 Package Outlines 1 8 2 7 3 6 4 5 Figure 2. SOIC-8 (Top View) Thermal Characteristics(2) Package 8-Pin Small Outline Integrated Circuit (SOIC) JL(3) JT(4) JA(5) JB(6) JT(7) Unit 38 29 87 41 2.3 C/W Notes: 2. Estimates derived from thermal simulation; actual values depend on the application. 3. Theta_JL (JL): Thermal resistance between the semiconductor junction and the bottom surface of all the leads (including any thermal pad) that are typically soldered to a PCB. 4. Theta_JT (JT): Thermal resistance between the semiconductor junction and the top surface of the package, assuming it is held at a uniform temperature by a top-side heatsink. 5. Theta_JA (JA): Thermal resistance between junction and ambient, dependent on the PCB design, heat sinking, and airflow. The value given is for natural convection with no heatsink, using a 2S2P board, as specified in JEDEC standards JESD51-2, JESD51-5, and JESD51-7, as appropriate. 6. Psi_JB (JB): Thermal characterization parameter providing correlation between semiconductor junction temperature and an application circuit board reference point for the thermal environment defined in Note 5. For the SOIC-8 package, the board reference is defined as the PCB copper adjacent to pin 6. 7. Psi_JT (JT): Thermal characterization parameter providing correlation between the semiconductor junction temperature and the center of the top of the package for the thermal environment defined in Note 5. (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 2 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Ordering Information NC 1 INA 2 GND 3 INB 4 A B 8 NC NC 1 7 OUTA INA 2 6 VDD GND 3 5 OUTB INB 4 FAN3213 A B 8 NC 7 OUTA 6 VDD 5 OUTB FAN3214 Figure 3. Pin Configurations (Repeated) Pin Definitions Pin Name Pin Description 1 NC No Connect. This pin can be grounded or left floating. 2 INA Input to Channel A. 3 GND Ground. Common ground reference for input and output circuits. 4 INB Input to Channel B. 5 (FAN3213) OUTB Gate Drive Output B (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold. 5 (FAN3214) OUTB Gate Drive Output B: Held LOW unless required input(s) are present and VDD is above UVLO threshold. 6 VDD 7 (FAN3213) OUTA Gate Drive Output A (inverted from the input): Held LOW unless required input is present and VDD is above UVLO threshold. 7 (FAN3214) OUTA Gate Drive Output A: Held LOW unless required input(s) are present and VDD is above UVLO threshold. 8 NC Supply Voltage. Provides power to the IC. No Connect. This pin can be grounded or left floating. Output Logic FAN3213 (x=A or B) FAN3214 (x=A or B) INx OUTx INx OUTx 0 1 0(9) 0 (9) 0 1 1 1 Note: 9. Default input signal if no external connection is made. (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 3 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Pin Configurations NC 1 8 NC INA 2 7 OUTA 100k 100k UVLO GND 3 6 VDD VDD_OK INB 4 5 OUTB 100k 100k Figure 4. FAN3213 Block Diagram NC 1 8 NC INA 2 7 OUTA 100k 100k UVLO GND 3 6 VDD VDD_OK INB 4 5 OUTB 100k 100k Figure 5. FAN3214 Block Diagram (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 4 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Block Diagrams Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol Parameter Min. Max. Unit -0.3 20.0 V VDD VDD to PGND VIN INA and INB to GND GND - 0.3 VDD + 0.3 V OUTA and OUTB to GND GND - 0.3 VDD + 0.3 V VOUT TL Lead Soldering Temperature (10 Seconds) TJ Junction Temperature TSTG Storage Temperature +260 C -55 +150 C -65 +150 C Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol Parameter VDD Supply Voltage Range VIN Input Voltage INA and INB TA Operating Ambient Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 Min. Max. Unit 4.5 18.0 V 0 VDD V -40 +125 C www.fairchildsemi.com 5 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Absolute Maximum Ratings Unless otherwise noted, VDD=12 V, TJ=-40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit 18.0 V 0.70 0.95 mA Supply FAN321xT VDD Operating Range 4.5 IDD Supply Current, Inputs Not Connected VON Turn-On Voltage INA=VDD, INB=0 V 3.5 3.9 4.3 V VOFF Turn-Off Voltage INA=VDD, INB=0 V 3.3 3.7 4.1 V 0.70 1.20 mA FAN321xTMX_F085 (Automotive-Qualified Versions) IDD VON VOFF Supply Current, Inputs Not Connected(12) (12) INA=VDD, INB=0 V 3.3 3.9 4.5 V (12) INA=VDD, INB=0 V 3.1 3.7 4.3 V 0.8 1.2 Turn-On Voltage Turn-Off Voltage Inputs VIL_T INx Logic Low Threshold VIH_T INx Logic High Threshold 1.6 V 2.0 V FAN321xT IIN+ Non-Inverting Input IN from 0 to VDD -1.5 175.0 A IIN- Inverting Input IN from 0 to VDD -175.0 1.5 A 0.8 V 1.5 A VHYS_T TTL Logic Hysteresis Voltage 0.2 0.4 FAN321xTMX_F085 (Automotive-Qualified Versions) IINx_T Non-inverting Input Current(12) IN=0 V -1.5 IINx_T (12) IN=VDD 90 120 175 A IINx_T Inverting Input Current (12) IN=0 V -175 -120 -90 A IINx_T Inverting Input Current(12) IN=VDD -1.5 1.5 A 0.8 V VHYS_T Non-inverting Input Current TTL Logic Hysteresis Voltage (12) 0.1 0.4 Output OUT Current, Mid-Voltage, Sinking(10) OUTx at VDD/2, CLOAD=0.22 F, f=1 kHz 4.3 A ISOURCE OUT Current, Mid-Voltage, Sourcing(10) OUTx at VDD/2, CLOAD=0.22 F, f=1 kHz -2.8 A IPK_SINK OUT Current, Peak, Sinking(10) CLOAD=0.22 F, f=1 kHz 5 A CLOAD=0.22 F, f=1 kHz -5 A 500 mA ISINK IPK_SOURCE OUT Current, Peak, Sourcing IRVS (10) (10) Output Reverse Current Withstand TDEL.MATCH Propagation Matching Between Channels INA=INB, OUTA and OUTB at 50% Point 2 4 ns Continued on the following page... (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 6 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Electrical Characteristics Unless otherwise noted, VDD=12 V, TJ=-40C to +125C. Currents are defined as positive into the device and negative out of the device. Symbol Parameter Conditions Min. Typ. Max. Unit CLOAD=2200 pF 12 20 ns CLOAD=2200 pF 9 17 ns 17 29 ns CLOAD=2200 pF 12 22 ns CLOAD=2200 pF 9 18 ns 17 32 ns VOH=VDD-VOUT, IOUT=-1 mA 15 35 mV IOUT=1 mA 10 25 mV FAN321xT tRISE tFALL tD1, tD2 Output Rise Time(11) (11) Output Fall Time Output Propagation Delay, TTL Inputs (11) 0 - 5 VIN, 1 V/ns Slew Rate 9 FAN321xTMX_F085 (Automotive-Qualified Versions) tRISE tFALL tD1, tD2 VOH VOL Output Rise Time(11)(12) (11)(12) Output Fall Time Output Propagation Delay, TTL Inputs (11)(12) High Level Output Voltage(12) Low Level Output Voltage (12) 0 - 5 VIN, 1 V/ns Slew Rate 9 Notes: 10. Not tested in production. 11. See Timing Diagrams of Figure 6 and Figure 7. 12. Apply only to Automotive Version(FAN321xTMX_F085) 90% 90% Output Output 10% Input 10% VINH Input VINL tD1 tD2 tRISE VINL tD1 tFALL tD2 tRISE tFALL Figure 6. Non-Inverting Timing Diagram (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 VINH Figure 7. Inverting Timing Diagram www.fairchildsemi.com 7 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Electrical Characteristics (Continued) Typical characteristics are provided at TA=25C and VDD=12 V unless otherwise noted. Figure 8. IDD (Static) vs. Supply Voltage(12) Figure 9. IDD (Static) vs. Temperature(12) Figure 10. IDD (No Load) vs. Frequency Figure 11. IDD (2.2 nF Load) vs. Frequency Figure 12. Input Thresholds vs. Supply Voltage Figure 13. Input Thresholds vs. Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 8 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25C and VDD=12 V unless otherwise noted. UVLO Threshold vs. Temperature Figure 14. Propagation Delay vs. Supply Voltage Figure 15. Propagation Delay vs. Supply Voltage Figure 16. Propagation Delays vs. Temperature Figure 17. Propagation Delays vs. Temperature (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 9 Typical characteristics are provided at TA=25C and VDD=12 V unless otherwise noted. Figure 18. Fall Time vs. Supply Voltage Figure 19. Rise Time vs. Supply Voltage Figure 20. Rise and Fall Times vs. Temperature Figure 21. Rise/Fall Waveforms with 2.2 nF Load (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 Figure 22. Rise/Fall Waveforms with 10 nF Load www.fairchildsemi.com 10 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics Typical characteristics are provided at TA=25C and VDD=12 V unless otherwise noted. Figure 23. Quasi-Static Source Current with VDD=12 V(13) Figure 24. Quasi-Static Sink Current with VDD=12 V Figure 25. Quasi-Static Source Current with VDD=8 V(14) Figure 26. Quasi-Static Sink Current with VDD=8 V(14) (13) Notes: 13. For any inverting inputs pulled low, non-inverting inputs pulled high, or outputs driven high; static IDD increases by the current flowing through the corresponding pull-up/down resistor shown in Figure 4 and Figure 5. 14. The initial spike in each current waveform is a measurement artifact caused by the stray inductance of the current-measurement loop. Test Circuit VDD 470F Al. El. 4.7F ceramic Current Probe LECROY AP015 IN 1kHz IOUT 1F ceramic VOUT CLOAD 0.22F Figure 27. Quasi-Static IOUT / VOUT Test Circuit (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 11 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Performance Characteristics VDD Input Thresholds The FAN3213 and the FAN3214 drivers consist of two identical channels that may be used independently at rated current or connected in parallel to double the individual current capacity. Input stage The input thresholds meet industry-standard TTL-logic thresholds independent of the VDD voltage, and there is a hysteresis voltage of approximately 0.4 V. These levels permit the inputs to be driven from a range of input logic signal levels for which a voltage over 2 V is considered logic HIGH. The driving signal for the TTL inputs should have fast rising and falling edges with a slew rate of 6 V/s or faster, so a rise time from 0 to 3.3 V should be 550 ns or less. With reduced slew rate, circuit noise could cause the driver input voltage to exceed the hysteresis voltage and retrigger the driver input, causing erratic operation. VOUT Figure 28. MillerDriveTM Output Architecture Under-Voltage Lockout The FAN321x startup logic is optimized to drive groundreferenced N-channel MOSFETs with an under-voltage lockout (UVLO) function to ensure that the IC starts up in an orderly fashion. When VDD is rising, yet below the 3.9 V operational level, this circuit holds the output LOW, regardless of the status of the input pins. After the part is active, the supply voltage must drop 0.2 V before the part shuts down. This hysteresis helps prevent chatter when low VDD supply voltages have noise from the power switching. This configuration is not suitable for driving high-side P-channel MOSFETs because the low output voltage of the driver would turn the P-channel MOSFET on with VDD below 3.9 V. Static Supply Current In the IDD (static) typical performance characteristics shown in Figure 8 and Figure 9, each curve is produced with both inputs floating and both outputs LOW to indicate the lowest static IDD current. For other states, additional current flows through the 100 k resistors on the inputs and outputs shown in the block diagram of each part (see Figure 4 and Figure 5). In these cases, the actual static IDD current is the value obtained from the curves plus this additional current. MillerDriveTM Gate Drive Technology FAN3213 and FAN3214 gate drivers incorporate the MillerDriveTM architecture shown in Figure 28. For the output stage, a combination of bipolar and MOS devices provide large currents over a wide range of supply voltage and temperature variations. The bipolar devices carry the bulk of the current as OUT swings between 1/3 to 2/3 VDD and the MOS devices pull the output to the HIGH or LOW rail. VDD Bypass Capacitor Guidelines The purpose of the MillerDriveTM architecture is to speed up switching by providing high current during the Miller plateau region when the gate-drain capacitance of the MOSFET is being charged or discharged as part of the turn-on / turn-off process. A typical criterion for choosing the value of CBYP is to keep the ripple voltage on the VDD supply to 5%. This is often achieved with a value 20 times the equivalent load capacitance CEQV, defined here as QGATE/VDD. Ceramic capacitors of 0.1 F to 1 F or larger are common choices, as are dielectrics, such as X5R and X7R, with good temperature characteristics and high pulse current capability. To enable this IC to turn a device ON quickly, a local high-frequency bypass capacitor, CBYP, with low ESR and ESL should be connected between the VDD and GND pins with minimal trace length. This capacitor is in addition to bulk electrolytic capacitance of 10 F to 47 F commonly found on driver and controller bias circuits. For applications with zero voltage switching during the MOSFET turn-on or turn-off interval, the driver supplies high peak current for fast switching even though the Miller plateau is not present. This situation often occurs in synchronous rectifier applications because the body diode is generally conducting before the MOSFET is switched ON. If circuit noise affects normal operation, the value of CBYP may be increased, to 50-100 times the CEQV, or CBYP may be split into two capacitors. One should be a larger value, based on equivalent load capacitance, and the other a smaller value, such as 1-10 nF mounted closest to the VDD and GND pins to carry the higherfrequency components of the current pulses. The bypass capacitor must provide the pulsed current from both of the driver channels and, if the drivers are switching simultaneously, the combined peak current sourced from the CBYP would be twice as large as when a single channel is switching. The output pin slew rate is determined by VDD voltage and the load on the output. It is not user adjustable, but a series resistor can be added if a slower rise or fall time at the MOSFET gate is needed. (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 12 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Applications Information The FAN3213 and FAN3214 gate drivers incorporate fast-reacting input circuits, short propagation delays, and powerful output stages capable of delivering current peaks over 4 A to facilitate voltage transition times from under 10 ns to over 150 ns. The following layout and connection guidelines are strongly recommended: Figure 30 shows the current path when the gate driver turns the MOSFET OFF. Ideally, the driver shunts the current directly to the source of the MOSFET in a small circuit loop. For fast turn-off times, the resistance and inductance in this path should be minimized. VDD Keep high-current output and power ground paths separate from logic input signals and signal ground paths. This is especially critical for TTL-level logic thresholds at driver input pins. CBYP FAN321x Keep the driver as close to the load as possible to minimize the length of high-current traces. This reduces the series inductance to improve highspeed switching, while reducing the loop area that can radiate EMI to the driver inputs and surrounding circuitry. PWM If the inputs to a channel are not externally connected, the internal 100 k resistors indicated on block diagrams command a low output. In noisy environments, it may be necessary to tie inputs of an unused channel to VDD or GND using short traces to prevent noise from causing spurious output switching. Many high-speed power circuits can be susceptible to noise injected from their own output or other external sources, possibly causing output retriggering. These effects can be obvious if the circuit is tested in breadboard or non-optimal circuit layouts with long input or output leads. For best results, make connections to all pins as short and direct as possible. FAN3213 and FAN3214 are pin-compatible with many other industry-standard drivers. The turn-on and turn-off current paths should be minimized, as discussed in the following section. VDS Figure 30. Current Path for MOSFET Turn-Off Figure 29 shows the pulsed gate drive current path when the gate driver is supplying gate charge to turn the MOSFET on. The current is supplied from the local bypass capacitor, CBYP, and flows through the driver to the MOSFET gate and to ground. To reach the high peak currents possible, the resistance and inductance in the path should be minimized. The localized CBYP acts to contain the high peak current pulses within this driverMOSFET circuit, preventing them from disturbing the sensitive analog circuitry in the PWM controller. VDD VDS CBYP FAN321x PWM Figure 29. Current Path for MOSFET Turn-On (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 13 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Layout and Connection Guidelines At power-up, the driver output remains LOW until the VDD voltage reaches the turn-on threshold. The magnitude of the OUT pulses rises with VDD until steady-state VDD is reached. The non-inverting operation illustrated in Figure 31 shows that the output remains LOW until the UVLO threshold is reached, then the output is in-phase with the input. The inverting configuration of startup waveforms are shown in Figure 32. With IN+ tied to VDD and the input signal applied to IN-, the OUT pulses are inverted with respect to the input. At power-up, the inverted output remains LOW until the VDD voltage reaches the turn-on threshold, then it follows the input with inverted phase. VDD VDD Turn-on threshold Turn-on threshold IN- IN- IN+ IN+ (VDD) OUT OUT Figure 31. Non-Inverting Startup Waveforms (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 Figure 32. Inverting Startup Waveforms www.fairchildsemi.com 14 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Operational Waveforms Gate drivers used to switch MOSFETs and IGBTs at high frequencies can dissipate significant amounts of power. It is important to determine the driver power dissipation and the resulting junction temperature in the application to ensure that the part is operating within acceptable temperature limits. To give a numerical example, assume for a 12 V VDD (Vibas) system, the synchronous rectifier switches of Figure 33 have a total gate charge of 60 nC at VGS = 7 V. Therefore, two devices in parallel would have 120 nC gate charge. At a switching frequency of 300 kHz, the total power dissipation is: The total power dissipation in a gate driver is the sum of two components, PGATE and PDYNAMIC: PTOTAL = PGATE + PDYNAMIC (1) PGATE (Gate Driving Loss): The most significant power loss results from supplying gate current (charge per unit time) to switch the load MOSFET on and off at the switching frequency. The power dissipation that results from driving a MOSFET at a specified gatesource voltage, VGS, with gate charge, QG, at switching frequency, fSW, is determined by: PGATE = QG * VGS * fSW * n (5) PDYNAMIC = 3.0 mA * 12 V * 1 = 0.036 W (6) PTOTAL = 0.540 W (7) The SOIC-8 has a junction-to-board thermal characterization parameter of JB = 42C/W. In a system application, the localized temperature around the device is a function of the layout and construction of the PCB along with airflow across the surfaces. To ensure reliable operation, the maximum junction temperature of the device must be prevented from exceeding the maximum rating of 150C; with 80% derating, TJ would be limited to 120C. Rearranging Equation 4 determines the board temperature required to maintain the junction temperature below 120C: (2) where n is the number of driver channels in use (1 or 2). PDYNAMIC (Dynamic Pre-Drive / Shoot-through Current): A power loss resulting from internal current consumption under dynamic operating conditions, including pin pull-up / pull-down resistors. The internal current consumption (IDYNAMIC) can be estimated using the graphs in Figure 10 of the Typical Performance Characteristics to determine the current IDYNAMIC drawn from VDD under actual operating conditions: PDYNAMIC = IDYNAMIC * VDD * n PGATE = 120 nC * 7 V * 300 kHz * 2 = 0.504 W TB,MAX = TJ - PTOTAL * JB (8) TB,MAX = 120C - 0.54 W * 42C/W = 97C (9) (3) where n is the number of driver ICs in use. Note that n is usually be one IC even if the IC has two channels, unless two or more.driver ICs are in parallel to drive a large load. Once the power dissipated in the driver is determined, the driver junction rise with respect to circuit board can be evaluated using the following thermal equation, assuming JB was determined for a similar thermal design (heat sinking and air flow): TJ = PTOTAL * JB + TB (4) where: TJ = driver junction temperature; JB = (psi) thermal characterization parameter relating temperature rise to total power dissipation; and TB = board temperature in location as defined in the Thermal Characteristics table. (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 15 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Thermal Guidelines VIN VOUT PWM Timing/ Isolation 1 8 2 7 3 6 4 5 FAN3214 Vbias A 2 3 GND FAN3214 4 Figure 33. High-Current Forward Converter with Synchronous Rectification VIN 8 1 Figure 34. QC QA QD QB 7 VDD 6 B 5 Center-Tapped Bridge Output with Synchronous Rectifiers FAN3214 PWM-A FAN3225C SR-1 PWM-B Secondary Phase Shift Controller SR-2 PWM-C FAN3225C PWM-D Figure 35. Secondary Controlled Full Bridge with Current Doubler Output, Synchronous Rectifiers (Simplified) (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 16 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Typical Application Diagrams Type Related Products Part Number Gate Drive(15) Input (Sink/Src) Threshold Single 1 A FAN3111C +1.1 A / -0.9 A CMOS Single 1 A FAN3111E +1.1 A / -0.9 A External Single 2 A FAN3100C +2.5 A / -1.8 A Single 2 A FAN3100T +2.5 A / -1.8 A Single 2 A FAN3180 +2.4 A / -1.6 A Logic Package Single Channel of Dual-Input/Single-Output SOT23-5, MLP6 Single Non-Inverting Channel with External Reference SOT23-5, MLP6 CMOS Single Channel of Two-Input/One-Output SOT23-5, MLP6 TTL Single Channel of Two-Input/One-Output SOT23-5, MLP6 TTL Single Non-Inverting Channel + 3.3 V LDO SOT23-5 (16) Dual 2 A FAN3216T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 Dual 2 A FAN3217T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 Dual 2 A FAN3226C +2.4 A / -1.6 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3226T +2.4 A / -1.6 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3227C +2.4 A / -1.6 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3227T +2.4 A / -1.6 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 2 A FAN3228C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 Dual 2 A FAN3228T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.1 SOIC8, MLP8 Dual 2 A FAN3229C +2.4 A / -1.6 A CMOS Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 Dual 2 A FAN3229T +2.4 A / -1.6 A TTL Dual Channels of Two-Input/One-Output, Pin Config.2 SOIC8, MLP8 Dual 2 A FAN3268T +2.4 A / -1.6 A TTL 20 V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 Dual 2 A FAN3278T +2.4 A / -1.6 A TTL 30 V Non-Inverting Channel (NMOS) and Inverting Channel (PMOS) + Dual Enables SOIC8 Dual 4 A FAN3213T +2.5 A / -1.8 A TTL Dual Inverting Channels SOIC8 Dual 4 A FAN3214T +2.5 A / -1.8 A TTL Dual Non-Inverting Channels SOIC8 Dual 4 A FAN3223C +4.3 A / -2.8 A CMOS Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3223T +4.3 A / -2.8 A TTL Dual Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224C +4.3 A / -2.8 A CMOS Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3224T +4.3 A / -2.8 A TTL Dual Non-Inverting Channels + Dual Enable SOIC8, MLP8 Dual 4 A FAN3225C +4.3 A / -2.8 A CMOS Dual Channels of Two-Input/One-Output SOIC8, MLP8 Dual 4 A FAN3225T +4.3 A / -2.8 A TTL Dual Channels of Two-Input/One-Output SOIC8, MLP8 Single 9 A FAN3121C +9.7 A / -7.1 A CMOS Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3121T +9.7 A / -7.1 A TTL Single Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122C +9.7 A / -7.1 A CMOS Single Non-Inverting Channel + Enable SOIC8, MLP8 Single 9 A FAN3122T +9.7 A / -7.1 A TTL Single Non-Inverting Channel + Enable SOIC8, MLP8 Dual 12 A FAN3240 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 0 SOIC8 Dual 12 A FAN3241 +12.0 A TTL Dual-Coil Relay Driver, Timing Config. 1 SOIC8 Notes: 15. Typical currents with OUTx at 6 V and VDD=12 V. 16. Thresholds proportional to an externally supplied reference voltage. (c) 2008 Fairchild Semiconductor Corporation FAN3213 / FAN3214 * Rev. 1.9 www.fairchildsemi.com 17 FAN3213 / FAN3214 -- Dual-4A, High-Speed, Low-Side Gate Drivers Table 1. TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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