DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final 1
Version: DM9102A-DS-F03
August 28, 2000
Gener al Descri ption
The DM9102A is a fully integrated and cost-effective single
chip Fast Ethernet NIC controller. It is designed with the lo w
power and high performance process. It is a 3.3V device
with 5V tolerance then i t s upports 3. 3 V and 5V signaling.
The DM9102A provides direct interface to the PCI or the
CardBus. It supports bus master capability and fully
complies with PCI 2.2. In media side, The DM9102A
interfaces to the UTP3,4,5 in 10Base-T and UTP5 in
100Base-TX. It is fully compliance with the IEEE 802.3u
Spec. Its auto-negotiation function will automatically
configure the DM9102A to take the maximum ad vantage o f
its ab ilities. The DM9102A is also support IEEE 802.3x full-
duplex flow control.
The DM9102A supports two types o f power-management
mechanisms. The main mechanism is based upon the
OnNow architecture, w hich is required for PC99 . The
alternative mechanism is based upon th e remote Wake-On-
LAN mechanism.
Block D iagr am
DMA
EEPROM
Interface Boot ROM /
MII Interface
PCI
Interface
TX+/-
RX+/-
MII Management Control
& MII Register
Autonegotiation
LED Driver
Power
Management
Block
PME#
WOL
RX
Machine RX
FIFO
TX
FIFO
TX
Machine
MAC
MII
NRZ to NRZINRZI to MLT3 Parallel to
Serial Scrambler 4B/5B
Encoding
MLT3 to NRZI NRZI to NRZ Parallel to
Serial De-
Scrambler 4B/5B
Decoding
AEQ
PHYceiver
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
2Final
Version: DM9102A-DS-F03
August 28, 2000
Table of Con ten ts
General Description .............................................................1
Bloc k D iagr am......................................................................1
Features...............................................................................4
Pin Con figuration: DM9102A 128pin QFP..........................5
Pin Con figuration: DM9102A 128pin TQFP.......................6
Pin De sc ript ion.....................................................................7
- PCI Bus and CardBus Inter face S ignals.........................7
- Boot ROM and E EPROM Interface................................8
T
Mul tiple x Mo de ................................................................8
T
Dire ct M ode....................................................................10
- L ED P ins.........................................................................11
- N etw ork In ter face...........................................................1 2
- Miscellaneous Pins.........................................................12
- Po w er Pins.....................................................................13
- N ote: L E D M ode............................................................13
Re giste r De fin ition..............................................................14
✧ PC I C on figu rat ion Re gis ters..........................................14
Key to D efau lt.....................................................................14
T
Identification ID...............................................................15
T
Command & Status........................................................15
T
Re vis ion ID.....................................................................17
T
Miscellaneous Function .................................................18
T
I/O B as e Add res s...........................................................18
T
Memory Mapped Base Address....................................19
T
Subsystem Identification................................................19
T
Ca rdBu s CIS P oi nter......................................................20
T
Expansion ROM Base Address.....................................21
T
Capabilities Pointer.........................................................21
T
Interrupt & Latency Configuration..................................22
T
De vice Spe c ific Configuration Register.........................22
T
Power Manageme nt Re gister........................................23
T
Power Manageme nt Control/Status..............................24
✧ Co ntro l an d Sta tus R egis ter (C R)..................................2 5
Key to D efau lt.....................................................................25
1. System Cont rol Re gist er (CR0).....................................26
2. Tra ns mi t Des cr ipto r Po ll D ema n d (CR 1)......................2 7
3. Receive Des criptor Po ll Demand (CR2).......................27
4. R ece i ve De s cripto r B as e Add res s (CR 3).....................27
5. Tra ns mi t Des cr ipto r Bas e Add res s (C R4)....................28
6. Network Status Repor t Register (CR 5).........................28
7. N etw or k Ope rat ion R egis ter (C R6 )............................... 30
8. In terru p t Mas k Register (C R7)...................................... 32
9. Statistical Counter Reg ister (CR8)................................ 33
10. PROM & Manage ment Acces s Register (CR9) ........ 34
11 . Prog ra mmi ng R OM Add res s Re gis ter (CR 10).......... 35
12. General Purpose Timer Re gister (CR 11)................... 35
13 . PHY S tatu s R eg is ter (CR 12)...................................... 35
14 . Sa mple Fra m e A cc es s Reg iste r (CR 13).................... 36
15 . Sa mple Fra m e D a ta Reg is ter (C R14)........................ 36
16. Watching & Jabber Timer Register (CR15)................ 36
✧ CardBus Status Changed Register .............................. 39
1. Function Event Re gister: (o ffset 80h)............................ 39
2. Function Event Mask Register: (offset 84h).................. 39
3. Fun ctio n P res en t S tate Re gis ter : (o ffse t 8 8h )............... 39
4. Fun ctio n Fo rce E ven t Re g iste r: (o ffse t 8 Ch)................ 40
✧ PHY Manage ment Register Set................................... 41
Key To De fau lt................................................................... 41
Basic Mode Control Register (BMCR)
- Re gis ter 0......................................................................... 42
Basic Mode Status Register (BMSR)
- Re gis ter 1......................................................................... 43
PHY ID Identifier Register #1 ( PHYIDR1)
- Re gis ter 2......................................................................... 44
PHY ID Identifier Register #2 ( PHYIDR2)
- Re gis ter 3......................................................................... 44
Auto-negotiation Advertisement Register (ANAR)
- Re gis ter 4......................................................................... 44
Auto-negotiation Link Par tner Ability Register (ANLPAR) -
Re giste r 5........................................................................... 45
Auto-negotiation Expansion Register (ANER)
- Re gis ter 6......................................................................... 46
DAVICOM Spec ified Configuration Reg ister (DSCR)
- Re gis ter 10....................................................................... 46
DAV IC OM S pec i fied Co n figura tio n a n d Statu s Regist e r
(DS CSR) - Re g is ter 11...................................................... 47
10Base-T Configuration/Status (10BTSCRCSR)
- Re gis ter 12....................................................................... 48
Fun ct ional De s cr ipt ion....................................................... 49
✧ System Buffer Management ......................................... 49
1. O ver view........................................................................ 49
2. Data S tructure and Desc riptor List ................................ 49
3. Buffer Manage ment: Chain Structure Method.............. 49
5. D es crip tor L ist: Bu ffer De s crip tor Fo r mat...................... 49
(a) . Re ce i ve D es crip tor For ma t.........................................4 9
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final 3
Version: DM9102A-DS-F03
August 28, 2000
(b) . Tran s mit D es cripto r For mat .........................................51
✧ Initialization Procedure...................................................54
Da ta Bu ffer Proces sing Algo rith m.....................................54
1. R ece i ve Da ta Bu ffer Proce s sin g...................................54
2. Tra ns mi t Da ta Bu ffer Pr oce ss ing..................................55
✧ Ne tw ork Fun ct ion...........................................................56
1. O ver view.........................................................................56
2. Receive Process and State Machine............................56
a. Reception Initiation....................................................... 56
b. Address Recognition....................................................56
c. Frame Decapsulation ................................................... 56
3. Transmit Process and State Mach ine...........................56
a. Transmit Initiation.......................................................... 56
b . Fra me En cap s ula tion...................................................56
c. Collision.........................................................................56
4. Ph ys ica l Lay er O ver view...............................................56
✧ Serial Management Interface........................................57
✧ Power Management ......................................................58
1. O ver view.........................................................................58
2. PCI Function Power Management Status ....................58
3. The Power Management Operation .............................58
a. Detect Network L ink State Change.............................58
b . Acti ve M ag ic Pack e t Func tion ......................................58
c. Acti ve the Sa mple Frame Fu nction.............................58
✧ Sa mp le Fr a me Pro gra m ming Gu ide .............................60
Ser ial RO M O ver vie w........................................................61
1. Su bs ys te m ID B loc k.......................................................61
2. SR OM Ve rs ion...............................................................62
3. Controller Count.............................................................62
4. C ontr o ller_ X In for mat ion................................................62
5. Controller Information Body Po inted By Controller_X Info
Bloc k Offs et Item in C on trolle r Info rm atio n Header.......62
6. Examp le o f DM9102A SR OM Format.......................... 63
External MII/SRL Interface ................................................ 66
The Shar ing P in Tab le....................................................... 66
Abs olute Maximu m Ratings.............................................. 68
Ope ratin g Con dit ion s......................................................... 68
DC Electrical Characteristics............................................. 69
AC E lec tr ica l Ch ara cte r isti cs & T imin g Wa ve for ms..........70
T
PCI C lo ck Spe c . Ti ming.................................................7 0
T
Othe r P C I Sig na ls Ti ming Dia gra m............................... 70
T
Mul tiple x Mo de Boo t ROM T imin g................................71
T
Direct Mode Boot R OM Timing..................................... 72
T
EEPR OM Ti ming........................................................... 72
T
TP Inte rfa ce.................................................................... 73
T
Oscillator/Crys tal Timing................................................ 73
T
Auto-negotiation an d Fast Link Pulse Timing Parameters
........................................................................................ 73
Package Information (128 pin, QFP)................................ 75
Package Information (128 pin, TQFP).............................. 76
Orde ring Infor ma tion.......................................................... 77
Disclaimer .......................................................................... 77
Company O verview........................................................... 77
Products............................................................................. 77
Contact Windows............................................................... 77
Warning.............................................................................. 77
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
4Final
Version: DM9102A-DS-F03
August 28, 2000
Features
T
Integrated Fast Ethernet MAC, Physical Layer and
transceiver in one chip.
T
128pin QFP/128pin TQFP with CMOS process.
T
+3.3V Power supply with +5V tolerant I/O.
T
Supports PCI and CardBus interfaces.
T
Comply with PCI specification 2.2.
T
PCI clock up to 40MHz.
T
PCI bus master architecture.
T
PCI bus burst mode data trans fer.
T
Two large independent FIFO; receive FIFO & transmit
FIFO.
T
Up to 256K bytes Boot EPROM or Flash interface.
T
EEPROM 93C46 interface supports node ID accesses
configuration information and user define message.
T
Node address auto-load and reload.
T
Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
T
Comply with IEEE 802.3u auto-negotiation protocol for
automatic link type selection.
T
Full Duplex/Half Duplex capability.
T
Support IEEE 802.3x Full Duplex Flow Control
T
VLAN support.
T
Comply w ith ACPI and PCI Bus Power Management.
T
Supports the MII (Media Independent Interface ).
T
Supports Wake-On-LAN function and remote wake-up
(Magic packet, L ink Change and Microsoft® wake-up
frame).
T
Supports 4 Wake-On-LAN (WOL) s ignals (a ctive high
pulse, active low pulse, active h igh , active low ) .
T
High performance 100Mbps clock generator and data
recovery circuit.
T
Digita l clo c k r ec o ve ry c irc u i t us in g advanc e d digital
algorithm to reduce jitter.
T
Adaptive equalization circuit and Baseline wandering
restoration circuit for 100Mbps receiver.
T
Provides Loopback mode for easy system diagnostics.
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final 5
Version: DM9102A-DS-F03
August 28, 2000
Pin Configuration : 128 pin QFP
11
DM9102A
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
60
59
58
57
56
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
90
91
92
93
94
95
96
97
98
99
100
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
55
54
53
52
51
61
81
82
83
84
85
86
87
88
89
INT#
RST#
DVDD
GNT#
REQ#
PCICLK
AD31
AD30
AD29
AD28
AD27
AD26
AD25
AD24
CBE3#
DGND
IDSEL
AD23
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
AD22
FRAME#
STOP#
IRDY#
TRDY#
DEVSEL#
SERR#
PERR#
CBE0#
BGRESG
BGRES
DVDD
X1/OSC
X2
DGND
LINK&ACT#
FDX#
SPEED100#
SPEED10#
BPA0/WMODE2
BPA1/PCIMODE#
EEDI
EEDO
EECK
EECS
SELROM
NC
NC
NC
BPAD4
BPAD5
BPAD6
BPAD7/LEDMODE
BPCS#
BPAD1
BPAD0
BPAD2
BPAD3
AD0
AD1
AD2
AD6
AD7
AD5
AD3
TEST2
AD4
AD9
AD10
AD11
DVDD
AD13
AD14
AD15
AD12
AD8
CBE1#
PAR
(MA10/LINK&ACT#)
(MA11/FDX#)
(MA12 / SPEED100#)
(MA13/SPEED10#)
(MD0/EEDI)
(MD1)
(MD2)
(MD3)
(MD4)
(MD5)
(MD6)
(MD7/LEDMODE)
(ROMCS)
(MA0/WMODE)
(MA1/PCIMODE#)
(MA2)
(MA3/EEDO)
(MA4/EECK)
(MA5)
(MA6/SELROM)
(MA7)
(MA8)
(MA9)
DVDD
DVDD
DGND
DGND
DVDD
DVDD
DGND
DGND
27
DVDD
DVDD
DGND
DVDD
DGND
DVDD
WOL/CSTSCHG
MA16
102
101
MA15
MA14
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
127
128
126
DGND
DVDD
ISOLATE#
AVDD
RXI+
RXI-
AGND
TXO+
TXO-
AVDD
AGND
AVDD
NC
NC
WOL/CSTSCHG
NC
PME#
CLOCKRUN#
TEST1
AVDD
DGND
NC
DVDD
DGND
SUBGND
DGND
DVDD
DGND
DVDD
DGND
DGND
MA17
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
6Final
Version: DM9102A-DS-F03
August 28, 2000
Pin Configuration : 128 pin TQFP
11
DM9102A
74
73
72
71
70
69
68
67
66
65
64
63
62
60
59
58
57
56
50
49
48
47
46
45
44
43
42
41
40
39
32
31
84
85
86
87
88
89
90
91
92
93
94
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28
29
30
55
54
53
52
51
61
75
76
77
78
79
80
81
82
83
AGND
AGND
DVDD
AVDD
AVDD
TXO+
PCICLK
ISOLATE#
GNT#
REQ#
DVDD
AD31
AD30
AD24
CBE3#
DGND
IDSEL
AD23
AD21
AD20
AD19
AD18
AD17
AD16
CBE2#
AD22
FRAME#
STOP#
IRDY#
TRDY#
DEVSEL#
SERR#
PERR#
CBE0#
WOL/CSTSCHG
DVDD
SPEED10#
NC
NC
NC
SELROM
DVDD
NC
NC
BPAD5
BPAD6
TEST2
BPCS#
BPA0
BPA1/PCIMODE#
TEST1
EEDI
EEDO
EECK
BPAD4
BPAD1
BPAD0
BPAD2
AD0
AD1
AD2
AD6
AD7
AD5
AD3
BPAD3
AD4
AD9
AD10
AD11
DVDD
AD13
AD14
AD12
AD8
(MA10/LINK&ACT#)
(MA11/FDX#)
(MD0/EEDI)
(MD1)
(MD2)
(MD3)
(MD4)
(MD5)
(MD6)
(MD7/LEDMODE)
(ROMCS)
(MA0WMODE2)
(MA1/PCIMODE#)
(MA2)
(MA3/EEDO)
(MA4/EECK)
(MA5)
(MA6/SELROM)
(MA7/WMODE1)
(MA8)
(MA9)
DGND
DGND
DVDD
DVDD
DGND
27
DVDD
DVDD
DGND
DVDD
DGND
DGND
MA16
96
95
MA15
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
121
122
120
X2
DGND
SUBGND
BGRESG
AVDD
AVDD
RXI-
BGRES
RXI+
NC
LINK&ACT#
SPEED100#
DGND
INT#
BPAD7/LEDMODE
X1/OSC
DGND
FDX#
DVDD
DGND
NC
EECS
DVDD
DGND
DVDD
DVDD
MA17
128
127
126
125
124
123AD29
AD28
DGND
AD27
AD26
AD25
WOL/CSTSCHG
38
37
36
35
34
33 PAR
CBE1#
DGND
CLOCKRUN#
DGND
AD15
MA14
(MA13/SPEED10#)
(MA12/SPEED100#)
TXO-
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final 7
Version: DM9102A-DS-F03
August 28, 2000
Pin Description
I = Input, O = Output, I/O = Input / Output, O/D = Open Drain, P = Power,
LI = reset Latch Input, # = asserted L ow
PCI Bus and CardBus Interface Signals
Pin No.
128QFP/128TQFP Pin Name I/O Description
113 INT# O/D Interrupt Request
This signal will be ass erted low w hen an interrupt condition
as defined in CR5 is set, and the corresponding mask bit in
CR7 is not set.
114 RST# I System Reset
When this s ignal is as serted low, DM9102A per for ms the
internal system reset t o its initial state.
115 PCICLK I PCI system clock
PCI bus clock that pro vides timing fo r DM9102A related to
PCI bus transactions. The clock frequency range is up to
40MHz.
117 GNT# I Bus Grant
This signal is ass erted low to indicate that DM9102A has
been granted ownership of the bus by the ce n tral arb iter.
118 REQ# O Bus Request
The DM9102A will ass ert this signal low to request the
ownership of the bus.
119 PME# O/D Power Manageme nt Event.
Open drain. Active Low. The DM9102A drive it low to
indicates that a pow er management event has occurred.
3 IDSEL I Initialization Device Select
This signal is asserted high during the Configuration Space
read/write access.
21 FRAME# I/O Cycle F ra me
This signal is driven low by the D M9102A master mode to
indicate the beginning and duration of a bus transaction.
23 IRDY# I/O Initiator Ready
This signal is driven low w hen the master is ready to
complete the current data phase of the transaction. A da ta
phase is completed on any clock bo th IRDY# and TRDY#
are sampled asserted.
24 TRDY# I/O Target Ready
This signal is driven low w hen the target is ready to co mplete
the current data phase of the transaction. During a rea d, it
indicates that valid data is asserted. Du rin g a writ e, it
indicates the target is prepared to accept d ata.
26 DEVSEL# I/O De vice Se lect
The DM9102A ass erts the s ignal low w hen it recognizes its
target address a fter FRAME# is as serted. As a b us master,
the DM9102A w ill s ample this signal that insures its
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
8Final
Version: DM9102A-DS-F03
August 28, 2000
destination address of the data tran sfer i s recognized by a
target.
27 STOP# I/O Stop
This signal is asserted low by the target de vice to request the
master device to stop the current transaction.
30 PERR# I/O Parity Error
The DM9102A as a master or sla ve w ill ass ert this signal low
to indicate a pa rity error on any incoming data.
31 SER R# I/O S ys tem E rro r
This signal is ass erted low w hen address parity is detected
with PCICS bit31 (de tected parity error) Is enab led. The
system error as serts two clock cycles a fter the falling address
if an address parity error is detected.
33 PAR I/O Parity
This signal indicates e ven par ity across AD0~AD31 and
C/BE0#~C/BE3# including the PAR pin. This signal is an
output for the master and input for the slave device. It is
s t a b le and val i d o ne cl oc k a f t e r the address phase.
2
20
34
48
C/BE3#
C/BE2#
C/BE1#
C/BE0#
I/O Bus Command/Byte Enable
During the address phase, these signals define the bus
command or the type of bus transaction that will take place.
During the data phase these pins indicate which byte lanes
contain valid data. C/BE0# applies to bit7-0 and C/BE3#
applies to bit31-24.
121,122,123,124,126,127,
128,1,6,7,10,
11,13,14,16,
17,38,39,40,
41,43,44,47,
49,50,51,54,
55,56,57,59,
60
AD31~AD0 I/O Address & Data
These are multiplexed address and data bu s s ignals. As a
bus master, the DM9102A w ill drive address during the fir st
bus phas e. During s ubsequent phases, the DM9102A w ill
either read or write data expecting the target t o increment its
address pointer. As a target, the DM9102A w ill decode each
address on the bus and respond if it is the target being
addressed.
Boot R OM and EEPROM I nterface ( Including multiplex mode or direct mo de)
Mu ltiple x mo de
Pin No.
128QFP/128TQFP Pin Name I/O Description
62,63,64,65,
66,67,68,69 BPAD0~BPAD7
(BPAD7/LEDMODE) I/O, LI Boot ROM address and data bus (bits 0~7)
Boot ROM address and data m ultiplexed lines bits 0~7. In
MUX mode, there are two consecutive address cycles, these
lines contain the boot ROM address pins 7~2, out_enable and
write_enable of Boot ROM in the first cycle; and these lines
contain address pins 15~8 in second cycle.
After the first two cycles, these lines contain data bit 7~0 in
consective cycles.
BPAD1 is also a reset latch pin. It is Bo ot ROM address and
data b us when normal operation. When at power on reset, it is
used to pull up or down externally through a resister to select
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final 9
Version: DM9102A-DS-F03
August 28, 2000
the WOL as pulse or DC sign al.
0 = WOL pulse mode (default)
1 = WOL DC mode
BPAD2 is also a reset latch pin. It is Bo ot ROM address and
data b us when normal operation. When at power on reset, it is
used to pull up or down externally through a resister to select
the PME as pulse or DC signal.
0 = PME pulse mode (default)
1 = PME DC mode
BPAD7 is also a reset latch pin. It is Bo ot ROM address and
data b us when normal operation. When at power on reset, it is
used to pull up or down externally through a resister to select
LED mode.
0 = LED mode 0 (default)
1 = LED mode 1
72 BPCS# O Boot R OM Ch ip Selec t
Boot ROM or external register chip select signal.
73 BPA0/WMODE O, LI Boot ROM address line/ WOL mode selection
This multiplexed pin acts as boot ROM address bit 0 output
signal during normal operation. When at power on reset, it
used to select the type of WOL signal.
0 = WOL high active (default)
1 = WOL low active
74 BPA1/PCIMODE# I/O, LI Boot ROM addres s line / PCI mode s election
This multiplexed pin acts as the boot ROM address bit 1 output
signal during normal operation. When RST# is active (low), it
acts as the input s ystem type. If the DM9102A is used in a
CardBus system, this pin s hould be connected to a pull-up
resistor; otherwise, the DM9102A consider the host as a PCI
system.
0 = PCI mode (default)
1 = CardBus mode
77 EEDI I EEPR OM Data In
The DM9102A will read the contents of EEPROM serially
through this pin.
78 EEDO O EEPROM Da ta Out
The DM9102A w ill use this pin to s erially write opcodes,
addresses and data into the EEPROM.
79 EECK O EEPR OM Serial C lock
This p in p r ovid e s th e cl oc k f or th e EEP RO M d ata tr a nsf er.
80 EECS O EEPR OM Chip Select
This pin will enable the EEPROM during loading of the
Configuration Data.
81 SELROM I Multiplex or Director mode s election
0 = Multiplex mode (default)
1 = Direct mode
83,84,85,91,92,93,94 NC NC In Multiplex mode, these pins are not connected.
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Direct mode
Pin No.
128QFP/128TQFP Pin Name I/O Description
62 MD0/EEDI I Boot ROM data input/EEPROM data in
Th is is mu ltip le xed p in us ed by E E DI a n d MD 0.
When boot ROM is selected, it acts as boot RO M dat a in p ut .
When ROMCS select the EEPROM, the DM9102A will read
the contents of EEPROM serially through this pin.
63,64,65,66,67,68,69 MD1~MD7 I Boot ROM data input bus
MD1 is also a reset latch pi n. It is Boot ROM address and
data b us when normal operation. When at power on reset, it
is used to pull up or down externally through a resister to
select the WOL as pulse or le vel s ignal.
0 = WOL pulse mode (default)
1 = WOL le vel mode
MD2 is also a reset latch pi n. It is Boot ROM address and
data b us when normal operation. When at power on reset, it
is used to pull up or down externally through a resister to
select the P ME as pulse or level s ignal.
0 = PME pulse mode (default)
1 = PME level mode
MD7 is also a reset latch pi n. It is Boot ROM address and
data b us when normal operation. When at power on reset, it
is used to pull up or down externally through a resister to
select LED mode.
0 = LED mode 0 (default)
1 = LED mode 1
72 ROMCS O Boot R OM or EEPR OM chip selec tion.
73 MA0/WMODE O Boot ROM address output line/ WOL mode s election
This multiplexed pin acts as boot ROM address output bus
during normal operation. When RST# is active, it is used to
pull up or down externally through a resister to select WOL
High active or LOW active. (WMODE)
0 = WOL high active (default)
1 = WOL low active
74 MA1/PCIMODE# O, LI Boot ROM address output signal/PCI mode selection
This multiplexed pin acts as a boot ROM address output
signal during normal operation. When RST# is active, it acts
as the inpu t sys te m ty pe. If t he DM9102A is used in a
CardBus system, this pin s hould be connected to a pull-up
resistor; otherwise, the DM9102A consider the host as a PCI
system.
0 = PCI mode (default)
1 = CardBus mode
77 MA2 O Boot ROM address output signal
78 MA3/EEDO O Boot ROM address output/EEPROM da ta o ut
This is multiplexed pin used by MA3 and EEDO.
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When The DM9102A w ill use this pin to s erially write
opcodes, addresses and data into the EEPROM.
79 MA4/EECK O Boot ROM address output/EEPROM serial clock
This is multiplexed pin used by MA4 and EECK .
This p in p r ovid e s th e cl oc k f or th e EEP RO M d ata tr a nsf er.
80 MA5 O Boot ROM address output signal
81 MA6/SELROM O/LI Boot ROM address output/Multiplex or D irect mode s election
This multiplexed pin acts as boot ROM address output bus
during normal operation. When RST# is active, it is used as
multiplex and direct mode selection :
0 = Boot ROM interface is in multiplex mode (default)
1 = Boot RO M interface is in direct mode.
83,84,85 MA7~MA9 O Boot R OM address output bus
87 MA10/LIN K&ACT# O Boot ROM addres s output signal/Link & Ac tive LED
In D IR mode, thi s pin re pres ents the Boot ROM address bit
10 when at the time of bo ot ROM operation. When Boot
ROM is not accessed, this pin acts as traffic-and- link led in
LED MODE 0 or traffic led in LED MODE 1.
88 MA11/FDX# O Boot ROM address output/Full-duplex L ED
In D IR mode, thi s pin re pres ents the Boot ROM address bit
11 when at the time of bo ot ROM operation. When Boot
ROM is not accessed, this pin acts as full-duple x led.
89 MA12 /
SPEED100# O Boot ROM address output/ 100Mbps LED
In D IR mode, thi s pin re pres ents the Boot ROM address bit
12 when at the time of bo ot ROM operation. When Boot
ROM is not accessed, this pin acts as speed-100 led.
90 MA13/SPEED10# O Boot ROM addres s output signal/10Mbps LED
In D IR mode, thi s pin re pres ents the Boot ROM address bit
13 when at the time of bo ot ROM operation. When Boot
ROM is not accessed, this pin acts as speed-10 led.
91,92,93,
94 MA14~MA17 O Boot R OM address output bus
LED Pins (Please refer to p.11 “NOTE: LED M ode” f or details.)
Pin No.
128QFP/128TQFP Pin Name I/O Description
87 LINK&ACT#
/ AC T# O LED output pin, active low
mode 0 = Link and traffic LED. Active low to indicate nor mal
link, and it will flash as a traffic LED when tr an sm ittin g o r
receiving.
mode 1 = tra ffic LED on ly
88 FDX#
/ FDX # O LED output pin, active low
mode 0 = Full dup lex LED
mode 1 = Full dup lex LED
89 SPEED100#
/ SPEED100# O LED output pin, active low
mode 0 = 100Mbps LED
mode 1 = 100Mbps LED
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90 SPEED10#
/ LIN K# O LED output pin, active low
mode 0 = 10Mbps LED
mode 1 = Link LED
Network Inter face
Pin No.
128QFP/128TQFP Pin Name I/O Description
105,106 RXI+
RX- I 100M/10Mbps differential input pair.
These two pins are differential rec eive input pair for
100BASE-TX and 10BASE -T. They are capable of receiving
100BASE-TX ML T-3 or 10BASE-T Manch ester encoded
data.
109,110 TXO+
TXO- O 100M/10Mbps differential output pa ir.
These two pins are differential output pair for 100BAS E-TX
and 10BASE-T. This output pair provides controlled rise and
fall times designed to filter the transmitter output.
Miscellaneous P ins
Pin No.
128QFP/128TQFP Pin Name I/O Description
36 CLOCKRUN# I/O,
O/D Clockrun#
The clockrun# signal is used by the system to pause or slow
down the PCI clock signal. It is used by the DM9102A to
enable or disable suspension of the PCI clock sign al or restart
of the PC I clock. When the clockrun# s ignal is not used, this pin
should connected to an external pull-down resistor.
71 TEST2 I TEST mode control 2
In normal operation, this pin is p ull e d-high .
75 TEST1 I TEST mode control 1
In normal operation, this pin is p ulled lo w.
95 WOL/CSTSCHG O Wake up signal/Card Statu s Change
This is multiplexed pin to provide Wake on LAN signal or Card
Status Change. In a PC I system, it is used as a WOL signal. In
a CardBus s ystem, it is us ed as the Card Status Change
output signal and is asynchronous to the clock signal. It
indicates that a pow er management event has occurred in a
CardBus system. The DM9102A can assert t his pin if it d etects
link sta tus change, or magic packet, or sample frame. The
default is “normal low, active h igh pulse”. DM9102A a lso
support High/Low and Pu lse/Level options.
97 X2 O Crystal feedback output pin used for crystal connection only.
Leave this pin open if oscillator is used.
98 X1/OSC I Crystal or Oscillator input. (25MHZ
50ppm)
25MHz O scillator or series-reson anc e, fundam ental
frequency crystal.
102 BGRES I Bandgap Voltage Reference Resistor.
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It connects to a 6200
, 1% error tolerance res istor between
t h is p i n and B GRE S G p i n to pro vide an accurate current
reference for DM9102A..
101 BGRESG I For Bandgap circuit
It is used together w ith the B GRESG pin.
116 ISOLATE# I Isolate
This isolate s igna l is used to isolate the DM9102A from the
system, and it is suitable for LAN on motherboard. When
isolate signal is active low, it disables the D M9102A function
and the DM9102A will not drive any outputs and sample inputs.
In this case, the power consumption is minimum.
Power P ins
Pin No.
128QFP/128TQFP Pin Name I/O Description
100,107,
108 AGND P Analog ground
103,104,
111,112 AVDD P Analog power, +3.3V
8,9,15,22,28,29,35,37,45,
46,58,76,86,99,125 DGND P Digital ground
4,5,12,18,19,25,32,42,52,
53,61,70,82,96,120 DV D D P D ig it a l p ower , +3.3V
NOTE :
LED M odePin No.
128QFP/128TQFP MODE 0 MODE 1
87 LINK&ACT#
Link and traffic LED ACT#
Tra ffic L ED
88 FDX#
Full-duplex LED FDX#
Full-duplex LED
89 SPEED100#
100Mbps LED SPEED100#
100Mbps LED
90 SPEED10#
10Mbps LED LINK#
Link LED
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Register Definition
PCI Configuration Reg isters
Th e d efinition s of P CI Co nfi gur a tion Registers are based on
the PCI specification revis ion 2.2 and p rovides the
initialization an d configuration information to operate the PCI
interface in the DM9102A. All registers can be accessed
w ith byte, word, or double word mode. As defined in PCI
specification 2.1, read accesses to reserve or
unimplemented reg isters w ill return a value of “0.” These
registers are to be described in the following sections.
The default value of PCI configuration registers after reset.
Description Identifier Address Offset Value of Reset
Identification PCIID 00H 91021282H
Command & Status PCICS 04H 02100007H
Revision PCIRV 08H 02000031H
Miscellaneous PCILT 0CH BIOS determine
I/O Base Address PCIIO 10H System allocate
Memory Bas e Address PCIMEM 14H System allocate
Reser ved -------- 18H - 28H 00000000H
CardBus ICS pointer CIS 24H 00000000H
Subsystem Identification PCISID 2CH load from SROM
Expansion ROM Base Address PCIROM 30H 00000000H
Capability Pointer CAP_PTR 34H 00000050H
Reserved -------- 38H 00000000H
Inte rru p t & L ate nc y PCIIN T 3C H Sys te m al loca te bit7 ~0
De vice Specific Configuration Register PCIUSR 40H 00000000H
Power Manageme nt Re gister PCIPMR 50H C0310001H
Power Manageme nt Control & Status PMCSR 54H 00000100H
Key to Default
In the register description that follows, the default column
takes the form <Reset Value>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/Write
R/C: means Read / Write & Write "1" for Clear.
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Identification ID (xxxxxx00 - PCIID)
31 16 15 0
Dev_ID Vend_ID
Device ID
Vendor ID
Bit Default Type Description
16:31 9102h RO The field identifies the particular device. U nique and fixed number for the DM9102A
is 9102h. It is the pr oduct number assigned by DAVICOM.
0:15 1282h RO This field identifies the manu facturer o f the d evice. U nique and fix e d n umbe r fo r
Davicom is 1282h. It is a re gistered number from SIG.
Command & Status (xxxxxx04 - PCICS)
31 16 15 0
Status Command
Status
Command
98
Parity Error Response Enable/Disable
I/O Space Access Enable/Disable
Memory Space Access Enable/Disable
Master Device Capability Enable/Disable
SERR# Driver Enable/Disable
Mast Mode Fast Back-To-Back
Address/Data Steeping
VGA Palette snoop
Special Cycle
Memory Write and Invalid
31 30 29 28 27 26 25 24 23 22 21 20 10
0 0 1 0 0 0
19
1
Detected Parity Error
Signal For System Error
Master Abort Detected
Target Abort Detected
DEVSEL Timing
Data Parity Error Detected
Slave mode Fast back to Back
New Capability
66MHz Capability
User Definable
Send Target Abort
Reserved
00
76543210
00
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Bit Default Type Description
31 0 R/C Detected Par ity Error
The DM9102A samples the AD[0:31], C/BE[0:3]#, and the PAR signal to
c h ec k p a rity an d t o se t p ari t y e r r or s. In s lave m od e , the p ar ity c heck falls
on command phase and data valid phase (IRDY# and TRDY# both
active). While in master mode, the DM9102A will check during each data
phase of a m emory read cycle for a parity error Duri ng a memory write
cycle, if an error occurs, the PERR# sign al will be driven by the target. This
bit is set by the DM9102A and c leared by w riting "1 ". There is no e ffect by
w rit ing "0 " .
30 0 R/C Signa l For Sys te m Error
This b it is s et when the SERR# signal is driven by th e DM9102A. This
system error occurs when an address parity is detected under the
condition that bit 8 and bit 6 in command register below are set.
29 0 R/C Master Abort Detected
This b it is s et when the DM9102A terminates a master cycle w ith the
master-abort bus transaction.
28 0 R/C Target Abort Detected
This b it is s et when the DM9102A terminates a master cycle due to a
target-abort signal from other targets.
27 0 R/C Send Target Abort (0 For No Implementation)
The DM9102A w ill ne ver ass ert the target-abort sequence.
26:25 01 R/C DEVSEL Timing (01 Se lect Mediu m Timing)
Medium t iming o f DEVSEL# means the DM9102A w ill ass ert DEVSEL#
signal two clocks after FRAME# is sample “asserted.”
24 0 R/C Data Par ity Err or De tected
This bit will take effect only when operating as a master and when a Parity
Error Respons e Bit in command configuration register is set. It is set under
two conditions:
(i) PERR# asserted by the DM9102A in memory data read error, (ii)
PERR# sent from the target due to memory data write error.
23 0 RO Slave mode Fast Ba ck-To-Bac k Capable (0 For Not Support)
This b it is always reads "1" to indicate that the DM9102A is capab le o f
accepting fast back-to-back transaction as a slave mode device.
22 0 RO User-Definable-Feature Supported (0 For Not Support)
21 0 RO 66 MHz Capable (0 For No Capability)
20 1 RO New Capabilities (1 For Good Capab ility)
This b it indicates w hether this function implements a list of e xtended
capabilities such as PCI power management. When set this bit indicate s
the presence of New Capabil i tie s. A valu e of 0 m eans that this function
does not implement New Capabilities.
19:10 0 RO Reserved
9 0 RO Master Mode Fa st Back -To-Back (0 For Not Support)
The DM9102A does not support master mode fast back-to-back capability
and w ill not generate fast back-to-back cycles.
8 0 RW SERR# Driver Enable/Disable
This bit controls the assertion of SERR# sign al output. The SERR# output
will be asserted o n detect ion o f an address parity error and if both this bit
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and bit 6 are set.
7 0 RO Address/Data Stepping (0 For No Stepping)
6 0 RW Parity Error Respons e Enable/Disable
Setting this bit will enable the DM9102A to ass ert PERR# o n the detection
of a data parity error and to assert SERR # for reporting address parity
error.
5 0 RO VGA Palette Snooping (0 For Not Support)
4 0 RO Memory Write and Invalid (0 For Not Implementation)
The DM9102A on ly generates Memory write cy cle.
3 0 RO Special Cyc les (0 For Not Implementation)
2 1 RW Master Device Capability Enable/Disable
When this b it is s et, DM9102A has the a bility of master mode operation.
1 1 RW Memory Space Access Enable/Disable
This bit controls the ability of memory space access. The memor y access
includes memory mapped I/O access and Boot ROM access. As the
system boots up, this b it w ill be enabled by BIOS for Boot ROM memory
access. While in nor mal operation u sing memory mapped I/O access, this
bit should be set by driver before memory access cycles.
0 1 RW I/O Space A ccess Enable/Disable
This bit controls the ability of I/O space access. It will be set by BIOS after
power on.
Revision ID (xxxxxx08 - PCIRV)
31
078
Revision ID
Class Code
3
4
Class Code
Revision Major Number
Revision Minor Number
Bit Default Type Description
31:8 020000h RO Class Code (020000h)
This is the s tandard code for Ethernet LAN controller.
7:4 0011 RO Revision Major Number
Th is is t he s ili co n -major r evision n um ber that will increase for the subsequent
versions of the DM9102.A.
3:0 0001 RO Revision Minor Number
Th is is t he s ili co n -m in or r evision n um ber that will increase for the subsequent
versions of the DM9102A.
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Miscellaneous F unction (xxxxxx0c - PC ILT)
31 16 15 0872324
BIST Header Type Latency Timer Cache Line Size
Built-In Self Test
Header Type
Latency Timer For The Bus Master
Cache Line Size For Memory Read
Bit Default Type Description
31:24 00h RO Built In Self Test ( 00h Means Not Implementation)
23:16 00h RO Header Type ( 00h Means single function w ith Predefined Header Type )
15:8 00h RW Latency Timer For The Bus Master.
The latency timer is guaranteed by the system and measured by clock cycles.
Whe n th e F R A ME # a s se r t e d a t t h e b e g i n nin g of a m a s t e r p e r i o d b y t he D M9102A,
the value will be copied into a counter and start counting down. If the FRAME# is
de-asserted prior to count expiration, this value is meaningless. When the count
expires be fore GNT# is de-ass erted, the master transaction w ill be terminated a s
soon as the GNT # i s removed.
While GNT# s ignal is removed and the counter is non-zero, t he DM9102A will
continue w ith its data trans fers until the count e xpires. The syste m host will read
MIN_GNT and M AX_LAT registers to determine the latency requirement for the
device and then init ialize the latency timer w ith an appro priate v alue.
The reset value o f Latency Timer is determined by BIOS.
7:0 00h RO Cache line Size For Memory Read Mode Selection ( 00h Means Not
Implementation For Use)
I/O Base Address (xxxxxx10 - PCIIO)
31 0
1 7 8
1
0000000
I/O Base Address
I/O Base Address
PCI I/O Range
I/O or Memory Space Indicator
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Bit Default Type Description
31:7 Undefined RW PCI I/O Base Addre ss
This is the bas e address value for I/O accesses cycle s . It w ill b e c ompared to
AD[31:7] in the address phase of bus comm and cycle for the I/O r esource access.
6:1 000000 RO PCI I/O Range Indication
It indicates that the minimum I/O resource size is 80h.
0 1 RO I/O Space Or Memory Space Base Indicator
Determines that the register maps into the I/O space.( = 1 Indicates I/O Base)
Memory Mapped Base Address (xxxxxx14 - PCIMEM)
31 0
1 7
8
0000000
Memory Mapped
Base
0
Memory Base Address
Memory Range Indication
I/O or Memory Space I ndi cator
Bit Default Type Description
31:7 Undefined R/W PCI Memory Base Address
This is the base address value for Memory accesses cycles. It will be compared to
the AD[31:7] in the address phase of bus comm and cycle for the Memory resource
access.
6:1 000000 RO PCI Memory Range Indicat ion
It indicates that the minimum Me mory resource size is 80h.
0 0 RO I/O Space Or Memory Space Base Indicator
Determines that the register maps into the memory space( = 0 Indicates Memory
Base)
Subsystem Identification (xxxxxx2c - PCISID)
031
Subsystem ID Subsystem Vendor ID
Subsystem ID
Subsystem Vendor ID
Bit Default Type Description
31:16 XXXXh RO Subsystem ID
It can be loaded from EEPROM word 1 and different from each card.
15:0 XXXXh RO Subsystem Vendor ID
Unique number given by PCI SIG and loaded from EEPRO M word 0.
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CardBus CIS P ointer (xxxxxx28 - CCIS)
This Card Information Structure (C IS), also know n as tuples,
is a set o f data structures sa ved in a nonvolatile memory on
the CardBus Card. The data stored in CIS describe s the
product. Included in th is data are the product
manufacturer’s name, product name, and most importantly,
the hardware description. The CIS is supported in the boot
ROM space or the memory space (serial ROM).
CIS is read upon card insertion into the socket. The
software entity that traditi o n all y r eads the CIS is usually
known as Card Services and Sock et Services (CS & SS).
The CCIS pointer reg ister is a read-only 32-bit register.
This register points to one of the possible address space
where the card infor mation structure (CIS) begins. The
pointer is used in a CardBus environment. The content of
CCIS is loaded from the serial ROM after a hardware reset.
A va lue o f 0 in th is re g iste r ind ica tes tha t C IS is not
supported.
31 032728
ROM Image
Address Space Offset
Address Space Indicator
2
Bit Default Type Description
31:28 Note R/W ROM Image
The 4- bit RO M image field value when the CIS reside in an expansion ROM.
27:3 Note R/W Address Space Offset
This field contains the address offset w ithin the address space indic ate d by the
address space indicator field (CCIS<2:0>)
2:0 Note R/W Address Space Indicator
This field indicates the location o f the CIS bas e address. The value o f 2 indicates
that the CIS is stored in the serial ROM, and 7, indicates that the C IS is sto re d in the
expansion ROM.
note : read from serial ROM
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Expansion ROM Base Address (xxxxxx30 - PCIROM)
31 01
ROM Base Address R/W
11 10
Reserved
18 17
0000000
ROM Base Address
9
00000000
Bit Default Type Description
31:10 00h RW ROM Base Address With 256K Boundary
PCIROM bit17~10 are hardwired to 0, indicating ROM Size is up to 256K Size
9:1 000000000 RO Reserved Bits Read As 0
0 0 R W Expansion ROM Decoder Enable/Disable
If this bit and the me mory space access bit are bot h set to 1, the DM9102A will
responds to its expansion ROM.
Capabilities P ointer (xxxxxx34 - Cap _Ptr)
31
078
Reserved
0
Capability Pointer
10100 00
Bit Default Type Description
31:8 000000h RO Reserved
7:0 01010000 RO Capability Pointer
The Cap_Ptr pro vides an offset (default is 50h) into the function’s PCI Con figuration
Spa ce for th e loca tion o f the f ir st t er m i n th e Capabilitie s Linked List. The Cap_Ptr
offse t is DOUBLE WORD a ligned s o the two least s ignificant bits are a lways “0”s
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Interrupt & Latency Configuration (xxxxxx3c - PCIINT)
31 16 15 0872324
MAX_LAT MIN_GNT INT_PIN INT_LINE
Maximum Latency Timer
Minimum Grant
Interrupt Pin
Interrupt Line
Bit Default Type Description
31:24 28h RO Ma ximum Latency Timer that can b e su stained (Read Only and Rea d As 28h)
23:16 14h RO Minimum Grant
Minimum Length o f a Burst Period (Read Only and Read As 14h)
15:8 01h RO Interrupt Pin read as 01h to indicate INTA#
7:0 XX h RW Interrupt Line that Is Routed to the Interrupt Controller
The value depends on mainboard.
Device Specific Configuration Reg ister (xxxxxx40h- PCIUSR)
3130 29 1615 8 0
Reserved
272628 7
25 2423
Device Specific
Link Event enable/disable
Sample Frame Event enable/disable
Magic Packet Event enable/disable
Link Event Status
Sample Frame Event Status
Magic Packet Event Status
Device Specific
Reserved
Bit Default Type Description
31 0 RW Device Specific Bit (sleep mode)
30 0 RW Device Specific Bit (snooze mode)
29 0 RW When set enable Link Status Change Wake-up Event
28 0 RW When set enable Sample Frame Wake-up Event
27 0 RW When set enable Magic Packet Wake-up Event
26 0 RO When set, indicates link change and Link Status Change Event occurred
25 0 RO When set, indicates the sa mple frame is recei ved and Sample Frame Event
occurred
2 4 0 R O Wh e n s e t, in d ica te s th e Mag ic P acke t is r ece i ve d and Ma g ic p a c ke t E ve n t o ccu r re d
23:16 00h RO Reser ved Bits Read As 0
15:8 00h RW Device Specific
7:0 00h RO Reserved Bits Read As 0
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Power Management Register (xxxxxx50h~PCIPMR)
31 16 15 087
Power Management Capabilities
Next Item Pointer
Capability Identifier
P M C Next Item Pointer Capability ID
Bit Default Type Description
31:27 11000 RO PME_Support
These five bits field indicate the power states in which the function may assert
PME#. A value of 0 for any b it indicates that the fu nction i s no t c apable of asserting
the PME# signal while in tha t power state.
bit27
Æ
PME# s upport D0
bit28
Æ
PME# s upport D1
bit29
Æ
PME# s upport D2
bit30
Æ
PME# s upport D3(hot)
bit31
Æ
PME# s upport D3(cold)
DM9102A’s bit31~27=11000 indicates PME# can be asserted from D3(hot) &
D3(cold).
26:22 00000 RO Reser ved (DM9102A not supports D1, D2)
21 1 R O A “1 ” in d icate s tha t t he fu nc t io n re qu ir e s a d evi c e sp ec ific initiali za tion sequence
following transition to the D0 uninitialized state.
20 1 RO Auxiliary Power Source
Th is b it is o n ly me aningfu l if b it31 i s a “ 1” .
This b it is “1” in DM9102A ind icates that support for PME# in D3(cold) requires
auxiliary power.
19 0 RO PME# Clock
“0” indicates that no PCI clock is required for the function to generate PME#.
18:16 001 RO Version
A value of 001 indicates that this function complies with the Revision 1.0 of the PCI
Power Manageme nt Interface Specificati on.
A value o f 010 is for DM9102A/A tha t complies with the re vis ion 1 .1 of the PCI
Power Manageme nt Interface Specificati on.
15:8 00h RO Next It em Pointer
The offset into the function’s PCI Configuration Space pointing to the location of
next item in the function ’s capability list is “00h”
7:0 01h RO Capability Identifier
When “01h” indicates the linked list item as being the PCI Power Management
Registers.
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Power Management Control/Status (xxxxxx54h~PMCSR)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
31
R/W 0 0 0 0 0 0 R/W 0 0 0 0 0 0 R/W
16 15 14 9 8 7 2 1 0
PME_Status
PME_En
Power_State
Bit Default Type Description
31:16 0000h RO Reserved
15 0 RW/C PME_Status
This bit is set when the function would normally assert the PME# signal
independent of the state of the PME_En bit. Writing a “1” to this b it will clear it.
This b it de faults to “0” if the function does not support PME # generation from
D3(cold).If the function supports PME# from D3(cold) then t his bit is sti cky a n d
must be explicitly cleared by the operating system each time the operating
system is initially loaded.
14:9 000000 RO Reserved.
It means that the DM9102A does not s upport reporting power consumption.
8 1 RW PME_En
Write “1” to enables the function to assert PME#, write “0” to disable PME#
assertion.
This b it de faults to “0” if the function does not support PME # generation from
D3(cold).
If the function supports PME# from D3(cold) then this bit is sticky and must be
explicitly cleared by the operating system each time the operating system is
in itia lly loaded.
7:2 000000 RO Reserved
1:0 0 0 RW This tw o bits field is b oth used to de ter mine the current power state of a function
and to set the function i nt o a new power state. T h e d efini tions given below.
00 : D0
11 : D3(hot)
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Control and Status Registers (CR)
The DM9102A implements 16 control and status registers,
which can be accessed by the ho st. Th es e CRs a re double
long word aligned. All CRs are set to their default values by
hardware or software reset unless otherwise specifie d. All
Control and Status Reg isters with their de finitions and o ffse t
from IO or memory Base Address are shown belo w:
Register Description Offset from CSR
Base Address De fault va lue
after reset
CR0 System Control Re gister 00H FEC00000
CR1 Transmit Descriptor Poll Demand 08H FFFFFFFF
CR2 Receive Descriptor Poll D emand 10H FFFFFFFF
CR3 Receive Des criptor Base Address Register 18H 00000000
CR4 Transmit Descriptor Base Address Register 20H 00000000
CR5 Network Status Report Register 28H FC000000
CR6 Network Operation Mode Register 30H 02040000
CR7 Interrupt Mask Register 38H FFFE0000
CR8 Statistical Counter Reg ister 40H 00000000
CR9 E xternal Management Access Register 48H 044097FF
CR10 Progra mming R OM Address Register 50H Unpredictab le
CR11 General Purpose Timer Register 58H FFFE0000
CR12 PHY Status Reg ister 60H FFFFFFXX
CR13 Sample Fra me Access Register 68H XXXXXX00
CR14 Sample Frame Data Register 70H Unpredictable
CR15 Watchdog And Jabber Timer Register 78H 00000000H
Key to Default
In the register description that follows, the default column
take s the for m:
<Reset Value>, <Access Type>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
<Access Type>:
RO = Read only
RW = Read/Write
RW/C = Read/Write and Clear
WO = Wr ite on ly
Reserved bits are shaded and should be written with 0.
Reserved bits are undefined on read acce ss.
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1. System Co ntrol Register (CR0 )
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
24:22 Reserved 0,RO Reserved
21 MRM 0,RW Memory Read Multiple
When set, the DM9102A will use memory read multiple command (C/BE3~0 =
1100) when it initialize the memory read burst transaction as a master device.
When reset, it will use memory read command (C/BE3 ~ 0 = 0110) for the same
master operation.
20 Reserved 0,RO Reserved
19:17 TXAP 000,RW Transmit Automatic polling inter val time
When set, the DM9102A w ill poll transmit descriptor automatically when it is in the
suspend state due to buffer unavailab le. T he p o lling inte rval t ime is program mable
based on the ta ble shown below.
Bit 19 Bit 18 Bit 17 Time Interval
0 0 0 No polling
0 0 1 200us
0 1 0 800us
0 1 1 1.6ms
1 0 0 12.8us
1 0 1 25.6us
1 1 0 51.2us
1 1 1 102.4us
16 Reserved 0,RO Reserved
15:14 ABA 00,RW Address Boundary Alignment
When set, the DM9102A will execute each burst cy cles to stop at the prog rammed
address boundary. The address boundary can be progra mm e d t o b e 8 , 16, or 3 2
doubleword as shown bel ow.
Bit 15 Bit 14 Alignment Boundary
0 0 Reserved
0 1 8-double word
1 0 16-double word
1 1 32-double word
13:8 BL 000000,
RW Burst Length
When reset, the DM9102A’s burst length in one DMA transfer is limited b y the
amount o f data in the receive F IFO ( w hen receive ) or the amount o f free space in
the transmit FIFO (w hen transmit ). When s et, the D MA’s burst length is limited by
the programmed value . The permissible val ues are 0, 1, 2, 4, 8, 16, or 32
doublewords.
7 Reserved 0,RO Reserved
6:2 Reserved 00000
1 Reserved 0,RO Reserved
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Bit Name Default Description
0 SR 0,R W So ftw are Res et
When set, the DM9102A w ill make a internal reset cycle. All consequent action to
DM9102A2 should wait at least 32 PCI clock cycles to start and no necessary to
res e t th is b it.
2. Transmit Descriptor Poll Demand (CR1)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31:0 TDP FFFFFFFFh
,WO Transmit Descriptor Polling Co mmand
Writing any value to this port will force DM9102A to poll the tran smit d e sc riptor. If
the acting descriptor is not available, transmit proce ss will return to suspend state.
If the desc riptor show s buffer available, transmit proces s will begi n the data
transfer.
3. Receive Descriptor Poll Demand (CR2)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31:0 RDP FFFFFFFFh
,WO Receive Des criptor Polling Command
Writing any value to this port will force DM9102A to poll the receive descriptor. If the
ac tin g d e scri pt or i s n ot availabl e, r ec eiv e process will r eturn to suspend state. If the
descriptor shows buffer a vailable, recei ve process w ill begin the data transfer.
4. Receive Descriptor Base Address (CR3)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000
Bit Name Default Description
31:0 RDBA 00000000h
,RW Receive Descriptor Base Address
This register defines base address of receive descriptor-chain. The receive
descriptor- polling co mmand a fter CR3 is set w ill make D M9102A to fetch the
descriptor at the Base-Address.
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5. Transmit Descriptor Base Address (CR4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000
Bit Name Default Description
31:0 TDBA 00000000h,
RW Transmit Descriptor Base Address
This register defines bas e address of tra n smit d escript or-chain. The tra n smit
descriptor- polling co mmand a fter
CR4 is set will make DM9102A to fetch the descriptor at the Base-Address.
6. Network Status Re port Register (CR5)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
25:23 SBEB 000,RO Syste m Bus E rror B its
Thes e bits are read only and used to indicate the type of system bus fetal error. Valid
only w hen System Bus Error is set. The mapping bits are s hown belo w.
Bit25 Bit24 Bit23 Bus Error Type
0 0 0 Parity error
0 0 1 Master abort
0 1 0 Slave abort
0 1 1 Reserved
1 X X Reserved
22:20 TXPS 000,RO Transmit Process State
Thes e bits are read only and used to indicate the state of transmit process.
The mapping table is shown belo w.
Bit22 Bit21 Bit20 Process State
0 0 0 Transmit process stopped
0 0 1 Fetch transmit descriptor
0 1 0 Move Setup Frame from the host memory
0 1 1 Move data from host memory to transmit FIFO
1 0 0 Close descriptor by clearing owner bit of descriptor
1 0 1 Waiting end of transmit
1 1 0 Transmit end and Close descriptor by writing status
1 1 1 Transmit process suspend
19:17 RXPS 000,RO Receive Process State
Thes e bits are read only and used to indicate the state of receive process. The
mapping table is shown belo w.
Bit19 Bit18 Bit17 Process State
0 0 0 Receive process stopped
0 0 1 Fetch receive descriptor
0 1 0 Waiting for receive packet under buffer available
0 1 1 Move data from receive FIFO to host memory
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1 0 0 Close descriptor by clearing owner bit of descriptor
1 0 1 Close descriptor by writing status
1 1 0 Receive process suspended due to buffer unavailable
1 1 1 Purge the current frame from the rec eive FIFO
because of unavailable receive buff er
16 NIS 0,RW Normal Interrupt Summary
Normal interrupt includes any o f the t hree con ditions :
CR5<0> – TXCI : Tra n smit Complete Inte rrupt
CR5<2> – TXDU : Transmit Buffer Unavailable
CR5<6> – RXCI : Receive Complete Interrupt
15 AIS 0,RW Abnormal Interrupt Summary
Abnormal interrupt includes any interrupt condition as shown below excluding Normal
Interrupt conditions. They are TXPS(bit1), TXJT(bit3), TXFU(bit5), RX DU(bit7),
RXPS(bit8), RXWT(bit9), TXER(bit10), GPT(bit11), SBE(bit13).
14 ERI 0,R W Earl y Receive Interrupt
This bit will be set when ea rly receive interrupt has happened.
13 SBE 0,RW Syste m Bus E rror
The PC I sys tem bus errors w ill set this bit. Th e type of s ystem bus error is shown in
CR5<25:23>.
12 LCI 0,RW Link Status Change Interrupt
This b it w ill be set w hen link status change.
11 GPT 0,RW General-purpose Timer Expired
This b it is s et to ind icate the gener al-purpose timer (describe d in CR11) has expired.
10 TXER 0,R W Transmit Early Interrupt
Transmit Early Interrupt is set w hen the full packet data has been moved from hos t
memory into transmit FIFO. It will inform the host to process next step before the
tran smis sion end. Tra n smit compl ete ev e n t CR5<0 > wil l clea r this bit automa ticall y.
9 RXWT 0,RW Receive Watchdog Timer Expired
This b it is s et to indicate re ceive watchdog timer has e xpired.
8 RXPS 0,RW Receive Process Stopped
This b it is s et to indicate re ceive process enters the stopped state.
7 RX DU 0,R W Re cei ve B u ffer U nava ilab le
This b it is s et when the DM9102A fetches the next receive descriptor that is still
owned by the host. Rec ei ve proce ss will be suspended until a new frame enters or
the receive polling command is se t.
6 RX CI 0,R W Re cei ve Co mp lete Inte r rup t
This b it is s et when a rec eived frame is fully moved into host memory and receive
status has been written to descriptor. Receive process is still running and c onti nues to
fetch ne xt des criptor.
5 TXFU 0,RW Transmit FIFO Underrun
This b it is s et when transmit FIFO has underrun condition d uring the packet
transmission. It may happen due to the h eavy load on bus, receive process
dominates in full-duplex operation, or trans mit bu ffer una vailable be fore end o f
packet. In th is case, transmit process is placed in the suspend state and underrun
error TDES0 <1> is s et.
3 TXJT 0,RW Transmit Jabber Timer Expired
This b it is s et when the jabber timer e xpired w ith the transmitter is still active.
Transmit process will be aborted and placed in the stop state. It also causes transmit
jabber timeout TDES0 <14> to ass ert.
2 TXDU 0,R W Tra ns mit Bu ffe r Un a va ila ble
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This b it is s et when the DM9102A fetches the n ext tr ansmit descriptor that is still
owned by the host. Transmit process will be suspended until the transmit polling
command is set or auto-polling t imer time-out.
1 TXPS 0,RW Transmit Process Stopped
This b it is s et to indicate transmit process enters the stopped s tate.
0 TX CI 0,R W Trans mi t Co mp lete In terru p t
This b it is s et when a frame is fully transmitted and t ransmit status has been w ritten to
descriptor (the TDES1<31> is also asserted). Transmi t proc es s is still running and
continues to fetch next d escriptor.
7. Network O peration Mode Re gister (CR6)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
000 11 0000 0
0
Bit Name Default Description
30 RXA 0,RW Receive All
When s et, all incoming pa cket will be received, regardless the destination address.
The address match is checked according to theCR6<7>, CR6<6>, CR6<4>,
CR6<2>, CR6<0>, and RDE S0<30> will show this match.
29 NPFIFO 0,RW Set to not purg e RX FIFO if RX buffer unavailable
28:26 Reser ved 000,RO Must be Zero
25 Res erved 1,RO Must be One
24:23 Reser ved 00,RO Must be Zero
22 TXTM 1,RW Transmit Threshold Mode
When set, the trans mit threshold mode is 10Mb/s. When reset, the threshold mode
is 100Mb/s. Th is bit is used together w ith CR6<15:14> to decide the e xact
threshold level.
21 SFT 0,RW Store and Forward Transmit
When se t, the pa cket tra nsmission from MAC will b e started after a full fr ame has
been moved from the host memory to transmit FIFO. Whe n reset, the packet
transmission’s start will depend on the threshold value specified in CR6<15:14>
20 STI 0,RW Start Transmission Immediately
Wh en t his b it is s et , th e pa cke t t rans mi ssi o n fro m MA C wi ll be s ta r te d immediat ely
after trans mit FIFO’s threshold le vel reaches 16 b ytes, regar dless of the setting in
CR6<22> and CR6<15:14>. This mode will make transmit FIFO underrun
condition to happen more easily.
19 Reserved 0,RO Reserved
18 External
MII_Mode 1,R W 1: S e lect e x tern a l MI I inter fa ce .
0: Select external SRL interface.
In external MII mode that the pins TEST1, TEST2, and CLOCKRUN# ar e forced to
low, the DM9102A b ypasses internal PHY and us es external PHY , by s etting this
bit properly.
S e e page 6 6 for details.
17 Reserved 0,RO Reserved
16 1pkt 0,RW One Packet Mode
When this b it is set, only one packe t is s tored at TX FIFO.
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15:14 TSB 0,RW Threshold Bits
These bits are set together with CR6<22> (chose 10Mb or 100Mb) and will decide
the exact FIFO threshold level. The packet trans mission w i ll st a r t after the data level
exceeds the threshold value.
Bit15 Bit14 Threshold(100M) Threshold(10M)
0 0 128 72
0 1 256 96
1 0 512 128
1 1 Reserved Reserved
13 TXSC 0,RW Transmit Start/stop Command
When set, transmit process will begin by fetching the transmit descriptor for
available packe t data to be transmitted (running s tate). If the fetched d escriptor is
owned by the host, t ransmit proc ess will enter the suspend state and transmit buffer
unavailable (CR5 <2>) is s et. Otherwise it will begin to move data from host to
FIFO and transmit ou t after reaching threshold level.
When reset, tran smit process is placed in the stopped state a fter completing th e
transmission of the current frame.
12 FCM 0,RW Force Collision Mode
When set, the trans mission process is forced to be the collision status. Meaningful
on ly in the internal loopback mode.
11:10 LBM 0,RW Loopback Mode
Thes e bits de cide two l oopback modes besides normal operation. External
loopback mode expects transmitted data back to receive path and makes no
col lision det ection.
Bit11 Bit10 Loopback Mode
0 0 normal
0 1 internal loopback
1 0 internal PHY digital loopback
1 1 internal PHY analog loopback
9 FDM 0,RW Full-duplex Mode
This b it is s et to make DM9102A operate in the full-duplex mode. Transmit and
receive processes can work s imultaneously.
There is no collision detection needed during this mode operation.
8 Reserved 0,RO Must be zero.
7 PAM 0,R W Pass All Mu lticast
When set, any pac ket w ith a multicast destination address is received by the
DM9102A. The packet with a physical addres s will also be filtered based on the
filter mode setting.
6 PM 1,RW Promiscuous mode
When set, any incoming valid frame is received by the DM9102A, and no matter
what the de stination address. The DM9102A is initialized to this mode after reset
operation.
5 Reserved 0,RO Must be Zero.
4 IAFM 0,RO Inverse Address Filtering Mode
It is se t to in dic ate th e DM9102A operate i n a Inverse Filtering Mode. This is a read
only bit and mapped from the setup frame together with CR6<2>, CR6<0> setting.
T h at i s , i t i s val i d only d urin g p erfect f i lte rin g m ode.
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3 PBF 0,RW Pas s Bad Fra me
When set, the DM9102 is indicated to receive the bad frames including runt
packets, truncated frames caused by t he FIF O overflow. The bad frame also ha s to
pass the address filtering if the DM9102A is not set in promiscuous mode.
2 HOFM 0,RO Hash-only Filter Mode
This is a read-only bit and mapped from the set-up frame together with bit4,0 of
CR6.
It is se t to in dic ate th e DM9102A operate in a Hash-only Filtering Mode.
1 RXRC 0,RW Receive Start/Stop Co mmand
When set, rece ive process w ill begin by fetching the receive de scriptor for av ailable
buffer to store the new-coming packet (placed in the run ning state) . If the fetched
descriptor is owned by the host (no descriptor is owned by the DM9102A), the
receive process will enter the suspend state and receive buffer unavailable
CR5<7> sets. Otherwise it runs to wait for the pac ket’s inco me. When reset,
receive process is placed in the stopped state after completing the reception of the
current frame.
0 HPFM 0,RO Hash/Perfect Filter Mode
This is a read only bit and mapped from the setup frame together with CR6<4>,
CR6<2>. When reset, the DM9102A does a perfect address filter of incoming
frames according to the addresses specified in the setup frame. When set, th e
DM9102A does a imperfect address filtering for the inco ming frame w ith a multicast
address according to the hash table specified i n the setup fram e. The filte ring mode
(perfect / imperfect) for the frame w ith a physical address w ill depend o n CR6<2 >.
8. Interrupt Mask Register (CR7)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
16 NISE 0,RW Normal Interrupt Summary Enable
This b it is s et to enable the interrupt for Normal Interrupt Su mmary.
Normal interrupt includes three conditions :
CR5<0> – TXCI : Tra n smit Complete Inte rrupt
CR5<2> – TXDU : Transmit Buffer Unavailable
CR5<6> – RXCI : Receive Complete Interrupt
15 AISE 0,RW Abnormal Interrupt Summary Enable
This b it is s et to enable the interrupt for Abnormal Interrupt Summary.
Abnormal interrupt includes all interrupt condition as s hown below excluding
Normal Interrupt conditions. They a re TXPS(bit1), TXJT(bit3), TX FU(bit5),
RXDU(bit7), RX PS(bit8), RX WT(b it9), TXER(bit10), GPT(bit11), SB E(bit13).
14 ERIE 0,RW Early Receive Interrupt Enable
This b it is s et to enable the interrupt for Early Receive.
13 SBEE 0,RW Syste m Bus E rror Enable
When set togethe r with CR7<15>, CR5<13>, it enables the interrupt for System
Bus Error. The type o f system bus error is s hown in CR5 <24:23>.
12 LCIE 0,RW Link Status Change Interrupt Enable
This b it is s et to enable the interrupt for link status change .
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11 GPTE 0,RW General-purpose Timer Expired Enable
This b it is s et together w ith CR7<15>, CR5<11> then it will enable the interrupt for
the condition of the general-purpose timer (described in CR11) expired.
10 TXERE 0,RW Transmit Early Interrup t Enable
This b it is s et together w ith CR7<16>, CR5<10> then it enab les the interrupt of the
early transmit e vent.
9 RX WTE 0,RW Receive Watchdog Timer E xpired Enable
When this bit and CR7 <15>, (CR5<9> are set together, i t enable the interru pt of th e
condition of the receive watchdog timer expired.
8 RXPSE 0,RW Receive Process Stopped Enab le
When set togethe r with CR7<15> and CR 5<8>. Thi s bit i s se t t o enable the
interrupt of receive process stopped condition.
7 RX DUE 0,RW Receive Bu ffer Una vailable Enable
When this bit and CR7<15>, CR5<7> are s et together, it w ill enable the interrupt o f
receive bu ffer una vailable condition.
6 RX CIE 0,R W Re cei ve C o mple te Inte rru pt E nab le
When this bit and CR7<16>, CR5<6> are s et together, it w ill enable the interrupt o f
receive process co mplete cond ition.
5 TXFUE 0,RW Transmit FIFO Underrun Enable
When set together with CR 7<15>, CR5<5>, i t wil l enabl e th e i nterrupt of transmit
FIFO underrun condition.
4 Reserved 0,RO Reserved
3 TXJTE 0,R W Transmit Jabber Timer Expired Enab le
When this b it and CR7<15>, CR5 <3> are s et together, it enables the interrupt of
transmit Jabber Timer E xpired condition.
2 TXDUE 0,RW Transmit Buffer Una vailable Enab le
When this b it and CR7<16>, CR5<2> are set together, trans mit bu ffer unavailable
interrupt is enabled.
1 TXPSE 0,RW Transmit Process Stopped Enable
When this b it is set together w ith CR7<15> and CR5<1>, it will enable the interrupt
of the trans mit process stopped
0 TXC IE 0,R W Tran s mit C o mp le te Interr up t En ab le
When this bit and CR7<16>, CR5<0> are s et, the tra n smit i nterrupt is enabled.
9. Statistical Counter Register (CR8)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31 RX FU 0,RO Receive O ver flow Counter Overflow
This b it is s et when the Purged Packet Counter (RXDU) has a n o ve rflow condition.
It is a read only register bit.
30:17 RXDU 0,RO Receive Purged Packet Counter
This is a s tatistic counter to ind icate the purged received p acket count upon FIFO
overflow.
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16 RX PS 0,RO Receive M issed Counter O ver flow
This b it is s et when the Receive Missed Frame Counter (RXCI) has an o verflow
condition. It is a read only register bit.
15:0 RXCI 0,RO Receive Missed Frame Counter
This is a statistic counter to indicate the Receive Missed Frame Count when there is
a host buffer unavailabl e condition for receive process.
10. PROM & Management Access Register (CR9)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
31:22 Undefined X,RO Undefined
21 LES 0,RO Load EEPROM status
It is s et t o in di cate th e lo ad of EE PR OM is finis hed.
20 RLM 0,RW Reload EEPROM
It is set to r eload the conte nt of EEPROM.
19 MDIN 0,RO MII Management Data_In
This is read only bit to indi cate the MDIO input data.
18 MRW 0,RW MII Manage ment Read/ Write Mode Se lection
This b it de fines the Read/ Write Mode for MII management interface for PHY
access.
17 MDOUT 0,RW MII Management Data_Out
This b it is us ed to generate the output data signal for the M DIO pin.
16 MDCLK 0,RW MII Management Clock
This b it is us ed to generate the output clock signal for the MD C pin.
15 MBO 1,RO Must be One.
14 MRC 0,R W Me mory Read Control
This b it is s et to per form the read operation for the Bo ot PROM or EEPROM
access.
13 EWC 0,RW Memory Write Control
This b it is s et to perform the write operation for the Boot P ROM (M ultiplex mode) or
EEPR OM acces s.
12 BRS 1,RW Boot ROM Se lected
This b it is s e t to se lect th e Boo t RO M a c ces s for memo ry interface.
11 ERS 0,RW EEPROM Sele cted
This b it is s e t to se lect th e EE PRO M a c ces s for memor y interface.
10 XRS 1,RW External Register Selected
This b it is s e t to se lect a n e xtern a l reg is ter.
9:8 MBO 1,RO Must be One
7:0 DATA 1,RW Data input/output of Boot ROM
This field contains the data which reads from or write to the Boot ROM w hen the
Boot R OM mode is selected. ( CR9 <12> = 1 )
If EEPROM is selected ( CR9 <11> = 1 ), then CR9<3:0> are connected the s erial
ROM control pins.
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3 CRDOUT 1,RW Data_Out from EEPROM
This b it is s et to reflect the sig nal status of EEDI pi n when EEPROM mode is
selected.
2 CRDIN 1,RW Data_In to EEPROM
This b it is s et to generate the output sig n al to E E DO pin w hen EEPROM mod e is
selected.
1 CRCLK 1,RW Clock to EEPROM
This b it is s et to generate the output cl ock to E ECLK pi n when EEPROM mode i s
selected.
0 CRCS 1,RW Chip_Select to EEPROM
This b it is s et to generate the output si gn al to E EC S pin when EEPROM mode is
selected.
11. Programming ROM A ddress Re gister (CR10)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
17:0 BADR Unpredictable Boot ROM Address
This field contains the address pointer for Boot RO M when the mode o f
programming by register is selected.
12. General Purpose Timer Register (CR11)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543210
Bit Name Default Description
16 TCON 0,RW Continuous Mode o f Timer
Wh en this bit is s et, the t imer w ill c on tinuously re-initiated upon the set time is up.
When res et, the timer w ill be one-shot response after BCLK value is prog rammed.
15:0 MBCLK 0000h,RW Multiple o f Base Clock
This field set the iteration number of base clock. The base clock duration is def ined
to be
81.92us --- for M II po rt/100M is selected
2us --- for M II port/10 M is s elec ted
13. PHY Status Register (CR12)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9876543 210
Bit Name Default Description
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8 GEPC X,R W GEPD B its C on trol
Wh en in in itializa tio n , this bit is set and the unique “80h” must be w ritten to the
GEPD(7:0). After initialization, this bit is reset and it controls the functional mode of
GEPD in bit0~7.
7 GEPD(7) X,RW General PHY Res et Control
It mus t be set to “1” if CR12<8> is set.
When CR12<8> is reset, write “1” to this bit w ill reset the PHY of the DM9102A.
6:0 GEPD(6:0) XXXXXXX
,RW General PHY Status
When CR12<8> is set at initialization, it operates the o nly write operati on and write
the unique “0000000” to these se ven bits.
After initialization, CR12<8> is reset, write operation is mea ningless and read
these seven bits to indicate the PHY status.
These s tatus bits are s hown below.
bit 6:Current Media Link Sta tus
bit 5:Signal Detection
bit 4:RX-lock
bit 3:Internal PHY Link status (the s ame as bit2 o f PHY Reg ister)
bit 2:Full-duplex
bit 1:Speed 100Mbps link
bit 0:Speed 10Mbps link
14. Sample Frame Access Register (CR13) (reference to Power Management section)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
register general definition bit8 ~ 3 R/W
TxFIFO transmit FIFO access port 32h R/W
RxFIFO receive FIFO access port 35h R/ W
DiagReset general reset for diagnostic pointer port 38h W
15. Sample Frame Data Register (CR14) (reference to Power Management section)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
16. Watchdog and Ja bber Timer Register (CR15)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 987654 3 210
Bit Name Default Description
31:25 Reserved 0,RO Reserved
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24:22 ERIT 000,RW Early Receive Interrupt Threshold
These three bits determine the threshold of the received packet data from R X FIFO
to host memory.
bit24 bit 23 bit22 threshold (percentage)
0 0 0 Disable
0 0 1 12.5%
0 1 0 25.0%
0 1 1 37.5%
1 0 0 50.0%
1 0 1 62.5%
1 1 0 75.0%
1 1 1 87.5%
21:16 FIFOT 000000
,RW RX FIFO flow control threshold o ption
The value of bit21~16 determine the threshold of RX FIFO overflow when in flow
control mode. The exact threshold is 32bytes multiplied by this value.
15 TXPM 0,R W Transmit pause packet con dition control
1 = Indicate Transmit pause packet either CR15<11> or CR15<12> is set.
0 = Indicate Transmit pause packet both CR15<11> and CR15<12> are set.
14 TXP0 0,RW Transmit pause packet
Set to Transmit pause pack et with pause timer = 0000h
13 TXPF 0,RW Transmit pause packe t
Set to Transmit pause pack et with pause timer = FFFFh, this bit will be cleared if
packet had trans mitted.
12 TXPE1 0,RW Transmit pause packet enable
Set to enable T ransmit pause packet if d escriptor unavailable
11 TXPE2 0.RW Transmit pause packet enable
Set to enable T rans mit pause packe t with time = FFFFh if FIFO near overflow, or
with time = 0000h if FIFO empty.
10 FLCE 0,RW Flow Control Enable
Set to enable the decode o f the pause packet.
9 RXPS 0,R/C The latched status of the decod e of the pause packet.
8 Reserved 0,RO Reserved.
7 RXPCS 0,RO Of the decode o f the paus e packet.
6 VLAN 0,RW VLAN Capability Enable
It is set to enable th e VLAN mode.
5 TWDR 0,RW Time Interval o f Watchdog Release
This bit is used to select the time inte rval between receive Watchdog timer
expiration unt il re -enabling of the rec eive channel. When this bit is set, the tim e
inter val is 40~48 b its time. When this bit is reset, it is 16~24 bits time.
4 TWDE 0,RW Watchdog T imer D isable
When set, the Watchdog Timer is disabled. Otherwise it is enabled.
3 Reserved 0,RO Reserved
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2 JC 0,RW Jabber Clock
When set, the trans miss ion is cu t off after a range o f 2048 byte s to 2560 bytes is
transmitted.
Wh en res ets, tr an smission for the 10Mbps port is c ut off afte r a range of 26ms to
33ms.
Wh en res ets, tr an smission for the 100Mbps port is c ut off afte r a range of 2.6ms to
3.3ms.
1 TUNJ 0,RW Transmit Unjabber Inter val
This bit is used to select the time inte rval between t ran smit j abber timer expiration
until re-enabling of the transmit channel. When set, transmit channel is released
right after the jabber expiration. When reset, the time interval is 365~420ms for
10Mb/s port and 36.5~42.0ms for 100Mb/s.
0 TJE 0,RW Transmit Jabber Disable
When set, the transmit Jabber Timer is disabled. Otherwise it is enabled.
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Car dBus S tatus Ch ang ed R egister s
The DM9102A implements four status changed registers.
These status changed registers are a ccessed by the
CardBus systom software. These reg isters are mapped
only to the memory address space and not to the I/O
address space.
1. Function Event Register: (offset 80h)
Bit Name Default Description
0:3 Res erved R/W Unpredictable on read
4 General Wake-up
Event R/WC This b it is s et when the DM9102A has detected a power management event.
This bit is cleared upon power-up reset and by write 1. It is unaffected by either
hardware or software reset. When th e PME_Status bit in the PCI configuration is
cleared, th is b it is automatically cleared as well.
5:14 Reserved R/W Unpredictable on read
15 Interrupt R/WC This b it is s et when there is an interrupt pending.
Th is b it is c le a re d b y wri t e 1 . T hi s bit is cleared upon har dware o r software reset.
16:31 Reser ved R/W Unpredictable on read
2. Function Event Mask Register: (offset 84h)
Bit Name Default Description
0:3 Res erved R/W Unpredictable on read
4 General Wake-up
Event Enable R/WC When set together with the Wake-up Event Summar y Ena ble bit (Function Event
Mask Register<14>), enables the assertion of the CSTSCHG p in.
To disable the assertion of the CSTSCHG, the PME_Enable bit in the PCI
co nfigura tion r eg ister (P MC<8> ) m ust be cle ar ed as well.
This bit is cleared upon power up reset.
5:13 Reserved R/W Unpredictable on read
14 Wake-up Event
Summary Enable R/W When set togethe r with the General Wake-up Event Enable bit (Function Event
Mas k Register<4>), enables the assertion of the CSTSCHG pin.
To disable the assertion of the CSTSCHG pin, the PME_Enable bit in the PCI
co nfigura tion r eg ister (P MC<8> ) m ust be cle ar ed as well.
This is cleared upon power up reset.
15 Inter rup t R eg is ter
Enable R/W When s et, enable the assertion of the interrupt pin (INT#).
This b it is c leared upon har dware or software reset.
16:31 Reser ved R/W Unpredictable on read
3. Function Present State Register: (offset 88h)
Bit Name Default Description
0:3 Res erved R/W Unpredictable on read
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4 General Wake-up
Event R This b it reflects the current state o f the w ake-up event. It is cleared w hen either the
General Wake-up Event in the Function Event Register is cleared or when the
PME_Status in the PMC is cleared.
This b it is c leared upon har dware or software reset.
5:14 Reserved R/W Unpredictable on read
15 Interrupt R This b it reflects the internal state o f a function spec ific interrupt. It is c leared when
the event tha t caused the interrupt was either masked in CSR7, or c leared in
CSR5.
This b it is c leared upon har dware or software reset.
16:31 Reser ved R/W Unpredictable on read
4. Function Force Event Re gister: (offset 8Ch)
Bit Name Default Description
0:3 Res erved R/W Unpredictable on read
4 Force Wake-up W Writing 1 to this bit sets the wake-up event field in the Function Event Register
(Function Event Register<4>), but not in the Function Present State Register
(Function Present State Register<4>).
Writing 0 has no e ffect.
5:14 Reserved R/W Unpredictable on read
15 Forc e In te r ru pt W Wr it in g 1 to this b it s e ts th e in te rru p t f i eld in the Function Event Register (Function
Event Register<15>), but not in the Function Present State Reg ister (Function
Present State Reg ister<15>).
Writing 0 has no e ffect.
16:31 Reser ved R/W Unpredictable on read
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PHY Management Registers
Offset Register Name Description Default value after reset
0 BMCR Basic Mode Contro l Register 3100h
1 BMSR Basic Mode Status Register 7809h
2 PHYIDR1 PHY Identifier Register #1 0181h
3 PHYIDR2 PHY Identifier Register #2 B840h
4 ANAR Auto-Negotiation Ad vertise ment Reg ister 01E1h
5 ANLPAR Auto-Negotiation Link Par tner Ability Register 0000h
6 ANER Auto-Negotiation E xpansion Register 0000h
7-15 Reserved Reserved 0000h
10h DSCR DAVICOM Specified Con figuration Reg ister 0000h
11h DSCSR DAVICOM Spec ified Configuration/Status Register F010h
12h 10BTCSR 10BASE-T Configuration/Status Reg ister 7800h
Others Reserved Reserved for future use, do not Read/Write to these
Registers 0000h
Key to Default
In the register description that follows, the default column
take s the for m:
<Reset Value>, <Access Type> / <Attribute(s)>
Where
<Reset Value>:
1 Bit set to logic one
0 Bit set to logic zero
X No default value
(PIN#) Value latched in from pin # at reset
<Access Type>:
RO = Read only
RW = Read/Write
<Attribute (s )>:
SC = Self clear ing
P = Value permanently set
LL = Latching low
LH = Latching high
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Basic Mode Control Register (BMCR) – 0
Bit Name Default Description
0.15 Reset 0, R W/SC Reset:
1=Software reset
0=Normal operation
This b it s ets the status and controls the PHY registers o f the DM9102A to their
default states. This bit, w hich is self-clearing, will keep re turning a value o f one
until the reset process is co mpleted
0.14 Loopback 0, R W Loopback:
1=Loop-back enabled
0=Normal operation
When in 100Mbps operation mode, setting this bit may cause the
descrambler to lose synchronization and produce a 720ms "dead time" bef ore
any valid data appear at the MII rece ive outputs
0.13 Speed Selection 1, R W Speed Select:
1=100Mbps
0=10Mbps
Link speed may be s elected e ither by th is b it or by Auto-negotiation. When
Auto-negotiation is enabled and bit 12 is set, t his bit will return Auto-
negotiation s elected media type.
0.12 Auto-negotiation
Enable 1, R W Auto-negotiation Enable:
1= Auto-negotiation enabled: bit 8 and 13 will be in Auto -negoti ation status
0= Auto-negotiation disabled: bit 8 and 13 will determine the link speed and
mode
0.11 Power Down 0, RW Power Down:
Setting this bit willpower dow n the w hole chip e xcep t crystal / oscillator c ircu it.
1=Power Down
0=Normal Operation
0.10 Isolate 0,RW Isolate:
1= Isolates the DM9102A from the MII with the e xception of the serial
management.
0= Normal Operation
0.9 Res ta rt Au to-
negotiation 0,RW/SC Res tart Auto-negotiation:
1= Restart Auto-negotiation. Re-initiates the Auto-negotiation process. When
Auto-negotiation is d isabled (b it 12 of t his register cleared), this bit has no
fun ction a nd it shoul d be cleared. This bit i s se lf- cl e a ring and it wi ll keep
returning a value of 1 until Auto-negot iation is initiated by the DM9102A. The
operation o f the Auto-negotia tion process will not be affected by the
management entity that c lears this bit.
0= Normal Operation
0.8 Duplex Mode 1,RW Duplex Mode:
1= Full Duplex operation. Duplex selection is allowed when Auto-negotiati o n i s
disabled (bit 12 of this register is cleared). With Auto-negotiation enabled, this
bit reflects the duplex capability selected by Auto-negotiation.
0= Normal operation
0.7 Collis ion Test 0,RW Collision Test:
1= Collision Test enabled. When set, this bit will cause the COL signal to be
asserted in response to the assertion of TX_EN.
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0= Normal Operation
0.6:0.0 Reserved <0000000>,
RO Reserved. Write as 0, ignore on read
Basic Mode Status Register (B MSR) – 1
Bit Name Default Description
1.15 100BASE-T4 0,RO/P 100BASE-T4 Capab le:
1=DM9102A is ab le to p erform in 100BASE-T4 mode
0=DM9102A is not ab le to perform in 100BASE-T4 mode
1.14 100BASE-TX
Full Duplex 1,RO/P 100 BASE-TX FUL L D UPLEX CAPABL E:
1= DM9102A able to perform 100BASE-TX in Full Duplex mode
0= DM9102A not ab le to perform 100BASE -TX in Full Duplex mod e
1.13 100BASE-TX
Half Duplex 1,R O/P 100 BASE- TX H alf Du p lex Capable:
1=DM9102A is able to perform 100BASE-TX in Half Duplex mode
0=DM9102A is not ab le to pe rfo rm 100BASE-TX in Half Duplex mode
1.12 10BASE-T
Full Duplex 1,RO/P 10BASE-T Full Duplex Capable:
1=DM9102A is able to perform 10BASE-T in Full Duplex mode
0=DM9102A is not ab le to pe rfo rm 10BASE-T in Full Duplex mode
1.11 10BASE-T
Half Duplex 1,RO/P 10BASE-T Half Dup le x Capable:
1=DM9102A is able to perform 10BASE-T in Half Duplex mode
0=DM9102A is not ab le to pe rfo rm 10BASE-T in Half Duplex mode
1.10-1.7 Reserved 0000,RO Reserved:
Write as 0, ignore on read
1.6 MF Preamble
Suppression 0,RO MII Frame Preamble Suppression:
1=PHY w ill accep t management frames with preamble suppressed
0=PHY will not accept management frames with preamble suppressed
1.5 Auto-negotiation
Complete 0,RO Auto-negotiation Complete:
1=Auto-negotiation process completed
0=Auto-negotiation process not completed
1.4 Remote Fault 0,
RO/LH Remote Fault:
1= Remote fault condition detected (cleared on read or by a chip reset). Fault
criteria and detection method is DM9102A implem entati on s pecific. This bit will
set after the RF bit in the ANLPAR (b it 13, reg ister address 05) is set
0= No remote fault condition detected
1.3 Auto-negotiation
Ability 1,RO/P Auto Configuration Ability:
1=DM9102A able to per form Auto-negotiation
0=DM9102A not able to pe rform Auto-negotiation
1.2 Link Sta tus 0,RO/LL Link Status:
1=Valid link established ( for e ither 10Mbps or 100Mbps operation)
0=Link not es tablished
The link status bit is implemented with a latching function, so that the
occurrence o f a link failure condition causes the L ink Status bit to be cleared
and remain cleared until it is read v i a the management interface
1.1 Jabber Detect 0,
RO/LH Jabber Detect:
1=Jabber condition detected
0=No jabber
This b it is implemented with a latching function. Jabber cond itions w ill set this
bit u nles s it is c leare d by a read t o t hi s re gist er through a management
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interface or a DM9102A reset. This bit works only in 10Mbp s mode
1.0 Extended
Capability 1,RO/P Extended Capability:
1=Extended register capability
0=Basic register capability only
PHY ID Identifier Register #1 (PHYIDR1) – 2
The PHY Identifier Register#1 and Reg ister#2 w ork together in a single identifier of the DM9102A. The Identifier consists o f a
concatenation of the Organization ally Unique Identifier (OUI), a vendor's model number, and a model revis ion number.
DAVICOM Se miconductor's IEEE as signed OUI is 00606E.
Bit Name Default Description
2.15-2.0 OUI_MSB <0181H> OUI Mos t Significant Bits:
This register stores bit 3 to 18 of the OUI (00606E) to bit 15 to 0 of this register
respectively. The most significant two bits of the OUI are ignored (the IEE E
standard refers to these as bit 1 and 2)
PHY Identifier Register #2 (PHYIDR2) - 3
Bit Name Default Description
3.15-3.10 OUI_LSB <101110>,
RO/P OUI Least Significant Bits:
Bit 19 to 24 of the OUI (00606E) are mapped to bit 15 to 10 of this register
respectively
3.9-3.4 VNDR_MDL <000100>,
RO/P Vendor Mod el N umber:
Six bits of vendor model number mapped to bit 9 to 4 (most significant bit to bit
9)
3.3-3.0 MDL_REV <0000>,
RO/P Model Re vis ion Nu mber:
Four bits of vendor model revision number mapped to bit 3 to 0 (most
s igni fican t b it to b it 3)
Auto-negotiation A dvertisement Register (A NAR) – 4
This register contains the advertised abilities of this DM9102A device as they will be t ransmitted to its link partner during Auto-
negotiation.
Bit Name Default Description
4.15 NP 0,RO/P Next Page Ind ication:
0=No next page available
1=Next page available
The DM9102A has no next page, so this bit is permanently set t o 0
4.14 ACK 0,RO Acknowledge:
1=Link partner ab ility data reception a cknowledged
0=Not acknowledged
The DM9102A's Auto-negotiation state machine will automatically control this
bit in the outgoing FLP bursts and set it at the appropriate time during the
Auto-negotiation process. Software should not attempt to write to this bit.
4.13 RF 0, RW Remote Fault:
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1=Local Device senses a fault condition
0=No fault detected
4.12-4.11 Reser ved 00, R W Reserved:
Write as 0, ignore on read
4.10 FCS 0, R W Flow Control Support:
1=Controller chip supports flow control ability
0=Controller chip doesn ’t support flow control ability
4.9 T4 0, R O/P 100BASE-T4 Support:
1=100BASE-T4 supported by the local device
0=100BASE-T4 not s upported
The DM9102A does not support 100BASE-T4 s o this b it is per manently
4.8 TX_FDX 1, R W 100BASE-TX Full Duplex Support :
1=100BASE-TX Full Duplex supported by the local device
4.7 TX_HDX 1, R W 100BASE-TX Support :
1=100BASE-TX supported by the local device
0=100BASE-TX no t supported
4.6 10_FDX 1, RW 10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the local device
0=10BASE-T Full Duplex not supported
4.5 10_HDX 1, R W 10BASE-T Support :
1=10BASE-T supported by the local device
0=10BASE-T not supported
4.4-4.0 Selector <00001>,
RW Protocol Selection Bits:
These bits contain the binary encoded protocol selector supported by this
node. <00001> indicates that th is de vice supports IEEE 802.3 CS MA/CD.
Auto-negotiation Link Partner Ability Register (ANLPAR) – 5
This register contains the advertised abilities of the link partne r when receiv ed during Auto-negotiation.
Bit Name Default Description
5.15 NP 0, RO Next Page Indication:
0= Link partner, no ne xt page a vailable
1= Link partner, next page a vailab le
5.14 ACK 0, R O Acknowledge:
1=Link partner ab ility data reception a cknowledged
0=Not acknowledged
The DM9102A's Auto-negotiation state machine will automatically control this
bit from the incoming FLP bursts. Software should not attempt to write t o t his
bit.
5.13 RF 0, RO Remote Fault:
1=Remote fault indicated by link partner
0=No remote fault indicated by link partner
5.12-5.10 Reser ved 000, RO Reser ved:
Write as 0, ignore on read
5.9 T4 0, RO 100BASE-T4 Support:
1=100BASE-T4 supported by the link partner
0=100BASE-T4 not s upported by the link partner
5.8 TX_FDX 0, R O 100BASE-TX Fu ll Duple x Support:
1=100BASE-TX Full Duplex supported by the link partner
0=100BASE-TX Full Duplex not supported by the link partner
5.7 TX_HDX 0, RO 100BASE- TX Support:
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1=100BASE-TX Half Duplex supported b y the link partner
0=100BASE-TX Ha lf Duplex not supported by the l ink p artner
5.6 10_FDX 0, RO 10BASE-T Full Duplex Support:
1=10BASE-T Full Duplex supported by the link partner 0=10BASE-T Full
Duplex not supported by the link partner
5.5 10_HDX 0, RO 10BASE- T Support:
1=10BASE-T Half Duplex supported by the link partner
0=10BASE-T Half Duplex no t supported b y the link partner
5.4-5.0 Selector <00000>,
RO Protocol Selection Bits:
Link partner’s binary encoded protocol selector
A uto-Neg otiation Expa nsio n Register (A NER) – 6
Bit Name Default Description
6.15-6.5 Reserved 0, RO Reser ved:
Write as 0, ignore on read
6.4 PDF 0, RO/LH Local De vice Para llel Detection Fau lt:
PD F=1 : A fau lt de tected via p arallel detecti on fu nctio n.
PDF=0: No fault detected via parallel detection function
6.3 LP_NP_ABLE 0, RO Link Partner Next Page Able:
LP_NP_ABLE=1: Link partner, next page available
LP_NP_ABLE=0: Link partner, no next page
6.2 NP_ABLE 0,RO/P Local De vice Next Page Able:
NP_ABLE=1: DM9102A, next page a vailable
NP_ABLE=0: DM9102A, no next page
DM9102A does not support t his function, so this bit i s al w a y s 0.
6.1 PAGE_RX 0, RO/LH New Page Received:
A new link code word page received. This bit will be automatically
cleared w hen the register (Reg ister 6) is read by management
6.0 LP_AN_ABLE 0, RO Link Partner Auto-negotiation Able:
A “1” in this b it indicates that the link par tner supports Auto-negotiation.
DAVICOM Specified Configuration Register (DSCR) - 10h
Bit Name Default Description
16.15:16.8 Res erved 0, RO Reser ved
16.7 F_LINK_100 0, RW Force Good Link in 100Mbps:
0 = Normal 100Mbps operation
1 = Force 100Mbps good link status
This b it is us eful for d iagnostic purposes.
16.6:16.4 Reserved 0,RO Reserved
16.3 SMRST 0,RW Reset State Machine:
When writes 1 to this bit, all state mach ines o f PHY will be reset. Th is b it is
s elf-c lear a fter re se t is c o mp le ted.
16.2 MFPSC 0,RW MF Preamble Suppression Control:
MII frame preamble suppression control bit
1 = MF preamble suppression bit on
0 = MF preamble suppression bit off
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16.1 SLEEP 0,RW Sleep Mode:
Writing a 1 to this bit will cause PHY entering the Sleep mode and power
down all circuit except oscillator and clock generator circuit. When waking up
from Sleep mode (w rite this bit to 0), the configuration will go back to the state
before sleep; but the state machine will be reset
16.0 RLOUT 0,RW Remote Loop out Control:
Whe n th is b it is s et to 1 , th e r ec e ived d a t a will loop o u t to the t rans mit channel.
This is u se fu l for bi t e rro r rate te stin g
DAVICOM Specified Configuration and Status Register (DSCSR) - 11h
Bit Name Default Description
17.15 100FDX 1, RO 100M Full Duplex Operation Mode:
After Auto-negotiation is completed, res ults w ill be written to th is bit. If this bit is
1, it means the operation 1 mode is a 100Mbps Full Duplex mode. The
software can read bit[15:12] to see w hich mode is selected after Auto-
negotiation. This bit is in valid w hen it is not in the Auto-negotiation mode.
17.14 100HDX 1, RO 100M Half Dup lex Operation Mode :
After Auto-negotiation is completed, res ults w ill be written to th is bit. If this bit is
1, it means the operation 1 mode is a 100Mb ps Half Duplex mod e. The
software can read bit[15:12] to see w hich mode is selected after Auto-
negotiation. This bit is in valid w hen it is not in the Auto-negotiation mode.
17.13 10FDX 1, RO 10M Full Duplex Operation Mode:
After Auto-negotiation is completed, res ults w ill be written to th is bit. If this bit is
1, it means the operation 1 mode is a 10Mbps Full Duplex mode. The
software can read bit[15:12] to see w hich mode is selected after Auto-
negotiation. This bit is in valid w hen it is not in the Auto-negotiation mode.
17.12 10HDX 1, RO 10M Half Dup lex Operation Mode:
After Auto-negotiation is completed, res ults w ill be written to th is bit. If this bit is
1, it means the operation 1 mode is a 10Mb ps Half Duplex mod e. The
software can read bit[15:12] to see w hich mode is selected after Auto-
negotiation. This bit is in valid w hen it is not in the Auto-negotiation mode.
17.11-17.9 Reser ved 000, R W Reser ved:
Write as 0, ignore on read
17.8-17.4 PHYAD[4:0] 00001, RW PHY Addres s Bit 4:0:
The first PHY address bit trans mitted or rec eived is the MSB of the addre ss
(bit 4). A station management entity connected to multiple PHY ent ities must
know the appropriate address of each PHY. A PHY address of <00000> will
cause the isolate b it of the B MCR (bit 10, Reg ister Address 00) to be set.
17.3-17.0 ANMB[3:0] 0000, RO Auto-negotiation Monitor Bits:
These bits are for debug only. The Auto-negotiation status will be written to
the se bits.
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b3 b2 b1 b0
0
0
0
0
I
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t
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0
0
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0
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0011Acknowledge match fail
0
1
0
0
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n
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y
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0101Consistency match fail
0
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0 1 1 1 Parallel detects signal_link_ready
fail
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successfully
10BASE-T Configuration/Status (10BTCSRCSR) - 12h
Bit Name Default Description
18.15 Reserved 0, RO Reserved:
Write as 0, ignore on read
18.14 LP_EN 1, R W Link Pulse Enable:
1=Transmission o f link pulses enabled
0=Link pu lses disabled, good link condition forced
This b it is valid only in 10Mbps operation .
18.13 HBE 1,RW Heartbeat Enable:
1=Heartbeat function enabled
0=Heartbeat function disabled
When the DM9102A is configured for Full Duplex operation, this bit will be
ignored (the collision/heartbeat function is invalid in Full Duplex mode). It must
s et to b e 1.
18.12 SQUELCH 1, RW Squelch Enable
1 = normal squelch
0 = low squelch
18.11 JABEN 1, R W Jabber Enable:
Enables or disables the Jabber function when the DM9102A is in 10BASE-T
Full Duplex or 10BASE -T Tra n sceiver Loopback mode
1= Jabber function enabled
0= Jabber function d isabled
18.10-18.0 Reser ved 0, RO Res erved
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Fun ctional D escrip tion
Sys tem Buffer Mana gement
1.Overview
The data buffers for reception and tran s missio n of d at a
resides in the host memory. They are directed by the
descriptor list that is located in another region of the host
memory. All actions for the bu ffer management are operated
by the DM9102A in conjunction with the driver. The data
structures and processing algorithms are described in the
following text.
2. Data Structure and Descriptor List
There are two types of buffers that reside in the host
memory, the transmit buffer an d the receive buffer. The
buffers are composed of many distributed regions in the
host memory. They are linked together and controlled by the
descriptor lists that res ide in another reg ion o f the host
memory. The content of each d escriptor includes poi nter to
the buffer, count of the buffer, command and status for the
packe t to be transmitt ed or receive d. E ach descript or list
starts from the addres s setting o f CR3 ( receive de scriptor
base address) and CR4 (tran smit de scriptor base address).
The descriptor list is Chain structure.
3. B uff er Mana ge me nt - - C ha in S tr uct ure Me th od
As the Chain structure depicted below, each descriptor
contains two pointers, one point t o a single buffer and the
other to the next descriptor chained. The first descriptor is
chained to the last descriptor under hos t driver’s control.
With th is structure, a des criptor can be a llocated anyw here
in h o st m emor y and i s ch ained to th e n ext de scri pt or.
Buffer 1
Buffer 1
Descriptor 1
Descriptor N
Packet N
control
buffer address 1
status
own
not valid
next descriptor address
buffer 1 length
4. Descriptor List: Buffer Descriptor Format
(a). Receive Descri ptor Format
Each receive descriptor has four double-word entries and
may be read or written by the host or the DM9102A. The descriptor format is s hown below with a detailed functional
description.
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31 0
OWN
Status
Control bits
Buffer Address
Next Descriptor Address
RDES0
RDES1
RDES2
RDES3
Buffer Length
OWN
Receive Descriptor Format
RDES0:
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Frame Length ( FL )
AUN
OWN: Owner bit of received status
1=owned by DM9102, 0=owned by ho st
This b it s hould b e reset after pa cket reception is c ompleted.
The host will set this bit after received data is removed.
AUN: Received a ddress unmatched.
FL: Frame Length
Fra me length indicating total byte count o f received p acket.
151413121110 9 8 7 6 5 4 3 2 1 0
ES RF CE
MFDUE LBOM BD ED TLF LCS FT RWT PLE AE FOE
EFL
This w ord-wide content includes status of received frame.
They are loaded a fter the recei ved bu ffer that belongs to the
corresponding descriptor is full. All status bits are valid only
when the last descriptor (End Descriptor) bit is set.
Bit 15: ES, Error Summary
It is s e t for the f ollo win g error c onditions:
Descriptor Una vailable Error (DUE =1), Runt Frame
(RF =1), Exces sive Fra me Lengt h (EF L=1), Late Collision
Seen (LCS=1), CRC error (CE=1), FIFO Overflow error
(FOE=1). Valid only when ED is set.
Bit 14: DUE, Descriptor U navailab le Err or
It is set w hen the frame is truncated due to t h e b u f f e r
una va ilable. I t is vali d only when ED is set.
Bit 13,12: LBOM, Loopback Operation Mode
These two bits show the received frame is derived from:
00 --- nor mal operation
01 --- internal loopback
10 --- PHY loopback
11 --- externa l loopback
Bit 11: RF, Runt Frame
It is se t to in dic ate th e rec eived frame has the size smaller
than 64 bytes. It is val id o n l y when E D is s e t and FOE is
reset.
Bit 10: MF, Multicast Frame
It is se t to in dic ate th e rec eived frame has a multicast
address. It is valid only w hen ED is s et.
Bit 9: BD, Begin Descriptor
This bit is set for the descriptor indicating start of a received
frame.
Bit 8: ED, Ending Descriptor
This bit is set for descriptor to indicate end of a received
frame.
Bit 7: EFL, Excessive Frame Length
It is se t to in dic ate th e rec eived frame length exceeds 1518
bytes . Valid onl y when ED is set.
Bit 6 : LC S: La te Coll isi on Se e n
It is s e t t o i n dic at e a l at e c o llision found during the frame
reception. Valid only when ED is s et.
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Bit 5: FT, Frame Type
It is se t to in dic ate th e rec eived frame is the Ethernet-type. It
is reset to indicate the received frame is the EEE802.3- type.
Valid o nly when ED is set
Bit 4: RW T, Receive Watchdog Time-Out
It is set to indicate receive Watchdog time-out during the
frame reception. CR5<9> will also be set. Valid onl y when
ED is set.
Bit 3: PLE, Physical Layer Err or
It is set to indicate a physical layer error found during the
frame reception.
Bit 2: AE, Alignment Error
It is se t to in dic ate th e rec eived frame ends with a non-byte
boundary.
Bit 1: CE, CRC Error
It is se t to in dic ate th e rec eived frame ends with a CRC
error. Valid only w hen ED is set.
Bit 0: FOE, FIFO Overflow Error
This b it is valid for Ending Des criptor is s et. (ED = 1). It is set
to indicate a FIFO O verflow error happens during the frame
reception.
RDES1: Descriptor Status and Buffer Size
31 30 29 28 27 26 25 24 23 22
21 ~ 11 10 ~ 0
CE Buffer Length
Bit 24: CE, Chain Enable
Must be 1. Bit 10-0: B uffer Length
Indicates the size of the buffer.
RDES2: B uffer Start ing A ddress
Indicates the physical starting address of b uffer. This address must be double w ord alig nment.
31 0
Buffer Address
IRDES3: Next descriptor Address
Indicates the physical starting address of the chained descriptor under the Chain des cripto r structure.
This address must be eight w ord alignment.
31 0
Next descriptor Address
(b). Transmit Descriptor Format
Each transmit descriptor has four double-word content
and may be read or written by the host or by the DM9102A. The descriptor format is shown below with detailed
description
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31 0
OWN
Status
Control bits
Buffer Address
Next Descriptor Address
TDES0
TDES1
TDES2
TDES3
Buffer Length
OWN
Transmit Descriptor Format
TDES 0: Ow ner Bit with Tra nsmi t S tatus
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OWN
Bit 31: OWN ,
1=owned by DM9102A, 0=owned by h ost, this bit should be
set when the transmitting buffer is filled with data and ready
to be transmitted. It will be reset by DM9102A after
transmitting the whole data buffer.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ES
EC 0 CC
TX
JT LOC NC LC 0 FUE DF
This w ord wide content includes status of transmitted frame.
They are loaded after the data buffer that belongs to the
corresponding descriptor is tran smitted.
Bit 15: ES, Error Summary
It is s e t for the f ollo win g error c onditions:
Transmit Jabber Time-out (TXJ T=1), Los s of Carrier
(LOC =1), No C arrier (NC =1), La te C ollision (LC =1),
Excessive Collision (EC =1), FIFO Underrun Error (FUE=1).
Bit 14: TXJT, Transmit Jab ber Time Out
It is se t to in dic ate th e tran smi tted fr ame is truncated due to
transmit jabber time o ut co ndition. The transmit jabber time
ou t inter rup t C R5 <3 > is se t.
Bit 11: LOC, Loss of Carrier
It is se t to in dic ate th e lo s s of c ar rier during the frame
tra n s m is s io n . I t is not valid in internal loopback mode.
Bit 10: NC, No Carrier
It is se t to in dic ate th at n o car rie r signal from tra n sceiver i s
found. It is not valid in i nternal loopback mode.
Bit 9: LC , Late C oll isi on
It is s e t t o i n dic at e a c ollisi o n o cc ur s af te r t he c ollisi o n
window of 64 b ytes. Not valid if FUE is s et.
Bit 8: EC, Excessive collision
It is s et t o indic ate th e tran s mission is aborted due to 16
excessive collisions.
Bit 7: Reserved
This b it is 0 when read.
Bits 6-3: CC, Collision Count
These bits sho w the number of collision before
tran s miss ion . No t va lid if e xc es s ive co llis ion bi t is a ls o s e t.
Bit 2: Reserved
This b it is 0 when read.
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Bit 1: FUE, F IFO Underru n Error
It is s et t o in di cate th e tran s mission aborted due to transmit
FIFO underrun condition.
Bit 0: DF, Deferred
It is s e t to in dicate th e frame is d eferred before ready to
transmit.
TDES1: Transmit buffer control and buffer size
31 30 29 28 27 26 25 24 23 22 21 ~ 11 10 ~ 0
CI ED BD FMB1 SETF CAD /// CE PD FMB0
Buffer Length
Bit 31: C I, C om ple tio n Inte rr upt
It is s et to enable transmit interr up t after the prese nt frame
has been transmitted. It is valid only when TDES1<30> is
set or when it is a setup frame.
Bit 30: ED, Ending Descriptor
It is se t to in dic ate the pointed buffer contains the l ast
segment of a frame.
Bit 29: BD, Begin Descri ptor
It is se t to in dic ate the pointed buffer contains the first
segment of a frame.
Bit 28: FMB1, Filtering Mode Bit 1
This bit is used with FMB0 to indicate the filtering type when
the present frame is a setup frame.
Bit 27: SETF, Setup Frame
It is se t to in dic ate th e current frame i s a setup frame.
Bit 26: CAD, CRC A ppend Disable
It is set to disable the CR C appending at the end of the
transmitted frame. Valid only w hen TDES1<29> is set.
Bit 24: CE, Chain Enable
Mus t be “1” .
Bit 23: PD, Padding Disa ble
This b it is s et to disable the padding field for a packet shorter
than 64 bytes.
Bit 22: FMB0, Filtering Mode Bit 0
This bit is used with FMB1 to indicate the filtering type when
the present frame is a setup frame.
FMB1 FMB0 Filtering Type
0 0 Perfect Filtering
0 1 Hash Filtering
1 0 Inverse Filtering
1 1 Hash-Only Filtering.
Bit 10 -0: B uffer 1 length
Indicates the size o f buffer in Chain type structure.
TDES2: Buffer Starting Address indicates the physical starting address of buffer.
31 0
Buffer Address 1
TDES3: Address indicates the next descriptor starting address
Indicates the physical starting address of the chained descriptor under the Chain des cripto r structure.
This address must be eight w ord alignment.
31 0
Buffer Address 2
Initialization Procedure After hardware or s oftware reset, tr a n smi t and receive
processes are placed in the state of STOP. The DM9102A
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can accept the host commands to start operation. The
general procedure for initialization is described below:
(1) Read/write suitable values for the PCI configuration
registers.
(2) Write CR3 and CR4 to provide the starting address of
each descriptor list.
(3) Write CR0 to s et global hos t bus operat ion parameter s.
(4) Write CR7 to mask causes of unnecessary interrupt.
(5) Write CR6 to s et global parameters and start both
receive and transmit process es. Receive and transmit
processes will enter the running state and attempt to acquire
descriptors from the respective descriptor lists.
(6) Wait for any interrupt.
Data Buffer Processing Algorithm
The data buffer process algorithm is based on t he
cooperation o f the host and the DM9102A. The host sets
CR3 (receive descriptor base address) and CR4 (transmit
descriptor base address) for the descriptor list initialization.
The DM9102A w ill start the data b uffer transfer after the
descriptor polling and get the ownership. For detailed
processing procedure, please see below.
1. Receive Data Buffer Processing
The DM9102A a lways attempts to acqu ire a n extra
descriptor in anticipation o f the incoming frames. Any
incoming frame s ize co vers a few buffer reg ions and
descriptors. The following conditions satisfy the descriptor
acquisition at tempt:
When start/stop receive sets immediately after being placed
in the running state.
When the DM9102A begins writing frame data to a data
buffer pointed to by the current descriptor and the b uffer
ends before the frame ends.
When the DM9102A completes the reception of a frame
and the current receiving de scriptor is closed.
When receive process is sus pended due to no free b uffer for
the DM9102A and a new frame is received.
When receive po lling demand is iss ued. After acquiring the
free descriptor, the DM9102A processes the incoming frame
and places it in the acquired descriptor's data buffer. When
whole the received frame data has been tran sferred, the
DM9102A will w rite the status information to the last
descriptor. The same process will repea t until it enco u nters a
descriptor flagged as being owned by the ho st . If th is occurs,
receive process enters the suspended state and waits th e
host to ser vice.
Stop
State
Descriptor
Access
Datat
Transfer Write
Status
Suspended
Start Receive Command Or
Receive Poll Command
Buffer Available
( OWN bit = 1 )
FIFO Threshold
Reached
Frame Fully
Received
Buffer not
Full
Receive Buffer
Unavailable
New Frame Coming Or
Receive Poll Command
Stop Receive Command or
Reset Command
Buffer Full
Receive Buffer Management State Tr a nsiti on
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2. Transmit Data Buffer Processing
When start/stop transmit command is set and the DM9102A
is in runn ing s tate, transmit process polls tran smit d escriptor
list for frames requiring transmission. When it completes a
frame trans mission, the status related to the transmitted
fra me w i ll be w rit ten into th e tran s mit d es crip tor. If the
DM9102A detects a descriptor flagged as owned by the
host and no tra n smit b uffers are a vailabl e, transmi t pr oc es s
will be suspended. While in the running state, transmit
process can simultaneously acquire two frames. As trans mit
process completes copying the first frame, i t immediately
polls transmit descriptor list for the s econd frame. If the
second frame is valid, transmit process copies the frame
before writing the status information of the first frame.
Both conditions w ill make t ransmit process suspend. (i) The
DM9102A detects a d escriptor owned by the h os t. (ii) A
frame trans mission is aborted when a loc ally induced error is
detected. Under e ither condition, the host driver has to
service the condition before the DM9102A can resume.
Stop State
Descriptor
Access
Data
Transfer Write
Status
Suspended
Buffer Available
( OWN bit = 1 )
Frame Fully Transmited
Start Transmit Command Or
Transmit Poll Command
Under FIFO Threshold
Buffer not Empty
Buffer Empty
Transmit Buffer Unavailable
( Owned By Host )
Transmit Poll Command
Stop Transmit Command Or
Reset Command
Transmit Buffer Management State T ra n sitio n
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Networ k Function
1. Overview
This chapter will introduce the normal state machine
operation and MAC layer management like collision ba ckoff
algorithm. In tran smit mode, the DM9102A initiates a DM A
cycle to access data from a tra n smit b uffe r. I t p refa ce s the
data with the preamble, the SFD pattern, and it appends a
32-bit CRC. In receive mode, the data is de-serialized by
receive mechanism and fed into the internal FIFO. For
detailed process, please see below.
2. Receive Process an d State Machine
a. Reception Initiation
As a preamble being detected on receive data lines, the
DM9102A synchronizes itself to the d ata stream during the
preamble and waits for the S FD. The synchronization
process is based on byte boundary and the SFD byte is
10101011. If the DM9102A rece ives a 0 0 or a 11 after the
fi rs t 8 p r e am ble bit s and before receiving the SFD, the
reception proces s will be te rminated.
b. Address Recognition
After initial synchronization, the DM9102A will recognize the
6-byte destination address field. The first bi t of the
destination address signifies whether it is a p h ysical address
(=0) or a multicast address (=1). The DM9102A filters the
frame based on the node address of r eceive address filter
setting. If the frame passes the filter, the subsequent serial
data will be delivered into the host memory.
c. Frame Decapsulation
The DM9102A checks the CRC bytes of a ll received frames
before releasing the frame along with the CRC to the ho st
processor.
3. Transmit Pr ocess a nd State Machine
a. Tra nsm iss io n I nitia t ion
Once the host processor prepares a transmit descriptor for
the transmit bu ffer, the hos t processor s ignals the D M9102A
to take it. After the DM9102A has been notified of t his
transmit list, the DM9102A will start to move the data bytes
from the h ost memory to th e internal tra n smit FIFO. When
the transmit
FIFO is adequately filled to the programmed threshold level,
or when there is a full frame buffered into the trans mit FIFO,
the DM9102A begins to encapsulate the frame. The
transmit encapsulation is performed by the transmit state
ma ch in e , w h ich d e lay s t he a ct u al tr a n smission onto the
network until the network has been idle for a minimum inter
frame gap time.
b. Fr ame Enca psulation
The transmit data frame encapsulation stream consists of
tw o parts: Basic frame beginning and basic frame end. The
former contains 56 preamble bits and SFD, the later, FCS.
The basic frame rea d from the host memory includes the
destination address, the source address, the type/length
field, and the data fiel d. I f the da t a f ie ld is l e ss than 46 bytes,
the DM9102A will pad the frame with pattern up to 46 bytes.
c. C ol lisi on
When concurrent transmissions from two or more nodes
occur (termed; collision), the DM9102A halts the
transmission of data bytes and be gins a jam pattern
consisting o f AAAAAAAA . At the end o f the jam
transmission, it begins the ba ckoff wait time. If t he collision
was detected du ring the preamble transmission, the jam
pattern is transmitted a fter completing the preamble. The
backoff process is called truncated b inary e xponential
ba cko ff. The d ela y i s a random integer mu ltiple of slot times.
The number of slot times of delay before the Nth
retransmission attempt is chosen as a un iformly distributed
random integer in the range:
0 ≤ r < 2k
k = min ( n , N ) and N =10
4. Physical Layer Overview:
The DM9102A provides 100M/10Mbps dua l port operation.
It pro vides a direct interface either to Unshielded T wi st ed
pair Cab le U TP5 for 100BA SE-TX Fast Ethernet, or
UTP5/UTP3 Cable for 10BASE-T Ethernet. In physical level
operation, it cons ists o f the following blocks:
Ƒ
PCS
Ƒ
Clock genera tor
Ƒ
NRE/NREI, MLT-3 encoder/decoder and d river
Ƒ
MANCHESTER encoder/decoder
Ƒ
10BASE-T filter and driver
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Serial Management Interface
The serial management interface uses a simple, two-wired
serial interface to obtain an d control the status of PHY
managemen t register set through an MDC and M DIO. The
Management Data C lock (MDC) is equipped w ith a
maximum c lock rate o f 2.5MHz, w hile Management Data
Input /Outpu t (M DI O) wo rk s a s a b i-directional, shar ed by up
to 32 devices.
In read/write operation, the managem ent data frame is 64-
bit long start with 32 contiguous logic one bits (preamble)
synchronization clock cy cles on MDC. The Start of Frame
Delimiter (SFD) is indicated by a <01> pattern followed by
the operation code (OP):<10> indicates Read operati on and
<01> indicates Write oper ation. For read operation, a 2-bit
turnaround (TA) filing between Resistor Address fiel d and
Data field is provided for MDIO to avoid contention. “Z”
stands for the state o f high impedance. Following
turnaround time, a 16-bit data is read from or written o n to
management registers.
Management Interface - Read Frame Structure
32 "1"s 0110A4A3A0R4R3R0
Z0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Read
Write
MDC
MDIO Read D15 D14 D1 D0
// //
Management Interface - Write Frame Structure
32 "1"s 0 1 10 A4 A3 A0 R4 R3 R0 1 0 D15 D14 D1 D0
Idle Preamble SFD Op Code PHY Address Register Address Turn Around Data Idle
Write
MDC
MDIO Write
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Power Management
1. Overview
The DM9102A supports pow er management mechanis m. It
complies w ith the ACPI Specification Re v 1.0, the N etwork
Device C lass Power Management Sp ecification R ev 1.0,
and PCI Bus Power Management Interface Specification
Rev 1.0. I n add ition, it al s o support Wa k e - On L AN (W OL)
which is the features of the AMD’s Magic Packet™
technology. With this function, it can wake-up a remote
sleeping station.
2. PC I Fu nct ion Po wer Ma na gem en t S tate s
The DM9102A supports PCI function pow er states D0,
D3(hot), D3(cold), and not supports D1, D2 states.
Additional PCI signal PME# (power management event,
open drain) to pin A19 of the standard PCI connector.
D0: norma l & fully functional state
D3(ho t) : For controller, configuration space can be
a c c e s s e d and w a k e - u p o n L A N c i r c uit c a n b e enabled.
PME# operational circuit is active, full function is supported
to detect the wake-up F rame & Link status. Because of
functions in D3(hot) must respond to configuration space
access es as long as power and clock are supplied so that
they can be returned to D0 state by software.
D3 (col d) : I f Vc c i s removed from a PCI device, all of its PCI
functions transition immediately to D3(cold), no bus
transaction is ac tive under no pci_clk cond it ion a n d wake-up
on LAN operation should be alive. PME# operational ci r cuit
is active. Full function is s upported under a uxiliary power to
detect the wake-up Frame & Link status. When power
restored, PCI RST# must be asserted and function s will
return to D0 with a full PCI Spec. 2.2 compliant pow er-on
reset sequence. The power required in D3( cold) must be
provided by so me auxiliary power source.
3. The P owe r Mana ge me nt O per ati on
It co mplies with the PCI Bus Power Manageme nt Interface
Specification Rev. 1.0. The Power Management Event
(PME#) signal is an optional open drain, active low signal
that is intended to be driven low by a PCI function to request
a change in its cu rrent pow er management state and/or to
indicate that a power management event has occurred.
The PME# signal has been assigned to pin A19 of the
standard PCI Connector configuration. The assertion and
de-assertion of PME# is as ynchronous to the PC I clock.
Software w ill enable its use by setting the PME_En bit in t h e
PMCSR (write 1 to PMCSR<8>). When a PCI function
generates or detects an event that requires the s ystem to
change its power state, the function will assert PME#. It
must continue to assert PME# until software either clears
the PME_En bit (PMCSR<8> is set to 0) or clears the
PME _S tatu s b it in th e PMC SR (w r ite 1 to PMC SR <15 >) .
DM9102A support three main categories of network device
w ake-up e vents specified in Netw ork Device Class Power
Management Rev1.0. That is, the DM9102A can monitor
the network for a Link Change, Magic Packet or a Wake-up
Fra me and n otify th e sy st em by generating PME# if any of
three events oc curs. Program the PCIUSR (offse t = 40h)
can select the PME# event, and w rite 1 to PMCSR<15> will
clear the PME#.
a. Detect Network Link State Change
Any link status change w ill s et the w ake-up e vent.
1. Writes 1 into P MCSR<15>(54h) to clear previous PME#
status
2. Writes 1 into P MCSR<8> to enable P ME# function
3. Wri tes 1 in to PC IUSR<29 > to enable th e l i nk status
change function
b. Active Magic Packet Function
Co uld b e o ptional ly enabled from EEPROM contents. Send
a setup frame with a magic node address at first filter
address using perfect address filtering mode.
1. Writes 1 into PMCSR <15> to c lear pre vious P ME status
2. Writes 1 into PMCSR <8> to enable PM E# function
3. Writes 1 into PCIUSR<27> to enable magic packet
function.
c. Active the Sample Frame Function
Co uld b e o ptional ly enabled from PCIUSR<28>. Sample
frame data and corresponding byte mask are loaded into
transmit FIFO & receive FIFO before e ntering D3(h ot). The
software driver has to stop the TX/RX process before setting
the sample frame and byte mask into the FIFO. Tran smit &
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59
receive FIFO can be accessed from CR13 & CR14 by
programming CR6<28:25> = 0011.
The operation al sequence from D0 t o D3 should be:
Stop TX/RX process
wait for entering stop stat e
set
test mode, CR6 <28:25> = 0011
programming FIFO
contents
e xit tes t mode
enter D3(hot) s tate
The sample frame data comparison is completed when the
received frame data has exceeded the programmed frame
length or the full packet has been fully rece ived. The
operation procedure is s hown below.
DM9102A can handle 8 sample frames.
The max byte count is 256 byte each
sample frame.
Frame0
data0
Frame1
data0
Frame2
data0
Frame3
data0 0
4
508
bytebyte byte byte
0781516232431
252
256
Frame0
Mask 0
Frame1
Mask 0
Frame2
Mask 0
Frame3
Mask 0 0
4
bytebyte byte byte
0781516232431
508
TX FIFO 2K by t e = 8 * 256
bit1 bit0 description
00
01
10
1 1 end of mask(sample frame)
this byte musk check
this byte don’t care
this byte don’t care
Frame mask definition: only used bit0&bit1
mask_data mapping
Frame4
data0
Frame5
data0
Frame6
data0
Frame7
data0
260 260
256
252
Frame4
Mask 0
Frame5
Mask 0
Frame6
Mask 0
Frame7
Mask 0
RX FIFO 2K byte= 8 * 256
data1data1data1data1
data1data1data1data1 Mask 1 Mask 1
Mask 1 Mask 1
Mask 1 Mask 1
Mask 1 Mask 1
CR13 : Sample Frame Access Register
Name General definition Bit8:3 Type
TxFIFO Transmit FIFO access port 32h R/W
RxFIFO Receive FIFO access port 35h RW
DiagReset General reset for diagnostic pointer port 38h R W
In DiagReset port there are 7 bits:
Bit 0: clear TX FIFO write_address to 0.
Bit 1: clear TX FIFO read_address to 0 .,
Bit 2: clear RX FIFO write_address to 0.
Bit 3: clear RX FIFO read_address to 0.,
Bit 4 : r es er ved.
Bit 5: set TX FIFO w rite_address to 100H.,
Bit 6: set RX FIFO write_address to 100H.
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Sample Frame Pr ogramming Guide:
1. Enter the sample frame access mode
Let CR6<28:25>=0011
2.Reset the TX/RX FIFO, write p ointer to offset 0
Write 38h to CR13<8:3>
Write 01h to CR14 (reset)
Write 00h to CR14 (clear)
3. Write the s a mp le fra me 0-3 data t o RX FIFO
Write 35h to CR13<8:3>
Write xxxx xxxxh to CR14 (Fra me1~3 firs t byte)
Write xxxxxxxxh to CR14 (Fra me1~3 second b yte)
:
:
Repeat write until all frame data written to RX FIFO
4. RESET RX FIFO, write pointer to offset 100h
Write 38h to CR13<8:3>
Write 40h to CR14 (reset)
Write 00h to CR14 (clear)
5. Write the sa mple frame 4-7 to RX FIFO
Write 35h to CR13<8:3>
Write xxxx xxxxh to CR14 (Fra me4~7 firs t byte)
Write xxxxxxxxh to CR14 (Fra me4~7 second b yte)
:
:
Repeat write until all frame data written to RX FIFO
6. Write the sa mple frame 0-3 mask to TX FIFO
Write 32h to CR13<8:3>
Write xxxx xxxxh to CR14 (Fra me0~3 firs t mask byte)
Write xxxxxxxxh to CR14 (Frame0~3 second mask byte)
:
:
Repeat write until all frame mask which is written to TX
FIFO
7. RESET TX FIFO, write pointer to o ffset 100h
Write 38h to CR13<8:3>
Write 20h to CR14 (reset)
Write 00h to CR14 (clear)
8. Write the sa mple frame 4-7 mask to TX FIFO
Write 32h to CR13<8:3>
Write xxxx xxxxh to CR14 (Fra me4~7 firs t mask byte)
Write xxxxxxxxh to CR14 (Frame4~7 second mask byte)
:
:
Repeat write until all frame mask which is written to TX
FIFO
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Ser ial ROM Overv iew
The purpose of Configuration ROM (EE PROM) is to support
the DM9102A information to the driver for the card. The SROM must support 64 w ords or more space for
con figura tio n data. The format of the SROM is as followed
The format of EEPROM
Field Name Offset Size
Subsystem ID block 0 18
CROM version 18 1
Controller count 19 1
Controller_0 Information 20 n
Controller_1 Information 20+n m
: (depends on controller count) : :
CRC checksum 126 2
1. Subsystem ID Block
Every card must have a Subsystem ID to indicate the
system vendor information. The content will be transferred
into the PCI configuration space during hardware reset
function.
Vendor ID & Device ID can be s et in EEPR OM con tent &
auto-loaded to PCI configuration register after reset.(default
value = 1282, 9102) This function must be selectable for
enable/disable by Auto_Load_Control (offset 0 8 of
EEPROM) setting to avoid damaging default value due to
incorrect ly auto-load oper atio n. C RC check circuit of
EEPROM contents to decide the auto-l oad operation of
Vendor ID & Subsystem.
Subsystem Vendor ID
Subsystem ID
Reserved
Reserved
ID_block_CRC
PMCPMCSR
Reserved
PCI Device ID
PCI Vender ID
NCE
Auto_load_control
0
2
4
6
8
10
12
14
17,16
Byte Offset.
Subsystem ID Block
By te Of fset (08 ): Auto_ Load_Control
0347
Bit3~0: “1010” to enable auto-load of PCI Vendor_ID &
Device_ID, “0” to d isable.
Bit7~4: “1X1X” to enable a uto-load of NCE, PME & PMC &
PMCSR to PCI configuration space. These four bits can
also control the inverse of WOL or PULSE WOL..
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If bit4 = 0, WOL is Active HIGH.
If bit4 =1 , WOL is A c ti ve L O W
If bit6 = 0, WOL is PULSE signal
If bit6=1, WOL is DC L EVEL signal.
Byte Offset (09): New_Capabilities_Enable
017
Bit0: Directly mapping to bit20 (New Capabilities) o f the
PCICS
Byte Offset ( 14 ): PMC
07 32
Bit7~3: Directly mapping to b it15~11 of PMC (that is
bit31~27 of Power Management Register)
Bit2~0: Directly mapping to b it5~3 of PMC (that is bit21~19
of Power Management Register)
Byte Offset (15):
0347
Bi t7~4 : Re s er ved
Bit3: Set to disable the output of PME# pin.
Bit2: Set to disable the output of WOL pin.
Bit1: Set to enable the link change w ake u p event.
Bit0: Set to enable the Magic packet wake up event.
Byte Offset (16): ID_BLOCK_CRC
07
This field is implemented to confirm the correct reading of
the EEPROM contents.
2. SR OM Ve rs io n
Current version n umber is 03.
3. Controller C ount
The configurat ion R OM s upports multiple controllers in one
board. Every controller has its unique controller information
block. Controller count indicates the nu mber o f controllers
put in the card.
4. Controller_X Informati on
Each controller has its information b lock to address its node
ID, GPR control, supported connect media types (Media
Information Block) and other application c ircuit information
block.
Controller Information Header
ITEM Offset Size
Node Address 0 6
Controller_x Number 6 1
Controller_x Info. Block Offset 7 1
5. Controller Information Body Pointed By C ontroller_X
Info Bl ock Offset Item I n Co ntroller I nformation Header:
Item Offset Size
Connection Type Se lected 0 2
GPR C ont rol 2 1
Bloc k Count 3 1
Block_1 4 n
: 4+n m
* Connect Type Se lected ind icates the default connect
media type selected.
* GPR Control defines the input or output direction o f GPR.
There are three types of block:
1. PHY Information Block (type=01)
2. Media Information B lock (type=00)
3. Delay Period Block (type=80)
PHY information Block: (type=01)
Item Offset Size
Block Length 0 1
Block Type(01) 1 1
PHY Nu mber 2 1
GPR Initial Length(G_i) 3 1
GPR In it ial Da ta 4 G_i
Reset Sequence Length(R_i) 4+G_i 1
Re se t Da ta 5+G_ i R_i
Media Capabilities 5+G_i+R_i 2
Nway Ad vertisement 7+G_i+R_i 2
FDX Bit Map 9+G_i+R_i 2
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TTM B it Map 11+G_ i+R_i 2
Note 1: Th e definitio n of Medi a Capabilities and N way
Advertisement is the same w ith 802.3U in terms o f Auto-
negotiation.
Media Information Block: ( Type = 00)
ITEM Offset Size
Block Length 0 1
Block Type(00) 1 1
Media Code 2 1
GPR D ata 3 1
Command 4 2
Note 1: Media Cod e: 10BASE _T Half Duplex 00
10 BASE_T Full Duplex 04
100 BASE_T Half Duplex 01
100 BASE_T Full Duplex 05
Note 2: Command Format
Delay Period Block (Type = 80): Define the delay time unit
in u s.
ITEM Offset Size
Block Length 0 1
Block Type(80) 1 1
Time Unit 2 2
6. Example o f DM9102A SROM Format
Total Size: 128 Bytes
Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
Sub-Vendor ID 0 2 1282 ID Block
Sub-Device ID 2 2 9102
Reserved1 4 4 00000000
Auto_Load_Control 8 1 00 Auto-load function definition:
Bit 3~0 = 1010
Auto-Load PCI
Vendor ID/De vice ID enabled
Bit 7~4 = 1x1x
Auto-Load NCE,
PMC/PMCSR enabled
New_Capabilities_Enable
(NCE) 9 1 00 Please re fer to DM9102A Spec.
PCI Vendor ID 10 2 1282
PCI Device ID 12 2 9102 If Auto-Load PCI Vendor ID/Device
ID function disabled, the PCI
Vendor ID/Device ID will use the
default values (1282h, 9102h).
Power Manageme nt
Capabilities (PMC) 14 1 00 Please re fer to DM9102A Spec.
Power Manageme nt
Control/Status (PMCSR) 15 1 00 Please re fer to DM9102A Spec.
ID_BLOCK_CRC 16 1 - Offset 0..15, 17 ID CRC
Reserved2 17 1 00
Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
SROM Fo rmat Version 18 1 03 Version 3.0
Controller Count 19 1 01
IEEE Network Address 20 6 - Controller Info Header
Controller_0 De vice Nu mber 26 1 00
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Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
Controller_0 In fo Leaf Offset 27 2 001E O ffset 30
Reserved3 29 1 00
Selected Connec ted Type 30 2 0800 Controller_0 Info Lea f Block
General Purpose Control 32 1 80 MAC CR12 Register
Bloc k Count 3 3 1 06 6 B locks
F(1)+Length 34 1 8E Block 1 (PHY Info Block)
Type 35 1 01 PHY Information Block
PHY Number 36 1 01 PHY Addres s
GPR Length 37 1 00
Reset Sequence Length 38 1 02
Reset Sequence 39 2 0080
Media Capabilities 41 2 7800
Nway Ad vertisement 43 2 01E0
FDX Bit Map 45 2 5000
TTM Bit Map 47 2 1800
F(1)+Length 49 1 85 Block 2 (Delay Period Block)
Type 50 1 80 Delay Period Block
Delay Sequence 51 4 40002000 Micro-Second
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Field Name Offset
(Bytes) Size (Bytes) Value
(Hex) Commentary
F(1)+Length 55 1 85 Block 3 (Media Info Block)
Type 56 1 00 Media Information Block
Media Code 57 1 00 10Base-T Half_Duplex
GPR Data 58 1 00
Command 59 2 0087
F(1)+Length 61 1 85 Block 4 (Media Info Block)
Type 62 1 00 Media Information Block
Media Code 63 1 01 100Base-TX Half_Duplex
GPR Data 64 1 00
Command 65 2 0087
F(1)+Length 67 1 85 Block 5 (Media Info Block)
Type 68 1 00 Media Information Block
Media Code 69 1 04 10Base-T Full_Duplex
GPR Data 70 1 00
Command 71 2 0087
F(1)+Length 73 1 85 Block 6 (Media Info Block)
Type 74 1 00 Media Information Block
Media Code 75 1 05 100Base-TX Full_Duplex
GPR Data 76 1 00
Command 77 2 0087
SROM_CRC 126 2 - Offset 0..125 SROM CRC
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Exter nal M II/S RL In terface
DM9102A provides one external MII/SRL interface sharing
w ith a ll the p ins w ith Boo t R OM in ter fac e. This e xter nal
MII/SRL interface can be connected with external PHYceiver
such a s Home Net working PHYceiver or other future
technology applications. This e xternal MII/SRL interface can
be set up by hardware and software. The setup methods are
listed as below:
Test 1 (pin 75) Test 2 (pin 71) Clkrun# (pin 36) MA 8 (pin 84) MA 9 (pin 85)
Normal Operation 01 X XX
External MII mode 00 0 01/0
Note 1
External SRL mode 00 0 11/0
Note 2
Internal Test mode 1X X X X
Note 1: Externa l MII mode
MA9 = 1 (Set up by harw are; Mode cannot be changed.)
MA9 = 0 & MII_Mode = 1 (Select e xternal MII interface; Mode can be changed by so ftware.)
Where MII_Mode is the bit 18 o f CR6.
Note 2: External MII mode:
MA9 = 1 (Set up by harware; Mode cannot be changed.)
MA9 = 0 & MII_Mode = 0 (Select e xternal SRL interface; Mode can be changed by software.)
The Sharing Pin Table (o): output, (i): input, (b): bi-direction
Normal Operation External MII/SRL Interface
Boot ROM Mux mode Boot ROM Dir mode External MII interface External SRL interface
MA6 = 0 MA6 = 1 MA8 = 0 MA8 = 1
Pin
62 BPAD0 MD0/DI MII_ TXD 3 (o) BPAD0
63 BPAD1 MD1 MII_TX D2 (o) BPAD1
64 BPAD2 MD2 MII_TX D1 (o) BPAD2
65 BPAD3 MD3 MII_RXER (i) BPAD3
66 BPAD4 MD4 MII_RXD V (i) BPAD4
67 BPAD5 MD5 MII_RXD1 (i) BPAD5
68 BPAD6 MD6 MII_RXD2 (i) BPAD6
69 BPAD7 MD7 MII_MDI O (b) BPAD 7
72 BPCS# ROMCS MII_MD C (o) BPCS#
73 BPA0 MA0 NC BPA0
74 BPA1 MA1 MII_RXD (i) BPA1
77 EEDI MA2 EEDI (i) EEDI (i)
78 EEDO MA3/D O EEDO (o) EEDO (o)
79 EECK MA4/CK EEC K (o) EEC K (o)
80 EECS MA5 EECS (o) EECS (o)
81 MA6 MII_COL (i) SRL_COL (i)
83 MA7 MII_TXCLK (i) SRL_TXC (i)
84 MA8 MII_TX EN (o) SRL_TX E (o)
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85 MA9 MII_TXD0 (o) SRL_TXD (o)
87 TRFLED MA10/TRF NC NC
88 FDXLED MA11/FDX OSC20 (o) OSC20 (o)
89 SPD100 MA12/100 Link (i) Link (i)
90 SPD10 MA13/10 NC NC
91 MA14 MII_CRS (i) SRL_CRS (i)
92 MA15 MII_RXCLK (i) SRL_RXC (i)
93 MA16 MII_RXD0 (i) SRL_RXD (i)
94 MA17 MA17 NC NC
Where NC is no connection
Pin88 is 20MHz clock ou tput for e xternal PHY (such as DM9801)
Pin89 is link s tatus input from external PHY for power management changed event and r eflec t a t CR 12 bit6.
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A bsolute Maxim um Ratin gs
Absolute Max imum Rat ings* ( 25°
°°
°C )
Symbol Parameter Min. Max. Unit Conditions
DVCC,AVCC Supply Vo ltage -0.3 3.6 V
VIN DC Input Voltage (VIN) -0.5 5.5 V
VOUT DC Output Voltage(VOUT) -0.3 3.6 V
Tc Case Temperature Range 0 85 °C
Tstg Storage Temperature Rang (Tstg) -65 150 °C
LT Lead Temp. (TL, Soldering, 10 sec.) --- 220 °C
Oper at ing C o nd itio ns
Symbol Parameter Min. Max. Unit Conditions
DVCC,AVCC Supply Voltage 3.135 3.465 V
Tc Case Temperature 0 85 °C
100BASE-TX --- 115 mA 3.3V
100BASE-T X IDLE --- 115 mA 3.3V
10BASE-T TX --- 125 mA 3.3V
10BASE-T IDLE --- 45 mA 3.3V
PD
(Power
Dissipation)
Auto-negotiation --- 76 mA 3.3V
Comments
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only. Functional operation of this
device at these or any other c onditions above those indic ated
in the operational sections of this specification is not implied.
Exposure to absolute maximu m rating conditions for extended
periods may affect device reliability.
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DC Electrical Characteristics
(0°C<Tc<85°C, 3.135V<VCC<3.465V, unless otherwise noted)
Symbol Parameter Min. Typ. Max. Unit Conditions
Inputs
VIL Input Low Voltage - - - -- - 0.8 V
VIH Input High Voltage 2. 0 --- --- V
IIL Input Low Leakage Current -- - -- - 5 uA V IN = 0V
IIH Input High Leakage Current 5 --- - - - uA V IN = 3.3V
Outputs
VOL Out put Low Voltage -- - -- - 0.4 V IOL = 4mA
VOH Out put High Voltage 2.4 - - - --- V IOH = -4mA
Receiver
VICM RX+/RX- Common mode Input
Voltage --- 0.9 --- V 100 Ω Termination
Across
Transmitter
VTD100 100TX+/- Differential Output
Voltage 1.9 2.0 2.1 V Peak to Peak
VTD10 10TX+/- Differential Output
Voltage 4.4 5 5.6 V Peak to Peak
ITD100 100TX+/- Differential Output
Current 19 20 21 mA Absolute Value
ITD10 10TX+/- Differential Output
Current 44 50 56 mA Absolute Value
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A C Electrical C haract eristi cs & Timin g Wavef orms
PCI Clock Specifications Timing
t
HIGH
2.0V
0.8V
t
R
t
F
t
LOW
t
CYCLE
Symbol Parameter Min. Typ. Max. Unit Conditions
tR PCI_CLK rising time - - 4 ns -
tF PCI_CLK falling time - - 4 ns -
tCYCLE Cycle time 25 30 - ns -
tHIGH PCI_CLK High Time 12 - - ns -
tLOW PCI_CLK Low Time 12 - - ns -
Other PCI Sig nals Timing Diagram
t
OFF
t
H
t
SU
Input t
ON
Output
c
LK
2.5V t
VAL
(max) t
VAL
(min)
Symbol Parameter Min. Typ. Max. Unit Conditions
tVAL Cl k-To- Signal V alid Delay 2 - 11 ns Cload = 50 pF
tON Float-To-Active Delay Fro m Clk 2 - - ns -
tOFF Active-To-Fl oat Delay From Clk - - 28 ns -
tSU Input Signal Valid Setup Time Before Clk 7 - - ns -
tH Input Signal Hold Time From Clk 0 - - ns -
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Mu ltiple x M ode Bo ot R OM Tim ing
t
OH
t
EHQZ
t
ELQV
tAVAV
t
ELQX
Address=<7;2>
oe=1,we=0 Address
<15;8> Date<7;0>
Valld
t
ADS
t
ADH
t
ADS
t
ADH
BPAD
<7;0>
BPA1
BPCS#
Address<1>
Address<17> Address<16>
BPA0 Address<0>
Symbol Parameter Min. Type Max. Unit Conditions
tAVAV Read Cycle Time - 31 - PCI clock -
tELQV BPCS# To Output Delay 0 - 7 PCI clock -
tEHQZ BPCS# Rising Edge To Output High
Impedance - 1 - PCI cl ock -
t
OH Output Hold From BPCS# 0 - - PCI clock -
t
ADS Address Setup To Latch Enable High 4 - - PCI clock -
T
ADH Address Hold Fro m Latch Enable High 4 - - PCI clock -
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Dir ect M o de B oot ROM Timing
Frame#
Irdy#
Trdy#
Devsel#
CBEL[3:0]
AD[31:0]
MD[7:0]
MA[17:0]
ROMCS
tCBAD t1ADL t2ADL t3ADL t4ADL
tADTD
tRC
Symbol Parameter Min. Typ. Max. Unit Conditions
tRC Read Cycle Time - 50 - PCI clock -
tCBAD Bus Command to first addr ess delay - 18 - PCI clock -
t1ADL first addr ess length - 8 - PCI clock -
t2ADL second address delay - 8 - PCI clock -
t3ADL third address delay - 8 - PCI clock -
t4ADL fourth address delay - 7 - PCI clock -
tADTD end of address to Tardy active - 1 - PCI clock -
EEPR OM Timi ng
ROMCS
EECK
EEDO
tCSKD
tECKC
tEDSP
tECSC
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
tECKC
Serial ROM clock EECK period
64
-
-
PCI clock
-
tECSC
Read Cycle Time
1792
-
-
PCI clock
-
tCSKD
Delay from ROMCS High to EECK High
28
-
-
PCI clock
-
tEDSP
Setup T i me of EED O to EECK
24
-
-
PCI clock
-
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TP Interface
Symbol Parameter Min. Typ. Max. Unit Conditions
tTR/F 100TX+/- Differential Rise/Fall Time 3.0 --- 5.0 ns
tTM 100TX+/- Differential Rise/Fall Time
Mismatch 0 --- 0.5 ns
tTDC 100TX+/- Differential Output Duty Cycle
Distortion 0 0 0.5 ns
tT/T 100TX+/- Differential Output Peak-to-
Peak Jitter 0 --- 1.4 ns
XOST 100TX+/- Differential Voltage
Overshoot 0 --- 5 %
Oscillator/Crystal Timing
Symbol Parameter Min. Typ. Max. Unit Conditions
tCKC O SC Cy c le T i me 39.996 40 40.004 ns
TPWH OS C P u ls e Wi d t h Hig h 16 20 24 ns
TPWL OSC Pulse Width Low 16 20 24 ns
A uto-negotiatio n an d Fast Link Pulse Timing Parameters
Symbol Parameter Min. Typ. Max. Unit Conditions
t1Cloc k/Data Pulse Width --- 100 -- - ns
t2Clock Pulse To Data Pulse Period 55.5 62.5 69.5 us DATA = 1
t3Clock Pulse To Clock Pulse Period 111 125 139 us
t4FLP Burst Width - 2 - ms
t5FLP Burst To FLP Burst Period 8 16 24 ms
- Clock/ Data Pulses in a Burst 17 33 #
FLP Bursts
t
3
FLP Burst FLP Burst
t
4
t
5
NLPs
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FAST LINK
PULSES
Clock Pulse Data Pulse Clock Pulse
t
1
t
2
t
3
FLP Burst FLP Burst
t
4
t
5
10TX0+/-
t
1
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final
Version: DM9102A-DS-F03
August 28, 20 00
75
Packag e In form ation
QF P 128L Outline Dimension s Unit: Inches/mm
L
L1
Detail F
θ
θθ
θ
Seating Plane
See Detail F
D
y
0.10
See Detail A
A
A2A
1
y
B
e
138
128
103
65
102
D
D1
E1 E
64
39
With Plating
Base
Metal
Detail A
C
B
Symbol Dimension In Inch Dimension In mm
A 0.134 Max. 3.40 Max.
A1 0.010 Min. 0.25 Min.
A2 0.112± 0.005 2.85± 0.12
B0.009± 0.002 0.22±0.05
C0.006± 0.002 0.145± 0.055
D0.913± 0.007 23.20± 0.20
D1 0.787± 0.004 20.00 ± 0.10
E0.677± 0.008 17.20± 0.20
E1 0.551± 0.004 14.00± 0.10
e
0.020 BSC 0.5 BSC
L0.035± 0.006 0.88± 0.15
L1 0.063 BSC 1.60 BSC
y 0.004 Max. 0.10 Max.
θ0°~12°0°~12°
Note:
1. Dimension D1 and E1 do not include resin fins.
2. All dimensions are based on metric system.
3. General appearance spec. should base itself on final visual inspection spec.
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
76 Final
Version: DM9102A-DS-F03
August 28, 2000
Packag e In form ation
TQFP 128L Outline Dimensions Unit: Inches/mm
D
y
Symbol Dimensions In Inches Dimensions In mm
A 0.047 Max. 1.20 Max.
A10.004 ± 0.002 0.1 ± 0.05
A20.039 ± 0.002 1.0 ± 0.05
b0.006
+0.003
–0.001 0.16 +0.07
–0.03
c0.006± 0.002 0.15 ± 0.05
D0.551 ± 0.005 14.00 ± 0.13
E0.551 ± 0.005 14.00 ± 0.13
e0.016 BSC. 0.40 BSC.
F 0.494 NOM. 12.56 NOM.
GD0.606 NOM. 15.40 NOM.
HD0.630 ± 0.006 16.00 ± 0.15
HE0.630 ± 0.006 16.00 ± 0.15
L0.024 ± 0.006 0.60 ± 0.15
L10.039 Ref. 1.00 Ref.
y 0.003 Max. 0.08 Max.
θ0° ~ 12°0° ~ 12°
Note: 1. Dimension D & E do not include resin fins.
2. Dimension G
D is for PC Board surface mount, pad pitch design reference only.
3. All dimensions are based on metric system.
DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
Final
Version: DM9102A-DS-F03
August 28, 20 00
77
Ordering Information
Part Number Pin Count Package
DM9102AF 128 QFP
DM9102AT 128 TQFP
Disclaimer
The information appearing in this publication is
believed to be accurate. Integrated circuits sold by
DAVICOM Semiconductor are covered by the
warranty and patent inde mnification provisions
stipulated in the terms of sale only. DAVICOM makes
no warr anty, express, statut or y , implied or by
description regarding the information in this
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publication or regarding the freedom of the described
chip(s) from patent infringement. FURTHER,
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MERCHANTABILITY OR FITNESS FOR ANY
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Company Overview
DAVI COM Semi c onduc tor, I nc. dev elops and
manufactures integrated circuits for integration into
data commun ica tion pro ducts. Our mission i s to
design and produce IC produc ts that a re the indus tr y’s
best val ue for Data, A udio, Video, and
Int ernet/I ntranet applications. T o achieve this goal , w e
have built an organization that is able to develop
chipsets in response to the evolving technology
requirements of our customers while still deliveri ng
products that meet their cost requirements.
Products
We of fer only products that satisfy high performance
requirements and which are compatible with major
hardware and software standards. Our currently
a vailab le and soon to be released products are based
on our proprietary designs and deliver high quality,
high performance chipsets that comply with modem
communication standards and Ethernet networking
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WARNING
Conditions beyond those listed for the absolute maximum may destroy or damage the products. In addition, conditions for sustained periods at near
the limits of the operating ranges will stress and may temporarily (and permanently) affect and damage structure, performance and/or function.
