DM9102A
Si ngle Chi p Fast E thern et NIC c ontrol ler
2Final
Version: DM9102A-DS-F03
August 28, 2000
Table of Con ten ts
General Description .............................................................1
Bloc k D iagr am......................................................................1
Features...............................................................................4
Pin Con figuration: DM9102A 128pin QFP..........................5
Pin Con figuration: DM9102A 128pin TQFP.......................6
Pin De sc ript ion.....................................................................7
- PCI Bus and CardBus Inter face S ignals.........................7
- Boot ROM and E EPROM Interface................................8
T
Mul tiple x Mo de ................................................................8
T
Dire ct M ode....................................................................10
- L ED P ins.........................................................................11
- N etw ork In ter face...........................................................1 2
- Miscellaneous Pins.........................................................12
- Po w er Pins.....................................................................13
- N ote: L E D M ode............................................................13
Re giste r De fin ition..............................................................14
✧ PC I C on figu rat ion Re gis ters..........................................14
Key to D efau lt.....................................................................14
T
Identification ID...............................................................15
T
Command & Status........................................................15
T
Re vis ion ID.....................................................................17
T
Miscellaneous Function .................................................18
T
I/O B as e Add res s...........................................................18
T
Memory Mapped Base Address....................................19
T
Subsystem Identification................................................19
T
Ca rdBu s CIS P oi nter......................................................20
T
Expansion ROM Base Address.....................................21
T
Capabilities Pointer.........................................................21
T
Interrupt & Latency Configuration..................................22
T
De vice Spe c ific Configuration Register.........................22
T
Power Manageme nt Re gister........................................23
T
Power Manageme nt Control/Status..............................24
✧ Co ntro l an d Sta tus R egis ter (C R)..................................2 5
Key to D efau lt.....................................................................25
1. System Cont rol Re gist er (CR0).....................................26
2. Tra ns mi t Des cr ipto r Po ll D ema n d (CR 1)......................2 7
3. Receive Des criptor Po ll Demand (CR2).......................27
4. R ece i ve De s cripto r B as e Add res s (CR 3).....................27
5. Tra ns mi t Des cr ipto r Bas e Add res s (C R4)....................28
6. Network Status Repor t Register (CR 5).........................28
7. N etw or k Ope rat ion R egis ter (C R6 )............................... 30
8. In terru p t Mas k Register (C R7)...................................... 32
9. Statistical Counter Reg ister (CR8)................................ 33
10. PROM & Manage ment Acces s Register (CR9) ........ 34
11 . Prog ra mmi ng R OM Add res s Re gis ter (CR 10).......... 35
12. General Purpose Timer Re gister (CR 11)................... 35
13 . PHY S tatu s R eg is ter (CR 12)...................................... 35
14 . Sa mple Fra m e A cc es s Reg iste r (CR 13).................... 36
15 . Sa mple Fra m e D a ta Reg is ter (C R14)........................ 36
16. Watching & Jabber Timer Register (CR15)................ 36
✧ CardBus Status Changed Register .............................. 39
1. Function Event Re gister: (o ffset 80h)............................ 39
2. Function Event Mask Register: (offset 84h).................. 39
3. Fun ctio n P res en t S tate Re gis ter : (o ffse t 8 8h )............... 39
4. Fun ctio n Fo rce E ven t Re g iste r: (o ffse t 8 Ch)................ 40
✧ PHY Manage ment Register Set................................... 41
Key To De fau lt................................................................... 41
Basic Mode Control Register (BMCR)
- Re gis ter 0......................................................................... 42
Basic Mode Status Register (BMSR)
- Re gis ter 1......................................................................... 43
PHY ID Identifier Register #1 ( PHYIDR1)
- Re gis ter 2......................................................................... 44
PHY ID Identifier Register #2 ( PHYIDR2)
- Re gis ter 3......................................................................... 44
Auto-negotiation Advertisement Register (ANAR)
- Re gis ter 4......................................................................... 44
Auto-negotiation Link Par tner Ability Register (ANLPAR) -
Re giste r 5........................................................................... 45
Auto-negotiation Expansion Register (ANER)
- Re gis ter 6......................................................................... 46
DAVICOM Spec ified Configuration Reg ister (DSCR)
- Re gis ter 10....................................................................... 46
DAV IC OM S pec i fied Co n figura tio n a n d Statu s Regist e r
(DS CSR) - Re g is ter 11...................................................... 47
10Base-T Configuration/Status (10BTSCRCSR)
- Re gis ter 12....................................................................... 48
Fun ct ional De s cr ipt ion....................................................... 49
✧ System Buffer Management ......................................... 49
1. O ver view........................................................................ 49
2. Data S tructure and Desc riptor List ................................ 49
3. Buffer Manage ment: Chain Structure Method.............. 49
5. D es crip tor L ist: Bu ffer De s crip tor Fo r mat...................... 49
(a) . Re ce i ve D es crip tor For ma t.........................................4 9