1
Intel Corporation D55752-001
Intel and the Intel logo are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of oth ers. Copyright © 2006 Intel Corporation. All rights reserv ed.
Features
• Compliant with ETSI 300 744 DVB-T, Unified
Nordig and DTG performance specifications
• High performance with fast fully blind acquisition
and tra ckin g capab ility
• Low power consumption: less than 0.32 W, and
eco-friendly standby and sleep modes
• Digital filtering of adjacent channels
• Sin gl e 8 MHz S AW filt er for 6, 7 & 8 M Hz OF DM
• Sup er i o r s i ng le f r eq ue n cy ne twork pe rforma nce
• Fast AGC to track out signal fades
• Goo d Dopp ler trac kin g capab ility
• Enhanced frequency capture range to include
triple o ffsets
• External 4 MHz clock or single low-cost
20.48 MHz crystal, tolerance up to +/-200 ppm
• Aut omat ic mo de (2 K/8 K), gua rd an d spe ctra l
inversion detection
• Very low driver software overhead due to on-chip
state-machine control
• Novel RF level detect facility via a separate ADC
• Pre and post Viterbi-decoder bit error rates, and
uncorrectable block count
February 2006
Ordering Information
DJCE6353 882077 64 Pin LQFP Trays
WJCE6353 882206 64 Pin LQFP* Trays
DJCE6353 S L9E N 882128 64 Pin LQ FP Tape and Reel
WJCE6353 S L9G5 882170 64 Pin LQFP* Tape and Reel
*Pb Free Ma tte Tin
CE6353
Nordig Unified DVB-T COFDM Terrestrial
Demodulator for
PC-TV and Hand-held Digital TV (DTV)
Data Sheet
Figure 1 - Block Diagram
CE6353 Data Sheet
2
Intel Corporation
Applications
• Digital terrestrial set-top boxes
• Integrated digital televisions
• Personal video recorders
•PC-TV receivers
• Portable applications
Description
The CE63 53 is a super ior fourth g eneratio n fully comp liant ETSI ETS300 744 COFDM demodulat or that exce eds,
with margin, the performance requirements of all known DVB-T digital terrestrial television standards, including
Unified Nordig and DTG.
A high performance 10 bit on-chip ADC is used to sample the 44 or 36 MHz IF analog signal. Advanced digital
filteri ng of the upp er and lower channel en ables a sin gle 8 MHz channel SAW filt er to be used for 6, 7 a nd 8 MHz
OFDM s ignal recep tion. All s ampling an d other in ternal clocks are derive d from a s ingle 20.48 MHz crystal o r a 4
MHz clock input, the tolerance of which may be relaxed as much as 200 ppm.
The CE6353 has a wide frequency capture range able to automatically compensate for the combined offset
introduced by the tuner xtal and broadcaster triple frequency offsets.
An on-c hip state machine c ontrols all a cquisition and tracking operations of the CE6353 as wel l as controll ing the
tuner via a 2-wire bus. Any frequency range can be automatically scanned for digital TV channels. This mechanism
ensures minimal interaction, maximum flexibility and fast acquisition - very low software overhead.
Also inc luded in th e design is a 7-bi t ADC to det ect the RF sign al streng th and thereby e fficiently contr ol the tuner
RF AGC.
Users have access to all the relevant signa l quality information, including input signal power level, signal-to-noise
ratio, pr e-Viterbi BE R, pos t-Viterbi BER, and the uncor rectable bloc k co unts. The er ror rate m onitor ing p eriods are
programmable over a wide range.
The device is packaged in a 10 x 10 mm 64-pin LQFP and is very low power.
CE6353 Data Sheet
Table of C ontent s
3
Intel Corporation
1.0 Pin & Package Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1 Pin Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
1.2 Pin Allocation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
1.3 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
2.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
2.1 Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2 Automatic Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.3 IF to Baseband Conversion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.4 Adjacent Channel Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.5 Interpolation and Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.6 Carrier Frequency Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.7 Symbol Timing Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.8 Fast Fourier Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
2.9 Common Phase Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.10 Channel Equalization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.11 Impulse Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.12 Transmission Parameter Signalling (TPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.13 De-Mapper. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2.14 Symbol and Bit De-Interleaving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.15 Viterbi Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.16 MPEG Frame Aligner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.17 De-interleaver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.18 Reed-Solomon Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.19 De-scrambler. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.20 MPEG Transport Interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.0 Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1.1 Host . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.2 Tuner . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
3.1.3 Examples of 2-Wire Bus Messages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1.4 Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2 MPEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2.1 Data Output Header Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
3.2.2 MPEG Data Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.3 MPEG Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
3.2.4 MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.2.5 MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.1 Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.2 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
4.3 DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.4 Crystal Specification and External Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
4.4.1 Selection of External Components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4.1.1 Loop Gain Equation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4.1.2 List of Equation Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
4.4.1.3 Calculating Crystal Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4.1.4 Capacitor Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
4.4.1.5 Oscillator/Clock Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
5.0 Application Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
CE6353 Data Sheet
List of Figures
4
Intel Corporation
Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2 - Pin Outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3 - OFDM Demodulator Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - FEC Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 5 - Primary 2-Wire Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 6 - DVB Transport Packet Header Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 7 - MPEG Output Data Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 8 - MPEG Timing - MOCLKINV = 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 9 - MPEG Timing - MOCLKINV = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 10 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11 - External Clocking via AC Coupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12 - Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
CE6353 Data Sheet
List of Tables
5
Intel Corporation
Table 1 - Pin Names - numeric. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 2 - Pin Names - alphabetical order. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3 - Timing of 2-Wire Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
CE6353 Data Sheet
6
Intel Corporation
1.0 Pin & Package Details
1.1 Pin Outline
Figure 2 - Pin Outline
CE6353 Data Sheet
7
Intel Corporation
1.2 Pin Allocation
Pin Function Pin Function Pin Function Pin Function
1 Vss 17 SADD1 33 Vdd 49 MDO0
2 Vdd 18 SADD0 34 RFLEV 50 MDO1
3 Vss 19 CVdd 35 CLK2/GPP0 51 MDO2
4 CLK1 20 Vss 36 DATA2/GPP1 52 MDO3
5 DATA1 21 PLLVdd 37 CVdd 53 MDO4
6IRQ 22 PLLGND 38 Vss 54 Vdd
7CVdd 23XTI 39 CVdd 55 Vss
8 Vss 24 XTO 40 Vss 56 MDO5
9 RESET 25 Vss 41 AGC2/GPP2 57 MDO6
10 SLEEP 26 PLLTEST 42 AGC1 58 MDO7
11 STATUS 27 OSCMODE 43 GPP3 59 CVdd
12 28 AVdd 44 SMTEST 60 Vss
13 Vdd 29 AGnd 45 Vdd 61 MOCLK
14 Vss 30 VIN 46 Vss 62 BKERR
15 31 VIN 47 MOSTRT 63 MICLK
16 32 AGnd 48 MOVAL 64 CVdd
Table 1 - Pin Names - numeric
Function Pin Function Pin Function Pin Function Pin
AGC1 42 GPP3 43 PLLTEST 26 Vdd 54
AGC2/GPP2 41 IRQ 6PLLVdd 21VIN 30
AGnd 29 MDO0 49 RESET 9 VIN 31
AGnd 32 MDO1 50 RFLEV 34 Vss 1
AVdd 28 MDO2 51 SADD0 18 Vss 3
BKERR 62 MDO3 52 SADD1 17 Vss 8
CLK1 4 MDO4 53 N/C 16 Vss 14
CLK2/GPP0 35 MDO5 56 N/C 15 Vss 20
CVdd 7 MDO6 57 N/C 12 Vss 25
CVdd 19 MDO7 58 SLEEP 10 Vss 38
CVdd 37 MICLK 63 SMTEST 44 Vss 40
CVdd 39 MOCLK 61 STATUS 11 Vss 46
Table 2 - Pin Names - alphabetical order
CE6353 Data Sheet
8
Intel Corporation
1.3 Pin Description
CVdd 59 MOSTRT 47 Vdd 2 Vss 55
CVdd 64 MOVAL 48 Vdd 13 Vss 60
DATA1 5 OSCMODE 27 Vdd 33 XTI 23
DATA2/GPP1 36 PLLGND 22 Vdd 45 XTO 24
Pin Description Table
Pin No Name Pin Description I/O Type V mA
MPEG pins
47 MOSTRT MPEG packet start O
CMOS Tristate
3.3 1
48 MOVAL MPEG data valid O 3.3 1
49-53, 56-58 MDO (0:4)/MDO(5:7) MPEG data bus O 3.3 1
61 MOCLK MPEG clock out O 3.3 1
62 BKERR Block error O 3.3 1
63 MICLK MPEG clock in I CMOS 3.3
11 STATUS Status output O 3.3 1
6IRQ Interrupt outp ut O Open drai n 56
Control pins
4CLK1 Serial clock I CMOS 5
5DATA1 Serial data I/O Open drain 56
23 XTI Low phase noise oscillator I
CMOS
24 XTO O
10 SLEEP Device power down I 3.3
12, 15-18 SADD(4:0) Serial address set I 3.3
44 SMTEST Production test (only set low) I 3.3
35 CLK2/GPP0 Serial clock tuner I/O
Open drain
56
36 DATA2/GPP1 Serial data tuner I/O 56
42 AGC1 Primary AGC O 56
41 AGC2/GPP2 Secondary AGC I/O 56
43 GPP(3) General purpose I/O I/O 56
9RESET Device reset I CMOS 5
27 OSCMODE Crystal oscillator mode I CMOS 3.3
26 PLLTEST PLL analog test O (tristated)
Table 2 - Pin Names - alphabetical order (continued)
CE6353 Data Sheet
9
Intel Corporation
Analog inputs
30 VIN positiv e inp ut I
31 VIN negative input I
34 RFLEV RF level I
Supply pins
21 PLLVdd PLL supply S 1.8
22 PLLGnd S 0
7, 19, 37, 39, 59, 64 CVdd Core logic power S 1.8
2, 13, 45, 54, Vdd I/O ring power S 3.3
1, 3, 8, 14, 20, 25,
38, 40, 46, 55 , 60 Vss Core and I/O ground S 0
28 AVdd ADC analog supply S 1.8
29, 32 AGnd S 0
33 Vdd 2nd ADC supply S 3.3
Pin Description Table (continued)
Pin No Name Pin Description I/O Type V mA
CE6353 Data Sheet
10
Intel Corporation
2.0 Functio nal Descri ption
A functional block diagram of the CE6353 OFDM demodulator is shown in Figure 3. This accepts an IF analog
signal and delivers a stream of demodulated soft decision data to the on-chip Viterbi decoder. Clock, timing and
frequency synchronization operations are all digital and there are no analog control loops except the AGC. The
frequency capture range is large enough for all practical applications. This demodulator has novel algorithms to
combat impulse noise as well as co-channel and adjacent channel interference. If the modulation is hierarchical,
the OFDM outputs both high and low priority data streams. Only one of these streams is FEC-decoded, but the FEC
can be switched from one stream to another with minimal interruption to the transport stream.
Figure 3 - O FDM D emodul ator D iagram
The FEC mo dul e s hown in Figu re 4 cons is ts of a concatena ted c on vo lutional (Viterbi) and Reed -S olomo n decoder
separated by a depth-12 convolutional de-interleaver. The Viterbi decoder operates on 5-bit soft decisions to
provide the best performance over a wide range of channel conditions. The trace-back depth of 128 ensures
minimum loss of performance due to inevitable survivor truncation, especially at high code rates. Both the Viterbi
and Reed- Solomon dec oders are equipped wi th bit-error monitors . The former p rovides th e bit error r ate (BER) a t
the OFDM output. The latter is the more useful measure as it gives the Viterbi output BER. The error collecting
intervals of these are programmable over a very wide range.
CE6353 Data Sheet
11
Intel Corporation
Figure 4 - FEC Block Diagram
The FSM controll er shown i n Figure 3 controls both the de modulator an d the FE C. It also drives th e 2-wire bu s to
the tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the
received signal. It can also be used to scan any defined frequency range searching for OFDM channels. This
mechanism provides the fast channel scan and acquisition performance, whilst requiring minimal software
overhead in the host driver.
The algorithms and architectures used in the CE6353 have been optimized to minimize power consumption.
2.1 Analog-to-Digital Converter
The CE6353 has a high performance 10-bit analog-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:
• 36.17 MHz IF
• 43.75 MHz IF
• 5 - 10 MHz near-zero IF
An on-c hip pr ogram mab le phas e l oc ked l oop (P LL) i s u se d to g ener a te the ADC sam pl ing cl oc k. The P LL i s h igh ly
programmable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.
2.2 Automatic Gain Control
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error
signal is fi ltered an d is used to contr ol the ga in of the a mplif ier. A si gma-del ta modulate d outpu t is p rovi ded, whic h
has to be RC low-pass filtered to obtain the voltage to control the amplifier.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC
clippi ng and a s mall valu e resu lts in exce ssiv e quan tizati on noi se. Hen ce the o ptimum value has be en deter mine d
assuming the input signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit
theorem in statistics to the OFDM signal, which consists of a large number of randomly modulated carriers. This
reference or target value may have to be lowered slightly for some applications. Slope control bits have been
provid ed for the AGCs and these have to be set corre ctly depending on the gain -vers us-voltage slope of the gain
control amplifiers.
CE6353 Data Sheet
12
Intel Corporation
The bandwidth of the AGC is set to a large value for quick acquisitio n then reduced to a small value for tracking.
The AGC is free running during OFDM channel changes and locks to the new channel while the tuner lock is being
established. This is one of the features of CE6353 used to minimize acquisition time. A robust AGC lock
mechanism is provided and the other parts of the CE6353 begin to acquire only after the AGC has locked.
2.3 IF to Baseband Co nversion
Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at
approxi matel y 8 .9 MHz. The first step of the demod ulatio n proc ess is t o con vert th is s ignal to a comple x (in-ph ase
and quadrature) signal in baseband. A correction for spectral inversion is implemented during this conversion
process. Note also that the CE6353 has control mechanisms to search automatically for an unknown spectral
inversion status.
2.4 Adjacent Channel Filtering
Adjacent channels, in particular the Nicam digital sound signal associated with analog channels, are filtered prior to
the FFT.
2.5 Interpolation and Clock Synchron ization
CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the
signal at a fix ed rate, for exam ple, 45.0 56 MH z. Conversi on of the 45.056 MH z signal to the OFDM sample rate is
achieved using the tim e-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by
factors 6/8 and 7/8 for 6 and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is
programmed in a CE6353 register (defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase
locked loop in the CE6353 compensates fo r inaccuracies in this ratio due to uncertainties of the frequency of the
sampling clock.
2.6 Carrier Frequency Synchroniz ation
There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to
broadcast freque ncy shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes,
without the need for an analog frequency control (AFC) loop.
The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these values
can be increased, if necessary, by programming an on-chip register (see 7.4.1). It is recommended that a larger
capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to
adjust the tuner. After the OFDM mo dule has locked (the AFC will have been previously disabled), the freq uency
offset can be read from an on-chip register.
2.7 Symbol Timing Synchro nization
This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-
symbol interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated
to dynamically adapt to time-variations in the transmission channel.
2.8 Fast Fourier Transform
The FFT module uses the trigger information from the timing synchronization module to set the start point for an
FFT. It then uses either a 2 K or 8 K FFT to transform the d ata from th e time domain to the frequency domain. An
extremely hardware-efficient and highly accurate algorithm has been used for this purpose.
CE6353 Data Sheet
13
Intel Corporation
2.9 Common Phas e Error Correc tion
This mo dule subtracts the comm on phase offset from all the carriers of th e OFDM signal to min imize the effect of
the tuner phase noise on system performance.
2.10 Channel Equa lization
This cons i sts of two parts. The first part inv ol ves est im atin g th e c han nel fr equ ency re sp ons e fro m pi lo t in for ma tion .
Efficient algorithms have been used to track time-varying channels with a minimum of hardware.
The secon d part involve s applying a correcti on to the data ca rriers bas ed on the esti mated freq uency respons e of
the channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.
2.11 Impulse Filtering
CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.
2.12 Transmission Parameter Signa lling (TPS)
An OFDM frame c onsists of 68 symbo ls and a superfram e is made up of four such frames. The re is a set of TPS
carrier s in every symbol and al l these carr y one bit of TP S. These bits, whe n combine d, includ e informat ion about
the tran sm is si on mo de, gu ar d ra tio , c on ste llati on, hi er arch y and c od e ra te, as d efi ned i n E TS 30 0 7 44. In ad di tion ,
the first eight bits of the cell identifier are contained in even frames and the second eight bits of the cell identifier are
in odd frame s. The T PS module extracts all the TPS data, and pr ese nts these to the host proces s or in a str uctured
manner.
2.13 De-Mapper
This module generates soft decisions for demodulated bits using the channel-equalized in-phase and quadrature
componen ts of the data carriers as well as per-carrier chann el state information (CSI). The de-mapping algorithm
depends on the constellation (QPSK, 16QAM or 64QAM) and the hierarchy (α= 0, 1, 2 or 4). Soft decisions for both
low- and high-priority data streams are generated.
2.14 Symbol and B it De-Interleaving
The OFDM transmitter interleaves the bits within each carrier and also the carriers within each symbol. The de-
interle aver modu les con sist larg ely of mem ory to inve rt these interleavi ng functi ons and pres ent the so ft decisions
to the FEC in the original order.
CE6353 Data Sheet
14
Intel Corporation
2.15 Viterbi Dec oder
The Viterbi decoder acc ep ts the soft deci si on data from the OFDM de mod ulator and ou tputs a dec ode d bit -st ream .
The decoder does the de-puncturing of the input data for all code rates other than 1/2. It then evaluates the branch
metrics and passes these to a 64-state path-metric updating unit, which in turn outputs a 64-bit word to the survivor
memory. The Viterbi decoded bits are obtained by tracing back the survivor paths in this memory. A trace-back
depth of 128 is used to minimize any loss in performance, especially at high code rates.
The dec oder re-enc odes the decoded bits and co mpares these with receiv ed data (delay ed) to com pute bit e rrors
at its input, on the assumption that the Viterbi output BER is significantly lower than its input BER.
2.16 MPEG Fram e Aligner
The Viterbi decoded bit stream is aligned into 204-byte frames. A robust synchronization algorithm is used to
ensure correct lock and to prevent loss of lock due to noise impulses.
2.17 De-interleave r
Errors at the Viterbi output occur in bursts and the function of the de-interleaver is to spread these errors over a
number of 204-byte frames to give the Reed-Solomon decoder a better chance of correcting these. The de-
interle aver is a memory uni t which implements the in verse of the co nvolutional inte rleaving funct ion introduced by
the transmitter.
2.18 Reed-Sol omon Decod er
Every 188-byte transport packet is encoded by the transmitter into a 204-byte frame, using a truncated version of a
systematic (255,239) Reed-Solomon code. The corresponding (204,188) Reed-Solomon decoder is capable of
correcting up to eight byte errors in a 204-byte frame. It may also detect frames with more than eight byte errors.
In additio n to effici en tly perfo rm in g thi s d ec oding fu nc tio n, the Reed-Solom on decoder in CE6 353 ke eps a co unt of
the number of bit errors corrected over a programmable period and the number of uncorrectable blocks. This
information can be used to compute the post-Viterbi BER.
2.19 De-scrambler
The de-scrambler de-randomizes the Reed-Solomon decoded data by generating the exclusive-OR of this with a
pseudo-random bit sequence (PRBS). This outputs 188-byte MPEG transport packets. The TEI bit of the packet
header may be set if required to indicate uncorrectable packets.
2.20 MPEG Tran sport Interface
MPEG data can be outpu t in paralle l or seria l mod e. T he ou tput cloc k freque ncy is autom ati ca ll y c hosen to pre sen t
the MPEG data as un iformly s paced as poss ible to the transpo rt proces sor. Th is freq uency depen ds on the guard
ratio, co nstellation , hierar chy and code rate. T here is also an option for the data to be extracted from the CE 6353
with a clock provided by the user.
CE6353 Data Sheet
15
Intel Corporation
3.0 Interfaces
3.1 2-Wire Bus
3.1.1 Host
The primary 2-wire bus serial interface uses pins:
• DATA1 (pi n 5) seri al da ta, the most signi fic ant bit i s sent fi rst.
• CL K1 (pi n 4) s erial clo ck .
The 2-wire bus address is determined by applying VDD or VSS to the SADD[4:0] pins.
In TNIM evaluation applications, the 2-wire bus address is 0001 111 R/W with the pins connected as follows:
When the CE6353 is powered up, the RESET pin 9 should be he ld low fo r at least 50 ms after VDD has reache d
normal o perat ion le ve ls. As t he RES ET pi n goes hi gh, the logic levels on S ADD[4:0] are latc hed as the 2-wire bus
address. ADDR[0] is the R/W bit.
The circuit works as a slav e transmitter with the lsb set high or as a s lave receiver with the lsb set low. In re ceive
mode, the first data byte is written to the RADD virtual registe r, which forms the register sub-address. The RADD
registe r takes an 8-bit value th at det ermines which of 256 possi ble regi ster a ddresse s is wri tten to by t he followin g
byte. Not all addresses are valid and many are reserved registers that must not be changed from their default
values. Multiple byte reads or writes will auto-increment the value in RADD, but care should be taken not to access
the reserved registers accidentally.
Followin g a vali d c hi p ad dr ess, the 2- wir e b us STOP c omm and r ese ts the RA DD reg is ter to 00. If the ch ip add re ss
is not recognized, the CE6353 will ignore all activity until a valid chip address is received. The 2-wire bus START
command does NOT reset the RADD register to 00. This allows a combined 2-wire bus message, to point to a
particular read register with a write command, followed immediately with a read data command. If required, this
could n ext be fo llowed wi th a write command to conti nue from the latest address . RADD wou ld not be sent in th is
case. Finally, a STOP command should be sent to free the bus.
When the 2-wire bus is addressed (after a recognized STOP command) with the read bit set, the first byte read out
is the contents of register 00.
3.1.2 Tuner
The CE6353 has a General Pu rpose Port that can be configured to provide a secondary 2-wire bus. See register
GPP_CTL address 0x8C.
Master control mode is selected by setting register SCAN_CTL (0x62) [b3] = 1.
The allocation of the pins is: GPP0 pin 35 = CLK2, GPP1 pin 36 = DATA2.
ADDR[7] ADDR[6] ADDR[5] ADDR[4] ADDR[3] ADDR[2] ADDR[1]
Not programmable SADD[1] SADD[0]
VSS VSS VSS VDD VDD VDD VDD
CE6353 Data Sheet
16
Intel Corporation
3.1.3 Examples of 2-Wire Bu s Messa ges
KEY: S Start condition W Write (= 0)
P Stop condition R Read (= 1)
A Acknowledge NA NOT Acknowledge
Italics CE6353 output RADD Register Address
Write operation - as a slave receiver:
Read operation - CE6353 as a slave transmitter:
Write/read operation with repeated start - CE6353 as a slave transmitter:
3.1.4 Primary 2-Wire Bus Timing
Figure 5 - Primary 2-Wire Bus Timing
Where: S = Start
Sr = Restart, i.e., start without stopping first.
P=Stop.
SDEVICEWARADD ADATA ADATA AP
ADDRESS (n) (reg n) (reg n+1)
SDEVICERADATAADATA ADATA NA P
ADDRESS (reg 0) (reg 1) (reg 2)
S DEVICE W ARADD AS DEVICE R ADATA ADATA NA P
ADDRESS (n) ADDRESS (reg n) (reg n+1)
PS
Sr P
LOW
ttR
tHD;STA HD;DAT
t
tF
HIGH
ttSU;DAT SU;STA
t
DATA1
CLK1
tBUFF
tSU;STO
CE6353 Data Sheet
17
Intel Corporation
Parameter Symbol Value Unit
Min. Max.
CLK cl ock frequency (Primary) fCLK 0 400 1
1. If operating with an external 4 MHz clock, the serial clock frequency is reduced to 100 kHz maximum.
kHz
Bus free time betw een a STOP and START condition. tBUFF 200 ns
Hold time (repeated) START condition. tHD;STA 200 ns
LOW period of CLK clock. tLOW 1300 ns
HIGH period of CLK clock. tHIGH 600 ns
Set-up time for a repeated START condition. tSU;STA 200 ns
Data hold time (when input). tHD;DAT 100 ns
Data set-up time tSU;DAT 100 ns
Rise time of both CLK and DATA signals. tRnote 2
2. The rise time depends on the external bus pull up resistor. Loading prevents full speed operation.
ns
Fall time of both CLK and DATA signals, (100 pF to ground). tF20 ns
Set-up time for a STOP condition. tSU;STO 200 ns
Table 3 - Timing of 2-Wire Bus
CE6353 Data Sheet
18
Intel Corporation
3.2 MPEG
3.2.1 Data Output Header Format
Figure 6 - DVB Transport Packet Header Byte
After decoding the 188-byte MPEG packet, it is output on the MDO pins in 188 consecutive clock cycles.
Additionally when the TEI_En bit in the OP_CTRL_0 register (0x5A) is set high (default), the TEI bit of any
uncorrec table packet wi ll automaticall y be set to ‘1’. If TEI_E n bit is low then TEI bi t will not be changed (but note
that if this bit is already 1 , for exa mple, due to a chan nel error whi ch has n ot been c orrected, it wi ll rem ain high a t
output).
TEI
010001111st byte
2nd byte
Transport
Packet
Header
4 bytes
184 Transport packet bytes
188 byte packet output
MDO[7] MDO[0]
CE6353 Data Sheet
19
Intel Corporation
3.2.2 MPEG Data Output Signals
The MPE GEN bit in the CON FIG register mu st be set low to e nable the MPEG da ta. The max imum movement i n
the packet sy nc hroni z atio n by te p osi ti on i s limi ted to ± 1 out put c lock per iod. MOCLK wi ll be a con tin uou sl y r un nin g
clock once symbol lock has been achieved, and is derived from the symbol clock. MOCLK is shown in Figure 7 with
MOCLKINV = ‘1’, the default state, see register 0x50.
All output data and signals (MDO[7:0], MOSTRT, MOVAL & BKERR) change on the negative edge of MOCLK
(MOCLKINV = 1) to present stable data and signals on the positive edge of the clock.
A comple te packet is out put o n MDO[7: 0] on 188 c onsecuti ve cloc ks and the MDO[ 7:0] pins will remain lo w durin g
the inter -packet gaps. MO STRT goe s hig h for the f irst by te c lock o f a pack et . MO VAL goes h igh on the firs t by te o f
a packet and rem ains high until the la st byte has been c locked out. BKERR goes low on the first byte of a packe t
where uncorrectable bytes are detected and will remain low until the last byte has been clocked out.
Figure 7 - MPEG Output Data Waveforms
3.2.3 MPEG Outp ut Timing
Maximum delay conditions: VDD = 3.0V, CVDD = 1.62V, Tamb = 80oC, Output load = 10pF.
Minimum delay conditions: VDD = 3.6V, CVDD = 1.98V, Tamb = -10oC, Output load = 10pF.
MOCLK frequency = 45.06 MHz.
MDO7:0
MOCLKINV=1
MOCLK
MOSTRT
MOVAL
BKERR
Tp Ti
1st byte packet n 188 byte packet n 1st byte packet n+1
CE6353 Data Sheet
20
Intel Corporation
3.2.4 MOCLKINV =1
Figure 8 - MPEG Timing - MOCLKI NV =1
3.2.5 MOCLKINV =0
MDOSWAP = 0
The hold time is better when MOCLKINV = 1, therefore this should be used if possible.
Figure 9 - MPEG Timing - MOCLKI NV =0
Parameter Delay conditions Units
Maximum Minimum
Data output delay tD3.0 1.0
nsSetup Time tSU 7.0 10.0
Hold T ime tH7.0 10.0
Parameter Delay conditions Units
Maximum Minimum
Data output delay tD3.0 1.0
nsSetup Time tSU 18.0 20.0
Hold T ime tH1.0 0.2
tD
tSU
MOCLK
MDO
MOSTRT
MOVAL
BKERRB }tH
BKERR
tD
tSU
MOCLK
MDO
MOSTRT
MOVAL
BKERRB }tH
BKERR
CE6353 Data Sheet
21
Intel Corporation
4.0 Electrica l Char acteris tics
4.1 Recommende d Operating C onditions
4.2 Absolute Maximum Rating s
Note: St resses ex ceeding these listed under absolute maximum ratings m ay induce failure. Exposur e to absolute max imum ratings fo r
extended periods may reduce reliability. Functionality at or above these condit ions is not im plied.
Parameter Symbol Min. Typ. Max. Units
Power supply voltage: periphery VDD 3.0 3.3 3.6 V
core CVDD 1.62 1.8 1.98 V
Power supply current: periphery 1
1. Current from the 3.3 V supply will be mainly dependent on the external loads.
IDDP1mA
core IDDC170 mA 2
2. Current given is for optimum performance, lower cur rent is possible with reduced performance.
Input clock freque ncy 3
3. The min/max frequencies given are those supported by the oscillator cell. Required system frequencies are as def ined in the design
manual. Frequencies outside these limits are acceptable with an external clock signal.
XTI 16.00 20.48 25.00 MHz
CLK1 primary seria l clock frequency 4
4. If operating with an external 4 M Hz clock , the serial clock frequency is reduced to 100 kHz maximum.
fCLK 400 kHz
Ambient operating temperature -10 80 °C
Maximum Operating Conditions
Parameter Symbol Min. Max. Unit
Power supply VDD -0.3 +3.6 V
CVDD -0.3 +2.0 V
Voltage on input pins (5 V rated) VI -0.3 5.5 V
Voltage on input pins (3.3 V rated) VI -0.3 VDD + 0.3 V
Voltage on output pins (5 V rated) VO -0.3 5.5 V
Voltage on output pins (3.3 V rated) VO -0.3 VDD + 0.3 V
Stor age temp erature TSTG -55 150 °C
Operating ambient temperature TOP -10 80 °C
Junction temperature TJ 125 °C
CE6353 Data Sheet
22
Intel Corporation
4.3 DC Electrical Charac teristics
4.4 Crystal Specifica tion and Extern al Clocking
Parallel resonant fundamental frequency (preferred) 20.4800 MHz
Tolerance over operating temperature range ± 150 ppm
Tolerance overall ± 200 ppm
Typical load capacitance 27 pF
Drive level 0.4 mW max
Equivalent series resistance <25 Ω
DC Electrical Characteristics
Parameter Conditions Pins Symbol Min. Typ. Max. Unit
Operating
voltage periphery VDD 3.0 3.3 3.6 V
core CVDD 1.62 1.8 1.98 V
Supply curren t 1
1. Current given is for optimum performance, lower cur rent is possible with reduced performance.
1.62>CVDD>1.98 IDDCORE 170 mA
Supply current sleep mode 300 μA
Outputs
Output levels IOH 2mA
3.0>VDD>3.6 MDO(7:0), MOVAL,
MOSTRT, MOCLK,
STATUS, BKERR
VOH 2.4 V
IOL 2mA
3.0>VDD>3.6 VOL 0.4 V
IOL 6mA
3.0>VDD>3.6 GPP(3:0), DATA1,
AGC1, AGC2, IRQ VOL 0.4 V
Output capacitance Not including track MDO(7:0), MOVAL,
MOSTRT, MOCLK,
STATUS, BKERR
3.0 pF
GPP(3:0), DATA1,
AGC1, AGC2,IRQ 3.6 pF
Output leakage (tri-state) 1μA
Inputs
Input levels 3.0>VDD>3.6
-0.5 ≥ Vin ≥
VDD+0.5V
MICLK, SADD(4:0)
SLEEP, OSCMODE VIH 2.0 V
Input levels 3.0>VDD>3.6
-0.5 ≥ Vin ≥ +5.5V GPP(3:0), CLK1,
DATA1, RESET VIH 2.0 V
Input levels 3.0>VDD>3.6
Capacitances do
not include track
All inputs VIL 0.8 V
Input leakage Current SLEEP, SMTEST,
MICLK, CLK1,
OSCMODE
±1 μA
Input capacitance 1.8 pF
Input capacitance SADD(4:0), DATA1,
GPP(3:0) 3.6 pF
CE6353 Data Sheet
23
Intel Corporation
Figure 10 - Crystal Oscillator Circuit
4.4.1 Selection of Ex ternal Com ponents
The capacitor values used must ensure correct operation of the Pierce oscillator such that the total loop gain is
greater than unity. Correct selection of the two capacitors is very important and the following method is
recommended to obtain values for C1 and C2.
4.4.1.1 Loop Gain Equ ation
Although osc illation may sti ll occ ur if the l oop gain is just abov e 1, a loop gain of between 5 and 25 is optimum to
ensure that oscillations will occur across all variations in temperature, process and supply voltage, and that the
circuit will exhibit good start-up characteristics.
Equation 1 -
Equation 2 -
4.4.1.2 List of Equation Parameters
A total loop gain (between 5 and 25)
Cin C1 + Cpar
Cout C2 + Cpar
Cpar parasitic capacitance associated with each oscillator pin (XTI and XTO). It consists of track
capacitances, package capacitance and cell input capacitance. Normally Cpar ≈ 4pF.
Zo 9.143 kΩ - output impedance of amplifier at 1.8 V operation - typical
gm 8.736 mA/V - transconductance of amplifier at 1.8 V operation -typical
Rf 2.3 MΩ - internal feedback resistor
ESR maximum equivalent series resistance of crystal - given by crystal manufacturer (Ω)
f fundamental frequency of crystal (Hz)
XTI XT0
XTI
C2
OSCMODE
C1
-
A = Cout.gm
Cin
Cout + Cin
Rf.Cin +1
Zin
-11
Zo
+
-
Zin = 1
(2.π.f.Cout)2.ESR
CE6353 Data Sheet
24
Intel Corporation
4.4.1.3 Calculating Crystal Power Dissipation
To calculate the power dis sipated in a crys tal the following equati on can be used.
Equation 3 -
Pc = power dissipated in crystal at resonant frequency (W)
Vpp = maximum peak to peak output swing of amplifier is 1.8 V for all CVDD
Zin = crystal network impedance (see Equation 2)
4.4.1.4 Capacitor Value s
Using the loop gain lim its (5 < A < 25), the maximum and minimum valu es for C1 and C2 can be calculated with
Equation 4 below.
Equation 4 -
Note: Equation 4 was derived from Equation 1 and Equation 2 using the premise that C1 = C2.
Within these limits, any value for C1 and C2 can now be selected. Normally C1 and C2 are chosen such that the
resulting crystal load capacitance CL (see Equation 5) is close to the crystal manufacturers recommended CL
(standard values for CL are 15 pF, 20 pF and 30 pF). The crystal will then operate very near its specified frequency.
Equation 5 -
Cpar12 =parasitic capacitance between the XTI and XTO pins. It consists of the IC package’s pin-to-pin
capacitance (including any socket used) and the printed circuit board’s track-to-track capacitance.
Cpar12 ≈2pF.
If some frequency pulling can be tolerated, a crystal load capacitance different from the crystal manufacturer’s
recommended CL may be acceptable. Larger values of CL tend to reduce the influence of circuit variations and
tolerances on frequency stability. Smaller values of CL tend to reduce startup time and crystal power dissipation.
Care must however be taken that CL does no t fa ll ou tside the c rys tal pu ll in g r an ge or the ci rcui t m ay fa il to start u p
altogether. It is also po ssible to qu ote CL to the crystal manufa cturer who can then cu t a crystal to order which will
resonate, under the specified load conditions, at the desired frequency.
Finally the power d issi pation in the c rys tal mu st be c he cked. If P c i s too hig h C1 and C2 m us t be reduc ed. If th is is
not feasible C2 alone may be reduced. Unbalancing C1 and C2 will, however, require checking if the loop gain
condition is still satisfied. This must be done using Equation 1.
Pc = 8.Zin
Vpp2
Cin = Cout = gm
A2
Rf
1
Zo
1
(2.π.f)2.ESR when: C1 = C2 = Cout - Cpar
-- .
-
CL = Cout . Cin
Cout + Cin +Cpar12
Note: 2 > C2
C1>0.5
CE6353 Data Sheet
25
Intel Corporation
4.4.1.5 Oscillator/Clock App lication Notes
• On the printed circuit board, the tracks to the crystal and capacitors must be made as short as possible.
Other signal tracks must not be allowed to cross through this area. The component tracks should preferably
be ringed by a ground track connected to the chip ground (0 V) on adjacent pins either side of the crystal
pins. It is also advisable to provide a ground plane for the circuit to reduce noise.
• Exter nal cl ock signals, applied t o XTI an d/or XT O, must not excee d the cell suppl y limit s (i. e., 0V and CVD D)
and cur rent into or ou t of XT I and/or XTO must be limited to less than 10mA to avoid damaging the cell’s
amplitude clamping circuit.
• An exter nal, DC coup led, sin gle ended squa re wa ve clock signal may be applied to XTI if OSCMODE = 0. To
limit the current taken from the signal source a resistor should be placed between the clock source and XTI.
The recommended value for this series resistor is 470 Ω for a clo ck si gnal swit chin g betwe en 0 V an d
CVDD. The current the clock source needs to source/sink is then <1.9 mA. The XTO pin must be left
unconnected in this configuration.
• AC coupling of a single ended external clock to XTI, with OSCMODE = 0, is not recommended. The duty
cycle of the OSCOUT signal cannot be guaranteed in such a configuration.
• AC coupli ng of a si ngle ende d exte rnal clock to XTI , with OSC MODE = 1, is possibl e. It is recomme nded t hat
the circ uit shown in Figur e 11 be used to cor rect ly bias the o scillat or inpu t s: The common -mode volt age VCM
for XTI and XTO, (set by the 36 kΩ and 22 kΩ resistors) must be 800 mV < VCM < CVDD and the ampl itude
Vpp of the clock signal must be >100 mV.
Figure 11 - External Clocki ng via AC Coup ling
• External, differential clock signals may be applied to XTI and XTO if OSCMODE = 1. The common-mode
voltage VCM for the differential clock signals must be 800 mV < VCM < CVDD, and the peak-to-peak signal
amplitude Vpp must be >100 mV. It is recommended that differential clock signals have VCM = 1.0V. For
Vpp > 400 mV a resistor of >390 Ω in series wi th XTI or XTO may be req ui r e d to li mi t th e cur re n t take n fro m
or supplied to the clock sources.
External clock 10nF
XTI
100k
10nF 22k
36k
XTO Vdd OSCMODE
CE6353 Data Sheet
26
Intel Corporation
5.0 Appli cation Cir cui t
Figure 12 - Typica l Applicat ion Circui t
