28172968E90 - VISHAY - Datasheet.Live

Not recommended for new design

This is information on a product still in production but not recommended for new designs.

December 2010 Doc ID 5676 Rev 5 1/20

M40Z111

M40Z111W

5 V or 3 V NVRAM supervisor for up to two LPSRAMs

Features

■Convert low power SRAMs into NVRAMs

■Precision power monitoring and power

switching circuitry

■Automatic write-protection when VCC is out-of-

tolerance

■Choice of supply voltages and

power-fail deselect voltages:

–M40Z111: V

CC = 4.5 to 5.5 V

THS = VSS; 4.5 ≤ VPFD ≤ 4.75 V

THS = VOUT; 4.2 ≤ VPFD ≤ 4.5 V

–M40Z111W: V

CC = 3.0 to 3.6 V

THS = VSS; 2.8 ≤ VPFD ≤ 3.0 V

VCC = 2.7 to 3.3 V

THS = VOUT; 2.5 ≤ VPFD ≤ 2.7 V

■Less than 15 ns chip enable access

propagation delay (for 5.0 V device)

■Packaging includes a 28-lead SOIC and

SNAPHAT® top (to be ordered separately)

■SOIC package provides direct connection for a

SNAPHAT top which contains the battery

■RoHS compliant

– Lead-free second level interconnect

SOH28 (MH)

SNAPHAT (SH)

battery

www.st.com

Obsolete Product(s) - Obsolete Product(s)

Contents M40Z111, M40Z111W

2/20 Doc ID 5676 Rev 5

Contents

1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1 Data retention lifetime calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2 VCC noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . 10

3 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

5 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

6 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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M40Z111, M40Z111W List of tables

Doc ID 5676 Rev 5 3/20

List of tables

Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 4. DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 5. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 6. DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Table 7. SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data . . . . . . . . . . 15

Table 8. 4-pin SNAPHAT housing for 48 mAh battery, package mechanical data . . . . . . . . . . . . . . 16

Table 9. 4-pin SNAPHAT housing for 120 mAh battery, package mechanical data . . . . . . . . . . . . . 17

Table 10. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 11. Battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Table 12. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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List of figures M40Z111, M40Z111W

4/20 Doc ID 5676 Rev 5

List of figures

Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. SOIC28 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 4. Power-down timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 5. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 6. Supply voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Figure 7. AC testing load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Figure 8. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT, package outline . . . . 15

Figure 9. 4-pin SNAPHAT housing for 48 mAh battery, package outline . . . . . . . . . . . . . . . . . . . . . 16

Figure 10. 4-pin SNAPHAT housing for 120 mAh battery, package outline . . . . . . . . . . . . . . . . . . . . 17

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M40Z111, M40Z111W Description

Doc ID 5676 Rev 5 5/20

1 Description

The M40Z111/W NVRAM supervisor is a self-contained device which converts a standard

low-power SRAM into a non-volatile memory.

A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance

condition.

When an invalid VCC condition occurs, the conditioned chip enable (ECON) output is forced

inactive to write-protect the stored data in the SRAM.

During a power failure, the SRAM is switched from the VCC pin to the lithium cell within the

SNAPHAT® to provide the energy required for data retention. On a subsequent power-up,

the SRAM remains write protected until a valid power condition returns.

The 28-pin, 330 mil SOIC provides sockets with gold plated contacts at both ends for direct

connection to a separate SNAPHAT housing containing the battery. The unique design

allows the SNAPHAT battery package to be mounted on top of the SOIC package after the

completion of the surface mount process.

Insertion of the SNAPHAT housing after reflow prevents potential battery damage due to the

high temperatures required for device surface-mounting. The SNAPHAT housing is keyed to

prevent reverse insertion.

The SOIC and battery packages are shipped separately in plastic anti-static tubes or in tape

& reel form. For the 28-lead SOIC, the battery package (e.g., SNAPHAT) part number is

“M4Z28-BR00SH1” (SNAPHAT housing for 48 mAh battery) or “M4Z32-BR00SH1”

(SNAPHAT housing for 120 mAh battery).

Figure 1. Logic diagram

AI02238B

THS

VCC

M40Z111

M40Z111W

ECON

VSS

VOUT

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Description M40Z111, M40Z111W

6/20 Doc ID 5676 Rev 5

Table 1. Signal names

Figure 2. SOIC28 connections

THS Threshold select input

EChip enable input

ECON Conditioned chip enable output

VOUT Supply voltage output

VCC Supply voltage

VSS Ground

NC Not connected internally

AI02239B

VCC

NCNC

THS

NCVSS

ECON

VOUT VCC

M40Z111

M40Z111W

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M40Z111, M40Z111W Description

Doc ID 5676 Rev 5 7/20

Figure 3. Hardware hookup

AI02394

VCC

ECON

VSS

VOUT VCC

CMOS

SRAM

x8 or x16

3.0, 3.3, or 5V

THS

0.1µF0.1µF

M40Z111/W

Threshold

1N5817 or

MBR5120T3

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Operation M40Z111, M40Z111W

8/20 Doc ID 5676 Rev 5

2 Operation

The M40Z111/W, as shown in Figure 3 on page 7, can control up to two standard low-power

SRAMs. These SRAMs must be configured to have the chip enable input disable all other

input signals. Most slow, low-power SRAMs are configured like this, however many fast

SRAMs are not. During normal operating conditions, the conditioned chip enable (ECON)

output pin follows the chip enable (E) input pin with timing shown in Table 2 on page 10. An

internal switch connects VCC to VOUT

. This switch has a voltage drop of less than 0.3 V

(IOUT1).

When VCC degrades during a power failure, ECON is forced inactive independent of E. In this

situation, the SRAM is unconditionally write protected as VCC falls below an out-of-tolerance

threshold (VPFD). The power fail detection value associated with VPFD is selected by the

THS pin and is shown in Table 6 on page 13.

Note: The THS pin must be connected to either VSS or VOUT

If chip enable access is in progress during a power fail detection, that memory cycle

continues to completion before the memory is write protected. If the memory cycle is not

terminated within time tWP

, ECON is unconditionally driven high, write protecting the SRAM.

A power failure during a write cycle may corrupt data at the currently addressed location, but

does not jeopardize the rest of the SRAM's contents. At voltages below VPFD (min), the user

can be assured the memory will be write protected provided the VCC fall time exceeds tF

As VCC continues to degrade, the internal switch disconnects VCC and connects the internal

battery to VOUT

. This occurs at the switchover voltage (VSO). Below the VSO, the battery

provides a voltage VOHB to the SRAM and can supply current IOUT2 (see Ta ble 6 o n

page 13). When VCC rises above VSO, VOUT is switched back to the supply voltage. Output

ECON is held inactive for tER (200 ms maximum) after the power supply has reached VPFD,

independent of the E input, to allow for processor stabilization (see Figure 5 on page 9).

2.1 Data retention lifetime calculation

Most low power SRAMs on the market today can be used with the M40Z111/W NVRAM

SUPERVISOR. There are, however some criteria which should be used in making the final

choice of which SRAM to use. The SRAM must be designed in a way where the chip enable

input disables all other inputs to the SRAM. This allows inputs to the M40Z111/W and

SRAMs to be “Don't Care” once VCC falls below VPFD (min). The SRAM should also

guarantee data retention down to VCC = 2.0 V. The chip enable access time must be

sufficient to meet the system needs with the chip enable propagation delays included. If the

SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT

. If data

retention lifetime is a critical parameter for the system, it is important to review the data

retention current specifications for the particular SRAMs being evaluated. Most SRAMs

specify a data retention current at 3.0 V.

Manufacturers generally specify a typical condition for room temperature along with a worst

case condition (generally at elevated temperatures). The system level requirements will

determine the choice of which value to use. The data retention current value of the SRAMs

can then be added to the ICCDR value of the M40Z111/W to determine the total current

requirements for data retention.

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M40Z111, M40Z111W Operation

Doc ID 5676 Rev 5 9/20

The available battery capacity for the SNAPHAT® of your choice can then be divided by this

current to determine the amount of data retention available (see Table 11 on page 18). For

more information on battery storage life refer to the application note AN1012.

Figure 4. Power-down timing

Figure 5. Power-up timing

AI02396

VCC

ECON

tFB

VOHB

VPFD (max)

VPFD (min)

VSO

tWPT

VPFD

AI02397

VCC

ECON

tER

tRB

VOHB

VPFD (max)

VPFD (min)

VSO

VPFD

tEDLtEDH

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Operation M40Z111, M40Z111W

10/20 Doc ID 5676 Rev 5

Table 2. Power down/up AC characteristics

2.2 VCC noise and negative going transients

ICC transients, including those produced by output switching, can produce voltage

fluctuations, resulting in spikes on the VCC bus. These transients can be reduced if

capacitors are used to store energy which stabilizes the VCC bus. The energy stored in the

bypass capacitors will be released as low going spikes are generated or energy will be

absorbed when overshoots occur. A ceramic bypass capacitor value of 0.1 µF (as shown in

Figure 6) is recommended in order to provide the needed filtering.

In addition to transients that are caused by normal SRAM operation, power cycling can

generate negative voltage spikes on VCC that drive it to values below VSS by as much as

one volt. These negative spikes can cause data corruption in the SRAM while in battery

backup mode. To protect from these voltage spikes, STMicroelectronics recommends

connecting a Schottky diode from VCC to VSS (cathode connected to VCC, anode to VSS).

Schottky diode 1N5817 is recommended for through hole and MBRS120T3 is

recommended for surface mount.

Figure 6. Supply voltage protection

Symbol Parameter(1)

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except

where noted).

Min Max Unit

tF(2)

2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring

until 200 µs after VCC passes VPFD (min).

VPFD (max) to VPFD (min) VCC fall time 300 µs

tFB(3)

3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.

VPFD (min) to VSS VCC fall time 10 µs

tRVPFD (min) to VPFD (max) VCC rise time 10 µs

tRB VSS to VPFD (min) VCC rise time 1 µs

tEDL Chip enable propagation delay M40Z111 15 ns

M40Z111W 20 ns

tEDH Chip enable propagation delay M40Z111 10 ns

M40Z111W 20 ns

tER(4)

4. tER (min) = 20 ms for industrial temperature range - grade 6 device.

Chip enable recovery 40 200 ms

tWPT Write protect time M40Z111 40 150 µs

M40Z111W 40 250 µs

AI00622

VCC

0.1µF DEVICE

VCC

VSS

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M40Z111, M40Z111W Maximum ratings

Doc ID 5676 Rev 5 11/20

3 Maximum ratings

Stressing the device above the rating listed in the absolute maximum ratings table may

cause permanent damage to the device. These are stress ratings only and operation of the

device at these or any other conditions above those indicated in the operating sections of

this specification is not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability.

Table 3. Absolute maximum ratings

Caution: Negative undershoots below –0.3 V are not allowed on any pin while in the battery backup

mode.

Caution: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.

Symbol Parameter Value Unit

TAAmbient operating temperature Grade 6 –40 to 85 °C

TSTG Storage temperature (VCC off) SNAPHAT®–40 to 85 °C

SOIC –55 to 125 °C

TSLD(1)

1. For SO package, lead-free (Pb-free) lead finish: reflow at peak temperature of 260 °C (the time above

255 °C must not exceed 30 seconds).

Lead solder temperature for 10 seconds 260 °C

VIO Input or output voltages –0.3 to VCC +0.3 V

VCC

Supply voltage M40Z111 –0.3 to 7.0 V

M40Z111W –0.3 to 4.6 V

IOOutput current 20 mA

PDPower dissipation 1 W

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DC and AC parameters M40Z111, M40Z111W

12/20 Doc ID 5676 Rev 5

4 DC and AC parameters

This section summarizes the operating and measurement conditions, as well as the DC and

AC characteristics of the device. The parameters in the following DC and AC characteristic

tables are derived from tests performed under the measurement conditions listed in Table 4:

DC and AC measurement conditions. Designers should check that the operating conditions

in their projects match the measurement conditions when using the quoted parameters.

Table 4. DC and AC measurement conditions

Note: Note that Output Hi-Z is defined as the point where data is no longer driven.

Figure 7. AC testing load circuit

1. 50 pF for M40Z111W.

Table 5. Capacitance

Parameter M40Z111 M40Z111W

VCC supply voltage 4.5 to 5.5 V 2.7 to 3.6 V

Ambient operating temperature –40 to 85 °C –40 to 85 °C

Load capacitance (CL) 100 pF 50 pF

Input rise and fall times ≤ 5 ns ≤ 5 ns

Input pulse voltages 0 to 3 V 0 to 3 V

Input and output timing ref. voltages 1.5 V 1.5 V

Symbol Parameter(1)(2)

1. Effective capacitance measured with power supply at 5 V (M40Z111) or 3.3 V (M40Z111W); sampled only,

not 100% tested.

2. At 25 °C, f = 1 MHz.

Min Max Unit

CIN Input capacitance - 8 pF

COUT(3)

3. Outputs deselected

Output capacitance - 10 pF

AI02326

CL = 100pF(1)

or 5pF

CL includes JIG capacitance

645Ω

DEVICE

UNDER

TEST

1.75V

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M40Z111, M40Z111W DC and AC parameters

Doc ID 5676 Rev 5 13/20

Table 6. DC characteristics

Sym Parameter Test condition(1)

1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = 4.5 to 5.5 V or 2.7 to 3.6 V (except where noted).

M40Z111 M40Z111W

Unit

Min Typ Max Min Typ Max

ICC Supply current Outputs open 3 6 2 4 mA

ICCDR

Data retention mode

current 150 150 nA

ILI Input leakage current 0 V ≤ VIN ≤ VCC ±1 ±1 µA

ILO(2)

2. Outputs deselected.

Output leakage current 0 V ≤ VOUT ≤ VCC ±1 ±1 µA

IOUT1 VOUT current (active) VOUT > VCC –0.3 160 100 mA

VOUT > VCC –0.2 100 65 mA

IOUT2

VOUT current (battery

backup) VOUT > VBAT –0.3 100 100 µA

VBAT Battery voltage 2.0 3.0 3.5 2.0 3.0 3.5 V

VIH Input high voltage 2.2 VCC + 0.3 2.0 VCC +

0.3 V

VIL Input low voltage –0.3 0.8 –0.3 0.8 V

VOH Output high voltage IOH = –2.0 mA 2.4 2.4 V

VOHB VOH battery backup IOUT2 = –1.0 µA 2.0 2.9 3.6 2.0 2.9 3.6 V

VOL Output low voltage IOL = 4.0 mA 0.4 0.4 V

THS Threshold select voltage VSS VOUT VSS VOUT V

VPFD

Power-fail deselect

voltage (THS = VSS)4.50 4.60 4.75 2.80 2.90 3.00 V

Power-fail deselect

voltage (THS = VOUT)4.20 4.35 4.50 2.50 2.60 2.70 V

VSO

Battery back-up

switchover voltage 3.0 VPFD –

100 mV V

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Package mechanical data M40Z111, M40Z111W

14/20 Doc ID 5676 Rev 5

5 Package mechanical data

In order to meet environmental requirements, ST offers these devices in different grades of

ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®

specifications, grade definitions and product status are available at: www.st.com.

ECOPACK® is an ST trademark.

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M40Z111, M40Z111W Package mechanical data

Doc ID 5676 Rev 5 15/20

Figure 8. SOH28 – 28-lead plastic small outline, 4-socket battery SNAPHAT,

package outline

Note: Drawing is not to scale.

SOH-A

LA1 α

Table 7. SOH28 – 28-lead plastic small outline, battery SNAPHAT, pack. mech. data

Symbol

mm inches

Typ Min Max Typ Min Max

A 3.05 0.120

A1 0.05 0.36 0.002 0.014

A2 2.34 2.69 0.092 0.106

B 0.36 0.51 0.014 0.020

C 0.15 0.32 0.006 0.012

D 17.71 18.49 0.697 0.728

E 8.23 8.89 0.324 0.350

e 1.27 – – 0.050 – –

eB 3.20 3.61 0.126 0.142

H 11.51 12.70 0.453 0.500

L 0.41 1.27 0.016 0.050

a0°8°0°8°

N28 28

CP 0.10 0.004

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Package mechanical data M40Z111, M40Z111W

16/20 Doc ID 5676 Rev 5

Figure 9. 4-pin SNAPHAT housing for 48 mAh battery, package outline

Note: Drawing is not to scale.

Table 8. 4-pin SNAPHAT housing for 48 mAh battery, package mechanical data

SHZP-A

A1 A

Symbol

mm inches

Typ Min Max Typ Min Max

A 9.78 0.385

A1 6.73 7.24 0.265 0.285

A2 6.48 6.99 0.255 0.275

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 14.22 14.99 0.560 0.590

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

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M40Z111, M40Z111W Package mechanical data

Doc ID 5676 Rev 5 17/20

Figure 10. 4-pin SNAPHAT housing for 120 mAh battery, package outline

Note: Drawing is not to scale.

Table 9. 4-pin SNAPHAT housing for 120 mAh battery, package mechanical data

SHZP-A

A1 A

Symbol

mm inches

Typ Min Max Typ Min Max

A 10.54 0.415

A1 8.00 8.51 0.315 0.335

A2 7.24 8.00 0.285 0.315

A3 0.38 0.015

B 0.46 0.56 0.018 0.022

D 21.21 21.84 0.835 0.860

E 17.27 18.03 0.680 0.710

eA 15.55 15.95 0.612 0.628

eB 3.20 3.61 0.126 0.142

L 2.03 2.29 0.080 0.090

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Part numbering M40Z111, M40Z111W

18/20 Doc ID 5676 Rev 5

6 Part numbering

Table 10. Ordering information scheme

Caution: Do not place the SNAPHAT battery package “M4ZXX-BR00SH” in conductive foam as this

will drain the lithium button-cell battery.

For a list of available options (e.g., speed, package) or for further information on any aspect

of this device, please contact the ST sales office nearest to you.

Table 11. Battery table

Example: M40Z 111W MH 6 E

Device type

M40Z

Supply voltage and write protect voltage

111(1) = VCC = 4.5 to 5.5 V; VPFD = 4.3 to 4.5 V

1. Not recommended for new design. Contact local ST sales office for availability.

THS = VSS = 4.5 ≤ VPFD ≤ 4.75 V

THS = VOUT = 4.2 ≤ VPFD ≤ 4.5 V

111W(1) = VCC = 2.7 to 3.6V; VPFD = 2.6 to 2.7 V

THS = VSS = 2.8 ≤ VPFD ≤ 3.0 V

VCC = 2.7 to 3.3 V

THS = VOUT = 2.5 ≤ VPFD ≤ 2.7 V

Package

MH(2) = SOH28

2. The SOIC package (SOH28) requires the battery package (SNAPHAT®) which is ordered separately under

the part number “M4ZXX-BR00SHX” in plastic tubes or “M4ZXX-BR00SHXTR” in tape & reel form.

Temperature range

6 = –40 to 85 °C

Shipping method for SOIC

E = Lead-free ECOPACK® package, tubes

F = Lead-free ECOPACK® package, tape & reel

Part number Description Package

M4Z28-BR00SH1 SNAPHAT housing for 48 mAh battery SH

M4Z32-BR00SH1 SNAPHAT housing for 120 mAh battery SH

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M40Z111, M40Z111W Revision history
Doc ID 5676 Rev 5 19/20
7 Revision history
Table 12. Document revision history
Date Revision Changes
Sep-2000 1 First Draft Issue
14-Sep-2001 2
Reformatted, TOC added, changed DC Characteristics (Ta b l e 6 ); 
changed battery, ind. temperature information (Ta bl e 3 , 2, 10, 11, 
Figure 9, 10); Corrected SOIC label (Figure 2); added E2 to Hookup 
(Figure 3)
13-May-2002 3 Modify reflow time and temperature footnote (Ta bl e 3 )
12-Nov-2007 4
Reformatted document; added lead-free second level interconnect 
information to cover page and Section 5: Package mechanical data; 
updated Figure 5, Ta b l e 3 , 10, 11.
15-Dec-2010 5
Devices are not recommended for new design, updated document 
status and Ta bl e 1 0 ; updated footnote in Ta b l e 3 ; updated ECOPACK® 
text in Section 5: Package mechanical data; reformatted document.
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M40Z111, M40Z111W

20/20 Doc ID 5676 Rev 5

Please Read Carefully:

Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the

right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any

time, without notice.

All ST products are sold pursuant to ST’s terms and conditions of sale.

Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no

liability whatsoever relating to the choice, selection or use of the ST products and services described herein.

No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this

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