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D1.25 Gigabits Per Second (Gbps) Gigabit
Ethernet Transceiver
DBased on the P802.3Z Specification
DTransmits Serial Data up to 1.25 Gbps
DOperates With 3.3-V Supply Voltage
D5-V Tolerant on TTL Inputs
DInterfaces to Electrical Cables/Backplane or
Optical Modules
DPECL Voltage Differential Signaling Load,
1 V Typ With 50 Ω − 75 Ω
DReceiver Differential Input Voltage
200 mV Minimum
DLow Power Consumption
D64-Pin Quad Flat Pack With Thermally
Enhanced Package
description
The TNETE2201B gigabit Ethernet transceiver provides for ultra high-speed bidirectional point-to-point data
transmission. This device is based on the timing requirements of the proposed 10-bit interface specification by
the P802.3z Gigabit Task Force.
1718 19
RC0
SYNC
GND_TTL
RD0
RD1
RD2
VCC_TTL
RD3
RD4
RD5
RD6
VCC_TTL
RD7
RD8
RD9
GND_TTL
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND_CMOS
TD0
TD1
TD2
VCC_CMOS
TD3
TD4
TD5
TD6
VCC_CMOS
TD7
TD8
TD9
GND_CMOS
GND_TX
TC1 21 22 23 24
DIN_RXP
63 62 61 60 5964 58
DOUT_TXP
DOUT_TXN
GND_CMOS
GND_A
RESERVED
LCKREFN
LOOPEN
GND_A
REFCLK
SYNCEN
GND_CMOS
56 55 5457
25 26 27 28 29
53 52
TC0
DIN_RXN
51 50 49
30 31 32
RBC1
RBC0
GND_A
GND_RX
RC1
GND_A
VCC_TX
VCC_A
VCC_CMOS
VCC_A
VCC_A
VCC_RX
VCC_A
VCC_A
VCC_A
VCC_A
VCC_A
VCC_A
PHD, PJD, OR PJW PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
! "#$ ! %#&'" ($)
(#"! " !%$""! %$ *$ $! $+! !#$!
!(( ,- (#" %"$!!. ($! $"$!!'- "'#($
$!. '' %$$!
Copyright 1999 − 2007, Texas Instruments Incorporated
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description (continued)
The intended application of this device is to provide building blocks for developing point-to-point baseband data
transmission over controlled-impedance media of approximately 50 Ω to 75 Ω. The transmission media can be
printed-circuit board traces, back planes, cables, or fiber optical media. The ultimate rate and distance of data
transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the
environment.
The TNETE2201B performs the data serialization and deserialization (SERDES) functions for the gigabit
ethernet physical layer interface. The transceiver operates at 1.25 Gbps (typical), providing up to 1000 Mbps
of bandwidth over a copper or optical media interface. The serializer/transmitter accepts 8b/10b parallel
encoded data bytes. The parallel data bytes are serialized and transmitted differentially nonreturn-to-zero
(NRZ) at pseudo-ECL (PECL) voltage levels. The deserializer/receiver extracts clock information from the input
serial stream and deserializes the data, outputting a parallel 10-bit data byte. The 10-bit data bytes are output
with respect to two receive byte clocks (RBC0, RBC1), allowing a protocol device to clock the parallel bytes in
RBC clock rising edges.
The transceiver automatically locks onto incoming data without the need to prelock. However, the transceiver
can be commanded to lock to the externally supplied reference clock (REFCLK) as a reset function, if needed.
The TNETE2201B provides an internal loopback capability for self-test purposes. Serial data from the serializer
is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.
The TNETE2201B is characterized for operation from 0°C to 70°C.
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functional block diagram
LOOPEN
TD0 − TD9 10-Bit
Register
10
/10
/Shift
Register
REFCLK Clock
Multiplier
2:1
MUX
Synchronous
Detect
SYNCEN
SYNC
RD0 − RD9 10-Bit
Register
10
/10
/Shift
Register
PLL Clock
Recovery and
Data Retiming
÷ 2 125 MHz
125 MHz
62.5 MHz
62.5 MHz
RBC0
RBC1
RX+
RX−
TX+
TX−
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I/O structures
_
+
VCM
VDD
VDD
100 Ω
4 kΩ
4 kΩ
DIN_RXP
DIN_RXN
VDD
VDD
DOUT_TXP
DOUT_TXN
PECL inputs (DIN_RXP, DIN_RXN) PECL outputs (DIN_TXP, DIN_TXN)
CMOS inputs (TD0 − TD9, LOOPEN, REFCLK, SYNCEN, LCKREFN)
VDD
R2
R1
VDD
120 Ω
Input
REFCLK, TD0 − TD9
LOOPEN
SYNCEN, LCKREFN
R1 R2
Open Circuit Open Circuit
Open Circuit
Open Circuit
400 kΩ
400 kΩ
TERMINALS
P
N
CMOS outputs (RD0 − RD9, RBC0, RBC1, SYNC) VDD
Output
P
N
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Terminal Functions
TERMINAL
DESCRIPTION
NAME NO. TYPE
DESCRIPTION
I/O and DATA
DOUT_TXP
DOUT_TXN 62
61 Output Differential output transmit. DOUT_TXP and DOUT_TXN are differential serial outputs that interface
to a copper or an optical I/F module. These terminals transmit NRZ data at a rate of 1.25 Gbps.
DOUT_TXP and DOUT_TXN are held static when LOOPEN is high and are active when LOOPEN is
low.
DIN_RXP
DIN_RXN 54
52 Input Differential input receive. DIN_RXP and DIN_RXN together are the differential serial input interface
from a copper or an optical I/F module. These terminals receive NRZ data at a rate of 1.25 Gbps and
are active when LOOPEN is held low.
LCKREFN 27 Input Lock to reference. When LCKREFN is asserted low, the receive PLL phase locks to the supplied
REFCLK signal. LCKREFN prelocks or resets the receive PLL.
LOOPEN 19 Input Loop enable. When LOOPEN is high (active), the internal loop-back path is activated. The
transmitted serial data is directly routed to the inputs of the receiver. This provides a self-test
capability in conjunction with the protocol device. The DOUT_TXP and DOUT_TXN outputs are held
static during the loop-back test. LOOPEN is held low during standard operational state with external
serial outputs and inputs active.
RBC0
RBC1 31
30 Output Receive byte clock. RBC0 and RBC1 are 62.5-MHz recovered clocks used for synchronizing the
10-bit output data on RD0 − RD9. The 10-bit output data words are valid on the rising edges of RBC0
and RBC1. These clocks are adjusted to half-word boundaries in conjunction with synchronous
detect. The clocks are always expanded during data realignment and never slivered or truncated.
RBC0 registers bytes 1 and 3 of received data. RBC1 registers bytes 0 and 2 of received data.
RC1,
RC0 49
48 Analog Receive capacitor. RC0 and RC1 are external capacitor connections used for the receiver internal
PLL filter. The recommend value for this external capacitor is 2 n F ( a value of 0.1 µF can also be used,
see Note 1).
RD0 − RD9 45,44,43,41
40,39,38,36
35,34
Output Receive data. These outputs carry 10-bit parallel data output from the transceiver to the protocol
layer. The data is referenced to terminals RBC0 and RBC1. Received data byte 0, which contains the
K28.5 character, is byte aligned to the rising edge of RBC1. RD0 is the first bit received.
REFCLK 22 Input Reference clock. REFCLK is an external 125 MHz input clock that synchronizes the receiver and
transmitter interfaces. The transmitter uses this clock to register the 10-bit input data (TD0..TD9) for
serialization. REFCLK is also used as a RX PLL preset or reference when LCKREFN is enabled.
SYNC 47 Output Synchronous detect. SYNC is asserted high upon detection of the K28.5 character in the serial data
path. SYNC is a high level for 1/2 REFCLK period. SYNC pulses are output only when SYNCEN is
activated (asserted high). Note: SYNC is active on byte0 and, therefore, active on rising edge of
RCB1.
SYNCEN 24 Input Synchronous function enable. When SYNCEN is asserted high, the internal synchronization function
is activated. When this function is enabled, the transceiver detects the K28.5 character (0011111010
negative beginning disparity) in the serial data stream and realigns data on byte boundaries if
required. When SYNCEN is low, serial input data is unframed in RD0 − RD9.
TC1
TC0 16
17 Analog Transmit capacitor. TC0 and TC1 are external capacitor connections used for the transmitter internal
PLL filter. The recommended value of this external capacitor is 2 nF (a value of 0.1 µF can also be
used, see Note 1).
TD0 − TD9 2,3,4,6
7,8,9,11
12,13
Input Transmit data. These inputs carry 10-bit parallel data output from a protocol device to the transceiver
for serialization and transmission. This 10-bit parallel data is clocked into the transceiver on the rising
edge of REFCLK and transmitted as a serial stream with TD0 sent as the first bit.
NOTE 1: A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due
to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage
supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power
supply noise.
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Terminal Functions (Continued)
TERMINAL
DESCRIPTION
NAME NO. TYPE
DESCRIPTION
POWER
VCC_A 20,28,29,53
55,57,59,60
63
Supply Analog power. VCC_A provides a supply reference voltage for the high-speed analog circuits.
VCC_CMOS 5,10,23, Supply Digital PECL logic power. VCC_CMOS provides an isolated low-noise power supply for the logic
circuits.
VCC_RX 50 Supply Receiver power. VCC_RX provides a low-noise supply reference voltage for the receiver high-speed
analog circuits.
VCC_TTL 42,37 Supply TTL power. VCC_TTL provides a supply reference voltage for the receiver TTL circuits.
VCC_TX 18 Supply Transmitter power. VCC_TX provides a low-noise supply reference voltage for the transmitter
high-speed analog circuits.
GROUND
GND_A 21,32,56,64 Ground Analog ground. GND_A provides a ground reference for the high-speed analog circuits.
GND_CMOS 1,14,
25,58 Ground Digital PECL logic ground. GND_CMOS provides an isolated low-noise ground for the logic circuits.
GND_RX 51 Ground Receiver ground. GND_RX provides a ground reference for the receiver circuits.
GND_TTL 33,46 Ground TTL circuit ground. GND_TTL provides a ground for TTL interface circuits.
GND_TX 15 Ground Transmitter ground. GND_TX provides a ground reference for the transmitter circuits.
MISCELLANEOUS
RESERVED 26 Reserved. Internally pulled to GND, leave open or assert low.
detailed description
data transmission
The transmitter registers incoming 10-bit-wide data words (8b/10b encoded data, TD0...TD9) on the rising edge
of REFCLK (125 MHz). The reference clock is also used by the serializer, which multiplies the clock by a factor
of 10 providing a 1.25 Gbaud signal that is fed to the shift register. The data is then transmitted differentially at
PECL voltage levels. The 8b/10b encoded data is transmitted sequentially bit 0 through 9.
transmission latency
The data transmission latency of the TNETE2201B is defined as the delay from the initial 10-bit word load to
the serial transmission of bit 9. The typical transmission latency is 9 ns.
data reception
The receiver of the TNETE2201B deserializes 1.25 Gbps differential serial data. The 8b/10b data (or equivalent)
is retimed based on an extracted clock from the serial data. The serial data is then aligned to the 10-bit word
boundaries and presented to the protocol controller along with two receive byte clocks (RBC0, RBC1). RBC0
and RBC1 are 180 degrees out of phase and are generated by dividing down the recovered 1.25 Gbps
(625 MHz) clock by 10 providing for two 62.5-MHz signals. The receiver presents the protocol device byte 0 of
the received data valid on the rising edge of RBC1.
NOTE:
This allows the option of byte alignment without the use of the synchronous detection
(SYNC) function by the protocol device.
The receiver PLL can lock to the incoming 1.25 GHz data without the need for a lock-to-reference preset. The
received serial data rate (RX+ and RX−) should be 1.25 Gbps ±0.01% (100 ppm) for proper operation.
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data reception (continued)
During a bus error condition or word alignment, the receive byte clocks RBC0 and RBC1 are stretched (never
truncated). When the incoming serial data does not meet its frequency requirements, then the receive byte clock
frequency is maintained at 62.5 MHz.
receive PLL operation
The receive PLL provides automatic locking to the incoming data. At power up, the maximum initial lock time
is 500 µs. The PLL can also be initiated or set to phase lock to the externally supplied reference clock by enabling
lock-to-reference (LCKREFN). The lock-to-reference causes the receive PLL to lock to 10× the reference clock
(REFCLK) input providing a PLL preset and reset capability.
If during normal operation a transient occurs, which is defined as any arbitrary phase shift in the incoming data
and/or a frequency wander of up to 200 ppm, then the PLL recovers lock within 2.4 µs. Any condition exceeding
these values is considered a power-up scenario and the PLL recovers lock within 500 µs with a 0.1 µF capacitor
the PLL recovers lock within 10 ms on power up (see the following note).
NOTE:
A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking
bandwidth o f the PLL will be reduced due to the larger filter capacitor. This reduces the transmit and
receive PLL’s ability to reject low-frequency noise or wonder in the voltage supply or datastream.
Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50)
to reject power supply noise.
receiver word alignment
The TNETE2201B uses a 10-bit K28.5 character (comma character) word alignment scheme. The following
sections explain how this scheme works and how it realigns itself.
comma character on expected boundary
The TNETE2201B provides 10-bit K28.5 character recognition and word alignment. The 10-bit word alignment
is enabled by forcing SYCNEN high. This enables the function that examines and compares ten bits of serial
input data to the K28.5 synchronization character. The K28.5 character is defined in the fibre channel standard
as a pattern consisting of 0011111010 (a negative number beginning disparity) with the 7 MSBs (0011111)
referred to a s the comma character. The K28.5 character was implemented specifically for aligning data words.
As long as the K28.5 character falls within the expected 10-bit word boundary, the received 10-bit data is
properly aligned and data realignment is not required. Figure 1 shows the timing characteristics of RBC0, RBC1,
SYNC and RD0 − RD9 while synchronized.
NOTE:
The K28.5 character is valid on the rising edge of RBC1.
RBC0
RD0 − RD9
RBC1
SYNC
K28.5 Dxx.x Dxx.x Dxx.x K28.5 Dxx.x
Figure 1. Synchronous Timing Characteristics Waveforms
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comma character not on expected boundary
When synchronization is enabled and a K28.5 character straddles the expected 10-bit word boundary, then
word realignment is necessary. Realignment or shifting the 10-bit word boundary truncates the character
following the misaligned K28.5, but the following K28.5 and all subsequent data is aligned properly as shown
in Figure 2. The 10b specification requires that RCLK cycles can not be truncated and can only be stretched
or stalled in their current state during realignment. With this design the maximum stretch that occurs is an extra
10 bit times. This occurs during a worst case scenario when the K28.5 is aligned to the falling edge of RBC1
instead of the rising edge. This system transmits a minimum of three consecutively ordered K28.5 data sets
between frames and ensures that the receiver sees at least two of K28.5 sets (the fabric is allowed to drop one).
Figure 2 shows the timing characteristics of the data realignment.
Systems that do not require framed data can disable byte alignment by tying SYNCEN low.
When a synchronization character is detected the SYNC signal is asserted high and is aligned with the K28.5
character. The duration of the SYNC-signal pulse is equal to the duration of the data which is half an RCLK
period.
RBC0
RBC1
SYNC
Serial Rx Data Stream
DIN_RxP − DIN_RxN K28.5 Dxx.x Dxx.x Dxx.xK28.5 Dxx.x
RD0 − RD9 K28.5 Dxx.x Dxx.x Dxx.x
Dxx.x K28.5
20 Bit Times
(MAX)
Typical Receive
Path Latency = 18 ns
Dxx.x Dxx.x Dxx.x
Worst Case
Misaligned K28.5
Corrupted Data
Misalignment
Corrected
10 Bit Times
10 Bit Times
Dxx.x K28.5
K28.5Dxx.x
K28.5
Figure 2. Word Realignment Timing Characteristics Waveforms
data reception latency
The serial-to-parallel data latency is the time from when the first bit arrives at the receiver until it is output in the
aligned parallel word with RD0 received as first bit. The receive latency is typically 18 ns.
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loop-back testing
The transceiver can provide a self-test function by enabling (LOOPEN to high level) the internal loop-back path.
Enabling LOOPEN causes serially transmitted data to be routed internally to the receiver. The parallel data
output can be compared to the parallel input data for functional verification. The external differential output is
held in a static state during loop-back testing.
absolute maximum ratings†
Supply voltage, VCC (see Note 2) −0.5 to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (TTL, PECL) −0.5 to 4.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current IO, (TTL) 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current IO, (PECL) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range at any terminal −0.5 to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge, 5-V tolerant input terminals (see Note 3) Class 1, A:1 kV, B:150 V. . . . . . . . . . . . . .
Electrostatic discharge, all other terminals (see Note 3) Class 1, A:2 kV, B:200 V. . . . . . . . . . . . . . . . . . . . . .
Characterized free-air operating temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 2. All voltage values, except differential I/O bus voltages, are with respect to network ground.
3. This parameter is tested in accordance with MIL-PRF-38535.
recommended operating conditions
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Supply voltage, VCC 3.14 3.3 3.47 V
Supply current, ICC (static) Static pattern†180 260 mA
Power dissipation, PD (static) Outputs open, Static pattern†590 900 mW
Supply current, ICC (dynamic) K28.5 240 330 mA
Power dissipation, PD (dynamic) Outputs open, K28.5 790 1150 mW
Operating free-air temperature, TA0 70 °C
†Power (static pattern) = 125 MHz to the receiver and 5 ones and 5 zeros to the transmitter.
reference clock (REFCLK) timing requirements over recommended operating conditions (unless
otherwise noted)†
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
Frequency TYP −
0.01% 125 TYP +
0.01% MHz
Accuracy −100 100 ppm
Duty cycle 40% 50% 60%
Jitter Random and deterministic 40 ps
†This clock should be crystal referenced to meet the requirements of the this table. The maximum rate of frequency change specified is valid after
10 seconds from power on.
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electrical characteristics over recommended operating conditions (unless otherwise noted)
TTL Signals: TD0 .. TD9, REFCLK, LOOPEN, SYNCEN, SYNC, RD0 .. RD9, RBC0, RBC1, LCKREFN
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage VCC = MIN, IOH = −400 µA 2.4 3 V
VOL Low-level output voltage VCC = MIN, IOL = 1 mA 0.25 0.4 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IIH
High-level input current
VCC = MAX, VI = 2.4 V 40 µA
IIH High-level input current REFCLK VCC = MAX, VI = 2.4 V 900 µA
IIL
Low-level input current
VCC = MAX, VI = 0.4 V −40 µA
IIL Low-level input current REFCLK VCC = MAX, VI = 0.4 V −900 µA
ciInput capacitance 4 pF
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TRANSMITTER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VODP
Driver differential output voltage (peak) (TXP − TXN)
RL = 75 Ω,See Figure 3 550 1100
mV
VODPDriver differential output voltage (peak) (TXP − TXN)RL = 50 Ω,See Figure 3 550 1100 mV
VOC Driver common-mode output voltage RL = 75 Ω2100 mV
differential switching characteristics over recommended operating conditions (unless otherwise
noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Serial data deterministic jitter (peak-to-peak) Differential output jitter 80 ps
Serial data total jitter (peak-to-peak) Differential output jitter 192 ps
tr3 Differential signal rise time (20% to 80%) R
L
= 75 Ω,
See Figure 3
C
L
= 5 pF, 300 ps
tf3 Differential signal fall time (20% to 80%)
RL = 75 ,
See Figure 3
CL = 5 pF,
300 ps
50%
20%
80% ≈VCC − 0.7 V
≈VCC − 1.6 V
tf
tr
TX+
50%
20%
80% ≈VCC − 0.7 V
≈VCC − 1.6 V
tr
tf
TX−
20%
80%
tf3
tr3
VOD
|VOD|P
0 V
Figure 3. Differential and Common-Mode Output Voltage Definitions
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transmitter timing requirements over recommended operating conditions (unless otherwise
noted)
TEST CONDITIONS MIN NOM MAX UNIT
tsu1 Setup time, TD0 − TD9 valid to REFCLK ↑See Figure 4 2 ns
th1 Hold time, REFCLK ↑ to TD0 − TD9 invalid See Figure 4 1 ns
Parallel-to-serial data latency 9 ns
transmit interface timing
The transmit interface is defined in the 10 b spec as the 10-bit parallel data input to the physical layer for serial
transmission. The timing values are specified from REFCLK midpoint to valid input signal levels or from valid
input signal levels to REFCLK midpoint.
TD0 − TD9
ÉÉÉÉÉÉ
ÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
ÉÉÉÉÉÉÉ
Valid Valid Valid
50%
tsu1 th1
REFCLK
Figure 4. Transmit 10-Bit Interface Timing Waveforms
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RECEIVER SECTION
differential electrical characteristics over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|VID|PReceive input voltage (peak) (RXP − RXN)See Figure 5 200 1300 mV
receiver and phase-locked loop performance characteristics over recommended operating
conditions (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT†
Jitter tolerance See P802.3Z specification 74.9% UI
From power up at 2 nF capacitor value 500 µs
Data acquisition lock time From power up at 0.1 µF capacitor value
(See Note 4) 10 ms
Data relock time From synchronization loss 2500 ns
†UI is the unit interval of a single bit (800 ps).
NOTE 4: A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced due
to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the voltage
supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to reject power
supply noise.
receive clock timing requirements over recommended operating conditions (unless otherwise
noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fclk Clock frequency, RBC0 62.5 MHz
fclk Clock frequency, RBC1 (180 deg out of phase with RBC0) 62.5 MHz
tr4 Data rise time See Figure 6 0.7 4 ns
tf4 Data fall time See Figure 6 0.7 4 ns
tr5 Rise time, single-ended output signal on RBC0 or RBC1 See Figure 6 0.7 2 ns
tf5 Fall time, single-ended output signal on RBC0 or RBC1 See Figure 6 0.7 2 ns
Duty cycle, RBC0 or RBC1 40% 60%
t(skew) Skew time, RBC1 ↑ to RBC0 ↑See Figure 7 7.5 8 8.5 ns
tsu2 Setup time, RD0 − RD9, SYNC valid to RBC0 ↑See Figure 7 2.5 ns
tsu3 Setup time, RD0 − RD9, SYNC valid to RBC1 ↑See Figure 7 2.5 ns
tsu4 Setup time, RBC1 ↑ to RD0 − RD9, SYNC invalid See Figure 7 1.5 ns
tsu5 Setup time, RBC1 ↑ to RD0 − RD9, SYNC invalid See Figure 7 1.5 ns
Serial-to-parallel data latency 18 ns
†t(drift) is the minimum time for RBC0 or RBC1 to drift from 63.5 MHz to 64.5 MHz or from 60 MHz to 59 MHz from the RCLK lock value. This is
applicable under all input signal conditions with PLL locked to the REFCLK of DATA signals.
|VID|0 V
|VID |P
Figure 5. Differential Input Voltage (Peak-to-Peak) Timing Waveform
SLLS367D − JUNE 1999 − REVISED AUGUST 2007
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Clock
50%
20%
80%
tf4
tr4
Data
50%
20%
80%
tf5
tr5
Figure 6. Receiver Data Measurement Levels
RD0 − RD9, SYNC
ÉÉÉ
ÉÉÉ
ÉÉÉ
ÉÉÉ
Valid
50% 50%
RBC1
50%
RBC0
ÉÉÉ
ÉÉÉ
Valid
ÉÉ
ÉÉ
Valid
ÉÉ
ÉÉ
Valid
ÉÉ
ÉÉ
Valid
tsu3
tsu4
tsu2
tsu5
t(skew)
50%
Figure 7. Receiver Interface Timing Waveforms
SLLS367D − JUNE 1999 − REVISED AUGUST 2007
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Host
Protocol
Device
TD0 − TD9
10
/
REFCLK
LCKREFN
LOOPEN
SYNCEN
SYNC
RD0 − RD9
RBC0,RBC1
RC1
RC0
DOUT_TXP
DOUT_TXN
DIN_RXP
DIN_RXN
TC1
TC0
VCC_TXVCC_RX
Controlled Impedance
Transmission Line
Controlled Impedance
Transmission Line
Controlled Impedance
Transmission Line
Controlled Impedance
Transmission Line
PLL Filter
Capacitor = 2 nF or 0.1 µF
(see Note C)
PLL Filter
Capacitor = 2 nF or 0.1 µF
(see Note C)
TNETE2201B
3.3 V
3.3 V
10
/
2
/
50 18
22
27
19
24
47
31,30
62
61
54
52
49
48
16
17
GND_RX GND_TX
51 15
Ferrite Bead
Ferrite Bead
0.01 µF
0.01 µF
R(pd)
(see Note A)
5 Ω at 100 MHz
50 Ω − 75 Ω
Vt
(see Note B)
NOTES: A. R(pd) − This value is set to match the falling edge to rising edge transistion times, typically 150 Ω. to 220 Ω..
B. Vt (termination voltage): Vt = VCC − 1.3 V, if ac coupled
Vt = VCC − 2 V, if directly coupled.
C. A filter capacitor value of 0.1 µF can be used with the following consideration: The tracking bandwidth of the PLL will be reduced
due to the larger filter capacitor. This reduces the transmit and receive PLL’s ability to reject low-frequency noise or wonder in the
voltage supply or datastream. Care must be taken in the filtering of the supply VCC_TX (terminal 18) and VCC_RX (terminal 50) to
reject power supply noise.
Figure 8. Typical Application Circuit
SLLS367D − JUNE 1999 − REVISED AUGUST 2007
16 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
The TNETE2201B incorporates the latest development in TI’s package line. The new patent-pending design,
designated the PWP, delivers thermal performance comparing to a heat-spreader design in a true low-profile
package. The PWP for the TNETE2201B is designed to maximize heat transfer away from the die through the
top of the chip. As seen in Figures 9 and 10 the bottom of the leadframe is deep downset towards the top of
the chip, providing a thermal path away from the die and board. All this has been accomplished without
exceeding the 1.15 mm height of the TQFP. This package in the 10mm × 10mm TQFP (PJD) provides a thermal
resistance RθJA of 40°C/W and the package in the 14mm × 14mm TQFP (PHD) provides a RθJA of 40°C/W.
Figure 9. Heat-Spreader Design
Figure 10. Leadframe Downset
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
TNETE2201BPHD ACTIVE HTQFP PHD 64 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPHDG4 ACTIVE HTQFP PHD 64 90 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJD ACTIVE HTQFP PJD 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJDG4 ACTIVE HTQFP PJD 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJDR ACTIVE HTQFP PJD 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJDRG4 ACTIVE HTQFP PJD 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJW ACTIVE HTQFP PJW 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJWG4 ACTIVE HTQFP PJW 64 160 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJWR ACTIVE HTQFP PJW 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
TNETE2201BPJWRG4 ACTIVE HTQFP PJW 64 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 9-Aug-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TNETE2201BPJDR HTQFP PJD 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2
TNETE2201BPJWR HTQFP PJW 64 1000 330.0 24.4 13.7 13.7 1.6 16.0 24.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TNETE2201BPJDR HTQFP PJD 64 1000 367.0 367.0 45.0
TNETE2201BPJWR HTQFP PJW 64 1000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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