SY58608UMGTR - Micrel - Datasheet.Live

SY58608U

3.2Gbps Precision, 1:2 LV DS Fanout Buffer

with Inter nal Termination a nd Fail Safe Input

Precision Edge is a registered tradem ark of Micrel, Inc.

Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com

October 2006

M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

General Description

The SY58608U is a 2.5V, high-speed, fully differential

1:2 LVDS fanout buffer optimized to provide two

identical output copies with less than 20ps of skew and

less tha n 10psPP tota l jitter. The SY58 608U can proces s

clock signals as fast as 2GHz or data patterns up to

3.2Gbps.

The differential input includes Micrel’s unique, 3-pin

input termination arc h itec tu re t hat int erf ac es to LV PEC L,

LVDS or CML differential signals, (AC- or DC-coupled)

as small as 100mV (200mVPP) without any level-shifting

or termination resistor networks in the signal path. For

AC-coupled input interface applications, an integrated

voltage reference (VREF-AC) is provided to bias the VT pin.

The outputs are 325mV LVDS, with rise/fall times

guaranteed to be less than 100ps.

The S Y58608U opera tes f rom a 2.5V ±5% suppl y and is

guaranteed over the full industrial temperature range (–

40°C to +85°C). For applications that require CML or

LVPECL outputs, consider Micrel’s SY58606U and

SY58607U, 1:2 fanout buffers with 400mV and 800mV

output swings respectively. The SY58608U is part of

Micrel’s high-speed, Precision Edge® product line.

Data sheets and support documentation can be found

on Micrel’s web site at: www.micrel.com.

Functional Block Diagram

Precision Edge®

Features

• Precision 1:2, 325mV LVDS fanout buffer

• Guaranteed AC performance over temperature and

voltage:

– DC-to > 3.2Gbps throughput

– <300ps propagation delay (IN-to-Q)

– <20ps within-device skew

– <100ps rise/fall times

• Fail Safe Input

– Prevents outputs from oscillating when input is

invalid

• Ultra-low jitter design

– <1psRMS cycle-to-cycle jitter

– <10psPP total jitter

– <1psRMS random jitter

– <10psPP deterministic jitter

• High-speed LVDS outputs

• 2.5V ±5% power supply operation

• Industrial temperature range: –40°C to +85°C

• Available in 16-pin (3mm x 3mm) QFN package

Applications

• All SONET clock and data distribution

• Fibre Channel clock and data distribution

• Gigabit Ether net c lock and data distribut ion

• Backplane dis tri but ion

Markets

• DataCom

• Telecom

• Storage

• ATE

• Test and Measurement

Micrel, Inc.

SY58608U

October 2006 2 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Ordering Information(1)

Part Number Package

Type Operating

Range Package Marking Lead

Finish

SY58608UMG QFN-16 Industrial 608U with Pb-Free

bar-line indicator NiPdAu

Pb-Free

SY58608UMGTR

(2)

QFN-16 Industrial 608U with Pb-Free

bar-line indicator NiPdAu

Pb-Free

Notes:

1. Contact f act ory for die availabi lit y. Dice are guaranteed at TA = 25°C, DC Electricals only.

2. Tape and Reel.

Pin Configuration

16-Pin QFN

Pin Description

Pin Number Pin Name Pin Function

1, 4 IN, /IN Differential Inputs: This input pair is the differential signal input to the device. Input

accepts DC-coupled differential signals as small as 100mV (200mVPP). Each pin of

this pair internally terminates w ith 50Ω to the VT pin. If the input swing falls below a

certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a

stable output by latching the outputs to its last valid state. See “Input Interface

Applicat ion s” sect ion for more details.

2 VT Input Termination Center-Tap: Each input terminates to this pin. The VT pin

provides a center -tap for each input (IN, /IN) to a termination network for maximum

interface flexibility. See “Input Interface Applications” section.

3 VREF-AC Reference Voltage: This output bias to VCC–1.2V. It is used for AC-coupling inputs

IN and /IN. Connect VREF-AC directly to the VT pin. Bypass with 0.01µF low ESR

capacitor to VCC. Maximum sink/source current is ±1.5mA. See “Input Interface

Applications” section for more detai ls.

5, 8,13, 16 VCC Positive Power Supply: Bypass with 0.1µF//0.01µF low ESR capacitors as close to

the VCC pins as possible.

6, 7, 14, 15 GND,

Exposed pad Ground. Exposed pad must be connected to a ground plane that is the same

potential as the ground pin.

9, 10

11, 12 /Q1, Q1

/Q0, Q0 LVDS Differential Output Pairs: Differential buffered output copy of the input signal.

The output swing is typically 325mV. Normally terminated 100Ω across the output

pairs (Q and /Q). See “LVDS Output Termination” section.

Micrel, Inc.

SY58608U

October 2006 3 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Absolute Maximum Ratings(1)

Supply Voltage (VCC) ............................... –0.5V to +4.0V

Input Voltage (VIN) ............................ –0.5V to VCC +0.3V

LVDS Output Current (IOUT) .................................. ±10mA

Input Current

Source or Sink Current on (IN, /IN) ............... ±50mA

Current (VREF)

Source or sink current on VREF-AC(4) .............. ±1.5mA

Maximum Operating Junction Temperature .......... 125°C

Lead Temperature (soldering, 20sec.) .................. 260°C

Storage Temperature (Ts) .................... –65°C to +150°C

Operating Ratings(2)

Supply Voltage (VIN) ...................... +2.375V to +2.635V

Ambient Temperature (TA) ................... –40°C to +85°C

Package Thermal Resistance(3)

QFN

Still-air (θJA) ........................................... 60°C/W

Junction-to-board (ψJB) ......................... 33°C/W

DC Electrical Characteristics(5)

TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VCC Power Supply Voltage Range 2.375 2.5 2.625 V

ICC Power Supply Current No load, max. VCC 55 75 mA

RDIFF_IN Differential Input R esistance

(IN-to-/IN) 90 100 110 Ω

VIH Input HIGH Voltage

(IN, /IN) IN, /IN 1.2 VCC V

VIL Input LO W Voltage

(IN, /IN) IN, /IN 0 VIH–0.1 V

VIN Input Voltage Swing

(IN, /IN) see Figure 3a, Note 6 0.1 1.7 V

VDIFF_IN Differential Input Voltage Swing

(|IN - /IN|) see Figure 3b 0.2 V

VIN_FSI Input Voltage Threshold that

Triggers FSI 30 100 mV

VREF-AC Output Reference Voltage VCC–1.3 VCC–1.2 VCC–1.1 V

IN to VT Voltage from Input to VT 1.28 V

Notes:

1. Permanent device dam age may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not

implied at conditions other than those detailed i n the operational secti ons of this data sheet. E xposure to abs ol ute maxim um ratings c ondit i ons

for extended periods may affect device reliabil ity.

2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings.

3. Package thermal resist ance assumes exposed pad is s ol dered (or equivalent ) t o the device's most negative potential on the PCB. ψJB and θJA

values are determined for a 4-layer board in still-air num ber, unless otherwise s tated.

4. Due to the limited drive capabi lit y, use for input of the same package only.

5. The ci rcuit is designed to meet the DC specifications shown in the above table after therm al equilibrium has been est ablis hed.

6. VIN (max) is s pecifi ed when VT is floating.

Micrel, Inc.

SY58608U

October 2006 4 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

LVDS Outputs DC Electrical Characteristics(7)

VCC = +2.5V ±5%, RL = 100Ω across the output pairs; TA = –40°C to +85°C, unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

VOUT Output Voltage Swing See Figure 3a 250 325 mV

VDIFF_OUT Differ ential Output Voltage Swing See Figure 3b 500 650 mV

VOCM Output Common Mode Voltage 1.125 1.20 1.275 V

∆VOCM Change in Common Mode

Voltage –50 50 mV

Notes:

7. The ci rcuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been establis hed.

Micrel, Inc.

SY58608U

October 2006 5 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

AC Electrical Characteristics(8)

VCC = +2.5V ±5% , RL = 100Ω across the output pairs, Input tr/tf: ≤300ps; TA = –40°C to +85°C,

unless otherwise stated.

Symbol Parameter Condition Min Typ Max Units

fMAX Maximum Frequency NRZ Data 3.2 4.25 Gbps

VOUT > 200mV Clock 2 3 GHz

tPD Propagation Delay IN-to-Q VIN: 100mV-200mV 170 280 420 ps

VIN: 200mV-800mV 130 200 300 ps

tSkew Within Device Skew Note 9 5 20 ps

Part-to-Part Skew Note 10 135 ps

tJitter Data Random Jitter Note 11 1 psRMS

Deterministic Jitter Note 12 10 psPP

Clo ck Cycle-to-Cycle Jitter Note 13 1 psRMS

Total Jitter Note 14 10 psPP

tr, tf Output Rise/Fall Time

(20% to 80%) At full output swing.

35 60 100 ps

Duty Cycle Differential I/O 47 53 %

Notes:

8. These hi gh-speed paramet ers are Guaranteed by desi gn and characterization.

9. Within-device skew is measured between two different outputs under ident ical input trans iti ons.

10. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and no sk ew at the edges at the

respective inputs.

11. Random jitt er is measured with a K28.7 pattern, measured at ≤ f

MAX.

12. Determini st ic jitter is m easured at 2.5Gbps with both K28.5 and 223–1 PRBS pattern.

13. Cycle-to-cycle jitter definition: the variation period bet ween adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn –Tn+1,

where T is the time between rising edges of the output signal.

14. Total jitter definition: with an ideal clock input frequency of ≤ f

MAX (device), no more than one output edge in 1012 output edges will deviate by

more than the specified peak-to-peak jitter value.

Micrel, Inc.

SY58608U

October 2006 6 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Functional Description

Fail-Safe Input (FSI)

The input includes a special fail-safe circuit to sense

the amplitude of the input signal and to latch the

outputs when there is no input signal present, or

when the amplitude of the input signal drops

sufficiently below 100mVPK (200mVPP), typically

30mVPK. Maximum frequency of SY58608U is limited

by the FSI function.

Input Clock Failure Case

If the input c lock fails to a float ing, static, or extr emely

low signal swing such that the differential voltage

across the input pair is less than 100mV, the FSI

function will e liminate a metastable cond iti on a nd l atc h

the outputs to the last valid state. No ringing and no

indeterminate state will occur at the output under

these conditions. The output recovers to normal

operatio n once the input signa l returns to a valid stat e

with a differential voltage ≥100mV.

Note that the FSI function will not prevent duty cycle

distortion in case of a slowly deteriorating (but still

toggling) input signal. Due to the FSI function, the

propagation delay will depend on rise and fall time of

the input sig nal and on its amplitude . Refer to “ Typical

Characteristics” for detailed information.

Timing Diagrams

Figure 1a. Propagation Delay

Figure 1b. Fail Safe Feature

Micrel, Inc.

SY58608U

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Typical Characteris tics

VCC = 2.5V, GND = 0V, VIN = 100mV, RL = 100Ω across the output pairs, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58608U

October 2006 8 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics

VCC = 2.5V, GND = 0V, VIN = 250mV, Data Pattern: 223-1, RL = 100Ω across the outputs, TA = 25°C, unless otherwise

stated.

Micrel, Inc.

SY58608U

October 2006 9 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Functional Characteristics (continued)

VCC = 2.5V, GND = 0V, VIN = 250mV, RL = 100Ω across the outputs, TA = 25°C, unless otherwise stated.

Micrel, Inc.

SY58608U

October 2006 10 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Input Stage

Figure 2. Simplified Differential Input Buffer

Figure 3a. Single-Ended Swing

Figure 3c. LVDS Differential Measurement

Figure 3b. Differential Swing

Figure 3d. LVDS Common Mode Measurement

Micrel, Inc.

SY58608U

October 2006 11 M9999-102706-A

hbwhelp@micrel.com or (408) 955-1690

Input Interface Applications

Figure 4a. CML Interface

(DC-Coupled)

Figure 4b. CML Interface

(AC-Coupled)

Figure 4c. LVPECL Interface

(DC-Coupled)

Figure 4d. LVPECL Interface

(AC-Coupled)

Figure 4e. LVDS Interface

(DC-Coupled)