GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM ASYNCHRONOUS SRAM 128K x 8 SRAM WITH TWO CHIP ENABLE TRADITIONAL PINOUT FEATURES GENERAL DESCRIPTIO N * * * * * * * * The GVT72024A8 is organized as a 131,072 x 8 SRAM using a four-transistor memory cell with a high performance, silicon gate, low-power CMOS process. Galvantech SRAMs are fabricated using double-layer polysilicon, double-layer metal technology. Static design eliminates the need for external clocks or timing strobes. For increased system flexibility and eliminating bus contention problems, this device offers two chip enables (CE1# and CE2) along with output enable (OE#) for this organization. The chip is enabled when CE1# is LOW and CE2 is HIGH. With chip being enabled, writing to this device is accomplished when write enable (WE#) is LOW and reading is accomplished when (OE#) go LOW with (WE#) remaining HIGH. The device offers a low power standby mode when chip is not selected. This allows system designers to meet low standby power requirements. Fast access times: 10, 12, 15and 20ns Fast OE# access times: 5, 6, 7 and 8ns Single +5V +10% power supply Fully static -- no clock or timing strobes necessary All inputs and outputs are TTL-compatible Three state outputs Easy memory expansion with CE1#, CE2 and OE# options High-performance, low-power consumption, CMOS double-poly, double-metal process OPTIONS * * * * MARKING Timing 10ns access 12ns access 15ns access 20ns access -10 -12 -15 -20 Packages 32-pin SOJ (400 mil) 32-pin SOJ (300 mil) 32-pin TSOP (type I) J SJ TS Power consumption Standard Low Temperature Commercial Industrial PIN ASSIGNMENT 32-Pin SOJ NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ1 DQ2 DQ3 VSS None L None I (0C to 70C) (-40C to 85C) 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 VCC A15 CE2 WE# A13 A8 A9 A11 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 PIN ASSIGNMENT 32-Pin TSOP (Type I) A11 A9 A8 A13 WE# CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Tel (408) 566-0688 Fax (408) 566-0699 Web Site: http://www.galvantech.com Rev. 1/99 1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17 OE# A10 CE1# DQ8 DQ7 DQ6 DQ5 DQ4 VSS DQ3 DQ2 DQ1 A0 A1 A2 A3 Galvantech, Inc. reserves the right to chang e products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. FUNCTIONAL BLOCK DIAGRAM VCC VSS A0 MEMORY ARRAY 512 ROWS X 256 X 8 COLUMNS I/O CONTROL ADDRESS BUFFER ROW DECODER DQ1 DQ8 CE2 CE1# WE# OE# POWER DOWN A16 COLUMN DECODER TRUTH TABLE MODE CE1# CE2 WE# OE# DQ POWER L L L H X H H H X L H L H X X L X H X X Q D HIGH-Z HIGH-Z HIGH-Z ACTIVE ACTIVE ACTIVE STANDBY STANDBY READ WRITE OUTPUT DISABLE STANDBY STANDBY PIN DESCRIPTION S SOJ & DIP Pin Numbers TSOP Pin Numbers 12, 11, 10, 9, 8, 7, 20, 19, 18, 17, 16, 6, 5, 27, 28, 23, 15, 14, 13, 3, 2, 31, 25, 4, 28, 3, 31, 2 1, 12, 4, 11, 7, 10 SYMBOL TYPE DESCRIPTION A0-A16 Input Addresses Inputs: These inputs determine which cell is addressed . 29 5 WE# Input Write Enable: This input determines if the cycle is a READ or WRITE cycle. WE# is LOW for a WRITE cycle and HIGH for a READ cycle . 22, 30 30, 6 CE1#, CE2 Input Chip Enables: These inputs are used to enable the device. When CE1# is LOW and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is LOW, the chip is disabled and automatically goes into standby power mode . 24 32 OE# Input 13, 14, 15, 17, 18, 19, 20, 21 21, 22, 23, 25, 26, 27, 28, 29 DQ1-DQ8 Input/ Output 32 8 VCC Supply Power Supply: 5V +10% 16 24 VSS Supply Ground January 22, 199 9 Rev. 1/99 Output Enable: This active LOW input enables the output drivers . SRAM Data I/O: Data inputs and data output s 2 Galvantech, Inc. reserves the right to change products or specifications without notice . GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM *Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ABSOLUTE MAXIMUM RATINGS * Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V VIN ..........................................................-0.5V to VCC+0.5V Storage Temperature (plastic) ..........................-55oC to +125o Junction Temperature .....................................................+125o Power Dissipation ...........................................................1.2W Short Circuit Output Current .......................................50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S (All Temperature Ranges; VCC = 5V +10% unless otherwise noted) DESCRIPTION CONDITIONS SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) voltage VIH 2.2 VCC+1 V 1, 2 Input Low (Logic 0) Voltage VIl -0.5 0.8 V 1, 2 Input Leakage Current 0V < VIN < VCC ILI -5 5 uA Output Leakage Current Output(s) disabled, 0V < VOUT < VCC ILO -5 5 uA Output High Voltage IOH = -4.0mA VOH 2.4 Output Low Voltage IOL = 8.0mA VOL Supply Voltage VCC DESCRIPTION CONDITIONS Power Supply Current: Operating TTL Standby CMOS Standby 4.5 V 1 0.4 V 1 5.5 V 1 SYM TYP POWER -10 -12 -15 -20 Device selected; CE1# < VIL & CE2 > VIH; VCC =MAX; f=fMAX; outputs open Icc 80 210 180 150 110 200 170 140 110 CE1# >VIH or CE2 <VIL; VCC = MAX; f=fMAX ISB1 standard low standard low CE1# >VCC -0.2 or CE2< VSS +0.2; VCC = MAX; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 ISB2 20 0.02 standard low 60 55 50 40 45 40 35 30 10 10 10 10 1.0 1.0 1.0 1.0 UNITS NOTES mA 3, 14 mA 14 mA 14 CAPACITANCE DESCRIPTION CONDITIONS Input Capacitance TA = 25oC; f = 1 MHz VCC = 5V Input/Output Capacitance (DQ) January 22, 199 9 Rev. 1/99 SYMBOL MAX UNITS NOTES CI 6 pF 4 CI/O 8 pF 4 3 Galvantech, Inc. reserves the right to change products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. AC ELECTRICAL CHARACTERISTICS (Note 5) (All Temperature Ranges; VCC = 5V DESCRIPTION +10%) - 10 - 12 MAX MIN - 15 MAX MIN - 20 SYM MIN MAX MIN MAN UNITS NOTES READ cycle time tRC 10 Address access time tAA 10 12 15 20 ns tACE 10 12 15 20 ns READ Cycle Chip Enable access time 12 15 20 ns tOH 3 4 4 4 ns Chip Enable to output in Low-Z tLZCE 3 4 4 4 ns 4, 7 Chip disable to output in High- Z tHZCE ns 4, 6, 7 Output hold from address chang e Output Enable access time 5 tAOE Output Enable to output in Low-Z tLZOE Output Enable to output in High-Z tHZOE Chip Enable to power-up time tPU Chip disable to power-down tim e tPD 6 5 0 6 0 6 0 8 0 7 0 10 8 7 0 5 0 7 12 8 0 15 ns ns 20 ns 4, 6 ns 4 ns 4 WRITE Cycle WRITE cycle time tWC 10 12 15 20 ns Chip Enable to end of write tCW 8 8 9 10 ns Address valid to end of write, with OE# HIGH tAW 8 8 9 10 ns Address setup time tAS 0 0 0 0 ns Address hold from end of write tAH 0 0 0 0 ns WRITE pulse width tWP2 10 10 11 12 ns WRITE pulse width, with OE# HIG H tWP1 8 8 9 10 ns Data setup time tDS 6 6 7 8 ns Data hold time tDH 0 0 0 0 ns Write disable to output in Low-Z tLZWE 3 Write Enable to output in High- Z tHZWE January 22, 199 9 Rev. 1/99 4 5 5 6 4 5 7 8 ns 4, 7 ns 4, 6, 7 Galvantech, Inc. reserves the right to change products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. OUTPUT LOADS AC TEST CONDITIONS Input pulse levels Q 0V to 3.0V Input rise and fall times 1.5ns Input timing reference levels 1.5V Output reference levels 1.5V Output load Z 0 = 50 50 30 pF Vt = 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT See Figures 1 and 2 +5V 480 Q 255 5 pF Fig. 2 OUTPUT LOAD EQUIVALENT NOTES 8. WE# is HIGH for READ cycle. 1. All voltages referenced to VSS (GND). 9. 2. Overshoot: Undershoot: Device is continuously selected. Chip enable and output enables are held in their active state. VIH +7.0V for t tRC /2. VIL -2.0V for t tRC /2 3. Icc is given with no output current. Icc increases with greater output loading and faster cycle times. 4. This parameter is sampled. 5. Test conditions as specified with the output loading as shown in Fig. 1 unless otherwise noted. 6. Output loading is specified with CL=5pF as in Fig. 2. Transition is measured +500mV from steady state voltage. 7. At any given temperature and voltage condition, tHZCE is less than tLZCE and tHZWE is less than tLZWE. 10. Address valid prior to, or coincident with, latest occurring chip enable. 11. tRC = Read Cycle Time. 12. Chip Enable and Write Enable can initiate and terminate a WRITE cycle. 13. Capacitance derating applies to capacitance different from the load capacitance shown in Fig. 1. 14. Typical values are measured at 5V, 25oC and 20ns cycle time. DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only ) DESCRIPTION CONDITIONS SYMBOL MIN VDR ICCDR ICCDR 2 Chip Deselect to Data Retention Time tCDR Operation Recovery Time tR Vcc for Retention Data Data Retention Current January 22, 199 9 Rev. 1/99 CE1# >VCC -0.2 or CE2< VSS +0.2; all other inputs < VSS +0.2 or >VCC -0.2; all inputs static; f= 0 Vcc = 2V Vcc = 3V 5 TYP MAX UNITS NOTES 2 400 uA 13 3 600 uA 13 0 ns 4 tRC ns 4, 11 V Galvantech, Inc. reserves the right to change products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. LOW VCC DATA RETENTION WAVEFORM DATA RETENTION MODE 4.5V VCC CE1# VIH CE2 VIH 4.5V VDR tCDR DATA RETENTION MODE tRC VIL < 0.2V VIL READ CYCLE NO. 1(8, 9) tRC ADDR VALID tAA tOH Q PREVIOUS DATA VALID DATA VALID READ CYCLE NO. 2(7, 8, 10, 12) tRC CE1# CE2 tAOE tLZOE OE# tHZCE tACE tHZOE tLZCE Q HIGH Z DATA VALID DON'T CARE UNDEFINED January 22, 199 9 Rev. 1/99 6 Galvantech, Inc. reserves the right to change products or specifications without notice . GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM WRITE CYCLE NO. 1(7, 12, 13) (Write Enable Controlled with Output Enable OE# active LOW) ) t WC ADDR t t AW t AH CW CE2 CE1# t t WP2 AS WE# t D t DS t DH DATA VALID HZWE t Q LZWE HIGH Z WRITE CYCLE NO. 2(12, 13) (Write Enable Controlled with Output Enable OE# inactive HIGH ) t WC ADDR tAW tAH t CW CE2 CE1# t tWP1 AS WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE UNDEFINED January 22, 199 9 Rev. 1/99 7 Galvantech, Inc. reserves the right to change products or specifications without notice . GALVANTECH, INC. GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM WRITE CYCLE NO. 3(12, 13) (Chip Enable Controlled) t WC ADDR tAW tAH t tAS CW CE2 CE1# tWP1 WE# tDS D Q tDH DATA VALID HIGH Z DON'T CARE January 22, 199 9 Rev. 1/99 8 Galvantech, Inc. reserves the right to change products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. Package Dimension s 32-pin 400 Mil Plastic SOJ (J) .830 (21.08) .820 (20.83) .405 (10.29) .395 (10.03) PIN #1 INDEX .445 (11.30) .435 (11.05) .145 (3.68) .131 (3.33) .050 (1.27) TYP .095 (2.41) .080 (2.03) SEATING PLANE .020 (0.51) .015 (0.38) .380 (9.65) .360 (9.14) .030 (0.76) MIN Note: All dimensions in inches (millimeters) MAX MIN or typical, min where noted. 32-pin 300 Mil Plastic SOJ (SJ) .825 (20.96) .810 (20.57) .305 (7.75) .292 (7.42) PIN #1 INDEX .340 (8.64) .330 (8.38) .140 (3.55) .120 (3.04) .050 (1.27) TYP .095 (2.41) .080 (2.03) SEATING PLANE .020 (0.51) .015 (0.38) .274 (6.95) .254 (6.44) .025 (0.63) MIN Note: All dimensions in inches (millimeters) January 22, 199 9 Rev. 1/99 MAX MIN or typical, min where noted. 9 Galvantech, Inc. reserves the right to change products or specifications without notice . GVT72024A8 TRADITIONAL PINOUT 128K X 8 SRAM GALVANTECH, INC. Package Dimensions (continued) 32-pin Plastic TSOP (TS) .795 (20.20) .780 (19.80) .012 (0.30) .006 (0.15) .319 (8.10) .311 (7.90) .020 (0.50) TYP .728 (18.50) .720 (18.30) .047 (1.20) MAX Note: All dimensions in inches (millimeters) MAX MIN .041 (1.05) .037 (0.95) or typical, max where noted. Ordering Information GVT 72024A8 XX - XX X X Galvantech Prefix Temperature (Blank = Commercial I = Industrial) Power (Blank= Standard, L= Low Power) Part Number Speed (10 = 10ns, 12= 12ns, 15 = 15ns, 20 = 20ns) Package (J = 400 mil SOJ, SJ= 300 mil SOJ, TS= TSOP TYPE I) January 22, 199 9 Rev. 1/99 10 Galvantech, Inc. reserves the right to change products or specifications without notice .