ASYNCHRONOUS
SRAM 128K x 8 SRAM
WITH TWO CHIP ENABLE
TRADITIONAL PINOUT
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
Galvantech, Inc. reserves the right to change
products or specifications without notice.
Rev. 1/99
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051
Tel (408) 566-0688 Fax (408) 566-0699Web Site: http://www.galvantech.com
FEATURES
•Fast access times: 10, 12, 15and 20ns
•Fast OE# access times: 5, 6, 7 and 8ns
•Single +5V +10% power supply
•Fully static -- no clock or timing strobes necessary
•All inputs and outputs are TTL-compatible
•Three state outputs
•Easy memory expansion with CE1#, CE2 and OE# options
•High-performance, low-power consumption, CMOS
double-poly, double-metal process
OPTIONSMARKING
•Timing
10ns access -10
12ns access -12
15ns access -15
20ns access -20
•Packages
32-pin SOJ (400 mil) J
32-pin SOJ (300 mil) SJ
32-pin TSOP (type I) TS
•Power consumption
Standard None
Low L
•Temperature
Commercial None (0°C to 70°C)
Industrial I (-40°C to 85°C)
GENERAL DESCRIPTION
The GVT72024A8 is organized as a 131,072 x 8 SRAM
using a four-transistor memory cell with a high performance,
silicon gate, low-power CMOS process. Galvantech SRAMs
are fabricated using double-layer polysilicon, double-layer
metal technology.
Static design eliminates the need for external clocks or
timing strobes. For increased system flexibility and
eliminating bus contention problems, this device offers two
chip enables (CE1# and CE2) along with output enable (OE#)
for this organization.
The chip is enabled when CE1# is LOW and CE2 is
HIGH. With chip being enabled, writing to this device is
accomplished when write enable (WE#) is LOW and reading
is accomplished when (OE#) go LOW with (WE#) remaining
HIGH. The device offers a low power standby mode when
chip is not selected. This allows system designers to meet low
standby power requirements.
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
18
17
A15
CE2
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
WE#
A13
A8
A9
A11
OE#
A16
A14
A2
A1
A0
DQ1
DQ2
DQ3
VSS
A12
A7
A6
A5
A4
A3
VCCNC
PIN ASSIGNMENT
32-Pin SOJ
1
2
3
4
5
6
7
8
9
10
32
31
30
29
28
27
26
25
24
23
22
21
20
11
12
13
14
15
16
19
18
17
A15
CE2
A10
CE1#
DQ8
DQ7
DQ6
DQ5
DQ4
WE#
A13
A8
A9
A11 OE#
A16
A14
A2
A1
A0
DQ1
DQ2
DQ3
VSS
A12
A7
A6
A5
A4 A3
VCC
NC
PIN ASSIGNMENT
32-Pin TSOP (Type I)
January 22, 199 92Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
FUNCTIONAL BLOCK DIAGRAM
TRUTH TABLE
PIN DESCRIPTIONS
MODECE1#CE2WE#OE#DQPOWER
READLH H LQACTIVE
WRITELHLXDACTIVE
OUTPUT DISABLELHHHHIGH-ZACTIVE
STANDBYHXXXHIGH-ZSTANDBY
STANDBY X LX X HIGH-ZSTANDBY
SOJ & DIP Pin
NumbersTSOP Pin
NumbersSYMBOLTYPEDESCRIPTION
12, 11, 10, 9, 8, 7,
6, 5, 27, 28, 23,
25, 4, 28, 3, 31, 2
20, 19, 18, 17, 16,
15, 14, 13, 3, 2, 31,
1, 12, 4, 11, 7, 10
A0-A16InputAddresses Inputs: These inputs determine which cell is addressed .
29 5 WE#InputWrite Enable: This input determines if the cycle is a READ or WRITE cycle. WE#
is LOW for a WRITE cycle and HIGH for a READ cycle.
22, 3030, 6CE1#, CE2InputChip Enables: These inputs are used to enable the device. When CE1# is LOW
and CE2 is HIGH, the chip is selected. When either CE1# is HIGH or CE2 is
LOW, the chip is disabled and automatically goes into standby power mode .
2432OE#InputOutput Enable: This active LOW input enables the output drivers.
13, 14, 15, 17,
18, 19, 20, 2121, 22, 23, 25,
26, 27, 28, 29DQ1-DQ8Input/
OutputSRAM Data I/O: Data inputs and data outputs
32 8 VCCSupplyPower Supply: 5V +10%
1624VSSSupplyGround
CE1#
ADDRESS BUFFER
ROW DECODER
COLUMN DECODER
MEMORY ARRAY
512 ROWS X 256 X 8
COLUMNS
I/O CONTROL
WE#
OE#
DQ8
DQ1
POWER
DOWN
A16
A0
VCC
VSS
CE2
ABSOLUTE MAXIMUM RATINGS *
Voltage on VCC Supply Relative to VSS........-0.5V to +7.0V
VIN ..........................................................-0.5V to VCC+0.5V
Storage Temperature (plastic) ..........................-55oC to +125o
Junction Temperature .....................................................+125o
Power Dissipation ...........................................................1.2W
Short Circuit Output Current .......................................50mA
*Stresses greater than those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.This is a stress
rating only and functional operation of the device at these or any
other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
January 22, 199 93Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S
(All Temperature Ranges; VCC = 5V +10% unless otherwise noted)
CAPACITANCE
DESCRIPTIONCONDITIONSSYMBOLMINMAXUNITSNOTES
Input High (Logic 1) voltageVIH2.2VCC+1V1, 2
Input Low (Logic 0) VoltageVIl-0.50.8V1, 2
Input Leakage Current0V < VIN < VCCILI-5 5 uA
Output Leakage CurrentOutput(s) disabled,
0V < VOUT < VCCILO-5 5 uA
Output High VoltageIOH = -4.0mA VOH2.4V1
Output Low VoltageIOL = 8.0mA VOL0.4V1
Supply VoltageVCC4.55.5V1
DESCRIPTIONCONDITIONSSYMTYPPOWER-10-12-15-20UNITSNOTES
Power Supply
Current: OperatingDevice selected; CE1# < VIL & CE2 > VIH;
VCC =MAX; f=fMAX; outputs openIcc80 standard210180150110mA3, 1 4
low200170140110
TTL Standb yCE1# >VIH or CE2 <VIL; VCC = MAX;
f=fMAXISB120 standard60 55 50 40 mA14
low45 40 35 30
CMOS StandbyCE1# >VCC -0.2 or CE2< VSS +0.2;
VCC = MAX;
all other inputs < VSS +0.2 or >VCC -0.2;
all inputs static; f= 0
ISB20.02standard10 10 10 10 mA14
low1.01.01.01.0
DESCRIPTIONCONDITIONSSYMBOLMAXUNITSNOTES
Input CapacitanceTA = 25oC; f = 1 MHz
VCC = 5VCI6pF4
Input/Output Capacitance (DQ)CI/O8pF4
January 22, 199 94Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
AC ELECTRICAL CHARACTERISTICS
(Note 5) (All Temperature Ranges; VCC = 5V +10%)
DESCRIPTION- 10- 12- 15- 20
SYMMINMAXMINMAXMINMAXMINMANUNITSNOTES
READ Cycle
READ cycle timetRC10 1215 20 ns
Address access timetAA10 1215 20 ns
Chip Enable access timetACE10 1215 20 ns
Output hold from address changetOH3444ns
Chip Enable to output in Low-ZtLZCE3444ns4, 7
Chip disable to output in High-ZtHZCE5678ns4, 6, 7
Output Enable access timetAOE5678ns
Output Enable to output in Low-ZtLZOE0000ns
Output Enable to output in High-ZtHZOE5678ns4, 6
Chip Enable to power-up timetPU0000ns4
Chip disable to power-down timetPD10 1215 20 ns4
WRITE Cycle
WRITE cycle timetWC10 1215 20 ns
Chip Enable to end of writetCW8 8 9 10 ns
Address valid to end of write, with OE#
HIGHtAW8 8 9 10 ns
Address setup timetAS0000ns
Address hold from end of writetAH0000ns
WRITE pulse widthtWP2 10 1011 12 ns
WRITE pulse width, with OE# HIGHtWP1 8 8 9 10 ns
Data setup timetDS6678ns
Data hold timetDH0000ns
Write disable to output in Low-ZtLZWE3455ns4, 7
Write Enable to output in High-ZtHZWE5678ns4, 6, 7
AC TEST CONDITIONS
Input pulse levels0V to 3.0V
Input rise and fall times1.5ns
Input timing reference levels1.5V
Output reference levels1.5V
Output loadSee Figures 1 and 2
OUTPUT LOADS
Vt = 1.5V
30 pF
Q
Z0 = 50Ω
Fig. 1 OUTPUT LOAD EQUIVALENT
50Ω
Q
+5V
480Ω
255Ω
Fig. 2 OUTPUT LOAD EQUIVALENT
5 pF
January 22, 199 95Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
NOTES
1. All voltages referenced to VSS (GND).
2. Overshoot: VIH ≤ +7.0V for t ≤ tRC /2.
Undershoot: VIL ≤ -2.0V for t ≤ tRC / 2
3. Icc is given with no output current. Icc increases with greater
output loading and faster cycle times.
4. This parameter is sampled.
5. Test conditions as specified with the output loading as shown in
Fig. 1 unless otherwise noted.
6. Output loading is specified with CL=5pF as in Fig. 2. Transition
is measured +500mV from steady state voltage.
7. At any given temperature and voltage condition, tHZCE is less
than tLZCE and tHZWE is less than tLZWE.
8. WE# is HIGH for READ cycle.
9. Device is continuously selected. Chip enable and output enables
are held in their active state.
10. Address valid prior to, or coincident with, latest occurring chip
enable.
11. tRC = Read Cycle Time.
12. Chip Enable and Write Enable can initiate and terminate a
WRITE cycle.
13. Capacitance derating applies to capacitance different from the
load capacitance shown in Fig. 1.
14. Typical values are measured at 5V, 25oC and 20ns cycle time.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only )
DESCRIPTIONCONDITIONSSYMBOLMINTYPMAXUNITSNOTES
Vcc for Retention DataVDR2V
Data Retention CurrentCE1# >VCC -0.2 or
CE2< VSS +0.2;
all other inputs < VSS +0.2
or >VCC -0.2;
all inputs static; f= 0
Vcc = 2VICCDR2400uA13
Vcc = 3VICCDR3600uA13
Chip Deselect to
Data Retention TimetCDR0 ns4
Operation Recovery TimetRtRCns4, 11
January 22, 199 96Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
LOW VCC DATA RETENTION WAVEFORM
READ CYCLE NO. 1(8, 9)
READ CYCLE NO. 2(7, 8, 10, 12)
VCC
CE1#
DATA RETENTION MODE
VDR
4.5V 4.5V
VIH
VIL
CE2 VIH
VIL < 0.2V
DATA RETENTION MODE
tRC
tCDR
ADDR VALID
tRC
DATA VALID
tOH
tAA
PREVIOUS DATA VALID
Q
CE1#
tRC
DATA VALID
tLZCE
tACE
OE#
HIGH Z
tAOE
tLZOE
tHZCE
tHZOE
CE2
Q
UNDEFINED
DON'T CARE
January 22, 199 97Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
WRITE CYCLE NO. 1(7, 12, 13)
(Write Enable Controlled with Output Enable OE# active LOW))
WRITE CYCLE NO. 2(12, 13)
(Write Enable Controlled with Output Enable OE# inactive HIGH)
ADDR
tWC
tAH
tDS
DATA VALID
CE2
CE1#
WE#
D
Q
tDH
tWP2
tAS
tAW
tCW
HIGH Z
tHZWE tLZWE
ADDR
tWC
tAH
tDS
DATA VALID
HIGH Z
CE2
CE1#
WE#
D
Q
tDH
tWP1
tAS
tAW
tCW
UNDEFINED
DON'T CARE
January 22, 199 98Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
WRITE CYCLE NO. 3(12, 13)
(Chip Enable Controlled)
ADDR
tWC
tAH
tDS
DON'T CARE
DATA VALID
CE2
CE1#
WE#
D
Q
tDH
tWP1
tAS
tAW tCW
HIGH Z
January 22, 199 99Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
Package Dimensions
Note: All dimensions in inches (millimeters)
.830 (21.08)
.820 (20.83)
.405 (10.29)
.395 (10.03)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.015 (0.38)
MAX
MIN or typical, min where noted.
SEATING PLANE
.380 (9.65)
.360 (9.14)
.095 (2.41)
.080 (2.03)
.145 (3.68)
.131 (3.33)
.030 (0.76)
MIN
.445 (11.30)
.435 (11.05)
32-pin 400 Mil Plastic SOJ (J)
Note: All dimensions in inches (millimeters)
.825 (20.96)
.810 (20.57)
.305 (7.75)
.292 (7.42)
PIN #1 INDEX .050 (1.27) TYP
.020 (0.51)
.015 (0.38)
MAX
MIN or typical, min where noted.
SEATING PLANE
.274 (6.95)
.254 (6.44)
.095 (2.41)
.080 (2.03)
.140 (3.55)
.120 (3.04)
.025 (0.63)
MIN
32-pin 300 Mil Plastic SOJ (SJ)
.340 (8.64)
.330 (8.38)
January 22, 199 910Galvantech, Inc. reserves the right to change products or specifications without notice.
Rev. 1/99
GVT72024A8
TRADITIONAL PINOUT 128K X 8 SRAM
GALVANTECH, INC.
Package Dimensions (continued)
Ordering Information
GVT 72024A8 XX - XX X X
.319 (8.10)
.311 (7.90)
.012 (0.30)
.006 (0.15)
.728 (18.50)
.720 (18.30)
.020 (0.50) TYP
.047 (1.20) MAX
.795 (20.20)
.780 (19.80)
.041 (1.05)
.037 (0.95)
Note: All dimensions in inches (millimeters) MAX
MIN or typical, max where noted.
32-pin Plastic TSOP (TS)
Galvantech Prefix
Part Number
Package (J = 400 mil SOJ,
15 = 15ns, 20 = 20ns)
Speed (10 = 10ns, 12= 12ns,
SJ= 300 mil SOJ,
Temperature (Blank = Commercial
I = Industrial)
Power (Blank= Standard,
L= Low Power)
TS= TSOP TYPE I)
