REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) Change to vendor similar part number for vendor CAGE number 61772 for devices 08KX, 09KX, 10KX, 11KX, 12KX, 13KX, 14KX, 15KX, and 16KX. Remove vendor CAGE number 61772 from devices 08YX, 09YX, 10YX, 11YX, 12YX, 13YX, 15YX, and 16YX. Change to vendor similar part number for vendor CAGE number 65786 for devices 09 and 11. Add vendor CAGE number 50088 to the drawing as a source of supply for devices 04JX and 05JX. Add vendor CAGE number 65896 to the drawing as a source of supply for devices 15 and 16. Removed 4.3.3 from drawing. Editorial changes throughout. E APPROVED 92-04-27 M. A. Frye F Added provisions for the addition of QD certified parts to drawing. Updated boilerplate. Added CAGE OC7V7 as supplier. - ksr 00-09-27 Raymond Monnin G Correction to marking paragraph 3.5. Updated boilerplate paragraphs. ksr 05-03-11 Raymond Monnin THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED CURRENT CAGE CODE 67268 REV SHEET REV G G G G G G G G SHEET 15 16 17 18 19 20 21 22 REV STATUS REV G G G G G G G G G G G G G G OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 James E. Jamison STANDARD MICROCIRCUIT DRAWING http://www.dscc.dla.mil CHECKED BY Ray Monnin APPROVED BY THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A Don Cool DRAWING APPROVAL DATE MICROCIRCUITS, MEMORY, DIGITAL, CMOS, 16K (2048 X 8) BIT STATIC RAM, MONOLITHIC SILICON 84 - 08 - 24 REVISION LEVEL G SIZE CAGE CODE A 14933 SHEET DSCC FORM 2233 APR 97 . 1 OF 84036 22 5962-E215-05 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 84036 Drawing number 01 Device type (see 1.2.1) J Case outline (see 1.2.2) X Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 Generic number 1/ Supply voltage variation 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% 10% Address access time 200 ns (synchronous) 90 ns 90 ns 150 ns 200 ns 70 ns 120 ns (synchronous) 45 ns 45 ns 55 ns 55 ns 70 ns 70 ns 35 ns 120 ns 90 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator Terminals J K L X Y Z CDIP2-T24 or GDIP1-T24 CDFP3-F24 or GDFP2-F24 CDIP4-T24 or GDIP3-T24 CQCC1-N32 See Figure 1 CQCC1-N32 24 24 24 32 24 32 3 CQCC1-N28 28 Package style dual-in-line package flat package dual-in-line package rectangular chip carrier package rectangular chip carrier package rectangular chip carrier package with castellated instead of chamfered corners and extended pad metallization at terminal number 1. square chip carrier package 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. 1/ Generic numbers are listed on the standardized military drawing source approval bulletin at the end of this Standard Microcircuit Drawing and will also be listed in MIL-HDBK-103. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 2 1.3 Absolute maximum ratings. Supply voltage range (VCC)---------------------------------- -0.3 V dc to +7.0 V dc 2/ Temperature under bias-------------------------------------- -55C to +125C Storage temperature range---------------------------------- -55C to +150C Maximum power dissipation (PD) -------------------------- 1.0 W Lead temperature (soldering, 5 seconds)---------------- +275C Thermal resistance, junction-to-case (JC):-------------- See MIL-STD-1835 Case Y ---------------------------------------------------------- 30C/W Junction temperature (TJ)------------------------------------ +150C 3/ All input or output voltages with respect to ground ---- -0.3 V dc to VCC +0.3 V dc 4/ 1.4 Recommended operating conditions. Case operating temperature range (TC) --------------------55C to +125C Input low voltage (VIL): Device types 01 through 16 ----------------------------------0.3 V dc to 0.8 V dc 2/ Input high voltage (VIH): Device types 01, 07--------------------------------------------2.4 V dc to VCC +0.3 V dc 2/ Device types 02 through 06, 08 through 16 ------------2.2 V dc to VCC +0.3 V dc 2/ Supply voltage range (VCC): ----------------------------------4.5 V dc to 5.5 V dc 2/ Minimum chip enable low time -----------------------------40 ns 5/ Minimum chip enable high time-----------------------------40 ns 5/ Maximum input rise time -------------------------------------40 ns Maximum input fall time --------------------------------------40 ns 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 2/ All voltages referenced to VSS. 3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions in accordance with method 5004 of MIL-STD-883. 4/ Negative undershoots to a minimum of -3.0 V are allowed with a maximum of 20 ns pulse width. 5/ For device types 02, 03, and 06 only. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 3 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535 is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or alternative approved by the Qualifying Activity. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3. 3.2.4 Logic diagram(s). The logic diagram(s) shall be as specified on figure 4. 3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only. Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. 3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535, Appendix A. For Class Q product built in accordance with A.3.2.2 of MIL-PRF-38535 or other alternative approved by the Qualifying Activity, the "QD" certification mark shall be used in place of the "QML" or "Q" certification mark. 3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 4 TABLE I. Electrical performance characteristics. Test High-level output voltage Low-level output voltage Symbol VOH VOL Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Limits Device type Min IOH = -1 mA 1,2,3 01-07, 15,16 IOH = -4 mA 1,2,3 08-14 Unit Max 2.4 V 01,07 IOL = +3.2 mA 1,2,3 IOL = +4.0 mA 0.4 02,03, V 06,15 High impedance output leakage current IIOLZ IOL = +2.0 mA 04,05, 16 IOL = +8.0 mA 08-14 01,02, 06,07 1,2,3 OE = VIH 1.0 -10.0 10.0 03,08, 10,12 -5.0 5.0 01,02, 06,07 -1.0 1.0 -2.0 2.0 -5.0 5.0 -10.0 10.0 04,05, 09,11, 13,14, 15,16 IIOHZ Input leakage current IIL VIN = GND IIH VIN = 5.5 V 1,2,3 04,05, 15 03,08, 10,12, 16 09,11, 13,14 01,07 Operating supply current ICC1 A -1.0 A 10 mA 1,2,3 VCC = 5.5 V, f = fmax 3/ 04,05, 13,15, 16 CE = VIL, outputs open All other inputs at VIL 90 02,03, 06 70 08,10, 12 85 09,11 120 14 150 See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 5 TABLE I. Electrical performance characteristics - Continued. Symbol Test Standby supply current Standby supply current ICC2 ICC3 Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Min 1,2,3 CE = WE = VIH, IO = 0 Limits Device type Unit Max 02,03, 06 8 04,05 10 10,12, 15,16 15 09,11, 13,14 25 06,07 50 mA 1,2,3 CE = VCC -0.3 V, IO = 0 01,02 100 A 04,05 250 03,08, 10,12, 15,16 900 13 mA 10 09,11, 14 Data retention current Input capacitance Output capacitance ICC4 4/ 4/ 1,2,3 CE = VCC, VCC = 2.0 V 20 01,02 50 04,05 100 08,10, 12,15, 16 200 03 300 06,07 25 A CI VI = VCC or GND f = 1 MHz See 4.3.1c 4 All 10 pF CO VI = VCC or GND f = 1 MHz See 4.3.1c 4 All 12 pF See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Read/write cycle time Symbol Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type 01 tAVAV 5/ 6/ 9, 10, 11 Address access time tAVQV 5/ 6/ 9, 10, 11 Limits Min 280 02,03,16 90 04 150 05 200 15 120 07 170 08,09 45 10,11 55 06,12,13 70 14 35 Output enable to output active 4/ Output enable access time tAVQX tOLQX tOLQV 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 Max ns 01 200 02,03,16 90 04 150 05 200 07,15 120 08,09 45 10,11 55 06,12,13 70 14 Output hold after address change 4/ Unit ns 35 15,16 0 04,05 10 02,03,06, 07,08-14 5 01,07 10 02,03,06, 08,12,13 5 04,05,09, 11,14,15, 16 0 ns ns 01,07,15 80 02,03,16 65 04 60 05 70 08,09 25 10,11 40 06,12,13 50 14 20 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 7 TABLE I. Electrical performance characteristics - Continued. Test Chip enable to output active 4/ Chip enable access time Chip enable to output in high Z 4/ Symbol Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups 01,07 tELQX tELQV tEHQZ 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 Write recovery time tWHAV Chip enable to end-ofwrite Device type tELWH 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 Limits Min 10 02,03,06, 08-14 5 04,05,15, 16 0 Unit Max ns 01 200 02,03,16 90 04 150 05 200 07,15 120 08,09 45 10,11 55 06,12,13 70 14 35 01 80 02,03,07, 15,16 50 04,05 60 08,09 25 10,11 30 06,12,13 35 14 15 02,03,04, 05,06,15, 16 10 09,11,14 0 ns ns ns 01 200 02,03,16 55 04 90 05,07 120 06 45 08,09,14 30 10-13 40 15 70 ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 8 TABLE I. Electrical performance characteristics - Continued. Test Address valid to end-ofwrite Address to WE setup time Address to CE setup time Output enable to output in high Z 4/ Write enable pulse width Symbol tAVWH tAVWL Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 tAVEL 5/ 6/ 9, 10, 11 tOHQZ 5/ 6/ 9, 10, 11 tWLWH 5/ 6/ 9, 10, 11 Device type 02,03, 12,13 Limits Min 65 Unit Max ns 04 100 05 130 15 105 06 50 08,09,14 30 10,11 45 16 80 02-06, 15,16 10 07,08,09, 11,14 0 ns 10 5 12,13 15 01,07 0 ns 01 80 02,03,15, 16 40 04,07 50 05 60 08,09 25 10,11 30 06,12,13 35 14 15 01 200 02,03,16 55 04 90 05,07 120 15 70 08,11 25 06,10, 12,13 40 09,14 20 ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 9 TABLE I. Electrical performance characteristics - Continued. Test Data setup to end-ofwrite Data hold after end-ofwrite Minimum chip-enable high time after write Address hold time after CE low Chip-enable pulse width during write Write enable pulse setup time Symbol Test conditions 1/ 2/ VSS = 0 V, 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type 01 tDVWH tWHDX tEHEL tELAX tELEH tWLEH 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 5/ 6/ 9, 10, 11 Limits Min 80 02,03,06, 12,13,16 30 04,07 50 05 70 08,09 20 10,11 25 15 35 14 15 01,06,07 10 02,03,04, 05,15,16 15 08,09,11, 14 0 10,12,13 5 01 80 07 50 01 50 07 30 01 200 07 120 01 200 02,03,16 55 04 90 05,07 120 08 30 06,10, 12,13 40 09,14 20 11 25 15 70 Unit Max ns ns ns ns ns ns 1/ 2/ 3/ 4/ 5/ All voltages referenced to VSS. Negative undershoots to a minimum of -0.3 V are allowed with a maximum of 20 ns pulse width. fmax = 1/tAVAV Tested initially, and after any design or process change which could affect these parameters. AC measurements assume transition time < 5 ns and input levels are from VSS to 3.0 V. Output load is specified on figure 5. Reference timing levels are at 1.5 V. 6/ For timing waveforms, see figure 6. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 10 Case Y 24 PIN RECTANGULAR LEADLESS CHIP CARRIER Inches .008 .020 .030 .040 .045 .050 .055 .062 .066 .078 .292 .308 .392 .408 Notes: 1. Dimensions are in inches. 2. Metric equivalents are for general information only. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 11 mm 0.20 0.50 0.76 1.01 1.14 1.27 1.39 1.57 1.68 1.98 7.41 7.82 9.95 10.36 All Device Types Case Outlines X and Z Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Terminal Symbol NC NC NC A7 A6 A5 A4 A3 A2 A1 A0 NC DQ0, I/O0 DQ1, I/O1 DQ2, I/O2 VSS NC DQ3, I/O3 DQ4, I/O4 DQ5, I/O5 DQ6, I/O6 DQ7, I/O7 23 24 CE , E A10 25 OE , G 26 27 28 29 30 31 32 WE , W NC A9 A8 NC NC VCC Y, J, K, and L Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 Terminal Symbol A7 A6 A5 A4 A3 A2 A1 A0 DQ0, I/O0 DQ1, I/O1 DQ2, I/O2 VSS DQ3, I/O3 DQ4, I/O4 DQ5, I/O5 DQ6, I/O6 DQ7, I/O7 18 19 CE , E A10 20 OE , G 21 22 23 24 WE , W A9 A8 VCC ----------------- 3 Terminal Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Terminal Symbol A7 A6 A5 A4 A3 A2 NC NC A1 A0 DQ1, I/O1 DQ2, I/O2 DQ3, I/O3 VSS DQ4, I/O4 DQ5, I/O5 DQ6, I/O6 DQ7, I/O7 DQ8, I/O8 20 21 22 23 CE , E NC NC A10 24 OE , G 25 WE , W A9 A8 VCC 26 27 28 --------- FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 12 Device types 01 and 07 Read cycle Time reference -1 0 1 2 3 4 5 Inputs Function CE H L L H OE X X L L X X X WE X H H H H X H A DQ X V X X X X V Z Z X V V Z Z Memory disabled Cycle begins, addresses are latched Output enabled Output valid Read accomplished Prepare for next cycle (same as -1) Cycle ends, next cycle begins (same as 0) Write cycle Time reference -1 0 1 2 3 4 5 Inputs Function CE H L L H OE H H H H H H H WE X X L H X X A DQ X V X X X X V X X X V X X X Memory disabled Cycle begins, addresses are latched Write period begins Data is written Write completed Prepare for next cycle (same as -1) Cycle ends, next cycle begins (same as 0) Device types 02 - 06 and 08 - 16 WE X Mode DQ VIH OE X Deselect High Z VIL X VIL Write DIN VIL VIL VIH Read VIL VIH VIH Read DOUT High Z CE X = Don't care H = HIGH L = LOW V = VALID = TRANSITION HIGH TO LOW = TRANSITION LOW TO HIGH FIGURE 3. Truth table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 13 Device types 01 and 07. ALL LINES POSITIVE LOGIC - ACTIVE HIGH THREE-STATE BUFFERS: A HIGH - OUTPUT ACTIVE ADDRESS LATCHED AND GATED DECODERS: LATCH ON RISING EDGE OF L GATE ON RISING EDGE OF G FIGURE 4. Block diagram. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 14 Device types 02 - 06 and 08 - 16 FIGURE 4. Block diagram - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 15 NOTE: 1. Including scope and jig capacitance. FIGURE 5. Output loading. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 16 Device types 01 and 07 The address information is latched in the on chip registers on the falling edge of CE (t = 0), minimum address setup and hold time requirements must be met. After the required hold time, the address may change state without affecting device operation. During time (t = 1), the outputs become enabled but data is not valid until time (t = 2), WE must remain high throughout the read cycle. After the data has been read, CE may return high (t = 3). This will force the output buffers into a high impedance mode at time (t = 4). OE is used to disable the output buffers when in a logical "1" state (t = -1, 0, 3, 4, 5). After (t = 4) time, the memory is ready for the next cycle. FIGURE 6. Timing waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 17 Device types 01 and 07 The write cycles is initiated on the falling edge of CE (t = 0), which latches the address information in the on chip registers. If a write cycle is to be performed where the output is not to become active, OE can be held high (inactive). Parameter tDVHW and tWHDX must be met for proper device operation regardless of OE. If CE and OE fall before WE falls (read mode), a possible bus conflict may exist. If CE rises before WE rises, reference data setup and hold times to the CE rising edge. The write operation is terminated by the first rising edge of WE (t = 2) or CE (t = 3). After the minimum CE high time (tEHEL), the next cycle may begin. If a series of consecutive write cycles are to be performed, the WE line may be held low until all desired locations have been written. In this case, data setup and hold times must be referenced to the rising of CE. FIGURE 6. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 18 Device types 02 - 06 and 08 - 16 NOTE: G is low throughout write cycle. To write, addresses must be stable, CE low and WE falling low for a period no shorter than tWLWH. Data is in referenced with the rising edge of WE or CE whichever occurs first (tDVWH and tWHDX). While addresses are changing, WE must be high. When WE falls low, the I/O pins are still in the output state for a period of tWLOZ and input data of the opposite phase to the outputs must not be applied (bus contention). If CE transitions low simultaneously with WE line transitioning low or after the WE transition, the output will remain in a high impedance state. OE is held continuously low. FIGURE 6. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 19 Device types 02 - 06 and 08 - 16 NOTE: W is high for a read cycle. Addresses must remain stable for the duration of the read cycle. To read, OE and CE must be < VIL and WE > VIH. The output buffers can be controlled independently by OE while CE is low. To execute consecutive read cycles, CE may be tied low continuously until all desired locations are accessed. When CE is low, addresses must be driven by stable logic levels and must not be in the high impedance stated. FIGURE 6. Timing waveforms - Continued. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 20 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. TABLE II. Electrical test requirements. MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table I) Interim electrical parameters (method 5004) Final electrical test parameters (method 5004) 1*, 2, 3, 7, 8A, 8B, 9, 10, 11 Group A test requirements (method 5005) 1, 2, 3, 4, 7, 8A, 8B, 9, 10, 11 Groups C and D end-point electrical parameters (method 5005) 1, 7, 9 * PDA applies to subgroup 1. 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CI and CO measurement) shall be measured only for the initial test and after process or design changes which may affect input capacitance. Sample size is five (5) devices with no failures, and all input and output terminals tested. d. Subgroups 7, 8A and 8B shall include verification of the truth table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 21 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor-prepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 84036 A REVISION LEVEL G SHEET 22 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 05-03-11 Approved sources of supply for SMD 84036 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This information bulletin is superseded by the next dated revisions of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number 8403601JA 3/ HM1-6516/883 8403601ZA 3/ HM1-6516/883 8403602JA 34371 HM1-65162/883 8403602ZA 4/ 34371 HM1-65162/883 8403603JA 4/ 34371 HM1-65162C/883 8403603ZA 3/ HM1-65162C/883 8403604JA 3/ 3/ MKB6116P-82 SMJ5517-15JDM 8403604ZA 3/ SMJ5517-15FGM 8403605JA 3/ 3/ MKB6116P-83 SMJ5517-20JDM 8403605ZA 3/ SMJ5517-20FGM 8403606JA 34371 HM1-65162B/883 8403606ZA 3/ HM1-65162B/883 8403607JA 3/ HM1-6516B/883 8403607ZA 3/ HM1-6516B/883 8403608JA 61772 IDT6116LA45DB 8403608XA 3/ IDT6116LA45L32B 8403608LA 61772 IDT6116LA45TDB 8403608KA 3/ IDT6116LA45EB 84036083A 3/ IDT6116LA45L28B 8403608YA 3/ IDT6116LA45L24B 1 of 5 Vendor similar PIN 2/ STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued Standard microcircuit drawing PIN 1/ Vendor CAGE number 8403609JA 61772 0C7V7 3/ IDT6116SA45DB QP6116A-45DMB CY6116A-45DMB 8403609XA 0C7V7 3/ 3/ QP6117A-45LMB IDT6116SA45L32B CY6117A-45LMB 8403609LA 0C7V7 3/ 61772 3/ 3DTT2 QP7C128A-45DMB SMJ68CE16S-45JDM IDT6116SA45TDB CY7C128A-45DMB P4C116-45DMB 8403609KA 0C7V7 3/ 3/ 3DTT2 QP7C128A-45KMB IDT6116SA45EB CY7C128-45KMB P4C116-45FMB 84036093A 0C7V7 3/ 3/ 3DTT2 QP6116A-45LMB IDT6116SA45L28B CY6116A-45LMB P4C116-45L28MB 8403609YA 0C7V7 3/ 3/ 3DTT2 QP7C128A-45LMB IDT6116SA45L24B CY7C128A-45LMB P4C116-45LMB 8403610JA 61772 IDT6116LA55DB 8403610XA 3/ 0C7V7 IDT6116LA55L32B 6116-55/XA 8403610LA 61772 IDT6116LA55TDB 8403610KA 3/ 0C7V7 3/ 0C7V7 IDT6116LA55EB 6116-55/KA 8403610YA 3/ 0C7V7 IDT6116LA55L24B 6116-55/YA 8403611JA 0C7V7 61772 3/ QP6116A-55DMB IDT6116SA55DB CY6116A-55DMB 8403611XA 0C7V7 3/ 3/ QP6117A-55LMB IDT6116SA55L32B CY6117A-55LMB 8403611LA 0C7V7 3/ 61772 3/ 3DTT2 QP7C128A-55DMB SMJ68CE16S-55JDM IDT6116SA55TDB CY7C128A-55DMB P4C116-55DMB 84036103A 2 of 5 Vendor similar PIN 2/ IDT6116LA55L28B 6116-55/3A STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued Standard microcircuit drawing PIN 1/ Vendor CAGE number 8403611KA 0C7V7 3/ 3/ 3DTT2 QP7C128A-55KMB IDT6116SA55EB CY7C128-55KMB P4C116-55FMB 84036113A 0C7V7 3/ 3/ 3DTT2 QP6116A-55LMB IDT6116SA55L28B CY6116A-55LMB P4C116-55L28MB 8403611YA 0C7V7 3/ 3/ 3DTT2 QP7C128A-55LMB IDT6116SA55L24B CY7C128A-55LMB P4C116-55LMB 8403612JA 61772 IDT6116LA70DB 8403612XA 3/ IDT6116LA70L32B 8403612LA 61772 IDT6116LA70TDB 8403612KA 3/ IDT6116LA70EB 84036123A 3/ IDT6116LA70L28B 8403612YA 3/ IDT6116LA70L24B 8403613JA 61772 8403613XA 3/ IDT6116SA70L32B 8403613LA 61772 IDT6116SA70TDB 8403613KA 3/ IDT6116SA70EB 84036133A 3/ IDT6116SA70L28B 8403613YA 3/ IDT6116SA70L24B 8403614JA 0C7V7 3/ QP6116A-35DMB CY6116A-35DMB 0C7V7 3/ QP6117A-35LMB CY6117A-35LMB 8403614LA 0C7V7 3/ 3/ 3DTT2 QP7C128A-35DMB SMJ68CE16S-35JDM CY7C128A-35DMB P4C116-35DMB 8403614KA 0C7V7 3/ 3DTT2 QP7C128A-35KMB CY7C128A-35KMB P4C116-35FMB 8403614XA 3 of 5 Vendor similar PIN 2/ IDT6116SA70DB STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued Standard microcircuit drawing PIN 1/ Vendor CAGE number 84036143A 0C7V7 3/ 3DTT2 QP6116A-35LMB CY6116A-35LMB P4C116-35L28MB 8403614YA 0C7V7 3/ 3DTT2 QP7C128A-35LMB CY7C128A-35LMB P4C116-35LMB 8403615JA 3/ 61772 L6116HMB120 IDT6116LA120DB 8403615XA 3/ 3/ 0C7V7 L6116TMB120 IDT6116LA120L32B 6116-120/XA 8403615LA 3/ 61772 L6116CMB120 IDT6116LA120TDB 8403615KA 3/ 3/ 0C7V7 L6116FMB120 IDT6116LA120EB 6116-120/KA 84036153A 3/ 3/ 0C7V7 L6116KMB120 IDT6116LA120L28B 6116-120/3A 8403615YA 3/ 3/ 0C7V7 L6116TMB IDT6116LA120L24B 6116-120/YA 8403616JA 3/ 61772 L6116HMB90 IDT6116LA90DB 8403616XA 3/ 3/ L6116TMB90 IDT6116LA90L32B 8403616LA 3/ 61772 L6116CMB90 IDT6116LA90TDB 8403616KA 3/ 3/ L6116FMB90 IDT6116LA90EB 84036163A 3/ 3/ L6116KMB90 IDT6116LA90L28B L6116TMB 3/ IDT6116LA120L24B 3/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Not available from an approved source. Vendor has indicated an end-of-life date of 10/5/04 for this device. 8403616YA 1/ 2/ 3/ 4/ Vendor similar PIN 2/ 4 of 5 Vendor CAGE number Vendor name and address 34371 Intersil Corporation 2401 Palm Bay Blvd PO Box 883 Melbourne, FL 32902-0883 61772 Integrated Device Technology 2975 Stender Way Santa Clara, CA 95054 3DTT2 Pyramid Semiconductor Corporation 1340 Bordeaux Drive Sunnyvale, CA 94089 0C7V7 QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. 5 of 5