REVISIONS
LTR DESCRIPTION DATE (YR-MO-DA) APPROVED
E
Change to vendor similar part number for vendor CAGE number 61772
for devices 08KX, 09KX, 10KX, 11KX, 12KX, 13KX, 14KX, 15KX, and
16KX. Remove vendor CAGE number 61772 from devices 08YX,
09YX, 10YX, 11YX, 12YX, 13YX, 15YX, and 16YX. Change to vendor
similar part number for vendor CAGE number 65786 for devices 09
and 11. Add vendor CAGE number 50088 to the drawing as a source
of supply for devices 04JX and 05JX. Add vendor CAGE number
65896 to the drawing as a source of supply for devices 15 and 16.
Removed 4.3.3 from drawing. Editorial changes throughout.
92-04-27
M. A. Frye
F
Added provisions for the addition of QD certified parts to drawing.
Updated boilerplate. Added CAGE OC7V7 as supplier. - ksr
00-09-27
Raymond Monnin
G
Correction to marking paragraph 3.5. Updated boilerplate paragraphs.
ksr
05-03-11
Raymond Monnin
THE ORIGINAL FIRST PAGE OF THIS DRAWING HAS BEEN REPLACED
CURRENT CAGE CODE 67268
REV
SHEET
REV G G G G G G G G
SHEET 15 16 17 18 19 20 21 22
REV STATUS REV G G G G G G G G G G G G G G
OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14
PMIC N/A PREPARED BY
James E. Jamison
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990
STANDARD
MICROCIRCUIT
DRAWING
CHECKED BY
Ray Monnin
http://www.dscc.dla.mil
THIS DRAWING IS
AVAILABLE
FOR USE BY ALL
DEPARTMENTS
APPROVED BY
Don Cool
MICROCIRCUITS, MEMORY,
DIGITAL, CMOS, 16K
(2048 X 8) BIT STATIC RAM,
AND AGENCIES OF THE
DEPARTMENT OF DEFENSE DRAWING APPROVAL DATE
84 – 08 - 24
MONOLITHIC SILICON
AMSC N/A
REVISION LEVEL
G SIZE
A CAGE CODE
14933
84036
SHEET
1 OF
22
DSCC FORM 2233
APR 97 5962-E215-05
.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 2
DSCC FORM 2234
APR 97
1. SCOPE
1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in
accordance with MIL-PRF-38535, appendix A.
1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example:
84036 01 J X
⏐ ⏐ ⏐ ⏐
⏐ ⏐ ⏐ ⏐
⏐ ⏐ ⏐ ⏐
⏐ ⏐ ⏐ ⏐
Drawing number Device type Case outline Lead finish
(see 1.2.1) (see 1.2.2) (see 1.2.3)
1.2.1 Device type(s). The device type(s) identify the circuit function as follows:
Device type Generic number 1/ Supply voltage variation Address access time
01 10% 200 ns (synchronous)
02 10% 90 ns
03 10% 90 ns
04 10% 150 ns
05 10% 200 ns
06 10% 70 ns
07 10% 120 ns (synchronous)
08 10% 45 ns
09 10% 45 ns
10 10% 55 ns
11 10% 55 ns
12 10% 70 ns
13 10% 70 ns
14 10% 35 ns
15 10% 120 ns
16 10% 90 ns
1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows:
Outline letter Descriptive designator Terminals Package style
J CDIP2-T24 or GDIP1-T24 24 dual-in-line package
K CDFP3-F24 or GDFP2-F24 24 flat package
L CDIP4-T24 or GDIP3-T24 24 dual-in-line package
X CQCC1-N32 32 rectangular chip carrier package
Y See Figure 1 24 rectangular chip carrier package
Z CQCC1-N32 32 rectangular chip carrier package with
castellated instead of chamfered
corners and extended pad metallization
at terminal number 1.
3 CQCC1-N28 28 square chip carrier package
1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A.
1/ Generic numbers are listed on the standardized military drawing source approval bulletin at the end of this Standard
Microcircuit Drawing and will also be listed in MIL-HDBK-103.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 3
DSCC FORM 2234
APR 97
1.3 Absolute maximum ratings.
Supply voltage range (VCC)-----------------------------------0.3 V dc to +7.0 V dc 2/
Temperature under bias---------------------------------------55°C to +125°C
Storage temperature range-----------------------------------55°C to +150°C
Maximum power dissipation (PD) --------------------------1.0 W
Lead temperature (soldering, 5 seconds)----------------+275°C
Thermal resistance, junction-to-case (θJC):--------------See MIL-STD-1835
Case Y---------------------------------------------------------- 30°C/W
Junction temperature (TJ)------------------------------------+150°C 3/
All input or output voltages with respect to ground-----0.3 V dc to VCC +0.3 V dc 4/
1.4 Recommended operating conditions.
Case operating temperature range (TC) --------------------55°C to +125°C
Input low voltage (VIL):
Device types 01 through 16 ----------------------------------0.3 V dc to 0.8 V dc 2/
Input high voltage (VIH):
Device types 01, 07--------------------------------------------2.4 V dc to VCC +0.3 V dc 2/
Device types 02 through 06, 08 through 16 ------------2.2 V dc to VCC +0.3 V dc 2/
Supply voltage range (VCC): ----------------------------------4.5 V dc to 5.5 V dc 2/
Minimum chip enable low time -----------------------------40 ns 5/
Minimum chip enable high time-----------------------------40 ns 5/
Maximum input rise time -------------------------------------40 ns
Maximum input fall time --------------------------------------40 ns
2. APPLICABLE DOCUMENTS
2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part
of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the
solicitation or contract.
DEPARTMENT OF DEFENSE SPECIFICATION
MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for.
DEPARTMENT OF DEFENSE STANDARDS
MIL-STD-883 - Test Method Standard Microcircuits.
MIL-STD-1835 - Interface Standard Electronic Component Case Outlines.
DEPARTMENT OF DEFENSE HANDBOOKS
MIL-HDBK-103 - List of Standard Microcircuit Drawings.
MIL-HDBK-780 - Standard Microcircuit Drawings.
(Copies of these documents are available online at http://assist.daps.dla.mil/quicksearch/ or http://assist.daps.dla.mil or from
the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.)
2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text
of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a
specific exemption has been obtained.
2/ All voltages referenced to VSS.
3/ Maximum junction temperature shall not be exceeded except for allowable short duration burn-in screening conditions
in accordance with method 5004 of MIL-STD-883.
4/ Negative undershoots to a minimum of -3.0 V are allowed with a maximum of 20 ns pulse width.
5/ For device types 02, 03, and 06 only.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 4
DSCC FORM 2234
APR 97
3. REQUIREMENTS
3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for non-
JAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer
Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MIL-PRF-
38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity
approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make
modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These
modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MIL-PRF-38535
is required to identify when the QML flow option is used. This drawing has been modified to allow the manufacturer to use the
alternate die/fabrication requirements of paragraph A.3.2.2 of MIL-PRF-38535 or alternative approved by the Qualifying Activity.
3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified
in MIL-PRF-38535, appendix A and herein.
3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein and figure 1.
3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2.
3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 3.
3.2.4 Logic diagram(s). The logic diagram(s) shall be as specified on figure 4.
3.2.5 Die overcoat. Polyimide and silicone coatings are allowable as an overcoat on the die for alpha particle protection only.
Each coated microcircuit inspection lot (see inspection lot as defined in MIL-PRF-38535) shall be subjected to and pass the
internal moisture content test at 5000 ppm (see method 1018 of MIL-STD-883). The frequency of the internal water vapor
testing shall not be decreased unless approved by the preparing activity for class M. The TRB will ascertain the requirements as
provided by MIL-PRF-38535 for classes Q and V. Samples may be pulled any time after seal.
3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are
as specified in table I and shall apply over the full case operating temperature range.
3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical
tests for each subgroup are described in table I.
3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed
in 1.2 herein. In addition, the manufacturer's PIN may also be marked.
3.5.1 Certification/compliance mark. The compliance mark for device class M shall be a "C" as required in MIL-PRF-38535,
Appendix A. For Class Q product built in accordance with A.3.2.2 of MIL-PRF -38535 or other alternative approved by the
Qualifying Activity, the "QD" certification mark shall be used in place of the "QML" or "Q" certification mark.
3.6 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an
approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to
listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535,
appendix A and the requirements herein.
3.7 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided
with each lot of microcircuits delivered to this drawing.
3.8 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing.
3.9 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's
facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the
reviewer.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 5
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics.
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
Test
Symbol
unless otherwise specified Min Max
IOH = -1 mA 1,2,3 01-07,
15,16
High-level output voltage VOH
IOH = -4 mA 1,2,3 08-14
2.4 V
IOL = +3.2 mA 01,07
IOL = +4.0 mA 02,03,
06,15
IOL = +2.0 mA 04,05,
16
Low-level output voltage VOL
IOL = +8.0 mA
1,2,3
08-14
0.4 V
01,02,
06,07
-1.0
1.0
04,05,
09,11,
13,14,
15,16
-10.0
10.0
High impedance output
leakage current
IIOLZ
IIOHZ
OE = VIH
1,2,3
03,08,
10,12
-5.0
5.0
µA
01,02,
06,07
-1.0
1.0
04,05,
15 -2.0 2.0
03,08,
10,12,
16
-5.0
5.0
Input leakage current
IIL
IIH
VIN = GND
VIN = 5.5 V
1,2,3
09,11,
13,14
-10.0
10.0
µA
01,07 10
04,05,
13,15,
16
90
02,03,
06
70
08,10,
12
85
09,11
120
Operating supply current
ICC1
VCC = 5.5 V, f = fmax 3/
CE = VIL, outputs open
All other inputs at VIL
1,2,3
14 150
mA
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 6
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
Test
Symbol
unless otherwise specified Min Max
02,03,
06
8
04,05
10
10,12,
15,16
15
Standby supply current
ICC2
CE = WE = VIH, IO = 0
1,2,3
09,11,
13,14
25
mA
06,07 50
01,02
100
04,05
250
03,08,
10,12,
15,16
900
µA
13
10
Standby supply current
ICC3
CE = VCC –0.3 V, IO = 0
1,2,3
09,11,
14
20
mA
01,02 50
04,05 100
08,10,
12,15,
16
200
03 300
Data retention current
ICC4
CE = VCC, VCC = 2.0 V
1,2,3
06,07 25
µA
Input capacitance 4/ CI V
I = VCC or GND
f = 1 MHz
See 4.3.1c
4
All
10
pF
Output capacitance 4/ CO V
I = VCC or GND
f = 1 MHz
See 4.3.1c
4
All
12
pF
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 7
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
01 280
02,03,16 90
04 150
05 200
15 120
07 170
08,09 45
10,11 55
06,12,13 70
Read/write cycle
time
tAVAV
5/ 6/
9, 10, 11
14 35
ns
01 200
02,03,16 90
04 150
05 200
07,15 120
08,09 45
10,11 55
06,12,13 70
Address access time
tAVQV
5/ 6/
9, 10, 11
14 35
ns
15,16 0
04,05 10
Output hold after
address change 4/
tAVQX
5/ 6/
9, 10, 11 02,03,06,
07,08-14 5
ns
01,07 10
02,03,06,
08,12,13 5
Output enable to output
active 4/
tOLQX
5/ 6/
9, 10, 11
04,05,09,
11,14,15,
16
0
ns
01,07,15 80
02,03,16 65
04 60
05 70
08,09 25
10,11 40
06,12,13 50
Output enable access
time
tOLQV
5/ 6/
9, 10, 11
14 20
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 8
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
01,07 10
02,03,06,
08-14 5
Chip enable to output
active 4/
tELQX
5/ 6/
9, 10, 11
04,05,15,
16 0
ns
01 200
02,03,16 90
04 150
05 200
07,15 120
08,09 45
10,11 55
06,12,13 70
Chip enable access
time
tELQV
5/ 6/
9, 10, 11
14 35
ns
01 80
02,03,07,
15,16 50
04,05 60
08,09 25
10,11 30
06,12,13 35
Chip enable to output in
high Z 4/
tEHQZ
5/ 6/
9, 10, 11
14 15
ns
02,03,04,
05,06,15,
16
10
Write recovery time
tWHAV
5/ 6/
9, 10, 11
09,11,14 0
ns
01 200
02,03,16 55
04 90
05,07 120
06 45
08,09,14 30
10-13 40
Chip enable to end-of-
write
tELWH
5/ 6/
9, 10, 11
15 70
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 9
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
02,03,
12,13 65
04 100
05 130
15 105
06 50
08,09,14 30
10,11 45
Address valid to end-of-
write
tAVWH
5/ 6/
9, 10, 11
16 80
ns
02-06,
15,16 10
07,08,09,
11,14 0
10 5
Address to WE setup
time
tAVWL
5/ 6/
9, 10, 11
12,13 15
ns
Address to CE setup
time
tAVEL
5/ 6/
9, 10, 11
01,07
0
ns
01 80
02,03,15,
16 40
04,07 50
05 60
08,09 25
10,11 30
06,12,13 35
Output enable to output
in high Z 4/
tOHQZ
5/ 6/
9, 10, 11
14 15
ns
01 200
02,03,16 55
04 90
05,07 120
15 70
08,11 25
06,10,
12,13 40
Write enable pulse
width
tWLWH
5/ 6/
9, 10, 11
09,14 20
ns
See footnotes at end of table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 10
DSCC FORM 2234
APR 97
TABLE I. Electrical performance characteristics - Continued.
Test
Symbol
Test conditions 1/ 2/
VSS = 0 V, 4.5 V ≤ VCC ≤ 5.5 V
-55°C ≤ TC ≤ +125°C
Group A
subgroups
Device
type
Limits
Unit
unless otherwise specified Min Max
01 80
02,03,06,
12,13,16 30
04,07 50
05 70
08,09 20
10,11 25
15 35
Data setup to end-of-
write
tDVWH
5/ 6/
9, 10, 11
14 15
ns
01,06,07 10
02,03,04,
05,15,16 15
08,09,11,
14 0
Data hold after end-of-
write
tWHDX
5/ 6/
9, 10, 11
10,12,13 5
ns
01 80
Minimum chip-enable
high time after write
tEHEL
5/ 6/
9, 10, 11 07 50
ns
01 50
Address hold time after
CE low
tELAX
5/ 6/
9, 10, 11 07 30
ns
01 200
Chip-enable pulse width
during write
tELEH
5/ 6/
9, 10, 11 07 120
ns
01 200
02,03,16 55
04 90
05,07 120
08 30
06,10,
12,13 40
09,14 20
11 25
Write enable pulse
setup time
tWLEH
5/ 6/
9, 10, 11
15 70
ns
1/ All voltages referenced to VSS.
2/ Negative undershoots to a minimum of -0.3 V are allowed with a maximum of 20 ns pulse width.
3/ fmax = 1/tAVAV
4/ Tested initially, and after any design or process change which could affect these parameters.
5/ AC measurements assume transition time < 5 ns and input levels are from VSS to 3.0 V. Output
load is specified on figure 5. Reference timing levels are at 1.5 V.
6/ For timing waveforms, see figure 6.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 11
DSCC FORM 2234
APR 97
Case Y
24 PIN RECTANGULAR LEADLESS CHIP CARRIER
Inches mm
.008 0.20
.020 0.50
.030 0.76
.040 1.01
.045 1.14
.050 1.27
.055 1.39
.062 1.57
.066 1.68
.078 1.98
.292 7.41
.308 7.82
.392 9.95
.408 10.36
FIGURE 1. Case outline.
Notes:
1. Dimensions are in inches.
2. Metric equivalents are for general information only.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 12
DSCC FORM 2234
APR 97
Device Types
All
Case Outlines
X and Z
Y, J, K, and L
3
Terminal
Number Terminal
Symbol Terminal
Number Terminal
Symbol Terminal
Number Terminal
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
NC
NC
NC
A7
A6
A5
A4
A3
A2
A1
A0
NC
DQ0, I/O0
DQ1, I/O1
DQ2, I/O2
VSS
NC
DQ3, I/O3
DQ4, I/O4
DQ5, I/O5
DQ6, I/O6
DQ7, I/O7
CE , E
A10
OE , G
WE , W
NC
A9
A8
NC
NC
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
---
---
---
---
---
---
---
---
A7
A6
A5
A4
A3
A2
A1
A0
DQ0, I/O0
DQ1, I/O1
DQ2, I/O2
VSS
DQ3, I/O3
DQ4, I/O4
DQ5, I/O5
DQ6, I/O6
DQ7, I/O7
CE , E
A10
OE , G
WE , W
A9
A8
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
---
---
---
---
A7
A6
A5
A4
A3
A2
NC
NC
A1
A0
DQ1, I/O1
DQ2, I/O2
DQ3, I/O3
VSS
DQ4, I/O4
DQ5, I/O5
DQ6, I/O6
DQ7, I/O7
DQ8, I/O8
CE , E
NC
NC
A10
OE , G
WE , W
A9
A8
VCC
FIGURE 2. Terminal connections.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 13
DSCC FORM 2234
APR 97
Device types 01 and 07
Read cycle
Inputs
Time
reference
CE
WE
OE
A
DQ
Function
-1 H X X X Z Memory disabled
0 Ψ H X V Z Cycle begins, addresses are latched
1 L H L X X Output enabled
2 L H L X V Output valid
3 Ξ H X X V Read accomplished
4 H X X X Z Prepare for next cycle (same as –1)
5 Ψ H X V Z Cycle ends, next cycle begins (same as 0)
Write cycle
Inputs
Time
reference
CE
WE
OE
A
DQ
Function
-1 H X H X X Memory disabled
0 Ψ X H V X Cycle begins, addresses are latched
1 L L H X X Write period begins
2 L
Ξ H X V Data is written
3 Ξ H H X X Write completed
4 H X H X X Prepare for next cycle (same as –1)
5 Ψ X H V X Cycle ends, next cycle begins (same as 0)
Device types 02 – 06 and 08 - 16
CE OE WE Mode DQ
VIH X X Deselect High Z
VIL X VIL Write DIN
VIL V
IL V
IH Read DOUT
VIL V
IH V
IH Read High Z
X = Don’t care
H = HIGH
L = LOW
V = VALID
Ψ = TRANSITION HIGH TO LOW
Ξ = TRANSITION LOW TO HIGH
FIGURE 3. Truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 14
DSCC FORM 2234
APR 97
Device types 01 and 07.
ALL LINES POSITIVE LOGIC –
ACTIVE HIGH
THREE-STATE BUFFERS:
A HIGH – OUTPUT ACTIVE
ADDRESS LATCHED AND GATED
DECODERS:
LATCH ON RISING EDGE OF L
GATE ON RISING EDGE OF G
FIGURE 4. Block diagram.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 15
DSCC FORM 2234
APR 97
Device types 02 – 06 and 08 - 16
FIGURE 4. Block diagram – Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 16
DSCC FORM 2234
APR 97
NOTE:
1. Including scope and jig capacitance.
FIGURE 5. Output loading.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 17
DSCC FORM 2234
APR 97
Device types 01 and 07
The address information is latched in the on chip registers on the falling edge of CE (t = 0), minimum address setup and hold
time requirements must be met. Aft er the required hold time, the address may change state without affecting device operation.
During time (t = 1), the outputs become enabled but data is not valid until time (t = 2), WE must remain high throughout the
read cycle. After the data has been read, CE may return high (t = 3). This will force the output buffers into a high impedance
mode at time (t = 4). OE is used to disable t he output buffers when in a logical "1" state (t = -1, 0, 3, 4, 5). After (t = 4) time, the
memory is ready for the next cycle.
FIGURE 6. Timing waveforms.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 18
DSCC FORM 2234
APR 97
Device types 01 and 07
The write cycles is initiated on the falling edge of CE (t = 0), which latches the address information in t he on chip registers. If a
write cycle is to be performed where t he output is not to become active, OE can be held high (inactive). Parameter tDVHW and
tWHDX must be met for proper device operation regardless of OE. If CE and OE fall bef ore WE falls (read mode), a possible bus
conflict may exist. If CE rises before WE rises, reference data setup and hold times to the CE rising edge. The write operation
is terminated by the first rising edge of WE (t = 2) or CE (t = 3). After the minimum CE high time (tEHEL), the next cycle may
begin. If a series of consecutive write cycles are to be performed, the W E line may be held low until all desired locations have
been written. In this case, data setup and hold times must be referenced to the rising of CE.
FIGURE 6. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 19
DSCC FORM 2234
APR 97
Device types 02 - 06 and 08 - 16
NOTE: G is low throughout write cycle.
To write, addresses must be stable, CE low and WE falling low for a period no shorter than tWLWH. Data is in referenced with the
rising edge of WE or CE whichever occurs first (tDVWH and tWHDX).
While addresses are changing, WE must be high. When WE falls low, the I/O pins are still in the output state for a period of
tWLOZ and input data of the opposite phase to the outputs must not be applied (bus contention). If CE transitions low
simultaneously with WE line transitioning low or after the WE transition, the output will remain in a high impedance state. OE is
held continuously low. FIGURE 6. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 20
DSCC FORM 2234
APR 97
Device types 02 - 06 and 08 – 16
NOTE: W is high for a read cycle.
Addresses must remain stable for the duration of the read cycle. T o read, OE and CE must
be < VIL and WE > VIH. The output buffers can be controlled independently by OE while CE
is low. To execute consecutive read cycles, CE may be tied low continuously until all
desired locations are accessed. When CE is low, addresses must be driven by stable logic
levels and must not be in the high impedance stated.
FIGURE 6. Timing waveforms - Continued.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 21
DSCC FORM 2234
APR 97
4. VERIFICATION
4.1 Sampling and inspection. Sampling and inspection procedures sha ll be in accordance with MIL-PRF-38535,
appendix A.
4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices
prior to quality conformance inspection. The following additional criteria shall apply:
a. Burn-in test, method 1015 of MIL-STD-883.
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request . The test circuit shall specify
the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method
1015 of MIL-STD-883.
(2) TA = +125°C, minimum.
b. Interim and final electrical test parameters shall be as specified in t able II herein, except interim electrical parameter
tests prior to burn-in are optional at the discret ion of the manufacturer.
TABLE II. Electrical test requirements.
MIL-STD-883 test requirements
Subgroups
(in accordance with
MIL-STD-883, method 5005,
table I)
Interim electrical parameters
(method 5004)
Final electrical test parameters
(method 5004)
1*, 2, 3, 7, 8A, 8B,
9, 10, 11
Group A test requirements
(method 5005)
1, 2, 3, 4, 7, 8A, 8B,
9, 10, 11
Groups C and D end-point
electrical parameters
(method 5005)
1, 7, 9
* PDA applies to subgroup 1.
4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of
MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply.
4.3.1 Group A inspection.
a. Tests shall be as specified in table II herein.
b. Subgroups 5 and 6 in table I, method 5005 of MIL-ST D-883 shall be omitted.
c. Subgroup 4 (CI and CO measurement) shall be measured only for the initial test and after process or design changes
which may affect input capacitance. Sample size is five (5) devices with no failures, and all input and output terminals
tested.
d. Subgroups 7, 8A and 8B shall include verification of the truth table.
STANDARD
MICROCIRCUIT DRAWING
SIZE
A
84036
DEFENSE SUPPLY CENTER COLUMBUS
COLUMBUS, OHIO 43218-3990 REVISION LEVEL
G SHEET 22
DSCC FORM 2234
APR 97
4.3.2 Groups C and D inspections.
a. End-point electrical parameters shall be as specified in table II herein.
b. Steady-state life test conditions, method 1005 of MIL-STD-883.
(1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level
control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall
specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in
method 1005 of MIL-STD-883.
(2) TA = +125°C, minimum.
(3) Test durat ion: 1,000 hours, except as permitted by method 1005 of MIL-STD-883.
5. PACKAGING
5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A.
6. NOTES
6.1 Intended use. Microcircuits conf orming to this drawing are intended for use for Government microcircuit applications
(original equipment), design applications, and logistics purposes.
6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a
contractor-prepared specification or drawing.
6.3 Configuration control of SMD' s. All proposed changes to existing SMD's will be coordinated with the users of record for
the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal.
6.4 Record of users. Military and industrial users should inform Defense Supply Center Columbus (DSCC) when a system
application requires configuration control and which SMD's are applicable to that system. DSCC will maintain a record of users
and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering
microelectronic devices (FSC 5962) should contact DSCC-VA, t elephone (614) 692-0544.
6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone
(614) 692-0547.
6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors list ed in MIL-
HDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitt ed to and accepted by
DSCC-VA.
STANDARD MICROCIRCUIT DRAWING BULLETI N
DATE: 05-03-11
Approved sources of supply for SMD 84036 are listed below for immediate acquisition information only and shall be
added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to
include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of
compliance has been submitted to and accepted by DSCC-VA. T his information bulletin is superseded by the next
dated revisions of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of
supply at http://www.dscc.dla.mil/Programs/Smcr/.
Standard
microcircuit
drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
8403601JA 3/
HM1-6516/883
8403601ZA 3/
HM1-6516/883
8403602JA 34371
HM1-65162/883
8403602ZA 4/ 34371
HM1-65162/883
8403603JA 4/ 34371
HM1-65162C/883
8403603ZA 3/
HM1-65162C/883
8403604JA 3/
3/
MKB6116P-82
SMJ5517-15JDM
8403604ZA 3/
SMJ5517-15FGM
8403605JA 3/
3/
MKB6116P-83
SMJ5517-20JDM
8403605ZA 3/
SMJ5517-20FGM
8403606JA 34371
HM1-65162B/883
8403606ZA 3/
HM1-65162B/883
8403607JA 3/
HM1-6516B/883
8403607ZA 3/
HM1-6516B/883
8403608JA 61772
IDT6116LA45DB
8403608XA 3/
IDT6116LA45L32B
8403608LA 61772
IDT6116LA45TDB
8403608KA 3/
IDT6116LA45EB
84036083A 3/
IDT6116LA45L28B
8403608YA 3/
IDT6116LA45L24B
1 of 5
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued
Standard
microcircuit
drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
8403609JA 61772
0C7V7
3/
IDT6116SA45DB
QP6116A-45DMB
CY6116A-45DMB
8403609XA 0C7V7
3/
3/
QP6117A-45LMB
IDT6116SA45L32B
CY6117A-45LMB
8403609LA 0C7V7
3/
61772
3/
3DTT2
QP7C128A-45DMB
SMJ68CE16S-45JDM
IDT6116SA45TDB
CY7C128A-45DMB
P4C116-45DMB
8403609KA 0C7V7
3/
3/
3DTT2
QP7C128A-45KMB
IDT6116SA45EB
CY7C128-45KMB
P4C116-45FMB
84036093A 0C7V7
3/
3/
3DTT2
QP6116A-45LMB
IDT6116SA45L28B
CY6116A-45LMB
P4C116-45L28MB
8403609YA 0C7V7
3/
3/
3DTT2
QP7C128A-45LMB
IDT6116SA45L24B
CY7C128A-45LMB
P4C116-45LMB
8403610JA 61772 IDT6116LA55DB
8403610XA 3/
0C7V7 IDT6116LA55L32B
6116-55/XA
8403610LA 61772 IDT6116LA55TDB
8403610KA 3/
0C7V7 IDT6116LA55EB
6116-55/KA
84036103A 3/
0C7V7 IDT6116LA55L28B
6116-55/3A
8403610YA 3/
0C7V7 IDT6116LA55L24B
6116-55/YA
8403611JA 0C7V7
61772
3/
QP6116A-55DMB
IDT6116SA55DB
CY6116A-55DMB
8403611XA 0C7V7
3/
3/
QP6117A-55LMB
IDT6116SA55L32B
CY6117A-55LMB
8403611LA 0C7V7
3/
61772
3/
3DTT2
QP7C128A-55DMB
SMJ68CE16S-55JDM
IDT6116SA55TDB
CY7C128A-55DMB
P4C116-55DMB
2 of 5
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued
Standard
microcircuit
drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
8403611KA 0C7V7
3/
3/
3DTT2
QP7C128A-55KMB
IDT6116SA55EB
CY7C128-55KMB
P4C116-55FMB
84036113A 0C7V7
3/
3/
3DTT2
QP6116A-55LMB
IDT6116SA55L28B
CY6116A-55LMB
P4C116-55L28MB
8403611YA 0C7V7
3/
3/
3DTT2
QP7C128A-55LMB
IDT6116SA55L24B
CY7C128A-55LMB
P4C116-55LMB
8403612JA 61772 IDT6116LA70DB
8403612XA 3/ IDT6116LA70L32B
8403612LA 61772 IDT6116LA70TDB
8403612KA 3/ IDT6116LA70EB
84036123A 3/ IDT6116LA70L28B
8403612YA 3/ IDT6116LA70L24B
8403613JA 61772 IDT6116SA70DB
8403613XA 3/ IDT6116SA70L32B
8403613LA 61772 IDT6116SA70TDB
8403613KA 3/ IDT6116SA70EB
84036133A 3/ IDT6116SA70L28B
8403613YA 3/ IDT6116SA70L24B
8403614JA 0C7V7
3/ QP6116A-35DMB
CY6116A-35DMB
8403614XA 0C7V7
3/ QP6117A-35LMB
CY6117A-35LMB
8403614LA 0C7V7
3/
3/
3DTT2
QP7C128A-35DMB
SMJ68CE16S-35JDM
CY7C128A-35DMB
P4C116-35DMB
8403614KA 0C7V7
3/
3DTT2
QP7C128A-35KMB
CY7C128A-35KMB
P4C116-35FMB
3 of 5
STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued
Standard
microcircuit
drawing
PIN 1/
Vendor
CAGE
number
Vendor
similar
PIN 2/
84036143A 0C7V7
3/
3DTT2
QP6116A-35LMB
CY6116A-35LMB
P4C116-35L28MB
8403614YA 0C7V7
3/
3DTT2
QP7C128A-35LMB
CY7C128A-35LMB
P4C116-35LMB
8403615JA 3/
61772
L6116HMB120
IDT6116LA120DB
8403615XA 3/
3/
0C7V7
L6116TMB120
IDT6116LA120L32B
6116-120/XA
8403615LA 3/
61772
L6116CMB120
IDT6116LA120TDB
8403615KA 3/
3/
0C7V7
L6116FMB120
IDT6116LA120EB
6116-120/KA
84036153A 3/
3/
0C7V7
L6116KMB120
IDT6116LA120L28B
6116-120/3A
8403615YA 3/
3/
0C7V7
L6116TMB
IDT6116LA120L24B
6116-120/YA
8403616JA 3/
61772
L6116HMB90
IDT6116LA90DB
8403616XA 3/
3/
L6116TMB90
IDT6116LA90L32B
8403616LA 3/
61772
L6116CMB90
IDT6116LA90TDB
8403616KA 3/
3/
L6116FMB90
IDT6116LA90EB
84036163A 3/
3/
L6116KMB90
IDT6116LA90L28B
8403616YA 3/
3/
L6116TMB
IDT6116LA120L24B
1/ The lead finish shown for each PIN representing a hermetic
package is the most readily available from the manufacturer
listed for that part. If the desired lead finish is not listed
contact the vendor to determine its availability.
2/ Caution. Do not use this number for item acquisition. Items
acquired to this number may not satisfy the performance
requirements of this drawing.
3/ Not available from an approved source.
4/ Vendor has indicated an end-of-life date of 10/ 5/04 for this device.
4 of 5
Vendor CAGE Vendor name
number and address
34371 Intersil Corporation
2401 Palm Bay Blvd
PO Box 883
Melbourne, FL 32902-0883
61772 Int egrated Device Technology
2975 Stender Way
Santa Clara, CA 95054
3DTT2 Pyramid Semiconductor Corporation
1340 Bordeaux Drive
Sunnyvale, CA 94089
0C7V7 QP Semiconductor
2945 Oakmead Village Court
Santa Clara, CA 95051
The information contained herein is disseminated for convenience only and
the Government assumes no liability whatsoever for any inaccuracies in the
information bulletin.
5 of 5
