SN74CBT3384A
10-BIT FET BUS SWITCH
SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D5-Ω Switch Connection Between Two Ports
DTTL-Compatible Input Levels
description/ordering information
The SN74CBT3384A provides ten bits of
high-speed TTL-compatible bus switching. The
low on-state resistance of the switch allows
connections to be made with minimal propagation
delay.
The device is organized as two 5-bit switches with
separate output-enable (OE) inputs. When OE is
low, the switch is on, and port A is connected to
port B. When OE is high, the switch is open, and
the high-impedance state exists between the two
ports.
ORDERING INFORMATION
TAPACKAGE†ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
SOIC DW
Tube SN74CBT3384ADW
CBT3384A
SOIC − DW Tape and reel SN74CBT3384ADWR CBT3384A
SSOP − DB Tape and reel SN74CBT3384ADBR CU384A
−40°C to 85°CSSOP (QSOP) − DBQ Tape and reel SN74CBT3384ADBQR CBT3384A
TSSOP PW
Tube SN74CBT3384APW
CU384A
TSSOP − PW Tape and reel SN74CBT3384APWR CU384A
TVSOP − DGV Tape and reel SN74CBT3384ADGVR CU384A
†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each 5-bit bus switch)
INPUTS INPUTS/OUTPUTS
1OE 2OE 1B1−1B5 2B1−2B5
L L 1A1−1A5 2A1−2A5
L H 1A1−1A5 Z
HLZ2A1−2A5
H H Z Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 2004, Texas Instruments Incorporated
DB, DBQ, DGV, DW, OR PW PACKAGE
(TOP VIEW)
1OE
1B1
1A1
1A2
1B2
1B3
1A3
1A4
1B4
1B5
1A5
GND
VCC
2B5
2A5
2A4
2B4
2B3
2A3
2A2
2B2
2B1
2A1
2OE
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74CBT3384A
10-BIT FET BUS SWITCH
SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
32
1A1 1B1
11
1A5
1
1OE
10 1B5
14 15
2A1 2B1
22
2A5
13
2OE
23 2B5
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI/O < 0) −50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): DB package 63°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DBQ package 61°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DW package 46°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 88°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
MIN MAX UNIT
VCC Supply voltage 4 5.5 V
VIH High-level control input voltage 2 V
VIL Low-level control input voltage 0.8 V
TAOperating free-air temperature −40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN74CBT3384A
10-BIT FET BUS SWITCH
SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = −18 mA −1.2 V
IIVCC = 5.5 V, VI = 5.5 V or GND ±1μA
ICC VCC = 5.5 V, IO = 0, VI = VCC or GND 3μA
ΔICC‡Control inputs VCC = 5.5 V, One input at 3.4 V, Other inputs at VCC or GND 2.5 mA
CiControl inputs VI = 3 V or 0 4 pF
Cio(OFF) VO = 3 V or 0, OE = VCC 4.5 pF
VCC = 4 V,
TYP at VCC = 4 V VI = 2.4 V, II = 15 mA 14 20
ron§
V 0
II = 64 mA 5 7 Ω
ron§
VCC = 4.5 V VI = 0 II = 30 mA 5 7
Ω
CC
VI = 2.4 V, II = 15 mA 10 15
†All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.
‡This is the increase in supply current for each input that is at the specified TTL voltage level, rather than VCC or GND.
§Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lowest voltage of the two (A or B) terminals.
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
VCC = 4 V VCC = 5 V
± 0.5 V UNIT
PARAMETER
(INPUT) (OUTPUT) MIN MAX MIN MAX
UNIT
tpdA or B B or A 0.35 0.25 ns
ten OE A or B 6.2 1.9 5.7 ns
tdis OE A or B 5.5 2.1 5.2 ns
The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).
SN74CBT3384A
10-BIT FET BUS SWITCH
SCDS004L − NOVEMBER 1992 − REVISED JANUARY 2004
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOH
VOL
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
7 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
Output
Waveform 1
S1 at 7 V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
3 V
0 V
VOH
VOL
0 V
VOL + 0.3 V
VOH − 0.3 V
0 V
Input
3 V
3.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
7 V
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
Figure 1. Load Circuit and Voltage Waveforms