1. General description
The PCA9846 is an ultr a-low voltag e, quad bidirectional translating switch controlled via
the I2C-bus. The SCL/SDA upstream p ai r fans ou t to four downstre am pairs, or channels.
Any or all SCx/SDx channels can be selected, determined by the programmable control
register. This feature allows mu ltiple devices with the same I2C-bus address to re side on
the same bus. The switch device can also sep arate a heavily loaded I2C-bus into separate
bus segments, eliminating the need for a bus buffer.
An active LOW reset input allows the PCA9846 to recover from a situation where one of
the downstre am I2C-buses is stuck in a LOW state. Pulling the RESET pin LOW resets
the I2C-bus state machine and deselects all the channels, as does the internal
Power-On Reset (POR) function.
The pass gates of the switches are constructed such that the VDD1 pin is used to limit the
maximum high volt age which is passed by the PCA9846. This allows the use of different
bus voltage s o n each ch annel, so that 0.8 V, 1.8 V, 2.5 V or 3.3 V parts can comm unicate
without any additional protection. External pull-up resistors pull the bus up to the desired
voltage level for each channel. All I/O pins are 3.6 V tolerant.
2. Features and benefits
Ultra-low voltage operation, down to 0.8 V to interface with next-generation CPUs
1-of-4 bidirectional translating switch
Fm+ I2C-bus interface logic; compatible with SMBus standards
Active LOW reset input
2 address pins allowing up to 16 devices on the I2C-bus
Channel selection via I2C-bus
Power-up with all switch channels deselected
Low Ron switches
Allows voltage level translation between 0.8 V, 1.8 V, 2.5 V and 3.3 V buses
Reset via I2C-bus software command
I2C Device ID function
No glitch on power-up
Supports hot insertion since all channels are de-selected at power-on
Low standby current
PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus switch with reset
Rev. 1.1 — 4 April 2017 Product data sheet
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 2 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
3.6 V tolerant inputs
0 Hz to 1 MHz clock frequency
ESD protection exceeds 6000 V HBM per JESD22-A114 and 1000 V CDM per
JESD22-C101
Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
Two packages offered: TSSOP16 and H V QF N1 6
3. Ordering information
[1] Package is in development. Contact NXP for availability.
3.1 Ordering options
[1] Package is in development. Contact NXP for availability.
Table 1. Ordering information
Type number Topside
marking Package
Name Description Version
PCA9846BS[1] 846 HVQFN16 plastic thermal enhanced very thin quad flat package;
no leads; 16 terminals; body 4 40.85 mm SOT629-1
PCA9846PW PCA9846 TSSOP16 plastic thin shrink small outline package; 16 leads;
body width 4.4 mm SOT403-1
Table 2. Ordering options
Type number Orderable
part number Package Packing method Minimum
order
quantity
Temperature ran ge
PCA9846BS[1] PCA9846BSJ HVQFN16 Reel 13” Q1/T1
*Standard mark SMD 6000 Tamb = 40 Cto+85C
PCA9846PW PCA9846PWJ TSSOP16 Reel 13” Q1/T1
*Standard mark SMD 2500 Tamb = 40 Cto+85C
PCA9846PW PCA9846PWZ TSSOP16 Reel 13” Q1/T1
*Standard mark SMD 500 Tamb = 40 Cto+85C
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 3 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
4. Block diagram
Fig 1. Block diagram of PCA9846
SWITCH CONTROL LOGIC
PCA9846
RESET
CIRCUIT
aaa-017304
SC0
SC1
SC2
SC3
SD0
SD1
SD2
SD3
VSS
VDD2
VDD1
RESET
I2C-BUS
CONTROL
INPUT
FILTER
SCL
SDA
A0
A1
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Product data sheet Rev. 1.1 — 4 April 2017 4 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
5. Pinning information
5.1 Pinning
5.2 Pin description
[1] HVQFN16 package die supply ground is connected to both the VSS pin and the exposed center pad. The
VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical,
and board-level performance, the exposed pad needs to be soldered to the board using a corresponding
thermal pad on the board, and for proper heat conduction through the board thermal vias need to be
incorporated in the printed-circuit board in the thermal pad region.
Fig 2. Pin configuration for TSSOP16 Fig 3. Pin configuration for HVQFN16
PCA9846PW
VDD1 VDD2
A0 SDA
RESET SCL
SD0 A1
SC0 SC3
SD1 SD3
SC1 SC2
VSS SD2
aaa-017305
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
aaa-017306
Transparent top view
SD1 SD3
SC0 SC3
SD0 A1
RESET SCL
SC1
V
SS
SD2
SC2
A0
V
DD1
V
DD2
SDA
4 9
3 10
2 11
1 12
5
6
7
8
16
15
14
13
terminal 1
index area
PCA9846ABS
Ta ble 3. Pin description
Symbol Pin Description
TSSOP16 HVQFN16
VDD1 1 15 logic level power supply
A0 2 16 address input 0
RESET 3 1 active LOW reset input
SD0 4 2 serial data 0
SC0 5 3 serial clock 0
SD1 6 4 serial data 1
SC1 7 5 serial clock 1
VSS 86
[1] supply ground
SD2 9 7 serial data 2
SC2 10 8 serial clock 2
SD3 11 9 serial dat a 3
SC3 12 10 serial clock 3
A1 13 11 address input 1
SCL 14 12 serial clock line
SDA 15 13 serial data line
VDD2 16 14 core logic power supply
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Product data sheet Rev. 1.1 — 4 April 2017 5 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6. Functional description
Refer to Figure 1 “Block diagram of PCA9846.
6.1 Device address
Following a START condition, the bus master mus t ou tpu t th e ad dr es s of th e slave it is
accessing. The address of the PCA9 846 is shown in Figure 4. the device pins A0 and A1
must be connected to a valid logic signal — HIGH, LOW, SCL or SDA — to ensure a valid
slave address, since no internal pull-up resistors are provided.
See Table 4.
Fig 4. Slave address
aaa-011933
1 X 1 X X X X R/W
X = programmable by hardware
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Product data sheet Rev. 1.1 — 4 April 2017 6 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.2 Software Reset General Call, and device ID addresses
Two other different addresses can be sent to the device.
General Call address: allows to r es et the devic e thr o ug h th e I 2C-bus upon reception
of the right I2C-bus sequence. See Section 6.2.1 “Software Reset for more
information.
Device ID address: allows to read ID information fr om the device (manufacturer, part
identification, revision). See Section 6.2.2 “Device ID (PCA9846 ID field) for more
information.
Ta ble 4. Address selection
PCA9846
address pins 8-bit
I2C-bus
address
Slave address/bit pattern
master must send
A1 A0 A7 A6 A5 A4 A3 A2 A1 A0 - R/W
0SCL0xE0h1110000 0/1
0 0 0xE2h1110001 0/1
0SDA0xE4h1110010 0/1
0 1 0xE6h1110011 0/1
1SCL0xE8h1110100 0/1
1 0 0xEAh1110101 0/1
1SDA0xECh1110110 0/1
1 1 0xEEh1110111 0/1
SCLSCL0xB0h1011000 0/1
SCL0 0xB2h1011001 0/1
SCLSDA0xB4h1011010 0/1
SCL1 0xB6h1011011 0/1
SDASCL0xB8h1011100 0/1
SDA0 0xBAh1011101 0/1
SDASDA0xBCh1011110 0/1
SDA1 0xBEh1011111 0/1
Fig 5. General Call address Fig 6. Device ID address
0
002aac115
0000000
R/W
R/W
002aac116
1 1 1 1 1 0 0
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Product data sheet Rev. 1.1 — 4 April 2017 7 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.2.1 Software Reset
The Software Reset Call allows all the devices in the I2C-bus to be reset to th e po we r- up
state value th rough a specific formatted I2C-bus command. To be performed correctly, it
implies that the I2C-bus is functional and that there is no device hanging the bus.
The Software Reset sequence is defined as following:
1. A START command is sent by the I2C-bus master.
2. The reserved General Call I2C-bus address ‘0000 000’ with the R/W bit set to 0 (w rite)
is sent by the I2C-bus ma ster.
3. The device acknowledg es after seeing the General Call address ‘0000 0000’ (00h)
only. If the R/W bit is set to 1 (rea d), no acknowledge is returned to the I2C-bus
master.
4. Once the General Call address has been sent and acknowledged, the master sends
1 byte. The value of the byte must be equal to 06h.
a. The device acknowledges this val ue only. If the byte is not equal to 06h, th e device
does not acknowledge it.
If more than 1 byte of data is sent, the device does not acknowledge any more.
5. Once the right byte has been sent and correctly acknowledged, the master sends a
STOP command to end the Software Reset sequence: the device then resets to the
default value (power-up value) and is ready to be addressed again within the sp ecified
bus free time. If the master sends a Repeated START instead, no reset is performed.
The I2C-bus master must interpret a non-acknowledge from the device (at any time) as a
‘Software Reset Abort’. The device doe s not initiate a reset of its regi sters.
The unique sequence that initiates a Software Reset is described in Figure 7.
Fig 7. Software Reset sequence
aaa-017308
0 0 0 0 0 0 0 AS 0
SWRST Call I2C-bus address
START condition R/W
acknowledge
from slave(s)
0 0 0 0 1 1 00
SWRST data = 06h
A
acknowledge
from slave(s)
P
PCA9846 is reset.
Registers are set to default power-up values.
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Product data sheet Rev. 1.1 — 4 April 2017 8 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.2.2 Device ID (PCA9846 ID field)
The Device ID field is a 3-byte read-only (24 bits) word giving the following information:
12 bits with the manufacturer name, unique per manufacturer (for example, NXP).
9 bits with the part identification, assigned by manufacturer.
3 bits with the die revision, assigned by manufacturer (for example, Rev X).
The Device ID is read-only, hardwired in the device and can be accessed as follows:
1. START comm and
2. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 0 (write): ‘1111 1000’.
3. The master sends the I 2C-bus slave address of the slave device it needs to ide ntif y.
The LSB is a ‘Don’t care’ value. Only one device must acknowledge this byte (the one
that has the I2C-bus slave address).
4. The master sends a Re-START command.
Remark: A ST OP command followed by a START command will reset the slave st ate
machine and the Device ID read cannot be performed. Also, a STOP command or a
Re-START command followed by an access to another slave device will reset the
slave state mach ine and the Device ID Read cannot be performed.
5. The master sends the Reserved Device ID I2C-bus address followed by the R/W bit
set to 1 (read): ‘1111 1001’.
6. The Device ID Read can be done, starting with the 12 manufacturer bits (first byte +
4 MSB of the second byte), followed by the 9 part identification bits (4 LSBs of the
second byte + 5 MSBs of the third byte), and then the 3 die revision bits (3 LSBs of
the third byte).
7. The master ends the read ing sequence by NACKing the last byte, thus resetting the
slave device state machine and allowing the master to send the STOP command.
Remark: The reading of the Device ID can be stopped anytime by sending a NACK
command.
If the master continues to ACK the bytes afte r the third byte, the slave rolls back to the
first byte and keeps sending the Device ID sequence until a NACK has been
detected.
For the PCA9846, the Device ID is shown in Figure 8.
Fig 8. PCA984 6 Device ID fiel d
0
aaa-017527
0 0
10 0 0 0 1 0 1
00 0 0 0 0 0 0
revision
1
0 0 0 0
part identification
manufacturer
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Product data sheet Rev. 1.1 — 4 April 2017 9 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.3 Control register
Following the successful acknowledgement of the slave address, the bus master will send
a byte to the PCA9846, which will be stored in the control register. If multiple bytes are
received by the PCA9846, it will save the last byte received. This register can be written
and read via the I2C-bus.
If more than 3 bytes are read, the slave device loops back to the first byte (manufacturer byte) and keeps sending data until the
master generates a ‘no acknowledge’.
Fig 9. Device ID field read opera t ion
aaa-011781
A7 A6 A5 A4 A3 A2 A1
I2C-bus slave address
of the device to be identified
A
no acknowledge
from master
P
STOP condition
M
11
M
10 M9 M8 M7 M6 M5 M4
Sr
repeated START
condition
1 A
R/W
S1111100
Device ID address
START condition
0 A
R/W
acknowledge from
one or several slaves
0 A
don’t care
acknowledge from
slave to be identified
1111100
Device ID address
acknowledge from
slave to be identified
A M3 M2 M1 M0
acknowledge
from master
manufacturer name = 000000000000
P8 P7 P6 P5 A
acknowledge
from master
P4 P3 P2 P1 P0 R2 R1 R0
part identification = 100001010 revision = 000
Fig 10. Control regis te r
002aab190
X X X X B3 B2 B1 B0
channel selection bits
(read/write)
76543210
channel 0
channel 1
channel 2
channel 3
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Product data sheet Rev. 1.1 — 4 April 2017 10 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.3.1 Control register definition
A SCx/SDx downstream pair, or channel, is selected by the contents of the control
register. This register is written after the PCA9846 has been addressed. All 8 bits of the
control byte are used to determin e which channel or channels ar e to be selected. Whe n a
channel is selected, it will become active after a STOP condition has been placed on the
I2C-bus. This ensures that all SCx/SDx lines will be in a HIGH state when the channel is
made active, so that no false conditions are generated at the time of connection. Notice
that multiple channels may simultaneously be selected.
Remark: Several channels can be enabled at the same time. Example: B3 = 0, B2 = 1,
B1 = 1, B0 = 0, means that channel 0 and channel 3 are disabled and channel 1 and
channel 2 are enabled. Care should be taken not to exceed the maximum bus
capacitance.
6.4 RESET input
The RESET input is an active LOW signal which may be used to recover from a bus fault
condition. By asserting this signal LOW for a minimum of tw(rst)L, the PCA9846 will reset its
registers and I2C-bus state machine and will deselect all channels.
6.5 Power-on reset
When power is applied to VDD, an internal Power-On Reset (POR) holds the PCA9846 in
a reset co ndition until VDD2 has reached VPOR. At this point, the reset cond ition is released
and the PCA9846 registe rs and I2C-bus st ate machine are initialized to their default st ates
(all zeroes) causing all the channels to be deselected.
6.6 Power-on reset requirements
In the event of a glitch or data corruption, PCA9846 can be reset to its default conditions
by using the power-on reset featur e. Power-on reset requires that the device go through a
power cycle to be completely reset. This reset also happens when the device is
powered on for the first time in an application.
Power-on reset is shown in Figure 11.
Ta ble 5. Contro l register
Write = channel selection; Read = channel status
D7 D6 D5 D4 B3 B2 B1 B0 Command
XXXXXXX0 channel 0 disabled
1 ch annel 0 enabled
XXXXXX0Xchannel 1 disabled
1 channel 1 enabled
XXXXX0XXchannel 2 disabled
1 channel 2 enabled
XXXX0XXXchannel 3 disabled
1 channel 3 enabled
0 0 0 0 0 0 0 0 no ch annel selected;
power-up/reset default state
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Product data sheet Rev. 1.1 — 4 April 2017 11 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Table 6 specifies the performance of the power-on reset feature for PCA9846 for both
types of power-on reset.
[1] Level that VDD2 can glitch down to with a ramp rate = 0.4 s/V, but not cause a functional disruption when tw(gl)VDD <1s.
[2] Glitch width that will not cause a functional disruption when VDD(gl) =0.5VDD2.
Glitches in the power supply can also affect the power-on reset performance of this
device. The glitch width (tw(gl)VDD) and glitch height (VDD(gl)) are dependent on each
other . Th e bypass capacit ance, source impedance , and device impedance ar e factors that
affect power-on reset performance. Figure 12 and Table 6 provide more information on
how to measure these specifications.
VPOR is critical to the power-on reset. VPOR is th e voltage level at which the reset condition
is released and all the re gist er s an d th e I 2C-bus/SMBus state machine are initialized to
their default states. The value of VPOR differs based on the VDD2 being lowered to or from
0V. Figure 13 and Table 6 provide more details on this specification.
Fig 11. VDD2 is lowered below the POR threshold, then ramped back up to VDD2
aaa-014361
V
DD2
time
ramp-down
(dV/dt)
f
ramp-up
(dV/dt)
r
time to re-ramp
when V
DD2
drops
to V
POR(min)
− 50 mV or
below 0.2 V to V
SS
t
d(rst)
V
I
drops below POR levels
Table 6. Recommended supply sequencing and ramp rates
Tamb =25
C (unless otherwise noted). Not tested; specified by design.
Symbol Parameter Condition Min Typ Max Unit
(dV/dt)ffall rate of change of voltage Figure 11 0.1 - 2000 ms
(dV/dt)rrise rate of change of voltage Figure 11 0.1 - 2000 ms
td(rst) reset delay time Figure 11; re-ramp time when VDD2
drops to VPOR(min) 50 mV) or below
0.2 V to VSS
1- - s
VDD(gl) glitch supply voltage difference Figure 12 [1] --1.0V
tw(gl)VDD supply voltage glitch pulse width Figure 12 [2] --10s
VPOR(trip) power-on reset trip voltage falling VDD2 0.7 - - V
rising VDD2 --1.5V
Fig 12. Glitch width and glitch height
aaa-014362
V
DD2
time
t
w(gl)VDD
∆V
DD(gl)
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Product data sheet Rev. 1.1 — 4 April 2017 12 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Fig 13. Power-on reset voltage (VPOR)
aaa-014363
POR
time
V
DD2
time
V
POR
(rising V
DD2
)
V
POR
(falling V
DD2
)
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Product data sheet Rev. 1.1 — 4 April 2017 13 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
6.7 Voltage level translation between I2C-buses
Today’s complex systems often use multiple power supplies to maximize power savings
and to meet the ope ra tin g spe cif ica tion s of the de vic es used. This means th at vario u s
I2C-buses are also operating at differing voltage levels and cannot simply connect
together. In addition, modern microcontrollers operate down to 0.8 V to save power,
further complicating the connection of I2C-buses.
The PCA9846 is specifically d esigned to seamlessly handle these vo ltage level translation
issues. Any combination of bus vo ltage s can be inte rmixed on the PCA9846 and co rrectly
translated to the ot he r bu s at F m+ (1 M Hz ) s pee d.
Figure 14 shows a typical application. The microcontroller acts as the master and
operates at 0.8 V with its I2C-bus swinging between 0 V and 0.8 V. The temperature
sensor on channel 0 of the PCA9846 has a operates at 3.3 V, while the GPIO Expander
on channel 1 operates down to 1.8 V to interface with chip select and reset inputs on
various other ICs also operating at 1.8 V. Channel 2 of the PCA9846 is connected to the
I2C-bus of a power management device, operating at 2.5 V. The other channels of
PCA9846 are simply left unconnected.
In this example, VDD1 of the PCA9846 is a bias supply and is set at the lowest bus volt age,
or 0.8 V of the microcontroller . VDD1 sets the input switch ing points of each SCL and SDA
at 0.3 VDD1 for a LOW level and 0.7 VDD1 for a HIGH level.
VDD2 is the core logic supply from which most of the PCA9846 circuitry runs and must be
greater than 1.65 V.
The I2C-bus is open-drain, so pull-up resistors are needed on each I2C-bus segment. This
is where the voltage level translation happens. The pass transistor internal to the
PCA9846 limit the output voltage to the lower of VDD1 or VDD2. The pull-up resistors will
then limit the HIGH level of ea ch bu s se gm e nt to the powe r su pply of th e de vice s on tha t
segment. Note that the pull-up resistors on channel 0 are connected to 3.3 V, the and
resistors on channel 1 are connected to 1.8 V, while the resistors on channel 2 are
connected to 2.5 V — effectively translating the 0.8 V signal swing of the microcontroller
to the correct voltage level for each peripheral.
It is possible to level shif t from a higher volt age microcontrolle r connected to VDD1 to lower
voltage peripherals on the downstream side — the opposite of this par ticular example , as
long as VDD1 > 0.8 V and VDD2 > 1.65 V.
One thing to note is noise margin on each I2C-bus segment is somewhat reduced due to
the input levels set by VDD1. Especially in this example, the I2C-bus LOW level is
0.3 VDD1 or 0.24 V, so extreme care must be taken to ensure all bus segme nts meet this
specification. It also means that static offset buffers may not work correctly if the offset
side is connected to the PCA9846.
Another point to examine is that there is no buf fering cap ability between the upstream and
the downstream buses. This is simply a pass transistor, which acts like a switch and a
series resistor, between these bus segments. The series resist ance is the Ron of the pass
transistor and is inversely proportional to the minimum of VDD1 + VTH or VDD2, where VTH
is approximately 0.8 V. Refer to Table 8 for some representative Ron values. An upcoming
application note will explain Ron more thoroughly. Therefore, a careful analysis of bus
capacitance and pull-up resistor values is called for.
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Product data sheet Rev. 1.1 — 4 April 2017 14 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
A further point to consider is pull-up resistor selection. Since multiple channels can be
simultaneously selected, the pull-up resistors on each channel are connected in parallel.
Ensure each device can correctly drive the effective pull-up resistor value and still meet
the LOW-level specifications.
Fig 14. Ty pical app lication for PCA9846 with differing bus voltages
PCA9846
SC0
SD0
SDA
SCL
1.8 V
0.8 V
MICRO-
CONTROLLER
aaa-017307
SDA
SCL SC1
SD1
SC2
SD2
VDD2
0.8 V
VDD1
3.3 V 3.3 V
1.8 V 1.8 V
2.5 V 2.5 V
SCL
SDA
TEMP
SENSOR
3.3 V
SCL
SDA
GPIO
1.8 V
SCL
SDA
POWER MGMT
CONTROLLER
2.5 V
VDD
0.8 V 0.8 V
SC3
SD3
0.8 V to 3.6 V
SCL
SDA
I2C-BUS
PERIPHERAL
0.8 V to 3.6 V
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Product data sheet Rev. 1.1 — 4 April 2017 15 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
7. Characteristics of the I2C-bus
The PCA9846 is an I2C slave device. Data is exchanged between the master and the
PCA9846 through write an d re ad command s con fo rming to th e I2C-bus protocol. The two
communication lines are SCL (serial clock) and SDA (serial data), both of which must be
connected to VDD1 through pull-up resistors.
7.1 Write commands
Data is transmitted to the PCA9846 by sending its device address a nd setting the Least
Significant Bit (LSB) to a logic 0 (see Table 4 for device addresses), which the PCA9846
acknowledges (ACK). The control register byte is sent after the address that determines
which downstream channel is connected to the upstream channel by bit 0 through bit 2.
Bit 7 through bit 3 are ignored and can be writte n with any data. There is no limit on the
number of bytes sent after the address and before a STOP condition, only the last byte
written before the STOP condition is recognized and the selected channel is enabled only
at the following STOP condition.
7.2 Read commands
Data is read from the PCA9846 by sending its device address and setting the Least
Significant Bit (LSB) to a logic 1 (see Table 4 for device addresses), which the PCA9846
acknowledges. The control register byte is read by the master with each byte either ACK
or NACK by the master. If the master ACKs the control register byte, it continues to send
register data until the master NACKs, signaling the transaction is complete. There is no
limit on the number of bytes read from the PCA9846.
The control register bit defin itions are shown in Figure 10. Bit 0 through bit 2 will show the
enabled channels (as determined by the last write).
Refer to Table 4.
Fig 15. Write control register
aaa-019449
B7 B6 B5 B4 B3 B2 B1 B01/0 1 1/0 1/0 1/0 1/0 0 AS 1 A P
slave address
START condition R/W acknowledge
from slave
acknowledge
from slave
control register
SDA
STOP condition
Refer to Table 4.
Fig 16. Read control register
aaa-019450
B7 B6 B3 B2 B1 B01/0 1 1/0 1/0 1/0 1/0 1 AS 1 NA P
slave address
START condition R/W acknowledge
from slave
no acknowledge
from master
control register
SDA
STOP condition
last byte
B5 B4
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 16 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
8. Limiting values
[1] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 125 C.
9. Static characteristics
Table 7. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Voltages are referenced to VSS (ground=0V)
[1].
Symbol Parameter Conditions Min Max Unit
VDD supply voltage 0.5 +4.0 V
VIinput voltage 0.5 +4.0 V
IIinput current - 20 mA
IOoutput current - 25 mA
IDD supply current - 100 mA
ISS ground supply current - 100 mA
Ptot total power dissipation - 400 mW
Tstg storage temperature 60 +150 C
Tamb ambient temperature operating 40 +85 C
Table 8. Static characteristics
VSS = 0 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
Supply
VDD1 supply voltage 1 0.8 - 3.6 V
VDD2 supply voltage 2 1.65 - 3.6 V
IDD(VDD2) supply current on pin VDD2 VDD1 =3.6V, V
DD2 =3.6V; SC0toSC7
and SD0 to SD7 not connected;
RESET =V
DD1; A0 = A1 = SCL;
continuous register read/write
fSCL = 0 kHz - 5 12 A
fSCL = 100 kHz - 8 20 A
fSCL = 1000 kHz - 65 150 A
IDD(VDD1) supply current on pin VDD1 VDD1 =3.6V, V
DD2 =3.6V; SC0toSC7
and SD0 to SD7 not connected;
RESET =V
DD1; A0 = A1 = SCL;
continuous register read/write
fSCL = 0 kHz 52+2 A
fSCL = 100 kHz - 5 15 A
fSCL = 1000 kHz - 45 100 A
VPOR power-on reset voltage - 1.2 1.5 V
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 17 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
[1] Not tested in production. Guaranteed by design and characterization.
Input SCL; input/outpu t S DA
VIL LOW-level input voltage VDD1 1.1 V 0.5 - +0.2VDD1 V
VDD1 >1.1V 0.5 - +0.3VDD1 V
VIH HIGH-level input voltage VDD1 =1.1 V 0.8VDD1 -3.6 V
VDD1 > 1.1 V 0.7VDD1 -3.6 V
IOL LOW-level output current VOL = 0.4 V; VDD2 2V 15 - - mA
VOL = 0.4 V; VDD2 >2V 20 - - mA
ILleakage current VI=V
DD or VSS 1-+1 A
Ciinput capacitance VI=V
SS; all channels disabled [1] -2040pF
Select input s A0 to A1, RESET
VIL LOW-level input voltage VDD1 1.1 V 0.5 - +0.2VDD1 V
VDD1 >1.1V 0.5 - +0.3VDD1 V
VIH HIGH-level input voltage VDD1 1.1 V 0.8VDD1 -3.6
VDD1 > 1.1 V 0.7VDD1 -3.6 V
ILI input leakage current pin at VDD2 to 3.6 V or VSS 1-+1 A
Ciinput capacitance VI=V
SS or VDD1 [1] -510pF
Pass gate
Ron ON-state resistance ON resistance of the pass transistor
between SCL and SCx, and SDA and
SDx
VDD1 = 0.8 V; VDD2 1.65 V;
Vi(sw) =0.16V; I
O=3mA -1524
VDD1 = 1.2 V; VDD2 1.8 V;
Vi(sw) =0.24V; I
O=6mA -1218
VDD1 >2V; V
DD2 2.5 V;
Vi(sw) =0.4V;I
O=20mA -710
Io(sw) switch output current VDD2 = 1.65 V to 3 .6 V;
Vi(sw) =V
DD1 to 3.6 V;
Vo(sw) =V
DD1 to 3.6 V
0-100A
ILleakage current VI=V
DD or VSS 1-+1 A
Cio input/output capacitance VI=V
SS; all switches disabled [1] -815pF
Table 8. Static characteristics …continued
VSS = 0 V; Tamb =
40
C to +85
C; unless otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 18 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Ron = (Vo(sw) (Vi(sw)) / Io; Vi(sw) and Io are defined in Table 8
Fig 17. Ron test circuit
SDA or
SCL
SDx or
SCx
DUT
V
i(sw)
= 0.2 V
DD1
Measured V
o(sw)
V
DD2
I
O
V
DD1
aaa-015928
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 20 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
[1] Pass gate propagation delay is calculated from the 20 typical Ron and the 50 pF load capacitance.
[2] After this period, the first clock pulse is generated.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (referred to the VIH(min) of the SCL signal) in order to
bridge the undefined region of the falling edge of SCL.
[4] Necessary to be backwards compatible to Fast-mode.
[5] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should
allow for this when considering bus timing.
[6] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns.
[7] Measurements taken with 1 k pull-up resistor and 50 pF load.
[8] The maximum tHD;DAT could be 3.45 s and 0.9 s for Standard-mode and Fast-mode, but must be less than the maximum of tVD;DAT or
tVD;ACK by a transition time. This maximum must only be met if the device does not stretch the LOW period (tLOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
Fig 18. Definition of timing on the I2C-bus
t
SP
t
BUF
t
HD;STA
PP S
t
LOW
t
r
t
HD;DAT
t
f
t
HIGH
t
SU;DAT
t
SU;STA
Sr
t
HD;STA
t
SU;STO
SDA
SCL
002aaa986
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
Fig 19. Def inition of RESET timing
SDA
SCL
002aac549
50 %
30 %
50 % 50 %
t
REC;STA
t
w(rst)L
RESET
START
t
rst
ACK or read cycle
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 21 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Rise and fall times refer to VIL and VIH.
Fig 20. I2C-bu s timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
tHD;STA tSU;DAT tHD;DAT
tf
tBUF
tSU;STA tLOW tHIGH
tVD;ACK tSU;STO
1 / fSCL
tr
tVD;DAT
0.3 × VDD
0.7 × VDD
0.3 × VDD
0.7 × VDD
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 22 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
11. Package outline
Fig 21. Package outline SOT403-1 (TSSOP16)
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PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 23 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Fig 22. Package outline SOT629-1 (HVQFN16)
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PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 24 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
12. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
12.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on on e printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
12.2 Wave and reflow soldering
W ave soldering is a joining te chnology in which the joints are m ade by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solde r lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads ha ving a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering ve rsus SnPb soldering
12.3 Wave soldering
Key characteristics in wave soldering are:
Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
Solder bath specifications, including temperature and impurities
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 25 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
12.4 Reflow soldering
Key characteristics in reflow soldering are :
Lead-free ve rsus SnPb soldering; note th at a lead-free reflow process usua lly leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus
reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) an d cooling down. It is imperative that the peak
temperature is high enoug h for the solder to make reliable solder joint s (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. Th e peak temperature of the package
depends on p ackage thickness and volume and is classified in accordance with
Table 10 and 11
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during r eflow
soldering, see Figure 23.
Ta ble 10. SnPb eutectic process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350
< 2.5 235 220
2.5 220 220
Ta ble 11. Lead -fr ee process (from J-STD-020D)
Package thickness (mm) Package reflow temperature (C)
Volume (mm3)
< 350 350 to 2000 > 2000
< 1.6 260 260 260
1.6 to 2.5 260 250 245
> 2.5 250 245 245
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 26 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
For further informa tion on temperature profiles, re fer to Application Note AN10365
“Surface mount reflow soldering description”.
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
001aac844
temperature
time
minimum peak temperature
= minimum soldering temperature
maximum peak temperature
= MSL limit, damage level
peak
temperature
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 27 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
13. Soldering: PCB footprints
Fig 24. PCB footprint for SOT403-1 (TSSOP16 ); re flow soldering
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PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 28 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Fig 25. PCB footprint for SOT629-1 (HVQFN16); reflow soldering
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PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 29 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
14. Abbreviations
15. Revision history
Ta ble 12. Abbreviations
Acronym Description
CDM Charged-Device Model
CPU Central Processing Unit
ESD ElectroStatic Discharge
Fm+ Fast-mode Plus
HBM Human Body Model
IC Integrated Circuit
I2C-bus Inter-Inte grated Circu it bus
LSB Least Significant Bit
MSB Most Significant Bit
PCB Printed-Circuit Board
SMBus System Management Bus
Table 13. Revision history
Document ID Release date Data sh eet status Change notice Supersedes
PCA9846 v.1.1 20170404 Product data sheet 201703016I PCA9846 v.1
Modifications: Section 6.7 “Voltage level translation between I2C-buses: Minor text edits to clarify
operation of device.
Tabl e 1 “Ordering information: Corrected topside marking for PCA9846PW; no change to
device.
PCA9846 v.1 20151109 Product data sheet - -
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 30 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is document m ay have cha nged since thi s document w as publish ed and may di ffe r in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warrant ies as to t he accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not b e relied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semicond uctors sales
office. In case of any inconsistency or conflict wit h the short data sheet, th e
full data sheet shall pre va il.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warrant ies, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggreg ate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipme nt, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for il lustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applicati ons or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Custo mers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party custo mer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter m s and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or the gr ant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
PCA9846 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2017. All rights reserved.
Product data sheet Rev. 1.1 — 4 April 2017 31 of 32
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omotive use. It i s neither qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in au tomotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standards, custome r
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such au tomotive applications, use and specificatio ns, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconduct ors for an y
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respective ow ners.
I2C-bus — logo is a trademark of NXP Semi conductors N.V.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to : salesaddresses@nxp.com
NXP Semiconductors PCA9846
4-channel ultra-low voltage, Fm+ I2C-bus swit ch with reset
© NXP Semiconductors N.V. 2017. Al l rights reserv ed.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 4 April 2017
Document identifier: PCA9846
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
3.1 Ordering options. . . . . . . . . . . . . . . . . . . . . . . . 2
4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 5
6.1 Device address. . . . . . . . . . . . . . . . . . . . . . . . . 5
6.2 Software Reset General Call, and device ID
addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6.2.1 Software Reset. . . . . . . . . . . . . . . . . . . . . . . . . 7
6.2.2 Device ID (PCA9846 ID field). . . . . . . . . . . . . . 8
6.3 Control register. . . . . . . . . . . . . . . . . . . . . . . . . 9
6.3.1 Control register definition . . . . . . . . . . . . . . . . 10
6.4 RESET input. . . . . . . . . . . . . . . . . . . . . . . . . . 10
6.5 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . 10
6.6 Power-on reset requirements . . . . . . . . . . . . . 11
6.7 Voltage level translation between I2C-buses . 13
7 Characteristics of the I2C-bus . . . . . . . . . . . . 15
7.1 Write commands. . . . . . . . . . . . . . . . . . . . . . . 15
7.2 Read commands . . . . . . . . . . . . . . . . . . . . . . 15
8 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 16
9 Static characteristics. . . . . . . . . . . . . . . . . . . . 16
10 Dynamic characteristics . . . . . . . . . . . . . . . . . 19
11 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22
12 Soldering of SMD packages . . . . . . . . . . . . . . 24
12.1 Introduction to soldering . . . . . . . . . . . . . . . . . 24
12.2 Wave and reflow soldering . . . . . . . . . . . . . . . 24
12.3 Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . 24
12.4 Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . 25
13 Soldering: PCB footprints. . . . . . . . . . . . . . . . 27
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 29
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 29
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 30
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 30
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 30
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
17 Contact information. . . . . . . . . . . . . . . . . . . . . 31
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32