DS04-27202-6E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©1994-2006 FUJITSU LIMITED All rights reserved
ASSP
BIPOLAR
SWITCHING REGULATOR
CONTROLLER
MB3769A
■DESCRIPTION
The Fujitsu MB3769A is a pulse-width-modulation controller which is applied to fix ed frequency pulse modulation
technique. The MB3769A contains wide band width Op-Amp and high speed comparator to construct very high
speed switching regulator system up to 700 kHz. Output is suitable for power MOS FET drive owing to adoption
of totem pole output.
The MB3769A provides stand-b y mode at lo w v oltage po wer supp ly when it is applied in primary control system.
■ FEATURES
• High frequency oscillator (f = 1 kHz to 700 kHz)
• On-chip wide band frequency operation amplifier (BW = 8 MHz Typ)
• On-chip high speed comparator (td = 120 ns Typ)
• Internal reference voltage generator provides a stable reference supply (5 V ± 2%)
• Low power dissipation (1.5 mA Typ at standby mode, 8 mA Typ at operating mode)
• Output current ± 100 mA (± 600 mA at peak)
•High speed switching operation (tr = 60 ns, tf = 30 ns, CL = 1000 pF Typ)
• Adjustable Dead-time
• On-chip soft start and quick shut down functions
• Internal circuitry prohibits double pulse at dynamic current limit operation
• Under voltage lock out function (OFF to ON: 10 V Typ, ON to OFF: 8 V Typ)
• On-chip output shut down circuit with latch function at over voltage
• On-chip Zener diode (15 V)
• One type of package (SOP-16pin : 1 type)
■APPLICATIONS
• Power supply module
• Industrial Equipment
• AC/DC Converter etc.
MB3769A
2
■PIN ASSIGNMENT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+IN (OP)
-IN (OP)
FB
DTC
CT
RT
GND
VL
+IN (C)
-IN (C)
VREF
OVP
VCC
VZ
VH
OUT
(TOP VIEW)
(FPT-16P-M06)
MB3769A
3
■BLOCK DIAGRAM
+
-
+
-
-
+
+
+
+
+
+
-
-
+
S
R
Q
S
R
Q
Triangle Wave
Oscillator
Ov er Voltage Detector
-
+
Reference
Regulator +
-
Power
off
2.5 V
1.5 V to 3.5 V
(2.5 V)
15.4 V
30 kΩ
5.0 + 0.1 V
8/10 V STB
Over Current Detection Comparator
PWM
Comp.
1.85 V
1.8 V
STB STB
VREF
VH
VL
VREF
OUT
Error
Amp
DTC
FB
-IN (OP)
OVP
C T
R T
V CC
V Z
GND
Fig. 1 - MB3769A Block Diagram
16
4
3
1
2
13
5
6
12
11
7
14
8
9
10
15
-IN (C)
+IN (C)
+IN (OP)
MB3769A
4
■ABSOLUTE MAXIMUM RATINGS
*1 : Duty ≤ 5%
*2 : Ta = + 25 °C, SOP package is mounted on the epoxy board. (4 cm x 4 cm x 0.15 cm)
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Rating Unit
Min Max
Power Supply Voltage VCC ⎯20 V
Output Current IOUT ⎯120 (660*1)mA
Operation Amp Input Voltage Vin (OP) ⎯VCC + 0.3 (≤ 20) V
Power Dissipation : SOP PD⎯620*2mW
Storage Temperature TSTG -55 +125 °C
MB3769A
5
■RECOMMENDED OPERATING CONDITIONS
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol SOP package Unit
Min Typ Max
Power Supply Voltage VCC 12 15 18 V
Output Current (DC) IOUT -100 - +100 mA
Output Current (Peak) IOUT PEAK -600 - +600 mA
Operation Amp Input voltage VINOP -0.2 0 to VREF VCC-3 V
FB Sink Current ISINK --0.3mA
FB Source Current ISOURCE --2mA
Comparator Input Voltage VINC+-0.3 0 to 3 VCC V
VINC--0.3 0 to 2 2.5 V
Reference Section Output Current IREF -210mA
Timing Resistor RT91850kΩ
Timing Capacitor CT100 680 106pF
Oscillator Frequency fOSC 1 100 700 kHz
Zener Current IZ--5mA
Operating Ambient Temperature: SOP Ta -30 +25 +75 °C
MB3769A
6
■ELECTRICAL CHARACTERISTICS
(Continued)
(VCC=15V, Ta=+25°C)
Parameter Symbol Condition Value Unit
Min Typ Max
Reference
Section
Output Voltage VREF IREF = 1 mA 4.9 5.0 5.1 V
Input Regulation ∆VRIN 12 V ≤ VCC ≤ 18 V - 2 15 mV
Load Regulation ∆VRLD 1 mA ≤ IREF ≤10 mA - -1 -15 mV
Temp. Stability ∆VRTEMP -30 °C ≤ Ta ≤ +85 °C - ±200 ±750 µV/ °C
Short Circuit Output Current ISC VREF = 0 V 15 40 - mA
Oscillator
Section
Oscillator Frequency fOSC RT = 18 kΩ
CT = 680 pF 90 100 110 kHz
Voltage Stability ∆fOSCIN 12 V ≤ VCC ≤ 18 V - ±0.03 - %
Temp. Stability ∆fOSC /∆T-30 °C ≤ Ta ≤ +85 °C- ±2 - %
Dead -time
Control
Section
Input Bias Current ID--210µA
Max. Duty Cycle Dmax Vd = 1.5 V 75 80 85 %
Duty Cycle Set Dset Vd = 0.5 VREF 45 50 55 %
Input
Threshold
Voltage
0% Duty
Cycle VDO --3.53.8V
Max. Duty
Cycle VDM - 1.55 1.85 - V
Discharge Voltage VDH VCC = 7 V,
IDTC = -0.3 mA 4.5 - - V
Error
Amplifier
Section
Input Offset Voltage VIO (OP) V3 = 2.5 V - ±2 ±10 mV
Input Offset Current IIO (OP) V3 = 2.5 V - ±30 ±300 nA
Input Bias Current IIR (OP) V3 = 2.5 V -1 -0.3 - µA
Common-Mode Input Voltage VCM (OP) 12 V ≤ VCC ≤ 18 V -0.2 - VCC -3 V
Voltage Gain Av (OP) 0.5 V ≤ V3 ≤ 4 V 70 90 - dB
Band Width BW Av = 0 dB - 8 - MHz
Slew Rate SR RL = 10 kΩ, Av = 0 dB - 6 - V/µs
Common-Mode Rejection Rate CMR VIN = 0 V to 10 V 65 80 - dB
“H” Level Output Voltage VOH I3 = -2 mA 4.0 4.6 - V
“L” Level Output Voltage VOL I3 = 0.3 mA - 0.1 0.5 V
MB3769A
7
(Continued)
* : VCC = 8V
(VCC=15V, Ta=+25°C)
Parameter Symbol Condition Value Unit
Min Typ Max
Current
Comparator
Input Offset Voltage VIO (C) VIN = 1 V -±5±15 mV
Input Bias Current IIB (C) VIN = 1 V -5 -1 - µA
Common-Mode Input
Voltage VCM (C) -0-2.5V
Voltage Gain AV (C) --200- V/V
Response Time td 50 mV over drive -120250ns
PWM
Comparator
Section
0% Duty Cycle VOPO RT = 18 kΩ
CT = 680 pF -3.53.8 V
Max Duty Cycle VOPM 1.55 1.85 - V
Output
Section
“H” Level Output Voltage VHIOUT = -100 mA 12.5 13.5 - V
“L” Level Output Voltage VLIOUT = 100 mA -1.11.3 V
Rise Time tr CL = 1000 pF,
RL = ∞- 60 120 ns
Fall Time tf CL = 1000 pF,
RL = ∞-3080ns
Over
Voltage
Detector
Threshold Voltage VOVP -2.4 2.5 2.6 V
Input Current IIOVP VIN = 0 V -1.0 -0.2 - µA
VCC Reset VCC RST -2.0 3.0 4.5 V
Under
Voltage
Out Stop
Off to On VTHH -9.2 10.0 10.8 V
On to Off VTHL -7.2 8.0 8.8 V
Supply
Current
Standby * ISTB RT = 18 kΩ
4 pin Open -1.52.0mA
Operating ICC RT = 18 kΩ-8.012.0mA
Zener Voltage VZIZ = 1 mA -15.4- V
Zener Current IZV11-7 = 1 V -0.03- mA
MB3769A
8
Fig. 2 - MB3769A Test Circuit
16 15 14 13 12 11 10 9
12345678
+IN (C) -IN (C) VREF OVP VCC VZVHOUT
+IN (OP) -IN (OP) FB DTC CTRTGND VL
VFB VDTC
MB3769A
COMP
in
1.0 V 15.0 V OUTPUT
10 kΩ
18 kΩ680 pF
TEST INPUT
1000 pF
90%
10%
50%
tf
td
tr
1.05 V
1.0 V
<tr, tf, td>
3.5 V Typ
1.5 V Typ
Voltage at CT
COMP in
OUTPUT
0.95 V
tr of COMP-in should
be within 20 ns.
MB3769A
9
Soft Start Operation Quick Shutdown Operation
3.5 V
1.5 V
1.85V
(15 V)
10 V (Typ)
2.5 V
(1 V)
3 V
8 V
(Typ)
Standby Mode Over Voltage Detector
Latch OFF
Standby
Mode
Over Current
Detector Over Voltage
Detector
0 V
Dead-Time
Input Voltage
Triangle Wave
Form
Error Amp
Output
PWM Comparator
Output
Output Wave
Form
Comp. Current
-in Wave Form
Comp. Current
+in Wave Form
Comp. Current
Latch Output
Voltage at OVP
OVP Latch
Power Supply
Voltage
Fig. 3 - MB3769A Operating Timing
MB3769A
10
■FUNCTIONS
1. Error Amplifier
The error amplifier detects the output voltage of the switching regulator.
The error amplifier uses a high-speed operational amplifier with an 8 MHz bandwidth (typical) and 6 V/µs slew rate (typical).
For ease of use, the common mode input voltage ranges from -0.2 V to VCC-3 V. Figure 4 shows the equivalent circuit.
2. Overcurrent Detection Comparator
There are two methods for protection of the output transistor of this device from overcurrents; one restricts the transistor’s on-
time if an ov ercurrent that flo ws through the output tr ansistor is detected from an a v er age output current, and the other detects
an overcurrent in the external transistor (FET) and shuts the output down instantaneously. Using average output currents, the
peak current of the e xternal transistor (FET) cannot be detected, so an output transistor with a large saf e operation area (SO A)
margin is required.
For the method of detecting overcurrents in the external transistor (FET), the output transistor can be protected against a shorted
filter capacitor or power-on surge current.
The MB3769A uses dynamic current limiting to detect overcurrents in the output transistor (FET). A high-speed comparator
and flip-flop are built-in.
To detect ov ercurrents, compare the v oltage at +IN(C) of current detection resistor connected the source of the output transistor
(FET), with the ref erence voltage (connected to -IN(C)) using a comparator. To prev ent output oscillation during ov ercurrent, flip-
flop circuit protects against double pulses occurring within a cycle.
The output of overcurrent detector is ORed with other signals at the PWM comparator . See the example “■ Application Example”
for details on use.
Figure 5 shows the equivalent circuit of the over-current detection comparator.
Fig. 4 - MB3769A Equivalent Circuit Differential Amp
VCC
GND
-IN (OP)
+IN (OP)
150 Ω
700 µA
VREF
To PWM
Comp.
Protection element
MB3769A
11
3. DTC: Dead Time Contr ol (Soft-Start and Quick Shutdown)
The dead time control terminal and the error amplifier output are connected to the PWM comparator.
The maximum duty cycle for VDTC (voltage applied to pin 4) is obtained from the following for mula (approximate value at low
frequency): Duty Cycle = (3.5 - VDTC) x 50 (%) [0% ≤ duty cycle ≤ DMAX (80%)]
The dead time control terminal is used to provide soft start.
In Figure 6, the DTC terminal is connected to the VREF terminal through R and C. Because capacitor C does not charge
instantaneously when the pow er is turned on, the output transistor is kept turned off. The DTC input voltage and the output pulse
width increase gradually according to the RC time constant so that the control system operates safely.
The quick shutdo wn function pre v ents soft start malfunction when the power is turned off and on quickly. After the power is shut
down, soft star t is disabled because the DTC ter minal has low electric potential from the beginning if the power is tur ned on
again bef ore the capacitor is discharged. The MB3769A prev ents this by turning on the discharge transistor to quickly discharge
the capacitor in the stand-by mode.
Fig. 5 - MB3769A Equivalent Circuit Over Current Detection Comparator
Protection element
+IN (C)
VREF
To PWM
Comp.
-IN (C)
Fig. 6 - MB3769A Soft Start Function
VREF
DTC
C
R
Soft Start
VREF
DTC
CR
1
Soft Start + DTC
R2
MB3769A
12
4. Triangular Wave Oscillator
The oscillation frequency is expressed by the following formula:
F or master/slav e synchronized oper ation of se vera l MB3769As, the CT and R T terminals of the master MB3769A are connected
in the usual way and the CT terminals of the master and slave device (s) are connected together. The slave MB3769A’s RT
ter minal is connected to it’s VREF terminal to disable the slave’s oscillator. In this case, set 50/n kΩ (n is the number of master
and slave ICs) to the upper limit of RT so that internal bias currents do not stop the master oscillation.
5. Overvoltage Detector
The overvoltage detection circuit shuts the system power down if the switching regulator’s output voltage is abnormal or if
abnormal v oltage is appeared. The reference voltage is 2.5 V (VREF /2). The system po w er is shut down if the voltage at pin 13
rises above 2.5 V. The output is kept shut down by the latching circuit until the power supply is turned off (see Figure 3).
6. Stand-by Mode and Under-Voltage Lockout (UVLO)
Generally, VGS > 6 to 8 V is required to use power MOSFET for switching. UVLO is set so that output is on at VCC ≥ 10 V
(standard) when the power is turned on and is off at VCC ≤ 8 V (standard) when the power is turned off.
In the stand-by mode , the pow er supply current is limited to 2 mA or less when the output is inhibited b y the UVLO circuit. When
the MB3769A is operated from the 100 VAC line , the po wer supply current is supplied through resistor R (Figure 8). That is , the
IC power supply current is supplied by the AC line through resistor R until operation star ts. Current is then supplied from the
transformer tertiary winding, eliminating the need for a second power supply.
Two vo lts (typical) of hysteresis are provided for return from operation mode to stand-by mode not to return to stand-by mode
until output power is turned on or to avoid malfunction due to noise.
[kHz]
fOSC ~ :µF
0.8 x CT x R T + 0.0002 ms :kΩ
1CT
RT
Fig. 7 - MB3769A Synchronized Oper ation
master
RT CT
slave
VREF RTCT
MB3769A
13
7. Output Section
Because the OUT terminal (pin 9) carries a large current, the collector and emitter of the output transistor are brought out to the
VH and VL term inals. In principle, VH is connected to VCC and VL is connected to GND, but VH can be supplied from another
pow er supply (4 V to 18 V). Note that VL and GND should be connected as close to the IC package as possible. A capacitor of
0.1 µF or more is inserted between VH and VL (see Figure 9).
Fig. 8 - MB3769A Primary Control
MB3769A
C
R
Fig. 9 - MB3769A Typical Connection Circuit Of Output
10
9
≥ 0.1 µF
12
78
MB3769A
14
■APPLICATION EXAMPLE
Overcurrent Protection Circuit
The wavef orm at the output FET source terminal is shown in Figure 11. The RC time constant must be chosen so that the v oltage
glitch in the waveform does not cause erroneous overcurrent detection. This time constant is should be from 5 ns to 100 ns. A
detection current value depends on R or C because a waveform is weakened. To keep this glitch as small as possible, the
rectifiers on the transformer secondary winding must be the fast-recovery type.
Fig. 10 - MB3769A DC - DC Convertor
MB3769A
+IN (C) 16
IN (C) 15
VREF 14
OVP 13
VCC 12
VZ11
VH10
OUT 9
0.1 µF
20 kΩ
10 kΩ
R
C
100 kΩ
330 pF
3.3 kΩ
220 pF
51 kΩ18 kΩ10 kΩ5.1 kΩ1 Ω
S
5 V
1 A
3.6 kΩ
2.4 kΩ
12 to 18 V
1+IN (OP)
2-IN (OP)
3FB
4DTC
5CT
6RT
7GND
8VL
Fig. 11 - MB3769A Output FET Source Point
Glitch
Point S waveform
MB3769A
15
100 VAC
R
22
kΩ4.7 µF
22
kΩ680
pF 18
kΩ10 kΩ15
kΩ
22
Ω
*
47 kΩ
+IN(OP)
-IN(OP)
FB
DTC
CT
RT
GND
VL
+IN(C)
-IN(C)
VREF
OVP
VCC
VZ
VH
OUT
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
*: The resistance (22 Ω)
as an output current
limiter at pin 9 is
required when driving
the FET which is more
than 1000 pF (CGS).
-
+
Fig. 12 -Primary Control
-
+
43
kΩ
51
kΩ
680
pF
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
+IN(OP)
-IN(OP)
FB
DTC
CT
RT
GND
VL
+IN(C)
-IN(C)
VREF
OVP
VCC
VZ
VH
OUT
Secondly power supply
15 V
0 V
10
kΩ18
kΩ
5.1 kΩ
39
kΩ
27
kΩ
10
kΩ
12 V
1000
pF
Fig. 13 -Secondly Control
MB3769A
16
■SHORT PROTECTION CIRCUIT
The system power can be shut down to protect the output against intermittent short-circuits or continuous
overloads. This protection circuit can be configured using the OVP input as shown in Figure 14.
MB3769A
9
14
13
7
1 µFPC1 100 kΩ
10 kΩ
20 kΩPC2
8
5
34
16
V0
(5V output)
PC2
PC1
OUT-B
500 Ω
HYS-A
500 Ω
MB3761
15 kΩ
IN-B
8.2 kΩ
IN-A
6.8 kΩ
Fig. 14 -Case I. (Over Protection Input)
Primary Mode
MB3769A
14
13 OVP
VREF
MB3761
8
5
36
12
IN-A
IN-B
15 kΩ
8.2 kΩ
6.8 kΩ
OUT-B
HYS-A
200 kΩ
1 µF
20 kΩ
V0 (5V output)
Fig. 15 -Case II. (Over Protection Input)
Secondly Mode
MB3769A
17
■HOW TO SYNCHRONIZE WITH OUTSIDE CLOCK
The MB3769A oscillator circuit is shown in Figure 16. CT charge and discharge currents are e xpressed b y the f ollowing f ormula:
This circuit shows that if the v oltage at the CT terminal is set to 1.5 V or less, one oscillation cycle ends and the ne xt cycle starts.
An example of an external synchronous clock circuit is shown in Figure 17.
5 V
RT
ICT = ±2 x I1 = ±
VREF
2.5 V
RT
-
+
+
-
-
+
S
R
Q
3.5 V
1.5 V
2 x I12 x I1
1 kΩ500
Ω500 Ω
300
Ω150Ω
I1
ICT
CT
(4 x I1)
65
Fig. 16 -Oscillator Circuit
5
6
MB3769A
RTCT
R(5.1 k Ω)VP
ex. MB74HC04
clamp circuit
(VL)
VPtP
tcycle
tcycle = 2.5 µs (fEXT = 400 kHz)
tP= 0.5 µs
RT= 11 k Ω
Fig. 17 -Typical Connection of Synchronized Outside Clock Circuit
tP’
VL
VCT 1.85 V
3.5 V
VTH
( 2.5 V)
.
.
Fig. 18 -Voltage Waveform at CT
The Figure 18 shows the CT terminal waveform.
VTH may be near 2.5 V. In this case, the maximum duty cycle is restricted
as shown in the formula below if tP’ = 0.
Dmax= ≤ 59% (VL = 0 V: No clamp circuit)
(3.5 - 1.85) + (3.5 - VTH)
(3.5 - VL) + (3.5 - VTH)
When VTH = 2.5 V, CT can be provided by followings.
tcycle - tP =x
(3.5 - VL) + (3.5 - VTH)
fOSC(3.5 - 1.5) x 2
fOSC
1
MB3769A
18
Make VL high for a large duty cycle for the clamp circuit. The circ uits below can be used because the clamp voltage must be
much lower than 1.5 V.
In circuit A, R1 and R2 must be determined considering the effects of tP
, R, or RT.
The transistor saturation voltage must be ver y small (<0.15 V) for any clamp circuit, so a transistor with a very small VCE (sat)
should be used.
CT ~ x(t
cycle - tP) [pF] (RT: kΩ, tcycle, tP: ns)
14
0.8 x RT4.5 - VL
fOSC ~ 1
0.8 x CT x RT
0.1 µFR2 (1.2 kΩ)
(1.2 V)
R1 (4.7 kΩ)
VREF
A
(1.2 V)
0.1 µF
820 Ω
VREF
8
5
3
4MB3761
B
Fig. 19 -Clamp Circuit
MB3769A
19
■SYNCHRONIZED OUTSIDE CLOCK CIRCUIT
5 pin
CT
150 pF 5.1 kΩ
VP
MB74HC04
1.No Clamp Circuit (Connect with GND)
CT = 150 pF + Prove Capacitor (~ 15 pF)
RT = 11 kΩ
2.Clamp Circuit A (Dividing Resistor)
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
5 pin
CT
220 pF 5.1 kΩ
MB74HC04
VP
4.7 kΩ
1.2 kΩ
0.1
µF
3.Clamp Circuit B (Apply MB3761)
CT = 220 pF + Prove capacitor (~ 15 pF)
RT = 11 kΩ
5 pin
CT
220 pF 5.1 kΩVP
MB74HC04
0.1 µF
VREF
820 Ω8
5
4
3
VREF
MB3761
VP (5 V/div)
CT (1 V/div)
OUT (10 V/div)
GND Level (CT)
VP (5 V/div)
CT (1 V/div)
GND Level (CT)
OUT (10 V/div)
VP (5 V/div)
CT (1 V/div)
GND Level (CT)
OUT (10 V/div)
Fig. 20
Fig. 21
Fig. 22
10 V
1 V
500 nS
5 V 1 V
500 ns
10 V
5 V
1 V
500 ns
10 V
5 V
1 V
500 ns10 V
5 V
MB3769A
20
1
2.4 kΩ
11 kΩ
MB3769A
2.5 V
OUT
2.4 kΩ
15 V (VCC)
2
3
4
5
6
14
15
16
9
7813
12 10
Fig. 23 -Test Circuit
MB3769A
21
■TYPICAL PERFORMANCE CHARACTERISTICS
(Continued)
10.0
8.0
6.0
4.0
2.0
0.0
0.0 4.0 8.0 12.0 16.0 20.0
Fig. 24 -Power Supply Voltage vs.
Power Supply Current
(Low Voltage stop of VCC)2
1
0-30 + 0 + 25 + 50 + 85
Fig. 25 -Standby Current vs.
Operating Ambient Temperature
OVP
operating
V13 = 5 V
Normal
operating
V13 = 0 V
VCC = 8 V
Power Supply Voltage VCC (V) Operating Ambient Temperature Ta (°C)
Fig. 26 -Reference Voltage Fig. 27 -“L” level Output Voltage vs.
“L” level Output Current
VCC = 15 V
Ta = +25 °C
3
2
1
00.20.40.60.8
“L” level Output Current IOL (mA)
VCC = 15 V
IREF = 1 mA
5.1
5.0
4.9
0-30 0 + 25 + 50 + 85
Operating Ambient Temperature Ta (°C)
5
4
3
2
1
024 68 10
“H” level Output Current IOH (mA)
Fig. 28 -“H” level Output Voltage vs.
“H” level Output Current
Power Supply Current ICC (mA)
Reference Voltage VREF (V)
“H” level Output Voltage VOH (V)
Standby Current ISTB (mA)
“L” level Output Voltage VOL (V)
OVP
operating
±750 µV/C
VCC = 15 V
Ta = +25 °C
MB3769A
22
(Continued)
700
500
400
300
200
100
50
20 710 2030405070
Fig. 29 -Oscillator Frequency vs. RT, CTFig. 30 -“H”, “L” level Output Voltage vs.
Oscillator Frequency
CT = 100 pF
CT = 220 pFCT = 680 pF
CT = 1000 pF
CT = 2200 pF
4
3
2
1
020 k 50 k 100 k 200 k 500 k 1 M
VH
VL
Fig. 31 -Duty Cycle vs. Dead Time Control
Voltage
Fig. 32 -Oscillator Frequency vs.
Operating Ambient Temperature
Fig. 33 -Dead Time Control Voltage vs.
Current(Standby Mode)
-4
-2
0
2
4VCC = 15 V
100 kHz
300 kHz
500 kHz
fOSC = 200 kHz
fOSC = 500 kHz 5.0
4.0
3.0
2.0
VCC = 7 V
Ta = +25 °C
1.0
0-0.2 -0.4 -0.6 -0.8 -1.0 -1.2
100
80
60
40
20
0012345
RT (kΩ), CT (pF)
Frequency fOSC (Hz)
Operating Ambient Temperature Ta (°C)
-30 0 + 25 + 50 + 85
Dead Time Control Voltage VDTC (V) Dead Time Control Current IDTC (mA)
Oscillator Frequency fOSC (kHz)
Dead Time Control Voltage VDTC (V) “H”, “L” level Output Voltage VH, VL (V)
Oscillator Frequency fOSC (%)
Duty Cycle (%)
40
30
60
80
90
70
60
89
VH
VL
VCC = 15 V
Ta = +25 °C
VCC = 15 V
CT = 1000 pF
Ta = +25 °C
Target
fOSC = 100 kHz
±2 % typ
MB3769A
23
(Continued)
Fig. 34 -Gain/Phase vs. Frequency
(Set Gv = 60 dB)
Gain
Phase
60
40
20
0
10 k 100 k 1 M 10 M
-180
-240
-300
-360
fOSC = 500 kHz
fOSC = 200 kHz
VCC = 15 V
CL = 1000 pF
VDTC = 2.5 V
Fig. 35 -Duty vs.
Operating Ambient Temperature
55
50
45
0-30 0 + 25 + 50 + 85
Fig. 36 -“L” level Output Voltage vs.
“L” level Output Current
VCC = 15 V
Ta = +25 °CFig. 38 -tr/tf of Output and td of Comparator
vs. Operating Ambient Temperature
160
140
120
100
80
60
40
20
0-30 0 + 25 + 50 + 85
td
tr
tf
Fig. 37 -“H” level Output Voltage vs.
“H” level Output Current
1.5
1.0
0.5
00100 200 300 400 500 600
14.0
13.5
13.0
12.5
00100 200 300 400 500 600
Frequency f (Hz)
Operating Ambient Temperature Ta (°C)
“L” level Output Current IOL (mA)
“H” level Output Current IOH (mA)
VCC = 15 V
Ta = +25 °C
Operating Ambient Temperature Ta (°C)
Gain (dB)
“L” level Output Voltage VOL (V)
“H” level Output Voltage VOH (V)
Phase (deg)
Duty (%)
tr/tf/td (ns)
VCC = 15 V
Ta = +25 °C
VCC = 15 V
CL = 1000 pF
MB3769A
24
(Continued)
0
+ 20 + 40 + 60 + 100 + 80
6
5
4
3
2
-40 -20 0 + 20 + 40 + 60 + 80 + 100
Fig. 39 -OVP Latch Standby Power Supply Current
vs. Operating Ambient Temperature
VCC = 8 V
4 pin open
13 pin = 3 V
Operating Ambient Temperature Ta (°C)
Fig. 40 -OVP Supply Voltage Reset vs.
Operating Ambient Temperature
-40 -20
Operating Ambient Temperature Ta (°C)
5
4
3
2
1
0
Standby Power Supply Current (mA)
OVP Supply Voltage Reset (V)
0
MB3769A
25
■NOTES ON USE
• Take account of common impedance when designing the earth line on a printed wiring board.
• Take measures against static electricity.
- For semiconductors, use antistatic or conductive containers.
- When storing or carrying a printed circuit board after chip mounting, put it in a conductive bag or container.
- The work table, tools and measuring instruments must be grounded.
- The worker must put on a grounding device containing 250 kΩ to 1 MΩ resistors in series.
• Do not apply a negative voltage
- Applying a negative voltage of −0.3 V or less to an LSI may generate a parasitic transistor, resulting in
malfunction.
■ORDERING INFORMATION
■RoHS Compliance Information of Lead (Pb) Free version
The LSI products of Fujitsu with “E1” are compliant with RoHS Directive , and has observed the standard of
lead, cadmium, mercury, Hexavalent chromium, polybrominated biphenyls (PBB) , and polybrominated diphenyl
ethers (PBDE) .
The product that conforms to this standard is added “E1” at the end of the part number.
■MARKING FORMAT (Lead Free version)
Part number Package Remarks
MB3769APF-❏❏❏ 16-pin plastic SOP
(FPT-16P-M06) Conventional version
MB3769APF-❏❏❏E1 16-pin plastic SOP
(FPT-16P-M06) Lead Free version
INDEX
MB3769A
XXXX XXX
E1
Lead Free version
SOP-16
MB3769A
26
■LABELING SAMPLE (Lead free version)
2006/03/01
ASSEMBLED IN JAPAN
G
QC PASS
(3N) 1MB123456P-789-GE1
1000
(3N)2 1561190005 107210
1,000
PCS
0605 - Z01A
1000
1/1
1561190005
MB123456P - 789 - GE1
MB123456P - 789 - GE1
MB123456P - 789 - GE1
Pb
Lead Free version
Lead free mark
JEITA logo JEDEC logo
MB3769A
27
■MB3769APF-❏❏❏E1
RECOMMENDED
CONDITIONS
OF
MOISTURE SENSITIVITY LEVEL
[Temperature Profile for FJ Standard IR Reflow]
(1) IR (infrared reflow)
(2) Manual soldering (partial heating method)
Conditions : Temperature 400 °C Max
Times : 5 s max/pin
Item Condition
Mounting Method IR (infrared reflow) , Manual soldering (partial heating method)
Mounting times 2 times
Storage period
Before opening Please use it within two years after
Manufacture.
From opening to the 2nd
reflow Less than 8 days
When the storage period after
opening was exceeded Please processes within 8 days
after baking (125 °C, 24H)
Storage conditions 5 °C to 30 °C, 70%RH or less (the lowest possible humidity)
260 °C
(e)
(d')
(d)
255 °C
170 °C
190 °C
RT (b)
(a)
(c)
to
Note : Temperature : the top of the package body
(a) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(b) Preliminary heating : Temperature 170 °C to 190 °C, 60s to 180s
(c) Temperature Increase gradient : Average 1 °C/s to 4 °C/s
(d) Actual heating : Temperature 260 °C Max; 255 °C or more, 10s or less
(d’) : Temperature 230 °C or more, 40s or less
or
Temperature 225 °C or more, 60s or less
or
Temperature 220 °C or more, 80s or less
(e) Cooling : Natural cooling or forced cooling
H rank : 260 °C Max
MB3769A
28
■PACKAGE DIMENSION
16-pin plastic SOP Lead pitch 1.27 mm
Package width
×
package length
5.3× 10.15 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height 2.25 mm MAX
Weight 0.20 g
Code
(Reference) P-SOP16-5.3×10.15-1.27
16-pin plastic SOP
(FPT-16P-M06)
(FPT-16P-M06)
C
2002 FUJITSU LIMITED F16015S-c-4-7
0.13(.005)
M
Details of "A" part
7.80±0.405.30±0.30
(.209±.012) (.307±.016)
–.008
+.010
–0.20
+0.25
10.15
INDEX
1.27(.050)
0.10(.004)
18
916
0.47±0.08
(.019±.003)
–0.04
+0.03
0.17
.007
+.001
–.002
"A" 0.25(.010)
(Stand off)
0~8
˚
(Mounting height)
2.00
+0.25
–0.15
.079
+.010
–.006
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10
+0.10
–0.05
–.002
+.004
.004
.400
*1
*2
0.10(.004)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) *1 : These dimensions include resin protrusion.
Note 2) *2 : These dimensions do not include resin protrusion.
Note 3)Pins width and pins thickness include plating thickness.
Note 4) Pins width do not include tie bar cutting remainder.
MB3769A
F0605
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
of the use or exercise of any intellectual property right, such as
patent right or copyright, or any other right of Fujitsu or any third
party or does Fujitsu warrant non-infringement of any third-party’s
intellectual property right or other right by using such information.
Fujitsu assumes no liability for any infringement of the intellectual
property rights or other rights of third parties which would result
from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
personal injury, severe physical damage or other loss (i.e., nuclear
reaction control in nuclear facility, aircraft flight control, air traffic
control, mass transport control, medical life support system, missile
launch control in weapon system), or (2) for use requiring
extremely high reliability (i.e., submersible repeater and artificial
satellite).
Please note that Fujitsu will not be liable against you and/or any
third party for any claims or damages arising in connection with
above-mentioned uses of the products.
Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
incorporating safety design measures into your facility and
equipment such as redundancy, fire protection, and prevention of
over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
technologies subject to certain restrictions on export under the
Foreign Exchange and Foreign Trade Law of Japan, the prior
authorization by Japanese government will be required for export
of those products from Japan.
Edited Business Promotion Dept.
