A29DL16x Series
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary Simultaneous Operation Flash Memory
PRELIMINARY (September, 2004, Version 0.0) AMIC Technology, Corp.
Document Title
2M X 8 Bit / 1M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No. History Issue Date Remark
0.0 Initial issue September 28, 2004 Preliminary
A29DL16x Series
16 Megabit (2M x 8-Bit/1M x 16-Bit) CMOS 3.0 Volt-only,
Preliminary Simultaneous Operation Flash Memory
PRELIMINARY (September, 2004, Version 0.0) 1 AMIC Technology, Corp.
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Simultaneous Read/Write operatio ns
- Data can be continuously read from one bank while
executing erase/program functions in other bank
- Zero latency between read and write operations
Multiple bank architectures
- Three devices available with different bank sizes (refer to
Table 2)
Package options
- 48-ball TFBGA
- 48-pin TSOP
Top or bottom boot block
Manufactured on 0.18 µm pro c ess technology
- Compatible with A29DL16xC/ A29DL16xD devices
Compatible with JEDEC standards
- Pinout and software compatible with single- power-supply
flash standard
PERFORMANCE CHARACTERISTICS
High performance
- Access time as fast as 70ns
- Program time: 7µs/word typical utilizing Accelerate
function
Ultra low power consumption (typical values)
- 2mA active read current at 1M Hz
- 10mA active read curre nt at 5MHz
- 200nA in standby or automatic sleep mode
Minimum 1 million write cycles guaranteed per sector
20 Year data retention at 125°C
- Reliable operat ion for the life of the system
SOFTWARE FEATURES
Supports Common Flash Memor y Interface (CFI )
Erase Suspend/Erase Resume
- Suspends erase operations to allow programming in
same bank
Data Polling and Toggle Bits
- Provides a software method of detecting the status of
program or erase cycles
Unlock Bypass Program command
- Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
Any combination of sectors can be erased
Ready/Busy output (RY/BY)
- Hardware method for detecting program or erase cycle
completion
Hardware reset pin (RESET)
- Hardware method of resetting the internal s tate machine
to reading array data
WP /ACC input pin
- Write protect ( WP ) function allows protection of two
outermost boot sectors, regardless of sector protect
status
- Acceleration (ACC) function accelerat es program timing
Sector protection
- Hardware method of lock ing a sector, either in-system or
using programming equipment, to prevent any program
or erase operation within that sector
- Temporary Sector Unprotect allows changing data in
protected sectors in-system
Software temporary sector/sector block unprotect command
Software sector protect/unprotect command
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 2 AMIC Technology, Corp.
GENERAL DESCRIPTION
The A29DL16x family consists of 16 megabit, 3.0 volt-only
flash memory devices, organized as 1,048,576 words of 16
bits each or 2,097,152 bytes of 8 bits each. W ord mode data
appears on I/O0–I/O15; byte mode data appears on I/O0–I/O7.
The device is designed to be programmed in-s ystem with the
standard 3.0 volt VCC supply, and can also be programmed
in standard EPROM programmers.
The device is availabl e with an access time of 70, 90, or 120
ns. The devices are offered in 48-pin T SOP and 48-ball Fi ne-
pitch BGA. Standard control pins—chip enable ( CE), write
enable (WE ), and output enable (OE )—control normal read
and write operations, and avo id bus contention issues.
The device requires onl y a sing le 3.0 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
Simultaneous Read/Write Operations with Zero
Latency
The Simultaneous Read/Write architecture provides
simultaneous operation by dividing the memory space into
two banks. The device can improve overall system
performance by allowing a host system to program or erase
in one bank, then immediately and sim ultaneously read from
the other bank, with zero latency. This releases the system
from waiting for the completion of program or erase
operations.
The A29DL16x devices uses multiple bank architectures to
provide flexibilit y for different applications. Three devices ar e
available with these bank sizes:
Device Bank 1 Bank 2
DL162 2 Mb 14 Mb
DL163 4 Mb 12 Mb
DL164 8 Mb 8 Mb
A29DL16x Featu res
The device offers complete compatibility with the JEDEC
single-power-supply Flash command set standard.
Commands are written to the command register using
standard microprocessor write timings. Reading data out of
the device is similar to reading from other Flash or EPROM
devices.
The host system can detect whether a program or erase
operation is complete by using the device status bits:
RY/BY pin, I/O7 (Data Polling) and I/O6/I/O2 (toggle bits).
After a program or erase cycle has been completed, the
device automatically returns to reading array data.
The sector erase architecture allo ws memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The device is fully erased when
shipped from the factory.
Hardware data protection measures include a low VCC
detector that automatically inhibits write operations during
power transitions. The hardware sector protection feature
disables both program and erase operations in any
combination of the sectors of memor y. This can be achiev ed
in-s y s t e m or via programming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system
can also place the device into the standby mode. Power
consumption is greatly reduced in both mo des.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 3 AMIC Technology, Corp.
Pin Configurations
TSOP (I)
A29DL16xV
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A14
A13
A12
A11
A10
A9
A8
NC
WE
RESET
NC
WP/ACC
RY/BY
A18
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33 I/O2
I/O 10
I/O3
I/O 11
VCC
I/O4
I/O 12
I/O5
I/O 13
I/O6
I/O 14
I/O7
I/O 15(A-1)
VSS
BYTE
A16A15
A19
17
18
19
20
21
22
23
24 25
26
27
28
29
30
31
32 I/O9
I/O1
I/O8
I/O0
OE
VSS
CE
A0
A17
A7
A6
A5
A4
A3
A2
A1
TFBGA
A6 B6 C6 D6 E6 F6 G6 H6
TFBGA
Top View, Bal l s Fac ing D own
A5 B5 C5 D5 E5 F5 G5 H5
A4 B4 C4 D4 E4 F4 G4 H4
A3 B3 C3 D3 E3 F3 G3 H3
A2 B2 C2 D2 E2 F2 G2 H2
A1 B1 C1 D1 E1 F1 G1 H1
A13 A12 A14 A15 A16 BYTE I/O15(A-1) VSS
A9 A8 A10 A11 I/O7I/O14 I/O13 I/O6
WE RESET NC A19 I/O5I/O12 VCC I/O4
RY/BY A18 NC I/O2I/O10 I/O11 I/O3
A7 A17 A6 A5 I/O0I/O8I/O9I/O1
A3 A4 A2 A1 A0 CE OE VSS
WP/ACC
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 4 AMIC Technology, Corp.
Block Diagram
A0-A19
A0-A19 A0-A19
STATE
CONTROL
&
COMMAND
REGISTER
I/O0-I/O15
A0-A19
A0-A19
RESET
WE
CE
WP/ACC
RY/BY
Status
Control
BYTE
OE BYTE
Upper Bank Address
Lower Bank Address
I/O0-I/O15
Upper Bank
X-Decoder
Y-Decoder
Latches and Control Logic
Upper Bank
X-Decoder
Y-Decoder
Latches and
Control Logic
I/O0-I/O15 I/O0-I/O15
VCC
VSS
OE BYTE
Pin Descriptions
Pin No. Description
A0 - A19 Address Inputs
I/O0 - I/O14 Data Inputs/Outputs
I/O15 Data Input/Output, Word Mode
I/O15 (A-1) A-1 LSB Address Input, Byte Mode
CE Chip Enable
WE Write Enable
OE Output Enable
WP /ACC Hardware Write Protect/Acceleration Pin
RESET Hardware Reset Pin, Active Low
BYTE Selects 8-b it or 16-bit Mod e
RY/BY Ready/BUSY Output
VSS Ground
VCC 3.0 volt-only single power supply
NC Pin Not Connected Internally
Logic Symbol
A0-A19
CE
OE
WE
RESET
BYTE
RY/BY
I/O0-I/O15(A-1)
20
16 or 8
WP/ACC
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 5 AMIC Technology, Corp.
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. T he command register itself does
not occupy any addressable memor y location. The register is
composed of latches that store the commands, along with
the address and data information needed to execute the
command. The contents of the register serve as inputs to th e
internal state machine. The state machine output s dictate the
function of the device. The appropriate devic e bus operati ons
table lists the inputs and control levels required, and the
resulting output. The following subsections describe each of
these operations in further detail.
Table 1. A29DL16x Device Bus Operations
I/O8 - I/O15 Operation CE OE WE RESET WP/ACC A0 – A19
(Note 1)
I/O0 - I/O7
BYTE =VIH BYTE =VIL
Read L L H H L/H AIN DOUT DOUT I/O8~I/O14=High-Z,
I/O15=A-1
Write L H L H (Note 3) AIN DIN DIN High-Z
Standby VCC ±
0.3 V X X
VCC ±
0.3 V H X High-Z High-Z High-Z
Output Disable L H H H L/H X High-Z High-Z High-Z
Reset X X X L L/H X High-Z High-Z High-Z
Sector Protect
(See Note 2) L H L VID L/H
SA, A6=L,
A1=H, A0=L DIN X X
Sector Unprotect
(See Note 2) L H L VID (Note 3) SA, A6=H,
A1=H, A0=L DIN X X
Temporary Sector
Unprotect X X X VID (Note 3) AIN DIN DIN High-Z
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 8.5 -12.5V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector Address, AIN =
Address In, DIN= Data In, DOUT = Data Out
Notes:
1. Addresses are A19:A0 in word mode (BYTE=VIH), A19: A-1 in byte mode (BYTE=VIL).
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the
“Sector/Sector Block Protection and Unprotection” section.
3. If WP /ACC = VIL, the two outermost boot sectors remain protected. If WP /ACC = VIH, the two outermost boot sector
protection depends on whether they were last protected or unprotected using the method described in “Sector/Sector Block
Protection and Unprotection”. If WP /ACC = VHH all sectors will be unprotected.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 6 AMIC Technology, Corp.
Word/Byte Configuration
The BYTE pin determines whether the I/O pins I/O15-I/O0
operate in the byte or word configuration. If the BYTE pin is
set at logic ”1”, the device is in word configuration, I/O15-I/O0
are active and controlled by CE and OE.
If the BYTE pin is set at logic “0”, the device is in byte
configuration, and only I/O0-I/O7 are active and controlled by
CE and OE . I/O8-I/O14 are tri-stated, and I/O15 pin is used
as an input for the LSB(A-1) address function.
Requirements for Reading Array Data
To read array data from the outputs, the system must drive
the CE and OE pins to VIL. CE is the power control and
selects the device. OE is the output control and gates array
data to the output pins. WE should remain at VIH. The
BYTE pin determines whether the device outputs array data
in words or bytes.
The internal state machine is set for reading array data up on
device power-up, or after a hardware reset. This ensures that
no spurious alteration of the memory content occurs during
the power transition. No command is necessary in this mode
to obtain array data. Standard microprocessor read cycles
that assert valid addresses on the device address inputs
produce valid data on the device data outputs. Each bank
remains enabled for read access until the command register
contents are altered.
See "Requirements for Reading Array Data" for more
information. Refer to the AC Read-Only Operations table for
timing specifications and to Figure 11 for the timing
waveform, lCC1 in the DC Characteristics table repres ents the
active current specification for reading arr ay data.
Writing Commands/Command Sequences
To write a command or command sequence (which includes
programming data to the device and erasing sectors of
memory), the system must drive WE and CE to VIL, and
OE to VIH.
For program operations, the BYTE pin determines whether
the device accepts program data in bytes or words, Refer to
“Word/Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate
faster programming. Once a bank enters the Unlock Bypass
mode, only two write cycles are required to program a word
or byte, instead of four. The “Word / Byte Program Command
Sequence” section has details on programming data to the
device using both standard and Unlock Bypass command
sequence.
An erase operation can erase one sector, multipl e sectors, or
the entire device. The Sector Address Table s 3-4 indicate t he
address range that each sector occupies. The device
address space is divided i nto two banks: Bank 1 contains th e
boot/parameter sectors, and Bank 2 contai ns the larger, code
sectors of uniform size. A “bank address” is the address bits
required to uniquely select a bank. Similarly, a “sector
address” is the address bits required to uniquely select a
sector.
ICC2 in the DC Characteristics table represents the active
current specification for the write mode. The "AC
Characteristics" section contains timing specification tables
and timing diagrams for write operations.
Accelerated Program Operation
The device offers accelerated program operations through
the ACC function. This is one of two functions provided by
the WP /ACC pin. This function is primarily intended to allo w
faster manufacturing throughput at the factory.
If the system asserts VHH on this pin, the device a uto matically
enters the aforementioned Unlo ck Bypass mode, temporarily
unprotects any protected sectors, and uses the higher
voltage on the pin to reduce the time required for program
operations. The system would use a two-cycle program
command sequence as required by the Unlock Bypass
mode. Removing VHH from the WP /ACC pin returns the
device to normal operation. N ote that the WP /ACC pin must
not be at VHH for operations other than accel erated program-
ming, or device damage may result. In addition, the
WP /ACC pin must not be left floating or unconnected;
inconsistent behavior of the device ma y result.
Autoselect Functions
If the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then
read autoselect codes from the internal register (which is
separate from the memory array) on I/O7-I/O0. Standard read
cycle timings apply in this mode. Refer to the Autoselect
Mode and Autoselect Command S equence sections for more
information.
Simultaneous Read/Write Operations with Zero
Latency
This device is capable of reading data from one bank of
memory while programming or erasing in the other bank of
memory. An erase operation may also be suspended to rea d
from or program to another location within the same bank
(except the sector being erased). Figure 18 shows how read
and write cycles may be initiated for simultaneous operation
with zero latency. ICC6 and ICC7 in the DC Characteristics
table represent the current specifications for read-while-pro-
gram and read-while-erase, respectively.
Standby Mode
When the system is not reading or writing to the device, it
can place the device in the standby mode. In this mode,
current consumption is greatly reduced, and the outputs are
placed in the high impedance state, independent of the OE
input.
The device enters the CMOS standb y mode when the CE &
RESET pins are both held at VCC ± 0.3V. (Note that this is a
more restricted voltage range than VIH.) If CEand RESET
are held at VIH, but not within VCC ± 0.3V, the device will be
in the standby mode, but the standby current will be greater.
The device requires the standard access time (tCE) for read
access when the device is i n either of these standby modes,
before it is ready to read data.
If the device is deselected during erasure or programming,
the device draws active current until the operation is
completed.
ICC3 in the DC Characteristics tables represent the standby
current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t ACC +30n s. The automatic
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 7 AMIC Technology, Corp.
sleep mode is independent of the CE,WE and OE control
signals. Standard address access timings provide new data
when addresses are changed. While in sleep mode, output
data is latched and al ways available to the system. ICC4 in the
DC Characteristics table represents the automatic sleep
mode current specification.
RESET : Hardware Reset Pin
The RESET pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET pin low for at least a period of tRP, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the RESET pulse. T he device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another com mand sequence, to ensure data
integrity.
Current is reduced for the duration of the RESET pulse.
When RESET is held at VSS ± 0.3V, the device draws
CMOS standby current (ICC4 ). If RESETis hel d at VIL but not
within VSS ± 0.3V, the standby current will be greater.
The RESET pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If RESET is asserted during a program or erase operation,
the RY/BYpin remains a “0” (busy) until the internal reset
operation is complete, which requires a time tREADY (during
Embedded Algorithms). The system can thus monitor
RY/ BY to determine whether the reset operation is
complete. If RESET is asserted when a program or erase
operation is not executing (RY/ BY pin is “1”), the reset
operation is completed within a time of tREADY (not during
Embedded Algorithms). The system can read data tRH after
the RESET pin return to VIH.
Refer to the AC Characteristics tables for RESET
parameters and diagram.
Output Disable Mode
When the OE input is at VIH, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A29DL16x Device Bank Divisions
Bank 1 Bank 2
Device
Part Number Megabits Sector Sizes Megabits Sector Sizes
A29DL162 2 Mbit Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword 14 Mbit Twenty-eight
64 Kbyte/32 Kword
A29DL163 4 Mbit Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword 12 Mbit Twenty-four
64 Kbyte/32 Kword
A29DL164 8 Mbit Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword 8 Mbit Sixteen
64 Kbyte/32 Kword
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 8 AMIC Technology, Corp.
Table 3 Sector Addresses for Top Boot Sector De vices
A29DL164T
A29DL163T
A29DL162T
Sector Sector Address
A19–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 00000xxx 64/32 000000h-00FFFFh 00000h–07FFFh
SA1 00001xxx 64/32 010000h-01FFFFh 08000h–0FFFFh
SA2 00010xxx 64/32 020000h-02FFFFh 10000h–17FFFh
SA3 00011xxx 64/32 030000h-03FFFFh 18000h–1FFFFh
SA4 00100xxx 64/32 040000h-04FFFFh 20000h–27FFFh
SA5 00101xxx 64/32 050000h-05FFFFh 28000h–2FFFFh
SA6 00110xxx 64/32 060000h-06FFFFh 30000h–37FFFh
SA7 00111xxx 64/32 070000h-07FFFFh 38000h–3FFFFh
SA8 01000xxx 64/32 080000h-08FFFFh 40000h–47FFFh
SA9 01001xxx 64/32 090000h-09FFFFh 48000h–4FFFFh
SA10 01010xxx 64/32 0A00 00h-0AFFFFh 50000h–57FFFh
SA11 01011xxx 64/32 0B0000h-0BFFFFh 58000h–5FFFFh
SA12 01100xxx 64/32 0C0000h-0CFFFFh 60000h–67FFFh
SA13 01101xxx 64/32 0D0000h-0DFFFFh 68000h–6FFFFh
SA14 01110xxx 64/32 0E00 00h-0EFFFFh 70000h–77FFFh
Bank 2
SA15 01111xxx 64/32 0F0000h-0FFFFFh 78000h–7FFFFh
SA16 10000xxx 64/32 100000h-10FFFFh 80000h–87FFFh
SA17 10001xxx 64/32 110000h-11FFFFh 88000h–8FFFFh
SA18 10010xxx 64/32 120000h-12FFFFh 90000h–97FFFh
SA19 10011xxx 64/32 130000h-13FFFFh 98000h–9FFFFh
SA20 10100xxx 64/32 140000h-14FFFFh A0000h–A7FFFh
SA21 10101xxx 64/32 150000h-15FFFFh A8000h–AFFFFh
SA22 10110xxx 64/32 160000h-16FFFFh B0000h–B7FFFh
Bank 2
SA23 10111xxx 64/32 170000h-17FFFFh B8000h–BFFFFh
SA24 11000xxx 64/32 180000h-18FFFFh C0000h–C7FFFh
SA25 11001xxx 64/32 190000h-19FFFFh C8000h–CFFFFh
SA26 11010xxx 64/32 1A00 00h-1AFFFFh D0000h–D7FFFh
Bank 2
SA27 11011xxx 64/32 1B0000h-1BFFFFh D8000h–DFFFFh
SA28 11100xxx 64/32 1C0000h-1CFFFFh E0000h–E7FFFh
SA29 11101xxx 64/32 1D0000h-1DFFFFh E8000h–EFFFFh
SA30 11110xxx 64/32 1E00 00h-1EFFFFh F0000h–F7FFFh
SA31 11111000 8/4 1F0000h-1F1FFFh F8000h–F8FFFh
SA32 11111001 8/4 1F2000h-1F3FFFh F9000h–F9FFFh
SA33 11111010 8/4 1F4000h-1F5FFFh FA000h–FAFFFh
SA34 11111011 8/4 1F6000h-1F7FFFh FB000h–FBFFFh
SA35 11111100 8/4 1F8000h-1F9FFFh FC000h–FCFFFh
SA36 11111101 8/4 1FA000h-1FBFFFh FD000h–FDFFFh
SA37 11111110 8/4 1FC000h-1FDFFFh FE000h–FEFFFh
Bank 1
Bank 1
Bank 1
SA38 11111111 8/4 1FE000h-1FFFFFh FF000h–FFFFFh
Note:
The address range is A19: A-1in byte mode (BYTE=VIL) or A19:A0 in word mode (BYTE=VIH). The bank address bits are A19-
A17 for A29DL162T, A19 and A18 for A29DL163T, and A19 for A29DL16 4T.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 9 AMIC Technology, Corp.
Table 4. Sector Addresses for Bottom Boot Sec tor Devices
A29DL164U
A29DL163U
A29DL162U
Sector Sector Address
A19–A12 Sector Size
(Kbytes/Kwords) (x8)
Address Range (x16)
Address Range
SA0 00000000 8/4 000000h-001FFFh 00000h-00FFFh
SA1 00000001 8/4 002000h-003FFFh 01000h-01FFFh
SA2 00000010 8/4 004000h-005FFFh 02000h-02FFFh
SA3 00000011 8/4 006000h-007FFFh 03000h-03FFFh
SA4 00000100 8/4 008000h-009FFFh 04000h-04FFFh
SA5 00000101 8/4 00A000h-00BFFFh 05000h-05FFFh
SA6 00000110 8/4 00C000h-00DFFFh 06000h-06FFFh
SA7 00000111 8/4 00E000h-00FFFFh 07000h-07FFFh
SA8 00001XXX 64/32 010000h-01FFFFh 08000h-0FFFFh
SA9 00010XXX 64/32 020000h-02FFFFh 10000h-17FFFh
Bank 1
SA10 00011XXX 64/32 030000h-03FFFFh 18000h-1FFFFh
SA11 00100XXX 64/32 040000h-04FFFFh 20000h-27FFFh
SA12 00101XXX 64/32 050000h-05FFFFh 28000h-2FFFFh
SA13 00110XXX 64/32 060000h-06FFFFh 30000h-37FFFh
Bank 1
SA14 00111XXX 64/32 070000h-07FFFFh 38000h-3FFFFh
SA15 01000XXX 64/32 080000h-08FFFFh 40000h-47FFFh
SA16 01001XXX 64/32 090000h-09FFFFh 48000h-4FFFFh
SA17 01010XXX 64/32 0A0000h-0AFFFFh 50000h-57FFFh
SA18 01011XXX 64/32 0B0000h-0BFFFFh 58000h-5FFFFh
SA19 01100XXX 64/32 0C0000h-0CFFFFh 60000h-67FFFh
SA20 01101XXX 64/32 0D0000h-0DFFFFh 68000h-6FFFFh
SA21 01110XXX 64/32 0E0000h-0EFFFFh 70000h-77FFFh
Bank 1
SA22 01111XXX 64/32 0F0000h-0FFFFFh 78000h-7FFFFh
SA23 10000XXX 64/32 100000h-10FFFFh 80000h-87FFFh
SA24 10001XXX 64/32 110000h-11FFFFh 88000h-8FFFFh
SA25 10010XXX 64/32 120000h-12FFFFh 90000h-97FFFh
SA26 10011XXX 64/32 130000h-13FFFFh 98000h-9FFFFh
SA27 10100XXX 64/32 140000h-14FFFFh A0000h-A7FFFh
SA28 10101XXX 64/32 150000h-15FFFFh A8000h-AFFFFh
SA29 10110XXX 64/32 160000h-16FFFFh B0000h-B7FFFh
SA30 10111XXX 64/32 170000h-17FFFFh B8000h-BFFFFh
SA31 11000XXX 64/32 180000h-18FFFFh C0000h-C7FFFh
SA32 11001XXX 64/32 190000h-19FFFFh C8000h-CFFFFh
SA33 11010XXX 64/32 1A0000h-1AFFFFh D0000h-D7FFFh
SA34 11011XXX 64/32 1B0000h-1BFFFFh D8000h-DFFFFh
SA35 11100XXX 64/32 1C0000h-1CFFFFh E0000h-E7FFFh
SA36 11101XXX 64/32 1D0000h-1DFFFFh E8000h-EFFFFh
SA37 11110XXX 64/32 1E0000h-1EFFFFh F0000h-F7FFFh
Bank 2
Bank 2
Bank 2
SA38 11111XXX 64/32 1F0000h-1FFFFFh F8000h-FFFFFh
Note:
The address range is A19: A-1in byte mode (BYTE=VIL) or A19:A0 in word mode (BYTE=VIH). The bank address bits are A19-
A17 for A29DL162U, A19 and A18 for A29DL163U, and A19 for A29DL164U.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 10 AMIC Technology, Corp.
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, and sector protection verification, through
identifier codes output on I/O7 - I/O0. This mode is primarily
intended for programming equipment to automatically match
a device to be programmed with its corresponding
programming algorithm. However, the autoselect codes can
also be accessed in-system throug h the command register.
When using programming equipment, the autoselect mode
requires VID (8.5V to 12.5 V) on address pin A9. Address
pins A6, A1, and A0 must be as shown in Table 5. In
addition, when verifying sector protection, the sector addres s
must appear on the appropriate highest order address bits.
(see Table 3-4). Table 5 shows the remaining address bits
that are don't care. When all necessary bits have been set as
required, the programming equipment may then read the
corresponding identifier code on I/O7 - I/O0.
To access the autoselect codes in-system, the host system
can issue the autoselect command via the command
register, as shown in Table 12. This method does not req uire
VID. Refer to the Autoselect Command Sequence section for
more information.
Table 5. A29DL16x Autoselect Codes (High Voltage Method)
I/O8 to I/O15
Description CE
OE
WE
A19
to
A12
A11
to
A10 A9 A8
to
A7 A6 A5
to
A2 A1 A0 BYT
E
= VIH BYTE
= VIL
I/O7
to
I/O0
Manufacturer ID: AMIC L L H BA X VID X L X L L X X 37h
Device ID: A29DL162 L L H BA X VID X L X L H 22h X 2Dh (T), 2Eh (U)
Device ID: A29DL163 L L H BA X VID X L X L H 22h X 28h (T), 2Bh (U)
Device ID: A29DL164 L L H BA X VID X L X L H 22h X 33h (T), 35h (U)
Continuation ID L L H X X VID X L X H H X X 7Fh
Read Sector Status L L H SA X VID X L X H L X X 01h (protected), 00h
(unprotected)
L=Logic Low= VIL, H=Logic High=VIH, SA=Sector Address, X=Do n’t Care, BA=Bank Address
Note: The autoselect codes may also be accessed in-s ystem via command sequences.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 11 AMIC Technology, Corp.
Sector/Sector Block Protection and Unprotection
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
Table 6. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block A19–A12 Sector / Sector Block Size
SA0 00000XXX 64 Kbytes
SA1-SA3 00001XXX,
00010XXX,
00011XXX 192 (3x64) Kbytes
SA4-SA7 001XXXXX 256 (4x64) Kbytes
SA8-SA11 010XXXXX 256 (4x64) Kbytes
SA12-SA15 011XXXXX 256 (4x64) Kbytes
SA16-SA19 100XXXXX 256 (4x64) Kbytes
SA20-SA23 101XXXXX 256 (4x64) Kbytes
SA24-SA27 110XXXXX 256 (4x64) Kbytes
SA28-SA30 11100XXX,
11101XXX,
11110XXX 192 (3x64) Kbytes
SA31 11111000 8 Kbytes
SA32 11111001 8 Kbytes
SA33 11111010 8 Kbytes
SA34 11111011 8 Kbytes
SA35 11111100 8 Kbytes
SA36 11111101 8 Kbytes
SA37 11111110 8 Kbytes
SA38 11111111 8 Kbytes
Table 7. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection
Sector /
Sector Block A19–A12 Sector / Sector Block Size
SA38 11111XXX 64 Kbytes
SA37-SA35 11110XXX,
11101XXX,
11100XXX 192 (3x64) Kbytes
SA34-SA31 110XXXXX 256 (4x64) Kbytes
SA30-SA27 101XXXXX 256 (4x64) Kbytes
SA26-SA23 100XXXXX 256 (4x64) Kbytes
SA22-SA19 011XXXXX 256 (4x64) Kbytes
SA18-SA15 010XXXXX 256 (4x64) Kbytes
SA14-SA11 001XXXXX 256 (4x64) Kbytes
SA10-SA8 00001XXX,
00010XXX,
00011XXX 192 (3x64) Kbytes
SA7 00000111 8 Kbytes
SA6 00000110 8 Kbytes
SA5 00000101 8 Kbytes
SA4 00000100 8 Kbytes
SA3 00000011 8 Kbytes
SA2 00000010 8 Kbytes
SA1 00000001 8 Kbytes
SA0 00000000 8 Kbytes
The hardware sector protection feature disables both
program and erase operations in any sector. The hardware
sector unprotection feature re-enables both program and
erase operations in previously protected sectors. Sector
protection and unprotection can be implemented via two
methods.
The primary method requires VID on the RESET pin only,
and can be implemented either in-system or via
programming equipment. Figure 2 shows the algorithms and
Figure 23 shows the timing diagram. This method uses
standard microprocessor bus cycle timing. For sector
unprotect, all unprotected sectors must first be protected
prior to the first sector unprotect write cycle.
The sector unprotect algorithm unprotects all sectors in
parallel. All previously protected sectors must be individually
re-protected. To change data in protected sectors efficiently,
the temporary sector unprotect function is available. See
“Temporary Sector/Sector Block Unprotect”.
The alternate method for protection and unprotection is by
software sector /sector block protect unprotect command.
See Figure 2 for Command Flo w.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See the Autoselect Mode section for details.
Write Protect (WP)
The Write Protect function provides a hardware method of
protecting certain boot sectors without using VID. This
function is one of two provided by the WP /ACC pi n.
If the system asserts VIL on the WP /ACC pin, the device
disables program and erase functions in the two “outermost”
8 Kbyte boot sectors independent ly of whether those sectors
were protected or unprotected using the met hod described in
“Sector/Sector Block Protection and Unprotection”. The two
outermost 8 Kbyte boot sectors are the two sectors
containing the lowest addresses in a bottom-boot-configured
device, or the two sectors containing the highest addresses
in a top-boot-configured devic e.
If the system asserts VIH on the WP /ACC pin, the device
reverts to whether the two outermost 8 Kbyte boot sectors
were last set to be protected or unprotected. That is, sector
protection or unprotection for these two sectors depends on
whether they were last protected or unprotected using the
method described in “Sector/Sector Block Protection and
Unprotection”.
Note that the WP /ACC pin must not be left floating or
unconnected; inconsistent be havior of the device may result.
Temporary Sector/Sector Block Unprotect
(Note: For the following discussion, the term “sector” applies
to both sectors and sector blocks. A sector block consists of
two or more adjacent sectors that are protected or
unprotected at the same time (see Tables 6 and 7).
This feature allows temporary unprotection of previously
protected sectors to change data in-system. The Sector
Unprotect mode is activated by setting the RESET pin to VID
(8.5V-12.5V). During this mode, formerly protected sectors
can be programmed or erased by selecting the sector
addresses. Once VID is removed from the RESET pin, all the
previously protected sectors are protected again. Figure 1
shows the algorithm, and Figure 22 shows the timing
diagrams, for this feature.
A29DL16x Series
PRELIMINARY (September, 2004, Version 0.0) 12 AMIC Technology, Corp.
START
RESET = VID
(Note 1)
Perform Erase or
Program Operations
RESET = VIH
Temporary Sector
Unprotect
Comple ted (Note 2)
Notes:
1. All protect ed sectors unprotected (If WP/ACC=V IL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
Figure 1-1. Temporary Sector Unprotect Operation by RESET Mode
Figure 1-2. Temporary Sector Unprotect Operation by Software Mode
START
555/AA + 2AA/55 + 555/77
(Note 1 )
Perform Erase or
Program Opera tions
XXX/F0
(Reset Co m m a nd )
Soft-ware Temporary
Sector Un pro tect
Completed
(Note 2 )
Notes:
1. All protected sectors unprotected (If WP/ACC=VIL,
outermost boot sectors will remain protected).
2. All previously protected sectors are protected once again.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 13 AMIC Technology, Corp.
START
PLSCNT=1
RESET=VID
Wait 1 us
First Writ e
Cycle=60h?
Set up sector
address
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Read from
sector address
with A6=0,
A1=1, A0=0
Data=01h?
Protect another
sector?
Remove VID
from RESET
Write reset
command
Sector Protect
complete
Sector Protect
Algorithm
Temporary Sector
Unprotect Mode
Increment
PLSCNT
PLSCNT
=25?
Device fail e d
No
No
No
Yes
Reset
PLSCNT=1
Yes
Yes
No
Protect all sectors:
The indi cated porti on of
the secto r prot ec t
algorithm must be
performed fo r al l
unprotected sectors prior
to issuing the first sector
unprotect ad dress
START
PLSCNT=1
Wait 1 us
First Wri te
Cycle=60h? No Temporary Sector
Unprotect Mode
Yes
No
All sectors
protected?
Set up first sector
address
Sector Unprotect:
Write 60h to sector
address wit h A6=1,
A1=1, A0=0
Wait 15 ms
Verify Sector
Unprotect : Write
40h to sector
address wit h A6=1,
A1=1, A0=0
Read from sector
address wit h A6=1,
A1=1, A0=0
Data=00h?
Last sector
verified?
Remove VID
from RESET
Write reset
Command
Sector Unprotect
complete
Yes
Yes
Set up
next sector
address
No
Yes
Yes
Sector Unprotect
Algorithm
Increment
PLSCNT
PLSCNT=
1000?
Device failed
Yes
No
No
Figure 2-1. High Voltage Sector/Sector Block Protection and Unprotection Al gorithms
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
RESET=VID
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 14 AMIC Technology, Corp.
START
PLSCNT=1
555/AA + 2A A/ 5 5 +
555/77
Wait 1 us
First Writ e
Cycle=60h?
Set up sector
address
Sector Protect:
Write 60h to sector
address with A6=0,
A1=1, A0=0
Wait 150 us
Verify Sector
Protect: Write 40h
to sector address
with A6=0, A1=1,
A0=0
Read from
sector address
with A6=0,
A1=1, A0=0
Data=01h?
Protect another
sector?
Write reset
command
Sector Protect
complete
Sector Protect
Algorithm
Temporary Sector
Unprotect Mode
Increment
PLSCNT
PLSCNT
=25?
Device fail e d
No
No
No
Yes
Reset
PLSCNT=1
Yes
Yes
No
Protect all sectors:
The indi cated porti on of
the secto r prot ec t
algorithm must be
performed fo r al l
unprotected sectors prior
to issuing the firs t sector
unprotect ad dress
START
PLSCNT=1
Wait 1 us
First Wri te
Cycle=60h? No Temporary Sector
Unprotect Mode
Yes
No
All sectors
protected?
Set up fi rst sector
address
Sector Unprotect:
Write 60h to sector
address with A6=1,
A1=1, A0=0
Wait 15 m s
Verify Sector
Unprotect : Write
40h to sector
address with A6=1,
A1=1, A0=0
Read from sector
address with A6=1,
A1=1, A0=0
Data=00h?
Last sector
verified?
Write reset
Command
Sector Unprotect
complete
Yes
Yes
Set up
next sector
address
No
Yes
Yes
Sector Unprotect
Algorithm
Increment
PLSCNT
PLSCNT=
1000?
Device failed
Yes
No
No
Figure 2-2. Software Sector/Sector Block Protection and Unprotection Al go rithms
Note: The term “sector” in the figure applies to both sectors and sector blocks
* No other command is allowed during this process
555/AA + 2AA/55 +
555/77
A29DL16x Series
PRELIMINARY (September, 2004, Version 0.0) 15 AMIC Technology, Corp.
Hardware Data Protection
The command sequence requirement of unlock cycles for
programming or erasing provides data protection against
inadvertent writes (refer to Table 12 for command d efinitions).
In addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spur ious system level signals during
VCC power-up and power-down transitions, or from system
noise.
Low VCC Write Inhibit
When VCC is less than VLKO, the device does not accept any
write cycles. This protects data during VCC power-up and
power-down. The command register and all internal
program/erase circuits are disabled, an d the device resets to
reading array data. Subsequent writes are ignored until V CC
is greater than VLKO. The system must provide the proper
signals to the control pins to prevent unintentional writes
when VCC is greater than VLKO.
Write Pulse “Glitch” Protection
Noise pulses of less than 5ns (typical) on OE , CE or WE
do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL,
CE = VIH or WE = VIH. To initiate a write cycle, CE and
WE must be a logical zero while OE is a logical one.
Power-Up Write Inhibit
If WE = CE = VIL and OE = VIH during power up, the
device does not accept commands on the rising edge of WE .
The internal state machine is automatically reset to reading
array data on power-up.
COMMON FLASH MEMORY INTERFACE (CFI)
The Common Flash Interface (CFI) specification outlines
device and host system software interrogation handshake,
which allows specific vendor-specified soft ware algorithms to
be used for entire families of devices. Software support can
then be device-independent, JEDEC ID-independent, and
forward- and backward-compatible for the specified flash
device families. Flash vendors can standardize their existing
interfaces for long-term compatibility.
This device enters the CFI Query mode when the system
writes the CFI Query command, 98h, to address 55h in word
mode (or address AAh in byte mode), any time the device is
ready to read array data. The system can read CFI
information at the addresses given in Tables 8-11. To
terminate reading CFI data, the system must write the reset
command.
The system can also write the CFI quer y command when the
device is in the autoselect mode. The device enters the CFI
query mode, and the system can read CFI data at the
addresses given in Tables 8-11. The system must write the
reset command to return the device to the autoselect mode.
Table 8. CFI Query Identification String
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
10h
11h
12h
20h
22h
24h
0051h
0052h
0059h Query Unique ASCII string “QRY”
13h
14h 26h
28h 0002h
0000h Primary OEM Command Set
15h
16h 2Ah
2Ch 0040h
0000h Address for Primary Extended Table
17h
18h 2Eh
30h 0000h
0000h Alternate OEM Command Set (00h = none exists)
19h
1Ah 32h
34h 0000h
0000h Address for Alternate OEM Extended Table (00h = none exists)
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 16 AMIC Technology, Corp.
Table 9. System Interface String
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
1Bh 36h 0027h VCC Min. (write/erase)
I/O7- I/O4 : volt, I/O3- I/O0: 100 mil livolt
1Ch 38h 0036h VCC Max. (write/erase)
I/O7- I/O4: volt, I/O3- I/O0: 100 millivolt
1Dh 3Ah 0000h Vpp Min. voltage (00h = no Vpp pin present)
1Eh 3Ch 0000h Vpp Max. voltage (00h = no Vpp pin present)
1Fh 3Eh 0004h
Typical timeout per single b yte/word write 2N µs
20h 40h 0000h
Typical timeout for Min. size buffer write 2N µs (00h = not supported)
21h 42h 000Ah Typical timeout per ind ividual block erase 2N ms
22h 44h 0000h Typical timeout for full chip erase 2N ms (00h = not supporte d)
23h 46h 0005h Max. timeout for byte/word write 2N times typical
24h 48h 0000h Max. timeout for buffer write 2N times typical
25h 4Ah 0004h Max. timeout per individual block erase 2N times typical
26h 4Ch 0000h Max. timeout for full chip erase 2N times typical (00h = not supported)
Table 10 Device Geometry Definition
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
27h 4Eh 0015h
Device Size = 2N byte
28h
29h 50h
52h 0002h
0000h Flash Device Interface description
2Ah
2Bh 54h
56h 0000h
0000h
Max. number of byte in multi-byte write = 2N
(00h = not supported)
2Ch 58h 0002h
Number of Erase Block Regions within devic e
2Dh
2Eh
2Fh
30h
5Ah
5Ch
5Eh
60h
0007h
0000h
0020h
0000h
Erase Block Region 1 Information
(refer to the CFI specification)
31h
32h
33h
34h
62h
64h
66h
68h
001Eh
0000h
0000h
0001h
Erase Block Region 2 Information
35h
36h
37h
38h
6Ah
6Ch
6Eh
40h
0000h
0000h
0000h
0000h
Erase Block Region 3 Information
39h
3Ah
3BH
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase Block Region 4 Information
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 17 AMIC Technology, Corp.
Table 11. Primary Vendor-Specific Extended Query
Addresses
(Word Mode)
Addresses
(Byte Mode) Data Description
40h
41h
42h
80h
82h
84h
0050h
0052h
0049h
Query-unique ASCII string “PRI”
43h 86h 0031h Major version number, ASCII
44h 88h 0032h Minor version number, ASCII
45h 8Ah 0000h Address Sensitive Unlock
0 = Required, 1 = Not Required
46h 8Ch 0002h Erase Suspend
0 = Not Supported, 1 = To Read Only, 2 = To Read & Write
47h 8Eh 0001h Sector Protect
0 = Not Supported, X = Number of sectors in per group
48h 90h 0001h Sector Temporary Unprotect
00 = Not Supported, 01 = Supported
49h 92h 0004h Sector Protect/Unprotect scheme
04 = A29L800 mode
4Ah 94h 00XXh
(See Note) Simultaneous Operation
00 = Not Supported, 01 = Supported
48h 96h 0000h Burst Mode Type
00 = Not Supported, 01 = Supported
4Ch 98h 0000h Page Mode Type
00 = Not Supported, 01 = 4 Word Page, 02 = 8 W ord Page
4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum 00 h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Eh 9Ch 0095h ACC (Acceleration) Supply Maximum 00h = Not Supported, D7-D4: Volt,
D3-D0: 100 mV
4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag 02h = Bottom Boot Device, 03h = Top Boot
Device
Note:
The number of sectors in Bank 2 is device dependent.
A29DL162 = 1Ch
A29DL163 = 18h
A29DL164 = 10h
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 18 AMIC Technology, Corp.
COMMAND DEFINITIONS
Writing specific address and data commands or sequences
into the command register initiates device operations. Table
12 defines the valid register command sequences. Writing
incorrect address and data values or writing them in the
improper sequence may place the device in an unknown
state. A reset command is then required to return the device
to reading array data.
All addresses are latched on the falling edge of WE or CE,
whichever happens later. All data is latched on the rising
edge of WE or CE, whichever happens first. Refer to the
AC Characteristics section for timing diagrams.
Reading Array Data
The device is automatically set to reading array data after
device power-up. No commands are required to retrieve
data. The device is also ready to read array data after
completing an Embedded Program or Embedded Erase
algorithm.
After the device accepts an Erase Suspend command, the
corresponding bank enters the erase-suspend-read mode,
after which the system can read data from any non-erase-
suspended sector within the same bank. After completing a
programming operation in the Erase Suspend mode, the
system may once again read array data with the same
exception. See the Erase Suspend/Erase Resume
Commands section for more information.
The system must issue the reset command to return a bank
to the read (or erase-suspend-read) mode if I/O5 goes high
during an active progr am or erase operation, or if the bank is
in the autoselect mode. See the next section, Reset
Command, for more information.
See also Requirements for Reading Array Data in the Device
Bus Operations section for more information. The Read-Onl y
Operations table provides the read parameters, and Figure
11 shows the timing diagram.
Reset Command
Writing the reset command resets the banks to the read or
erase-suspend-read mode. Address bits are don’t cares for
this command.
The reset command may be written between the sequence
cycles in an erase command sequence before erasing
begins. This resets the bank to which the system was writing
to reading array data. Once erasure begins, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the sequence
cycles in a program command sequence before
programming begins. This resets the bank to which the
system was writing to reading array data. If the program
command sequence is written to a bank that is in the Erase
Suspend mode, writing the reset command returns that ba nk
to the erase-suspend-read mode. Once pro gr amming beg ins ,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the sequence
cycles in an autoselect command sequence. Once in the
autoselect mode, the reset command must be written to
return to reading array data. If a bank entered the autoselect
mode while in the Erase Suspend mode, writing the reset
command returns that bank to the erase-suspend-read mode.
If I/O5 goes high during a program or erase operation, writing
the reset command returns the banks to reading array data
(or erase-suspend-read mode if that bank was in Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host system
to access the manufacturer and device code s, and determine
whether or not a sector is protected. Table 12 shows the
address and data requirements. This method is an
alternative to that shown in Table 5, which is intended for
PROM programmers and requires VID on address pin A9.
The autoselect command sequence may be written to an
address wit h in a bank that is either in t he read or erase-
suspend-read mode. The autoselect command may not be
written while the device is actively programming or erasing in
the other bank.
The autoselect command sequence is initiated by first writing
two unlock cycles. This is followed by a third write cycle that
contains the bank address and the autoselect command. T he
bank then enter s the autoselect mode. T he system may read
at any address within the same bank any number of times
without initiating another autoselect command sequ ence:
A read c ycle at address (BA)XX00h (where BA is the bank
address) returns the manufacturer code.
A read cycle at address (BA)XX01h in word mode (or
(BA)XX02h in byte mode) returns the device code.
A read cycle to an address containing a sector address
(SA) within the same bank, and the address 02h on A7-A0
in word mode (or the address 04h on A 6-A-1 in b yte mode)
returns 01h if the sector is protected, or 00h if it is
unprotected. (Refer to Tables 3-4 for valid sector
addresses).
The system must write the reset command to return to
reading array data (or erase-suspend-read mode if the bank
was previously in Erase Suspend).
Byte/Word Program Command Seque nce
The system may program the device by word or byte,
depending on the state of the BYTE pin. Programming is a
four-bus-cycle operation. The program command sequence
is initiated by writing t wo unlock write cycles, follo wed by the
program set-up command. The program address and data
are written next, which in turn initiate the Embedded Program
algorithm. The system is not required to provide further
controls or timings. The device automatically provides
internally generated program pulses and verifies the
programmed cell margin. Table 12 shows the address and
data requirements for the byte program command sequence.
When the Embedded Program algorithm is complete, that
bank then returns to reading array data and addresses are
no longer latched. The system can determine the status of
the program operation by using I/O7, I/O6, or RY/ BY. Refer
to the Write Operation Status section for information on these
status bits.
Any commands written to the device during the Embedded
Program Algorithm are ignored. Note that a hardware reset
immediately terminates the program operation. The program
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across sector
boundaries. A bit cannot be programmed from “0” back to a
“1.” Attempting to do so may cause that bank to set I/O5 = 1,
or cause the I/O7 and I/O6 status bits to indicate the operation
was successful. However, a succeeding read will show that
the data is still “0.” Only eras e operations can conv ert a “0” to
a “1.”
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 19 AMIC Technology, Corp.
START
Write Program
Command
Sequence
Data Poll
from System
Verify Data ?
Last Address ?
Programming
Completed
No
Yes
Yes
Increment Address
Embedded
Program
algorithm in
progress
Note : See Table 14 for program command sequnce.
Figure 3. Program Operation
No
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to program
bytes or words to a bank faster than using the standard
program command sequence. The unlock bypass command
sequence is initiated by first writing two unloc k cycles. This is
followed by a third write cycle containing the unlock bypass
command, 20h. The device then enters the unlock bypass
mode. A two-cycle unlock bypass program command
sequence is all that is require d to program in this mode. The
first cycle in this sequence contains the unlock bypass pro-
gram command, A0h; the second cycle contains the pr ogram
address and data. Additional data is programmed in the
same manner. This mode dispenses with the initial two
unlock cycles required in the standard program command
sequence, resulting in faster total programming time. Table
12 shows the requirements for the command sequence.
During the unlock bypass mode, only the Unlock Bypass
Program and Unlock Bypass Reset commands are valid. To
exit the unlock bypass mode, the system must issue the two-
cycle unlock bypass reset command sequence. The device
then returns to reading array data.
The device offers accelerated program operations through
the WP /ACC pin. When the system asserts VHH on the
WP /ACC pin, the device automatically enters the Unlock
Bypass mode. The system may then write the two-cycle
Unlock Bypass program command sequence. The device
uses the higher voltage on the WP /ACC pin to accelerate
the operation. Note that the WP /ACC pin must not be at V HH
any operation other tha n acce lerated pro gramming, or dev ice
damage may result. In addition, the WP /ACC pin must not
be left floating or unconnected; inconsistent behavior of the
device may result.
Figure 3 illustrates the algorithm for the program operation.
Refer to the Erase and Program Operations table in the AC
Characteristics section for parameters, and Figure 15 for
timing diagrams.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 20 AMIC Technology, Corp.
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. Two additional unlock write
cycles are then followed by the chip erase command, which
in turn invokes the Embedded Erase algorithm. The device
does not require the system to preprogram prior to erase.
The Embedded Erase algorithm automatically preprograms
and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provi de
any controls or timings during these operations. Table 12
shows the address and data requirements f or the chip erase
command sequence.
When the Embedded Erase algorithm is complete, that bank
returns to reading array data and addresses are no longer
latched. The system can determine the status of the erase
operation by using I/O7, I/O6, I/O2, or RY/BY. Refer to the
Write Operation Status section for information on these
status bits.
Any commands written during the chip erase operation are
ignored. However, note that a hardware reset immediately
terminates the erase operation. If that occurs, the chip era se
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operati ons tables in the AC
Characteristics section for par ameters, and Figure 17 section
for timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector erase
command sequence is initiated by writing two unlock cycles,
followed by a set-up command. T wo additional unlock cycles
are written, and are then followed by the address of the
sector to be erased, and the sector erase command. Table
12 shows the address and data requirements for the sector
erase command sequence.
The device does not require the system to preprogram prior
to erase. The Embedded Erase algorithm automatically
programs and verifies the entire memory for an all zero data
pattern prior to electrical erase. T he system is not required to
provide any controls or timings during these operations.
After the command sequence is written, a sector erase time-
out of 50 µs occurs. During the time-out period, additional
sector addresses and sector erase commands within the
bank may be written. Loading the sector erase buffer may be
done in any sequence, and the number of sectors may be
from one sector to all sectors. The time between these
additional cycles must be less than 50µs, otherwise erasure
may begin. Any sector erase address and command
following the exceeded time-out may or may not be accepted.
It is recommended that processor interrupts be disabled
during this time to ensure all commands are accepted. The
interrupts can be re-enabled after the last Sector Erase
command is written. Any command other than Sector Erase
or Erase Suspend during the time-out period resets that bank
to reading array data. The system must rewrite the command
sequence and any additio nal addresses and commands.
The system can monitor I/O3 to determine if the sector erase
timer has timed out (See the section on I/O3: Sector Erase
Timer.). The time-out begins from the rising edge of the final
WE pulse in the command sequence.
When the Embedded Erase algorithm is complete, the bank
returns to reading array data and addresses are no longer
latched. Note that while the Embedded Erase operation is in
progress, the system can read data from the non-erasing
bank. The system can determine the status of the erase
operation by reading I/O7, I /O6, I/O2, or RY/BY in the erasing
bank.
Refer to the Write Operation Status section for information on
these status bits.
Once the sector erase operation has begun, only the Erase
Suspend command is valid. All other commands are ignor ed.
However, note that a hardware reset immediately terminates
the erase operation. If that occurs, the sector erase
command sequence should be reinitiated once that bank has
returned to reading array data, to ensure data integrity.
Figure 4 illustrates the algorithm for the erase operation.
Refer to the Erase and Program Operati ons tables in the AC
Characteristics section for par ameters, and Figure 17 section
for timing diagrams
Erase Suspend/Erase Resume Commands
The Erase Suspend command, B0h, allows the system to
interrupt a sector erase operation and then read data from, or
program data to, any sector not selected for erasure. This
command is valid only during the sector erase operation,
including the 50 µs time-out period during the sector erase
command sequence. The Erase Suspend command is
ignored if written during the chip erase operation or
Embedded Program algorithm.
When the Erase Suspend command is written during the
sector erase operation, the d evice requires a ma ximum of 20
µs to suspend the erase operation. However, when the Erase
Suspend command is written during the sector erase time-
out, the device immediately terminates the time-out period
and suspends the erase operation.
After the erase operation has been suspended, the bank
enters the erase-suspend-read mode. The system can read
data from or program data to any sector not selected for
erasure. (The device “erase suspends” all sectors selected
for erasure.) Reading at any addr ess within erase-sus pend ed
sectors produces status information on I/O7–I/O0. The system
can use I/O7, or I/O6 and I/O2 together, to determine if a
sector is actively erasing or is erase-suspended. Refer to t he
Write Operation Status section for information on these
status bits.
After an erase-suspended program operation is complete,
the bank returns to the erase-suspend-read mode. The
system can determine the status of the program operation
using the I/O7 or I/O6 status bits, just as in the standard Byt e
Program operation. Refer to the Write Operation Status
section for more information.
In the erase-suspend-read mode, the system can also issue
the autoselect command sequence. Refer to the Autoselect
Mode and Autoselect Command Sequence sections for
details.
To resume the sector erase o peration, the system must write
the Erase Resume command. The bank address of the
erase-suspended bank is igno red when writing this command.
Further writes of the Resume command are ignored. Anot her
Erase Suspend command can be written after the chip has
resumed erasing.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 21 AMIC Technology, Corp.
START
Write Erase
Command Sequence
(Notes 1,2)
Data Poll to Erasing
Bank from System
Data = FFh ?
Erasure Completed
Yes
Embedded
Erase
algorithm in
progress
Note :
1. See Table 14 for erase command sequence.
2. See the section on I/O3 for information on the sector
erase timer.
No
Figure 4. Erase Operation
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 22 AMIC Technology, Corp.
Command Definitions Table 12. A29DL16x Command Definitions
Bus Cycles (Notes 2–5)
First Second Third Fourth Fifth Sixth
Command
Sequence
(Note 1)
Cycle
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 6) 1 RA RD
Reset (Note 7) 1 XXX F0
Word 555 2AA (BA)555
Manufacturer ID Byte 4 AAA AA 555 55 (BA)AAA 90 (BA)X00 37
Word 555 2AA (BA)555 (BA)X01
Device ID Byte 4 AAA AA 555 55 (BA)AAA 90 (BA)X02 (see
Table5)
Word 555 2AA 555 X03
Continuation ID Byte 4 AAA AA 555 55 AAA 90 X06 7F
Word 555 2AA (BA)555 (SA)
Autoselect
(
Note 8
)
Sector Protect Verify
(Note 9) Byte 4 AAA AA 555 55 (BA)AAA 90 (SA)X04 00/01
Word 555 2AA 555
Command Temporary
Sector Unprotect (Note15) Byte 3 AAA AA 555 55 AAA 77
Word 555 2AA 555
Program Byte 4 AAA AA 555 55 AAA A0 PA PD
Word 555 2AA 555
Unlock Bypass Byte 3 AAA AA 555 55 AAA 20
Unlock Bypass Program (Note 10) 2 XXX A0 PA PD
Unlock Bypass Reset (Note 11) 2 XXX 90 XXX 00
Word 555 2AA 555 555 2AA 555
Chip Erase Byte 6 AAA AA 555 55 AAA 80 AA A AA 555 55 AAA 10
Word 555 2AA 55 555 80 555 2AA
Sector Erase Byte 6 AAA AA 555 AAA AAA
AA 555 55 SA 30
Erase Suspend (Note 12) 1 XXX B0
Erase Resume (Note 13) 1 XXX 30
Word 55
CFI Query (Note 14) Byte 1 AA 98
Legend:
X = Don't care
RA = Address of the memory location to be read.
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. Addresses latch on the falling edge of the WE or CE pulse,
whichever happens later.
PD = Data to be programmed a t loca tion PA. Data latches on the rising edge of WE or CE pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or erased. Address bits A19 - A12 select a unique sector.
BA = Address of the bank that is being switched to autoselect mode, is in bypass mode, or is being erased.
Note:
1. See Table 1 fo r description of bus operations.
2. All values are in hexadecimal.
3. Except for the read cycle and the fourth cycle of the autoselec t command sequence, all bus cycles are write cycles.
4. Data bits I/O15-I/O8 are don’t care in command sequences. Except for RD and PD.
5. Unless otherwise noted, address bits A19-A11 are don’t cares.
6. No unlock or command cycles required when bank is reading array data.
7. The Reset command is required to return to reading array data (or to the erase-suspend-read mode if previously in Erase
Suspend) when a bank is in the autoselect mode, or if I/O5 goes high ( while the bank is providing status information).
8. The fourth cycle of the autoselect command sequence is a read cycle. T he system must provide the bank address to obtai n
the manufacture ID, or device ID information. Data bits I/O15-I/O8 are don’t care. See the Autoselect Command Sequence
section for more information.
9. The data is 00h for an un protected sector/sector block and 01h for a protected sector/sector block.
10. The Unlock B ypass command is required prior to the Unlock Bypass Program Command.
11. The Unlock Bypass Res et command is req uired to return to reading array data when the bank is in the unlock bypass mode.
12. The sy stem may read and p rogram in non -e rasing secto rs, or enter the autoselect mode , w hen in the Era se Suspend mode.
The Erase Suspend command i s valid only during a se ctor era se opera tion, and requi re the ban k address.
13. The Erase Resume command is valid only during the Erase.
14. Command is valid when device is read y to read array data or when device is in autosel ect mode.
15. Once a reset command is applied, software temporary unprotect is exit to return to read array data. But under erase
suspend condition, this command is still effe ctive even a reset command has been applied. The reset command which can
deactivate the software temporary unprotect command is useful only after the erase command is complete.
A29DL16x Series
PRELIMINARY (September, 2004, Version 0.0) 23 AMIC Technology, Corp.
WRITE OPERATION STATUS
The device provides sev eral bits to determine the status of a
program or erase operation: I/O2, I/O3, I/O5, I/O6, and I/O7.
Table 13 and the follo wing subsections descr ibe the function
of these bits. I/O7 and I/O6 each offer a method for
determining whether a program or erase operation is
complete or in progress. The device also provides a
hardware-based output signal, RY/BY, to determine whether
an Embedded Program or Erase operation is in progress or
has been completed.
I/O7: Data Polling
The Data Polling bit, I/O7, indicates to the host system
whether an Embedded Algorithm is in progre ss or completed,
or whether the device is in Erase Suspend. Data Polling is
valid after the rising edge of the final WE pulse in the
program or erase command sequence.
During the Embedded Program algorithm, the device out puts
on I/O7 the complement of the datum programmed to I/O7.
This I/O7 status also applies to programming during Erase
Suspend. When the Embedded Program algorithm is
complete, the device outputs the datum programmed to I/O7.
The system must provide the program address to read valid
status information on I/O7. If a program address falls within a
protected sector, Data Polling on I/O7 is active for
approximately 1µs, then the device returns to reading array
data.
During the Embedded Erase algorithm, Data Pollin g
produces a "0" on I/O7. When the Embe dded Erase al gorit h m
is complete, or if the device enters the Eras e Suspend mo de,
Data Polling produces a "1" on I/O7. The system must
provide an address within any of the sectors selected for
erasure to read valid status information on I/O7.
After an erase command sequence is written, if all sectors
selected for erasing are protected, Data Polling on I/O7 is
active for approximately 100µs, then the bank returns to
reading array data. If not all selected sectors are protected,
the Embedded Erase algorithm erases the unprotected
sectors, and ignores the selected sectors that are protected.
However, if the system reads I/O7 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program or
Erase operation, I/O7 may change as ynchronously with I/O0–
I/O6 while Output Enable (OE) is asserted low. That is, the
device may change from prov iding status information to valid
data on I/O7. Depending on when the system samples the
I/O7 output, it may read the status or valid data. Even if the
device has completed the program or erase operation and
I/O7 has valid data, the data outputs on I/O0-I/O6 may be still
invalid. Valid data on I/O0-I/O7 will appear on successive read
cycles.
Table 13 shows the outputs for Data Polling on I/O7. Figure
5 shows the Data Polling algorithm. Figure 19 in the AC
Characteristics section shows the Data Polling timing
diagram.
START
Read I/O
7
-I/O
0
Address = VA
I/O
7
= Data ?
FAIL
No
Note :
1. VA = Valid address for programming. During a sector
erase operation, a valid address is an address within any
sector selected for erasure. During chip erase, a valid
address is any non-protected sector address.
2. I/O
7
should be rechecked even if I/O
5
= "1" because
I/O
7
may change simultaneously with I/O
5
.
No
Read I/O
7
- I/O
0
Address = VA
I/O
5
= 1?
I/O
7
= Data ?
Yes
No
PASS
Yes
Yes
Figure 5. Data Polling Algorithm
A29DL16x Series
PRELIMINARY (September, 2004, Version 0.0) 24 AMIC Technology, Corp.
RY/BY : Read/Busy
The RY/ BY is a dedicated, open-drain output pin that
indicates whether an Embedded algorithm is in progress or
complete. The RY/ BY status is valid after the rising edge of
the final WE pulse in the command sequ ence. Since RY/BY
is an open-drain output, several RY/ BY pins can be tied
together in parallel with a pull-up resistor to VCC.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase
Suspend mode.) If the output is high (Ready), the device is
ready to read array data (including during the Erase Suspend
mode), or is in the standby mode.
Table 13 shows the outputs for RY/BY.
I/O6: Toggle Bit I
Toggle Bit I on I/O6 indicates whether an Embedded Pro gram
or Erase algorithm is in progress or complete, or whether the
device has entered the Erase Suspend mode. Toggle Bit I
may be read at any address, and is valid after the risin g edge
of the final WE pulse in the command sequence (prior t o the
program or erase operation), and during the sector erase
time-out.
During an Embedded Program or Erase algorithm operation,
successive read cycles to any address cause I/O6 to toggle.
The system may use either OE or CE to control the read
cycles. When the operation is complete, I/O6 stops toggling.
After an erase command sequence is written, if all sectors
selected for erasing are protected, I/O6 toggles for
approximately 100µs, then returns to reading array data. If not
all selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores the
selected sectors that are protected.
The system can use I/O6 and I/O2 together to determine
whether a sector is actively erasing or is erase-suspended.
When the device is actively erasing (that is, the Embedded
Erase algorithm is in progr ess), I/O6 toggles . When the device
enters the Erase Suspend mode, I/O6 stops toggling.
However, the system must also use I/O2 to determine which
sectors are erasing or erase-suspended. Alternatively, the
system can use I/O7 (see the subsection on " I/O7 : Data
Polling").
If a program address falls within a protected sector, I/O6
toggles for approximately 1µs after the program command
sequence is written, then returns to reading a rray data.
I/O6 also toggles during the erase-suspend-program mode,
and stops toggling once the Embedded Program algorithm is
complete.
Table 13 shows the outputs for Toggle Bit I on I/O6. Figure 6
shows the toggle bit algorithm. Figure 20 in the “AC
Characteristics” section sho ws the toggle bit timing diagrams.
Figure 23 shows the differences between I/O2 and I/O6 in
graphical form. See also the subsection on I/O2: Toggle Bit II.
START
Read I/O7-I/O0
Toggle Bit
= Toggle ?
Program/Erase
Operation Not
Commplete, Write
Reset Command
Yes
Note:
The system should recheck the toggle bit even if I/O5=”1"
because the toggle bit may stop toggling as I/O5changes to
“1”. See the subsections on I/O6and I/O2 for mor e information.
No
Read I/O7 - I/O0
Twice
I/O5 = 1?
Toggle Bit
= Toggle ?
Yes
Yes
Program/Erase
Operation Complete
No
No
Read I/O7-I/O0
(Notes 1,2)
Figure 6. Toggle Bit Algorithm
(Note 1)
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 25 AMIC Technology, Corp.
I/O2: Toggle Bit II
The "Toggle Bit II" on I/O2, when used with I/O6, indicates
whether a particular sector is actively erasing (that is, the
Embedded Erase algorithm is in progress), or whether that
sector is erase-suspended. Toggle Bit II is valid after the
rising edge of the final WE pulse in the command sequence.
I/O2 toggles when the system reads at addr esses within those
sectors that have been selected for eras ure. (The system may
use either OE or CE to control the read cycles.) But I/O2
cannot distinguish whether the sector is actively erasing or is
erase-suspended. I/O6, by comparison, indicates whether the
device is actively erasin g, or is in Erase Suspend, but can not
distinguish which sectors ar e selected for erasure. Thus, b oth
status bits are required for sector and mode information.
Refer to Table 8 to compare outputs for I/O2 and I/O6.
Figure 6 shows the toggle bit algor ithm in flowchart form, and
the section " I/O2: Toggle Bit II" explains the algorithm. See
also the " I/O6: Toggle Bit I" subsection. Figure 20 shows the
toggle bit timing diagram. Figure 21 shows the differences
between I/O2 and I/O6 in graphical form.
Reading Toggle Bits I/O6, I/O2
Refer to Figure 6 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read
I/O7-I/O0 at least twice in a row to determine whether a toggle
bit is toggling. Typically, a system would note and store the
value of the toggle bit after the first read. After the second
read, the system would compare the new value of the toggle
bit with the first. If the toggle bit is not toggling, the device has
completed the program or erase operation. The system can
read array data on I/O7-I/O0 on the following read cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the system also
should note whether the value of I/O 5 is high (see the section
on I/O5). If it is, the system should then determine again
whether the toggle bit is toggling, since the toggle bit may
have stopped toggling just as I/O5 went high. If the toggle bit
is no longer toggling, the device has successfully completed
the program or erase operation. If it is still toggling, the device
did not complete the operation successfully, and the system
must write the reset command to return to reading array data.
The remaining scenario is that the system initially determines
that the toggle bit is toggling and I/O 5 has not gone high. The
system may continue to monitor the toggle bit and I/O5
through successive read cycles, determining the status as
described in the previous paragraph. Alternatively, it may
choose to perform other system tasks. In this case, the
system must start at the beginning of the algorithm when it
returns to determine the status of the operation (top of Figu re
6).
I/O5: Exceeded Timing Limits
I/O5 indicates whether the program or erase time has
exceeded a specified internal pulse count limit. Under these
conditions I/O5 produces a "1." T his is a failure condition that
indicates the program or erase cycle was not successfully
completed.
The device may output a “1” on I/O5 if the system tries to
program a “1” to a location that was previously programmed
to “0.” Only an erase operation can change a “0” back to a
“1.” Under this condition, the device halts the operation, and
when the timing limit has been exceeded, I/O5 produces a
“1.” .
Under both these conditio ns, the system must write the reset
command to return to reading array data (or to the erase-
suspend-read mode if a bank was previously in the erase-
suspend-program mode).
I/O3: Sector Erase Timer
After writing a sector erase command sequence, the system
may read I/O3 to determine whether or not an erase
operation has begun. (T he sector erase timer does not apply
to the chip erase command.) If additional sectors are
selected for erasure, the entire time-out also applies after
each additional sector erase command. Whe n the time-out is
complete, I/O3 switches from "0" to "1." The system may
ignore I/O3 if the system can guarantee that the time
between additional sector erase commands will always be
less than 50µs. See also the "Sector Erase Command
Sequence" section.
After the sector erase command sequence is written, the
system should read the status on I/O7 ( Data Polling) or I/O6
(Toggle Bit 1) to ensure the device has accepted the
command sequence, and then read I/O3. If I/O3 is "1", the
internally controlled erase cycle has begun; all further
commands (Except Erase Suspend) are ignored until the
erase operation is complete. If I/O3 is "0", the device will
accept additional sector erase commands. To ensure the
command has been accepted, the system software should
check the status of I/O3 prior to and following each
subsequent sector erase command. If I/O3 is high on the
second status check, the last command might not have been
accepted.
Table 13 shows the status of I/O3 relative to the other statu s
bits.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 26 AMIC Technology, Corp.
Table 13. Write Operation Status
I/O7 I/O6 I/O5 I/O3 I/O2 RY/BY
Status (Note 2) (Note 1) (Note 2)
Embedded Program Algorithm 7I/O Toggle 0 N/A No toggle 0
Standard
Mode Embedded Erase Algorit hm 0 Toggle 0 1 Toggle 0
Erase
Suspended Sector 1 No toggle 0 N/A Toggle 1
Erase-Suspend-
Read Non-Erase
Suspend Sector Data Data Data Data Data 1
Erase
Suspend
Mode
Erase-Suspend-Program 7I/O Toggle 0 N/A N/A 0
Notes:
1. I/O5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has e xceeded the maximum timing limits.
Refer to the section on I/O5 for more information.
2. I/O7 and I/O2 require a valid address when reading status informatio n. Refer to the appropriate subsection for further details.
3. When rea ding write operation status bi ts, the system must always provide the bank addre ss where the Embedded Algorithm
is in progress. The device outputs arra y data if the system addresses a non-busy bank.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 27 AMIC Technology, Corp.
ABSOLUTE MAXIMUM RATINGS*
Storage Temperature Plastic Packages. . . -65°C to + 150°C
Ambient Temperature with Power Applied. -65°C to + 125°C
Voltage with Respect to Ground
VCC (Note 1) . . . . . . . . . . . . . . . . . . . . ……. . -0.5V to +4.0V
A9, OE & RESET (Note 2) . . . . . . . . . . . . -0.5V to +12.5V
WP /ACC . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to +10.5V
All other pins (Note 1) . . . . . . . . . . …. . -0.5V to VCC + 0.5V
Output Short Circuit Current (Note 3) . . . . . . . …. . 200mA
Notes:
1. Minimum DC voltage on input or I/O pins is -0.5V. During
voltage transitions, input or I/O pins may undershoot VSS
to -2.0V for periods of up to 20ns. Maximum DC voltage
on input and I/O pins is VCC +0.5V. See Figure 7. During
voltage transitions, input or I/O pins may overshoot to
VCC +2.0V for periods up to 20ns. See Figure 8.
2. Minimum DC input voltage on A9, OE , RESET and
WP /ACC is -0.5V. During voltage transitions, A9, OE ,
WP /ACC and RESET may overshoot VSS to -2.0V for
periods of up to 20ns. See Figure 7. Maximum DC input
voltage on A9 is +12.5V which may overshoot to 14.0V
for periods up to 20ns. Maximum DC input voltage on
WP /ACC is +9.5V which may overshoot to +12.0V for
period up to 20ns.
3. No more than one output is shorted to ground at a time.
Duration of the short circuit should not be greater than
one second.
*Comments
Stresses above those listed under "Absolute Maximum
Ratings" may cause permanent damage to this device. This
is a stress rating only; functional operation of the device at
these or any other conditions above those indicated in the
operational sections of this data sheet is not implied.
Exposure of the device to absolute maximum rating
conditions for extended periods may affect device reliability.
OPERATING RANGES
Industrial (I) Devices
Ambient Temperature (TA) . . . . . . . . . . . . . . -40°C to +85°C
VCC Supply Voltages
VCC for all devices . . . . . . . . . . . . . . . . . …...+2.7V to +3.6V
Operating ranges define those limits between which the
functionally of the device is guaranteed.
Figure 7. Maximum Negative Ov ershoot Waveform
20ns 20ns
20ns
+0.8V
-0.5V
-2.0V
Figure 8. Maximum Positive Overshoot Waveform
20ns20ns
20ns
VCC+0.5V
2.0V
VCC+2.0V
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 28 AMIC Technology, Corp.
DC CHARACTERISTICS
CMOS Compatible
Parameter
Symbol Parameter Description Test Description Min. Typ. Max. Unit
ILI Input Load Current VIN = VSS to VCC. VCC = VCC Max
±1.0 µA
ILIT A9 Input Load Current VCC = VCC Max, A9 =12.5V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC. VCC = VCC Max
±1.0 µA
5 MHz 9 16
CE = VIL, OE = VIH
Byte Mode 1 MHz 2 4
5 MHz 9 16
ICC1 VCC Active Read Current
(Notes 1, 2) CE = VIL, OE = VIH
Word Mode 1 MHz 2 4
mA
ICC2 VCC Active Write Current
(Notes 2, 3) CE= VIL, OE =VIH 20 30 mA
ICC3 VCC Standby Current (Note 2) CE= VIH, RESET= VCC ± 0.3V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) RESET= VSS ± 0.3V 0.2 5 µA
ICC5 Automatic Sleep Mode
(Note 2, 4) VIH = VCC ± 0.3V; VIL = VSS ± 0.3V 0.2 5 µA
Byte 21
45
ICC6 VCC Active Read-While-Program
Current (Notes 1, 2) CE = VIL, OE = VIH
Word
21 45 mA
Byte 21
45
ICC7 VCC Active Read-While-Erase
Current (Notes 1, 2) CE = VIL, OE = VIH
Word
21 45 mA
ICC8 VCC Active
Program-While-Erase-Suspen ded
Current (Notes 2, 5) CE = VIL, OE = VIH
17 35 mA
ACC pin 5 10
IACC ACC Accelerated Program Current,
Word or Byte CE = VIL, OE = VIH
VCC pin
15 30 mA
VIL Input Low Level -0.5 0.8 V
VIH Input High Level 0.7 x VCC VCC + 0.3 V
VHH Voltage forWP /ACC Sector
Protect/Unprotect and Program
Acceleration VCC = 3.0 V ± 10% 8.5 9.5 V
VID Voltage for Autoselect and
Temporary Unprotect Sector VCC = 3.0 V ± 10% 8.5 12.5 V
VOL Output Low Voltage IOL = 4.0mA, VCC = VCC Min
0.45 V
VOH1 IOH = -2.0 mA, VCC = VCC Min 0.85 x VCC
V
VOH2 Output High Voltage IOH = -100 µA, VCC = VCC Min VCC - 0.4
V
VLKO Low VCC Lock-Out Voltage (Note 5) 2.3 2.5 V
Notes:
1. The ICC current listed is t ypical ly less than 2 mA/MHz, withOEat VIH.
2. Maximum ICC specifications are tested with VCC = VCC max.
3. ICC active while Embedded Algorithm (program or erase) is in progress.
4. Automatic slee p mode en able s the lo w power mode when addresses rema in stable for tACC + 30ns. Typical sleep mode curren t
is 200nA.
5. Not 100% tested.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 29 AMIC Technology, Corp.
TEST CONDITIONS
Table 14. Test Specifications
Test Condition -70, -80 -90, -120 Unit
Output Load 1 TTL gate
Output Load Capacitance, CL(including jig capacitance) 30 100 pF
Input Rise and Fall Times 5 5 ns
Input Pulse Levels 0.0 - 3.0 0.0 - 3.0 V
Input timing measurement referenc e levels 1.5 1.5 V
Output timing measurement reference levels 1.5 1.5 V
Figure 9. Test Setup
Figure 10. Input Waveforms and Measurement Le vels
Measurement Le ve l
Input 1.5V 1.5V Output
3.0V
0.0V
6.2 K
Ω
Device
Under
Test
C
L
Diodes = IN3064 or Equivalent
2.7 K
Ω
3.3 V
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 30 AMIC Technology, Corp.
AC CHARACTERISTICS
Read Only Operations
Parameter Speed
JEDEC Std
Description Test Setup
-70 -80 -90 -120
Unit
tAVAV tRC Read Cycle Time (Note 1) Min. 70 80 90 120 ns
tAVQV tACC Address to Output Delay CE = VIL
OE = VIL Max. 70 80 90 120 ns
tELQV tCE Chip Enable to Output Delay OE = VIL Max. 70 80 90 120 ns
tGLQV tOE Output Enable to Output Delay Max. 30 30 40 50 ns
tEHQZ tDF Chip Enable to Output High Z
(Notes 1,3) Max. 16 16 16 16 ns
tGHQZ tDF Output Enable to Output High Z
(Notes 1,3) Max. 16 16 16 16 ns
tAXQX tOH Output Hold Time from Addresses,
CEor OE , Whichever Occurs First Min. 0 ns
Read Min. 0 ns
tOEH Output Enable Hold
Time (Note 1) Toggle and
Data Polling
Min. 10 ns
Notes:
1. Not 100% tested.
2. See Figure 9 and Table 14 for test specifications.
3. Measurements performed by placing a 50-ohm termination on the data pin with a bias of VCC/2. The time from OE high to
the data bus driven to VCC/2 is taken as tDF.
Figure 11. Read Operation Timings
Addresses Addresses Stable
CE
OE
WE
Out put Val i d High-Z
Output
tRC
tOEH
tOE
tCE
High-Z tOH
tDF
tACC
0V
RESET
RY/BY
tRH
tRH
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 31 AMIC Technology, Corp.
AC CHARACTERISTICS
Hardware Reset (RESET)
Parameter
JEDEC Std Description Test Setup All Speed Options Unit
tREADY RESET Pin Low (During Embedded
Algorithms) to Read or Write (See Note) Max 20 µs
tREADY RESET Pin Low (Not During Embedded
Algorithms) to Read or Write (See Note) Max 500 ns
tRP RESET Pulse Width Min 500 ns
tRH RESET High Time Before Read (See Note) Min 50 ns
tRB RY/BY Recovery Time Min 0 ns
tRPD RESET Low to Standby Mode Min 20 µs
Note: Not 100% tested.
Figure 12. RESET Timings
CE, OE
RESET tRH
tRP
tReady
Reset Timings NOT during Embedded Algorithms
RESET
tRP
~
~
Reset Timing s during Embedded Al gorithms
RY/BY
~
~
tRB
~
~
tReady
CE, OE
RY/BY
0V
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 32 AMIC Technology, Corp.
Data Output
(I/O
0
-I/O
14
)Data Output
(I/O
0
-I/O
7
)
I/O
15
Output Address Input
Data Output
(I/O
0
-I/O
14
)
Data Output
(I/O
0
-I/O
7
)
I/O
15
Output
Address Input
t
FHQV
t
FLQZ
t
ELFH
t
ELFL
CE
OE
BYTE
I/O
0
-I/O
14
I/O
15
(A-1)
BYTE
I/O
0
-I/O
14
I/O
15
(A-1)
BYTE
Switching
from word to
byte mode
BYTE
Switching
from byte to
word mode
AC CHARACTERISTICS
Word/Byte Configuration (BYTE)
Parameter All Speed Options
JEDEC Std
Description
-70 -80 -90 -120
Unit
tELFL/tELFH CE to BYTE Switching Low or High Max 5 ns
tFLQZ BYTE Switching Low to Output High-Z Max 25 25 30 30 ns
tHQV BYTE Switching High to Output Active Min 70 80 90 120 ns
Figure 13. BYTE Timings for Read Operations
Figure 14. BYTE Timings for Write Operations
Note:
Refer to the Erase/Program Operations table for tAS and tAH specifications.
The falling edge of the last WE signal
tHOLD(tAH)
tSET
(tAS)
CE
BYTE
WE
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 33 AMIC Technology, Corp.
AC CHARACTERISTICS
Erase and Program Operations
Parameter Speed
JEDEC Std
Description
-70 -80 -90 -120
Unit
tAVAV tWC Write Cycle Time (Note 1) Min. 70 80 90 120 ns
tAVWL tAS Address Setup Time Min. 0 ns
tASO Address Setup Time to OE low during toggle bit
polling 15 15 15 15
ns
tWLAX tAH Address Hold Time Min. 45 45 45 50
ns
tAHT Address Hold Time From CE or OE high during
toggle bit polling 0 ns
tDVWH tDS Data Setup Time Min. 35 35 45 50
ns
tWHDX tDH Data Hold Time Min. 0 ns
tOEPH Output Enable High during toggle bit polling Min. 20 20 20 20 ns
tGHWL tGHWL Read Recover Time Before Write
(OE high to WE low) Min. 0 ns
tELWL tCS CE Setup Time Min. 0 ns
tWHEH tCH CE Hold Time Min. 0 ns
tWLWH tWP Write Pulse Width Min. 30 30 35 50
ns
tWHDL tWPH Write Pulse Width High Min. 30 30 30 30
ns
tSR/W Latency Between Read and Write Operations Min. 0
Byte Typ. 5
tWHWH1 tWHWH1 Byte Programming Operation
(Note 2) Word Typ. 7 µs
tWHWH1 tWHWH1 Accelerated Programming Operation,
Word or Byte (Note 2) Typ. 4 sec
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec
tvcs VCC Set Up Time (Note 1) Min. 50 µs
tRB Recovery Time from RY/BY Min 0 ns
tBUSY Program/Erase Valid to RY/BY Delay Min 90 ns
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performance" section for more information.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 34 AMIC Technology, Corp.
AC CHARACTERISTICS
Figure 15. Program Operation Timings
Figure 16. Accelerated Program Timing Diagram
WP/ACC tVHH
~
~
VHH
VIL or VIH
tVHH
VIL or VIH
Addresses
CE
OE
WE
Data
VCC
A0h PD
tWC
PA
Program Command Se quence (l as t t wo cycles)
PA
DOUT
~
~
~
~
PA
~
~
Status
~
~
~
~
~
~
~
~
tAS
tVCS
Read Status Data (last two cycles)
555h
tAH
tWHWH1
tCH
tWP
tWPH
tCS tDS tDH
Note :
1. PA = program address, PD = program data, Dout is the true data at the program address.
2. Illustration shows device in word mode.
~
~
tRB
tBUSY
RY/BY
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 35 AMIC Technology, Corp.
Addresses
CE
OE
WE
Data
VCC
55h 30h
tWC
SA
Erase Command Sequence (last t w o cycles)
VA
Complete
~
~
~
~
VA
~
~
In
Progress
~
~
~
~
~
~
~
~
tAS
tVCS
Read Status Dat a
2AAh
tAH
tWHWH2
tCH
tWP
tWPH
tCS tDS tDH
Note :
1. SA = Sector Address (f or Sector Erase), VA = Valid Address for reading status data (see "Write Operaion Ststus").
2. Il lustration shows device i n word mode.
555h for chip erase
10h for chip erase
~
~
tRB
tBUSY
RY/BY
AC CHARACTERISTICS
Figure 17. Chip/Sector Erase Operation Timings
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 36 AMIC Technology, Corp.
AC CHARACTERISTICS
Figure 18. Back-to-back Read/Write Cycle Timings
Addresses
CE
OE
WE
Data
tWC
Valid RA Valid PA Valid PA
Valid
Out Valid
In
Valid PA
tRC tWC tWC
tCE
tACC tCPH
tCP
tOE
tGHWL
tOEH
tWP
tWPH
Valid
In
tDS tDH
tSR/W
Valid
In
tDF
tOH
tAH
WE Controlled Write Cycl e Read Cycle CE Controlled Write Cycles
Figure 19. Data Polling Timings (During Embedded Algorithms)
Addresses
CE
OE
WE
I/O7
tRC
VAVA VA
~
~
~
~
~
~
~
~
~
~
Complement
~
~
Complement True Valid Data High-Z
Status Data
~
~
Status Data True Valid Data High-Z
I/O0 - I/O6
tACC
tCE
tCH tOE
tOEH tDF
tOH
Note : VA = Valid Address. Il lustation shows f i rst status cycle after command sequence, last stat us read cycle, and array data
read cycle.
~
~
tBUSY
RY/BY
High-Z
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 37 AMIC Technology, Corp.
AC CHARACTERISTICS
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
Addresses
CE
OE
WE
I/O6 , I/O2
~
~~
~
Valid Status
tOEH
Valid Status Valid Status Valid Data
~
~
(first read) (second read) (stop togging)
RY/BY
~
~~
~
~
~
tAStAHT
tCEPH
tAHT
tASO
Valid Status
tOEPH
tOEtDH
Note: VA = Valid Address; not required for I/O6. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 21. I/O2 vs. I/O6
Enter
Embedded
Erasing
Erase
Suspend Enter Erase
Suspend Program Erase
Resume
WE
I/O6
I/O2
Erase Erase Suspend
Read Erase Suspend
Read Erase Erase
Complete
I/O2 and I/O6 toggle with OE and CE
Note : Both I/O6 and I/O2 toggle wi th OE or CE. See the text on I/O6 and I/O2 in the section "Write Operation Status" for
more information.
~
~
~
~
~
~
Erase
Suspend
Program
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
~
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 38 AMIC Technology, Corp.
AC CHARACTERISTICS
Temporary Sector/Sector Block Unprotect
Parameter
JEDEC Std Description All Speed Options Unit
tVIDR VID Rise and Fall Time (See Note) Min 500 ns
tVHH VHH Rise and Fall Time (See Note) Min 250 µs
tRSP RESET Setup Time for Temporary
Sector/Sector Block Unprotect Min 4 µs
tRRB RESET Hold Time from RY/BY High for
Temporary Sector/Sector Block Unprotect Min 4 µs
Note: Not 100% tested.
Figure 22. Temporary Sector/Sector Block Unprotect Timing Diagram
Program or Erase Command Sequence
RESET
~
~~
~~
~
VID
VSS, VIL,
or VIH
tVIDR tVIDR
tRSP
CE
WE
RY/BY
~
~
VID
VSS, VIL,
or VIH
tRRB
Program/Erase Command Sequence
555 2AA 555 XXX
~
~
~
~
AA 55 77 FQ
~
~
~
~
CE
WE
RY/BY
Address
I/O0 - I/O7
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 39 AMIC Technology, Corp.
AC CHARACTERISTICS
Figure 23. Sector/Sector Block Protect and Unprotect Timing Diagram
V
ID
Note : For sector protect, A6=0, A1=1, A0=0. For sector unprotect, A6=1, A1=1, A0=0
~
~
~
~~
~
~
~
V
IH
RESET
SA, A6,
A1, A0
Data
CE
WE
OE
Valid* Valid* Valid*
60h 60h 40h Status
Sector Protect/Unprotect Verify
1us Sector Protect:150us
Sector Unprotect:15ms
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 40 AMIC Technology, Corp.
AC CHARACTERISTICS
Alternate CE Controlled Erase and Prog ram Operations
Parameter Speed
JEDEC Std
Description
-70 -80 -90 -120
Unit
tAVAV tWC Write Cycle Time (Note 1) Min. 70 80 90 120 ns
tAVEL tAS Address Setup Time Min. 0 ns
tELAX tAH Address Hold Time Min. 45 45 45 50 ns
tDVEH tDS Data Setup Time Min. 35 35 45 50 ns
tEHDX tDH Data Hold Time Min. 0 ns
tGHEL tGHEL Read Recover Time Before Write
(OE High to WE Low) Min. 0 ns
tWLEL tWS WE Setup Time Min. 0 ns
tEHWH tWH WE Hold Time Min. 0 ns
tELEH tCP CE Pulse Width Min. 30 30 45 50 ns
tEHEL tCPH CE Pulse Width High Min. 30 30 30 30 ns
Byte Typ. 5
tWHWH1 tWHWH1 Programming Operation
(Note 2) Word Typ. 7
µs
tWHWH1 tWHWH1 Accelerated Programmi ng Operation,
Word or Byte (Note 2) Typ. 4 µs
tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ. 0.7 sec
Notes:
1. Not 100% tested.
2. See the "Erase and Programming Performa nce" section for more information.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 41 AMIC Technology, Corp.
AC CHARACTERISTICS
Figure 24. Alternate CE Controlled Write (Erase/Program) Operati on Timings
Addresses
WE
OE
CE
Data
555 for program
2AA f or er ase
PA
DOUT
~
~
~
~
I/O7
~
~
~
~
~
~
Data Polling
PD for program
30 for sector erase
10 for chip erase
~
~
tBUSY
tWHWH1 or 2
tAH
tAStWC
tWH
tCP
tWS
tCPH
PA for program
SA for sector erase
555 for chip erase
A0 for program
55 for erase
tRH
tDStDH
~
~
~
~
RESET
RY/BY
tGHEL
Notes:
1. Figure indicates last two bus cycles of a program or erase operation.
2. PA = program address, SA = sector address, PD = program data.
3. 7I/O is the complement of the data written to the device. DOUT is the data written to the device.
4. Waveforms are for the word mode.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 42 AMIC Technology, Corp.
ERASE AND PROGRAMMING PERFORMANCE
Parameter Typ. (Note 1) Max. (Note 2) Unit Comment s
Sector Erase Time 0.7 15 sec
Chip Erase Time 27 sec
Excludes 00h programming
prior to erasure (Note 4)
Byte Programming Time 5 150 µs
Word Programming Time 7 210 µs
Accelerated Word/Byte Progr amming Time 4 120 µs
Byte Mode 9 27 sec Chip Programming Time
(Note 3) Word Mode 6 18 sec
Excludes system-level
overhead (Note 5)
Notes:
1. Typical program and erase times assume the follo wing conditions: 25 °C, 3.0V VCC, 10, 000 cycles. Addition ally, progr amming
typically assumes checkerboard pattern.
2. Under worst case conditions of 90°C, VCC = 2.7V, 100,000 cycles.
3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes
program faster than the maximum byte program time listed.
4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programm ed to 00h before erasure.
5. System-level overhead is t he time requ ired to exec ute the four-b us-cycle comma nd sequence for programming. See T able 12
for further information on command definiti ons.
6. The device has a minimum erase and program cycle enduranc e of 10,000 cycles.
LATCH-UP CHARACTERISTICS
Description Min. Max.
Input Voltage with respect to VSS on all I/O pins -1.0V VCC+1.0V
VCC Current -100 mA +100 mA
Input voltage with respect to VSS on all pins except I/O pins
(including A9, OE and RESET) -1.0V 12.5V
Includes all pins except VCC. T est conditio ns: VCC = 3.0V, one pin at time.
PACKAGE AND PIN CAP ACITANCE
Parameter Symbol Parameter Description Test Setup Typ. Max. Unit
TSOP 6 7.5 pF
CIN Input Capacitance VIN=0 BGA 4.2 5 pF
TSOP 8.5 12 pF
COUT Output Capacitance VOUT=0 BGA 5.4 6.5 pF
TSOP 7.5 9 pF
CIN2 Control Pin Capacitance VIN=0 BGA 3.9 4.7 pF
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0MHz
DATA RETENTION
Parameter Test Conditions Min Unit
150°C 10 Years
Minimum Pattern Data Retention Time 125°C 20 Years
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 43 AMIC Technology, Corp.
Ordering Information
Top Boot Sector Flash
Part No. Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA) Package
A29DL162TV-70 48 pin TSOP
A29DL162TG-70 70 10 20 0.2
48 pin TFBGA
A29DL162TV-80 48 pin TSOP
A29DL162TG-80 80 10 20 0.2
48 pin TFBGA
A29DL162TV-90 48 pin TSOP
A29DL162TG-90 90 10 20 0.2
48 pin TFBGA
A29DL162TV-120 48 pin TSOP
A29DL162TG-120 120 10 20 0.2
48 pin TFBGA
A29DL163TV-70 48 pin TSOP
A29DL163TG-70 70 10 20 0.2
48 pin TFBGA
A29DL163TV-80 48 pin TSOP
A29DL163TG-80 80 10 20 0.2
48 pin TFBGA
A29DL163TV-90 48 pin TSOP
A29DL163TG-90 90 10 20 0.2
48 pin TFBGA
A29DL163TV-120 48 pin TSOP
A29DL163TG-120 120 10 20 0.2
48 pin TFBGA
A29DL164TV-70 48 pin TSOP
A29DL164TG-70 70 10 20 0.2
48 pin TFBGA
A29DL164TV-80 48 pin TSOP
A29DL164TG-80 80 10 20 0.2
48 pin TFBGA
A29DL164TV-90 48 pin TSOP
A29DL164TG-90 90 10 20 0.2
48 pin TFBGA
A29DL164TV-120 48 pin TSOP
A29DL164TG-120 120 10 20 0.2
48 pin TFBGA
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 44 AMIC Technology, Corp.
Ordering Information (continued)
Bottom Boot Sector Flash
Part No. Access Time
(ns)
Active Read
Current
Typ. (mA)
Program/Erase
Current
Typ. (mA)
Standby Current
Typ. (µA) Package
A29DL162UV-70 48 pin TSOP
A29DL162UG-70 70 10 20 0.2 48 pin TFBGA
A29DL162UV-80 48 pin TSOP
A29DL162UG-80 80 10 20 0.2 48 pin TFBGA
A29DL162UV-90 48 pin TSOP
A29DL162UG-90 90 10 20 0.2 48 pin TFBGA
A29DL162UV-120 48 pin TSOP
A29DL162UG-120 120 10 20 0.2 48 pin TFBGA
A29DL163UV-70 48 pin TSOP
A29DL163UG-70 70 10 20 0.2 48 pin TFBGA
A29DL163UV-80 48 pin TSOP
A29DL163UG-80 80 10 20 0.2 48 pin TFBGA
A29DL163UV-90 48 pin TSOP
A29DL163UG-90 90 10 20 0.2 48 pin TFBGA
A29DL163UV-120 48 pin TSOP
A29DL163UG-120 120 10 20 0.2 48 pin TFBGA
A29DL164UV-70 48 pin TSOP
A29DL164UG-70 70 10 20 0.2 48 pin TFBGA
A29DL164UV-80 48 pin TSOP
A29DL164UG-80 80 10 20 0.2 48 pin TFBGA
A29DL164UV-90 48 pin TSOP
A29DL164UG-90 90 10 20 0.2 48 pin TFBGA
A29DL164UV-120 48 pin TSOP
A29DL164UG-120 120 10 20 0.2 48 pin TFBGA
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 45 AMIC Technology, Corp.
Package Information
TSOP 48L (Type I) Outline Dimensions unit: inches/mm
1
E
c
D
L
θ
Detail "A"
0.25
24 25
48
D
1
D
y
e
SA1
A2A
Detail "A"
b
Dimensions in inches Dimensions in mm
Symbol Min Nom Max Min Nom Max
A - - 0.047 - - 1.20
A1 0.002 - 0.006 0.05 - 0.15
A2 0.037 0.039 0.042 0.94 1.00 1.06
b 0.007 0.009 0.011 0.18 0.22 0.27
c 0.004 - 0.008 0.12 - 0.20
D 0.779 0.787 0.795 19.80 20.00 20.20
D1 0.720 0.724 0.728 18.30 18.40 18.50
E - 0.472 0.476 - 12.00 12.10
e 0.020 BASIC 0.50 BASIC
L 0.016 0.020 0.024 0.40 0.50 0.60
S 0.011 Typ. 0.28 Typ.
y - - 0.004 - - 0.10
θ 0° - 8° 0° - 8°
Notes:
1. The maximum value of dimension D includes end flash.
2. Dimension E does not includ e resin fins.
3. Dimension S includes end flash.
A29DL16x Series
PRELIMINARY (September, 2004, Versi on 0.0) 46 AMIC Technology, Corp.
Package Information
48LD CSP (6 x 8 mm) Outline Dimensions unit: mm
(48TFBGA)
A1
H
G
F
E
D
C
B
A
TOP VIEW
SIDE VIEW
C SEATING PLANE
123456
BOTTOM VIEW
Ball*A1 CORNER
H
G
F
E
D
C
B
A
E
E1
e
e
D
1
D
b
0.10 C
A
Dimensions in mm
Symbol Min. Nom. Max.
A - - 1.20
A1 0.20 0.25 0.30
b 0.30 - 0.40
D 5.90 6.00 6.10
D1 4.00 BSC
e - 0.80 -
E 7.90 8.00 8.10
E1 5.60 BSC
