0.1 GHz to 18 GHz, GaAs SP4T Switch
Data Sheet
HMC641A
Rev. D Document Feedback
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FEATURES
Broadband frequency range: 0.1 GHz to 18 GHz
Nonreflective 50 Ω design
Low insertion loss: 2.1 dB to 12 GHz
High isolation: 42 dB to 12 GHz
High input linearity
P1dB: 25 dBm typical at VSS = −5 V
IP3: 41 dBm typical
High power handling at VSS = −5 V
24 dBm through path
23 dBm terminated path
Integrated 2 to 4 line decoder
8-pad, 1.92 mm × 1.60 mm × 0.102 mm, CHIP
APPLICATIONS
Test instrumentation
Microwave radios and very small aperture terminals (VSATs)
Military radios, radars, and electronic counter measures (ECMs)
Broadband telecommunications systems
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
GENERAL DESCRIPTION
The HMC641A is a nonreflective, single-pole, four-throw
(SP4T) switch, manufactured using a gallium arsenide (GaAs)
process. This switch typically provides low insertion loss of
2.1 dB and high isolation of 42 dB in broadband frequency
range from 0.1 GHz to 18 GHz.
The HMC641A includes an on-chip, binary 2 to 4 line decoder
that provides control from two logic input lines.
The switch operates with a negative supply voltage of −5 V to
−3 V and requires two negative logic control voltages.
All electrical performance data is acquired with the HMC641A
that all RFx pads are connected to by the 50 Ω transmission
lines via one 3.0 mil × 0.5 mil ribbon bond of minimal length.
50Ω 50Ω
RF1 RF2
RF4 RF3
GND
RFC CTRLA
CTRLB
V
SS
HMC641A
50Ω 50Ω
15148-001
2 TO 4 LINE DE CODER
HMC641A Data Sheet
Rev. D | Page 2 of 10
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Power Derating Curve ................................................................. 4
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
Interface Schematics..................................................................... 5
Typical Performance Characteristics ..............................................6
Insertion Loss, Return Loss, and Isolation ................................6
Input Power Compression (P1dB) and Third-Order Intercept
(IP3) ................................................................................................7
Theory of Operation .........................................................................8
Applications Information .................................................................9
Mounting and Bonding Techniques ...........................................9
Assembly Diagram ........................................................................9
Outline Dimensions ....................................................................... 10
Ordering Guide .......................................................................... 10
REVISION HISTORY
10/2018—Rev. C to Rev. D
Updated Outline Dimensions ....................................................... 10
This Hittite Microwave Products data sheet has been reformatted to
meet the styles and standards of Analog Devices, Inc.
3/2017—Rev. 02.0316 to Rev. C
Updated Format .................................................................. Universal
Changes to Features Section, Figure 1, and General Description
Section ................................................................................................ 1
Changed VSS = −5 V to VSS = −5 V to −3 V, Table 1 ..................... 3
Changes to Table 1 ............................................................................ 3
Deleted Bias Voltage & Current Table, TTL/CMOS Control
Voltage Table, and Truth Table ....................................................... 3
Changes to Table 2 ............................................................................ 4
Added Power Derating Curve Section and Figure 2;
Renumbered Sequentially ................................................................ 4
Added Figure 4 .................................................................................. 5
Deleted GND Interface Schematic Figure and TTL Interface
Circuit Figure ..................................................................................... 5
Changes to Table 3 and Figure 5...................................................... 5
Added Table 4; Renumbered Sequentially ..................................... 8
Added Theory of Operation Section .............................................. 8
Added Applications Information Section, Figure 14, Figure 15,
and Assembly Diagram Section ....................................................... 9
Updated Outline Dimensions ....................................................... 10
Updated Ordering Guide .............................................................. 10
Data Sheet HMC641A
Rev. D | Page 3 of 10
SPECIFICATIONS
VSS = −5 V to −3 V, VCTL = 0 V or VSS, TDIE = 25°C, 50 Ω system, unless otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
BROADBAND FREQUENCY RANGE f 0.1 18 GHz
INSERTION LOSS 0.1 GHz to 12 GHz 2.1 2.4 dB
0.1 GHz to 18 GHz 2.3 3.0 dB
ISOLATION
Between RFC and RF1 to RF4 0.1 GHz to 12 GHz 39 42 dB
0.1 GHz to 18 GHz
36
38
dB
RETURN LOSS
RFC 0.1 GHz to 18 GHz 15 dB
RF1 to RF4
On State 0.1 GHz to 18 GHz 15 dB
Off State 0.1 GHz to 18 GHz 15 dB
SWITCHING CHARACTERISTICS
Rise and Fall Time
t
RISE
, t
FAL L
10% to 90% of RF output
15
ns
On and Off Time tON, tOFF 50% VCTL to 90% of RF output 95 ns
INPUT LINEARITY1 250 MHz to 18 GHz
1 dB Compression P1dB VSS = −5 V 22 25 dBm
VSS = −3 V 22 dBm
Third-Order Intercept IP3 10 dBm per tone, 1 MHz spacing
VSS = −5 V 38 41 dBm
VSS = −3 V 41 dBm
SUPPLY VSS pin
Voltage VSS −5 −3 V
Current ISS 1.9 6 mA
DIGITAL CONTROL INPUTS CTRLA and CTRLB pins
Voltage VCTL
Low VINL VSS = −5 V −3 0 V
VSS = −3 V −1 0 V
High VINH VSS = −5 V −5 −4.2 V
VSS = −3 V −3 −2.2 V
Current ICTL
Low IINL 50 µA
High IINH 0.2 µA
1 Input linearity performance degrades at frequencies less than 250 MHz; see Figure 10, Figure 11, Figure 12, and Figure 13.
HMC641A Data Sheet
Rev. D | Page 4 of 10
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage −7 V
Digital Control Input Voltage
V
SS
− 0.5 V to +1 V
RF Input Power1
(f = 250 MHz to 18 GHz, TDIE = 85°C)
VSS = −5 V
Through Path 24 dBm
Terminated Path 23 dBm
Hot Switching
20 dBm
VSS = −3 V
Through Path 21 dBm
Terminated Path 20 dBm
Hot Switching 17 dBm
Temperature
Junction Temperature, TJ 150°C
Die Bottom Temperature Range, TDIE −55°C to +85°C
Storage Temperature Range −65°C to +150°C
Junction to Die Bottom Thermal Resistance
Through Path 201°C/W
Terminated Path 322°C/W
ESD Sensitivity
Human Body Model (HBM) 250 V (Class 1A)
1 For power derating at frequencies less than 250 MHz, see Figure 2.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
POWER DERATING CURVE
Figure 2. Power Derating at Frequencies Less Than 250 MHz
ESD CAUTION
2
–10 0.10.01 1
POWER DE RATI NG (d B)
FRE Q UE NCY ( GHz)
–8
–6
–4
–2
0
15148-002
Data Sheet HMC641A
Rev. D | Page 5 of 10
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 3. Pin Configuration
Table 3. Pad Function Descriptions1
Pad No. Mnemonic Description
1 RFC
RF Common Pad. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
2 RF1
RF Throw Pad 1. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
3 RF2
RF Throw Pad 2. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
4 CTRLA Control Input A; see Table 4. See Figure 5 for the interface schematic.
5 CTRLB Control Input B; see Table 4. See Figure 5 for the interface schematic.
6 VSS Negative Supply Voltage.
7 RF3
RF Throw Pad 3. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
8 RF4
RF Throw Pad 4. This pad is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 4 for the interface schematic.
Die Bottom GND Ground. Die bottom must be attached directly to the ground plane eutectically or with conductive epoxy.
1 No connection is required for the unlabeled grounds.
INTERFACE SCHEMATICS
Figure 4. RFC to RF4 Interface Schematic Figure 5. CTRLA and CTRLB Interface Schematic
23
1
87
4
5
6
CTRLA
CTRLB
V
SS
RFC
RF1
HMC641A
TOP VIEW
(Not to Scale)
RF2
RF4 RF3
15148-003
RFC,
RF1,
RF2,
RF3,
RF4
15148-004
500Ω
CTRLA,
CTRLB
V
SS
100kΩ
15148-005
HMC641A Data Sheet
Rev. D | Page 6 of 10
TYPICAL PERFORMANCE CHARACTERISTICS
INSERTION LOSS, RETURN LOSS, AND ISOLATION
Figure 6. Insertion Loss Between RFC and RF1 vs. Frequency over
Temperature
Figure 7. Return Loss for RFC, RF1 to RF4 On and RF1 to RF4 Off vs.
Frequency
Figure 8. Insertion Loss Between RFC and RF1 to RF4 vs. Frequency
Figure 9. Isolation Between RFC and RF1 to RF4 vs. Frequency
0
–5 020
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
–4
–3
–2
–1
246810 12 14 16 18
TDIE = +85°C
TDIE = +25°C
TDIE = –55° C
15148-006
0
–40
RET URN LOS S ( dB)
–35
–30
–25
–20
–15
–10
–5
020
FRE Q UE NCY ( GHz)
246810 12 14 16 18
RFC
RF1 TO RF4 ON
RF1 TO RF4 OFF
15148-007
0
–5 020
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
–4
–3
–2
–1
246810 12 14 16 18
RF1
RF2
RF3
RF4
15148-008
0
–100
ISOLATION (dB)
–90
–80
–70
–60
–50
–40
–30
–20
–10
020
FRE Q UE NCY ( GHz)
246810 12 14 16 18
RF1
RF2
RF3
RF4
15148-009
Data Sheet HMC641A
Rev. D | Page 7 of 10
INPUT POWER COMPRESSION (P1dB) AND THIRD-ORDER INTERCEPT (IP3)
Figure 10. Input P1dB vs. Frequency over Temperature, VSS = −5 V
Figure 11. Input IP3 vs. Frequency over Temperature, VSS = −5 V
Figure 12. Input P1dB vs. Frequency over Temperature, VSS = −3 V
Figure 13. Input IP3 vs. Frequency over Temperature, VSS = −3 V
30
10 0246810 12 14 16 18
INPUT P1dB (dBm)
FRE Q UE NCY ( GHz)
12
14
16
18
20
22
24
26
28 TDIE = +85°C
TDIE = +25°C
TDIE = –55° C
15148-010
50
45
40
35
30
25
20
INPUT I P 3 ( dBm)
0246810 12 14 16 18
FRE Q UE NCY ( GHz)
TDIE = +85°C
TDIE = +25°C
TDIE = –55° C
15148-011
30
10 0246810 12 14 16 18
INPUT P1dB (dBm)
FRE Q UE NCY ( GHz)
12
14
16
18
20
22
24
26
28 TDIE = +85°C
TDIE = +25°C
TDIE = –55° C
15148-012
50
45
40
35
30
25
20
INPUT I P 3 ( dBm)
0246810 12 14 16 18
FRE Q UE NCY ( GHz)
TDIE = +85°C
TDIE = +25°C
TDIE = –55° C
15148-013
HMC641A Data Sheet
Rev. D | Page 8 of 10
THEORY OF OPERATION
The HMC641A requires a negative supply voltage at the VSS pad
and two logic control inputs at the CTRLA and CTRLB pads to
control the state of the RF paths.
Depending on the logic level applied to the CTRLA and CTRLB
pads, one RF path is in the insertion loss state while the other
three paths are in an isolation state (see Table 4). The insertion loss
path conducts the RF signal between the RF throw pad and RF
common pad while the isolation paths provide high loss between
RF throw pads terminated to internal 50 Ω resistors and the
insertion loss path.
The ideal power-up sequence is as follows:
1. Ground to the die bottom.
2. Power up VSS.
3. Power up the digital control inputs. The relative order of the
logic control inputs is not important. However, powering the
digital control inputs before the VSS supply can inadvertently
become forward-biased and damage the internal electrostatic
discharge (ESD) protection structures.
4. Apply an RF input signal. The design is bidirectional; the
RF input signal can be applied to the RFC pad while the RF
throw pads are the outputs or the RF input signal can be
applied to the RF throw pads while the RFC pad is the
output. All of the RF pads are dc-coupled to 0 V, and no dc
blocking is required at the RF pads when the RF line
potential is equal to 0 V.
The power-down sequence is the reverse of the power-up
sequence.
Table 4. Control Voltage Truth Table
Digital Control Input RF Paths
CTRLA CTRLB RF1 to RFC RF2 to RFC RF3 to RFC RF4 to RFC
High High Insertion loss (on) Isolation (off ) Isolation (off) Isolation (off)
Low High Isolation (off) Insertion loss (on) Isolation (off) Isolation (off)
High Low Isolation (off) Isolation (off) Insertion loss (on) Isolation (off)
Low Low Isolation (off) Isolation (off) Isolation (off) Insertion loss (on)
Data Sheet HMC641A
Rev. D | Page 9 of 10
APPLICATIONS INFORMATION
MOUNTING AND BONDING TECHNIQUES
The HMC641A is back metallized and must be attached directly
to the ground plane with gold tin (AuSn) eutectic preforms or
with electrically conductive epoxy.
The die thickness is 0.102 mm (4 mil). The 50 Ω microstrip
transmission lines on 0.127 mm (5 mil) thick alumina thin film
substrates are recommended for bringing RF to and from the
HMC641A (see Figure 14).
Figure 14. Bonding RF Pads to 5 mil Substrate
When using 0.254 mm (10 mil) thick alumina thin film substrates,
the HMC641A must be raised 0.150 mm (6 mil) so the surface of
the HMC641A is coplanar with the surface of the substrate. One
way to accomplish this is by attaching the 0.102 mm (4 mil) thick
die to a 0.150 mm (6 mil) thick molybdenum heat spreader (moly
tab), which is then attached to the ground plane (see Figure 15).
Figure 15. Bonding RF Pads to 10 mil Substrate
Microstrip substrates are placed as close to the HMC641A as
possible to minimize bond length. Typical die to substrate
spacing is 0.076 mm (3 mil).
RF bonds made with 3 mil × 5 mil ribbon are recommended.
DC bonds made with 1 mil diameter wire are recommended.
All bonds must be as short as possible.
ASSEMBLY DIAGRAM
An assembly diagram of the HMC641A is shown in Figure 16.
Figure 16. Die Assembly Diagram
RF G R O UND P LANE
0.10 2mm (0 . 0 04") T HICK GaAs MM IC
RIBB ON BOND
0.12 7mm (0. 00 5") T HICK ALUM INA
THIN FILM SUBSTRATE
0.076mm
(0.003")
15148-014
RF GROUND PLANE
0.10 2mm (0.004") THI CK G a As M M I C
RIBBON BOND
0.254mm (0.010") THI CK ALUM INA
THIN FILM SUBSTRATE
0.150mm
(0.006”) THICK
MOLY TAB
0.076mm
(0.003")
15148-015
15148-016
HMC641A Data Sheet
Rev. D | Page 10 of 10
OUTLINE DIMENSIONS
Figure 17. 8-Pad Bare Die [CHIP]
(C-8-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2 Temperature Range Package Description Package Option
HMC641A −55°C to +85°C 8-Pad Bare Die [CHIP] C-8-9
HMC641A-SX −55°C to +85°C 8-Pad Bare Die [CHIP] C-8-9
1 The HMC641A is a RoHS compliant part.
2 The HMC641A-SX is a sample order model.
09-24-2018-B
0.102
SIDE VIEW
TOP VIEW
(CIRCUI T SIDE)
1.600
1.920
0.661
0.125
2
1
3
8 7
4
5
6
K6101
2015
0.122
0.140
0.548
0.266
0.457
0.455
0.1140.100
0.127
0.200
0.200
0.200
0.200
0.203
0.206
0.074 ×0.074
(Pads 4-6)
0.198 ×0.100
(Pads 2-3 and 7-8)
0.100 ×0.198
©2018 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15148-0-10/18(D)
