PIC16F1934-I/PT - MICROCHIP

 2008-2011 Microchip Technology Inc. DS41364E

PIC16(L)F1934/6/7

Data Sheet

28/40/44-Pin Flash-Based, 8-Bit

CMOS Microcontrollers with

LCD Driver and nanoWatt XLP Technology

DS41364E-page 2  2008-2011 Microchip Technology Inc.

Information contained in this publication regarding device

applications and the like is provided only for your convenience

and may be superseded by updates. It is your responsibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, MXLAB, SEEVAL and The Embedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial

Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

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SQTP is a service mark of Microchip Technology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-013-4

Note the following details of the code protection feature on Microch ip devices:

• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our

products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

 2008-2011 Microchip Technology Inc. DS41364E-page 3

PIC16(L)F1934/6/7

Devices Included In This Data Sheet:

Other PIC16(L)F193X Devices Available:

High-Performance RISC CPU:

• Only 49 Instructions to Learn:

- All single-cycle instructions except branches

• Operating Speed:

- DC – 32 MHz oscillator/clock input

- DC – 125 ns instruction cycle

• Up to 16K x 14 Words of Flash Program Memory

• Up to 1024 Bytes of Data Memory (RAM)

• Interrupt Capability with Automatic Context

Saving

• 16-Level Deep Hardware Stack

• Direct, Indirect and Relative Addressing modes

• Processor Read Access to Program Memory

• Pinout Compatible to other 28/40/44-pin

PIC16CXXX and PIC16FXXX Microcontrollers

S pecial Microcontroller Features:

• Precision Internal Oscillator:

- Factory calibrated to ±1%, typical

- Software selectable frequency range from

32 MHz to 31 kHz

• Power-Saving Sleep mode

• Power-on Reset (POR)

• Power-up Timer (PWRT) and Oscillator Start-up

Timer (OST)

• Brown-out Reset (BOR)

- Selectable between two trip points

- Disable in Sleep option

• Multiplexed Master Clear with Pull-up/Input Pin

• Programmable Code Protection

• High Endurance Flash/EEPROM cell:

- 100,000 write Flash endurance

- 1,000,000 write EEPROM endurance

- Flash/Data EEPROM retention: > 40 years

• Wide Operating Voltage Range:

- 1.8V-5.5V (PIC16F193X)

- 1.8V-3.6V (PIC16LF193X)

PIC16LF193X Low-Power Features:

• Standby Current:

- 60 nA @ 1.8V, typical

• Operating Current:

-7.0A @ 32 kHz, 1.8V, typical (PIC16LF193X)

-150A @ 1 MHz, 1.8V, typical (PIC16LF193X)

• Timer1 Oscillator Current:

- 600 nA @ 32 kHz, 1.8V, typical

• Low-Power Watchdog Timer Current:

- 500 nA @ 1.8V, typical (PIC16LF193X)

Peripheral Feat ures:

• Up to 35 I/O Pins and 1 Input-only Pin:

- High-current source/sink for direct LED drive

- Individually programmable interrupt-on-pin

change pins

- Individually programmable weak pull-ups

• Integrated LCD Controller:

- Up to 96 segments

- Variable clock input

- Contrast control

- Internal voltage reference selections

• Capacitive Sensing module (mTouchTM)

- Up to 16 selectable channels

• A/D Converter:

- 10-bit resolution and up to 14 channels

- Selectable 1.024/2.048/4.096V voltage

reference

• Timer0: 8-Bit Timer/Counter with 8-Bit

Programmable Prescaler

• Enhanced Timer1

- Dedicated low-power 32 kHz oscillator driver

- 16-bit timer/counter with prescaler

- External Gate Input mode with toggle and

single shot modes

- Interrupt-on-gate completion

• Timer2, 4, 6: 8-Bit Timer/Counter with 8-Bit Period

• Two Capture, Compare, PWM modules (CCP)

- 16-bit Capture, max. resolution 125 ns

- 16-bit Compare, max. resolution 125 ns

- 10-bit PWM, max. frequency 31.25 kHz

• Three Enhanced Capture, Compare, PWM

modules (ECCP)

- 3 PWM time-base options

- Auto-shutdown and auto-restart

- PWM steering

- Programmable dead-band delay

• PIC16F1934 • PIC16LF1934

• PIC16F1936 • PIC16LF1936

• PIC16F1937 • PIC16LF1937

• PIC16(L)F1933 (DS41575)

• PIC16(L)F1938/9 (DS41574)

Note: PIC16(L)F193X devices referred to in this

data sheet apply to PIC16(L)F1934/6/7.

28/40/44-Pin F l ash-Based, 8-Bi t CMOS Microcon trollers wit h

LCD Driver with nanoWatt XLP Technology

PIC16(L)F1934/6/7

DS41364E-page 4  2008-2011 Microchip Technology Inc.

Peripheral Feat ures (Continued):

• Master Synchronous Serial Port (MSSP) with SPI

and I2 CTM with:

- 7-bit address masking

- SMBus/PMBusTM compatibility

- Auto-wake-up on start

• Enhanced Universal Synchronous Asynchronous

Receiver Transmitter (EUSART)

- RS-232, RS-485 and LIN compatible

- Auto-Baud Detect

• SR Latch (555 Timer):

- Multiple Set/Reset input options

- Emulates 555 Timer applications

• 2 Comparators:

- Rail-to-rail inputs/outputs

- Power mode control

- Software enable hysteresis

• Voltage Reference module:

- Fixed Voltage Reference (FVR) with 1.024V,

2.048V and 4.096V output levels

- 5-bit rail-to-rail resistive DAC with positive

and negative reference selection

PIC16(L)F193X Famil y Types

Device

Program Memory

Flash (words)

Data EEPROM

(bytes)

SRAM (bytes)

I/O’s

10-bit A/D

(ch)

CapSense

(ch)

Comparators

Timers

8/16-bit

EUSART

I2C™/SPI

ECCP

CCP

LCD

PIC16F1934

PIC16LF1934 4096 256 256 36 14 16 2 4/1 Yes Yes 3 2 24/4

PIC16F1936

PIC16LF1936 8192 256 512 25 11 8 2 4/1 Yes Yes 3 2 16(1)/4

PIC16F1937

PIC16LF1937 8192 256 512 36 14 16 2 4/1 Yes Yes 3 2 24/4

Note 1: COM3 and SEG15 share the same physical pin on PIC16(L)F1936, therefore, SEG15 is not available when using 1/4

multiplex displays.

 2008-2011 Microchip Technology Inc. DS41364E-page 5

PIC16(L)F1934/6/7

Pin Diagram – 28-Pin SPDIP/SOIC/SSOP (PIC16(L)F1936)

28-pin SPDIP, SOIC, SSOP

PIC16F1936

PIC16LF1936

VPP/MCLR/RE3

SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0

SEG7/C12IN1-/AN1/RA1

COM2/DACOUT/VREF-/C2IN+/AN2/RA2

SEG15/COM3/VREF+/C1IN+/AN3/RA3

SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4

SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5

RB6/ICSPCLK/ICDCLK/SEG14

RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1

RB4/AN11/CPS4/P1D/COM0

RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3

RB2/AN8/CPS2/P1B/VLCD2

RB1/AN10/C12IN3-/CPS1/P1C/VLCD1

RB0/AN12/CPS0/CCP4/SRI/INT/SEG0

VDD

VSS

14 15

VSS

SEG2/CLKIN/OSC1/RA7

SEG1/VCAP(2)/CLKOUT/OSC2/RA6

P2B(1)/T1CKI/T1OSO/RC0

P2A(1)/CCP2(1)/T1OSI/RC1

SEG3/P1A/CCP1/RC2

SEG6/SCL/SCK/RC3

RC5/SDO/SEG10

RC4/SDI/SDA/T1G(1)/SEG11

RC7/RX/DT/P3B/SEG8

RC6/TX/CK/CCP3(1)/P3A(1)/SEG9

RB7/ICSPDAT/ICDDAT/SEG13

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1936 devices only.

PIC16(L)F1934/6/7

DS41364E-page 6  2008-2011 Microchip Technology Inc.

Pin Diagram – 28-Pin QFN/UQFN (PIC16(L)F1936)

P2B(1)/T1CKI/T1OSO/RC0

RB7/ICSPDAT/ICDDAT/SEG13

RB6/ICSPCLK/ICDCLK/SEG14

RB5/AN13/CPS5/P2B(1)/CCP3(1)/P3A(1)/T1G(1)/COM1

RB4/AN11/CPS4/P1D/COM0

RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3

RB2/AN8/CPS2/P1B/VLCD2

RB1/AN10/C12IN3-/CPS1/P1C/VLCD1

RB0/AN12/CPS0/CCP4/SRI/INT/SEG0

VDD

VSS

RC7/RX/DT/P3B/SEG8

SEG9/P3A(1)/CCP3(1)/CK/TX/RC6

SEG10/SDO/RC5

SEG11/T1G(1)/SDA/SDI/RC4

RE3/MCLR/VPP

RA0/AN0/C12IN0-/C2OUT(1)/SRNQ(1)/SS(1)/VCAP(2)/SEG12

RA1/AN1/C12IN1-/SEG7

COM2/DACOUT/VREF-/C2IN+/AN2/RA2

SEG15/COM3/VREF+/C1IN+/AN3/RA3

SEG4/CCP5/SRQ/T0CKI/CPS6/C1OUT/RA4

SEG5(1)/VCAP(2)/SS(1)/SRNQ/CPS7/C2OUT(1)/AN4/RA5

VSS

SEG2/CLKIN/OSC1/RA7

SEG1/VCAP(2)/CLKOUT/OSC2/RA6

(1)P2A/(1)CCP2/T1OSI/RC1

SEG3/P1A/CCP1/RC2

SEG6/SCL/SCK/RC3

PIC16(L)F1936

PIC16LF1936

28-pin QFN/UQF N

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1936 devices only.

 2008-2011 Microchip Technology Inc. DS41364E-page 7

PIC16(L)F1934/6/7

TABLE 1: 28-PIN SUMMARY (PIC16(L)F1936)

I/O

28-Pin SP DIP

28-Pin QFN/UQFN

ANSEL

A/D

Cap Sense

Comparator

SR Latch

Timers

CCP

EUSART

MSSP

LCD

Interrupt

Pull-up

Basic

RA0 227 YAN0 —C12IN0-/

C2OUT(1) SRNQ(1) — — — SS(1) SEG12 — — VCAP(2)

RA1 3 28 Y AN1 — C12IN1- — — — — — SEG7 — — —

RA2 4 1 Y AN2/

VREF-

—C2IN+/

DACOUT

— — — — — COM2 — — —

RA3 5 2 Y AN3/

VREF+

— C1IN+ — — — — — SEG15/

COM3

—— —

RA4 6 3 Y — CPS6 C1OUT SRQ T0CKI CCP5 — — SEG4 — — —

RA5 7 4 Y AN4 CPS7 C2OUT(1) SRNQ(1) ———SS

(1) SEG5 — — VCAP(2)

RA6 10 7 — — — — — — — — — SEG1 — — OSC2/

CLKOUT

VCAP(2)

RA7 9 6 — — — — — — — — — SEG2 — — OSC1/

CLKIN

RB0 21 18 YAN12 CPS0 —SRI —CCP4 — — SEG0 INT/

IOC

Y —

RB1 22 19 Y AN10 CPS1 C12IN3- — — P1C — — VLCD1 IOC Y —

RB2 23 20 YAN8 CPS2 — — — P1B — — VLCD2 IOC Y —

RB3 24 21 Y AN9 CPS3 C12IN2- — — CCP2(1)/

P2A(1) — — VLCD3 IOC Y —

RB4 25 22 YAN11 CPS4 — — — P1D — — COM0 IOC Y —

RB5 26 23 Y AN13 CPS5 — — T1G(1) P2B(1)

CCP3(1)/

P3A(1)

——COM1IOCY —

RB6 27 24 — — — — — — — — — SEG14 IOC YICSPCLK/

ICDCLK

RB7 28 25 — — — — — — — — — SEG13 IOC Y ICSPDAT/

ICDDAT

RC0 11 8 — — — — — T1OSO/

T1CKI

P2B(1) — — — — — —

RC1 12 9 — — — — — T1OSI CCP2(1)/

P2A(1) —— ——— —

RC2 13 10 — — — — — — CCP1/

P1A

— — SEG3 — — —

RC3 14 11 — — — — — — — — SCK/SCL SEG6 — — —

RC4 15 12 — — — — — T1G(1) — — SDI/SDA SEG11 — — —

RC51613———— —— — —SDOSEG10—— —

RC6 17 14 — — — — — — CCP3(1)

P3A(1) TX/CK —SEG9 — — —

RC7 18 15 — — — — — — P3B RX/DT — SEG8 — — —

RE3126———— —— — —— ——YMCLR

/VPP

VDD 20 17 — — — — — — — — — — — — VDD

Vss 8,

———— —— — —— ——— VSS

Note 1: Pin functions can be moved using the APFCON register.

2: PIC16F1936 devices only.

PIC16(L)F1934/6/7

DS41364E-page 8  2008-2011 Microchip Technology Inc.

Pin Diagram – 40-Pin PDIP (PIC16(L)F1934/7)

40-Pin PDIP

PIC16F1934/7

PIC16LF1934/7

VPP/MCLR/RE3

SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0

SEG7/C12IN1-/AN1/RA1

COM2/DACOUT/VREF-/C2IN+/AN2/RA2

SEG15/VREF+/C1IN+/AN3/RA3

SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4

SEG5/VCAP(2)/SS(1)/SRNQ(1)/CPS7/C2OUT(1)/AN4/RA5

SEG21/CCP3(1)/P3A(1)/AN5/RE0

SEG22/P3B/AN6/RE1

SEG23/CCP5/AN7/RE2

RB6/ICSPCLK/ICDCLK/SEG14

RB5/AN13/CPS5/CCP3(1)/P3A(1)/T1G(1)/COM1

RB4/AN11/CPS4/COM0

RB3/AN9/C12IN2-/CPS3/CCP2(1)/P2A(1)/VLCD3

RB2/AN8/CPS2/VLCD2

RB1/AN10/C12IN3-/CPS1/VLCD1

RB0/AN12/CPS0/SRI/INT/SEG0

VDD

VSS

RD2/CPS10/P2B(1)

VDD

VSS

SEG2/CLKIN/OSC1/RA7

SEG1/VCAP(2)/CLKOUT/OSC2/RA6

P2B(1)/T1CKI/T1OSO/RC0

P2A(1)/CCP2(1)/T1OSI/RC1

SEG3/P1A/CCP1/RC2

SEG6/SCK/SCL/RC3

COM3/CPS8/RD0

CCP4/CPS9/RD1

RC5/SDO/SEG10

RC4/SDI/SDA/T1G(1)/SEG11

RD3/CPS11/P2C/SEG16

RD4/CPS12/P2D/SEG17

RC7/RX/DT/SEG8

RC6/TX/CK/SEG9

RD7/CPS15/P1D/SEG20

RD6/CPS14/P1C/SEG19

RD5/CPS13/P1B/SEG18

RB7/ICSPDAT/ICDDAT/SEG13

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/7 devices only.

 2008-2011 Microchip Technology Inc. DS41364E-page 9

PIC16(L)F1934/6/7

Pin Diagram – 40-Pin UQFN 5X5 (PIC16(L)F1934/7)

40-pin UQFN

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/7 devices only.

PIC16F1934/7

PIC16LF1934/7

SEG15/C1IN+/VREF+/AN3/RA3

COM2/DACOUT/C2IN+/VREF-/AN2/RA2

SEG7/C12IN1-/AN1/RA1

SEG12/SRNQ(1)/C2OUT(1)/C12IN0-/VCAP(2)/SS(1)/AN0/RA0

VPP/MCLR/RE3

SEG13/ICDDAT/ICSPDAT/RB7

SEG14/ICDCLK/ICSPCLK/RB6

COM1/T1G(1)/CCP3(1)/P3A(1)/CPS5/AN13/RB5

COM0/CPS4/AN11/RB4

VSS

VDD

SEG0/SRI/INT/CPS0/AN12/RB0

VLCD1/C12IN3-/CPS1/AN10/RB1

VLCD2/CPS2/AN8/RB2

VLCD3/P2A(1)/CCP2(1)/C12IN2-/CPS3/AN9/RB3

SEG8/DT/RX/RC7

SEG17/P2D/CPS12/RD4

SEG18/P1B/CPS13/RD5

SEG19/P1C/CPS14/RD6

SEG20/P1D/CPS15/RD7

RC6/TX/CK/SEG9

RC5/SDO/SEG10

RC4/SDI/SDA/T1G(1)/SEG11

RD3/CPS11/P2C/SEG16

RD2/CPS10/P2B(1)

RD1/CPS9/CCP4

RD0/CPS8/COM3

RC3/SCK/SCL/SEG6

RC2/CCP1/P1A/SEG3

RC1/T1OSI/CCP2(1)/P2A(1)

RC0/T1OSO/T1CKI/P2B

RA6/OSC2/CLKOUT/VCAP(2)/SEG1

RA7/OSC1/CLKIN/SEG2

VSS

VDD

RE2/AN7/CCP5/SEG23

RE1/AN6/P3B/SEG22

RE0/AN5/CCP3(1)/P3A(1)/SEG21

RA4/CPS6/T0CKI/C1OUT/SRQ/SEG4

RA5/AN4/CPS7/SS(1)/VCAP(2)/SRNQ(1)/C2OUT(1)/SEG5

PIC16(L)F1934/6/7

DS41364E-page 10  2008-2011 Microchip Technology Inc.

Pin Diagram – 44-Pin QFN (PIC16(L)F1934/7)

SEG7/C12IN1-/AN1/RA1

SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0

VPP/MCLR/RE3

VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3

SEG13/ICDDAT/ICSPDAT/RB7

SEG14/ICDCLK/ICSPCLK/RB6

COM1/T1G(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5

COM0/CPS4/AN11/RB4

NC RC6/TX/CK/SEG9

RC5/SDO/SEG10

RC4/SDI/SDA/T1G(1)/SEG11

RD3/CPS11/P2C/SEG16

RD2/CPS10/P2B(1)

RD1/CPS9/CCP4

RD0/CPS8/COM3

RC3/SCL/SCK/SEG6

RC2/CCP1/P1A/SEG3

RC1/T1OSI/CCP2(1)/P2A(1)

RC0/T1OSO/T1CKI/P2B(1)

RA6/OSC2/CLKOUT/VCAP(2)/SEG1

RA7/OSC1/CLKIN/SEG2

VSS

VDD

RE2/AN7/CCP5/SEG23

RE1/AN6/P3B/SEG22

RE0/AN5/CCP3(1)/P3A(1)/SEG21

RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5

RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4

SEG8/DT/RX/RC7

SEG17/P2D/CPS12/RD4

SEG18/P1B/CPS13/RD5

SEG19/P1C/CPS14/RD6

SEG20/P1D/CPS15/RD7

VSS

VDD

SEG0/INT/SRI/CPS0/AN12/RB0

VLCD1/CPS1/C12IN3-/AN10/RB1

VLCD2/CPS2/AN8/RB2

44-pin QFN

PIC16F1934/7

PIC16LF1934/7

SEG15VREF+/C1IN+/AN3/RA3

COM2/DACOUT/VREF-/C2IN+/AN2/RA2

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/7 devices only.

 2008-2011 Microchip Technology Inc. DS41364E-page 11

PIC16(L)F1934/6/7

Pin Diagram – 44-Pin TQFP (PIC16(L)F1934/7)

44-pin TQFP

SEG15/VREF+/C1IN+/AN3/RA3

COM2/DACOUT/VREF-/C2IN+/AN2/RA2

SEG7/C12IN1-/AN1/RA1

SEG12/VCAP(2)/SS(1)/SRNQ(1)/C2OUT(1)/C12IN0-/AN0/RA0

VPP/MCLR/RE3

SEG13/ICDDAT/ICSPDAT/RB7

SEG14/ICDCLK/ICSPCLK/RB6

COM1/T1G(1)/P3A(1)/CCP3(1)/CPS5/AN13/RB5

COM0/CPS4/AN11/RB4

RC0/T1OSO/T1CKI/P2B(1)

VSS

VDD

SEG0/INT/SRI/CPS0/AN12/RB0

VLCD1/CPS1/C12IN3-/AN10/RB1

VLCD2/CPS2/AN8/RB2

VLCD3/P2A(1)/CCP2(1)/CPS3/C12IN2-/AN9/RB3

4PIC16F1934/7

PIC16LF1934/7

RA6/OSC2/CLKOUT/VCAP(2)/SEG1

RA7/OSC1/CLKIN/SEG2

VSS

VDD

RE2/AN7/CCP5/SEG23

RE1/AN6/P3B/SEG22

RE0/AN5/CCP3(1)/P3A(1)/SEG21

RA5/AN4/C2OUT(1)/CPS7/SRNQ(1)/SS(1)/VCAP(2)/SEG5

RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4

SEG8/DT/RX/RC7

SEG17/P2D/CPS12/RD4

SEG18/P1B/CPS13/RD5

SEG19/P1C/CPS14/RD6

SEG20/P1D/CPS15/RD7

RC6/TX/CK/SEG9

RC5/SDO/SEG10

RC4/SDI/SDA/T1G(1)/SEG11

RD3/CPS11/P2C/SEG16

RD2/CPS10/P2B(1)

RD1/CPS9/CCP4

RD0/CPS8/COM3

RC3/SCL/SCK/SEG6

RC2/CCP1/P1A/SEG3

RC1/T1OSI/CCP2(1)/P2A(1)

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/7 devices only.

PIC16(L)F1934/6/7

DS41364E-page 12  2008-2011 Microchip Technology Inc.

TABLE 2: 40/44-PIN SUMMARY(PIC16(L)F1934/7)

I/O

40-Pin PDIP

40-Pin UQFN

44-Pin TQFP

44-Pin QFN

ANSEL

A/D

Cap Sense

Comparator

SR Lat ch

Timers

CCP

EUSART

MSSP

LCD

Interrupt

Pull-up

Basic

RA0 217 19 19 YAN0 —C12IN0-/

C2OUT(1) SRNQ(1) — — — SS(1) SEG12 — — VCAP

RA1 3 18 20 20 Y AN1 — C12IN1- — — — — — SEG7 — — —

RA2 419 21 21 YAN2/

VREF-

—C2IN+/

DACOUT

— — — — — COM2 — — —

RA3 5 20 22 22 Y AN3/

VREF+

—C1IN+ — — — — —SEG15—— —

RA4 621 23 23 Y — CPS6 C1OUT SRQ T0CKI — — SEG4 — — —

RA5 7 22 24 24 Y AN4 CPS7 C2OUT(1) SRNQ(1) ———SS

(1) SEG5 — — VCAP

RA6 14 29 31 33 — — — — — — — — — SEG1 — — OSC2/

CLKOUT

VCAP

RA713283032—————————SEG2——OSC1/

CLKIN

RB0 33 8 8 9 Y AN12 CPS0 —SRI — — — — SEG0 INT/

IOC

Y —

RB1 34 9 9 10 Y AN10 CPS1 C12IN3- — — — — — VLCD1 IOC Y —

RB2 35 10 10 11 YAN8 CPS2 — — — — — — VLCD2 IOC Y —

RB3 36 11 11 12 Y AN9 CPS3 C12IN2- — — CCP2(1)/

P2A(1) — — VLCD3 IOC Y —

RB4 37 12 14 14 YAN11 CPS4 — — — — — — COM0 IOC Y —

RB5 38 13 15 15 Y AN13 CPS5 — — T1G(1) CCP3(1)/

P3A(1) ——COM1IOCY—

RB6 39 14 16 16 — — — — — — — — — SEG14 IOC YICSPCLK/

ICDCLK

RB740151717—————————SEG13IOCYICSPDAT/

ICDDAT

RC0 15 30 32 34 — — — — — T1OSO/

T1CKI

P2B(1) — — — — — —

RC1 16 31 35 35 — — — — — T1OSI CCP2(1)/

P2A(1) ——————

RC2 17 32 36 36 — — — — — — CCP1/

P1A

— — SEG3 — — —

RC3 18 33 37 37 — — — — — — — — SCK/SCL SEG6 — — —

RC4 23 38 42 42 — — — — — T1G(1) — — SDI/SDA SEG11 — — —

RC5 24 39 43 43 — — — — — — — — SDO SEG10 — — —

RC6 25 40 44 44 — — — — — — — TX/CK —SEG9 — — —

RC7 26 1 1 1 — — — — — — — RX/DT — SEG8 — — —

RD0 19 34 38 38 Y — CPS8 — — — — — — COM3 — — —

RD1 20 35 39 39 Y — CPS9 — — — CCP4 — — — — — —

RD2 21 36 40 40 Y — CPS10 — — — P2B(1) — — — — — —

RD3 22 37 41 41 Y — CPS11 — — — P2C — — SEG16 — — —

RD4 27 2 2 2 Y — CPS12 — — — P2D — — SEG17 — — —

RD5 28 3 3 3 Y — CPS13 — — — P1B — — SEG18 — — —

RD6 29 4 4 4 Y — CPS14 — — — P1C — — SEG19 — — —

RD7 30 5 5 5 Y — CPS15 — — — P1D — — SEG20 — — —

RE0 823 25 25 YAN5 — — — — CCP3(1)

P3A(1) — — SEG21 — — —

RE1 9 24 26 26 Y AN6 — — — — P3B — — SEG22 — — —

RE2 10 25 27 27 YAN7 — — — — CCP5 — — SEG23 — — —

RE3 1 16 18 18 — — — — — — — — — — — Y MCLR/VPP

VDD 11,

7,8,

— — — — — — — — — — — — VDD

Vss 12,

6,30,

—— — — — — — — — — —— VSS

Note 1: Pin functions can be moved using the APFCON register.

 2008-2011 Microchip Technology Inc. DS41364E-page 13

PIC16(L)F1934/6/7

Table of Contents

1.0 Device Overview ........................................................................................................................................................................ 15

2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 23

3.0 Memory Organization ................................................................................................................................................................. 25

4.0 Device Configuration .................................................................................................................................................................. 61

5.0 Oscillator Module (With Fail-Safe Clock Monitor)....................................................................................................................... 67

6.0 Resets ........................................................................................................................................................................................ 85

7.0 Interrupts .................................................................................................................................................................................... 93

8.0 Low Dropout (LDO) Voltage Regulator .................................................................................................................................... 107

9.0 Power-Down Mode (Sleep) ...................................................................................................................................................... 109

10.0 Watchdog Timer (WDT) ........................................................................................................................................................... 111

11.0 Data EEPROM and Flash Program Memory Control ............................................................................................................... 115

12.0 I/O Ports ................................................................................................................................................................................... 129

13.0 Interrupt-On-Change ................................................................................................................................................................ 151

14.0 Fixed Voltage Reference.......................................................................................................................................................... 155

15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 157

16.0 Temperature Indicator Module ................................................................................................................................................. 171

17.0 Digital-to-Analog Converter (DAC) Module .............................................................................................................................. 173

18.0 Comparator Module.................................................................................................................................................................. 177

19.0 SR Latch................................................................................................................................................................................... 187

20.0 Timer0 Module ......................................................................................................................................................................... 191

21.0 Timer1 Module with Gate Control............................................................................................................................................. 197

22.0 Timer2/4/6 Modules.................................................................................................................................................................. 207

23.0 Capture/Compare/PWM Modules (ECCP1, ECCP2, ECCP3, CCP4, CCP5).......................................................................... 211

24.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 239

25.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 291

26.0 Capacitive Sensing Module...................................................................................................................................................... 319

27.0 Liquid Crystal Display (LCD) Driver Module............................................................................................................................. 327

28.0 In-Circuit Serial Programming™ (ICSP™) ............................................................................................................................... 361

29.0 Instruction Set Summary .......................................................................................................................................................... 365

30.0 Electrical Specifications............................................................................................................................................................ 379

31.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 411

32.0 Development Support............................................................................................................................................................... 439

33.0 Packaging Information.............................................................................................................................................................. 443

Appendix A: Data Sheet Revision History.......................................................................................................................................... 459

Appendix B: Migrating From Other PIC® Devices.............................................................................................................................. 459

Index .................................................................................................................................................................................................. 461

The Microchip Web Site..................................................................................................................................................................... 469

Customer Change Notification Service .............................................................................................................................................. 469

Customer Support .............................................................................................................................................................................. 469

Reader Response .............................................................................................................................................................................. 470

Product Identification System ............................................................................................................................................................ 471

PIC16(L)F1934/6/7

DS41364E-page 14  2008-2011 Microchip Technology Inc.

TO OUR VALUED CUSTOMERS

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enhanced as new volumes and updates are introduced.

If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via

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welcome your feedback.

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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page.

The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000).

Errata

An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current

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To determine if an errata sheet exists for a particular device, please check with one of the following:

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When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are

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Customer No tific atio n Syst em

 2008-2011 Microchip Technology Inc. DS41364E-page 15

PIC16(L)F1934/6/7

1.0 DEVICE OVERVIEW

The PIC16(L)F1934/6/7 are described within this data

sheet. They are available in 28/40/44-pin packages.

Figure 1-1 shows a block diagram of the

PIC16(L)F1934/6/7 devices. Ta bl e 1-2 shows the

pinout descriptions.

Reference Tab le 1-1 for peripherals available per

device.

TABLE 1-1: DEVICE PERIPHERAL

SUMMARY

Peripheral

PIC16F193X

PIC16LF193X

ADC ●●

Capacitive Sensing Module ●●

Digital-to-Analog Converter (DAC) ●●

EUSART ●●

Fixed Voltage Reference (FVR) ●●

LCD ●●

SR Latch ●●

Temperature Indicator ●●

Capture/Compare/PWM Modules

ECCP1 ●●

ECCP2 ●●

ECCP3 ●●

CCP4 ●●

CCP5 ●●

Comparators

C1 ●●

C2 ●●

Operational Amplifiers

OPA1 ●●

OPA2 ●●

Master Synchronous Serial Ports

MSSP1 ●●

Timers

Timer0 ●●

Timer1 ●●

Timer2 ●●

Timer4 ●●

Timer6 ●●

PIC16(L)F1934/6/7

DS41364E-page 16  2008-2011 Microchip Technology Inc.

FIGURE 1-1: PIC16(L)F1934/6/7 BLOCK DIAGRAM

PORTA

EUSART

Comparators

MSSP

Timer2Timer1 Timer4Timer0

ECCP1

ADC

10-Bit

ECCP2 ECCP3 CCP4 CCP5

Timer6

PORTB

PORTC

PORTD

PORTE

LCD

Latch

Note 1: See applicable chapters for more information on peripherals.

CPU

Program

Flash Memory

EEPROM

RAM

Timing

Generation

INTRC

Oscillator

MCLR

Figure 2-1

OSC1/CLKIN

OSC2/CLKOUT

 2008-2011 Microchip Technology Inc. DS41364E-page 17

PIC16(L)F1934/6/7

TABLE 1-2: PIC16(L)F1934/6/7 PINOUT DESCRIPTION

Name Function Input

Type Output

Type Description

RA0/AN0/C12IN0-/C2OUT(1)/

SRNQ(1)/SS(1)/VCAP(2)/SEG12

RA0 TTL CMOS General purpose I/O.

AN0 AN — A/D Channel 0 input.

C12IN0- AN — Comparator C1 or C2 negative input.

C2OUT — CMOS Comparator C2 output.

SRNQ — CMOS SR Latch inverting output.

SS ST — Slave Select input.

VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1934/6/7 only).

SEG12 — AN LCD Analog output.

RA1/AN1/C12IN1-/SEG7 RA1 TTL CMOS General purpose I/O.

AN1 AN — A/D Channel 1 input.

C12IN1- AN — Comparator C1 or C2 negative input.

SEG7 — AN LCD Analog output.

RA2/AN2/C2IN+/VREF-/

DACOUT/COM2

RA2 TTL CMOS General purpose I/O.

AN2 AN — A/D Channel 2 input.

C2IN+ AN — Comparator C2 positive input.

VREF- AN — A/D Negative Voltage Reference input.

DACOUT — AN Voltage Reference output.

COM2 — AN LCD Analog output.

RA3/AN3/C1IN+/VREF+/

COM3(3)/SEG15

RA3 TTL CMOS General purpose I/O.

AN3 AN — A/D Channel 3 input.

C1IN+ AN — Comparator C1 positive input.

VREF+ AN — A/D Voltage Reference input.

COM3(3) — AN LCD Analog output.

SEG15 — AN LCD Analog output.

RA4/C1OUT/CPS6/T0CKI/SRQ/

CCP5/SEG4

RA4 TTL CMOS General purpose I/O.

C1OUT — CMOS Comparator C1 output.

CPS6 AN — Capacitive sensing input 6.

T0CKI ST — Timer0 clock input.

SRQ —CMOS SR Latch non-inverting output.

CCP5 ST CMOS Capture/Compare/PWM5.

SEG4 — AN LCD Analog output.

RA5/AN4/C2OUT(1)/CPS7/

SRNQ(1)/SS(1)/VCAP(2)/SEG5

RA5 TTL CMOS General purpose I/O.

AN4 AN — A/D Channel 4 input.

C2OUT — CMOS Comparator C2 output.

CPS7 AN — Capacitive sensing input 7.

SRNQ — CMOS SR Latch inverting output.

SS ST — Slave Select input.

VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1934/6/7 only).

SEG5 — AN LCD Analog output.

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/6/7 devices only.

3: PIC16(L)F1936 devices only.

4: PORTD is available on PIC16(L)F1934/7 devices only.

5: RE<2:0> are available on PIC16(L)F1934/7 devices only.

PIC16(L)F1934/6/7

DS41364E-page 18  2008-2011 Microchip Technology Inc.

RA6/OSC2/CLKOUT/VCAP(2)/

SEG1

RA6 TTL CMOS General purpose I/O.

OSC2 — XTAL Crystal/Resonator (LP, XT, HS modes).

CLKOUT — CMOS FOSC/4 output.

VCAP Power Power Filter capacitor for Voltage Regulator (PIC16F1934/6/7 only).

SEG1 — AN LCD Analog output.

RA7/OSC1/CLKIN/SEG2 RA7 TTL CMOS General purpose I/O.

OSC1 XTAL — Crystal/Resonator (LP, XT, HS modes).

CLKIN CMOS — External clock input (EC mode).

SEG2 — AN LCD Analog output.

RB0/AN12/CPS0/CCP4/SRI/INT/

SEG0

RB0 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN12 AN — A/D Channel 12 input.

CPS0 AN — Capacitive sensing input 0.

CCP4 ST CMOS Capture/Compare/PWM4.

SRI — ST SR Latch input.

INT ST — External interrupt.

SEG0 — AN LCD analog output.

RB1/AN10/C12IN3-/CPS1/P1C/

VLCD1

RB1 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN10 AN — A/D Channel 10 input.

C12IN3- AN — Comparator C1 or C2 negative input.

CPS1 AN — Capacitive sensing input 1.

P1C — CMOS PWM output.

VLCD1 AN — LCD analog input.

RB2/AN8/CPS2/P1B/VLCD2 RB2 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN8 AN — A/D Channel 8 input.

CPS2 AN — Capacitive sensing input 2.

P1B — CMOS PWM output.

VLCD2 AN — LCD analog input.

RB3/AN9/C12IN2-/CPS3/

CCP2(1)/P2A(1)/VLCD3

RB3 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN9 AN — A/D Channel 9 input.

C12IN2- AN — Comparator C1 or C2 negative input.

CPS3 AN — Capacitive sensing input 3.

CCP2 ST CMOS Capture/Compare/PWM2.

P2A — CMOS PWM output.

VLCD3 AN — LCD analog input.

TABLE 1-2: PIC16(L)F1934/6/7 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/6/7 devices only.

3: PIC16(L)F1936 devices only.

4: PORTD is available on PIC16(L)F1934/7 devices only.

5: RE<2:0> are available on PIC16(L)F1934/7 devices only.

 2008-2011 Microchip Technology Inc. DS41364E-page 19

PIC16(L)F1934/6/7

RB4/AN11/CPS4/P1D/COM0 RB4 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN11 AN — A/D Channel 11 input.

CPS4 AN — Capacitive sensing input 4.

P1D — CMOS PWM output.

COM0 — AN LCD Analog output.

RB5/AN13/CPS5/P2B/CCP3(1)/

P3A(1)/T1G(1)/COM1

RB5 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

AN13 AN — A/D Channel 13 input.

CPS5 AN — Capacitive sensing input 5.

P2B — CMOS PWM output.

CCP3 ST CMOS Capture/Compare/PWM3.

P3A — CMOS PWM output.

T1G ST — Timer1 Gate input.

COM1 — AN LCD Analog output.

RB6/ICSPCLK/ICDCLK/SEG14 RB6 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPCLK ST — Serial Programming Clock.

ICDCLK ST — In-Circuit Debug Clock.

SEG14 — AN LCD Analog output.

RB7/ICSPDAT/ICDDAT/SEG13 RB7 TTL CMOS General purpose I/O. Individually controlled interrupt-on-change.

Individually enabled pull-up.

ICSPDAT ST CMOS ICSP™ Data I/O.

ICDDAT ST CMOS In-Circuit Data I/O.

SEG13 — AN LCD Analog output.

RC0/T1OSO/T1CKI/P2B(1) RC0 ST CMOS General purpose I/O.

T1OSO XTAL XTAL Timer1 oscillator connection.

T1CKI ST — Timer1 clock input.

P2B — CMOS PWM output.

RC1/T1OSI/CCP2(1)/P2A(1) RC1 ST CMOS General purpose I/O.

T1OSI XTAL XTAL Timer1 oscillator connection.

CCP2 ST CMOS Capture/Compare/PWM2.

P2A — CMOS PWM output.

RC2/CCP1/P1A/SEG3 RC2 ST CMOS General purpose I/O.

CCP1 ST CMOS Capture/Compare/PWM1.

P1A — CMOS PWM output.

SEG3 — AN LCD Analog output.

RC3/SCK/SCL/SEG6 RC3 ST CMOS General purpose I/O.

SCK ST CMOS SPI clock.

SCL I2CODI

2C™ clock.

SEG6 — AN LCD Analog output.

TABLE 1-2: PIC16(L)F1934/6/7 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/6/7 devices only.

3: PIC16(L)F1936 devices only.

4: PORTD is available on PIC16(L)F1934/7 devices only.

5: RE<2:0> are available on PIC16(L)F1934/7 devices only.

PIC16(L)F1934/6/7

DS41364E-page 20  2008-2011 Microchip Technology Inc.

RC4/SDI/SDA/T1G(1)/SEG11 RC4 ST CMOS General purpose I/O.

SDI ST — SPI data input.

SDA I2CODI

2C™ data input/output.

T1G ST — Timer1 Gate input.

SEG11 — AN LCD Analog output.

RC5/SDO/SEG10 RC5 ST CMOS General purpose I/O.

SDO — CMOS SPI data output.

SEG10 — AN LCD Analog output.

RC6/TX/CK/CCP3/P3A/SEG9 RC6 ST CMOS General purpose I/O.

TX — CMOS USART asynchronous transmit.

CK ST CMOS USART synchronous clock.

CCP3 ST CMOS Capture/Compare/PWM3.

P3A — CMOS PWM output.

SEG9 — AN LCD Analog output.

RC7/RX/DT/P3B/SEG8 RC7 ST CMOS General purpose I/O.

RX ST — USART asynchronous input.

DT ST CMOS USART synchronous data.

P3B — CMOS PWM output.

SEG8 — AN LCD Analog output.

RD0(4)/CPS8/COM3 RD0 ST CMOS General purpose I/O.

CPS8 AN — Capacitive sensing input 8.

COM3 — AN LCD analog output.

RD1(4)/CPS9/CCP4 RD1 ST CMOS General purpose I/O.

CPS9 AN — Capacitive sensing input 9.

CCP4 ST CMOS Capture/Compare/PWM4.

RD2(4)/CPS10/P2B RD2 ST CMOS General purpose I/O.

CPS10 AN — Capacitive sensing input 10.

P2B — CMOS PWM output.

RD3(4)/CPS11/P2C/SEG16 RD3 ST CMOS General purpose I/O.

CPS11 AN — Capacitive sensing input 11.

P2C — CMOS PWM output.

SEG16 — AN LCD analog output.

RD4(4)/CPS12/P2D/SEG17 RD4 ST CMOS General purpose I/O.

CPS12 AN — Capacitive sensing input 12.

P2D — CMOS PWM output.

SEG17 — AN LCD analog output.

RD5(4)/CPS13/P1B/SEG18 RD5 ST CMOS General purpose I/O.

CPS13 AN — Capacitive sensing input 13.

P1D — CMOS PWM output.

SEG18 — AN LCD analog output.

TABLE 1-2: PIC16(L)F1934/6/7 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/6/7 devices only.

3: PIC16(L)F1936 devices only.

4: PORTD is available on PIC16(L)F1934/7 devices only.

5: RE<2:0> are available on PIC16(L)F1934/7 devices only.

 2008-2011 Microchip Technology Inc. DS41364E-page 21

PIC16(L)F1934/6/7

RD6(4)/CPS14/P1C/SEG19 RD6 ST CMOS General purpose I/O.

CPS14 AN — Capacitive sensing input 14.

P1C — CMOS PWM output.

SEG19 — AN LCD analog output.

RD7(4)/CPS15/P1D/SEG20 RD7 ST CMOS General purpose I/O.

CPS15 AN — Capacitive sensing input 15.

P1D — CMOS PWM output.

SEG20 — AN LCD analog output.

RE0(5)/AN5/P3A(1)/CCP3(1)/

SEG21

RE0 ST CMOS General purpose I/O.

AN5 AN — A/D Channel 5 input.

P3A — CMOS PWM output.

CCP3 ST CMOS Capture/Compare/PWM3.

SEG21 — AN LCD analog output.

RE1(5)/AN6/P3B/SEG22 RE1 ST CMOS General purpose I/O.

AN6 AN — A/D Channel 6 input.

P3B — CMOS PWM output.

SEG22 — AN LCD analog output.

RE2(5)/AN7/CCP5/SEG23 RE2 ST CMOS General purpose I/O.

AN7 AN — A/D Channel 7 input.

CCP5 ST CMOS Capture/Compare/PWM5.

SEG23 — AN LCD analog output.

RE3/MCLR/VPP RE3 TTL — General purpose input.

MCLR ST — Master Clear with internal pull-up.

VPP HV — Programming voltage.

VDD VDD Power — Positive supply.

VSS VSS Power — Ground reference.

TABLE 1-2: PIC16(L)F1934/6/7 PINOUT DESCRIPTION (CONTINUED)

Name Function Input

Type Output

Type Description

Legend: AN = Analog input or output CMOS = CMOS compatible input or output OD = Open Drain

TTL = TTL compatible input ST = Schmitt Trigger input with CMOS levels I2C™ = Schmitt Trigger input with I2C

HV = High Voltage XTAL = Crystal levels

Note 1: Pin function is selectable via the APFCON register.

2: PIC16F1934/6/7 devices only.

3: PIC16(L)F1936 devices only.

4: PORTD is available on PIC16(L)F1934/7 devices only.

5: RE<2:0> are available on PIC16(L)F1934/7 devices only.

PIC16(L)F1934/6/7

DS41364E-page 22  2008-2011 Microchip Technology Inc.

NOTES:

 2008-2011 Microchip Technology Inc. DS41364E-page 23

PIC16(L)F1934/6/7

2.0 ENHANCED MID-RANGE CPU

This family of devices contain an enhanced mid-range

8-bit CPU core. The CPU has 49 instructions. Interrupt

capability includes automatic context saving. The

hardware stack is 16 levels deep and has Overflow and

Underflow Reset capability. Direct, Indirect, and

Relative Addressing modes are available. Two File

Select Registers (FSRs) provide the ability to read

program and data memory.

• Automatic Interrupt Context Saving

• 16-level Stack with Overflow and Underflow

• File Select Registers

• Instruction Set

2.1 Automatic Interrupt Context

Saving

During interrupts, certain registers are automatically

saved in shadow registers and restored when returning

from the interrupt. This saves stack space and user

code. See Section 7.5 “Automatic Context Saving”,

for more information.

2.2 16-level Stack with Overflow and

Underflow

These devices have an external stack memory 15 bits

wide and 16 words deep. A Stack Overflow or Under-

flow will set the appropriate bit (STKOVF or STKUNF)

in the PCON register, and if enabled will cause a soft-

ware Reset. See section Section 3.4 “St ack” for more

details.

2.3 File Select Registers

There are two 16-bit File Select Registers (FSR). FSRs

can access all file registers and program memory,

which allows one Data Pointer for all memory. When an

FSR points to program memory, there is 1 additional

instruction cycle in instructions using INDF to allow the

data to be fetched. General purpose memory can now

also be addressed linearly, providing the ability to

access contiguous data larger than 80 bytes. There are

also new instructions to support the FSRs. See

Section 3.5 “Indirect Addressing” for more details.

2.4 Instruction Set

There are 49 instructions for the enhanced mid-range

CPU to support the features of the CPU. See

Section 29.0 “Instruction Set Summary” for more

details.

PIC16(L)F1934/6/7

DS41364E-page 24  2008-2011 Microchip Technology Inc.

FIGURE 2-1: CORE BLOCK DIAGRAM

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

Power-up

Timer

Oscillator

Start-up Timer

Power-on

Reset

Watchdog

Timer

Instruction

Decode &

Control

Timing

Generation

OSC1/CLKIN

OSC2/CLKOUT

VDD

Brown-out

Reset

VSS

Internal

Oscillator

Block

Configuration

Data Bus 8

Program

Bus

Instruction reg

Program Counter

8 Level Stack

(13-bit)

Direct Addr 7

Addr MUX

FSR reg

STATUS reg

MUX

ALU

W reg

Instruction

Decode &

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

15 Data Bus 8

Program

Bus

Instruction Reg

Program Counter

16-Level Stack

(15-bit)

Direct Addr 7

RAM Addr

Addr MUX

Indirect

Addr

FSR0 Reg

STATUS Reg

MUX

ALU

Instruction

Decode and

Control

Timing

Generation

VDD

VSS

Internal

Oscillator

Block

Configuration

Flash

Program

Memory RAM

FSR regFSR reg

FSR1 Reg

MUX

Program Memory

Read (PMR)

 2008-2011 Microchip Technology Inc. DS41364E-page 25

PIC16(L)F1934/6/7

3.0 MEMORY ORGANIZATION

There are three types of memory in PIC16(L)F1934/6/7

devices: Data Memory, Program Memory and Data

EEPROM Memory(1).

• Program Memory

• Data Memory

- Core Registers

- Special Function Registers

- General Purpose RAM

- Common RAM

- Device Memory Maps

- Special Function Registers Summary

• Data EEPROM memory(1)

The following features are associated with access and

control of program memory and data memory:

• PCL and PCLATH

•Stack

• Indirect Addressing

3.1 Program Memory Organization

The enhanced mid-range core has a 15-bit program

counter capable of addressing 32K x 14 program

memory space. Table 3-1 shows the memory sizes

implemented for the PIC16(L)F1934/6/7 family.

Accessing a location above these boundaries will cause

a wrap-around within the implemented memory space.

The Reset vector is at 0000h and the interrupt vector is

at 0004h (see Figures 3-1 and 3-2).

Note 1: The data EEPROM memory and the

method to access Flash memory through

the EECON registers is described in

Section 1 1.0 “Dat a EEPROM and Flash

Program Memory Control”.

TABLE 3-1: DEVICE SIZES AND ADDRESSES

Device Program Memory Space (Words) Last Program Memory Address

PIC16F1934/PIC16LF1934 4,096 0FFFh

PIC16F1936/PIC16LF1936 8,192 1FFFh

PIC16F1937/PIC16LF1937 8,192 1FFFh

PIC16(L)F1934/6/7

DS41364E-page 26  2008-2011 Microchip Technology Inc.

FIGURE 3-1: PROGRAM MEMORY MAP

AND STACK FOR

4KW PARTS

FIGURE 3-2: PROGRAM MEMORY MAP

AND STACK FOR

8KW PARTS

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

CALL, CALLW

RETURN, RETLW

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 1

Interrupt, RETFIE

PC<14:0>

0000h

0004h

Stack Level 0

Stack Level 15

Reset Vector

Interrupt Vector

Stack Level 1

0005h

On-chip

Program

Memory

Page 0

07FFh

Rollover to Page 0

0800h

0FFFh

1000h

7FFFh

Page 1

Rollover to Page 3

Page 2

Page 3

17FFh

1800h

1FFFh

2000h

CALL, CALLW

RETURN, RETLW

Interrupt, RETFIE

 2008-2011 Microchip Technology Inc. DS41364E-page 27

PIC16(L)F1934/6/7

3.1.1 READING PROGRAM MEMORY AS

DATA

There are two methods of accessing constants in pro-

gram memory. The first method is to use tables of

RETLW instructions. The second method is to set an

FSR to point to the program memory.

3.1.1.1 RETLW Instruction

The RETLW instruction can be used to provide access

to tables of constants. The recommended way to create

such a table is shown in Example 3-1.

EXAMPL E 3-1: RETLW INSTRUCTION

The BRW instruction makes this type of table very sim-

ple to implement. If your code must remain portable

with previous generations of microcontrollers, then the

BRW instruction is not available so the older table read

method must be used.

constants

BRW ;Add Index in W to

;program counter to

;select data

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW DATA_INDEX

call constants

;… THE CONSTANT IS IN W

PIC16(L)F1934/6/7

DS41364E-page 28  2008-2011 Microchip Technology Inc.

3.1.1.2 Indirect Read with FSR

The program memory can be accessed as data by set-

ting bit 7 of the FSRxH register and reading the match-

ing INDFx register. The MOVIW instruction will place the

lower 8 bits of the addressed word in the W register.

Writes to the program memory cannot be performed via

the INDF registers. Instructions that access the pro-

gram memory via the FSR require one extra instruction

cycle to complete. Example 3-2 demonstrates access-

ing the program memory via an FSR.

The HIGH directive will set bit<7> if a label points to a

location in program memory.

EXAMPLE 3-2: ACCESSING PROGRAM

MEMORY VIA FSR

3.2 Data Memor y Organization

The data memory is partitioned in 32 memory banks

with 128 bytes in a bank. Each bank consists of

(Figure 3-3):

• 12 core registers

• 20 Special Function Registers (SFR)

• Up to 80 bytes of General Purpose RAM (GPR)

• 16 bytes of common RAM

The active bank is selected by writing the bank number

into the Bank Select Register (BSR). Unimplemented

memory will read as ‘0’. All data memory can be

accessed either directly (via instructions that use the

file registers) or indirectly via the two File Select

Registers (FSR). See Section 3.5 “Indirect

Addressing” for more information.

3.2.1 CORE REGISTERS

The core registers contain the registers that directly

affect the basic operation of the PIC16(L)F1934/6/7.

These registers are listed below:

• INDF0

• INDF1

•PCL

•STATUS

•FSR0 Low

• FSR0 High

•FSR1 Low

• FSR1 High

• BSR

•WREG

•PCLATH

• INTCON

constants

RETLW DATA0 ;Index0 data

RETLW DATA1 ;Index1 data

RETLW DATA2

RETLW DATA3

my_function

;… LOTS OF CODE…

MOVLW LOW constants

MOVWF FSR1L

MOVLW HIGH constants

MOVWF FSR1H

MOVIW 0[FSR1]

;THE PROGRAM MEMORY IS IN W

Note: The core registers are the first 12

addresses of every data memory bank.

 2008-2011 Microchip Technology Inc. DS41364E-page 29

PIC16(L)F1934/6/7

3.2.1.1 STATUS Register

The STATUS register, shown in Register 3-1, contains:

• the arithmetic status of the ALU

• the Reset status

The STATUS register can be the destination for any

instruction, like any other register. If the STATUS

the Z, DC or C bits, then the write to these three bits is

disabled. These bits are set or cleared according to the

device logic. Furthermore, the TO and PD bits are not

writable. Therefore, the result of an instruction with the

STATUS register as destination may be different than

intended.

For example, CLRF STATUS will clear the upper three

bits and set the Z bit. This leaves the STATUS register

as ‘000u u1uu’ (where u = unchanged).

It is recommended, therefore, that only BCF, BSF,

SWAPF and MOVWF instructions are used to alter the

STATUS register, because these instructions do not

affect any Status bits. For other instructions not

affecting any Status bits (Refer to Section 29.0

“Instruction Set Summary”).

Note 1: The C and DC bits operate as Borrow

and Digit Borrow out bits, respectively, in

subtraction.

U-0 U-0 U-0 R-1/q R-1/q R/W-0/u R/W-0/u R/W-0/u

— — — TO PD ZDC

(1) C(1)

bit 7 bit 0

Legend:

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’

u = Bit is unchanged x = Bit is unknown -n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set ‘0’ = Bit is cleared q = Value depends on condition

bit 7-5 Unimplemented: Read as ‘0’

bit 4 TO: Time-out bit

1 = After power-up, CLRWDT instruction or SLEEP instruction

0 = A WDT time-out occurred

bit 3 PD: Power-down bit

1 = After power-up or by the CLRWDT instruction

0 = By execution of the SLEEP instruction

bit 2 Z: Zero bit

1 = The result of an arithmetic or logic operation is zero

0 = The result of an arithmetic or logic operation is not zero

bit 1 DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1)

1 = A carry-out from the 4th low-order bit of the result occurred

0 = No carry-out from the 4th low-order bit of the result

bit 0 C: Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)

1 = A carry-out from the Most Significant bit of the result occurred

0 = No carry-out from the Most Significant bit of the result occurred

Note 1: For Borrow, the polarity is reversed. A subtraction is executed by adding the two’s complement of the

second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order

bit of the source register.

PIC16(L)F1934/6/7

DS41364E-page 30  2008-2011 Microchip Technology Inc.

3.2.2 SPECIAL FUNCTION REGISTER

The Special Function Registers (SFR) are registers

used by the application to control the desired operation

of peripheral functions in the device. The registers

associated with the operation of the peripherals are

described in the appropriate peripheral chapter of this

data sheet.

3.2.3 GENERAL PURPOSE RAM

There are up to 80 bytes of GPR in each data memory

bank.

3.2.3.1 Linear Access to GPR

The general purpose RAM can be accessed in a

non-banked method via the FSRs. This can simplify

access to large memory structures. See Section 3.5.2

“Linear Data Memory” for more information.

3.2.4 COMMON RAM

There are 16 bytes of common RAM accessible from all

banks.

FIGURE 3-3: BANKED MEM ORY

PARTITIONING

3.2.5 DEVICE MEMORY MAPS

The memory maps for the device family are as shown

in Table 3-2.

0Bh

0Ch

1Fh

20h

6Fh

70h

7Fh

00h

Common RAM

(16 bytes)

General Purpose RAM

(80 bytes maximum)

Core Registers

(12 bytes)

Special Function Registers

(20 bytes maximum)

Memory Region

7-bit Bank Offset

TABLE 3-2: MEMORY MAP TABLES

Device Banks Table No.

PIC16F1934

PIC16LF1934

0-7 Table 3-3

8-15 Tabl e 3 - 4 ,Tab l e 3 -1 0

16-23 Table 3-7

23-31 Table 3-8, Ta b le 3 - 11

PIC16F1936

PIC16LF1936

0-7 Table 3-5

8-15 Table 3-6, Tabl e 3- 9

16-23 Table 3-7

23-31 Table 3-8, Ta b le 3 - 11

PIC16F1937

PIC16LF1937

0-7 Table 3-5

8-15 Tabl e 3-6, Table 3-10

16-23 Table 3-7

23-31 Table 3-8, Ta b le 3 - 11

PIC16(L)F1934/6/7

DS41364E-page 31  2008-2011 Microchip Technology Inc.

TABLE 3-3: PIC16(L)F1934 MEMORY MAP, BANKS 0-7

Legend: = Unimplemented data memory locations, read as ‘0’.

Note 1: Not available on PIC16(L)F1936.

BANK 0 BANK 1 BANK 2 BANK 3 BANK 4 BANK 5 BANK 6 BANK 7

000h INDF0 080h INDF0 100h INDF0 180h INDF0 200h INDF0 280h INDF0 300h INDF0 380h INDF0

001h INDF1 081h INDF1 101h INDF1 181h INDF1 201h INDF1 281h INDF1 301h INDF1 381h INDF1

002h PCL 082h PCL 102h PCL 182h PCL 202h PCL 282h PCL 302h PCL 382h PCL

003h STATUS 083h STATUS 103h STATUS 183h STATUS 203h STATUS 283h STATUS 303h STATUS 383h STATUS

004h FSR0L 084h FSR0L 104h FSR0L 184h FSR0L 204h FSR0L 284h FSR0L 304h FSR0L 384h FSR0L

005h FSR0H 085h FSR0H 105h FSR0H 185h FSR0H 205h FSR0H 285h FSR0H 305h FSR0H 385h FSR0H

006h FSR1L 086h FSR1L 106h FSR1L 186h FSR1L 206h FSR1L 286h FSR1L 306h FSR1L 386h FSR1L

007h FSR1H 087h FSR1H 107h FSR1H 187h FSR1H 207h FSR1H 287h FSR1H 307h FSR1H 387h FSR1H

008h BSR 088h BSR 108h BSR 188h BSR 208h BSR 288h BSR 308h BSR 388h BSR

009h WREG 089h WREG 109h WREG 189h WREG 209h WREG 289h WREG 309h WREG 389h WREG

00Ah PCLATH 08Ah PCLATH 10Ah PCLATH 18Ah PCLATH 20Ah PCLATH 28Ah PCLATH 30Ah PCLATH 38Ah PCLATH

00Bh INTCON 08Bh INTCON 10Bh INTCON 18Bh INTCON 20Bh INTCON 28Bh INTCON 30Bh INTCON 38Bh INTCON

00Ch PORTA 08Ch TRISA 10Ch LATA 18Ch ANSELA 20Ch — 28Ch — 30Ch — 38Ch —

00Dh PORTB 08Dh TRISB 10Dh LATB 18Dh ANSELB 20Dh WPUB 28Dh — 30Dh — 38Dh —

00Eh PORTC 08Eh TRISC 10Eh LATC 18Eh —20Eh—28Eh—30Eh—38Eh—

00Fh PORTD(1) 08Fh TRISD(1) 10Fh LATD(1) 18Fh ANSELD(1) 20Fh —28Fh—30Fh—38Fh—

010h PORTE 090h TRISE 110h LATE(1) 190h ANSELE(1) 210h WPUE 290h — 310h — 390h —

011h PIR1 091h PIE1 111h CM1CON0 191h EEADRL 211h SSPBUF 291h CCPR1L 311h CCPR3L 391h —

012h PIR2 092h PIE2 112h CM1CON1 192h EEADRH 212h SSPADD 292h CCPR1H 312h CCPR3H 392h —

013h PIR3 093h PIE3 113h CM2CON0 193h EEDATL 213h SSPMSK 293h CCP1CON 313h CCP3CON 393h —

014h —094h— 114h CM2CON1 194h EEDATH 214h SSPSTAT 294h PWM1CON 314h PWM3CON 394h IOCBP

015h TMR0 095h OPTION_REG 115h CMOUT 195h EECON1 215h SSPCON1 295h CCP1AS 315h CCP3AS 395h IOCBN

016h TMR1L 096h PCON 116h BORCON 196h EECON2 216h SSPCON2 296h PSTR1CON 316h PSTR3CON 396h IOCBF

017h TMR1H 097h WDTCON 117h FVRCON 197h — 217h SSPCON3 297h — 317h — 397h —

018h T1CON 098h OSCTUNE 118h DACCON0 198h —218h— 298h CCPR2L 318h CCPR4L 398h —

019h T1GCON 099h OSCCON 119h DACCON1 199h RCREG 219h — 299h CCPR2H 319h CCPR4H 399h —

01Ah TMR2 09Ah OSCSTAT 11Ah SRCON0 19Ah TXREG 21Ah — 29Ah CCP2CON 31Ah CCP4CON 39Ah —

01Bh PR2 09Bh ADRESL 11Bh SRCON1 19Bh SPBRGL 21Bh — 29Bh PWM2CON 31Bh —39Bh—

01Ch T2CON 09Ch ADRESH 11Ch — 19Ch SPBRGH 21Ch — 29Ch CCP2AS 31Ch CCPR5L 39Ch —

01Dh — 09Dh ADCON0 11Dh APFCON 19Dh RCSTA 21Dh — 29Dh PSTR2CON 31Dh CCPR5H 39Dh —

01Eh CPSCON0 09Eh ADCON1 11Eh — 19Eh TXSTA 21Eh — 29Eh CCPTMRS0 31Eh CCP5CON 39Eh —

01Fh CPSCON1 09Fh —11Fh— 19Fh BAUDCTR 21Fh — 29Fh CCPTMRS1 31Fh —39Fh—

020h

General

Purpose

96 Bytes

0A0h

General

Purpose

80 Bytes

120h

General

Purpose

80 Bytes

1A0h

Unimplemented

Read as ‘0’

220h

Unimplemented

Read as ‘0’

2A0h

Unimplemented

Read as ‘0’

320h

Unimplemented

Read as ‘0’

3A0h

Unimplemented

Read as ‘0’

06Fh 0EFh 16Fh 1EFh 26Fh 2EFh 36Fh 3EFh

070h 0F0h

Accesses

70h – 7Fh

170h

Accesses

70h – 7Fh

1F0h

Accesses

70h – 7Fh

270h

Accesses

70h – 7Fh

2F0h

Accesses

70h – 7Fh

370h

Accesses

70h – 7Fh

3F0h

Accesses

70h – 7Fh

07Fh 0FFh 17Fh 1FFh 27Fh 2FFh 37Fh 3FFh

PIC16(L)F1934/6/7

DS41364E-page 32  2008-2011 Microchip Technology Inc.

TABLE 3-4: PIC16(L)F1934 MEMORY MAP, BANKS 8-15

Legend: = Unimplemented data memory locations, read as ‘0’.

BANK 8 BANK 9 BANK 10 BANK 11 BANK 12 BANK 13 BANK 14 BANK 15

400h INDF0 480h INDF0 500h INDF0 580h INDF0 600h INDF0 680h INDF0 700h INDF0 780h INDF0

401h INDF1 481h INDF1 501h INDF1 581h INDF1 601h INDF1 681h INDF1 701h INDF1 781h INDF1

402h PCL 482h PCL 502h PCL 582h PCL 602h PCL 682h PCL 702h PCL 782h PCL

403h STATUS 483h STATUS 503h STATUS 583h STATUS 603h STATUS 683h STATUS 703h STATUS 783h STATUS

404h FSR0L 484h FSR0L 504h FSR0L 584h FSR0L 604h FSR0L 684h FSR0L 704h FSR0L 784h FSR0L

405h FSR0H 485h FSR0H 505h FSR0H 585h FSR0H 605h FSR0H 685h FSR0H 705h FSR0H 785h FSR0H

406h FSR1L 486h FSR1L 506h FSR1L 586h FSR1L 606h FSR1L 686h FSR1L 706h FSR1L 786h FSR1L

407h FSR1H 487h FSR1H 507h FSR1H 587h FSR1H 607h FSR1H 687h FSR1H 707h FSR1H 787h FSR1H

408h BSR 488h BSR 508h BSR 588h BSR 608h BSR 688h BSR 708h BSR 788h BSR

409h WREG 489h WREG 509h WREG 589h WREG 609h WREG 689h WREG 709h WREG 789h WREG

40Ah PCLATH 48Ah PCLATH 50Ah PCLATH 58Ah PCLATH 60Ah PCLATH 68Ah PCLATH 70Ah PCLATH 78Ah PCLATH

40Bh INTCON 48Bh INTCON 50Bh INTCON 58Bh INTCON 60Bh INTCON 68Bh INTCON 70Bh INTCON 78Bh INTCON

40Ch —48Ch —50Ch —58Ch —60Ch —68Ch —70Ch —78Ch —

40Dh —48Dh —50Dh —58Dh —60Dh —68Dh —70Dh —78Dh —

40Eh —48Eh —50Eh —58Eh —60Eh —68Eh —70Eh —78Eh —

40Fh —48Fh —50Fh —58Fh —60Fh —68Fh —70Fh —78Fh —

410h —490h —510h —590h —610h —690h —710h —790h —

411h —491h —511h —591h —611h —691h —711h —791h

See Ta bl e 3 - 9 or

Tab l e 3 -1 0

412h —492h —512h —592h —612h —692h —712h —792h

413h —493h —513h —593h —613h —693h —713h —793h

414h —494h —514h —594h —614h —694h —714h —794h

415h TMR4 495h —515h —595h —615h —695h —715h —795h

416h PR4 496h —516h —596h —616h —696h —716h —796h

417h T4CON 497h —517h —597h —617h —697h —717h —797h

418h —498h —518h —598h —618h —698h —718h —798h

419h —499h —519h —599h —619h —699h —719h —799h

41Ah —49Ah —51Ah —59Ah —61Ah —69Ah —71Ah —79Ah

41Bh —49Bh —51Bh —59Bh —61Bh —69Bh —71Bh —79Bh

41Ch TMR6 49Ch —51Ch —59Ch —61Ch —69Ch —71Ch —79Ch

41Dh PR6 49Dh —51Dh —59Dh —61Dh —69Dh —71Dh —79Dh

41Eh T6CON 49Eh —51Eh —59Eh —61Eh —69Eh —71Eh —79Eh

41Fh —49Fh —51Fh —59Fh —61Fh —69Fh —71Fh —79Fh

420h

Unimplemented

Read as ‘0’

4A0h

Unimplemented

Read as ‘0’

520h

Unimplemented

Read as ‘0’

5A0h

Unimplemented

Read as ‘0’

620h

Unimplemented

Read as ‘0’

6A0h

Unimplemented

Read as ‘0’

720h

Unimplemented

Read as ‘0’

7A0h

46Fh 4EFh 56Fh 5EFh 66Fh 6EFh 76Fh 7EFh

470h

Accesses

70h – 7Fh

4F0h

Accesses

70h – 7Fh

570h

Accesses

70h – 7Fh

5F0h

Accesses

70h – 7Fh

670h

Accesses

70h – 7Fh

6F0h

Accesses

70h – 7Fh

770h

Accesses

70h – 7Fh

7F0h

Accesses

70h – 7Fh

47Fh 4FFh 57Fh 5FFh 67Fh 6FFh 77Fh 7FFh

PIC16(L)F1934/6/7

DS41364E-page 33  2008-2011 Microchip Technology Inc.

TABLE 3-5: PIC16(L)F1936/1937 MEMORY MAP, BANKS 0-7