March 2004 AS7C31024B (R) 3.3V 128K X 8 CMOS SRAM Features * Easy memory expansion with CE1, CE2, OE inputs * TTL/LVTTL-compatible, three-state I/O * 32-pin JEDEC standard packages * Industrial and commercial temperatures * Organization: 131,072 words x 8 bits * High speed - 10/12/15/20 ns address access time - 5, 6, 7, 8 ns output enable access time * Low power consumption: ACTIVE - - 252 mW / max @ 10 ns 300 mil SOJ 400 mil SOJ 8 x 20mm TSOP 1 8 x 13.4mm sTSOP 1 * ESD protection 2000 volts * Latch-up current 200 mA * Low power consumption: STANDBY - 18 mW / max CMOS * 6T 0.18u CMOS technology Pin arrangement NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND VCC GND 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC A15 CE2 WE A13 A8 A9 A11 OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 32-pin (8 x 20mm) TSOP I 32-pin (8 x 13.4mm) sTSOP1 I/O0 A11 A9 A8 A13 WE CE2 A15 VCC NC A16 A14 A12 A7 A6 A5 A4 WE OE CE1 CE2 Control circuit A9 A10 A11 A12 A13 A14 A15 A16 Column decoder I/O7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C31024B 512 x 256 x 8 Array (1,048,576) Sense amp A0 A1 A2 A3 A4 A5 A6 A7 A8 Row decoder Input buffer 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 AS7C31024B 32-pin SOJ (300 mil) 32-pin SOJ (400 mil) Logic block diagram OE A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A0 A1 A2 A3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Selection guide Maximum address access time -10 -12 -15 -20 Unit 10 12 15 20 ns Maximum output enable access time 5 6 7 8 ns Maximum operating current 70 65 60 55 mA Maximum CMOS standby current 5 5 5 5 mA 3/24/04, v.1.2 Alliance Semiconductor P. 1 of 9 Copyright (c) 2003 Alliance Semiconductor. All rights reserved. AS7C31024B (R) Functional description The AS7C31024B is a high performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high performance applications. Active high and low chip enables (CE1, CE2) permit easy memory expansion with multiple-bank systems. When CE1 is high or CE2 is low, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C31024B is guaranteed not to exceed 18 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and both chip enables (CE1, CE2). Data on the input pins I/O0 through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2). To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write enable is active, output drivers stay in high-impedance mode. Absolute maximum ratings Symbol Min Max Unit Voltage on VCC relative to GND Parameter Vt1 -0.50 +5.0 V Voltage on any pin relative to GND Vt2 -0.50 VCC +0.50 V Power dissipation PD - 1.0 W Storage temperature (plastic) Tstg -65 +150 C Ambient temperature with VCC applied Tbias -55 +125 C DC current into outputs (low) IOUT - 20 mA Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Truth table CE1 CE2 WE OE Data Mode H X X X High Z Standby (ISB, ISB1) X L X X High Z Standby (ISB, ISB1) L H H H High Z Output disable (ICC) L H H L DOUT Read (ICC) L H L X DIN Write (ICC) Key: X = don't care, L = low, H = high 3/24/04, v.1.2 Alliance Semiconductor P. 2 of 9 AS7C31024B (R) Recommended operating conditions Parameter Symbol Min Nominal Max Unit Supply voltage VCC 3.0 3.3 3.6 V Input voltage VIH 2.0 - VCC + 0.5 V VIL -0.5 - 0.8 V TA 0 - 70 C Ambient operating temperature commercial VIL = -1.0V for pulse width less than 5ns VIH = VCC + 1.5V for pulse width less than 5ns DC operating characteristics (over the operating range)1 -10 Parameter -12 -15 -20 Unit Sym Test conditions Min Max Min Max Min Max Min Max Input leakage current |ILI| VCC = Max, VIN = GND to VCC - 1 - 1 - 1 - 1 A Output leakage current |ILO| VCC = Max, CE1 = VIH or CE2 = VIL, VOUT = GND to VCC - 1 - 1 - 1 - 1 A Operating power supply current ICC VCC = Max, CE1 VIL, CE2 VIH, f = fMax, IOUT = 0 mA - 70 - 65 - 60 - 55 mA ISB VCC = Max, CE1 VIH and/or CE2 VIL, f = fMax - 30 - 25 - 20 - 20 ISB1 VCC = Max, CE1 VCC-0.2V and/ or CE2 0.2V VIN 0.2V or VIN VCC -0.2V, f = 0 - 5 - 5 - 5 - 5 VOL IOL = 8 mA, VCC = Min - 0.4 - 0.4 - 0.4 - 0.4 V VOH IOH = -4 mA, VCC = Min 2.4 - 2.4 - 2.4 - 2.4 - V Standby power supply current Output voltage mA Capacitance (f = 1 MHz, Ta = 25 C, VCC = NOMINAL)2 Parameter Symbol Signals Test conditions Max Unit Input capacitance CIN A, CE1, CE2, WE, OE VIN = 0V 5 pF I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF 3/24/04, v.1.2 Alliance Semiconductor P. 3 of 9 AS7C31024B (R) Read cycle (over the operating range)3,9,12 -10 Parameter Symbol Min Read cycle time Address access time -12 -15 -20 Max Min Max Min Max Min tRC 10 - 12 - 15 - 20 Max Unit Notes ns tAA - 10 - 12 - 15 - 20 ns 3 Chip enable (CE1) access time tACE1 - 10 - 12 - 15 - 20 ns 3, 12 Chip enable (CE2) access time tACE2 - 10 - 12 - 15 - 20 ns 3, 12 Output enable (OE) access time tOE - 5 - 6 - 7 - 8 ns tOH 3 - 3 - 3 - 3 - ns 5 CE1 low to output in low Z Output hold from address change tCLZ1 3 - 3 - 3 - 3 - ns 4, 5, 12 CE2 high to output in low Z tCLZ2 3 - 3 - 3 - 3 - ns 4, 5, 12 CE1 high to output in high Z tCHZ1 - 3 - 3 - 4 - 5 ns 4, 5, 12 CE2 low to output in high Z tCHZ2 - 3 - 3 - 4 - 5 ns 4, 5, 12 OE low to output in low Z tOLZ 0 - 0 - 0 - 0 - ns 4, 5 OE high to output in high Z tOHZ - 5 - 6 - 7 - 8 ns 4, 5 Power up time tPU 0 - 0 - 0 - 0 - ns 4, 5, 12 Power down time tPD - 10 - 12 - 15 - 20 ns 4, 5, 12 Key to switching waveforms Rising input Falling input Undefined / don't care Read waveform 1 (address controlled)3,6,7,9,12 tRC Address tAA tOH DOUT Data valid Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12 tRC1 CE1 CE2 tOE OE DOUT Supply current 3/24/04, v.1.2 tOHZ tCHZ1, tCHZ2 tOLZ tACE1, tACE2 tCLZ1, tCLZ2 tPU Data valid tPD 50% Alliance Semiconductor 50% ICC ISB P. 4 of 9 AS7C31024B (R) Write cycle (over the operating range)11, 12 -10 Parameter -12 -15 -20 Symbol Min Max Min Max Min Max Min Max Unit Notes Write cycle time tWC 10 - 12 - 15 - 20 - ns Chip enable (CE1) to write end tCW1 8 - 9 - 10 - 12 - ns 12 Chip enable (CE2) to write end tCW2 8 - 9 - 10 - 12 - ns 12 Address setup to write end tAW 8 - 9 - 10 - 12 - ns Address setup time tAS 0 - 0 - 0 - 0 - ns Write pulse width tWP 7 - 8 - 9 - 12 - ns Write recovery time tWR 0 - 0 - 0 - 0 - ns Address hold from end of write tAH 0 - 0 - 0 - 0 - ns Data valid to write end tDW 5 - 6 - 8 - 10 - ns Data hold time tDH 0 - 0 - 0 - 0 - ns 4, 5 Write enable to output in high Z tWZ - 5 - 6 - 7 - 8 ns 4, 5 Output active from write end tOW 1 - 1 - 1 - 1 - ns 4, 5 12 Write waveform 1 (WE controlled)10,11,12 tWC tWR tAH tAW Address tWP WE tAS tDW DIN tDH Data valid tWZ tOW DOUT 3/24/04, v.1.2 Alliance Semiconductor P. 5 of 9 AS7C31024B (R) Write waveform 2 (CE1 and CE2 controlled)10,11,12 tAW tWC tAH tWR Address tAS tCW1, tCW2 CE1 CE2 tWP WE tWZ DIN tDW tDH Data valid DOUT AC test conditions - - - - Output load: see Figure B. Input pulse level: GND to 3.0V. See Figure A. Input rise and fall times: 2 ns. See Figure A. Input and output timing reference levels: 1.5V. Thevenin equivalent: 168 DOUT +1.728V +3.0V DOUT 255 +3.3V 320 GND 90% 10% 90% 2 ns 10% C13 GND Figure B: 3.3V Output load Figure A: Input pulse Notes 1 2 3 4 5 6 7 8 9 10 11 12 13 14 During VCC power-up, a pull-up resistor to VCC on CE1 is required to meet ISB specification. This parameter is sampled and not 100% tested. For test conditions, see AC Test Conditions, Figures A, and B. tCLZ and tCHZ are specified with CL = 5pF, as in Figure C. Transition is measured 500 mV from steady-state voltage. This parameter is guaranteed, but not 100% tested. WE is high for read cycle. CE1 and OE are low and CE2 is high for read cycle. Address valid prior to or coincident with CE1 transition Low. All read cycle timings are referenced from the last valid address to the first transitioning address. N/A All write cycle timings are referenced from the last valid address to the first transitioning address. CE1 and CE2 have identical timing. C = 30 pF, except all high Z and low Z parameters where C = 5 pF. N/A 3/24/04, v.1.2 Alliance Semiconductor P. 6 of 9 AS7C31024B (R) Package dimensions D 32-pin SOJ 300 mil e E1E2 B Pin 1 c A A1 A2 b Seating Plane E Min Max Min Max A 0.128 0.145 0.132 0.146 A1 0.025 - 0.025 - A2 0.095 0.105 0.105 0.115 B 0.026 0.032 0.026 0.032 b 0.016 0.020 0.015 0.020 c 0.007 0.010 0.007 0.013 D 0.820 0.830 0.820 0.830 E 0.255 0.275 0.354 0.378 E1 0.295 0.305 0.395 0.405 E2 0.330 0.340 0.435 0.445 e b 0.050 BSC 0.050 BSC 32-pin TSOP 8x20 mm e Min c D Hd A2 L pin 1 E 3/24/04, v.1.2 32-pin SOJ 400 mil pin 16 A A1 pin 32 pin 17 Alliance Semiconductor Max A - 1.20 A1 0.05 0.15 A2 0.95 1.05 b 0.17 0.27 c 0.10 0.21 D 18.30 18.50 e 0.50 nominal E 7.90 8.10 Hd 19.80 20.20 L 0.50 0.70 0 5 P. 7 of 9 AS7C31024B (R) Ordering codes Package \ Access time Temp 10 ns Plastic SOJ, 300 mil Commercial AS7C31024B-10TJC Plastic SOJ, 400 mil Commercial TSOP1 8x20 mm sTSOP1 8 x 13.4mm 12 ns 15 ns 20 ns AS7C31024B-12TJC AS7C31024B-15TJC AS7C31024B-20TJC AS7C31024B-10JC AS7C31024B-12JC AS7C31024B-15JC AS7C31024B-20JC Commercial AS7C31024B-10TC AS7C31024B-12TC AS7C31024B-15TC AS7C31024B-20TC Commercial AS7C31024B-10STC AS7C31024B-12STC AS7C31024B-15STC AS7C31024B-20STC Note: Add suffix `N' to the above part number for lead free parts (Ex. AS7C31024B-10TJCN) Part numbering system AS7C X 1024B -XX SRAM Device Access 3 = 3.3 V CMOS prefix number time 3/24/04, v.1.2 X X X Package: T = TSOP1 8x20 mm ST = sTSOP1 8 x 13.4 mm J = SOJ 400 mil TJ = SOJ 300 mil Temperature range C = Commercial, 0 C to 70 C N=Lead Free Part Alliance Semiconductor P. 8 of 9 AS7C31024B (R) (R) Alliance Semiconductor Corporation Copyright (c) Alliance Semiconductor 2575, Augustine Drive, All Rights Reserved Santa Clara, CA 95054 Part Number: AS7C31024B Tel: 408 - 855 - 4900 Document Version: v.1.2 Fax: 408 - 855 - 4999 www.alsc.com (c) Copyright 2003 Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. 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