October 2012 210403 - Rev 4 1/51
1
Numonyx® NAND SLC small page
70 nm Discrete
512 Mbit, 528 Byte/264 Word page, x8/x16, 1.8 V/3 V
Features
Density
– 512 Mbit: 4096 blocks
NAND Flash interface
– x8 or x16 bus width
– Multiplexed address/data
Memory configuration
– Page size:
x8 device: (512 + 16 spare) Bytes
x16 device: (256 + 8 spare) Words
– Block size:
x8 device: (16K + 512 spare) Bytes
x16 device: (8K + 256 spare) Words
Supply voltage: 1.8 V, 3 V
Read/write performance
– Random access: 12 µs (3 V)/15 µs(1.8 V)
(max)
– Sequential access: 30 ns (3 V)/50 ns
(1.8 V)(min)
– Page program time: 200 µs (typ)
– Block erase time: 2 ms (typ)
– Programming performance (typ):
x8 device: 2.3 MByte/s
x16 device: 2.4 MByte/s
Additional features
– Copy back program mode
– Error correction code models
– Bad blocks management and wear leve ling
algorithms
– Hardwar e sim ula tio n mod els
Quality and reliability
– 100,000 program/erase cycles (with ECC)
– 10 years data retention
– Operating temperature: –40 to 85 °C
Security
– OTP area
– Serial number (unique ID)
– Hardware program/erase locked during
power transitions
Electronic signature
– Manufacturer ID:
x8 device: 20h
x16 device: 0020h
–Device ID:
NAND512W3A2S: 76h
NAND512W4A2S: 0056h
NAND512R3A2S: 36h
NAND512R4A2S: 0046h
Package
– RoHS compliant
– TSOP48 12 x 20 mm
–VFBGA63 9x11mm
Table 1. Device summary
Root part number list - see Table 25 for details
NAND512W3A2S
NAND512W4A2S
NAND512R3A2S
NAND512R4A2S
www.numonyx.com
Contents Numonyx SLC SP 70 nm
2/51 210403 - Rev 4
Contents
1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2 Memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 Command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.2 Address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.3 Data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.4 Data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.5 Write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.6 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5 Command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6 Device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.1 Pointer operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.2 Read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.1 Random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.2.2 Page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.2.3 Sequential row read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.3 Page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.4 Copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.5 Block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
6.7 Read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7.1 Write protection bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7.2 P/E/R controller bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7.3 Error bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved . . . . . . . . . . . . . . . . . . . . . 26
6.8 Read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Numonyx SLC SP 70 nm Contents
210403 - Rev 4 3/51
7 Software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.1 Bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.2 NAND Flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
7.3 Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.4 Wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.5 Error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.6 Hardware simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6.1 Behavioral simulation models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.6.2 IBIS simulations models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
8 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 32
9 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
10.1 Ready/Busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 44
10.2 Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
12 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of tables Numonyx SLC SP 70 nm
4/51 210403 - Rev 4
List of tables
Table 1. Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Product description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 4. Valid blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 5. Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 6. Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 7. Address insertion, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 8. Address insertion, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 9. Address definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 10. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table 11. Copy back program addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 12. Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 13. Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 14. NAND Flash failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 15. Pr ogram, erase times and program erase endura nce cycles. . . . . . . . . . . . . . . . . . . . . . . 32
Table 16. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 17. Operatin g an d AC me as ur em e nt con ditio n s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 18. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 19. DC characteristics, 1.8 V devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 20. DC characteristics, 3 V devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 21. AC characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 22. AC characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 23. TSOP48 - 48 lead pla stic th in sm all ou tlin e, 12 x 20 mm, mechanical data. . . . . . . . . . . . 47
Table 24. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball array, 0.8 mm pitch, mechanical data 48
Table 25. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 26. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Numonyx SLC SP 70 nm List of figures
210403 - Rev 4 5/51
List of figures
Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2. Logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3. TSOP48 connections - x8 devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. VFBGA63 connections - x8 devices (top view through package). . . . . . . . . . . . . . . . . . . . 10
Figure 5. Memory array organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Pointer operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 7. Pointer operations for programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 8. Read (A,B,C) operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 9. Sequential row read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Sequential row read block diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 11. Read block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 12. Page program operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 13. Copy back operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 14. Block erase operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 16. Garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 17. Equivalent testing circuit for AC characteristics measurement. . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. Command Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 19. Address Latch AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 20. Data Input Latch AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 21. Sequential data output after read AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 22. Read status register AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 23. Read electronic signature AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 24. Page read A/read B operation AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 25. Read C operation, one page AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 26. Page program AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 27. Block erase AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 28. Reset AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 29. Program/erase enable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 30. Program/erase disable waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 31. Ready/Busy AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 32. Ready/Busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 33. Resistor value versus waveform timings for Ready/Busy signal. . . . . . . . . . . . . . . . . . . . . 46
Figure 34. Data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 35. TSOP48 - 48 lead plastic thin sm all ou tlin e, 12 x 2 0 mm , pa ck ag e outline . . . . . . . . . . . . 47
Figure 36. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15, 0.8 mm pitch, package outline . . . . . . . . . . . . . . 48
Description Numonyx SLC SP 70 nm
6/51 210403 - Rev 4
1 Description
The NAND Flash 528 Byte/264 Word page is a family of non-volatile Flash memories that
uses the single level cell (SLC) NAND technology. It is referred to as the small page family.
The devices have a density o f 512 Mbits and operate with ei ther a 1.8 or 3 V voltag e supply.
The size of a page is either 528 Bytes (512 + 16 spare) or 264 Words (256 + 8 spare)
depending on whether the device has a x8 or x16 bus width.
The address lines ar e multiple xed with th e Data Input/Output signals on a multiplexed x8 or
x16 input/output bus. This interface reduces the pin count and makes it possible to migrate
to other densities without changing the footprint.
To extend the lifetime of NAND Flash devices it is strongly recommended to implement an
error correction code (ECC). The use of ECC correction allows to achieve up to 100,000
program/erase cycles for each block. A write protect pin is available to give a hardware
protection against program and erase operations.
The devices feature an open-drain Ready/Busy output that can be used to identify if the
program/erase/read (P/E/R) controller is currently active. The use of an open-drain output
allows the ready/busy pins from several memories to be connected to a single pull-up
resistor.
A Copy Back command is available to optimize the management of defective blocks. When
a page program operation fails, the data can be programmed in another page without
having to resend the data to be programmed.
The devices are available in the TSOP48 (12 x 20 mm) and VFBGA63 (9 x 11 x 1.05 mm)
packages and in two different versions:
lNo option (Chip Enable ‘care’, sequential row read enabled): the sequential row read
feature allows to download up to all the pages in a block with one read command and
addressing only the first page to read
lWith Chip Enable ‘don’t care’ feature. This enables the sharing of the bus between
more active memories that are simult aneo usly active as Chip En able transition s during
latency do not stop read operations. Program and erase operations are not interrupted
by Chip Enable transitions.
They also come with the following security features:
lOTP (one time progr ammable) area, which is a restricted access area where sensitive
data/code can be stored permanently. The access sequence and further details about
this feature are subject to an NDA (non disclosure agreement)
lSerial number (unique identifier), which enables each device to be uniquely identified.
It is subject to an NDA and is, therefore, not described in the datasheet.
For more details about these security features, contact your nearest Numonyx sales office.
For informati on on how to or de r thes e de vice s re fe r to Table 25: Ordering information
scheme. Devices are shipped from the factory with block 0 always valid and the memory
content bits, in valid blocks, erased to ’1’.
See Table 2: Product description, for all the devices available in the family.
Numonyx SLC SP 70 nm Description
210403 - Rev 4 7/51
Figure 1. Logic diagram
Table 2. Product description
Root part
number Density Bus
width Page
size Block
size Memory
array Operating
voltage
Timings
Package
Random
access
Max
Sequential
access
Min
Page
program
Typ
Block
erase
Typ
NAND512W3A2S
512
Mbit
x8 512+16
Bytes 16K+512
Bytes
32 pages x
4096 blocks
2.7 to 3.6 V 12 µs 30 ns
200 µs 2 ms TSOP48
VFBGA63
NAND512W4A2S x16 256+8
Words 8K+256
Words
NAND512R3A2S x8 512+16
Bytes 16K+512
Bytes 1.7 to 1.95 V 15 µs 50 ns
NAND512R4A2S x16 256+8
Words 8K+256
Words
AI07557C
W
I/O8-I/O15, x16
VDD
NAND flash
E
VSS
WP
AL
CL
RB
R
I/O0-I/O7, x8/x16
8
Description Numonyx SLC SP 70 nm
8/51 210403 - Rev 4
Figure 2. Logic block diagram
Table 3. Signal names
Signal Function Direction
I/O8-15 Data input/outputs for x16 devices I/O
I/O0-7 Data input/outputs, address inputs, or command inputs for x8 and
x16 devices I/O
AL Address Latch Enable Input
CL Command Latch Enable Input
EChip Enable Input
RRead Enable Input
RB Ready/Busy (open-drain output) Output
WWrite Enable Input
WP Write Protect Input
VDD Supply voltage Power supply
VSS Ground Ground
NC Not connected internally –
DU Do not use –
Address
register/counter
Command
interface
logic
P/E/R controller,
high voltage
generator
WP
I/O buffers & latches
I/O8-I/O15, x16
E
W
AI07561c
R
Y decoder
Page buffer
NAND flash
memory array
X decoder
I/O0-I/O7, x8/x16
Command register
CL
AL
RB
Numonyx SLC SP 70 nm Description
210403 - Rev 4 9/51
Figure 3. TSOP48 conne ctions - x8 devices
I/O3
I/O2
I/O6
R
RB
NC
I/O4
I/O7
AI07585C
NAND flash
(x8)
12
1
13
24 25
36
37
48
E
I/O1
NC
NC
NC
NC
NC
NC
NC
WP
W
NC
NC
NC
VSS
VDD
AL
NC
NC
CL
NC
I/O5
NC
NC
NC
I/O0
NC
NC
NC
NC
NC
VDD
NC
NC
NC
VSS
NC
NC
NC
NC
Description Numonyx SLC SP 70 nm
10/51 210403 - Rev 4
Figure 4. VFBGA63 connections - x8 devices (top view through package)
AI07586B
I/O7
WP
I/O4I/O3
NC VDD
I/O5VDD
NC
H
VSS
I/O6
D
E
CL
C
NC
NC
BDU
NC
W
NC
A
87654321
NCNC
NC NC
G
F
E
I/O0
AL
DU
NC NC
NC
NCNC NC NCNC
NCNC
VSS
NCNC
NC NC
RB
I/O2
DU
NC
DU
I/O1
109
R
NC
NC
NC
VSS
DU
DU DU
DU
DU DU
DU
DU
DU DU
DU
M
L
K
J
Numonyx SLC SP 70 nm Memory array organization
210403 - Rev 4 11/51
2 Memory array organization
The memory array is made up of NAND structures where 16 cells are connected in series.
The memory arra y is orga nized in blo cks where e ach bl ock contains 32 pages. The arr ay is
split into two areas, the main area and the spare area. The main area of the array is used to
store dat a whereas the sp are ar ea is typically u sed to store error correction codes, software
flags or bad block identification.
In x8 devices the p ages are split into a ma in area with two half pages of 256 Bytes each and
a spare area of 16 Bytes. In the x16 devices the pages are split into a 256 Word main area
and an 8 Word spare area. Refer to Figure 5: Memory array organization.
Bad blocks
The NAND Flash 528 Byte/264 Word page devices may contain bad blocks, that is blocks
that contain one or more invalid bits whose reliability is not guaranteed. Additional bad
blocks may develop during the lifetime of the device.
The bad block information is written prior to shipping (refer to Section 7.1: Bad block
management for more details).
Table 4 shows the minimum number of valid blocks in each device. The values shown
include both the bad blocks that are present when the device is shipped and the bad blocks
that could develop later on.
These blocks need to be managed using bad blocks management, block replacement or
error correction codes (refer to Section 7: Software algorithms).
Table 4. Valid blocks
Density of device Min Max
512 Mbit 4016 4096
Memory array organization Numonyx SLC SP 70 nm
12/51 210403 - Rev 4
Figure 5. Memory array organization
AI07587
Block = 32 pages
Page = 528 bytes (512+16)
512 bytes
512 Bytes
Spare area
2nd half page
(256 bytes)
16
bytes
Block
8 bits
16
bytes 8 bits
Page
Page buffer, 512 bytes
1st half page
(256 bytes)
Block = 32 pages
Page = 264 words (256+8)
256 words
256 words
Spare area
Main area
8
words
16 bits
8
words 16 bits
Page buffer, 264 words
Block
Page
x8 DEVICES x16 DEVICES
Numonyx SLC SP 70 nm Signal descriptions
210403 - Rev 4 13/51
3 Signal descriptions
See Figure 1: Logic diagram, and Table 3: Signal names, for a brief overview of the signals
connected to the devices. Table 5 provides the detailed descriptions of the sig na ls.
Table 5. Signal descriptions
Symbol Type Description
Input/Outp ut signals
I/O0-I/O7 Input/Output
Input/outputs 0 to 7 are used to input the selected address,
output the data during a read operation or input a
command or data during a write operation. Th e inputs are
latched on the rising edge of Write Enable. I/O0-I/O7 are
left floating when the device is deselected or the outputs
are disabled.
I/O8-I/O15 Input/Output
Input/outputs 8 to 15 are only available in x16 devices.
They are used to output the data during a read operation or
input data during a write operation. Command and address
inputs only require I/O0 to I/O7.
The inputs are latched on the rising edge of Write Enable.
I/O8-I/O15 are left floating when the device is deselected
or the outputs are disabled.
Control signals
AL Input
The Address Latch Enable activates the latching of the
address inputs in the command interface. When AL is
High, the inputs are latched on the rising edge of Write
Enable.
CL Input
The Command Latch Enable activates the latching of the
command inputs in the command interface. When CL is
High, the inputs are latched on the rising edge of Write
Enable.
EInput
The Chip Enable inpu t activates the memory control logic,
input buffers, decoders and read circuitry. When Chip
Enable is Low, VIL, the device is selected.
If Chip Enable goes High (VIH) while the device is busy
programming or erasing, the device remains selected and
does not go into standby mode.
While the device is busy reading:
– the Chip Enable input should be hel d Low during the
whole busy time (tBLBH1) for devices that do not feature
the Chip Enable don’t care option. Otherwise, the read
operation in progress is interrupted and the device goes
into standby mode.
– for devices that feature the Chip Enable don’t care
option, the Chip Enable going High during the busy time
(tBLBH1) will not interrupt the read operation and the
device will not go into standby mode.
Signal descriptions Numonyx SLC SP 70 nm
14/51 210403 - Rev 4
RInput
The Read Enable, R, co ntrols the sequential data output
during read operations. Data is valid tRLQV after the falling
edge of R. The falling edge of R also increments the
internal column address counter by one.
WInput
The Write Enable input, W, controls writing to the
command interface, input address and data latches. Both
addresses and data are latched on the rising edge of Write
Enable.
During power-up and power-down a recovery time of 10 µs
(min) is required before the command interface is ready to
accept a command. It is recommended to keep Write
Enable High during the recovery time.
WP Input
The Write Protect pin is an input that gives a hardware
protection against unwanted program or erase operations.
When Write Protect is Low , VIL, the device does not accept
any program or erase operations.
It is recommended to keep the Write Protect pin Low, VIL,
during power-up and power-down.
RB Output
The Ready/Busy outp ut, RB, is an open-d ra in output that
can be used to identify if the P/E/R controller is currently
active.
When Ready/Busy is Low, VOL, a read, program or erase
operation is in progress. When the operation completes
Ready/Busy goes High, VOH.
The use of an open-drain output allows the Ready/Busy
pins from several memories to be connected to a single
pull-up resistor. A Low will then indicate that one, or more,
of the memories is busy.
During power-up and power-down a recovery time of 10 µs
(min) is required before the command interface is ready to
accept a command. During the recovery time the RB signal
is Low, VOL.
Refer to the Section 10.1: Ready/Busy signal electrical
characteristics for details on how to calculate the value of
the pull-up resistor.
Supply
VDD Supply voltage
VDD provides the power supply to the internal core of the
memory device. It is the main power supply for all
operations (read, program and erase).
An internal voltage detector disables all functions
whenever VDD is below the VLKO threshold (see Figure 34:
Data protection) to protect the device from any involuntary
program/erase operations during power-transitions.
VSS Ground Ground, VSS, is the reference for the power supply. It must
be connected to the system ground.
Table 5. Signal descriptions (continued)
Symbol Type Description
Numonyx SLC SP 70 nm Bus operations
210403 - Rev 4 15/51
4 Bus operations
There are six standard bus operations that contro l the memory. Each of these is described
in this section, see Table 6: Bus operations, for a summa ry.
4.1 Command input
Command input bus operations are use d to give commands to the memory. Command are
accepted when Chip Enable is Low, Command Latch Enable is High, Address Latch Enable
is Low and Read Enable is High. They ar e latche d on the rising edge of the Write Enable
signal.
Only I/O0 to I/O7 are used to input commands.
See Figure 18 and Table 21 for details of the timings requirements .
4.2 Address input
Address input bus operations are used to input the memory address. Four bus cycles are
required to input the addresses for the 512 Mbit devices (refer to Table 7 and Table 8,
Address Insertion).
The addresses are accepted when Chip Enable is Low, Address Latch Enable is High,
Command Latch Enable is Low and Read Enable is High. They are latched on the rising
edge of the Write Enable signal. Only I/O0 to I/O7 are used to input addresses.
See Figure 19 and Table 21 for details of the timings requirements .
4.3 Data input
Data Input bus operations are used to input the data to be programmed.
Data is accepted only when Chip Enable is Low, Address Latch Enable is Low, Command
Latch Enable is Low and Read Enable is High. The data is latched on the rising edge of the
Write Enable signal. The data is input sequentially using the Write Enable signal.
See Figure 20, Table 21, and Table 22 for details of the timings requirements.
4.4 Data output
Data Output bus operations are used to read: the data in the memory array, the status
register, the electronic signature and the serial number.
Data is output when Chip Enable is Low , Write Enable is High, Address Latch Enable is
Low, and Command Latch Enable is Low.
The data is output sequentially using the Read Enable signal.
See Figure 21 and Table 22 for details of the timings requirements .
Bus operations Numonyx SLC SP 70 nm
16/51 210403 - Rev 4
4.5 Write protect
Write protect bus operations ar e used to protect the memory against program or erase
operations. When the Write Protect signal is Low the device will not accept program or
erase operations and so the contents of the memory array cannot be altered. The Write
Protect signal is not latched by Write Enable to ensure protection even during power-up.
4.6 Standby
When Chip Enable is High the memory enters standby mode, the device is deselected,
outputs are disabled and power consumption is reduced.
Table 6. Bus operations
Bus operation E AL CL R WWP I/O0 - I/O7 I/O8 - I/O15(1)
1. Only for x16 devices.
Command input VIL VIL VIH VIH Rising X(2)
2. WP must be VIH when issuing a program or erase command.
Command X
Address input VIL VIH VIL VIH Rising X Address X
Data input VIL VIL VIL VIH Rising X Data input Data input
Data output VIL VIL VIL Falling VIH X Data output Data output
Wr ite protect X X X X X VIL XX
Standby VIH XX X XX X X
Table 7. Address insertion, x8 devices(1)(2)
1. A8 is set Low or High by the 00h or 01h command, see Section 6.1: Pointer operations.
2. Any additional address input cycles is ignored.
Bus
cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st A7 A6 A5 A4 A3 A2 A1 A0
2nd A16 A15 A14 A13 A12 A11 A10 A9
3rd A24 A23 A22 A21 A20 A19 A18 A17
4th VIL VIL VIL VIL VIL VIL VIL A25
Table 8. Address insertion, x16 devices (1)(2)
1. A8 is don’t care in x16 devices.
2. Any additional address input cycle is ignored.
Bus
cycle I/O8-
I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
1st XA7 A6 A5 A4 A3 A2 A1 A0
2nd XA16 A15 A14 A13 A12 A11 A10 A9
3rd XA24 A23 A22 A21 A20 A19 A18 A17
4th(4) X VIL VIL VIL VIL VIL VIL VIL A25
Numonyx SLC SP 70 nm Bus operations
210403 - Rev 4 17/51
Table 9. Address definition
Address Definition
A0 - A7 Column address
A9 - A25 Page address
A9 - A13 Address in block
A14 - A25 Block address
A8 A8 is set Low or High by the 00h or 01h
command, and is don’t care in x16 devices
Command set Numonyx SLC SP 70 nm
18/51 210403 - Rev 4
5 Command set
All bus write operations to the device are interpreted by the command interface. The
commands are input on I/O0-I/O7 and are latch ed on the rising edge of Write Enable when
the Command Latch Enable signal is High. Device operations are selected by writing
specific commands to the command register. The two-step command sequences for
program and erase operations are imposed to maximize data security.
The commands are summarized in Table 10.
Table 10. Commands
Command Bus write operation s (1)(2)
1. The bus cycles are only shown for issuing the codes. The cycles required to input the addresses or
input/output data are not shown.
2. Any undefined command sequence is ignored by the device.
Command
accepted during
busy
1st cycle 2nd cycle 3rd cycle
Read A 00h – –
Read B(3)
3. The Read B command (code 01h) is not used in x16 devices.
01h – –
Read C 50h – –
Read Electronic Signature 90h – –
Read Status Register 70h – – Yes
Page Program 80h 10h –
Copy Back Program 00h 8Ah (10h)(4)
4. The Program Confirm command (code 10h) is no more necessary for 512 Mbit, 70 nm devices. It is
optional and has been maintained for backward compatibility.
Block Erase 60h D0h –
Reset FFh – – Yes
Numonyx SLC SP 70 nm Device operations
210403 - Rev 4 19/51
6 Device operations
6.1 Pointer operations
As the NAND Flash memories cont ain two dif ferent areas for x16 devices and three dif ferent
areas for x8 devices (see Figure 6) the read command code s (0 0h , 01 h, 50h ) ar e us ed to
act as pointers to the different areas of the memory array (they select the most significant
column address).
The Read A and Read B commands act as pointers to the main memory area. Their use
depends on the bus width of the device.
lIn x16 devices the Read A command (00h) sets the pointer to area A (the whole of the
main area) that is Words 0 to 255.
lIn x8 devices the Read A command (00h) set s the p ointer to area A (the first half of the
main area) that is Bytes 0 to 255, and the Read B command (0 1h) sets the pointer to
area B (the second half of the main area) that is Bytes 256 to 511.
In both the x8 an d x16 de vices th e Read C co mmand (5 0h), acts as a pointer to area C (t he
spare memory area) that is Bytes 512 to 527 or Words 256 to 263.
Once the Read A and Read C commands have been issued the pointer remains in the
respective areas until another pointer code is issued. However, the Read B command is
effective for only one operation, once an operation has been executed in area B the pointer
returns automatically to area A.
The pointer ope rations can also be used before a prog ram operation , that is the ap propriate
code (00h, 01h or 50h) can be issued before the program command 80h is issued (see
Figure 7).
Figure 6. Pointer operations
AI07592
Area A
(00h)
A
Area B
(01h) Area C
(50h)
bytes 0 - 255 bytes 256 - 511 bytes
512 - 527
CB
Pointer
(00h,01h,50h)
Page buffer
Area A
(00h)
A
Area C
(50h)
words 0 - 255 words
256 - 263
C
Pointer
(00h,50h)
Page buffer
x8 devices x16 devices
Device operations Numonyx SLC SP 70 nm
20/51 210403 - Rev 4
Figure 7. Pointer operations for programming
6.2 Read memory array
Each operation to read the memory area starts with a pointer operation as shown in the
Section 6.1: Pointer operations. Once the are a (main or sp are ) has been selecte d using the
Read A, Read B or Read C commands four bus cycles are required to input the address
(refer to Table 7 and Table 8) of the data to be read.
The device defaults to read A mode after power-up or a reset operation.
When reading the spare area addresses:
lA0 to A3 (x8 devices)
lA0 to A2 (x16 devices)
are used to set the start address of the spare area while addresses:
lA4 to A7 (x8 devices)
lA3 to A7 (x16 devices)
are ignored.
Once the Read A or Read C commands have been issued they do not need to be reissued
for subsequent read operations as the pointer remains in the respective area. However, the
Read B command is ef fective for only on e ope ratio n, once an operatio n has been execu ted
in area B the pointer returns automatically to area A and so another Read B command is
required to start another read operation in area B.
Once a Read command is issued two types of operations ar e available: random read and
page read.
6.2.1 Random read
Each time the command is issued the first read is random read.
ai07591
I/O Address
Inputs Data Input 10h
80h
Areas A, B, C can be programmed depending on how much data is input. Subsequent 00h commands can be omitted.
AREA A
00h Address
Inputs Data Input 10h
80h
00h
I/O Address
Inputs Data Input 10h
80h
Areas B, C can be programmed depending on how much data is input. The 01h command must be re-issued before each program.
AREA B
01h Address
Inputs Data Input 10h
80h
01h
I/O Address
Inputs Data Input 10h
80h
Only Areas C can be programmed. Subsequent 50h commands can be omitted.
AREA C
50h Address
Inputs Data Input 10h
80h
50h
Numonyx SLC SP 70 nm Device operations
210403 - Rev 4 21/51
6.2.2 Page read
After the random read access the page data is transferred to the page buffer in a time of
tWHBH (refer to Table 22 for value). Once the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequentially (from selected column address to
last column address) by pulsing the Read Enable signal.
Figure 8. Read (A,B,C) operations
6.2.3 Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed and
Chip Enable remains Low, then the next page is automatically loaded into the page buffer
and the read operation continues. A sequential row rea d operation can only be used to rea d
within a block. If the block changes a new read command must be issued. Refer to Figure 9:
Sequential row read operations and Figure 10: Sequential row read block diagrams for
details ab out seq uen tia l ro w r ead ope ra tio ns. To termin ate a seq uen tial row r ead ope ratio n,
set to High the Chip Enable signal for more than tEHEL. Sequential r ow read is not available
when the Chip Enable don’t care option is enabled.
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595c
Busy
Command
code
Address input Data output (sequentially)
tBLBH1
(read)
Device operations Numonyx SLC SP 70 nm
22/51 210403 - Rev 4
Figure 9. Sequential row read operations
Figure 10. Sequential row read block diagrams
Figure 11. Read block diagrams
1. Highest address depends on device density.
I/O
RB
Address Inputs
ai07597
1st
Page Output
Busy
tBLBH1
(Read Busy time)
00h/
01h/ 50h
Command
Code
2nd
Page Output Nth
Page Output
BusyBusy
tBLBH1 tBLBH1
AI07596
A0-A7
A9-A26(1)
Area A
(1st half page)
Read A command, x8 devices
Area B
(2nd half page) Area C
(spare) Area A
(main area) Area C
(spare)
A0-A7
Read A command, x16 devices
A0-A7
Read B command, x8 devices
Area A
(1st half page) Area B
(2nd half page) Area C
(spare)
A0-A3 (x 8)
A0-A2 (x 16)
Read C command, x8/x16 devices
Area A Area A/ B Area C
(spare)
A9-A26(1)
A9-A26(1)
A9-A26(1)
A4-A7 (x 8), A3-A7 (x 16) are don't care
Numonyx SLC SP 70 nm Device operations
210403 - Rev 4 23/51
6.3 Page program
The page program operation is the st andard operation to prog ram data to the memory arr ay.
The main area of the memory array is programmed by page, however partial page
programming is allowed where any number of Bytes (1 to 528) or Words (1 to 264) can be
programmed.
The maximum number of consecutive p ar tial page program operations allowed in the same
page is three. After exceeding this a Block Erase command must be issued before any
further program operations can take place in that page.
Before st arting a page program operation a pointer operation can be performed to point to
the area to be programmed. Refer to the Section 6.1: Pointer operations and Figure 7 for
details.
Each page program operation consists of five steps (see Figure 12):
1. One bus cycle is required to setup the Page Program command
2. Four bus cycles are then required to input the program address (refer to Table 7 and
Table 8)
3. The data is then input (up to 528 Bytes/264 Words) and loaded into the page buffer
4. One bus cycle is required to issue the confirm command to start the P/E/R controller
5. The P/E/R controller then programs the data into the array.
Once the program operation has started the status register can be read using the Read
Status Register command. During program operations the status register only flags errors
for bits set to '1' that have not been successfully programmed to '0'.
During the program operation, only the Read Status Register and Reset commands are
accepted, all other commands ar e ignored.
Once the program operation has completed the P/E/R controller bit SR6 is set to ‘1’ and the
Ready/Busy signal goes High.
The device remains in read status register mode until another valid command is written to
the command interface.
Figure 12. Page program operation
1. Before starting a page program operation a pointer operation can be performed. Refer to Section 6.1: Pointer operations for
details.
I/O
RB
Address Inputs SR0
ai07566
Data Input 10h 70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
Busy
tBLBH2
(Program Busy time)
Device operations Numonyx SLC SP 70 nm
24/51 210403 - Rev 4
6.4 Copy back program
The copy back program operation is used to copy the data stored in one page and
reprogram it in another page.
The copy back p rogram opera tion does not require external memor y and so the operation is
faster and more efficient because the reading and loading cycles are not required. The
operation is p articularly u seful when a po rtion of a blo ck is updated and the rest of the block
needs to be copied to the newly assigned block.
If the copy back pr ogram operation fails an error is signalled in the status register. However
as the standard external ECC cannot be used with the copy back operation bit error due to
charge loss cannot be detected. For this reason it is recommended to limit the number of
copy back operations on the same data and or to improve the performance of the ECC.
The copy back program operation requires two steps:
1. The source page must be read using the Read A command (one bu s write cycle to
setup the command and then 4 bus write cycles to input the source page address).
This operation copies all 264 Words/ 528 Bytes from the page into the page buffer
2. When the device returns to the ready state (Ready/Busy High), the second bus write
cycle of the command is given with the 4 bus cycles to input the target page address.
Refer to Table 11 for the addresses that must be the same for the source and target
pages
3. The Program Confirm command (code 10h ) is no more necessary on 512 Mbit, 70 nm
devices. It is optional and has been maintained for backward compatibility.
After a copy back program operation, a partial-p age program is not allowed in the target
page until the block has been erased.
See Figure 13 for an example of the copy back operation.
Figure 13. Copy back operation
1. The Program Confirm command (code 10h) is no more necessary on 512 Mbit, 70 nm devices. It is optional and has been
maintained for backward compatibility.
Table 11. Copy back program addresses
Density Same addr e s s for source and ta rget pages
512 Mbit A25
I/O
RB
Source
Address Inputs SR0
ai13187
8Ah 70h00h
Copy Back
Code
Read
Code Read Status Register
Target
Address Inputs
tBLBH1
(Read Busy time)
10h(1)
Busy
tBLBH2
(Program Busy time)
Numonyx SLC SP 70 nm Device operations
210403 - Rev 4 25/51
6.5 Block erase
Erase operations are done one block at a time. An erase operation sets all of the bits in the
addressed block to ‘1’. All previo us data in th e blo ck is lost.
An erase operation consists of three steps (refer to Figure 14):
1. One bus cycle is required to setup the Block Erase command
2. Only three bus cycles are required to inpu t the block addr ess. The first cycle ( A0 to A7)
is not required as only addresses A14 to A25 are valid, A9 to A13 are ignored. In the
last address cycle I/O2 to I/O7 must be set to VIL.
3. One bus cycle is required to issue the Confirm command to start the P/E/R controller.
Once the erase operation has completed the status register can be checked for errors.
Figure 14. Block erase operation
6.6 Reset
The Reset command is used to reset the command interface and status register. If the
Reset command is issued during any operation, the operation will be aborted. If it was a
program or er ase operation tha t was abo rt ed , the contents of the memory locations being
modified will no longer be valid as the data will be partially programmed or erased.
If the device has already been reset then the new Reset command will not be accepted.
The Ready/Busy signal goes Low for tBLBH4 after the Reset command is issued. The value
of tBLBH4 depends on the operation that the device was perfo rming when the comma nd was
issued, refer to Table 22 for the values.
I/O
RB
Block Address
Inputs SR0
ai07593
D0h 70h
60h
Block Erase
Setup Code Confirm
Code Read Status Register
Busy
tBLBH3
(Erase Busy time)
Device operations Numonyx SLC SP 70 nm
26/51 210403 - Rev 4
6.7 Read status reg i ster
The device contains a status register which provides information on the current or previous
program or erase operation. The various bits in the status register convey information and
errors on the operation.
The status registe r is read by issuing the Read Status Register command. The status
register information is presen t on the output da t a bus ( I/O0-I/O7) on the falling edge of Chip
Enable or Read Enable, wh ichever occurs l ast. When several memo ries are conn ected in a
system, the use of Chip Ena b le an d Re ad Enable sign als allo ws the sys te m to poll each
device separately, even when the Ready/Busy pins are common-wired. It is not necessary
to toggle the Chip Enable or Read Enable signals to update the contents of the status
register.
After the Read Status Register command has been issued, the device remains in read
status register mode until another command is issued. Therefore if a Read Status Register
command is issued during a random read cycle a new read command must be issued to
continue with a page read.
The status re gister bits are summarize d in Table 12: St atus register bit s. Refer to Table 12 in
conjunction with the following text descriptions.
6.7.1 Write protection bit (SR7)
The write protection bit can be used to identify if the device is protected or not. If the write
protection bit is set to ‘1’ the device is not protected and program or erase operations are
allowed. If the write protection bit is set to ‘0’ the device is protected and program or erase
operations are not allowed.
6.7.2 P/E/R controller bit (SR6)
The program/erase/read controller bit indicates whether the P/E/R controller is active or
inactive. When the P/E/R controller bit is set to ‘0’, the P/E/R controller is active (device is
busy); when the bit is set to ‘1’, the P/E/R controller is inactive (device is ready).
6.7.3 Error bit (SR0)
T he err or bit is use d to identify if any er rors have b een detected by the P/E/R controller. The
error bit is set to ’1’ when a program or era se operation has failed to write the correct data to
the memory. If the error bit is set to ‘0’ the operat ion has completed successfully.
6.7.4 SR5, SR4, SR3, SR2 and SR1 are reserved
Table 12. Status register bits
Bit Name Logic level Definition
SR7 Write protection '1' Not protected
'0' Protected
SR6 Program/ erase/ read controller '1' P/E/R C inactive, device ready
'0' P/E/R C active, device busy
SR5, SR4, SR3, SR2, SR1 Reserved Don’t care
Numonyx SLC SP 70 nm Device operations
210403 - Rev 4 27/51
6.8 Read electronic signature
The device cont ains a manufacturer code and device code. To read these codes two steps
are required :
1. first use one bus write cycle to issue the Read Electronic Signature command (90h),
followed by an address input of 00h
2. then perform two bus read operations – the first reads the manufacturer code and the
second, the device code. Further bus read o perations are ignored.
Refer to Table 13: Electronic signature, for information on the addresses.
SR0 Generic error ‘1’ Error – operation failed
‘0’ No error – operation successful
Table 12. Status register bits
Bit Name Logic level Definition
Table 13. Electronic signature
Part number I/O organiza tion Supply voltage Manufacturer code Device code
NAND512W3A2S x8 3 V 20h 76h
NAND512W4A2S x16 0020h 0056h
NAND512R3A2S x8 1.8 V 20h 36h
NAND512R4A2S x16 0020h 0046h
Software algorithms Numonyx SLC SP 70 nm
28/51 210403 - Rev 4
7 Software algorithms
This section gives inform at i on on th e software algo rit hm s th at Nu mo nyx re co mm e nd s to
implement to manage the bad blocks and e xt en d th e lifet im e of the NAND device.
NAND Flash memories are progr ammed and er ased by Fowler-Nor dheim tunnelin g using a
high voltage. Exposing the device to a high voltage for extended periods can cause the
oxide layer to be damaged. For this reason, the number of program and erase cycles is
limited (see Table 15: Program, erase times and program erase endur ance cycles for value)
and it is recommended to implement garbage collection, a wear-leveling algorithm and an
error correct i on cod e, to ext en d th e nu m be r of pro gr am an d er as e cycle s an d inc re as e the
data retention.
To help integrate a NAND memory into an application Numonyx can provide a full range of
software solutions: file system, sector management, driver s, and code management.
Contact the nearest Numo nyx sales office or visit www.numonyx.com for more details.
7.1 Bad block management
Devices with bad blocks have the same quality level and the same AC and DC
characterist ics as de vic es wh er e all the blo cks are valid. A bad block does not affect the
performance of valid blocks because it is isolated from the bit line and common source line
by a select transistor.
The devices are supplied with all the locations inside valid blocks erased (FFh). The bad
block information is written prior to shipping. Any block, where the 1st and 6th Bytes (x8
device)/1st Word (x16 device), in the spare area of the 1st page, does not contain FFh is a
bad block.
The bad block information must be read before any erase is attempted as the bad block
information may be erased. For the system to be able to reco gnize the bad blocks based on
the original information it is recommended to create a bad block t able following the flowchart
shown in Figure 15.
7.2 NAND Flash memory failure modes
Over the lifetime of the device additional ba d blocks may develop.
To implement a highly reliable system, all the possible failure modes must be considered:
lProgram/erase failure: in this case the block has to be replaced by copying the data to
a valid block. These additional bad blocks can be identified as attempts to program or
erase them will give errors in the status register.
As the failure of a page progr am operation does not af fect the data in other p ages in the
same block, the block can be replaced by re-programming the current data and
copying the rest of the replaced block to an available valid block. The Copy Back
Program command can be used to copy the data to a valid block. See Section 6.4:
Copy back program for more details
lRead failure: in this case, ECC correction must be implemented. To efficiently use the
memory spac e, it is mandatory to recover single-bit errors, which occur during read
operations, by using ECC without replacing the whole block.
Numonyx SLC SP 70 nm Software algorithms
210403 - Rev 4 29/51
Refer to Table 14 for the procedure to follow if an error occurs during an operation.
Figure 15. Bad block management flowchart
Table 14. NAND Flash failure modes
Operation Procedure
Erase Block Replacement
Program Block Replacement
Read ECC
AI07588C
START
END
NO
YES
YES
NO
Block Address =
Block 0
Data
= FFh?
Last
block?
Increment
Block Address
Update
Bad Block table
Software algorithms Numonyx SLC SP 70 nm
30/51 210403 - Rev 4
7.3 Garbage collection
When a data page needs to be modified, it is faster to write to the first available page, and
the previous page is marked as invalid . After several updates it is necessary to remove
invalid pages to free some memory space.
To free this memory space and allow further program operations it is recommended to
implement a garbage collection algorithm. In a garbage collection software the valid pages
are copied into a free are a an d th e blo ck co ntaining the invalid pages is erased (se e
Figure 16).
Figure 16. Garbage collection
7.4 Wear-leveling algorithm
For write-intensive applications, it is recommended to implement a wear-leveling algorithm
to monitor and spread the number of write cycles per block.
In memories that do not use a wear-leveling algorithm not all blocks get used at the same
rate.
The wear-leveling algorithm ensures that equal use is made of all the available write cycles
for each block. There are two wear-leveling levels:
lFirst level wear-leveling, new data is programmed to the free blocks that have had the
fewest write cycles
lSecond level wear-leveling, long-lived data is copied to another block so that the
original block can be used for more frequently-changed data.
The second level wear-leveling is trig gered when the difference between the maximum and
the minimum number of write cycles per block reaches a specific threshold.
7.5 Error correction code
Users must implement an error correction code (ECC) to identify and correct erro rs in the
data stored in the NAND Flash memories.
The ECC implemented must be able to correct 1 bit every 512 Bytes. Sensible data stored
in the spare area must be covered by ECC as well.
Valid
page
Invalid
page Free
page
(erased)
Old area
AI07599B
New area (after GC)
Numonyx SLC SP 70 nm Software algorithms
210403 - Rev 4 31/51
7.6 Hardware simulation models
7.6.1 Behavioral simulation models
Denali software corporation models are platform independ ent functional models designed to
assist customers in performing entire system simulations (typical VHDL/Verilog). These
models describe the logic behavior and timings of NAND Flash devices, and so allow
software to be developed before hardware.
7.6.2 IBIS simulations models
IBIS (I/O buffer information specification) models describe the behavior of the I/O buffers
and electrical characteristics of Flash devices.
These models provide informa tion such as AC characteristics, rise/fall times and package
mechanical dat a, all of which ar e measured or simulated at volt age and temperatur e ranges
wider than those allowed by target specifications.
IBIS models are used to simulate PCB connections and can be used to resolve compatibility
issues when upgrading devices. They can be imported into SPICETOOLS.
Program and erase times and end urance cycles Numonyx SLC SP 70 nm
32/51 210403 - Rev 4
8 Program and erase times and endurance cycles
The program and er ase times and the number of p rogram/erase cycles per block ar e shown
in Table 15.
9 Maximum ratings
Stressing the device above the ratings listed in Table 16: Absolute maximum ratings, may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any ot he r co nd itio ns abo ve tho se ind i ca te d in th e op er at ing sec tion s of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Table 15. Program, erase times and program erase endurance cycles
Parameters NAND Flash Unit
Min Typ Max
Page program time 200 500 µs
Block erase time 23ms
Program/erase cycles per block (with ECC) 100,000 cycles
Data retention 10 years
Table 16. Absolute maximum ratings
Symbol Parameter Value Unit
Min Max
TBIAS Temperature under bias – 50 125 °C
TSTG Storage temperature – 65 150 °C
TLEAD Lead temperature during soldering 260 °C
VIO(1) Input or output voltage 1.8 V devices – 0.6 2.7 V
3 V devices – 0.6 4.6 V
VDD Supply voltage 1.8 V devices – 0.6 2.7 V
3 V devices – 0.6 4.6 V
1. Minimum voltage may undershoot to –2 V for less than 20 ns during transitions on input and I/O pins. Maximum voltage
may overshoot to VDD + 2 V for less than 20 ns during transitions on I/O pins.
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 33/51
10 DC and AC parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characterist ics of th e de vice. The paramete rs in the DC and AC characteristics tables that
follow, are derived from tests performed un der the measurement conditions su mmarized in
Table 17: Operating and AC measureme nt conditions. Designers should check that the
operating conditions in their circuit match the measurement conditions when relying on the
quoted pa rameters.
Table 17. Operating and AC measurement conditions
Parameter NAND Flash Units
Min Max
Supply voltage (VDD)1.8 V devices 1.7 1.95 V
3 V devices 2.7 3.6
Ambient temperature (TA) Grade 6 –40 85 °C
Load capacitance (CL) (1 TTL GATE
and CL)1.8 V devices 30 pF
3 V devices 50
Input pulses voltages 1.8 V devices 0 VDD V
3 V devices 0.4 2.4
Input and output timing ref. voltages 1.8 V devices 0.9 V
3 V devices 1.5
Input rise and fall times 5 ns
Output circuit resistors, Rref 8.35 k
Table 18. Capacitance(1)(2)
1. TA = 25 °C, f = 1 MHz. CIN and CI/O are not 100% tested.
2. Input/output capacitances double on stacked devices.
Symbol Parameter Test conditions Typ Max Unit
CIN Input capacitance VIN = 0 V 10 pF
CI/O Input/output
capacitance VIL = 0 V 10 pF
DC and AC parameters Numonyx SLC SP 70 nm
34/51 210403 - Rev 4
M
Figure 17. Equivalent testing circuit for AC characteristics measurement
Ai11085
NAND flash
CL
2Rref
VDD
2Rref
GND
GND
Table 19. DC characteristics, 1.8 V devices(1)
Symbol Parameter Test conditions Min Typ Max Unit
IDD1
Operating current
Sequential
read tRLRL minimum
E=V
IL, IOUT =0mA –815mA
IDD2 Program ––815mA
IDD3 Erase ––815mA
IDD4 Standby current (TTL) E=VDD-0.2, WP=0V/VDD – – 1 mA
IDD5 Standby current (CMOS) E=VDD-0.2, WP=0/VDD –10 50 µA
ILI Input leakage current VIN= 0 to VDDmax – – ±10 µA
ILO Output leakage current VOUT= 0 to VDDmax – – ±10 µA
VIH Input high voltage – VDD-0.4 – VDD+0.3 V
VIL Input low voltage –0.3 –0.4 V
VOH Output high voltage level IOH = 100 µA VDD-0.1 – – V
VOL Output low voltage level IOL = 100 µA – – 0.1 V
IOL (RB)Output low current (RB) VOL = 0.1 V 3 4 mA
VLKO VDD supply voltage (erase and
program lockout) – – – 1.1 V
1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 35/51
Table 20. DC characteristics, 3 V devices(1)
Symbol Parameter Test cond itions Min Typ Max Unit
IDD1
Operating current
Sequential
read tRLRL minimum
E=V
IL, IOUT =0mA –1020mA
IDD2 Program – – 10 20 mA
IDD3 Erase – – 10 20 mA
IDD4 Standby current (TTL) E=VIH, WP=0V/VDD ––1mA
IDD5 Standby current (CMOS) E=VDD-0.2, WP=0/VDD –10 50 µA
ILI Input leakage current VIN= 0 to VDDmax – – ±10 µA
ILO Output leakage current VOUT= 0 to VDDmax – – ±10 µA
VIH Input high voltage –2.0 – VDD+0.3 V
VIL Input low voltage –0.3 –0.8 V
VOH Output high voltage level IOH = 400 µA 2.4 – – V
VOL Output low voltage level IOL = 2.1 mA – – 0.4 V
IOL (RB)Output low current (RB) VOL = 0.4 V 810 mA
VLKO VDD supply voltage (erase and
program lockout) – – – 1.5 V
1. Standby and leakage currents refer to a single die device. For a multiple die device, their value must be multiplied for the
number of dice of the stacked device, while the active power consumption depends on the number of dice concurrently
executing different operations.
Table 21. AC characteristics for command, address, data input
Symbol Alt.
symbol Parameter 1.8 V
devices 3 V
devices Unit
tALLWH tALS Address Latch Low to Write Enable High AL setup time Min 25 15 ns
tALHWH Address Latch High to Write Enable High
tCLHWH tCLS Command Latch High to Write Enable High CL setup time Min 25 15 ns
tCLLWH Command Latch Low to Write Enable High
tDVWH tDS Data Valid to Write Enable High Data setup time Min 20 15 ns
tELWH tCS Chip Enable Low to Write Enable High E setup time Min 30 20 ns
tWHALH tALH Write Enable High to Address Latch High AL hold time Min 10 5ns
tWHALL Write Enable High to Address Latch Low
tWHCLH tCLH Write Enable High to Command Latch High CL hold time Min 10 5ns
tWHCLL Write Enable High to Command Latch Low
tWHDX tDH Write Enable High to Data Transition Data hold time Min 10 5ns
tWHEH tCH Wr ite Enable High to Chip Enable High E hold time Min 10 5ns
tWHWL tWH Write Enable High to Write Enable Low W High hold
time Min 15 10 ns
tWLWH tWP Write Enable Low to Write Enable High W pulse width Min 25 15 ns
tWLWL tWC Write Enable Low to Write Enable Low Write cycle time Min 45 30 ns
DC and AC parameters Numonyx SLC SP 70 nm
36/51 210403 - Rev 4
Table 22. AC characteristics for operations
Symbol Alt.
symbol Parameter 1.8 V
devices 3 V
devices Unit
tALLRL1 tAR Address Latch Low to
Read Enabl e Lo w Read electronic signature Min 10 10 ns
tALLRL2 Read cycle Min 10 10 ns
tBHRL tRR Ready/Busy High to Read Enable Low Min 20 20 ns
tBLBH1
Ready/Busy Low to
Ready/Busy High
Read busy time Max 15 12 µs
tBLBH2 tPROG Program busy time Max 500 500 µs
tBLBH3 tBERS Erase busy time Max 3 3 ms
tBLBH4 tRST
Reset busy time, during ready Max 5 5 µs
Reset busy time, during read Max 5 5 µs
Reset busy time, during program Max 10 10 µs
Reset busy time, during erase Max 500 500 µs
tCLLRL tCLR Command Latch Low to Read Enable Low Min 10 10 ns
tDZRL tIR Data Hi-Z to Read Enable Low Min 0 0 ns
tEHQZ tCHZ Chip Enable High to Output Hi-Z Max 30 30 ns
tELQV tCEA Chip Enable Low to Output Valid Max 45 35 ns
tRHRL tREH Read Enable High to
Read Enable Low Read En able High hold time Min 15 10 ns
tRHQZ tRHZ Read Enable High to Output Hi-Z Max 30 30 ns
tEHQX TOH Chip Enable High or Read Enable High to Output Hold Min 10 10 ns
tRHQX
tRLRH tRP Read Enable Low to
Read Enable High Read Enable pulse width Min 25 15 ns
tRLRL tRC Read Enable Low to
Read Enabl e Lo w Read cycle time Min 50 30 ns
tRLQV tREA Read Enable Low to
Output Valid Read Enable access time Max 30 18 ns
Read ES access time(1)
tWHBH tRWr ite Enable High to
Ready/Busy High Read busy time Max 15 12 µs
tWHBL tWB Wr ite Enable High to Ready/Busy Low Max 100 100 ns
tWHRL tWHR Write Enable High to Read Enable Low Min 60 60 ns
tVHWH
tVLWH(2) tWW Write protection time Min 100 100 ns
1. ES = electronic signature.
2. During a program/erase enable operation, tVHWH is the delay from WP High to W High. During a program/erase disable
operation, tVLWH is the delay from WP Low to W High.
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 37/51
Figure 18. Command Latch AC waveforms
Figure 19. Address Latch AC waveforms
ai13105
CL
E
W
AL
I/O
tCLHWH
tELWH
tWHCLL
tWHEH
tWLWH
tALLWH tWHALH
Command
tDVWH tWHDX
(CL Setup time) (CL Hold time)
(Data Setup time) (Data Hold time)
(ALSetup time) (AL Hold time)
H(E Setup time) (E Hold time)
ai13106
CL
E
W
AL
I/O
tWLWH
tELWH tWLWL
tCLLWH
tWHWL
tALHWH
tDVWH
tWLWL tWLWL
tWLWHtWLWH tWLWH
tWHWL tWHWL
tWHDX
tWHALL
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
tWHALL
Adrress
cycle 1
tWHALL
(AL Setup time)
(AL Hold time)
Adrress
cycle 4
Adrress
cycle 3
Adrress
cycle 2
(CL Setup time)
(Data Setup time)
(Data Hold time)
(E Setup time)
Adrress
cycle 5
tWLWL
tWLWH
tDVWH
tWHDX
tWHWL
tWHALL
DC and AC parameters Numonyx SLC SP 70 nm
38/51 210403 - Rev 4
Figure 20. Data Input Latch AC waveforms
Figure 21. Sequential data output after read AC waveforms
1. CL = Low, AL = Low, W = High.
tWHCLH
CL
E
AL
W
I/O
tALLWH
tWLWL
tWLWH
tWHEH
tWLWH
tWLWH
Data In 0 Data In 1 Data In
Last
tDVWH
tWHDX
tDVWH
tWHDX
tDVWH
tWHDX
ai13107
(Data Setup time)
(Data Hold time)
(ALSetup time)
(CL Hold time)
(E Hold time)
tEHQX
tEHQZ
ai08031b
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 39/51
Figure 22. Read status register AC waveforms
Figure 23. Read electroni c signature AC waveforms
1. Refer to Table 13 for the values of the manufacturer and device codes.
tEHQX
ai08032c
tCLHWH
tELWH
90h 00h Man.
code Device
code
CL
E
W
AL
R
I/O
tRLQV
Read Electronic
Signature
Command
1st Cycle
Address Manufacturer and
Device Codes
ai08039b
(Read ES Access time)
tALLRL1
DC and AC parameters Numonyx SLC SP 70 nm
40/51 210403 - Rev 4
Figure 24. Page read A/read B operation AC waveforms
CL
E
W
AL
R
I/O
RB
tWLWL
tWHBL
tALLRL2
00h or
01h
Data
NData
N+1 Data
N+2 Data
Last
tWHBH tRLRL
tEHQZ
tRHQZ
ai08033c
Busy
Command
Code Address N Input Data Output
from Address N to Last Byte or Word in Page
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Read Cycle time)
tRLRH
tBLBH1
tRHQX
tEHQX
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 41/51
Figure 25. Read C operation, one page AC waveforms
1. A0-A7 is the address in the spare memory area, where A0-A3 are valid and A4-A7 are don’t care.
CL
E
W
AL
R
I/O
RB
tWHALL
Data M Data
Last
tALLRL2
ai08035b
tWHBH
tBHRL
50h Add. M
cycle 1 Add. M
cycle 4
Add. M
cycle 3
Add. M
cycle 2
Busy
Command
Code Address M Input Data Output from M to
Last Byte or Word in Area C
DC and AC parameters Numonyx SLC SP 70 nm
42/51 210403 - Rev 4
Figure 26. Page program AC waveforms
CL
E
W
AL
R
I/O
RB
SR0
ai08037
N
Last 10h
70h
80h
Page Program
Setup Code Confirm
Code Read Status Register
tWLWL tWLWL tWLWL
tWHBL
tBLBH2
Page
Program
Address Input Data Input
Add.N
cycle 1 Add.N
cycle 4
Add.N
cycle 3
Add.N
cycle 2
(Write Cycle time)
(Program Busy time)
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 43/51
Figure 27. Block erase AC waveforms
Figure 28. Reset AC waveforms
D0h60h SR0
70h
ai08038b
tWHBL
tWLWL
tBLBH3
Block Erase
Setup Command Block Erase
CL
E
W
AL
R
I/O
RB
Confirm
Code Read Status Register
Block Address Input
(Erase Busy time)
(Write Cycle time)
Add.
cycle 1 Add.
cycle 3
Add.
cycle 2
W
R
I/O
RB
tBLBH4
AL
CL
FFh
ai08043
(Reset Busy time)
DC and AC parameters Numonyx SLC SP 70 nm
44/51 210403 - Rev 4
Figure 29. Program/erase enable waveforms
Figure 30. Program/erase disable waveforms
10.1 Ready/Busy signal electrical characteristics
Figure 31, Figure 32 and Figure 33 show the ele ctrical characteristics for the Ready/Busy
signal. The value required for the resistor RP can be calculate d using the following equation:
So,
where IL is the sum of the input curren t s of al l the devices tied to the Re ady/Busy signa l. RP
max is determined by the maximum value of tr.
W
RB
tVHWH
ai12477
WP
I/O 80h 10h
W
RB
tVLWH
ai12478
WP
I/O 80h 10h
High
RPmin VDDmax VOLmax
–
IOL IL
+
-------------------------------------------------------------=
RPmin 1.8V
1.85V
3mA IL
+
---------------------------=
RPmin 3V 3.2V
8mA IL
+
---------------------------=
Numonyx SLC SP 70 nm DC and AC parameters
210403 - Rev 4 45/51
Figure 31. Ready/Busy AC waveform
Figure 32. Ready/Busy load circuit
NI3087
busy
VOH
ready VDD
VOL
tftr
1.8 V device - VOL: 0.1 V, VOH : VDD - 0.1 V
3.3 V device - VOL: 0.4 V, VOH : 2.4 V
AI07563B
RP
VDD
VSS
RB
DEVICE
Open Drain Output
ibusy
DC and AC parameters Numonyx SLC SP 70 nm
46/51 210403 - Rev 4
Figure 33. Resistor value versus waveform timings for Ready/Busy signal
1. T = 25°C.
10.2 Data protection
The Numonyx NAND device is designed to guarantee data protection during power
transitions.
A VDD detection circuit disables all NAND operations, if VDD is below the VLKO threshold.
In the VDD range from VLKO to the lower limit of nominal range, the WP p in sh ou ld be k ept
Low (VIL) to guarantee hardware protection during power tra ns itio ns as shown in the figure
below (Figure 34).
Figure 34. Data protection
Ai13188
VLKO
VDD
WP
Nominal Range
Locked
Locked
Numonyx SLC SP 70 nm Package mechanic al
210403 - Rev 4 47/51
11 Package mechanical
To meet environmental requirements, Numonyx offers these devices in RoHS compliant
packages, which have a lead-free second-level interconnect. The category of second-level
interconnect is marked on the package and on the inner box label, in compliance with
JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also
marked on the inner box label.
RoHS compliant specifications are available at www.numonyx.com.
Figure 35. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, pack age outline
1. Drawing is not to scale.
TSOP-G
B
e
DIE
C
LA1 α
E1
E
A
A2
1
24
48
25
D1
L1
CP
Table 23. TSOP48 - 48 lead plastic thin small outline, 12 x 20 mm, mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A1.200.047
A1 0.10 0.05 0.15 0.004 0.002 0.006
A2 1.00 0.95 1.05 0.039 0.037 0.041
B 0.22 0.17 0.27 0.009 0.007 0.011
C 0.10 0.21 0.004 0.008
CP 0.08 0.003
D1 12.00 11.90 12.10 0.472 0.468 0.476
E 20.00 19.80 20.20 0.787 0.779 0.795
E1 18.40 18.30 18.50 0.724 0.720 0.728
e 0.50 – – 0.020 – –
L 0.60 0.50 0.70 0.024 0.020 0.028
L1 0.80 0.031
3° 0° 5° 3° 0° 5°
Package mechanical Numonyx SLC SP 70 nm
48/51 210403 - Rev 4
Figure 36. VFBGA63 9x11x1.05mm - 6x8+15, 0.8mm pitch, package outline
1. Drawing is not to scale.
E
D
e
D1
SD FD
SE
b
A2
FE
A1
A
BGA-Z75
ddd
FD1
D2
E2 E1
e
FE1
BALL "A1"
Table 24. VFBGA63 9 x 11 x 1.05 mm - 6 x 8 +15 active ball array, 0.8 mm pitch, mechanical data
Symbol millimeters inches
Typ Min Max Typ Min Max
A 1.05 0.041
A1 0.25 0.010
A2 0.65 0.026
b 0.45 0.40 0.50 0.018 0.016 0.020
D 9.00 8.90 9.10 0.354 0.350 0.358
D1 4.00 0.157
D2 7.20 0.283
ddd 0.10 0.004
E 11.00 10.90 11.10 0.433 0.429 0.437
E1 5.60 0.220
E2 8.80 0.346
e 0.80 0.031
FD 2.50 0.098
FD1 0.90 0.035
FE 2.70 0.106
FE1 1.10 0.043
SD 0.40 0.016
SE 0.40 0.016
Numonyx SLC SP 70 nm Ordering information
210403 - Rev 4 49/51
12 Ordering information
Note: Not all combinations are necessarily available. For a list of available devices or for further
information on any aspect of these products, please contact your nearest Numonyx sales
office.
Table 25. Ordering information scheme
Example: NAND512W3A 2 S ZA 6 E
Device type
NAND = NAND Flash memory
Density
512 = 512 Mbit
Operating voltage
R = VDD = 1.7 to 1.95 V
W = VDD = 2.7 to 3.6 V
Bus wid th
3 = x8
4 = x16
Family identifier
A = 528 Byte/264 Word page
Device op tions
0 = No option (Chip Enable ‘care’; sequential row read enabled)
2 = Chip Enable don’ t care enabled
Product version
S = fifth version
Package
N = TSOP48 12 x 20 mm
ZA = VFBGA63 9 x 11 x 1.05 mm
Temperatu re range
6 = –40°C to 85°C
X = –40°C to 85°C; included in product longevity program (PLP)
Option
E = RoHS compliant package, standard packing
F = RoHS compliant package, tape & reel packing
Revision history Numonyx SLC SP 70 nm
50/51 210403 - Rev 4
13 Revision history
Table 26. Document revision history
Date Revision Changes
03-Feb-2010 1 Initial release.
29-Jul-2010 2 Added information about 1.8 V devices.
25-Mar-2011 3 Removed “Preliminary Data” status from document.
17-Oct-2012 4 Added option X under temperature range in ordering information
table
Numonyx SLC SP 70 nm
51/51
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TER M S AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DIS CLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PUR POSE,
MERCHANTABILITY, OR I NFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications an d product descriptions a t any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to th e
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such pat ents, trademarks, cop yrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no re sponsibility whatsoeve r for conflicts or incomp atibilities arising from future changes to them.
Contact your local Numonyx sales office or your dis tributor to obtain the latest specifications and before placing your pro duct order.
Copies of doc uments which have an order number and are refer enced in thi s document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or reg istered trademark of Numony x or its subsidiaries in the United States and other co untries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx B.V. All Rights Reserved.