For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
General Description
The MAX9210/MAX9214/MAX9220/MAX9222 deserialize
three LVDS serial data inputs into 21 single-ended LVC-
MOS/LVTTL outputs. A parallel rate LVDS clock received
with the LVDS data streams provides timing for deserial-
ization. The outputs have a separate supply, allowing
1.8V to 5V output logic levels.
The MAX9210/MAX9214/MAX9220/MAX9222 feature
programmable DC balance, which allows isolation
between a serializer and deserializer using AC-coupling.
Each deserializer decodes data transmitted by one of
MAX9209/MAX9213 serializers.
The MAX9210/MAX9214 have rising-edge output
strobes, and when DC balance is not programmed, are
compatible with non-DC-balanced 21-bit deserializers
such as the DS90CR216A and DS90CR218A. The
MAX9220/MAX9222 have falling-edge output strobes.
Two frequency versions and two DC-balance default con-
ditions are available for maximum replacement flexibility
and compatibility with popular non-DC-balanced deserial-
izers. The transition time of the single-ended outputs is
increased on the low-frequency version parts
(MAX9210/MAX9220) for reduced EMI. The LVDS inputs
meet IEC 61000-4-2 Level 4 ESD specification, ±15kV for
Air Discharge and ±8kV Contact Discharge.
The MAX9210/MAX9214/MAX9220/MAX9222 are avail-
able in a TSSOP package, and operate over the -40°C to
+85°C temperature range.
Applications
Automotive Navigation Systems
Automotive DVD Entertainment Systems
Digital Copiers
Laser Printers
Features
♦Programmable DC Balance or Non-DC Balance
♦DC Balance Allows AC-Coupling for Wider Input
Common-Mode Voltage Range
♦As Low as 8MHz Operation (MAX9210/MAX9220)
♦Falling-Edge Output Strobe (MAX9220/MAX9222)
♦Slower Output Transitions for Reduced EMI
(MAX9210/MAX9220)
♦High-Impedance Outputs when PWRDWN is Low
Allow Output Busing
♦Pin Compatible with DS90CR216A/DS90CR218A
(MAX9210/MAX9214)
♦Fail-Safe Inputs in Non-DC-Balanced Mode
♦5V Tolerant PWRDWN Input
♦PLL Requires No External Components
♦Up to 1.785Gbps Throughput
♦Separate Output Supply Pins Allow Interface to
1.8V, 2.5V, 3.3V, and 5V Logic
♦LVDS Inputs Meet IEC 61000-4-2 Level and ISO
10605 ESD Requirements
♦LVDS Inputs Conform to ANSI TIA/EIA-644 LVDS
Standard
♦Low-Profile 48-Lead TSSOP Package
♦+3.3V Main Power Supply
♦-40°C to +85°C Operating Temperature Range
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-2864; Rev 5; 11/07
Functional Diagram and Pin Configurations appear at end
of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX9210EUM -40°C to +85°C 48 TSSOP
MAX9214EUM -40°C to +85°C 48 TSSOP
MAX9220EUM -40°C to +85°C 48 TSSOP
MAX9222EUM -40°C to +85°C 48 TSSOP
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
DC ELECTRICAL CHARACTERISTICS
(VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |VID| = 0.05V to
1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = VCCO = +3.3V, VID| = 0.2V, VCM = 1.25V, TA= +25°C). (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VCC to GND...........................................................-0.5V to +4.0V
VCCO to GND.........................................................-0.5V to +6.0V
RxIN_, RxCLK IN_ to GND ....................................-0.5V to +4.0V
PWRDWN to GND .................................................-0.5V to +6.0V
DCB/NC to GND.........................................-0.5V to (VCC + 0.5V)
RxOUT_, RxCLK OUT to GND .................-0.5V to (VCCO + 0.5V)
Continuous Power Dissipation (TA= +70°C)
48-Pin TSSOP (derate 16mW/°C above +70°C) ....... 1282mW
Storage Temperature Range .............................-65°C to +150°C
Junction Temperature......................................................+150°C
ESD Protection
Human Body Model (RD= 1.5kΩ, CS= 100pF)
All Pins to GND ..........................................................±5kV
IEC 61000-4-2 (RD= 330Ω, CS= 150pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND ...........±8kV
Air Discharge (RxIN_, RxCLK IN_) to GND ..................±15kV
ISO 10605 (RD= 2kΩ, CS= 330pF)
Contact Discharge (RxIN_, RxCLK IN_) to GND ...........±8kV
Air Discharge (RxIN_, RxCLK IN_) to GND ..................±25kV
Lead Temperature (soldering, 10s) .................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SINGLE-ENDED INPUTS (PWRDWN, DCB/NC)
PWRDWN 2.0 5.5
High-Level Input Voltage VIH DCB/NC 2.0 VCC +
0.3
V
Low-Level Input Voltage VIL -0.3 +0.8 V
Input Current IIN VIN = high or low, PWRDWN = high or low -20 +20 µA
Input Clamp Voltage VCL ICL = -18mA -1.5 V
SINGLE-ENDED OUTPUTS (RxOUT_, RxCLK OUT)
IOH = -100µA VCCO -
0.1
RxCLK OUT VCCO -
0.25
MAX9210/
MAX9220
RxOUT_ VCCO -
0.40
High-Level Output Voltage VOH
IOH = -2mA
MAX9214/MAX9222 VCCO -
0.25
V
IOL = 100µA 0.1
RxCLK OUT 0.2
MAX9210/
MAX9220 RxOUT_ 0.26
Low-Level Output Voltage VOL IOL = 2mA
MAX9214/MAX9222 0.2
V
High-Impedance Output Current IOZ
PWRDWN = low,
VOUT_ = -0.3V to VCCO + 0.3V -20 20 µA
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 3
DC ELECTRICAL CHARACTERISTICS (continued)
(VCC = +3.0V to +3.6V, VCCO = +3.0V to +5.5V, PWRDWN = high, DCB/NC = high or low, differential input voltage |VID| = 0.05V to
1.2V, input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise noted. Typical values are at
VCC = VCCO = +3.3V, VID| = 0.2V, VCM = 1.25V, TA= +25°C). (Notes 1, 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RxCLK OUT -10 -40
MAX9210/
MAX9220 RxOUT_ -5 -20
VCCO = 3.0V
to 3.6V,
VOUT = 0
MAX9214/MAX9222 -10 -40
RxCLK OUT -28 -75
MAX9210/
MAX9220 RxOUT_ -14 -37
Output Short-Circuit Current
(Note: Short one output at a
time.)
IOS
VCCO = 4.5V
to 5.5V,
VOUT = 0
MAX9214/MAX9222 -28 -75
mA
LVDS INPUTS
Differential Input High Threshold VTH 50 mV
Differential Input Low Threshold VTL -50 mV
Input Current IIN+,
IIN-
PWRDWN = high or low -25 +25 µA
Power-Off Input Current IINO+,
IINO-
VCC = VCCO = 0 or open,
DCB/NC, PWRDWN = 0 or open -25 +25 µA
PWRDWN = high or low, Figure 1
Input Resistor 1 RIN1 VCC = VCCO = 0 or open, Figure 1 42 78 kΩ
PWRDWN = high or low, Figure 1
Input Resistor 2 RIN2 VCC = VCCO = 0 or open, Figure 1 246 410 kΩ
POWER SUPPLY
8MHz 32 42
16MHz 46 57
MAX9210/
MAX9220
34MHz 81 98
16MHz 52 63
34MHz 86 106
CL = 8pF, worst-
case pattern,
DC- balanced
mode; VCC = VCCO
= 3.0V to 3.6V,
Figure 2
MAX9214/
MAX9222 66MHz 152 177
10MHz 33 42
20MHz 46 58
33MHz 67 80
MAX9210/
MAX9220
40MHz 78 94
20MHz 53 64
33MHz 72 85
40MHz 81 99
66MHz 127 149
Worst-Case Supply Current ICCW
CL = 8pF, worst
case pattern,
non-DC-balanced
mode; VCC = VCCO
= 3.0V to 3.6V,
Figure 2 MAX9214/
MAX9222
85MHz 159 186
mA
Power-Down Supply Current ICCZ PWRDWN = low 50 µA
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
4 _______________________________________________________________________________________
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground
except VTH and VTL.
Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production
tested at TA= +25°C.
Note 3: AC parameters are guaranteed by design and characterization, and are not production tested. Limits are set at ±6 sigma.
Note 4: CLincludes probe and test jig capacitance.
Note 5: RCIP is the period of RxCLK IN. RCOP is the period of RxCLK OUT. RCIP = RCOP.
Note 6: RSKM measured with ≤150ps cycle-to-cycle jitter on RxCLK IN.
AC ELECTRICAL CHARACTERISTICS
(VCC = VCCO = +3.0V to +3.6V, 100mVP-P at 200kHz supply noise, CL= 8pF, PWRDWN = high, DCB/NC = high or low, differential
input voltage |VID| = 0.1V to 1.2V, Input Common Mode Voltage VCM = |VID/2| to 2.4V - |VID/2|, TA= -40°C to +85°C, unless otherwise
noted. Typical values are at VCC = VCCO = +3.3V, |VID| = 0.2V, VCM = 1.25V, TA= 25°C). (Notes 3, 4, 5)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
RxOUT_ 3.52 5.04 6.24
MAX9210/
MAX9220 RxCLK OUT 2.2 3.15 3.9
Output Rise Time CLHT
0.1VCCO
to
0.9VCCO,
Figure 3 MAX9214/MAX9222 2.2 3.15 3.9
ns
RxOUT_ 1.95 3.18 4.35
MAX9210/
MAX9220 RxCLK OUT 1.3 2.12 2.9
Output Fall Time CHLT
0.9VCCO
to
0.1VCCO,
Figure 3 MAX9214/MAX9222 1.3 2.12 2.9
ns
8MHz 6600 7044
16MHz 2560 3137
34MHz 900 1327
DC-balanced mode,
Figure 4 (Note 6)
66MHz 330 685
10MHz 6600 7044
20MHz 2500 3300
40MHz 960 1448
RxIN Skew Margin RSKM
Non-DC-balanced mode,
Figure 4 (Note 6)
85MHz 330 685
ps
RxCLK OUT High Time RCOH Figures 5a, 5b 0.35 x
RCOP ns
RxCLK OUT Low Time RCOL Figures 5a, 5b 0.35 x
RCOP ns
RxOUT Setup to RxCLK OUT RSRC Figures 5a, 5b 0.30 x
RCOP ns
RxOUT Hold from RxCLK OUT RHRC Figures 5a, 5b 0.45 x
RCOP ns
RxCLK IN to RxCLK OUT Delay RCCD Figures 6a, 6b 4.9 6.17 8.1 ns
Deserializer Phase-Locked Loop
Set RPLLS Figure 7 32800
x RCIP ns
Deserializer Power-Down Delay RPDD Figure 8 100 ns
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 5
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
MAX9210 toc01
20
30
50
40
80
90
70
60
100
SUPPLY CURRENT (mA)
5152010 25 30 35 40
FREQUENCY (MHz)
MAX9220
DC-BALANCED MODE
WORST-CASE PATTERN
27 - 1 PRBS
WORST-CASE PATTERN AND PRBS
SUPPLY CURRENT vs. FREQUENCY
MAX9210 toc02
20
30
50
40
80
90
70
60
100
SUPPLY CURRENT (mA)
5152010 25 30 35 40
FREQUENCY (MHz)
MAX9220
NON-DC-BALANCED MODE
WORST-CASE PATTERN
27 - 1 PRBS
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
MAX9210 toc03
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
65503520
60
80
100
120
140
160
40
580
MAX9214
DC-BALANCED MODE
WORST-CASE PATTERN SUPPLY CURRENT
vs. FREQUENCY
MAX9210 toc04
FREQUENCY (MHz)
SUPPLY CURRENT (mA)
75 9060
30 45
60
80
100
120
160
40
15
140
MAX9214
NON-DC-BALANCED MODE
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9210 toc05
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
4.54.03.53.0
2
3
4
5
1
2.5 5.0
MAX9214
tF
tR
OUTPUT TRANSITION TIME
vs. OUTPUT SUPPLY VOLTAGE (VCCO)
MAX9210 toc06
OUTPUT SUPPLY VOLTAGE (V)
OUTPUT TRANSITION TIME (ns)
4.54.03.53.0
2
3
4
5
7
6
1
2.5 5.0
tF
tR
MAX9220
Typical Operating Characteristics
(VCC = VCCO = +3.3V, CL= 8pF, PWRDWN = high, differential input voltage ⏐VID⏐= 0.2V, input common-mode voltage VCM = 1.2V,
TA= +25°C, unless otherwise noted.)
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
6 _______________________________________________________________________________________
Pin Description
PIN
TSSOP NAME FUNCTION
1, 2, 4, 5, 45, 46, 47
RxOUT14–
RxOUT20 Channel 2 Single-Ended Outputs
3, 25, 32, 38, 44 GND Ground
6 DCB/NC
LVTTL/LVCMOS DC-Balance Programming Input:
MAX9210: pulled up to VCC
MAX9214: pulled up to VCC
MAX9220: pulled up to VCC
MAX9222: pulled up to VCC
See Table 1.
7, 13, 18 LVDS GND LVDS Ground
8 RxIN0- Inverting Channel 0 LVDS Serial Data Input
9 RxIN0+ Noninverting Channel 0 LVDS Serial Data Input
10 RxIN1- Inverting Channel 1 LVDS Serial Data Input
11 RxIN1+ Noninverting Channel 1 LVDS Serial Data Input
12 LVDS VCC LVDS Supply Voltage
14 RxIN2- Inverting Channel 2 LVDS Serial Data Input
15 RxIN2+ Noninverting Channel 2 LVDS Serial Data Input
16 RxCLK IN- Inverting LVDS Parallel Rate Clock Input
17 RxCLK IN+ Noninverting LVDS Parallel Rate Clock Input
19, 21 PLL GND PLL Ground
20 PLL VCC PLL Supply Voltage
22 PWRDWN 5V Tolerant LVTTL/LVCMOS Power-Down Input. Internally pulled down to GND. Outputs
are high impedance when PWRDWN = low or open.
23 RxCLK OUT Parallel Rate Clock Single-Ended Output. MAX9210/MAX9214, rising edge strobe.
MAX9220/MAX9222, falling edge strobe.
24, 26, 27, 29, 30, 31,
33
RxOUT0–
RxOUT6 Channel 0 Single-Ended Outputs
28, 36, 48 VCCO Output Supply Voltage
34, 35, 37, 39, 40, 41,
43
RxOUT7–
RxOUT13 Channel 1 Single-Ended Outputs
42 VCC Digital Supply Voltage
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 7
Detailed Description
The MAX9210/MAX9220 operate at a parallel clock fre-
quency of 8MHz to 34MHz in DC-balanced mode and
10MHz to 40MHz in non-DC-balanced mode. The
MAX9214/MAX9222 operate at a parallel clock frequency
of 16MHz to 66MHz in DC-balanced mode and 20MHz to
85MHz in non-DC-balanced mode. The transition times of
the single-ended outputs are increased on the
MAX9210/MAX9220 for reduced EMI.
DC-balanced or non-DC-balanced operation is con-
trolled by the DCB/NC pin (see Table 1 for DCB/NC
default settings and operating modes). In non-DC-bal-
anced mode, each channel deserializes 7 bits every
cycle of the parallel clock. In DC-balanced mode, 9 bits
are deserialized every clock cycle (7 data bits + 2 DC-
balance bits). The highest data rate in DC-balanced
mode for the MAX9214 and MAX9222 is 66MHz x 9 =
594Mbps. In non-DC-balanced mode, the maximum
data rate is 85MHz x 7 = 595Mbps.
DC Balance
Data coding by the MAX9209/MAX9213 serializers
(which are companion devices to the MAX9210/
MAX9214/MAX9220/MAX9222 deserializers) limits the
imbalance of ones and zeros transmitted on each chan-
nel. If +1 is assigned to each binary 1 transmitted and -1
is assigned to each binary 0 transmitted, the variation in
the running sum of assigned values is called the digital
sum variation (DSV). The maximum DSV for the data
channels is 10. At most, 10 more zeros than ones, or 10
more ones than zeros, are transmitted. The maximum
DSV for the clock channel is five. Limiting the DSV and
choosing the correct coupling capacitors maintains dif-
ferential signal amplitude and reduces jitter due to
droop on AC-coupled links.
VCC - 0.3V
VCC
RIN2
RIN1
RxIN_ + OR
RxCLK IN+
RxIN_ - OR
RxCLK IN-
RIN1
RIN1
RxIN_ + OR
RxCLK IN+
RxIN_ - OR
RxCLK IN-
RIN1
NON-DC-BALANCED MODE DC-BALANCED MODE
1.2V
Figure 1. LVDS Input Circuits
Table 1. DC-Balance Programming
DEVICE DCB/NC OUTPUT STROBE
EDGE OPERATING MODE OPERATING
FREQUENCY (MHz)
High or open DC balanced 8 to 34
MAX9210 Low Rising Non-DC balanced 10 to 40
High or open DC balanced 16 to 66
MAX9214 Low Rising Non-DC balanced 20 to 85
High or open DC balanced 8 to 34
MAX9220 Low Falling Non-DC balanced 10 to 40
High or open DC balanced 16 to 66
MAX9222 Low Falling Non-DC balanced 20 to 85
RCIP
RxCLK OUT
ODD RxOUT
EVEN RxOUT
RISING EDGE STROBE SHOWN.
Figure 2. Worst-Case Test Pattern
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
8 _______________________________________________________________________________________
IDEAL
MIN MAX
INTERNAL STROBE
IDEAL
RSKM RSKM
IDEAL SERIAL BIT TIME
1.3V
1.1V
Figure 4. LVDS Receiver Input Skew Margin
RxOUT_
RxCLK OUT
RCIP
RCOHRCOL
2.0V
0.8V
2.0V
0.8V
2.0V
2.0V
2.0V
0.8V 0.8V
RHRCRSRC
Figure 5a. Rising-Edge Output Setup/Hold and High/Low Times
RxOUT_
RxCLK OUT
RCIP
RCOH RCOL
2.0V
0.8V
2.0V
0.8V
2.0V 2.0V
0.8V 0.8V 0.8V
RHRCRSRC
Figure 5b. Falling-Edge Output Setup/Hold and High/Low Times
VID = 0
1.5V
RCCD
RxCLK IN
RxCLK OUT
Figure 6a. Rising-Edge Clock-IN to Clock-OUT Delay
RxCLK IN
RxCLK OUT
+
-
RCCD
1.5V
VID = 0
Figure 6b. Falling-Edge Clock-IN to Clock-OUT Delay
90%90%
10%10%
CHLTCLHT
RxOUT_ OR
RxCLK OUT RxOUT_ OR
RxCLK OUT
8pF
Figure 3. Output Load and Transition Times
PWRDWN
VCC
RxCLK IN
RxCLK OUT
3V
2V
RPLLS
HIGH-Z
Figure 7. Phase-Locked Loop Set Time
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
_______________________________________________________________________________________ 9
To obtain DC balance on the data channels, the serial-
izer parallel data is inverted or not inverted, depending
on the sign of the digital sum at the word boundary.
Two complementary bits are appended to each group
of 7 parallel input data bits to indicate to the MAX9210/
MAX9214/MAX9220/MAX9222 deserializers whether
the data bits are inverted (see Figures 9 and 10). The
deserializer restores the original state of the parallel
data. The LVDS clock signal alternates duty cycles of
4/9 and 5/9, which maintain DC balance.
AC-Coupling Benefits
Bit errors experienced with DC-coupling can be elimi-
nated by increasing the receiver common-mode voltage
range by AC-coupling. AC-coupling increases the com-
mon-mode voltage range of an LVDS receiver to nearly
TxIN_ IS DATA FROM THE SERIALIZER.
TxIN1
TxIN7TxIN8
TxIN14TxIN15
+
-
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN0TxIN1TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN7TxIN8TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
TxIN0
RxCLK IN
RxIN1
RxIN0
RxIN2
Figure 9. Deserializer Serial Input in Non-DC-Balanced Mode
TxIN_, DCA_, AND DCB_ ARE DATA FROM THE SERIALIZER.
DCA0
DCB1DCA1
DCB2DCA2
CYCLE N + 1CYCLE NCYCLE N - 1
TxIN2TxIN6 TxIN3TxIN4TxIN5
TxIN9TxIN13 TxIN10TxIN11TxIN12
TxIN2TxIN3TxIN4DCA0 TxIN5TxIN6DCB0
TxIN9TxIN10TxIN11DCA1 TxIN12TxIN13DCB1
TxIN16TxIN17TxIN18DCA2 TxIN19TxIN20DCB2
TxIN0TxIN1
TxIN7TxIN8
TxIN14TxIN15TxIN16TxIN20 TxIN17TxIN18TxIN19
DCB0
RxCLK IN
RxIN1
RxIN0
RxIN2
TxIN1
TxIN8
TxIN15
TxIN0
TxIN7
TxIN14
+
-
Figure 10. Deserializer Serial Input in DC-Balanced Mode
0.8V
PWRDWN
RxCLK IN
RxOUT_
RxCLK OUT
RPDD
HIGH-Z
Figure 8. Power-Down Delay
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
10 ______________________________________________________________________________________
the voltage rating of the capacitor. The typical LVDS dri-
ver output is 350mV centered on an offset voltage of
1.25V, making single-ended output voltages of 1.425V
and 1.075V. An LVDS receiver accepts signals from 0 to
2.4V, allowing approximately ±1V common-mode differ-
ence between the driver and receiver on a DC-coupled
link (2.4V - 1.425V = 0.975V and 1.075V - 0V = 1.075V).
Common-mode voltage differences may be due to
ground potential variation or common-mode noise. If
there is more than ±1V of difference, the receiver is not
guaranteed to read the input signal correctly and may
cause bit errors. AC-coupling filters low-frequency
ground shifts and common-mode noise and passes
high-frequency data. A common-mode voltage differ-
ence up to the voltage rating of the coupling capacitor
(minus half the differential swing) is tolerated. DC-bal-
anced coding of the data is required to maintain the dif-
ferential signal amplitude and limit jitter on an
AC-coupled link. A capacitor in series with each output
of the LVDS driver is sufficient for AC-coupling.
However, two capacitors—one at the serializer output
and one at the deserializer input—provide protection in
case either end of the cable is shorted to a high voltage.
Applications Information
Selection of AC-Coupling Capacitors
Voltage droop and the DSV of transmitted symbols
cause signal transitions to start from different voltage
levels. Because the transition time is finite, starting the
signal transition from different voltage levels causes
timing jitter. The time constant for an AC-coupled link
needs to be chosen to reduce droop and jitter to an
acceptable level.
The RC network for an AC-coupled link consists of the
LVDS receiver termination resistor (RT), the LVDS driver
output resistor (RO), and the series AC-coupling capac-
itors (C). The RC time constant for two equal-value
7 : 1 1 : 7
77
100Ω
7 : 1 1 : 7
77
100Ω
7 : 1 1 : 7
77
100Ω
PLL PLL
100Ω
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
TRANSMISSION LINE
Figure 11. DC-Coupled Link, Non-DC-Balanced Mode
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 11
series capacitors is (C x (RT + RO))/2 (Figure 12). The
RC time constant for four equal-value series capacitors
is (C x (RT + RO))/4 (Figure 13).
RTis required to match the transmission line imped-
ance (usually 100Ω) and ROis determined by the LVDS
driver design (the minimum differential output resis-
tance of 78Ωfor the MAX9209/MAX9213 serializers is
used in the following example). This leaves the capaci-
tor selection to change the system time constant.
In the following example, the capacitor value for a
droop of 2% is calculated. Jitter due to this droop is
then calculated assuming a 1ns transition time:
C = - (2 x tBx DSV)/(ln (1 - D) x (RT+ RO)) (Eq 1)
where:
C = AC-coupling capacitor (F).
tB= bit time (s).
DSV = digital sum variation (integer).
ln = natural log.
D = droop (% of signal amplitude).
RT= termination resistor (Ω).
RO= output resistance (Ω).
Equation 1 is for two series capacitors (Figure 12). The
bit time (tB) is the period of the parallel clock divided by
9. The DSV is 10. See equation 3 for four series capaci-
tors (Figure 13).
The capacitor for 2% maximum droop at 8MHz parallel
rate clock is:
C = - (2 x tBx DSV)/(ln (1 - D) x (RT+ RO))
C = - (2 x 13.9ns x 10)/(ln (1 - 0.02) x (100Ω+ 78Ω))
C = 0.0773µF
Jitter due to droop is proportional to the droop and
transition time:
tJ= tTx D (Eq 2)
where:
tJ= jitter (s).
tT= transition time (s) (0 to 100%).
D = droop (% of signal amplitude).
Jitter due to 2% droop and assumed 1ns transition time is:
tJ= 1ns x 0.02
tJ= 20ps
(7 + 2):1 1:(9 - 2)
77
100Ω
(7 + 2):1 1:(9 - 2)
77
100Ω
(7 + 2):1 1:(9 - 2)
77
100Ω
PLL PLL
100Ω
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY, CERAMIC
SURFACE-MOUNT CAPACITORS
CAN ALSO BE PLACED AT THE
SERIALIZER INSTEAD OF THE DESERIALIZER.
Figure 12. Two Capacitors per Link, AC-Coupled, DC-Balanced Mode
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
12 ______________________________________________________________________________________
The transition time in a real system depends on the fre-
quency response of the cable driven by the serializer.
The capacitor value decreases for a higher frequency
parallel clock and for higher levels of droop and jitter.
Use high-frequency, surface-mount ceramic capacitors.
Equation 1 altered for four series capacitors (Figure 13) is:
C = - (4 x tBx DSV)/(ln (1 - D) x (RT+ RO)) (Eq 3)
Fail-Safe
The MAX9210/MAX9214/MAX9220/MAX9222 have fail-
safe LVDS inputs in non-DC-balanced mode (Figure 1).
Fail-safe drives the outputs low when the correspond-
ing LVDS input is open, undriven and shorted, or
undriven and parallel terminated. The fail-safe on the
LVDS clock input drives all outputs low. Fail-safe does
not operate in DC-balanced mode.
Input Bias and Frequency Detection
In DC-balanced mode, the inverting and noninverting
LVDS inputs are internally connected to +1.2V through
42kΩ(min) to provide biasing for AC-coupling (Figure 1).
A frequency-detection circuit on the clock input detects
when the input is not switching, or is switching at low
frequency. In this case, all outputs are driven low. To
prevent switching due to noise when the clock input is
not driven, bias the clock input to differential +15mV by
connecting a 10kΩ±1% pullup resistor between the
noninverting input and VCC, and a 10kΩ±1% pulldown
resistor between the inverting input and ground. These
bias resistors, along with the 100Ω±1% tolerance ter-
mination resistor, provide +15mV of differential input.
However, the +15mV bias causes degradation of
RSKM proportional to the slew rate of the clock input.
For example, if the clock transitions 250mV in 500ps,
the slew rate of 0.5mV/ps reduces RSKM by 30ps.
Unused LVDS Data Inputs
In non-DC-balanced mode, leave unused LVDS data
inputs open. In non-DC balanced mode, the input fail-
safe circuit drives the corresponding outputs low and no
pullup or pulldown resistors are needed. In DC-balanced
mode, at each unused LVDS data input, pull the inverting
input up to VCC using a 10kΩresistor, and pull the nonin-
verting input down to ground using a 10kΩresistor. Do
not connect a termination resistor. The pullup and pull-
down resistors drive the corresponding outputs low and
prevent switching due to noise.
(7 + 2):1 1:(9 - 2)
77
100Ω
(7 + 2):1 1:(9 - 2)
77
100Ω
(7 + 2):1 1:(9 - 2)
77
100Ω
PLL PLL
100Ω
MAX9209
MAX9213
MAX9210
MAX9214
MAX9220
MAX9222
TxOUT
TxCLK OUT
RxIN
RxCLK IN
21:3 SERIALIZER 3:21 DESERIALIZER
PWRDWN
RxCLK OUT
RxOUT
PWRDWN
TxCLK IN
TxIN
HIGH-FREQUENCY CERAMIC
SURFACE-MOUNT CAPACITORS
Figure 13. Four Capacitors per Link, AC-Coupled, DC-Balanced Mode
PWRDWN
Driving PWRDWN low puts the outputs in high imped-
ance, stops the PLL, and reduces supply current to
50µA or less. Driving PWRDWN high drives the outputs
low until the PLL locks. The outputs of two deserializers
can be bused to form a 2:1 mux with the outputs con-
trolled by PWRDWN. Wait 100ns between disabling one
deserializer (driving PWRDWN low) and enabling the
second one (driving PWRDWN high) to avoid con-
tention of the bused outputs.
Input Clock and PLL Lock Time
There is no required timing sequence for the applica-
tion or reapplication of the parallel rate clock (RxCLK
IN) relative to PWRDWN, or to a power-supply ramp for
proper PLL lock. The PLL lock time is set by an internal
counter. The maximum time to lock is 32,800 clock
periods. Power and clock should be stable to meet the
lock time specification. When the PLL is locking, the
outputs are low.
Power-Supply Bypassing
There are separate on-chip power domains for digital
circuits, outputs, PLL, and LVDS inputs. Bypass each
VCC, VCCO, PLL VCC, and LVDS VCC pin with high-fre-
quency, surface-mount ceramic 0.1µF and 0.001µF
capacitors in parallel as close to the device as possi-
ble, with the smallest value capacitor closest to the
supply pin.
Cables and Connectors
Interconnect for LVDS typically has a differential imped-
ance of 100Ω. Use cables and connectors that have
matched differential impedance to minimize impedance
discontinuities.
Twisted-pair and shielded twisted-pair cables offer
superior signal quality compared to ribbon cable and
tend to generate less EMI due to magnetic field cancel-
ing effects. Balanced cables pick up noise as common
mode, which is rejected by the LVDS receiver.
Board Layout
Keep the LVTTL/LVCMOS outputs and LVDS input sig-
nals separated to prevent crosstalk. A four-layer printed-
circuit board (PCB) with separate layers for power,
ground, LVDS inputs, and digital signals is recom-
mended.
ESD Protection
The MAX9210/MAX9214/MAX9220/MAX9222 ESD toler-
ance is rated for IEC 61000-4-2, Human Body Model and
ISO 10605 standards. IEC 61000-4-2 and ISO 10605
specify ESD tolerance for electronic systems. The IEC
61000-4-2 discharge components are CS= 150pF and
RD= 330Ω(Figure 14). For IEC 61000-4-2, the LVDS
inputs are rated for ±8kV Contact Discharge and ±15kV
Air Discharge. The Human Body Model discharge com-
ponents are CS= 100pF and RD= 1.5kΩ(Figure 15). For
the Human Body Model, all pins are rated for ±5kV
Contact Discharge. The ISO 10605 discharge compo-
nents are CS= 330pF and RD= 2kΩ(Figure 16). For ISO
10605, the LVDS inputs are rated for ±8kV Contact
Discharge and ±25kV Air Discharge.
5V Tolerant Input
PWRDWN is 5V tolerant and is internally pulled down to
GND. DCB/NC is not 5V tolerant. The input voltage
range for DCB/NC is nominally ground to VCC.
Normally, DCB/NC is connected to VCC or ground.
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100ΩRD
2kΩ
CS
330pF
Figure 16. ISO 10605 Contact Discharge ESD Test Circuit
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 13
CS
150pF STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
50Ω TO 100ΩRD
330Ω
Figure 14. IEC 61000-4-2 Contact Discharge ESD Test Circuit
STORAGE
CAPACITOR
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
CHARGE-CURRENT-
LIMIT RESISTOR
DISCHARGE
RESISTANCE
1MΩRD
1.5kΩ
CS
100pF
Figure 15. Human Body ESD Test Circuit
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
14 ______________________________________________________________________________________
Skew Margin (RSKM)
Skew margin (RSKM) is the time allowed for degrada-
tion of the serial data sampling setup and hold times by
sources other than the deserializer. The deserializer
sampling uncertainty is accounted for and does not
need to be subtracted from RSKM. The main outside
contributors of jitter and skew that subtract from RSKM
are interconnect intersymbol interference, serializer
pulse position uncertainty, and pair-to-pair path skew.
VCCO Output Supply and Power Dissipation
The outputs have a separate supply (VCCO) for interfacing
to systems with 1.8V to 5V nominal input logic levels. The
DC Electrical Characteristics table gives the maximum
supply current for VCCO = 3.6V with 8pF load at several
switching frequencies with all outputs switching in the
worst-case switching pattern. The approximate incremen-
tal supply current for VCCO other than 3.6V with the same
8pF load and worst-case pattern can be calculated using:
II= CTVI 0.5fCx 21 (data outputs)
+ CTVIfCx 1 (clock output)
where:
II= incremental supply current.
CT= total internal (CINT) and external (CL) load capaci-
tance.
VI= incremental supply voltage.
fC= output clock switching frequency.
The incremental current is added to (for VCCO >3.6V)
or subtracted from (for VCCO <3.6V) the DC Electrical
Characteristics table maximum supply current. The
internal output buffer capacitance is CINT = 6pF. The
worst-case pattern switching frequency of the data out-
puts is half the switching frequency of the output clock.
In the following example, the incremental supply current is
calculated for VCCO = 5.5V, fC= 34MHz, and CL= 8pF:
VI= 5.5V - 3.6V = 1.9V
CT= CINT + CL= 6pF + 8pF = 14pF
where:
II= CTVI 0.5FCx 21 (data outputs) + CTVIfCx 1 (clock
output).
II= (14pF x 1.9V x 0.5 x 34MHz x 21) + (14pF x 1.9V x
34MHz).
II= 9.5mA + 0.9mA = 10.4mA.
The maximum supply current in DC-balanced mode for
VCC = VCCO = 3.6V at fC= 34MHz is 106mA (from the
DC Electrical Characteristics table). Add 10.4mA to get
the total approximate maximum supply current at VCCO
= 5.5V and VCC = 3.6V.
If the output supply voltage is less than VCCO = 3.6V,
the reduced supply current can be calculated using the
same formula and method.
At high switching frequency, high supply voltage, and
high capacitive loading, power dissipation can exceed
the package power dissipation rating. Do not exceed
the maximum package power dissipation rating. See
the Absolute Maximum Ratings for maximum package
power dissipation capacity and temperature derating.
Rising- or Falling-Edge Output Strobe
The MAX9210/MAX9214 have a rising-edge output
strobe, which latches the parallel output data into the
next chip on the rising edge of RxCLK OUT. The
MAX9220/MAX9222 have a falling-edge output strobe,
which latches the parallel output data into the next chip
on the falling edge of RxCLK OUT. The deserializer out-
put strobe polarity does not need to match the serializ-
er input strobe polarity. A deserializer with rising or
falling edge output strobe can be driven by a serializer
with a rising edge input strobe.
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
______________________________________________________________________________________ 15
48
47
46
45
44
43
42
41
40
39
1
2
3
4
5
6
7
8
9
10
VCCO
RxOUT16
RxOUT15
RxOUT14RxOUT19
GND
RxOUT18
RxOUT17
TOP VIEW
MAX9210
MAX9214
MAX9220
MAX9222
GND
RxOUT13
VCC
RxOUT12RxIN0-
LVDS GND
DCB/NC
RxOUT20
RxOUT11
RxOUT10RxIN1-
RxIN0+
38
37
36
35
34
33
32
31
30
29
GND
RxOUT9
VCCO
RxOUT8
RxOUT7
RxOUT6
GND
RxOUT5
RxOUT4
RxOUT3
11
12
13
14
15
16
17
18
19
RxIN2-
LVDS GND
LVDS VCC
RxIN1+
LVDS GND
RxCLK IN+
RxCLK IN-
RxIN2+
PLL VCC
PLL GND
20
21
PWRDWN
PLL GND
22
28
27
VCCO
RxOUT2
TSSOP
23
RxOUT0
RxCLK OUT
24
26
25
RxOUT1
GND
Pin Configuration
Chip Information
MAX9210 TRANSISTOR COUNT: 10,248
MAX9214 TRANSISTOR COUNT: 10,248
MAX9220 TRANSISTOR COUNT: 10,248
MAX9222 TRANSISTOR COUNT: 10,248
PROCESS: CMOS
RxIN0+
LVDS DATA
RECEIVER 0
RxIN0- STROBE
DATA
CHANNEL 0
RxOUT0–6
SERIAL-TO-
PARALLEL
CONVERTER
RxIN1+
LVDS DATA
RECEIVER 1
RxIN1- STROBE
DATA
CHANNEL 1
RxOUT7–13
SERIAL-TO-
PARALLEL
CONVERTER
RxIN2+
LVDS DATA
RECEIVER 2
RxIN2- STROBE
DATA
CHANNEL 2
RxOUT14–20
SERIAL-TO-
PARALLEL
CONVERTER
RxCLK IN+
LVDS CLOCK
RECEIVER
RxCLK IN-
DCB/NC
7x/9x
PLL
RxCLK OUT
REFERENCE
CLOCK
GENERATOR
PWRDWN
Functional Diagram
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
16 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
48L TSSOP.EPS
NOTES:
1. DIMENSIONS D & E ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED 0.15MM ON D SIDE, AND 0.25MM ON E SIDE.
3. CONTROLLING DIMENSION: MILLIMETERS.
4. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION MO-153, VARIATIONS, ED (48L), EE (56L).
5. "N" REFERS TO NUMBER OF LEADS.
6. THE LEAD TIPS MUST LIE WITHIN A SPECIFIED ZONE. THIS TOLERANCE ZONE IS DEFINED BY TWO PARALLEL
PLANES. ONE PLANE IS THE SEATING PLANE, DATUM (-C-), THE OTHER PLANE IS AT THE SPECIFIED DISTANCE
FROM (-C-) IN THE DIRECTION INDICATED.
7. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
8. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
SECTION C-C
DETAIL A
N
SIDE VIEW
TOP VIEW
C
L
1
HE
e
D
b
A
A2 A1
BOTTOM VIEW
c
0.25
(
)b1
b
c1
BASE METAL
c
END VIEW
SEATING
PLANE
SEE DETAIL A
PARTING
LINE
WITH PLATING
L
PACKAGE OUTLINE,
21-0155 1
1
C
48 & 56L TSSOP, 6.1mm BODY
AAA
23
A
MARKING
MAX9210/MAX9214/MAX9220/MAX9222
Programmable DC-Balance
21-Bit Deserializers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER REVISION DATE REVISION DESCRIPTION PAGES CHANGED
0 — Initial release —
1—— —
2—— —
3—— —
4 3/05 Various changes —
5 11/07
Removed all references to MAX9212/MAX9216 and thin QFN-EP
package; various style edits; and updated package outline for
TSSOP.
All pages
