TPS61281AYFFR - Texas Instruments

1.5µF X5R 6.3V (0402)

C (x2)

10µF X5R 6.3V (0603)

VBAT’

0.47 Hμ

TPS61280A

VIN

VSEL

BYP

SCL

SDA

PGND

VOUT

GPIO

AGND

Battery

2.5V .. 4.35V

Enable

1.8V

Interrupt

Forced Bypass / Auto

Voltage Select

I C Bus

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

TPS6128xA Low-, Wide- Voltage Battery Front-End DC/DC Converter

Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications

1 Features

1• 95% Efficiency at 2.3MHz Operation

• 3µA Quiescent Current in Low IQPass-Through

Mode

• Wide VIN Range From 2.3V to 4.8V

• IOUT ≥4A (Peak) at VOUT = 3.35V, VIN ≥2.65V

• Integrated Pass-Through Mode (35mΩ)

• Programmable Valley Inductor Current Limit and

Output Voltage

• True Pass-Through Mode During Shutdown

•Best-in-Class Line and Load Transient

• Low-Ripple Light-Load PFM Mode

• In-Situ Customization with On-Chip E2PROM

(Write Protection)

• Two Interface Options:

– I2C Compatible I/F up to 3.4Mbps

(TPS61280A)

– Simple I/O Logic Control Interface

(TPS6128xA)

• Thermal Shutdown and Overload Protection

• Total Solution Size < 20mm2, Sub 1-mm Profile

2 Applications

• Single-Cell Ni-Rich, Si-Anode, Li-Ion, LiFePO4

Smart-Phones or Tablet PCs

• 2.5G/3G/4G Mini-Module Data Cards

• Current Limited Applications Featuring High Peak

Power Loads

3 Description

The TPS6128xA device provides a power supply

solution for products powered by either by a Li-Ion,

Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery.

The voltage range is optimized for single-cell portable

applications like in smart-phones or tablet PCs.

Used as a high-power pre-regulator, the TPS6128xA

extends the battery run-time and overcomes input

current- and voltage limitations of the powered

system.

While in shutdown, the TPS6128xA operates in a true

pass-through mode with only 3µA quiescent

consumption for longest battery shelf life.

During operation, when the battery is at a good state-

of-charge, a low-ohmic, high-efficient integrated pass-

through path connects the battery to the powered

system.

If the battery gets to a lower state of charge and its

voltage becomes lower than the desired minimum

system voltage, the device seamlessly transits into

boost mode to uses the full battery capacity.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

TPS61280A DSBGA (16) 1.66 mm x 1.66 mmTPS61281A

TPS61282A

(1) For all available packages, see the orderable addendum at

the end of the datasheet.

4 Simplified Schematic

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS61280A TPS61281A TPS61282A

Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Simplified Schematic............................................. 1

5 Revision History..................................................... 2

6 Device Comparison Table..................................... 3

7 Description (continued)......................................... 3

8 Pin Configurations and Functions....................... 4

9 Specifications......................................................... 6

9.1 Absolute Maximum Ratings ..................................... 6

9.2 ESD Ratings.............................................................. 6

9.3 Recommended Operating Conditions....................... 6

9.4 Thermal Information.................................................. 7

9.5 Electrical Characteristics........................................... 7

9.6 I2C Interface Timing Characteristics ........................ 9

9.7 I2C Timing Diagrams............................................... 11

9.8 Typical Characteristics............................................ 12

10 Detailed Description ........................................... 14

10.1 Overview ............................................................... 14

10.2 Functional Block Diagram..................................... 15

10.3 Feature Description............................................... 16

10.4 Device Functional Modes...................................... 17

10.5 Programming......................................................... 22

10.6 Register Maps....................................................... 25

11 Application and Implementation........................ 33

11.1 Application Information.......................................... 33

11.2 Typical Application................................................ 34

12 Power Supply Recommendations ..................... 46

13 Layout................................................................... 46

13.1 Layout Guidelines ................................................. 46

13.2 Layout Example .................................................... 46

13.3 Thermal Information.............................................. 47

14 Device and Documentation Support................. 48

14.1 Device Support...................................................... 48

14.2 Related Links ........................................................ 48

14.3 Receiving Notification of Documentation Updates 48

14.4 Community Resources.......................................... 48

14.5 Trademarks........................................................... 48

14.6 Electrostatic Discharge Caution............................ 48

14.7 Glossary................................................................ 48

15 Mechanical, Packaging, and Orderable

Information........................................................... 49

15.1 Package Summary................................................ 49

15.2 Chip Scale Package Dimensions.......................... 49

5 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision A (September 2014) to Revision B Page

• Moved Storage temperature spec, Tstg from Handling Ratings table to Abs Max Ratings table; and, re-named

Handling ratings to ESD Ratings ........................................................................................................................................... 6

• Changed the device number in Figure 11 From TPS61281 and TPS61282 To: TPS61281A and TPS61282A................. 12

• Changed the device number in Figure 24 through Figure 26 From TPS6128x To: TPS6128xA......................................... 24

• Added legal Note at Application and Implementation section.............................................................................................. 33

• Added cross reference to the Third-Party Products Disclaimer. ......................................................................................... 37

• Corrected legend for Figure 30, Gray is VIN = 3.0 V, Red is VIN = 2.5 V. ............................................................................ 38

• Added cross reference to Third-Party Products Disclaimer ................................................................................................. 42

• Changed the markings on Figure 67 ................................................................................................................................... 49

Changes from Original (May 2014) to Revision A Page

• Changed the Device Information table Package From: DGBA To: DSBGA ......................................................................... 1

• Deleted the Package Marking Chip Code column from the Device Comparison Table. The information is found in

the POA at the end of the datasheet...................................................................................................................................... 3

TPS61280A

TPS61281A

TPS61282A

www.ti.com

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

Product Folder Links: TPS61280A TPS61281A TPS61282A

(1) The 'A’ version has lower ripple and overshoot, supports Forced PWM at startup but with a 0.4 μA higher IQ.

6 Device Comparison Table

PART NUMBER(1) DEVICE

SPECIFIC FEATURES

TPS61280A I2C Control Interface

User Prog. E2PROM Settings

DC/DC boost / bypass threshold = 3.15V (Vsel = L)

DC/DC boost / bypass threshold = 3.35V (Vsel = H)

Valley inductor current limit = 3A

TPS61281A Simple Logic Control Interface DC/DC boost / bypass threshold = 3.15V (Vsel = L)

DC/DC boost / bypass threshold = 3.35V (Vsel = H)

Valley inductor current limit = 3A

TPS61282A Simple Logic Control Interface DC/DC boost / bypass threshold = 3.3V (Vsel = L)

DC/DC boost / bypass threshold = 3.5V (Vsel = H)

Valley inductor current limit = 4A

7 Description (continued)

TPS6128xA device supports more than 4A pulsed load current even from a deeply discharged battery. In this

mode of operation, the TPS6128xA enables the utilization of the full battery capacity: A high battery-cut-off

voltage originated by powered components with a high minimum input voltage is overcome; new battery

chemistries can be fully discharged; high current pulses forcing the system into shutdown are buffered by the

device seamlessly transitioning between boost and by-pass mode back and forth.

This has significant impact on the battery on-time and translates into either a longer use-time and better user-

experience at an equal battery capacity or into reduced battery costs at similar use-times.

The TPS6128xA offers a small solution size (< 20mm2) due to minimum amount of external components,

enabling the use of small inductors and input capacitors, available as a 16-pin chip-scale package (CSP).

The TPS6128xA operates in synchronous, 2.3MHz boost mode and enters power-save mode operation (PFM) at

light load currents to maintain high efficiency over the entire load current range.

PGND

SDA

PGND

nBYP

AGND PGND

TOP VIEW

D4 D3 D2 D1

PGND

C3 C2 C1

nBYP

PGND

SW SDA

AGND

BOTTOM VIEW

VSEL SCL VOUT VOUT VOUT

VOUT VSELSCL

EN GPIO VIN VIN VIN

VIN ENGPIO

PGND

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS61280A TPS61281A TPS61282A

8 Pin Configurations and Functions

TPS61280A

16-Bump DSBGA

YFF Package

Pin Functions - TPS61280A

PIN I/O DESCRIPTION

NAME NO.

VIN A3, A4 I Power supply input.

VOUT B3, B4 O Boost converter output.

EN A1 I

This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default

values. This input must not be left floating and must be terminated.

EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the

logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be

regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current

consumption is reduced to a few µA. For more details, refer to Table 2.

EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For

more details, refer to Table 2.

GPIO A2 I/O

This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT )

pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be

terminated.

Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a

falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output

followed by a start-up phase.

Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output

voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edge-

triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.

Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at

high-load currents and in pulse frequency modulation mode (PFM) at light load currents.

Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.

VSEL B1 I VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left

floating and must be terminated.

nBYP C1 I A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to . This pin must

not be left floating and must be terminated.

SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.

SDA C2 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.

SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.

PGND D2, D3, D4 Power ground pin.

AGND D1 Analog ground pin. This is the signal ground reference for the IC.

PGND

AGND

PGND

nBYP

AGND PGND

TOP VIEW

D4 D3 D2 D1

PGND

C3 C2 C1

nBYP

PGND

SW AGND

AGND

BOTTOM VIEW

VSEL MODE VOUT VOUT VOUT

VOUT VSEL

MODE

EN PG VIN VIN VIN

VIN ENPG

PGND

TPS61280A

TPS61281A

TPS61282A

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SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

Product Folder Links: TPS61280A TPS61281A TPS61282A

(TPS6128xA)

16-Bump DSBGA

YFF Package

Pin Functions - TPS6128xA

PIN I/O DESCRIPTION

NAME NO.

VIN A3, A4 I Power supply input.

VOUT B3, B4 O Boost converter output.

EN A1 I

This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default

values. This input must not be left floating and must be terminated.

EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the

converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit

the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For

more details, refer to Table 2.

EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For

more details, refer to Table 2.

PG A2 O

Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output

voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage

out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes

proper operation.

VSEL B1 I VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left

floating and must be terminated.

nBYP C1 I A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to Table 2. This

pin must not be left floating and must be terminated.

MODE B2 I

This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be

connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates

that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by

applying a high level on this pin.

MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load

currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during

device start-up.

MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.

SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.

PGND D2, D3, D4 Power ground pin.

AGND C2, D1 Analog ground pin. This is the signal ground reference for the IC.

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

www.ti.com

Product Folder Links: TPS61280A TPS61281A TPS61282A

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.

(2) All voltages are with respect to network ground terminal.

(3) Limit the junction temperature to 105°C for continuous operation at maximum output power.

(4) Limit the junction temperature to 105°C for 15% duty cycle operation.

(5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may

have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the

maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package

in the application (θJA), as given by the following equation: TA(max) = TJ(max) – (θJA X PD(max)). To achieve optimum performance, it is

recommended to operate the device with a maximum junction temperature of 105°C.

9 Specifications

9.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Input voltage

Voltage at VOUT(2) DC –0.3 4.7 V

Voltage at VIN(2), EN(2), VSEL(2), BYP(2), PG(2),

GPIO(2) DC –0.3 5.2 V

Voltage at SCL(2), SDA(2)MODE(2) DC –0.3 3.6 V

Voltage at SW(2) DC –0.3 4.7 V

Transient: 2 ns, 2.3

MHz –0.3 5.5 V

Differential voltage between VIN and VOUT DC –0.3 4 V

Input current Continuous average current into SW (3) 1.8 A

Peak current into SW (4) 5.5 A

Power dissipation Internally limited

Temperature range Operating temperature range, TA(5) –40 85 °C

Operating virtual junction, TJ–40 150 °C

Tstg Storage temperature range –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

9.2 ESD Ratings VALUE UNIT

VESD Electrostatic discharge

Human body model (HBM), per

ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V

Charged device model (CDM), per JEDEC

specification JESD22-C101, all pins(2) ±1000 V

Machine Model - (MM) ±200 V

9.3 Recommended Operating Conditions MIN NOM MAX UNIT

VIInput voltage range 2.30 4.85 V

Input voltage range for in-situ customization by E2PROM write operation 3.4 3.5 3.6 V

L Inductance 200 470 800 nH

COOutput capacitance 9 13 100 µF

ILMaximum load current during start-up 250 mA

TAAmbient temperature –40 85 °C

TJOperating junction temperature –40 125 °C

TPS61280A

TPS61281A

TPS61282A

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SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

Product Folder Links: TPS61280A TPS61281A TPS61282A

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report (SPRA953).

9.4 Thermal Information

THERMAL METRIC(1)

TPS6128xA

UNIT

YFF PACKAGE

(DSBGA)

16 PINS

RθJA Junction-to-ambient thermal resistance 78 °C/W

RθJCtop Junction-to-case (top) thermal resistance 0.6 °C/W

RθJB Junction-to-board thermal resistance 13 °C/W

ψJT Junction-to-top characterization parameter 2.4 °C/W

ψJB Junction-to-board characterization parameter 13 °C/W

RθJCbot Junction-to-case (bottom) thermal resistance n/a °C/W

9.5 Electrical Characteristics

Minimum and maximum values are at VIN = 2.3V to 4.85V, VOUT = 3.4V (or VIN, whichever is higher), EN = 1.8V, VSEL =

1.8V, nBYP = 1.8V, –40°C ≤TJ≤125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).

Typical values are at VIN = 3.2V, VOUT = 3.4V, EN = 1.8V, TJ= 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY CURRENT

Operating quiescent current

into VIN TPS6128xA

DC/DC boost mode. Device not

switching

IOUT = 0mA, VIN = 3.2V, VOUT = 3.4V

–40°C ≤TJ≤

85°C

47.4 65.6 µA

Pass-through mode (auto)

EN = 1.8V, BYP = 1.8V, VIN = 3.6V 27.4 42.6 µA

Pass-through mode (forced)

EN = 1.8V, BYP = AGND, VOUT = 3.6V 15.4 25.6 µA

Operating quiescent current

into VOUT

DC/DC boost mode. Device not

switching

IOUT = 0mA, VIN = 3.2V, VOUT = 3.4V 8.9 19.6 µA

ISD Shutdown current TPS6128xA EN = 0V, BYP = 0V, VIN = 3.6V 3.0 6.6 μA

EN = 0V, BYP = 1.8V, VIN = 3.6V 8.9 20.6 μA

VUVLO Under-voltage lockout threshold TPS6128xA Falling 2.0 2.1 V

Hysteresis 0.1 V

EN, VSEL, nBYP, MODE, SDA, SCL, GPIO, PG

VIL Low-level input voltage TPS6128xA 0.4 V

VIH High-level input voltage 1.2 V

VOL

Low-level output voltage (SDA) TPS61280A IOL = 8mA 0.3 V

Low-level output voltage (GPIO) IOL = 8mA, GPIOCFG = 0 0.3 V

Low-level output voltage (PG) TPS6128xA IOL = 8mA 0.3 V

RPD EN, VSEL, BYP,

pull-down resistance TPS6128xA Input ≤0.4 V 300 kΩ

CIN

EN, VSEL, BYP, MODE, PG

input capacitance TPS6128xA Input connected to AGND or VIN

9 pF

SDA, SCL, GPIO input

capacitance TPS61280A 9 pF

VTHPG Power good threshold TPS6128xA Rising VOUT 0.95 x

VOUT

Falling VOUT 0.9 x

VOUT

Ilkg Input leakage current TPS6128xA Input connected to AGND –40°C ≤TJ≤

85°C 0 µA

Input connected VIN 0.5 µA

OUTPUT

VOUT(TH) Threshold DC voltage accuracy TPS6128xA No load. Open loop -1.5 +1.5 %

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

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Product Folder Links: TPS61280A TPS61281A TPS61282A

Electrical Characteristics (continued)

Minimum and maximum values are at VIN = 2.3V to 4.85V, VOUT = 3.4V (or VIN, whichever is higher), EN = 1.8V, VSEL =

1.8V, nBYP = 1.8V, –40°C ≤TJ≤125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).

Typical values are at VIN = 3.2V, VOUT = 3.4V, EN = 1.8V, TJ= 25°C (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(1) Specified by characterization. Not tested in production.

VOUT Regulated DC voltage accuracy TPS6128xA

2.65V ≤VIN ≤VOUT_TH - 150mV

IOUT = 0mA

PWM operation. -2.0 +2.0 %

2.65V ≤VIN ≤VOUT_TH - 150mV

IOUT = 0mA

PFM/PWM operation -2.0 +4.0 %

ΔVOUT

Power-save mode

output ripple voltage TPS6128xA PFM operation, IOUT = 1mA 30 mVpk

PWM mode output ripple voltage PWM operation, IOUT = 500mA 15 mVpk

POWER SWITCH

rDS(on)

Low-side switch MOSFET

on resistance

TPS6128xA

VIN = 3.2, VOUT = 3.5V 45 80 mΩ

High-side rectifier MOSFET

on resistance VIN = 3.2V, VOUT = 3.5V 40 70 mΩ

High-side pass-through MOSFET

on resistance VIN = 3.2V 35 60 mΩ

Ilkg

Reverse leakage current into SW

TPS6128xA

EN = AGND, VIN = VOUT = SW = 3.5V

–40°C ≤TJ≤85°C 0.1 2 µA

Reverse leakage current into

VOUT

EN = BYP = VIN, VIN = 2.9V, VOUT = 4.4V, VSW = 0V

device not switching

–40°C ≤TJ≤85°C 0.11 2 µA

ISINK VOUT sink capability TPS6128xA EN = AGND, VOUT ≤3.6V,IOUT = -10mA 0.3 V

Valley inductor current limit TPS61280A

TPS61281A VIN = 2.9V, VOUT = 3.5V, –40°C ≤TJ≤125°C, auto

PFM/PWM 2475 3000 3525 mA

Valley inductor current limit TPS61282A VIN = 2.9V, VOUT = 3.5V, –40°C ≤TJ≤125°C, auto

PFM/PWM 3300 4000 4700 mA

Pass through mode current limit TPS6128xA EN = BYP = GND, VIN = 3.2V 5000 mA

EN = VIN, BYP = don't care , VIN = 3.2V 5600 7400 9100 mA

Pre-charge mode current limit

(linear mode, phase 1) TPS6128xA VIN - VOUT >= 300mV 500 650 mA

Pre-charge mode current limit

(linear mode, phase 2) 2000 mA

OSCILLATOR

fOSC Oscillator frequency TPS6128xA VIN = 2.7V, VOUT = 3.5 2.3 MHz

THERMAL SHUTDOWN, HOT DIE DETECTOR

Thermal shutdown(1) TPS6128xA 140 160 °C

Hot die detector accuracy(1) TPS61280A -10 105 +10 °C

TIMING

Start-up time TPS6128xA VIN = 3.2V, VOUT_TH = 01011 (3.4V), RLOAD = 50Ω

Time from active VIN to VOUT settled 500 µs

GPIO rise time(1) TPS61280A 200 ns

TPS61280A

TPS61281A

TPS61282A

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Product Folder Links: TPS61280A TPS61281A TPS61282A

(1) Specified by design. Not tested in production.

9.6 I2C Interface Timing Characteristics(1)

PARAMETER TEST CONDITIONS MIN MAX UNIT

f(SCL) SCL Clock Frequency

Standard mode 100 kHz

Fast mode 400 kHz

Fast mode plus 1 MHz

High-speed mode (write operation), CB– 100 pF max 3.4 MHz

High-speed mode (read operation), CB– 100 pF max 3.4 MHz

High-speed mode (write operation), CB– 400 pF max 1.7 MHz

High-speed mode (read operation), CB– 400 pF max 1.7 MHz

tBUF Bus Free Time Between a STOP and

START Condition

Standard mode 4.7 μs

Fast mode 1.3 μs

Fast mode plus 0.5 μs

tHD, tSTA Hold Time (Repeated) START

Condition

Standard mode 4 μs

Fast mode 600 ns

Fast mode plus 260 ns

High-speed mode 160 ns

tLOW LOW Period of the SCL Clock

Standard mode 4.7 μs

Fast mode 1.3 μs

Fast mode plus 0.5 μs

High-speed mode, CB– 100 pF max 160 ns

High-speed mode, CB– 400 pF max 320 ns

tHIGH HIGH Period of the SCL Clock

Standard mode 4 μs

Fast mode 600 ns

Fast mode plus 260 ns

High-speed mode, CB– 100 pF max 60 ns

High-speed mode, CB– 400 pF max 120 ns

tSU, tSTA Setup Time for a Repeated START

Condition

Standard mode 4.7 μs

Fast mode 600 ns

Fast mode plus 260 ns

High-speed mode 160 ns

tSU, tDAT Data Setup Time

Standard mode 250 ns

Fast mode 100 ns

Fast mode plus 50 ns

High-speed mode 10 ns

tHD, tDAT Data Hold Time

Standard mode 0 3.45 μs

Fast mode 0 0.9 μs

Fast mode plus 0 μs

High-speed mode, CB– 100 pF max 0 70 ns

High-speed mode, CB– 400 pF max 0 150 ns

tRCL Rise Time of SCL Signal

Standard mode 1000 ns

Fast mode 20 + 0.1 CB300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 40 ns

High-speed mode, CB– 400 pF max 20 80 ns

tRCL1 Rise Time of SCL Signal After a Repeated

START Condition and After an

Acknowledge BIT

Standard mode 20 + 0.1 CB1000 ns

Fast mode 20 + 0.1 CB300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 80 ns

High-speed mode, CB– 400 pF max 20 160 ns

TPS61280A

TPS61281A

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I2C Interface Timing Characteristics(1) (continued)

PARAMETER TEST CONDITIONS MIN MAX UNIT

tFCL Fall Time of SCL Signal

Standard mode 20 + 0.1 CB300 ns

Fast mode 300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 40 ns

High-speed mode, CB– 400 pF max 20 80 ns

tRDA Rise Time of SDA Signal

Standard mode 1000 ns

Fast mode 20 + 0.1 CB300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 80 ns

High-speed mode, CB– 400 pF max 20 160 ns

tFDA Fall Time of SDA Signal

Standard mode 300 ns

Fast mode 20 + 0.1 CB300 ns

Fast mode plus 120 ns

High-speed mode, CB– 100 pF max 10 80 ns

High-speed mode, CB– 400 pF max 20 160 ns

tSU, tSTO Setup Time of STOP Condition

Standard mode 4 μs

Fast mode 600 ns

Fast mode plus 260 ns

High-Speed mode 160 ns

CBCapacitive Load for SDA and SCL

Standard mode 400 pF

Fast mode 400 pF

Fast mode plus 550 pF

High-Speed mode 400 pF

Sr PSr

tfDA trDA

thd;DAT

tsu;STA thd;STA tsu;DAT tsu;STO

trCL1 tfCL

tHIGH tLOW tLOW tHIGH

trCL trCL1

= MCS Current Source Pull-Up

= R(P) Resistor Pull-Up

SDAH

SCLH

Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.

See Note ASee Note A

tftLOW tr

thd;STA

thd;DAT

tsu;DAT tf

HIGH

tsu;STA

S Sr P S

thd;STA tr

tBUF

tsu;STO

SDA

SCL

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9.7 I2C Timing Diagrams

Figure 1. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus

Figure 2. Serial Interface Timing Diagram for H/S-Mode

3.5 4.5

Quiescent Current_Force Bypass (µA)

Input Voltage (V)

Tj=25C

Tj=-40

Tj = 85 C

C005

TJ = 30°C

TJ = -40°C

TJ = 85°C

3.5 4.5

Quiescent Current_Auto Bypass (µA)

Input Voltage (V)

Tj=25C

Tj=-40

Tj = 85 C

C006

TJ = 30°C

TJ = -40°C

TJ = 85°C

-40 -20 0 20 40 60 80 100 120

LS FET On Resistance (m

Junction Temperature (ƒC)

C003

2.3 2.5 2.7 2.9 3.1

Quiescent Current_Boost (µA)

Input Voltage (V)

Tj=25C

Tj=-40

Tj = 85 C

C004

TJ = 30°C

TJ = -40°C

TJ = 85°C

-40 -20 0 20 40 60 80 100 120

HS FET On Resistance (m

Junction Temperature (ƒC)

C001

-40 -20 0 20 40 60 80 100 120

LS FET On Resistance (m

Junction Temperature (ƒC)

C002

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9.8 Typical Characteristics

VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C

Figure 3. High side Rds(on) vs Junction Temperature

VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C

Figure 4. Low side Rds(on) vs Junction Temperature

VIN = 3.2 V Bypass TJ= –40 to 125°C

Figure 5. Bypass FET Rds(on) vs Junction Temperature

VIN = 2.3 - 3.4 V VOUT = 3.4 V IOUT = 0 mA

EN = High Bypass = High

Figure 6. Quiescent Current at Boost Mode vs Input Voltage

VIN = 3.5 - 4.4 V VOUT = 3.4 V IOUT = 0 mA

EN = High Bypass = Low

Figure 7. Quiescent Current at Forced Bypass Mode vs

Input Voltage

VIN = 3.6 - 4.4 V VOUT = 3.4 V IOUT = 0 mA

EN = High Bypass = High

Figure 8. Quiescent Current at Auto Bypass Mode vs Input

Voltage

0.50

0.60

0.70

0.80

0.90

1.00

1.10

-40 -20 0 20 40 60 80 100 120

EN Logic Threshold (V)

Junction Temperature (ƒC)

EN Rising

EN Falling

C011

0.50

0.60

0.70

0.80

0.90

1.00

1.10

-40 -20 0 20 40 60 80 100 120

EN Logic Threshold (V)

Junction Temperature (ƒC)

nBYP Rising

nBYP Falling

C012

2.0

2.5

3.0

3.5

4.0

4.5

-40 10 60 110

Switch Valley Current Limit (A)

Temperature (ƒC)

TPS61281A

TPS61282A

C009

1.80

2.00

2.20

-40 -20 0 20 40 60 80 100 120

Vin UVLO Threshold (V)

Junction Temperature (ƒC)

Vin Rising

Vin Falling

C010

VIN Rising

VIN Falling

2.3 3.3 4.3

Leakage Current_Low Iq (µA)

Input Voltage (V)

Tj=25C

Tj=-40

Tj = 85 C

C007

TJ = 30°C

TJ = -40°C

TJ = 85°C

2.3 3.3 4.3

Leakage Current_Low Iq (µA)

Input Voltage (V)

Tj = 25C

Tj = -40

Tj = 85 C

C008

TJ = 30°C

TJ = -40°C

TJ = 85°C

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Typical Characteristics (continued)

VIN = 2.3 - 4.4 V VOUT = 4.4 V VSW = 0 V

EN = Low Bypass = Low

Figure 9. Shutdown Current at Low IQmode vs Input

Voltage

VIN = 2.3 - 4.4 V VOUT = 4.4 V VSW = 0 V

EN = Low Bypass = High

Figure 10. Shutdown Current vs Input Voltage

VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C

EN = High Bypass = High

Figure 11. Switch Valley Current Limit: TPS61281A,

TPS61282A vs Input Voltage

VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C

Figure 12. VIN UVLO Threshold Rising/Falling vs Junction

Temperature

VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C

Figure 13. EN Logic High Threshold Rising/Falling vs

Junction Temperature

VIN = 3.2 V TJ= –40 to 125°C

Figure 14. BYP Logic High Threshold Rising/Falling vs

Junction Temperature

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10 Detailed Description

10.1 Overview

The TPS6128xA is a high-efficiency step-up converter featuring pass-through mode optimized to provide low-

noise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for

supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC and so on.

It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption levels

from a low-, wide- voltage battery cell.

The capability of the TPS6128xA to step-up the voltage as well as to pass-through the input battery voltage when

its level is high enough allow systems to operate at maximum performance over a wide range of battery voltages,

thereby extending the battery life between charging. The device also addresses brownouts caused by the peak

currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the

TPS6128xA device as a pre-regulator eliminates system brownout condition while maintaining a stable supply rail

for critical sub-system to function properly.

The TPS6128xA synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency pulse

width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128xA converter

operates in power-save mode with pulse frequency modulation (PFM).

In general, a dc/dc step-up converter can only operate in "true" boost mode, that is the output “boosted” by a

certain amount above the input voltage. The TPS6128xA device operates differently as it can smoothly transition

in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold and load

current, the integrated bypass switch automatically transitions the converter into pass-through mode to maintain

low-dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the total

dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer to the

typical characteristics section (DC Output Voltage vs. Input Voltage) for further details.

During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to

achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on

the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-

side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-

time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the

inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on

timer again and activating the low-side N-MOS switch.

The current mode architecture provides excellent transient load response, requiring minimal output filtering.

Internal soft-start and loop compensation simplifies the design process while minimizing the number of external

components.

The TPS6128xA directly and accurately controls the average input current through intelligent adjustment of the

valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6128xA

allows an application to be interfaced directly to its load, without overloading the input source due to appropriate

set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an

interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits, and

so on).

The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic

control input (VSEL) without the need for external feedback resistors. This features can either be used to raise

the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage

depending on its mode of operation and/or transmitting power.

The TPS61280A integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication

interface can be used to set the output voltage threshold at which the converter transitions between boost and

pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the

average input current limit or resetting the output voltage for instance.

Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The

I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the

E2PROMCTRL Register, it is possible to store the active configuration in non-volatile E2PROM; during power-up,

the contents of the E2PROM are copied into the I2C registers and used to configure the device.

Undervoltage

Lockout

Thermal

Shutdown

Control

Logic

Gate

Driver

PMOS

VREF

NMOS

Pulse Width

Modulator

Control Logic

Valley

Current

Sense

VMAX

Control

Averaging

VIN VOUT

Start-Up

Control

NMOS

VMAX

Control

Gate

Driver

Error

Amplifier

Band-gap

Bias Supply

VIN

SDA

VIN

VOUT

GPIO: RESET (I) / FAULT (O)

SW VIN

VOUT

Control I/F

SCL

MODE

nBYP

VSEL

PGND PGND PGND AGND

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10.2 Functional Block Diagram

( )

hmfB

ffmfB

fmh

mcfm

×+××=

+D×=+××=

)(212

( ) )(212 mcfm ffmfB +D×=+××=

0dBV

0dBVref

FENV,PEAK Dfc Dfc Non-modulatedharmonic

Side-bandharmonics

windowaftermodulation

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10.3 Feature Description

10.3.1 Voltage Scaling Management (VSEL)

In order to maintain a certain minimum output voltage under heavy load transients, the output voltage set point

can be dynamically increased by asserting the VSEL input. The functionality also helps to mitigate undershoot

during severe line transients, while minimizing the output voltage during more benign operating conditions to

save power.

The output voltage ramps up (floor to roof transition) at pre-defined rate defined by the average input current limit

setting. The required time to ramp down the voltage (roof to floor transition) largely depends on the amount of

capacitance present at the converter's output as well as on the load current. Table 1 shows the ramp rate control

when transitioning to a lower voltage.

Table 1. Ramp Down Rate vs. Target Mode

Mode Associated with Floor Voltage Output Voltage Ramp Rate

Forced PWM Output capacitance is being discharged at a rate of approx. 50mA (or higher) constant current

in addition to the load current drawn

PFM Output capacitance is being discharged (solely) by the load current drawn

(1) Spectrum illustrations and formulae (Figure 15 and Figure 16) copyright IEEE TRANSACTIONS ON ELECTROMAGNETIC

COMPATIBILITY, VOL. 47, NO.3, AUGUST 2005.

10.3.2 Spread Spectrum, PWM Frequency Dithering

The goal is to spread out the emitted RF energy over a larger frequency range so that the resulting EMI is similar

to white noise. The end result is a spectrum that is continuous and lower in peak amplitude, making it easier to

comply with electromagnetic interference (EMI) standards and with the power supply ripple requirements in

cellular and non-cellular wireless applications. Radio receivers are typically susceptible to narrowband noise that

is focused on specific frequencies.

Switching regulators can be particularly troublesome in applications where electromagnetic interference (EMI) is

a concern. Switching regulators operate on a cycle-by-cycle basis to transfer power to an output. In most cases,

the frequency of operation is either fixed or regulated, based on the output load. This method of conversion

creates large components of noise at the frequency of operation (fundamental) and multiples of the operating

frequency (harmonics).

The spread spectrum architecture varies the switching frequency by ca. ±15% of the nominal switching frequency

thereby significantly reducing the peak radiated and conducting noise on both the input and output supplies. The

frequency dithering scheme is modulated with a triangle profile and a modulation frequency fm.

Figure 15. Spectrum of a Frequency Modulated

Sin. Wave with Sinusoidal Variation in Time Figure 16. Spread Bands of Harmonics in

Modulated Square Signals (1)

The above figures show that after modulation the sideband harmonic is attenuated compared to the non-

modulated harmonic, and the harmonic energy is spread into a certain frequency band. The higher the

modulation index (mf) the larger the attenuation.

( ) ( )

m c m

B = 2 1 + m = 2 +

´ ¦ ´ ´ D¦ ¦

=ƒ

δ ƒ

m = ƒ

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where

•fcis the carrier frequency (approx. 2.3MHz)

•fmis the modulating frequency (approx. 40kHz)

•δis the modulation ratio (approx 0.15) (1)

(2)

The maximum switching frequency fcis limited by the process and finally the parameter modulation ratio (δ),

together with fm, which is the side-band harmonics bandwidth around the carrier frequency fc. The bandwidth of

a frequency modulated waveform is approximately given by the Carson’s rule and can be summarized as:

(3)

fm< RBW: The receiver is not able to distinguish individual side-band harmonics, so, several harmonics are

added in the input filter and the measured value is higher than expected in theoretical calculations.

fm> RBW: The receiver is able to properly measure each individual side-band harmonic separately, so the

measurements match with the theoretical calculations.

10.4 Device Functional Modes

10.4.1 Power-Save Mode

The TPS6128xA integrates a power-save mode to improve efficiency at light load. In power save mode the

converter only operates when the output voltage trips below a set threshold voltage. It ramps up the output

voltage with several pulses and goes into power save mode once the output voltage exceeds the set threshold

voltage. The PFM mode is left and PWM mode entered in case the output current can not longer be supported in

PFM mode.

Figure 17. Power-Save Mode Ripple

10.4.2 Pass-Through Mode

The TPS6128xA contains an internal switch for bypassing the dc/dc boost converter during pass-through mode.

When the input voltage is larger than the preset output voltage, the converter seamlessly transitions into 0% duty

cycle operation and the bypass FET is fully enhanced. Entry in pass-through mode is triggered by condition

where VOUT >(1+2%)* VOUT_NORM and no switching has occurred during past 8µs.

In this mode of operation, the load (2G RF PA for instance) is directly supplied from the battery for maximum RF

output power, highest efficiency and lowest possible input-to-output voltage difference. The device consumes

only a standby current of 15µA (typ). In pass-through mode, the device is short-circuit protected by a very fast

current limit detection scheme.

During this operation, the output voltage follows the input voltage and will not fall below the programmed output

voltage threshold as the input voltage decreases. The output voltage drop during pass-through mode depends on

the load current and input voltage, the resulting output voltage is calculated as:

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

Input Voltage (V)

Output Voltage (V)

Vout_nom = 3.15V

Vout_nom = 3.35V

Vout_nom = 3.3V

Vout_nom = 3.5V

G000

OUT

DSON(BP)

η = 1 - R V

OUT IN DSON(BP) OUT

V = V - (R x I )

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Device Functional Modes (continued)

(4)

Conversely, the efficiency in pass-through mode is defined as:

• in which RDSON(BP) is the typical on-resistance of the bypass FET (5)

Figure 18. DC Output Voltage vs. Input Voltage

Pass-through mode exit is triggered when the output voltage reaches the pre-defined threshold (that is, 3.4V).

During pass-through mode, the TPS6128xA device is short-circuit protected by a fast current limit detection

scheme. If the current in the pass-through FET exceeds approximately 7.3 Amps a fault is declared and the

device cycles through a start-up procedure.

10.4.3 Mode Selection

Depending on the settings of CONFIG Register the device can be operated at a quasi-constant 2.3-MHz

frequency PWM mode or in automatic PFM/PWM mode. In this mode, the converter operates in pseudo-fixed

frequency PWM mode at moderate to heavy loads and in the PFM mode during light loads, which maintains high

efficiency over a wide load current range. For more details, see the CONFIG Register description.

The quasi-constant frequency PWM mode has the tightest regulation and the best line/load transient

performance. In forced PWM mode, the device features a unique RDS(ON) management function to maintain high

broadband efficiency as well as low resistance in pass-through mode.

In the TPS61280A device, the GPIO pin can be configured (via the CONFIG Register) to select the operating

mode of the device. In the other TPS6128xA devices, the MODE pin is used to select the operating mode.

Pulling this pin high forces the converter to operate in the PWM mode even at light load currents. The advantage

is that the converter modulates its switching frequency according to a spread spectrum PWM modulation

technique allowing simple filtering of the switching harmonics in noise-sensitive applications.

For additional flexibility, it is possible to switch from power-save mode (GPIO or MODE input = L) to PWM mode

(GPIO or MODE input = H) during operation. This allows efficient power management by adjusting the operation

of the converter to the specific system requirements (that is, 2G RF PA Rx/Tx operation).

Entry to forced pass-through mode (nBYP = L) initiates with a current limited transition followed by a true bypass

state. To prevent reverse current to the battery, the devices waits until the output discharges below the input

voltage level before entering forced pass-through mode. Care should be taken to prohibit the output voltage from

collapsing whilst transitioning into forced pass-through mode under heavy load conditions and/or limited output

capacitance. This can be easily done by adding capacitance to the output of the converter. In forced pass-

through mode, the output follows the input below the preset output threshold voltage (VOUT_TH).

ΔI IN

L×=

IVALLEY

IPEAK

Rectifier

Current

IOUT(DC)

Inductor

Current

Increased

Load Current

IIN(DC)

Current Limit

Threshold

IOUT

DIL

´=D

IIN

h´´=

OUT

I N

)O U T ( M A X _ D C V

IL I M I T

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Device Functional Modes (continued)

10.4.4 Current Limit Operation

The TPS6128xA device features a valley inductor current limit scheme.

In dc/dc boost mode, the TPS6128xA device employs a current limit detection scheme in which the voltage drop

across the synchronous rectifier is sensed during the off-time. In the TPS61280A the current limit threshold can

be set via an I2C register. TPS6128xA devices have a fixed current limit threshold. See device ordering table for

detailed information.

The output voltage is reduced as the power stage of the device operates in a constant current mode. The

maximum continuous output current (IOUT(MAX)), before entering current limit (CL) operation, can be defined by

Equation 6.

where

•ηis the efficiency

• The inductor peak-to-peak current ripple (ΔIL) is calculated by Equation 7 (6)

(7)

The output current, IOUT(DC), is the average of the rectifier ripple current waveform. When the load current is

increased such that the trough is above the current limit threshold, the off-time is increased to allow the current to

decrease to this threshold before the next on-time begins (so called frequency fold-back mechanism). When the

current limit is reached the output voltage decreases during further load increase.

Figure 19 illustrates the inductor and rectifier current waveforms during current limit operation.

Figure 19. Inductor/Rectifier Currents in Current Limit Operation (DC/DC Boost Mode)

During pass-through mode, the TPS6128xA device is short-circuit protected by a very fast current limit detection

scheme. If the current in the bypass FET exceeds approximately 7.5Amps a fault is declared and the device

cycles through a start-up procedure.

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Device Functional Modes (continued)

10.4.5 Start-Up and Shutdown Mode

The TPS6128xA automatically powers-up as soon as the input voltage is applied. The device has an internal

soft-start circuit that limits the inrush current during start-up. The first phase in the start-up procedure is to bias

the output node close to the input level (so called pre-charge phase).

In this operating mode, the device limits its output current to ca. 500mA. Should the output voltage not have

reached the input level within a maximum duration of 750µs, the device automatically increases its pre-charge

current to ca. 2000mA. If the output voltage still fails to reach its target after 1.5ms, a fault condition is declared.

After waiting 1ms, a restart is attempted.

When output voltage being close to Vout, the device enters into boost startup mode (for Auto Mode only). The

device provides a reduced current limit of ~1.25A (I2C programable for TPS61280A to set it back to normal

current limit) when the output voltage is below pre-set voltage to avoid the high inrush current from battery.

During start-up, it is recommended to keep DC load current draw below 250mA.

The TPS6128xA device contains a thermal regulation loop that monitors the die temperature during the pre-

charge phase. If the die temperature rises to high values of about 110°C, the device automatically reduces the

current to prevent the die temperature from increasing further. Once the die temperature drops about 10°C below

the threshold, the device will automatically increase the current to the target value. This function also reduces the

current during a short-circuit condition.

When the EN and nBYP pins are set high, the device enters normal operation (that is, automatic dc/dc boost,

pass-through mode) and ensures that the output voltage remains above a pre-defined threshold (That is, 3.3V).

Setting the EN pin low (nBYP = 1) forces the TPS6128xA device in shutdown mode with a current consumption

of <8.5µA typ. In this mode, the output of the converter is regulated to a minimum level so as to limit the input-to-

output voltage difference to less than 3.6V (typ). The device is capable of sinking up to 10mA output current and

prohibits reverse current flow from the output to the input. For proper operation, the EN pin must be terminated

and must not be left floating.

Changing operating mode from auto mode (EN = nBYP = 1) to low IQPass-through mode (EN = nBYP = 0) with

device pins EN and nBYP can either be done controlling EN and nBYP pins from same control signal (delay

between signal < 60ns) or first switching in forced pass-through mode (EN = 1, nBYP = 0) followed by switching

to low IQPass-through mode (EN = nBYP = 0).

The TPS6128xA device also features the possibility of shutting the converter's output for a short period of time,

either via the nRST/nFAULT (GPIO). Pulling this input low initiates a reset of the converter's output. The

sequence is falling edge-triggered and consists of a discharge phase (down to ca. 600mV or lower) of the

capacitance located at the converter's output followed by a start-up phase.

Table 2. Mode of Operation

EN Input nBYP Input Device State

0 0 The device is shut down in pass-through mode featuring a shutdown current down to ca. 3µA typ.

The load current capability is limited (up to ca. 250mA).

0 1 The device is shut down and the output voltage is reduced to a minimum value (VIN - VOUT ≤3.6V).

The device shutdown current is approximately 8.5µA typ.

1 0 The device is active in forced pass-through mode.

The device supply current is approximately 15µA typ. from the battery. The device is short circuit protected

by a current limit of ca.7300mA.

1 1 The device is active in auto mode (dc/dc boost, pass-through).

The device supply current is approximately 50µA typ. from the battery.

10.4.6 Undervoltage Lockout

The under voltage lockout circuit prevents the device from malfunctioning at low input voltages and the battery

from excessive discharge. The I2C control interface and the output stage of the converter are disabled once the

falling VIN trips the under-voltage lockout threshold VUVLO (2V typ). The device starts operation once the rising VIN

trips VUVLO threshold plus its hysteresis of 100 mV at typ. 2.1V.

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10.4.7 Thermal Shutdown

As soon as the junction temperature, TJ, exceeds 160°C (typ.) the device goes into thermal shutdown. In this

mode the bypass, high-side and low-side MOSFETs are turned-off. When the junction temperature falls below

the thermal shutdown minus its hysteresis, the device continuous the operation.

10.4.8 Fault State and Power-Good

The TPS6128xA enters the fault state under any of the followings conditions:

• The output voltage fails to achieve the required level during a start-up phase.

• The output voltage falls out of regulation (in pre-charge mode).

• The device has entered thermal shutdown.

Once a fault is triggered, the regulator stops operating and disconnects the load. After waiting 1ms, the device

attempts to restart. The TPS61280A device can be configured to signal a fault condition by pulling the open-drain

GPIO pin (nFAULT) low for a short period of time. The nFAULT output provides a falling edge triggered interrupt

signal to the host. To ensure proper operation, the GPIO port needs to be pull high quick enough, that is, faster

than ca. 200ns. To do so, it is recommended to use a GPIO pull-up resistor in the range of 1kΩto 10kΩ.

The TPS6128xA (simple logic I/F version) device only provide a power-good output (PG) for signaling the system

when the regulator has successfully completed start-up and no faults have occurred. Power-good also functions

as an early warning flag for excessive die temperature and overload conditions.

• PG is asserted high when the start-up sequence is successfully completed.

• PG is pulled low when the output voltage falls approximately 10% below its regulation level or the die

temperature exceeds 115°C. PG is re-asserted high when the device cools below ca. 100°C.

• Any fault condition causes PG to be de-asserted.

• PG is pulled high when the device is operating in forced pass-through mode (that is, nBYP = L).

• PG is pulled high when the device is in shutdown mode.

Dataline

stable;

datavalid

DATA

CLK

Change

ofdata

allowed

START Condition

DATA

CLK

STOP Condition

S P

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10.5 Programming

10.5.1 Serial Interface Description (TPS61280A)

I2C™ is a 2-wire serial interface developed by Philips Semiconductor, now NXP Semiconductors (see I2C-Bus

Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-

up structures. When the bus is idle, both SDA and SCL lines are pulled high. All the I2C compatible devices

connect to the I2C bus through open drain I/O pins, SDA and SCL. A master device, usually a microcontroller or

a digital signal processor, controls the bus. The master is responsible for generating the SCL signal and device

addresses. The master also generates specific conditions that indicate the START and STOP of data transfer. A

slave device receives and/or transmits data on the bus under control of the master device.

The TPS6128xA device works as a slave and supports the following data transfer modes, as defined in the I2C-

Bus Specification: standard mode (100 kbps) and fast mode (400 kbps), fast mode plus (1 Mbps) and high-speed

mode (3.4 Mbps). The interface adds flexibility to the power supply solution, enabling most functions to be

programmed to new values depending on the instantaneous application requirements. Register contents remain

intact as long as supply voltage remains above 2.1V.

The data transfer protocol for standard and fast modes is exactly the same, therefore they are referred to as F/S-

mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as HS-

mode. The TPS6128xA device supports 7-bit addressing; 10-bit addressing and general call address are not

supported. The device 7bit address is defined as ‘111 0101’.

It is recommended that the I2C masters initiates a STOP condition on the I2C bus after the initial power up of

SDA and SCL pull-up voltages to ensure reset of the TPS6128xA I2C engine.

10.5.2 Standard-, Fast-, Fast-Mode Plus Protocol

The master initiates data transfer by generating a start condition. The start condition is when a high-to-low

transition occurs on the SDA line while SCL is high, as shown in Figure 20. All I2C-compatible devices should

recognize a start condition.

Figure 20. START and STOP Conditions

The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W

on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires

the SDA line to be stable during the entire high period of the clock pulse (see Figure 21). All devices recognize

the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a

matching address generates an acknowledge (see Figure 22) by pulling the SDA line low during the entire high

period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a

slave has been established.

Figure 21. Bit Transfer on the Serial Interface

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Programming (continued)

The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the

slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an

acknowledge signal can either be generated by the master or by the slave, depending on which one is the

receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as

necessary.

To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to

high while the SCL line is high (see Figure 20). This releases the bus and stops the communication link with the

addressed slave. All I2C compatible devices must recognize the stop condition. Upon the receipt of a stop

condition, all devices know that the bus is released, and they wait for a start condition followed by a matching

address.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

Figure 22. Acknowledge on the I2C Bus

Figure 23. Bus Protocol

Slave Address R/W A Register Address A P

171 1 1 1

Data

A/A

HS-Master Code A

1 1

F/S Mode HS Mode F/S Mode

Data Transferred

(n x Bytes + Acknowledge) HS Mode Continues

From Master to TPS6128xA

From TPS6128xA to Master

A = Acknowledge (SDA low)

= Not acknowledge (SDA high)

S = START condition

Sr = REPEATED START condition

P = STOP condition

Slave AddressSr

Slave Address R/W A Register Address A Data P

171 1 1 1 1

“0” Write

Slave Address R/W

“1” Read

From Master to TPS6128xA

From TPS6128xA to Master

A/A

A = Acknowledge (SDA low)

= Not acknowledge (SDA high)

S = START condition

Sr = REPEATED START condition

P = STOP condition

Slave Address R/W A Register Address A Data A/A PS

171 1 1 1 1

8 8

“0” Write

From Master to TPS6128xA

From TPS6128xA to Master

A = Acknowledge (SDA low)

= Not acknowledge (SDA high)

S = START condition

Sr = REPEATED START condition

P = STOP condition

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Programming (continued)

10.5.3 HS-Mode Protocol

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of

the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be

used to secure the bus in HS-mode.

Attempting to read data from register addresses not listed in this section will result in 00h being read out.

10.5.4 TPS6128xA I2C Update Sequence

The TPS6128xA requires a start condition, a valid I2C address, a register address byte, and a data byte for a

single update. After the receipt of each byte, TPS6128xA device acknowledges by pulling the SDA line low

during the high period of a single clock pulse. A valid I2C address selects the TPS6128xA. TPS6128xA performs

an update on the falling edge of the acknowledge signal that follows the LSB byte.

Figure 24. : “Write” Data Transfer Format in Standard-, Fast, Fast-Plus Modes

Figure 25. “Read” Data Transfer Format in Standard-, Fast, Fast-Plus Modes

Figure 26. Data Transfer Format in H/S-Mode

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10.6 Register Maps

10.6.1 Slave Address Byte

MSB LSB

1 1 1 0 1 A1 A0

The slave address byte is the first byte received following the START condition from the master device.

10.6.2 Register Address Byte

MSB LSB

0 0 0 0 0 D2 D1 D0

Following the successful acknowledgment of the slave address, the bus master will send a byte to the

TPS6128xA, which will contain the address of the register to be accessed.

10.6.3 I2C Registers, E2PROM, Write Protect

Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The

I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the

E2PROMCTRL Register, it is possible to store the active configuration in non-volatile E2PROM; during power-up,

the contents of the E2PROM are copied into the I2C registers and used to configure the device.

NOTE

An active high Write Protect (WP) bit prevents the configuration parameters from being

changed by accident. Once the E2PROM memory has been programmed with Write

Protect (WP) bit set, its content will be locked and can not be reprogrammed any more.

Configuration parameters can be read from the I2C register(s) or E2PROM registers at any time (the WP bit has

no effect on read operations).

10.6.4 E2PROM Configuration Parameters

Table 3 shows the memory map of the configuration parameters.

Table 3. Configuration Memory Map

Address Register Name Factory

Default Description

01h CONFIG Register xxh Sets miscellaneous configuration bits

02h VOUTFLOORSET Register xxh Sets the floor output voltage threshold boost / pass-through mode change

(VSEL = L)

03h VOUTROOFSET Register xxh Sets the roof output voltage threshold boost / pass-through mode change

(VSEL = H)

04h ILIMSET Register xxh Sets the average input current limit in dc/dc boost mode

05h Status Register xxh Returns status flags

FFh E2PROMCTRL Register 00h Controls whether read and write operations access

I2C or E2PROM registers

S0A A7-Bit Slave Address Control Register Address Control Register Data A

EAh

FFh C0h

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The following procedure details how to save the content of all I2C registers to the E2PROM non-volatile

configuration memory.

1. Bus master sends START condition

2. Bus master sends 7-bit slave address plus low R/W bit (for example EAh)

3. TPS6128xA acknowledges (SDA low)

4. Bus master sends address of E2PROMCTRL Register (FFh)

5. TPS6128xA acknowledges (SDA low)

6. Bus master sends data to be written to the Control Register (C0h)

7. TPS6128xA acknowledges (SDA low)

8. Bus master sends STOP condition

Figure 27. Saving Contents of all I2C Registers to E2PROM

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10.6.5 CONFIG Register

Memory location: 0x01

Description RESET ENABLE RESERVED GPIOCFG SSFM MODE_CTRL

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type R/W R/W R/W R/W R/W R/W R/W R/W

Default value 00000001

Stored in

E2PROM? N Y Y N Y Y Y Y

Bit Description

RESET Device reset bit.

0: Normal operation.

1: Default values are set to all internal registers. The device operation is cycled (ON-OFF-ON), that is, the converter

is disabled for a short period of time and the output is reset.

ENABLE[1:0] Device enable bits.

00: Device operation follows hardware control signal (refer toTable 2).

01: Device operates in auto transition mode (dc/dc boost, bypass) regardless of the nBYP control signal (EN = 1).

10: Device is forced in pass-through mode regardless of the nBYP control signal (EN = 1).

11: Device is in shutdown mode. The output voltage is reduced to a minimum value (VIN - VOUT ≤3.6V)

regardless of the nBYP control signal (EN = 1).

RESERVED Reserved bit.

This bits is reserved for future use. During write operations data intended for this bit is ignored, and during read

operations 0 is returned.

GPIOCFG GPIO port configuration bit.

0: GPIO port is configured to support manual reset input (nRST) and interrupt generation output (nFAULT).

1: GPIO port is configured as a device mode selection input.

SSFM Spread modulation control.

0: Spread spectrum modulation is disabled.

1: Spread spectrum modulation is enabled in PWM mode.

MODE_CTRL[1:0] Device mode of operation bits.

00: Device operation follows hardware control signal (GPIO must be configured as mode selection input).

01: PFM with automatic transition into PWM operation.

10: Forced PWM operation.

11: PFM with automatic transition into PWM operation (VSEL = L), forced PWM operation (VSEL = H).

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10.6.6 VOUTFLOORSET Register

Memory location: 0x02

Description RESERVED RESERVED RESERVED VOUTFLOOR_TH

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type R/W R/W R/W R/W R/W R/W R/W R/W

Default value 00000110

Stored in

E2PROM? N N N Y Y Y Y Y

Bit Description

RESERVED Reserved bit.

This bits is reserved for future use. During write operations data intended for this bit is ignored, and during

read operations 0 is returned.

VOUTFLOOR_TH[4:0] Output voltage threshold, dc/dc boost / pass-through mode change.

00000: 2.850V

00001: 2.900V

00010: 2.950V

00011: 3.000V

00100: 3.050V

00101: 3.100V

00110: 3.150V

00111: 3.200V

01000: 3.250V

01001: 3.300V

01010: 3.350V

01011: 3.400V

01100: 3.450V

01101: 3.500V

01110: 3.550V

01111: 3.600V

10000: 3.650V

10001: 3.700V

10010: 3.750V

10011: 3.800V

10100: 3.850V

10101: 3.900V

10110: 3.950V

10111: 4.000V

11000: 4.050V

11001: 4.100V

11010: 4.150V

11011: 4.200V

11100: 4.250V

11101: 4.300V

11110: 4.350V

11111: 4.400V

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10.6.7 VOUTROOFSET Register

Memory location: 0x03

Description RESERVED RESERVED RESERVED VOUTROOF_TH

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type R/W R/W R/W R/W R/W R/W R/W R/W

Default value 00001010

Stored in

E2PROM? N N N Y Y Y Y Y

Bit Description

RESERVED Reserved bit.

This bits is reserved for future use. During write operations data intended for this bit is ignored, and during

read operations 0 is returned.

VOUTROOF_TH[4:0] Output voltage threshold, dc/dc boost / pass-through mode change.

00000: 2.850V

00001: 2.900V

00010: 2.950V

00011: 3.000V

00100: 3.050V

00101: 3.100V

00110: 3.150V

00111: 3.200V

01000: 3.250V

01001: 3.300V

01010: 3.350V

01011: 3.400V

01100: 3.450V

01101: 3.500V

01110: 3.550V

01111: 3.600V

10000: 3.650V

10001: 3.700V

10010: 3.750V

10011: 3.800V

10100: 3.850V

10101: 3.900V

10110: 3.950V

10111: 4.000V

11000: 4.050V

11001: 4.100V

11010: 4.150V

11011: 4.200V

11100: 4.250V

11101: 4.300V

11110: 4.350V

11111: 4.400V

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10.6.8 ILIMSET Register

Memory location: 0x04

Description RESERVED RESERVED ILIM OFF Soft-start ILIM

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type R/W R/W R/W R/W R/W R/W R/W R/W

Default value 00011011

Stored in

E2PROM? N N N Y Y Y Y Y

(1) Refer to Start-Up and Shutdown Mode section for additional information.

Bit Description

RESERVED Reserved bit.

This bits is reserved for future use. During write operations data intended for this bit is ignored, and during read

operations 0 is returned.

ILIM[3:0] Inductor valley current limit in dc/dc boost mode (COUTRNG bit = 0)(1).

1000: 1500mA

1001: 2000mA

1010: 2500mA

1011: 3000mA

1100: 3500mA

1101: 4000mA

1110: 4500mA

1111: 5000mA

Soft-Start Soft-start selection bit.

0: DC/DC boost soft-start current is limited per ILIM bit settings

1: DC/DC boost soft-start current is limited to ca. 1250mA inductor valley current

ILIM OFF Enable/Disable Current Limit

0 : Current Limit Enabled

1 : Current Limit Disabled

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10.6.9 Status Register

Memory location: 0x05

Description TSD HOTDIE DCDCMODE OPMODE ILIMPT ILIMBST FAULT PGOOD

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type RRRRRRRR

Default value 00000000

Stored in

E2PROM? NNNNNNNN

Bit Description

TSD Thermal shutdown status bit.

0: Normal operation.

1: Thermal shutdown tripped. This flag is reset after readout.

HOTDIE Instantaneous die temperature bit.

0: TJ< 115ºC.

1: TJ> 115ºC.

DCDCMODE DC/DC mode of operation status bit.

1: Device operates in PFM mode.

0: Device operates in PWM mode.

OPMODE Device mode of operation status bit.

0: Device operates in pass-through mode.

1: Device operates in dc/dc mode.

ILIMPT Current limit status bit (pass-through mode).

0: Normal operation.

1: Indicates that the bypass FET current limit has triggered. This flag is reset after readout.

ILIMBST Current limit status bit (dc/dc boost mode).

0: Normal operation.

1: Indicates that the average input current limit has triggered for 1.5ms in dc/dc boost mode. This flag is reset after

readout.

FAULT FAULT status bit.

0: Normal operation.

1: Indicates that a fault condition has occurred. This flag is reset after readout.

PGOOD Power Good status bit.

0: Indicates the output voltage is out of regulation.

1: Indicates the output voltage is within its nominal range. This bit is set if the converter is forced in pass-through

mode.

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10.6.10 E2PROMCTRL Register

Memory location: 0xFF

Description WEN WP ISE2PROMWP RESERVED RESERVED RESERVED RESERVED RESERVED

Bits D7 D6 D5 D4 D3 D2 D1 D0

Memory type R/W R/W R R/W R/W R/W R/W R/W

Default value 0 0 0 0 0 0 0 0

Stored in E2PROM? N Y N N N N N N

Bit Description

WEN E2PROM Write Enable bit.

0: No operation.

1: Forces the contents of selected I2C register bits to be copied into E2PROM, thereby making them the default

values during power-up. When the contents of all the I2C register bits have been written to the E2PROM, the device

automatically resets this bit.

WP E2PROM Write Protect bit.

0: Normal operation.

1: Forces the E2PROM content to be locked following a write sequence (WEN = 1). This protects the E2PROM

content from undesirable write actions making it virus safe. This process is non reversible.

ISE2PROMWP E2PROM Write Protect Status bit.

0: E2PROM content is not write protected. E2PROM content can still be updated.

1: E2PROM content is write protected. E2PROM content is permanently locked.

RESERVED Reserved bit.

This bits is reserved for future use. During write operations data intended for this bit is ignored, and during read

operations 0 is returned.

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11 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

11.1 Application Information

The devices are step up dc/dc converters with true bypass function integrated. They are typically used as

preregulators with input voltage ranges from 2.3V to 4.8V, extend the battery run time and overcome input

current and input voltage limitations of the system being powered.

While the input voltage higher than boost/bypass threshold, the high-efficient integrated pass-through path

connects the battery to the powered system directly.

If the input voltage becomes lower than boost/bypass threshold, the device seamlessly transitions into boost

mode operation with a maximum available output current of 3 A.

The following design procedure can be used to select component values for the TPS61281A and TPS61282A

(also applicable for TPS61280A just by I2C program).

VBAT’

PMIC

eMMC, 2.95V

LCD, 2.80V

Antenna switches

2.60V

10 F

DECOUPLING

Vcore1, 1.05V

Vcore2, 1.15V

10 F

DECOUPLING

WIFI PA

WL8PM27

4.7 F

SMPS

SuPA

BUCK

PMIC

eMMC, 2.95V

Note: Resistive load equivalent

for the measurement result.

Antenna switches

2.60V

Vcore1, 1.05V

Vcore2, 1.15V

WIFI PA

SMPS

SuPA

BUCK

LDOLDO

Battery

2.7V .. 4.35V

Battery

200 to 600mV

2.7V

3G PA

LM3242

10 µF

SuPA

BUCK / BYPASS

1.5µF X5R 6.3V (0402)

C (x2)

10µF X5R 6.3V (0603)

0.47 μH

VIN

VSEL

BYP

MODE

PGND

VOUT

AGND

Enable 1.8V

Interrupt

Forced Bypass / Auto

Voltage Select

PFM/FPWM

TPS61281A

4.7 F

2G PA

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11.2 Typical Application

11.2.1 TPS61281A with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280A with I2C Programmable)

Figure 28. TPS61281A Application Circuit with 1500mA Output Current

11.2.1.1 Design Requirement

Table 4. Design Parameters

REFERENCE DESCRIPTION SAMPLE VALUES

VIN Input voltage range 2.5V-4.35V

VOUT Output voltage range at VSEL = Low VOUT= 3.15V if VIN ≤3.15V, VOUT = VIN if VIN > 3.15V

VOUT Output voltage range VSEL = High VOUT= 3.35V if VIN ≤3.35V, VOUT = VIN if VIN > 3.35V

IOUT Output current 1500mA

11.2.1.2 Detailed Design Parameters

11.2.1.2.1 Inductor Selection

A boost converter normally requires two main passive components for storing energy during the conversion, an

inductor and an output capacitor are required. It is advisable to select an inductor with a saturation current rating

higher than the possible peak current flowing through the power switches.

OUT OUT IN

MIN

OUT

I x (V - V )

C = f x V x VD

OUT

L(DC) OUT

I = x x I

OUT

IN IN

L(PEAK)

OUT

V x D V

I = + with D 1

2 x f x L (1 D) x V

= -

- h

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The inductor peak current varies as a function of the load, the input and output voltages and can be estimated

using Equation 8.

(8)

Selecting an inductor with insufficient saturation performance can lead to excessive peak current in the

converter. This could eventually harm the device and reduce it's reliability.

When selecting the inductor, as well as the inductance, parameters of importance are: maximum current rating,

series resistance, and operating temperature. The inductor DC current rating should be greater than the

maximum input average current, refer to Equation 9 and the Current Limit Operation section for more details.

(9)

The TPS6128xA series of step-up converters have been optimized to operate with a effective inductance in the

range of 200nH to 800nH. Larger or smaller inductor values can be used to optimize the performance of the

device for specific operating conditions. For more details, see the Checking Loop Stability section.

In high-frequency converter applications, the efficiency is essentially affected by the inductor AC resistance (that

is, quality factor) and to a smaller extent by the inductor DCR value. To achieve high efficiency operation, care

should be taken in selecting inductors featuring a quality factor above 25 at the switching frequency. Increasing

the inductor value produces lower RMS currents, but degrades transient response. For a given physical inductor

size, increased inductance usually results in an inductor with lower saturation current.

The total losses of the coil consist of both the losses in the DC resistance, R(DC) , and the following frequency-

dependent components:

• The losses in the core material (magnetic hysteresis loss, especially at high switching frequencies)

• Additional losses in the conductor from the skin effect (current displacement at high frequencies)

• Magnetic field losses of the neighboring windings (proximity effect)

• Radiation losses

For good efficiency, the inductor’s DC resistance should be less than 30mΩ. The following inductor series from

different suppliers have been used with the TPS6128xA converters.

Table 5. List of Inductors

SERIES DIMENSIONS (in mm) DC INPUT CURRENT LIMIT SETTING

DFE252010C 2.5 x 2.0 x 1.0 max. height ≤3000 mA

DFE252012C 2.5 x 2.0 x 1.2 max. height ≤3500 mA

DFR252010C 2.5 x 2.0 x 1.0 max. height ≤3000 mA

DFE252012C 2.5 x 2.0 x 1.2 max. height ≤3500 mA

DFE252012P 2.5 x 2.0 x 1.2 max. height ≤3500 mA

DFE201610C 2.0 x 1.6 x 1.0 max. height ≤2000 mA

DFE201612C 2.0 x 1.6 x 1.2 max. height ≤3000 mA

DFE201612P 2.0 x 1.6 x 1.2 max. height ≤3000 mA

11.2.1.2.2 Output Capacitor

For the output capacitor, it is recommended to use small ceramic capacitors placed as close as possible to the

VOUT and GND pins of the IC. If, for any reason, the application requires the use of large capacitors which can

not be placed close to the IC, using a smaller ceramic capacitor in parallel to the large one is highly

recommended. This small capacitor should be placed as close as possible to the VOUT and GND pins of the IC.

To get an estimate of the recommended minimum output capacitance, Equation 10 can be used.

where

• f is the switching frequency which is 2.3MHz (typ.) and ΔV is the maximum allowed output ripple. (10)

OUT L

OUT(ESL) OUT

SW(FALL)

IΔI 1

ΔV = ESL x - - I x

1 - D 2 t

æ ö

ç ÷

è ø

OUT L

OUT(ESL) OUT

SW(RISE)

IΔI 1

ΔV = ESL x + - I x

1 - D 2 t

æ ö

ç ÷

è ø

OUT L

OUT(ESR)

IΔI

ΔV = ESR x +

1 - D 2

æ ö

ç ÷

è ø

TPS61280A

TPS61281A

TPS61282A

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

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Product Folder Links: TPS61280A TPS61281A TPS61282A

With a chosen ripple voltage of 20mV, a minimum effective capacitance of 10μF is needed. The total ripple is

larger due to the ESR and ESL of the output capacitor. This additional component of the ripple can be calculated

using Equation 11

(11)

(12)

where

• IOUT = output current of the application

• D = duty cycle

•ΔIL= inductor ripple current

• tSW(RISE) = switch node rise time

• tSW(FALL) = switch node fall time

• ESR = equivalent series resistance of the used output capacitor

• ESL = equivalent series inductance of the used output capacitor (13)

An MLCC capacitor with twice the value of the calculated minimum should be used due to DC bias effects. This

is required to maintain control loop stability. The output capacitor requires either an X7R or X5R dielectric. Y5V

and Z5U dielectric capacitors, aside from their wide variation in capacitance over temperature, become resistive

at high frequencies. There are no additional requirements regarding minimum ESR. Larger capacitors cause

lower output voltage ripple as well as lower output voltage drop during load transients.

In applications featuring high (pulsed) load currents (e.g. ≥2Amps), it is recommended to run the converter with a

reasonable amount of effective output capacitance and low-ESL device, for instance x2 22µF X5R 6.3V (0603)

MLCC capacitors connected in parallel with a 1µF X5R 6.3V (0306-2T) MLCC LL capacitor.

DC bias effect: high cap. ceramic capacitors exhibit DC bias effects, which have a strong influence on the

device's effective capacitance. Therefore the right capacitor value has to be chosen very carefully. Package size

and voltage rating in combination with material are responsible for differences between the rated capacitor value

and it's effective capacitance. For instance, a 10µF X5R 6.3V (0603) MLCC capacitor would typically show an

effective capacitance of less than 5µF (under 3.5V bias condition, high temperature).

For RF Power Amplifier applications, the output capacitor loading is combined between the dc/dc converter and

the RF Power Amplifier (x2 10µF X5R 6.3V (0603) + PA input cap 4.7µF X5R 6.3V (0402)) are recommended.

High values of output capacitance are mainly achieved by putting capacitors in parallel. This reduces the overall

series resistance (ESR) to very low values. This results in almost no voltage ripple at the output and therefore

the regulation circuit has no voltage drop to react on. Nevertheless to guarantee accurate output voltage

regulation even with very low ESR the regulation loop can switch to a pure comparator regulation scheme.

11.2.1.2.3 Input Capacitor

Multilayer ceramic capacitors are an excellent choice for input decoupling of the step-up converter as they have

extremely low ESR and are available in small footprints. Input capacitors should be located as close as possible

to the device. While a 4.7μF input capacitor is sufficient for most applications, larger values may be used to

reduce input current ripple without limitations.

Take care when using only ceramic input capacitors. When a ceramic capacitor is used at the input and the

power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce

ringing at the VIN pin. This ringing can couple to the output and be mistaken as loop instability or could even

damage the part. Additional "bulk" capacitance (electrolytic or tantalum) should in this circumstance be placed

between CIand the power source lead to reduce ringing than can occur between the inductance of the power

source leads and CI.

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(1) See Third-Party Products Disclaimer

11.2.1.2.4 Checking Loop Stability

The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:

• Switching node, SW

• Inductor current, IL

• Output ripple voltage, VOUT(AC)

These are the basic signals that need to be measured when evaluating a switching converter. When the

switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the

regulation loop may be unstable. This is often a result of board layout and/or L-C combination.

As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between

the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply

all of the current required by the load. VOUT immediately shifts by an amount equal to ΔI(LOAD) x ESR, where ESR

is the effective series resistance of COUT.ΔI(LOAD) begins to charge or discharge COUT generating a feedback

error signal used by the regulator to return VOUT to its steady-state value. The results are most easily interpreted

when the device operates in PWM mode.

During this recovery time, VOUT can be monitored for settling time, overshoot or ringing that helps judge the

converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin. Because the

damping factor of the circuitry is directly related to several resistive parameters (that is, MOSFET rDS(on)) that are

temperature dependant, the loop stability analysis has to be done over the input voltage range, load current

range, and temperature range.

The TPS6128xA series of step-up converters have been optimized to operate with a effective inductance in the

range of 200nH to 800nH and with output capacitors in the range of 8uF to 100µF. The internal compensation is

optimized for an output filter of L = 0.5µH and CO= 15µF.

Table 6. Component List

REFERENCE DESCRIPTION PART NUMBER, MANUFACTURER(1)

CIN 1.5μF, 6.3V, 0402, X5R ceramic GRM155R60J155ME80D

COUT 2 x 10μF, 6.3V, 0603, X5R ceramic 2 x GRM188R60J106ME84

L 470nH, 47mΩ, 2.5mm x 2.0mm x 1.2mm DFE252012CR470

3.055

3.087

3.118

3.15

3.181

3.213

3.244

3.276

0.0001 0.001 0.01 0.1 1 2

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

3.055

3.087

3.118

3.15

3.181

3.213

1.5 1.9 2.3 2.7

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.0V

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 2

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.6V

VIN = 4.3V

85.0

90.0

95.0

100.0

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

Current (A)

Efficiency (%)

V = 3.0V

VIN = 2.7V

VIN = 2.5V VIN = 3.6V

VIN = 4.3V

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 2

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.6V

VIN = 4.3V

85.0

90.0

95.0

100.0

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V VIN = 3.6V

VIN = 4.3V

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TPS61281A

TPS61282A

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Product Folder Links: TPS61280A TPS61281A TPS61282A

11.2.1.3 Application Performance Curves

VOUT = 3.15 V VSEL = Low Mode = Low

Figure 29. TPS61281A Efficiency vs Output Current

VOUT = 3.15 V VSEL = Low Mode = Low

Figure 30. TPS61281A Efficiency vs Output Current

VOUT = 3.35 V VSEL = High Mode = Low

Figure 31. TPS61281A Efficiency vs Output Current

VOUT = 3.35 V VSEL = High Mode = Low

Figure 32. TPS61281A Efficiency vs Output Current

VOUT = 3.15 V Mode = Low

Figure 33. TPS61281A DC Output Voltage vs Output

Current

VOUT = 3.15 V Mode = Low

Figure 34. TPS61281A DC Output Voltage vs Output

Current

2.1

2.2

2.3

2.4

2.5

2.6

2.7

2.8

2.9

3.1

2.5 2.6 2.7 2.8 2.9 3 3.1 3.2

Input Voltage (V)

Output Current (A)

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

Input Voltage (V)

Output Voltage (V)

I = 1mA

OUT

I = 100mA

OUT

I = 1000mA

OUT

I = 1500mA

OUT

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

Input Voltage (V)

Output Voltage (V)

I = 1mA

OUT

IOUT = 100mA

IOUT = 1000mA

IOUT = 1500mA

3.25

3.284

3.317

3.35

3.384

3.417

3.451

3.484

0.0001 0.001 0.01 0.1 1 2

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

3.25

3.284

3.317

3.35

3.384

3.417

1.6 2 2.4 2.8

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

VIN = 3.2V

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VOUT = 3.35 V Mode = Low

Figure 35. TPS61281A DC Output Voltage vs Output

Current

VOUT = 3.35 V Mode = Low

Figure 36. TPS61281A DC Output Voltage vs Output

Current

VOUT = 3.15 V VSEL = Low

Figure 37. TPS61281A DC Output Voltage vs Input Voltage

VOUT = 3.35 V VSEL = High Mode = Low

Figure 38. TPS61281A DC Output Voltage vs Input Voltage

VOUT = 3.35 V TA= 85°C Mode = Low

Figure 39. TPS61281A Maximum Output Current vs Input

Voltage Figure 40. Boost to Pass-Through Mode Exit / Entry

TPS61280A

TPS61281A

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Figure 41. TPS61281A Dynamic Voltage Management

(VSEL) Load Current 50 mA Figure 42. TPS61281A Dynamic Voltage Management

(VSEL) Load Current 500 mA

Figure 43. TPS61281A Forced Pass-Through to Boost

Mode Transition Figure 44. TPS61280A, 81A Load Transient Response In

PFM/PWM Operation

Figure 45. TPS61280A, 81A Load Transient Response In

PFM/PWM Operation Figure 46. Start-Up at No Load

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Figure 47. Start-Up at 30-ΩLoad

VBAT’

Battery

2.7V .. 4.35V

PMIC

eMMC, 2.95V

LCD, 2.80V

Antenna switches

2.60V

10 F

DECOUPLING

Vcore1, 1.05V

Vcore2, 1.15V

10 F

DECOUPLING

WIFI PA

WL8PM27

4.7 F

SMPS

SuPA

BUCK

Battery

PMIC

eMMC, 2.95V

LCD, 2.80V

Antenna switches

2.60V

Vcore1, 1.05V

Vcore2, 1.15V

WIFI PA

SMPS

SuPA

BUCK

LDOLDO

2G PA

4.7 µF

3G PA

LM3242

10 µF

3G PA

SuPA

BUCK/BYPASS

200 to 600mV

2.7V

1.5µF X5R 6.3V (0402)

C (x4)

10µF X5R 6.3V (0603)

0.47 μH

TPS61282A

VIN

VSEL

BYP

MODE

PGND

VOUT

AGND

Enable 1.8V

Interrupt

Forced Bypass / Auto

Voltage Select

PFM/FPWM

Note: Resistive load equivalent

for the measurement result.

Note: Resistive load equivalent

for the measurement result.

TPS61280A

TPS61281A

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Product Folder Links: TPS61280A TPS61281A TPS61282A

11.2.2 TPS61282A with 2.5V-4.35 VIN, 2000 mA Output Current (TPS61280A with I2C Programmable)

Figure 48. TPS61282A Application Circuit with 2000 mA Output Current

11.2.2.1 Design Requirements

Table 7. Design Parameters

REFERENCE DESCRIPTION PART NUMBER, MANUFACTURER

VIN Input voltage range 2.5 V to 4.35 V

VOUT Output voltage range at VSEL=Low VOUT=3.3 V if VIN ≤3.3 V, VOUT= VIN if VIN >3.3 V

VOUT Output voltage range VSEL=High VOUT=3.5 V if VIN ≤3.5 V, VOUT= VIN if VIN >3. 5V

IOUT Output Current 2000 mA

(1) See Third-Party Products Disclaimer

Table 8. Component List

REFERENCE DESCRIPTION PART NUMBER, MANUFACTURER(1)

CI1.5μF, 6.3V, 0402, X5R ceramic GRM155R60J155ME80D

CO4 x 10μF, 6.3V, 0603, X5R ceramic 4 x GRM188R60J106ME84

L 470nH, 47mΩ, 2.5mm x 2.0mm x 1.2mm DFE252012CR470

11.2.2.2 Detailed Design Procedures

See TPS61281A with 2.5V-4.35 VIN, 1500 mA Output Current (TPS61280A with I2C Programmable) for all

Detailed Design Procedures.

3.201

3.234

3.267

3.3

3.333

3.366

3.399

3.432

0.0001 0.001 0.01 0.1 1 2

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

3.201

3.234

3.267

3.3

3.333

2 2.4 2.8 3.2 3.6 4

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

VIN = 3.2V

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 2

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.3V

VIN = 4.3V

85.0

90.0

95.0

100.0

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.3V

VIN = 4.3V

85.0

90.0

95.0

100.0

0.1 0.3 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.3V

VIN = 4.3V

60.0

70.0

80.0

90.0

100.0

0.0001 0.001 0.01 0.1 1 2

Current (A)

Efficiency (%)

V = 2.5V

VIN = 2.7V

VIN = 3.0V

VIN = 3.6V

VIN = 4.3V

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11.2.2.3 Application Performance Curves

VOUT = 3.3 V VSEL = Low Mode = Low

Figure 49. TPS61282A Efficiency vs Output Current

VOUT = 3.3 V VSEL = Low Mode = Low

Figure 50. TPS61282A Efficiency vs Output Current

VOUT = 3.5 V VSEL = High Mode = Low

Figure 51. TPS61282A Efficiency vs Output Current

VOUT = 3.5 V VSEL = High Mode = Low

Figure 52. TPS61282A Efficiency vs Output Current

VOUT = 3.3 V Mode = Low

Figure 53. TPS61282A DC Output Voltage vs Output

Current

VOUT = 3.3 V Mode = Low

Figure 54. TPS61282A DC Output Voltage vs Output

Current

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

Input Voltage (V)

Output Voltage (V)

I = 1mA

OUT

IOUT = 100mA

IOUT = 1000mA

IOUT = 2000mA

3.0

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

4.0

4.1

4.2

4.3

4.4

4.5

2.5 2.7 2.9 3.1 3.3 3.5 3.7 3.9 4.1 4.3 4.5

Output Voltage(V)

Input Voltage(V)

Iout=1mA

Iout=100mA

Iout=1000mA

Iout=2000mA

C013

IOUT = 1mA

IOUT = 100mA

IOUT = 1000mA

IOUT = 2000mA

3.395

3.43

3.465

3.5

3.535

3.57

3.605

3.64

0.0001 0.001 0.01 0.1 1 2

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

3.395

3.43

3.465

3.5

3.535

3.57

1.8 2.2 2.6 3 3.4 3.8

Current (A)

Output Voltage (V)

V = 2.5V

VIN = 2.7V

VIN = 2.9V

VIN = 3.1V

VIN = 3.2V

VIN = 3.4V

TPS61280A

TPS61281A

TPS61282A

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Product Folder Links: TPS61280A TPS61281A TPS61282A

VOUT = 3.5 V Mode = Low

Figure 55. TPS61282A DC Output Voltage vs Output

Current

VOUT = 3.5 V Mode = Low

Figure 56. TPS61282A DC Output Voltage vs Output

Current

VOUT = 3.3 V VSEL = Low Mode = Low

Figure 57. TPS61282A DC Output Voltage vs Input Voltage

VOUT = 3.5 V VSEL = High Mode = Low

Figure 58. TPS61282A DC Output Voltage vs Input Voltage

Figure 59. Boost to Pass-Through Mode Exit / Entry Figure 60. TPS61282A Dynamic Voltage Management

(VSEL) Load Current 50mA

TPS61280A

TPS61281A

TPS61282A

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Figure 61. TPS61282A Dynamic Voltage Management

(VSEL) Load Current 500mA Figure 62. TPS61282A Line Transient

Figure 63. TPS61282A Load Transient Response In PWM

Operation Figure 64. TPS61282A Load Transient Response In

PFM/PWM Operation

Cout

Cin

Vin

Vout

GND

TPS61280A

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Product Folder Links: TPS61280A TPS61281A TPS61282A

12 Power Supply Recommendations

The devices are designed to operate from an input voltage supply range between 2.3 V and 4.8 V. This input

supply should be well regulated. If the input supply is located more than a few inches from the TPS61280A,

TPS61281A or TPS61282A converter additional bulk capacitance may be required in addition to the ceramic

bypass capacitors. An electrolytic or tantalum capacitor with a value of 47 μF is a typical choice.

13 Layout

13.1 Layout Guidelines

• For all switching power supplies, the layout is an important step in the design, especially at high peak

currents and high switching frequencies.

• If the layout is not carefully done, the regulator could show stability problems as well as EMI problems.

• Therefore, use wide and short traces for the main current path and for the power ground tracks.

• To minimize voltage spikes at the converter's output:

– Place the output capacitor(s) as close as possible to GND and VOUT, as shown in Figure 65.

– The input capacitor and inductor should also be placed as close as possible to the IC.

– Use a common ground node for power ground and a different one for control ground to minimize the

effects of ground noise.

– Connect these ground nodes at any place close to the ground pins of the IC.

– Junction-to-ambient thermal resistance is highly application and board-layout dependent.

– It is suggested to maximize the pour area for all planes other than SW. Especially the ground pour should

be set to fill available PWB surface area and tied to internal layers with a cluster of thermal vias.

13.2 Layout Example

Figure 65. Suggested Layout (Top)

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13.3 Thermal Information

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added

heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-

dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

• Improving the power dissipation capability of the PCB design

• Improving the thermal coupling of the component to the PCB

• Introducing airflow in the system

As power demand in portable designs is more and more important, designers must figure the best trade-off

between efficiency, power dissipation and solution size. Due to integration and miniaturization, junction

temperature can increase significantly which could lead to bad application behaviors (that is, premature thermal

shutdown or worst case reduce device reliability).

Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where

high maximum power dissipation exists, special care must be paid to thermal dissipation issues in board design.

The device operating junction temperature (TJ) should be kept below 125°C.

TPS61280A

TPS61281A

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14 Device and Documentation Support

14.1 Device Support

14.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

14.2 Related Links

The table below lists quick access links. Categories include technical documents, support and community

resources, tools and software, and quick access to sample or buy.

Table 9. Related Links

PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL

DOCUMENTS TOOLS &

SOFTWARE SUPPORT &

COMMUNITY

TPS61280A Click here Click here Click here Click here Click here

TPS61281A Click here Click here Click here Click here Click here

TPS61282A Click here Click here Click here Click here Click here

14.3 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

14.4 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

14.5 Trademarks

E2E is a trademark of Texas Instruments.

I2C is a trademark of NXP Semiconductors.

All other trademarks are the property of their respective owners.

14.6 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

14.7 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

D1D2D3D4

B1B2B3B4

YMLLLLS

TPS6128xA

TPS61280A

TPS61281A

TPS61282A

www.ti.com

SLVSCG9B –MAY 2014–REVISED SEPTEMBER 2016

Product Folder Links: TPS61280A TPS61281A TPS61282A

15 Mechanical, Packaging, and Orderable Information

The following pages include mechanical packaging and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

15.1 Package Summary

Figure 66. CHIP SCALE PACKAGE

(BOTTOM VIEW) Figure 67. CHIP SCALE PACKAGE

(TOP VIEW)

Code:

• YM — Year Month date code

• LLLL — Lot trace code

• S — Assembly site code

15.2 Chip Scale Package Dimensions

The TPS6128xA device is available in a 16-bump chip scale package (YFF, NanoFree™). The package

dimensions are given as:

• D = ca. 1666 ±30 μm

• E = ca. 1666 ±30 μm

PACKAGE OPTION ADDENDUM

www.ti.com 14-Nov-2014

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

TPS61280AYFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61280A

TPS61280AYFFT ACTIVE DSBGA YFF 16 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61280A

TPS61281AYFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61281A

TPS61281AYFFT ACTIVE DSBGA YFF 16 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61281A

TPS61282AYFFR ACTIVE DSBGA YFF 16 3000 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61282A

TPS61282AYFFT ACTIVE DSBGA YFF 16 250 Green (RoHS

& no Sb/Br) SNAGCU Level-1-260C-UNLIM -40 to 85 TPS

61282A

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Nov-2014

Addendum-Page 2

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS61280AYFFR DSBGA YFF 16 3000 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1

TPS61280AYFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1

TPS61281AYFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1

TPS61282AYFFR DSBGA YFF 16 3000 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1

TPS61282AYFFT DSBGA YFF 16 250 180.0 8.4 1.78 1.78 0.69 4.0 8.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS61280AYFFR DSBGA YFF 16 3000 182.0 182.0 20.0

TPS61280AYFFT DSBGA YFF 16 250 182.0 182.0 20.0

TPS61281AYFFT DSBGA YFF 16 250 182.0 182.0 20.0

TPS61282AYFFR DSBGA YFF 16 3000 182.0 182.0 20.0

TPS61282AYFFT DSBGA YFF 16 250 182.0 182.0 20.0

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2016

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

0.625 MAX

0.30

0.12

1.2

TYP

1.2 TYP

0.4 TYP

16X 0.3

0.2

B E A

DSBGA - 0.625 mm max heightYFF0016

DIE SIZE BALL GRID ARRAY

4219386/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

BALL A1

CORNER

SEATING PLANE

BALL TYP 0.05 C

123

0.015 C A B

SYMM

SCALE 8.000

D: Max =

E: Max =

1.696 mm, Min =

1.636 mm

www.ti.com

EXAMPLE BOARD LAYOUT

16X ( 0.23)

(0.4) TYP

( 0.23)

METAL

0.05 MAX

SOLDER MASK

OPENING

METAL UNDER

SOLDER MASK

( 0.23)

SOLDER MASK

OPENING

0.05 MIN

DSBGA - 0.625 mm max heightYFF0016

DIE SIZE BALL GRID ARRAY

4219386/A 05/2016

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints. For more information,

see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

SYMM

LAND PATTERN EXAMPLE

SCALE:30X

123

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

(0.4) TYP

16X ( 0.25) (R0.05) TYP

METAL

TYP

DSBGA - 0.625 mm max heightYFF0016

DIE SIZE BALL GRID ARRAY

4219386/A 05/2016

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

SYMM

123

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL

SCALE:30X

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Mouser Electronics

Authorized Distributor

Click to View Pricing, Inventory, Delivery & Lifecycle Information:

Texas Instruments:

TPS61281AYFFR TPS61281AYFFT