C
1.5µF X5R 6.3V (0402)
I
C (x2)
10µF X5R 6.3V (0603)
O
VBAT’
L
0.47 Hμ
TPS61280A
SW
SW
VIN
VIN
VSEL
BYP
SCL
SDA
PGND
PGND
PGND
EN
VOUT
VOUT
GPIO
AGND
Battery
2.5V .. 4.35V
Enable
1.8V
Interrupt
Forced Bypass / Auto
Voltage Select
I C Bus
2
Product
Folder
Sample &
Buy
Technical
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Software
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS61280A
,
TPS61281A
,
TPS61282A
SLVSCG9B MAY 2014REVISED SEPTEMBER 2016
TPS6128xA Low-, Wide- Voltage Battery Front-End DC/DC Converter
Single-Cell Li-Ion, Ni-Rich, Si-Anode Applications
1
1 Features
1 95% Efficiency at 2.3MHz Operation
3µA Quiescent Current in Low IQPass-Through
Mode
Wide VIN Range From 2.3V to 4.8V
IOUT 4A (Peak) at VOUT = 3.35V, VIN 2.65V
Integrated Pass-Through Mode (35mΩ)
Programmable Valley Inductor Current Limit and
Output Voltage
True Pass-Through Mode During Shutdown
Best-in-Class Line and Load Transient
Low-Ripple Light-Load PFM Mode
In-Situ Customization with On-Chip E2PROM
(Write Protection)
Two Interface Options:
I2C Compatible I/F up to 3.4Mbps
(TPS61280A)
Simple I/O Logic Control Interface
(TPS6128xA)
Thermal Shutdown and Overload Protection
Total Solution Size < 20mm2, Sub 1-mm Profile
2 Applications
Single-Cell Ni-Rich, Si-Anode, Li-Ion, LiFePO4
Smart-Phones or Tablet PCs
2.5G/3G/4G Mini-Module Data Cards
Current Limited Applications Featuring High Peak
Power Loads
3 Description
The TPS6128xA device provides a power supply
solution for products powered by either by a Li-Ion,
Nickel-Rich, Silicon Anode, Li-Ion or LiFePO4 battery.
The voltage range is optimized for single-cell portable
applications like in smart-phones or tablet PCs.
Used as a high-power pre-regulator, the TPS6128xA
extends the battery run-time and overcomes input
current- and voltage limitations of the powered
system.
While in shutdown, the TPS6128xA operates in a true
pass-through mode with only 3µA quiescent
consumption for longest battery shelf life.
During operation, when the battery is at a good state-
of-charge, a low-ohmic, high-efficient integrated pass-
through path connects the battery to the powered
system.
If the battery gets to a lower state of charge and its
voltage becomes lower than the desired minimum
system voltage, the device seamlessly transits into
boost mode to uses the full battery capacity.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS61280A DSBGA (16) 1.66 mm x 1.66 mmTPS61281A
TPS61282A
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
4 Simplified Schematic
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Simplified Schematic............................................. 1
5 Revision History..................................................... 2
6 Device Comparison Table..................................... 3
7 Description (continued)......................................... 3
8 Pin Configurations and Functions....................... 4
9 Specifications......................................................... 6
9.1 Absolute Maximum Ratings ..................................... 6
9.2 ESD Ratings.............................................................. 6
9.3 Recommended Operating Conditions....................... 6
9.4 Thermal Information.................................................. 7
9.5 Electrical Characteristics........................................... 7
9.6 I2C Interface Timing Characteristics ........................ 9
9.7 I2C Timing Diagrams............................................... 11
9.8 Typical Characteristics............................................ 12
10 Detailed Description ........................................... 14
10.1 Overview ............................................................... 14
10.2 Functional Block Diagram..................................... 15
10.3 Feature Description............................................... 16
10.4 Device Functional Modes...................................... 17
10.5 Programming......................................................... 22
10.6 Register Maps....................................................... 25
11 Application and Implementation........................ 33
11.1 Application Information.......................................... 33
11.2 Typical Application................................................ 34
12 Power Supply Recommendations ..................... 46
13 Layout................................................................... 46
13.1 Layout Guidelines ................................................. 46
13.2 Layout Example .................................................... 46
13.3 Thermal Information.............................................. 47
14 Device and Documentation Support................. 48
14.1 Device Support...................................................... 48
14.2 Related Links ........................................................ 48
14.3 Receiving Notification of Documentation Updates 48
14.4 Community Resources.......................................... 48
14.5 Trademarks........................................................... 48
14.6 Electrostatic Discharge Caution............................ 48
14.7 Glossary................................................................ 48
15 Mechanical, Packaging, and Orderable
Information........................................................... 49
15.1 Package Summary................................................ 49
15.2 Chip Scale Package Dimensions.......................... 49
5 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2014) to Revision B Page
Moved Storage temperature spec, Tstg from Handling Ratings table to Abs Max Ratings table; and, re-named
Handling ratings to ESD Ratings ........................................................................................................................................... 6
Changed the device number in Figure 11 From TPS61281 and TPS61282 To: TPS61281A and TPS61282A................. 12
Changed the device number in Figure 24 through Figure 26 From TPS6128x To: TPS6128xA......................................... 24
Added legal Note at Application and Implementation section.............................................................................................. 33
Added cross reference to the Third-Party Products Disclaimer. ......................................................................................... 37
Corrected legend for Figure 30, Gray is VIN = 3.0 V, Red is VIN = 2.5 V. ............................................................................ 38
Added cross reference to Third-Party Products Disclaimer ................................................................................................. 42
Changed the markings on Figure 67 ................................................................................................................................... 49
Changes from Original (May 2014) to Revision A Page
Changed the Device Information table Package From: DGBA To: DSBGA ......................................................................... 1
Deleted the Package Marking Chip Code column from the Device Comparison Table. The information is found in
the POA at the end of the datasheet...................................................................................................................................... 3
3
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,
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,
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(1) The 'A’ version has lower ripple and overshoot, supports Forced PWM at startup but with a 0.4 μA higher IQ.
6 Device Comparison Table
PART NUMBER(1) DEVICE
SPECIFIC FEATURES
TPS61280A I2C Control Interface
User Prog. E2PROM Settings
DC/DC boost / bypass threshold = 3.15V (Vsel = L)
DC/DC boost / bypass threshold = 3.35V (Vsel = H)
Valley inductor current limit = 3A
TPS61281A Simple Logic Control Interface DC/DC boost / bypass threshold = 3.15V (Vsel = L)
DC/DC boost / bypass threshold = 3.35V (Vsel = H)
Valley inductor current limit = 3A
TPS61282A Simple Logic Control Interface DC/DC boost / bypass threshold = 3.3V (Vsel = L)
DC/DC boost / bypass threshold = 3.5V (Vsel = H)
Valley inductor current limit = 4A
7 Description (continued)
TPS6128xA device supports more than 4A pulsed load current even from a deeply discharged battery. In this
mode of operation, the TPS6128xA enables the utilization of the full battery capacity: A high battery-cut-off
voltage originated by powered components with a high minimum input voltage is overcome; new battery
chemistries can be fully discharged; high current pulses forcing the system into shutdown are buffered by the
device seamlessly transitioning between boost and by-pass mode back and forth.
This has significant impact on the battery on-time and translates into either a longer use-time and better user-
experience at an equal battery capacity or into reduced battery costs at similar use-times.
The TPS6128xA offers a small solution size (< 20mm2) due to minimum amount of external components,
enabling the use of small inductors and input capacitors, available as a 16-pin chip-scale package (CSP).
The TPS6128xA operates in synchronous, 2.3MHz boost mode and enters power-save mode operation (PFM) at
light load currents to maintain high efficiency over the entire load current range.
SW
PGND
SDA
PGND
SW
nBYP
AGND PGND
TOP VIEW
D4 D3 D2 D1
C4
PGND
C3 C2 C1
nBYP
PGND
SW SDA
AGND
BOTTOM VIEW
VSEL SCL VOUT VOUT VOUT
B1
B2
B3
B4
VOUT VSELSCL
EN GPIO VIN VIN VIN
A1
A2
A3
A4
VIN ENGPIO
SW
PGND
4
TPS61280A
,
TPS61281A
,
TPS61282A
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8 Pin Configurations and Functions
TPS61280A
16-Bump DSBGA
YFF Package
Pin Functions - TPS61280A
PIN I/O DESCRIPTION
NAME NO.
VIN A3, A4 I Power supply input.
VOUT B3, B4 O Boost converter output.
EN A1 I
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode and the I2C control interface is disabled. Depending on the
logic level applied to the nBYP input, the converter can either be forced in pass-through mode or it's output can be
regulated to a minimum level so as to limit the input-to-output voltage difference to less than 3.6V (typ). The current
consumption is reduced to a few µA. For more details, refer to Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to Table 2.
GPIO A2 I/O
This pin can either be configured as a input (mode selection) or as dual role input/open-drain output RST/FAULT )
pin. Per default, the pin is configured as RST/FAULT input/output. The input must not be left floating and must be
terminated.
Manual Reset Input: Drive RST/FAULT low to initiate a reset of the converter's output. nRST/nFAULT controls a
falling edge-triggered sequence consisting of a discharge phase of the capacitance located at the converter's output
followed by a start-up phase.
Fault Output (open-drain interrupt signal to host): Indicates that a fault has occurred (e.g. thermal shutdown, output
voltage out of limits, current limit triggered, and so on). To signal such an event, the device generates a falling edge-
triggered interrupt by driving a negative pulse onto the GPIO line and then releases the line to its inactive state.
Mode selection input = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at
high-load currents and in pulse frequency modulation mode (PFM) at light load currents.
Mode selection input = High: Low-noise mode enabled, regulated frequency PWM operation forced.
VSEL B1 I VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
nBYP C1 I A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to . This pin must
not be left floating and must be terminated.
SCL B2 I Serial interface clock line. This pin must not be left floating and must be terminated.
SDA C2 I/O Serial interface address/data line. This pin must not be left floating and must be terminated.
SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
PGND D2, D3, D4 Power ground pin.
AGND D1 Analog ground pin. This is the signal ground reference for the IC.
SW
PGND
AGND
PGND
SW
nBYP
AGND PGND
TOP VIEW
D4 D3 D2 D1
C4
PGND
C3 C2 C1
nBYP
PGND
SW AGND
AGND
BOTTOM VIEW
VSEL MODE VOUT VOUT VOUT
B1
B2
B3
B4
VOUT VSEL
MODE
EN PG VIN VIN VIN
A1
A2
A3
A4
VIN ENPG
SW
PGND
5
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(TPS6128xA)
16-Bump DSBGA
YFF Package
Pin Functions - TPS6128xA
PIN I/O DESCRIPTION
NAME NO.
VIN A3, A4 I Power supply input.
VOUT B3, B4 O Boost converter output.
EN A1 I
This is the enable pin of the device. On the rising edge of the enable pin, all the registers are reset with their default
values. This input must not be left floating and must be terminated.
EN = Low: The device is forced into shutdown mode. Depending on the logic level applied to the nBYP input, the
converter can either be forced in pass-through mode or it's output can be regulated to a minimum level so as to limit
the input-to-output voltage difference to less than 3.6V (typ). The current consumption is reduced to a few µA. For
more details, refer to Table 2.
EN = High: The device is operating normally featuring automatic dc/dc boost, pass-through mode transition. For
more details, refer to Table 2.
PG A2 O
Power-Good Output (open-drain output to host): A logic high on the PG output indicates that the converter's output
voltage is within its regulation limits. A logic low indicates a fault has occurred (e.g. thermal shutdown, output voltage
out of limits, current limit triggered, and so on). The PG signal is de-asserted automatically once the IC resumes
proper operation.
VSEL B1 I VSEL signal is primarily used to set the output voltage dc/dc boost, pass-through threshold. This pin must not be left
floating and must be terminated.
nBYP C1 I A logic low level on the BYP input forces the device in pass-through mode. For more details, refer to Table 2. This
pin must not be left floating and must be terminated.
MODE B2 I
This is the mode selection pin of the device. This pin must not be left floating, must be terminated and can be
connected to AGND. During start-up this pin must be held low. Once the output voltage settled and PG pin indicates
that the converter's output voltage is within its regulation limits the device can be forced in PWM mode operation by
applying a high level on this pin.
MODE = Low: The device is operating in regulated frequency pulse width modulation mode (PWM) at high-load
currents and in pulse frequency modulation mode (PFM) at light load currents. This pin must be held low during
device start-up.
MODE = High: Low-noise mode enabled, regulated frequency PWM operation forced.
SW C3, C4 I/O Inductor connection. Drain of the internal power MOSFET. Connect to the switched side of the inductor.
PGND D2, D3, D4 Power ground pin.
AGND C2, D1 Analog ground pin. This is the signal ground reference for the IC.
6
TPS61280A
,
TPS61281A
,
TPS61282A
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(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods my affect device reliability.
(2) All voltages are with respect to network ground terminal.
(3) Limit the junction temperature to 105°C for continuous operation at maximum output power.
(4) Limit the junction temperature to 105°C for 15% duty cycle operation.
(5) In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may
have to be derated. Maximum ambient temperature (TA(max)) is dependent on the maximum operating junction temperature (TJ(max)), the
maximum power dissipation of the device in the application (PD(max)), and the junction-to-ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max) (θJA X PD(max)). To achieve optimum performance, it is
recommended to operate the device with a maximum junction temperature of 105°C.
9 Specifications
9.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage
Voltage at VOUT(2) DC –0.3 4.7 V
Voltage at VIN(2), EN(2), VSEL(2), BYP(2), PG(2),
GPIO(2) DC –0.3 5.2 V
Voltage at SCL(2), SDA(2)MODE(2) DC –0.3 3.6 V
Voltage at SW(2) DC –0.3 4.7 V
Transient: 2 ns, 2.3
MHz –0.3 5.5 V
Differential voltage between VIN and VOUT DC 0.3 4 V
Input current Continuous average current into SW (3) 1.8 A
Peak current into SW (4) 5.5 A
Power dissipation Internally limited
Temperature range Operating temperature range, TA(5) –40 85 °C
Operating virtual junction, TJ–40 150 °C
Tstg Storage temperature range –65 150 °C
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
9.2 ESD Ratings VALUE UNIT
VESD Electrostatic discharge
Human body model (HBM), per
ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000 V
Charged device model (CDM), per JEDEC
specification JESD22-C101, all pins(2) ±1000 V
Machine Model - (MM) ±200 V
9.3 Recommended Operating Conditions MIN NOM MAX UNIT
VIInput voltage range 2.30 4.85 V
Input voltage range for in-situ customization by E2PROM write operation 3.4 3.5 3.6 V
L Inductance 200 470 800 nH
COOutput capacitance 9 13 100 µF
ILMaximum load current during start-up 250 mA
TAAmbient temperature –40 85 °C
TJOperating junction temperature –40 125 °C
7
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,
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,
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(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report (SPRA953).
9.4 Thermal Information
THERMAL METRIC(1)
TPS6128xA
UNIT
YFF PACKAGE
(DSBGA)
16 PINS
RθJA Junction-to-ambient thermal resistance 78 °C/W
RθJCtop Junction-to-case (top) thermal resistance 0.6 °C/W
RθJB Junction-to-board thermal resistance 13 °C/W
ψJT Junction-to-top characterization parameter 2.4 °C/W
ψJB Junction-to-board characterization parameter 13 °C/W
RθJCbot Junction-to-case (bottom) thermal resistance n/a °C/W
9.5 Electrical Characteristics
Minimum and maximum values are at VIN = 2.3V to 4.85V, VOUT = 3.4V (or VIN, whichever is higher), EN = 1.8V, VSEL =
1.8V, nBYP = 1.8V, –40°C TJ125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).
Typical values are at VIN = 3.2V, VOUT = 3.4V, EN = 1.8V, TJ= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
IQ
Operating quiescent current
into VIN TPS6128xA
DC/DC boost mode. Device not
switching
IOUT = 0mA, VIN = 3.2V, VOUT = 3.4V
–40°C TJ
85°C
47.4 65.6 µA
Pass-through mode (auto)
EN = 1.8V, BYP = 1.8V, VIN = 3.6V 27.4 42.6 µA
Pass-through mode (forced)
EN = 1.8V, BYP = AGND, VOUT = 3.6V 15.4 25.6 µA
Operating quiescent current
into VOUT
DC/DC boost mode. Device not
switching
IOUT = 0mA, VIN = 3.2V, VOUT = 3.4V 8.9 19.6 µA
ISD Shutdown current TPS6128xA EN = 0V, BYP = 0V, VIN = 3.6V 3.0 6.6 μA
EN = 0V, BYP = 1.8V, VIN = 3.6V 8.9 20.6 μA
VUVLO Under-voltage lockout threshold TPS6128xA Falling 2.0 2.1 V
Hysteresis 0.1 V
EN, VSEL, nBYP, MODE, SDA, SCL, GPIO, PG
VIL Low-level input voltage TPS6128xA 0.4 V
VIH High-level input voltage 1.2 V
VOL
Low-level output voltage (SDA) TPS61280A IOL = 8mA 0.3 V
Low-level output voltage (GPIO) IOL = 8mA, GPIOCFG = 0 0.3 V
Low-level output voltage (PG) TPS6128xA IOL = 8mA 0.3 V
RPD EN, VSEL, BYP,
pull-down resistance TPS6128xA Input 0.4 V 300 kΩ
CIN
EN, VSEL, BYP, MODE, PG
input capacitance TPS6128xA Input connected to AGND or VIN
9 pF
SDA, SCL, GPIO input
capacitance TPS61280A 9 pF
VTHPG Power good threshold TPS6128xA Rising VOUT 0.95 x
VOUT
Falling VOUT 0.9 x
VOUT
Ilkg Input leakage current TPS6128xA Input connected to AGND –40°C TJ
85°C 0 µA
Input connected VIN 0.5 µA
OUTPUT
VOUT(TH) Threshold DC voltage accuracy TPS6128xA No load. Open loop -1.5 +1.5 %
8
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Electrical Characteristics (continued)
Minimum and maximum values are at VIN = 2.3V to 4.85V, VOUT = 3.4V (or VIN, whichever is higher), EN = 1.8V, VSEL =
1.8V, nBYP = 1.8V, –40°C TJ125°C; Circuit of Parameter Measurement Information section (unless otherwise noted).
Typical values are at VIN = 3.2V, VOUT = 3.4V, EN = 1.8V, TJ= 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
(1) Specified by characterization. Not tested in production.
VOUT Regulated DC voltage accuracy TPS6128xA
2.65V VIN VOUT_TH - 150mV
IOUT = 0mA
PWM operation. -2.0 +2.0 %
2.65V VIN VOUT_TH - 150mV
IOUT = 0mA
PFM/PWM operation -2.0 +4.0 %
ΔVOUT
Power-save mode
output ripple voltage TPS6128xA PFM operation, IOUT = 1mA 30 mVpk
PWM mode output ripple voltage PWM operation, IOUT = 500mA 15 mVpk
POWER SWITCH
rDS(on)
Low-side switch MOSFET
on resistance
TPS6128xA
VIN = 3.2, VOUT = 3.5V 45 80 m
High-side rectifier MOSFET
on resistance VIN = 3.2V, VOUT = 3.5V 40 70 m
High-side pass-through MOSFET
on resistance VIN = 3.2V 35 60 m
Ilkg
Reverse leakage current into SW
TPS6128xA
EN = AGND, VIN = VOUT = SW = 3.5V
–40°C TJ85°C 0.1 2 µA
Reverse leakage current into
VOUT
EN = BYP = VIN, VIN = 2.9V, VOUT = 4.4V, VSW = 0V
device not switching
–40°C TJ85°C 0.11 2 µA
ISINK VOUT sink capability TPS6128xA EN = AGND, VOUT 3.6V,IOUT = -10mA 0.3 V
Valley inductor current limit TPS61280A
TPS61281A VIN = 2.9V, VOUT = 3.5V, –40°C TJ125°C, auto
PFM/PWM 2475 3000 3525 mA
Valley inductor current limit TPS61282A VIN = 2.9V, VOUT = 3.5V, –40°C TJ125°C, auto
PFM/PWM 3300 4000 4700 mA
Pass through mode current limit TPS6128xA EN = BYP = GND, VIN = 3.2V 5000 mA
EN = VIN, BYP = don't care , VIN = 3.2V 5600 7400 9100 mA
Pre-charge mode current limit
(linear mode, phase 1) TPS6128xA VIN - VOUT >= 300mV 500 650 mA
Pre-charge mode current limit
(linear mode, phase 2) 2000 mA
OSCILLATOR
fOSC Oscillator frequency TPS6128xA VIN = 2.7V, VOUT = 3.5 2.3 MHz
THERMAL SHUTDOWN, HOT DIE DETECTOR
Thermal shutdown(1) TPS6128xA 140 160 °C
Hot die detector accuracy(1) TPS61280A -10 105 +10 °C
TIMING
Start-up time TPS6128xA VIN = 3.2V, VOUT_TH = 01011 (3.4V), RLOAD = 50Ω
Time from active VIN to VOUT settled 500 µs
GPIO rise time(1) TPS61280A 200 ns
9
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(1) Specified by design. Not tested in production.
9.6 I2C Interface Timing Characteristics(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
f(SCL) SCL Clock Frequency
Standard mode 100 kHz
Fast mode 400 kHz
Fast mode plus 1 MHz
High-speed mode (write operation), CB 100 pF max 3.4 MHz
High-speed mode (read operation), CB 100 pF max 3.4 MHz
High-speed mode (write operation), CB 400 pF max 1.7 MHz
High-speed mode (read operation), CB 400 pF max 1.7 MHz
tBUF Bus Free Time Between a STOP and
START Condition
Standard mode 4.7 μs
Fast mode 1.3 μs
Fast mode plus 0.5 μs
tHD, tSTA Hold Time (Repeated) START
Condition
Standard mode 4 μs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tLOW LOW Period of the SCL Clock
Standard mode 4.7 μs
Fast mode 1.3 μs
Fast mode plus 0.5 μs
High-speed mode, CB 100 pF max 160 ns
High-speed mode, CB 400 pF max 320 ns
tHIGH HIGH Period of the SCL Clock
Standard mode 4 μs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode, CB 100 pF max 60 ns
High-speed mode, CB 400 pF max 120 ns
tSU, tSTA Setup Time for a Repeated START
Condition
Standard mode 4.7 μs
Fast mode 600 ns
Fast mode plus 260 ns
High-speed mode 160 ns
tSU, tDAT Data Setup Time
Standard mode 250 ns
Fast mode 100 ns
Fast mode plus 50 ns
High-speed mode 10 ns
tHD, tDAT Data Hold Time
Standard mode 0 3.45 μs
Fast mode 0 0.9 μs
Fast mode plus 0 μs
High-speed mode, CB 100 pF max 0 70 ns
High-speed mode, CB 400 pF max 0 150 ns
tRCL Rise Time of SCL Signal
Standard mode 1000 ns
Fast mode 20 + 0.1 CB300 ns
Fast mode plus 120 ns
High-speed mode, CB 100 pF max 10 40 ns
High-speed mode, CB 400 pF max 20 80 ns
tRCL1 Rise Time of SCL Signal After a Repeated
START Condition and After an
Acknowledge BIT
Standard mode 20 + 0.1 CB1000 ns
Fast mode 20 + 0.1 CB300 ns
Fast mode plus 120 ns
High-speed mode, CB 100 pF max 10 80 ns
High-speed mode, CB 400 pF max 20 160 ns
10
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,
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,
TPS61282A
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I2C Interface Timing Characteristics(1) (continued)
PARAMETER TEST CONDITIONS MIN MAX UNIT
tFCL Fall Time of SCL Signal
Standard mode 20 + 0.1 CB300 ns
Fast mode 300 ns
Fast mode plus 120 ns
High-speed mode, CB 100 pF max 10 40 ns
High-speed mode, CB 400 pF max 20 80 ns
tRDA Rise Time of SDA Signal
Standard mode 1000 ns
Fast mode 20 + 0.1 CB300 ns
Fast mode plus 120 ns
High-speed mode, CB 100 pF max 10 80 ns
High-speed mode, CB 400 pF max 20 160 ns
tFDA Fall Time of SDA Signal
Standard mode 300 ns
Fast mode 20 + 0.1 CB300 ns
Fast mode plus 120 ns
High-speed mode, CB 100 pF max 10 80 ns
High-speed mode, CB 400 pF max 20 160 ns
tSU, tSTO Setup Time of STOP Condition
Standard mode 4 μs
Fast mode 600 ns
Fast mode plus 260 ns
High-Speed mode 160 ns
CBCapacitive Load for SDA and SCL
Standard mode 400 pF
Fast mode 400 pF
Fast mode plus 550 pF
High-Speed mode 400 pF
Sr PSr
tfDA trDA
thd;DAT
tsu;STA thd;STA tsu;DAT tsu;STO
trCL1 tfCL
tHIGH tLOW tLOW tHIGH
trCL trCL1
= MCS Current Source Pull-Up
= R(P) Resistor Pull-Up
SDAH
SCLH
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
See Note ASee Note A
tftLOW tr
thd;STA
thd;DAT
tsu;DAT tf
HIGH
tsu;STA
S Sr P S
thd;STA tr
tBUF
tsu;STO
SDA
SCL
11
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9.7 I2C Timing Diagrams
Figure 1. Serial Interface Timing Diagram for Standard-, Fast-, Fast-Mode Plus
Figure 2. Serial Interface Timing Diagram for H/S-Mode
C005
15
17
19
21
23
25
27
29
31
33
35
3.5 4.5
Quiescent Current_Auto Bypass (µA)
Input Voltage (V)
Tj=25C
Tj=-40
Tj = 85 C
C006
TJ = 30°C
TJ = -40°C
TJ = 85°C
C003
C004
C001
C002
12
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9.8 Typical Characteristics
VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C
Figure 3. High side Rds(on) vs Junction Temperature
VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C
Figure 4. Low side Rds(on) vs Junction Temperature
VIN = 3.2 V Bypass TJ= –40 to 125°C
Figure 5. Bypass FET Rds(on) vs Junction Temperature
VIN = 2.3 - 3.4 V VOUT = 3.4 V IOUT = 0 mA
EN = High Bypass = High
Figure 6. Quiescent Current at Boost Mode vs Input Voltage
VIN = 3.5 - 4.4 V VOUT = 3.4 V IOUT = 0 mA
EN = High Bypass = Low
Figure 7. Quiescent Current at Forced Bypass Mode vs
Input Voltage
VIN = 3.6 - 4.4 V VOUT = 3.4 V IOUT = 0 mA
EN = High Bypass = High
Figure 8. Quiescent Current at Auto Bypass Mode vs Input
Voltage
0.50
0.60
0.70
0.80
0.90
1.00
1.10
-40 -20 0 20 40 60 80 100 120
EN Logic Threshold (V)
Junction Temperature (ƒC)
EN Rising
EN Falling
C011
0.50
0.60
0.70
0.80
0.90
1.00
1.10
-40 -20 0 20 40 60 80 100 120
EN Logic Threshold (V)
Junction Temperature (ƒC)
nBYP Rising
nBYP Falling
C012
Switch Valley Current Limit (A)
Temperature (ƒC)
TPS61281A
TPS61282A
C009
1.80
2.00
2.20
-40 -20 0 20 40 60 80 100 120
Vin UVLO Threshold (V)
Junction Temperature (ƒC)
Vin Rising
Vin Falling
C010
VIN Rising
VIN Falling
0
1
2
3
4
5
2.3 3.3 4.3
Leakage Current_Low IqA)
Input Voltage (V)
Tj=25C
Tj=-40
Tj = 85 C
C007
TJ = 30°C
TJ = -40°C
TJ = 85°C
3
4
5
6
7
8
9
10
11
12
13
2.3 3.3 4.3
Leakage Current_Low IqA)
Input Voltage (V)
Tj = 25C
Tj = -40
Tj = 85 C
C008
TJ = 30°C
TJ = -40°C
TJ = 85°C
13
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Typical Characteristics (continued)
VIN = 2.3 - 4.4 V VOUT = 4.4 V VSW = 0 V
EN = Low Bypass = Low
Figure 9. Shutdown Current at Low IQmode vs Input
Voltage
VIN = 2.3 - 4.4 V VOUT = 4.4 V VSW = 0 V
EN = Low Bypass = High
Figure 10. Shutdown Current vs Input Voltage
VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C
EN = High Bypass = High
Figure 11. Switch Valley Current Limit: TPS61281A,
TPS61282A vs Input Voltage
VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C
Figure 12. VIN UVLO Threshold Rising/Falling vs Junction
Temperature
VIN = 3.2 V VOUT = 3.5 V TJ= –40 to 125°C
Figure 13. EN Logic High Threshold Rising/Falling vs
Junction Temperature
VIN = 3.2 V TJ= –40 to 125°C
Figure 14. BYP Logic High Threshold Rising/Falling vs
Junction Temperature
14
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10 Detailed Description
10.1 Overview
The TPS6128xA is a high-efficiency step-up converter featuring pass-through mode optimized to provide low-
noise voltage supply for 2G RF power amplifiers (PAs) in mobile phones and/or to pre-regulate voltage for
supplying subsystem like eMMC memory, audio codec, LCD bias, antenna switches, RF engine PMIC and so on.
It is designed to allow the system to operate at maximum efficiency for a wide range of power consumption levels
from a low-, wide- voltage battery cell.
The capability of the TPS6128xA to step-up the voltage as well as to pass-through the input battery voltage when
its level is high enough allow systems to operate at maximum performance over a wide range of battery voltages,
thereby extending the battery life between charging. The device also addresses brownouts caused by the peak
currents drawn by the APU and GPU which can cause the battery rail to droop momentarily. Using the
TPS6128xA device as a pre-regulator eliminates system brownout condition while maintaining a stable supply rail
for critical sub-system to function properly.
The TPS6128xA synchronous step-up converter typically operates at a quasi-constant 2.3-MHz frequency pulse
width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS6128xA converter
operates in power-save mode with pulse frequency modulation (PFM).
In general, a dc/dc step-up converter can only operate in "true" boost mode, that is the output “boosted” by a
certain amount above the input voltage. The TPS6128xA device operates differently as it can smoothly transition
in and out of zero duty cycle operation. Depending upon the input voltage, output voltage threshold and load
current, the integrated bypass switch automatically transitions the converter into pass-through mode to maintain
low-dropout and high-efficiency. The device exits pass-through mode (0% duty cycle operation) if the total
dropout resistance in bypass mode is insufficient to maintain the output voltage at it's nominal level. Refer to the
typical characteristics section (DC Output Voltage vs. Input Voltage) for further details.
During PWM operation, the converter uses a novel quasi-constant on-time valley current mode control scheme to
achieve excellent line/load regulation and allows the use of a small ceramic inductor and capacitors. Based on
the VIN/VOUT ratio, a simple circuit predicts the required on-time. At the beginning of the switching cycle, the low-
side N-MOS switch is turned-on and the inductor current ramps up to a peak current that is defined by the on-
time and the inductance. In the second phase, once the on-timer has expired, the rectifier is turned-on and the
inductor current decays to a preset valley current threshold. Finally, the switching cycle repeats by setting the on
timer again and activating the low-side N-MOS switch.
The current mode architecture provides excellent transient load response, requiring minimal output filtering.
Internal soft-start and loop compensation simplifies the design process while minimizing the number of external
components.
The TPS6128xA directly and accurately controls the average input current through intelligent adjustment of the
valley current limit, allowing an accuracy of ±17.5%. Together with an external bulk capacitor, the TPS6128xA
allows an application to be interfaced directly to its load, without overloading the input source due to appropriate
set average input current limit. An open-drain output (PG or GPIO/nFAULT) provides a signal to issue an
interrupt to the system if any fault is detected on the device (thermal shutdown, output voltage out-of limits, and
so on).
The output voltage can be dynamically adjusted between two values (floor and roof voltages) by toggling a logic
control input (VSEL) without the need for external feedback resistors. This features can either be used to raise
the output voltage in anticipation of a positive load transient or to dynamically change the PA supply voltage
depending on its mode of operation and/or transmitting power.
The TPS61280A integrates an I2C compatible interface allowing transfers up to 3.4Mbps. This communication
interface can be used to set the output voltage threshold at which the converter transitions between boost and
pass-through mode, for reprogramming the mode of operation (PFM/PWM or forced PWM), for settings the
average input current limit or resetting the output voltage for instance.
Configuration parameters can be changed by writing the desired values to the appropriate I2C register(s). The
I2C registers are volatile and their contents are lost when power is removed from the device. By writing to the
E2PROMCTRL Register, it is possible to store the active configuration in non-volatile E2PROM; during power-up,
the contents of the E2PROM are copied into the I2C registers and used to configure the device.