MCM54100A•MCM5L4100A
1
MOTOROLA DRAM
Advance Information
4M x 1 CMOS Dynamic RAM
Fast Page Mode
The MCM54100A is a 0.7µ CMOS high–speed dynamic random access memory.
It is organized as 4,194,304 one–bit words and fabricated with CMOS silicon–gate
process technology. Advanced circuit design and fine line processing provide high
performance, improved reliability, and low cost.
The MCM54100A requires only 11 address lines; row and column address inputs
are multiplexed. The device is packaged in a standard 300 mil J lead small outline
package and a 300 mil thin small outline package (TSOP).
•Three–State Data Output
•Fast Page Mode
•Test Mode
•TTL–Compatible Inputs and Outputs
•RAS–Only Refresh
•CAS Before RAS Refresh
•Hidden Refresh
•1024 Cycle Refresh: MCM54100A = 16 ms
•Fast Access Time (tRAC):
MCM54100A–60 and MCM5L4100A–60 = 60 ns (Max)
MCM54100A–70 and MCM5L4100A–70 = 70 ns (Max)
MCM54100A–80 and MCM5L4100A–80 = 80 ns (Max)
•Low Active Power:
MCM54100A–60 and MCM5L4100A–60 = 660 mW (Max)
MCM54100A–70 and MCM5L4100A–70 = 550 mW (Max)
MCM54100A–80 and MCM5L4100A–80 = 468 mW (Max)
•Low Standby Power Dissipation:
MCM54100A and MCM5L400A = 11 mW (Max, TTL Levels)
MCM54100A = 5.5 mW (Max, CMOS Levels)
MCM5L4100A = 1.1 mW (Max, CMOS Levels)
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Order this document
by MCM54100A/D
MOTOROLA
SEMICONDUCTOR
TECHNICAL DATA MCM54100A
MCM5L4100A
N PACKAGE
300 MIL SOJ
CASE 822–03
T PACKAGE
300 MIL TSOP
CASE 892–01
PIN ASSIGNMENT
5
4
3
2
1
14
15
16
17
18
13
12
11
10
9
22
23
24
25
26
A10
NC
RAS
W
D
VCC
A3
A2
A1
A0
A9
NC
CAS
Q
VSS
A4
A5
A6
A7
A8
PIN NAMES
A0 – A10 Address Input. . . . . . . . . . . . . .
D Data Input. . . . . . . . . . . . . . . . . . . . . . . .
Q Data Output. . . . . . . . . . . . . . . . . . . . .
WRead/Write Enable. . . . . . . . . . . . . . .
RAS Row Address Strobe. . . . . . . . . . . .
CAS Column Address Strobe. . . . . . . . .
VCC Power Supply (+ 5 V). . . . . . . . . . .
VSS Ground. . . . . . . . . . . . . . . . . . . . . . .
NC No Connection. . . . . . . . . . . . . . . . . .
REV 4
10/95
Motorola, Inc. 1995
MCM54100A•MCM5L4100A
2MOTOROLA DRAM
BLOCK DIAGRAM
RAS
CAS
W
VSS
VCC
1024
4096
Q
D
A9
A10
A8
A7
A6
A5
A4
A3
A2
A1
A0
ROW
ADDRESS
BUFFERS (11)
DATA OUT
BUFFER
COLUMN
DECODER
SENS AMP
I/O GATING
MEMORY
ARRAY
SUBSTRATE BIAS
GENERATOR
#2 CLOCK
GENERATOR
#1 CLOCK
GENERATOR
DATA IN
BUFFER
COLUMN
ADDRESS
BUFFERS (11)
ROW
DECODER
REFRESH
COUNTER (10)
REFRESH
CONTROLLER
ABSOLUTE MAXIMUM RATINGS (See Note)
Rating Symbol Value Unit
Power Supply Voltage VCC – 1 to + 7 V
Voltage Relative to VSS for Any Pin
Except VCC Vin, Vout – 1 to + 7 V
Data Output Current Iout 50 mA
Power Dissipation PD700 mW
Operating Temperature Range TA0 to + 70 °C
Storage Temperature Range Tstg – 55 to + 150 °C
NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMENDED OPER-
ATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
This device contains circuitry to protect the
inputs against damage due to high static
voltages or electric fields; however, it is ad-
vised that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to these high–impedance
circuits.
MCM54100A•MCM5L4100A
3
MOTOROLA DRAM
DC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)
RECOMMENDED OPERATING CONDITIONS (All voltages referenced to VSS)
Parameter Symbol Min Typ Max Unit
Supply Voltage (Operating Voltage Range) VCC 4.5 5.0 5.5 V
VSS 0 0 0
Logic High Voltage, All Inputs VIH 2.4 — 6.5 V
Logic Low Voltage, All Inputs VIL – 1.0 — 0.8 V
DC CHARACTERISTICS
Characteristic Symbol Min Max Unit Notes
VCC Power Supply Current MCM54100A–60 and MCM5L4100A–60, tRC = 110 ns
MCM54100A–70 and MCM5L4100A–70, tRC = 130 ns
MCM54100A–80 and MCM5L4100A–80, tRC = 150 ns
ICC1 —
—
—
120
100
85
mA 1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 — 2.0 mA
VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VIH)
MCM54100A–60 and MCM5L4100A–60, tRC = 110 ns
MCM54100A–70 and MCM5L4100A–70, tRC = 130 ns
MCM54100A–80 and MCM5L4100A–80, tRC = 150 ns
ICC3 —
—
—
120
100
85
mA 1, 2
VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL)
MCM54100A–60 and MCM5L4100A–60, tPC = 45 ns
MCM54100A–70 and MCM5L4100A–70, tPC = 45 ns
MCM54100A–80 and MCM5L4100A–80, tPC = 50 ns
ICC4 —
—
—
70
70
60
mA 1, 2
VCC Power Supply Current (Standby) (RAS = CAS = VCC – 0.2 V) MCM54100A
MCM5L4100A
ICC5 —
—1.0
200 mA
µA
VCC Power Supply Current During CAS Before RAS Refresh Cycle
MCM54100A–60 and MCM5L4100A–60, tRC = 110 ns
MCM54100A–70 and MCM5L4100A–70, tRC = 130 ns
MCM54100A–80 and MCM5L4100A–80, tRC = 150 ns
ICC6 —
—
—
120
100
85
mA 1
VCC Power Supply Current, Battery Backup Mode — MCM5L4100A Only
(tRC = 125 µs; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC – 0.2 V;
Din = VCC – 0.2 V or 0.2 V or OPEN; A0 – A10 = VCC – 0.2 V or 0.2 V)
tRAS = 300 ns to 1 µs
tRAS = Min to 300 ns
ICC7
—
—400
300
µA 1, 3
Input Leakage Current (0 V ≤ Vin ≤ 6.5 V) Ilkg(I) – 10 10 µA
Output Leakage Current (CAS = VIH, 0 V ≤ Vout ≤ 5.5 V) Ilkg(O) – 10 10 µA
Output High Voltage (IOH = – 5 mA) VOH 2.4 — V
Output Low Voltage (IOL = 4.2 mA) VOL — 0.4 V
NOTES:
1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open.
2. Column address can be changed once or less while RAS = VIL and CAS = VIH.
3. tRAS (max) = 1 µs is only applied to refresh of battery–back up. tRAS (max) = 10 µs is applied to functional operating
CAPACITANCE (f = 1.0 MHz, TA = 25°C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested)
Characteristic Symbol Max Unit
Input Capacitance A0 – A10, D Cin 5 pF
RAS, CAS, W 7
I/O Capacitance (CAS = VIH to Disable Output) Q Cout 7 pF
NOTE:Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I ∆t/∆V.
MCM54100A•MCM5L4100A
4MOTOROLA DRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol MCM54100A–60
MCM5L4100A–60 MCM54100A–70
MCM5L4100A–70 MCM54100A–80
MCM5L4100A–80
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Random Read or Write Cycle Time tRELREL tRC 110 — 130 — 150 — ns 5
Read–Write Cycle Time tRELREL tRWC 140 — 155 — 175 — ns 5
Fast Page Mode Cycle Time tCELCEL tPC 45 — 45 — 50 — ns
Fast Page Mode Read–Write Cycle
Time tCELCEL tPRWC 65 — 70 — 75 — ns
Access Time from RAS tRELQV tRAC — 60 — 70 — 80 ns 6, 7
Access Time from CAS tCELQV tCAC — 20 — 20 — 20 ns 6, 8
Access Time from Column Address tAVQV tAA — 30 — 35 — 40 ns 6, 9
Access Time from Precharge CAS tCEHQV tCPA — 40 — 40 — 45 ns 6
CAS to Output in Low–Z tCELQX tCLZ 0 — 0 — 0 — ns 6
Output Buffer and Turn–Off Delay tCEHQZ tOFF 0 20 0 20 0 20 ns 10
Transition Time (Rise and Fall) tTtT3 50 3 50 3 50 ns
RAS Precharge Time tREHREL tRP 45 — 50 — 60 — ns
RAS Pulse Width tRELREH tRAS 60 10 k 70 10 k 80 10 k ns
RAS Pulse Width (Fast Page
Mode) tRELREH tRASP 60 200 k 70 200 k 80 200 k ns
RAS Hold Time tCELREH tRSH 20 — 20 — 20 — ns
CAS Hold Time tRELCEH tCSH 60 — 70 — 80 — ns
CAS Precharge to RAS Hold Time tCEHREH tRHCP 40 — 40 — 45 — ns
CAS Pulse Width tCELCEH tCAS 20 10 k 20 10 k 20 10 k ns
RAS to CAS Delay Time tRELCEL tRCD 20 40 20 50 20 60 ns 11
RAS to Column Address Delay
Time tRELAV tRAD 15 30 15 35 15 40 ns 12
CAS to RAS Precharge Time tCEHREL tCRP 5 — 5 — 5 — ns
CAS Precharge Time tCEHCEL tCP 10 — 10 — 10 — ns
Row Address Setup Time tAVREL tASR 0 — 0 — 0 — ns
Row Address Hold Time tRELAX tRAH 10 — 10 — 10 — ns
NOTES: (continued)
11. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. T ransition times are measured between VIH and VIL.
12.An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
13.The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
14.AC measurements tT = 5.0 ns.
15.The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (0°C ≤ TA ≤ 70°C)
is ensured.
16.Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
17.Assumes that tRCD ≤ tRCD (max).
18.Assumes that tRCD ≥ tRCD (max).
19.Assumes that tRAD ≥ tRAD (max).
10.tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels.
11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD
is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC.
12.Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD
is greater than the specified tRAD (max), then access time is controlled exclusively by tAA.
MCM54100A•MCM5L4100A
5
MOTOROLA DRAM
READ, WRITE, AND READ–WRITE CYCLES (Continued)
Symbol MCM54100A–60
MCM5L4100A–60 MCM54100A–70
MCM5L4100A–70 MCM54100A–80
MCM5L4100A–80
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Column Address Setup Time tAVCEL tASC 0 — 0 — 0 — ns
Column Address Hold Time tCELAX tCAH 15 — 15 — 15 — ns
Column Address to RAS Lead Time tAVREH tRAL 30 — 35 — 40 — ns
Read Command Setup Time tWHCEL tRCS 0 — 0 — 0 — ns
Read Command Hold Time
Referenced to CAS tCEHWX tRCH 0 — 0 — 0 — ns 13
Read Command Hold Time
Referenced to RAS tREHWX tRRH 0 — 0 — 0 — ns 13
Write Command Hold Time
Referenced to CAS tCELWH tWCH 10 — 15 — 15 — ns
Write Command Pulse Width tWLWH tWP 10 — 15 — 15 — ns
Write Command to RAS Lead Time tWLREH tRWL 20 — 20 — 20 — ns
Write Command to CAS Lead Time tWLCEH tCWL 20 — 20 — 20 — ns
Data in Setup Time tDVCEL tDS 0 — 0 — 0 — ns 14
Data in Hold Time tCELDX tDH 15 — 15 — 15 — ns 14
Refresh Period MCM54100A
MCM5L4100A tRVRV tRFSH —
—16
128 —
—16
128 —
—16
128 ms
Write Command Setup Time tWLCEL tWCS 0 — 0 — 0 — ns 15
CAS to Write Delay tCELWL tCWD 20 — 20 — 20 — ns 15
RAS to Write Delay tRELWL tRWD 60 — 70 — 80 — ns 15
Column Address to Write Delay
Time tAVWL tAWD 30 — 35 — 40 — ns 15
CAS Precharge to Write Delay Time
(Page Mode) tCEHWL tCPWD 40 — 40 — 40 — ns 15
CAS Setup Time for CAS Before
RAS Refresh tRELCEL tCSR 5 — 5 — 5 — ns
CAS Hold Time for CAS Before
RAS Refresh tRELCEH tCHR 15 — 15 — 15 — ns
RAS Precharge to CAS Active Time tREHCEL tRPC 0 — 0 — 0 — ns
CAS Precharge Time for CAS
Before RAS Counter Time tCEHCEL tCPT 30 — 40 — 40 — ns
Write Command Setup Time (Test
Mode) tWLREL tWTS 10 — 10 — 10 — ns
Write Command Hold Time (Test
Mode) tRELWH tWTH 10 — 10 — 10 — ns
Write to RAS Precharge Time (CAS
Before RAS Refresh) tWHREL tWRP 10 — 10 — 10 — ns
Write to RAS Hold Time (CAS
Before RAS Refresh) tRELWL tWRH 10 — 10 — 10 — ns
NOTES:
13.Either tRRH or tRCH must be satisfied for a read cycle.
14.These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in read–write cycles.
15.tWCS, tRWD, tCWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical
characteristics only; if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high
impedance) throughout the entire cycle; if tCWD ≥ tCWD (min), tRWD ≥ tRWD (min), tAWD ≥ tAWD (min), and tCPWD ≥ tCPWD (min)
(page mode), the cycle is a read–write cycle and the data out will contain data read from the selected cell. If neither of these sets of
conditions is satisfied, the condition of the data out (at access time) is indeterminate.
MCM54100A•MCM5L4100A
6MOTOROLA DRAM
READ CYCLE
HIGH–Z
tCSH
VALID DATA
D (DATA OUT)
RCS
tRCH
t
RRH
t
OFF
t
CAC
t
AA
t
CLZ
t
RAC
t
tCAS
W
CAS
RAS
ADDRESSES
RAL
t
RAH
t
CAH
t
ASR
tRAD
t
ASC
t
CRP
t
CP
t
CRP
tRCD
tRSH
t
RP
t
ROW
ADDRESS COLUMN
ADDRESS
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
tRC
tRAS
EARLY WRITE CYCLE
WCS
tWCH
t
CWL
t
RWL
t
DH
t
tCAS
RAL
t
DS
t
WP
t
RAH
t
CAH
t
ASR
tRAD
t
ASC
t
CSH
tCRP
t
CP
t
CRP
tRCD
tRSH
t
RP
t
RAS
tRC
t
HIGH–Z
VALID DATA
D (DATA OUT)
COLUMN
ADDRESS
ROW
ADDRESS
D (DATA IN)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
MCM54100A•MCM5L4100A
7
MOTOROLA DRAM
READ–WRITE CYCLE
HIGH–Z
VALID DATA
VALID DATA
CLZ
t
RAL
t
RAC
tOFF
t
AA
tCAC
t
DH
t
DS
t
RCS
t
WP
t
CWD
t
RWD
tAWD
t
RAH
t
CAH
t
ASR
tASC
t
RAD
tCWL
t
CSH
t
CRP
t
CP
t
RWL
t
CAS
t
CRP
tRCD
tRSH
t
RP
t
RAS
tRWC
t
ROW
ADDRESS COLUMN
ADDRESS
D (DATA OUT)
D (DATA IN)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
FAST PAGE MODE READ CYCLE
CPA
tCPA
t
CP
t
CAH
tCAH
t
RCH
t
RCH
tRRH
t
CLZ
tCLZ
t
OFF
tOFF
t
CAC
tCAC
t
AA
tAA
t
RCS
t
RCS
t
ASC
t
ASC
t
CP
t
CAS
t
CAS
t
RAL
t
RAC
t
OFF
t
AA
t
CAC
t
PC
t
RCS
t
CRP
t
RAH
tRCH
t
CAH
t
ASR
tASC
t
RAD
t
CSH
t
CP
t
CLZ
t
CAS
tRSH
t
RCD
t
RASP
tRP
t
RHCP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
VALID
DATA VALID
DATA VALID
DATA
D (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
MCM54100A•MCM5L4100A
8MOTOROLA DRAM
FAST PAGE MODE EARLY WRITE CYCLE
HIGH–Z
VALID DATA
VALID DATA
VALID DATA
CAH
t
WCS
t
WCS
tWCS
t
WCH
tWCH
t
WCH
t
WP
t
WP
t
WP
t
DS
tt
DS
tt DH
t
DH
t
DS
tt DH
t
RAH
t
CP
t
CAH
t
ASC
t
ASC
t
CP
t
CAS
t
CAS
t
RAL
t
PC
t
CRP
t
CAH
t
ASR
t
ASC
t
RAD
t
CP
t
CAS
tRSH
t
RCD
t
RASP
tRP
t
RHCP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
D (DATA OUT)
D (DATA IN)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
FAST PAGE MODE READ–WRITE CYCLE
CWD
t
CP
tCP
t
CP
tPRWC
t
CSH
t
CWL
t
CWL
tRWL
t
CWD
t
CPWD
t
AWD
tAWD
t
DH
tDH
t
DS
tDS
t
WP
tWP
t
CPA
t
AA
tAA
t
CAC
tCAC
t
CLZ
tCLZ
t
OFF
t
OFF
tOFF
t
CPA
t
CLZ
t
RAC
tAA
t
CAC
t
CPWD
t
WP
t
DH
t
DS
t
RWD
t
CWL
t
CWD
t
AWD
t
RCS
t
ASC
t
CAH
t
CAH
tASC
t
CAS
t
CAS
t
RAH
t
RAL
t
CRP
t
CAH
t
ASR
tASC
t
RAD
t
CAS
t
RSH
t
RCD
t
RASP
tRP
t
COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
ROW
ADDRESS
VALID
DATA VALID
DATA VALID
DATA
VALID
DATA VALID
DATA VALID
DATA
D (DATA OUT)
D (DATA IN)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
MCM54100A•MCM5L4100A
9
MOTOROLA DRAM
RAS ONLY REFRESH CYCLE
(W and A10 are Don’t Care)
RPC
t
RAH
t
ASR
t
CRP
t
RP
t
RAS
t
RC
t
HIGH–Z
ROW
ADDRESS
CAS
RAS
A0 TO A9
VIH
VIL
VIH
VIL
VIH
VIL
D (DATA OUT) VOH
VOL
CAS BEFORE RAS REFRESH CYCLE
(A0 – A10 are Don’t Care)
HIGH–Z
WRH
t
OFF
t
CHR
t
WRP
t
CP
t
CSR
t
RPC
t
RP
t
RAS
t
RC
t
CAS
RAS
W
VIH
VIL
VIH
VIL
VIH
VIL
D (DATA OUT) VOH
VOL
MCM54100A•MCM5L4100A
10 MOTOROLA DRAM
HIDDEN REFRESH CYCLE (READ)
CHR
t
WRP
tWRH
t
RAS
t
VALID DATA
RCS
tRRH
t
OFF
t
CAC
t
AA
t
CLZ
t
RAC
t
RAL
t
CAH
t
RAD
t
ASC
t
CP
t
CRP
tRCD
tRSH
t
RP
tRAS
t
RC
t
RAH
t
ASR
t
ROW
ADDRESS COLUMN
ADDRESS
D (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
HIDDEN REFRESH CYCLE (EARLY WRITE)
HIGH–Z
DH
t
DS
tWP
t
WRP
tWRH
t
WCS
tWCH
t
RWL
t
VALID DATA
COLUMN
ADDRESS
RAL
t
CAH
t
RAD
tASC
t
RAH
t
ASR
t
CHR
t
RAS
t
CP
t
CRP
tRCD
tRSH
t
RP
tRAS
t
RC
t
ROW
ADDRESS
D (DATA OUT)
D (DATA IN)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VIH
VIL
MCM54100A•MCM5L4100A
11
MOTOROLA DRAM
CAS BEFORE RAS REFRESH COUNTER TEST CYCLE
WCH
t
CSR
t
WRP
tWRH
tCWL
t
RWL
t
AWD
t
DH
t
DS
t
WP
t
CAC
t
OFF
t
CLZ
t
AA
t
CWL
t
CWD
t
RCS
t
WRP
tWRH
t
DH
t
DS
t
WP
t
WCS
t
RWL
t
RCH
t
RCS
tCLZ
t
CPT
t
CAH
t
ASC
t
RAL
t
RRH
t
CAS
t
RSH
t
WRP
tWRH
t
CHR
t
RAS
t
OFF
t
CAC
t
AA
t
RP
t
HIGH–Z
HIGH–Z
COLUMN ADDRESS
VALID DATA
VALID DATA
VALID DATA
VALID DATA
READ–WRITE CYCLE
EARLY WRITE CYCLE
READ CYCLE
HIGH–Z
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
Q (DATA OUT)
WVIH
VIL
VOH
VOL
Q (DATA OUT)
WVIH
VIL
VOH
VOL
D (DATA IN) VIH
VIL
Q (DATA OUT)
WVIH
VIL
VOH
VOL
D (DATA IN) VIH
VIL
MCM54100A•MCM5L4100A
12 MOTOROLA DRAM
DEVICE INITIALIZATION
On power–up, an initial pause of 200 microseconds is
required for the internal substrate generator to establish the
correct bias voltage. This must be followed by a minimum of
eight active cycles of the row address strobe (clock) to ini-
tialize all dynamic nodes within the RAM. During an extended
inactive state (greater than 16 milliseconds or 128 millisec-
onds in case of low power device, with the device powered
up), a wakeup sequence of eight active cycles is necessary to
ensure proper operation.
ADDRESSING THE RAM
The eleven address pins on the device are time multiplexed
at the beginning of a memory cycle by two clocks, row address
strobe (RAS) and column address strobe (CAS), into two
separate 11–bit address fields. A total of twenty–two address
bits, eleven rows and eleven columns, will decode one of the
4,194,304 bit locations in the device. RAS active transition is
followed by C AS active transition (active = V IL, tRCD mini-
mum) for all read or write cycles. The delay between RAS and
CAS active transitions, referred to as the multiplex window,
gives a system designer flexibility in setting up the external
addresses into the RAM.
The external CAS signal is ignored until an internal RAS sig-
nal is available. This “gate” feature on the external CAS clock
enables the internal CAS line as soon as the row address hold
time (tRAH) specification is met (and defines tRCD minimum).
The multiplex window can be used to absorb skew delays in
switching the address bus from row to column addresses and
in generating the CAS clock.
There are three other variations in addressing the 4M RAM:
RAS only refresh cycle, CAS before RAS refresh cycle,
and page mode.
READ CYCLE
The DRAM may be read with four different cycles: “normal”
random read cycle, page mode read cycle, read–write cycle,
and page mode read–write cycle. The normal read cycle is
outlined here, while the other cycles are discussed in separate
sections.
The normal read cycle begins as described in ADDRESS-
ING THE RAM, with RAS and CAS active transitions latching
the desired bit location. The write (W) input level must be high
(VIH), tRCS (minimum) before the C AS active transition, to
enable read mode.
Both the RAS and CAS clocks trigger a sequence of events
that are controlled by several delayed internal clocks. The
internal clocks are linked in such a manner that the read
access time of the device is independent of the address
multiplex window; however, CAS must be active before or at
tRCD maximum to guarantee valid data out (Q) at tRAC
(access time from RAS active transition). If the tRCD
maximum is exceeded, read access time is determined by the
CAS clock active transition (tCAC).
The RAS and C AS clocks must remain active for a mini–
mum time of tRAS and tCAS, respectively, to complete
the read cycle. W must remain high throughout the cycle, and
for time tRRH or tRCH after RAS or CAS inactive transition,
respectively, to maintain the data at that bit location. Once
RAS transitions to inactive, it must remain inactive for a mini-
mum time of tRP to precharge the internal device circuitry for
the next active cycle. Q is valid, but not latched, as long as the
CAS clock is active. When the CAS clock transitions to inac-
tive, the output will switch to High–Z (three–state).
WRITE CYCLE
The user can write to the DRAM with any of four cycles:
early write, late write, page mode early write, and page mode
read–write. Early and late write modes are discussed here,
while page mode write operations are covered elsewhere.
A write cycle begins as described in ADDRESSING THE
RAM. Write mode is enabled by the transition of W to active
(VIL). Early and late write modes are distinguished by the
active transition of W, with respect to CAS. Minimum active
time tRAS and tCAS, and precharge time tRP apply to write
mode, as in the read mode.
An early write cycle is characterized by W active transition
at minimum time tWCS before CAS active transition. Data in
(D) is referenced to CAS in an early write cycle. RAS and CAS
clocks must stay active for tRWL and tCWL, respectively,
after the start of the early write operation to complete the
cycle.
Q remains in three–state condition throughout an early write
cycle because W active transition precedes or coincides with
CAS active transition, keeping data–out buffers disabled. This
feature can be utilized on systems with a common I/O bus,
provided all writes are performed with early write cycles, to
prevent bus contention.
A late write cycle occurs when W active transition is made
after CAS active transition. W active transition could be
delayed for almost 10 microseconds after CAS active transi-
tion, (tRCD + tCWD + tRWL + 2tT) ≤ tRAS, if other timing
minimums (tRCD, tRWL, and tT) are maintained. D is
referenced to W active transition in a late write cycle. Output
buffers are enabled by CAS active transition but Q may be
indeterminate; see note 15 of AC Operating Conditions table.
RAS and CAS must remain active for tRWL and tCWL,
respectively, after W active transition to complete the write
cycle.
READ–WRITE CYCLE
A read–write cycle performs a read and then a write at the
same address, during the same cycle. This cycle is basically
a late write cycle, as discussed in the WRITE CYCLE section,
except W must remain high for tCWD minimum after the CAS
active transition, to guarantee valid Q before writing the bit.
PAGE MODE CYCLES
Page mode allows fast successive data operations at all
2048 column locations on a selected row of the 4M dynamic
RAM. Read access time in page mode (tCAC) is typically half
the regular RAS clock access time, tRAC. Page mode oper-
ation consists of keeping RAS active while toggling CAS
between VIH and VIL. The row is latched by RAS active transi-
tion, while each CAS active transition allows selection of a new
column location on the row.
A page mode cycle is initiated by a normal read, write, or
read–write cycle, as described in prior sections. Once the tim-
ing requirements for the first cycle are met, CAS transitions to
inactive for minimum of tCP, while RAS remains low ( VIL).
The second CAS active transition while RAS is low initiates the
first page mode cycle (tPC or tPRWC). Either a read, write, or
read–write operation can be performed in a page mode cycle,
subject to the same conditions as in normal operation
(previously described). These operations can be intermixed
MCM54100A•MCM5L4100A
13
MOTOROLA DRAM
in consecutive page mode cycles and performed in any order .
The maximum number of consecutive page mode cycles is
limited by tRASP. Page mode operation is ended when RAS
transitions to inactive, coincident with or following CAS
inactive transition.
REFRESH CYCLES
The dynamic RAM design is based on capacitor charge
storage for each bit in the array. This charge will tend to
degrade with time and temperature. Each bit must be peri-
odically refreshed (recharged) to maintain the correct bit
state. Bits in the MCM54100A require refresh every
16 milliseconds, while refresh time for the MCM5L4100A is
128 milliseconds.
This is accomplished by cycling through the 1024 row
addresses in sequence within the specified refresh time. All
the bits on a row are refreshed simultaneously when the row
is addressed. Distributed refresh implies a row refresh every
15.6 microseconds for the MCM54100A, and 124.8 micro-
seconds for the MCM5L4100A. Burst refresh, a refresh of all
1024 rows consecutively, must be performed every 16 milli-
seconds on the MCM54100A and 128 milliseconds on the
MCM5L4100A.
A normal read, write, or read–write operation to the RAM will
refresh all the bits (4096) associated with the particular row
decoded. Three other methods of refresh, RAS–only refresh,
CAS before RAS refresh, and hidden refresh are available
on this device for greater system flexibility.
RAS–Only Refresh
RAS–only refresh consists of RAS transition to active, latch-
ing the row address to be refreshed, while CAS remains high
(VIH) throughout the cycle. An external counter is employed to
ensure that all rows are refreshed within the specified limit.
CAS Before RAS Refresh
CAS before RAS refresh is enabled by bringing CAS active
before RAS. This clock order activates an internal refresh
counter that generates the row address to be refreshed. Exter-
nal address lines are ignored during the automatic refresh
cycle. The output buffer remains at the same state it was in
during the previous cycle (hidden refresh). W must be inactive
for time tWRP before and time tWRH after RAS active transi–
tion to prevent switching the device into test mode.
Hidden Refresh
Hidden refresh allows refresh cycles to occur while main-
taining valid data at the output pin. Holding CAS active at the
end of a read or write cycle, while RAS cycles inactive for tRP
and back to active, starts the hidden refresh. This is essentially
the execution of a CAS before RAS refresh from a cycle in
progress (see Figure 1). W is subject to the same conditions
with respect to RAS active transition (to prevent test mode
entry) as in CAS before RAS refresh.
CAS BEFORE RAS REFRESH COUNTER TEST
The internal refresh counter of this device can be tested with
a CAS before RAS refresh counter test. This test is per-
formed with a read–write operation. During the test, the inter-
nal refresh counter generates the row address, while the
external address supplies the column address. The entire
array is refreshed after 1024 cycles, as indicated by the check
data written in each row. See CAS before RAS refresh
counter test cycle timing diagram.
The test can be performed after a minimum of 8 CAS before
RAS initialization cycles. Test procedure:
1. Write 0s into all memory cells with normal write mode.
2. Select a column address, read 0 out and write 1 into the
cell by performing the CAS before RAS refresh count-
er test, read–write cycle. Repeat this operation 1024
times.
3. Read the 1s which were written in step two in normal
read mode.
4. Using the same starting column address as in step two,
read 1 out and write 0 into the cell by performing the CAS
before RAS refresh counter test, read–write cycle.
Repeat this operation 1024 times.
5. Read 0s which were written in step four in normal read
mode.
6. Repeat steps one through five using complement data.
RAS
CAS
VALID DATA–OUT
HIGH–Z
Q
CAS BEFORE RAS
REFRESH CYCLE
CAS BEFORE RAS
REFRESH CYCLE
MEMORY CYCLE
Figure 1. Hidden Refresh Cycle
MCM54100A•MCM5L4100A
14 MOTOROLA DRAM
TEST MODE
The internal organization of this device (512K x 8) allows it
to be tested as if it were a 512K x 1 DRAM. Nineteen of the
twenty–two addresses are used when operating the device in
test mode. Row address A0, and column addresses A0 and
A10 are ignored by the device in test mode. A test mode cycle
reads and/or writes data to a bit in each of eight 512K blocks
(B0 – B7) in parallel. External data out is determined by the
internal test mode logic of the device. See the following truth
table and test mode block diagram.
W, CAS before RAS timing puts the device in “Test Mode”
as shown in the test mode timing diagram. A CAS before RAS
or a RAS only refresh cycle puts the device back into normal
mode. Refresh is performed in test mode by using a W, CAS
before RAS refresh cycle which uses internal refresh address
counter.
TEST MODE TRUTH TABLE
D B0 B1 B2 B3 B4 B5 B6 B7 Q
0 0 0 0 0 0 0 0 0 1
1 1 1 1 1 1 1 1 1 1
— Any Other 0
TEST MODE
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V ±10%, TA = 0 to 70°C, Unless Otherwise Noted)
READ, WRITE, AND READ–WRITE CYCLES (See Notes 1, 2, 3, and 4)
Symbol MCM54100A–60
MCM5L4100A–60 MCM54100A–70
MCM5L4100A–70 MCM54100A–80
MCM5L4100A–80
Parameter Std Alt Min Max Min Max Min Max Unit Notes
Random Read or Write Cycle
Time tRELREL tRC 115 — 135 — 155 — ns 5
Fast Page Mode Cycle Time tCELCEL tPC 50 — 50 — 55 — ns
Access Time from RAS tRELQV tRAC — 65 — 75 — 85 ns 6, 7
Access Time from CAS tCELQV tCAC — 25 — 25 — 25 ns 6, 8
Access Time from Column
Address tAVQV tAA — 35 — 40 — 45 ns 6, 9
Access Time from Precharge
CAS tCEHQV tCPA — 45 — 45 — 50 ns 6
RAS Pulse Width tRELREH tRAS 65 10 k 75 10 k 85 10 k ns
RAS Pulse Width (Fast Page
Mode) tRELREH tRASP 65 200 k 75 200 k 85 200 k ns
RAS Hold Time tCELREH tRSH 25 — 25 — 25 — ns
CAS Hold Time tRELCEH tCSH 65 — 75 — 85 — ns
CAS Precharge to RAS Hold
Time tCEHREH tRHCP 45 — 45 — 50 — ns
CAS Pulse Width tCELCEH tCAS 25 10 k 25 10 k 25 10 k ns
Column Address to RAS Lead
Time tAVREH tRAL 35 — 40 — 45 — ns
NOTES:
1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. T ransition times are measured between VIH and VIL.
2. An initial pause of 200 µs is required after power–up followed by 8 RAS cycles before proper device operation is guaranteed.
3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must
transition between VIH and VIL (or between VIL and VIH) in a monotonic manner.
5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature
range (0°C ≤ TA ≤ 70°C) is ensured.
6. Measured with a current load equivalent to 2 TTL (– 200 µA, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V
and VOL = 0.8 V.
7. Assumes that tRCD ≤ tRCD (max).
8. Assumes that tRCD ≥ tRCD (max).
9. Assumes that tRAD ≥ tRAD (max).
MCM54100A•MCM5L4100A
15
MOTOROLA DRAM
WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY)
(D and A0 – A10 are Don’t Care)
tRC
tRAS tRP
tRPC tCHR
tCSR
tCP
tWTH
tWTS
tOFF
HIGH–Z
CAS
RAS
W
VIH
VIL
VIH
VIL
VIH
VIL
Q (DATA OUT) VOH
VOL
MCM54100A•MCM5L4100A
16 MOTOROLA DRAM
TEST MODE — READ CYCLE
HIGH–Z
tRP
tRAS
tRC
tRAC VALID DATA
tCAC
tCLZ
tAA
tRCS
tOFF
tRCH
tRRH
ROW
ADDRESS COLUMN ADDRESS
tASR tRAH
tRCD tCSH tRSH
tCAS
tCRP
tRAD
tCRP
tASC
tRAL
tCAH
Q (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
TEST MODE — EARLY WRITE CYCLE
tRP
tRAS
tRC
tRCD tRSH
tCAS
tCRP tCSH
ROW
ADDRESS COLUMN ADDRESS
tCAH
tRAD tRAL
tRAH tASC
tASR
tCWL
tWP
tWCH
VALID DATA
tRWL
tDS tDH
HIGH–Z
tWCS
CRP
t
Q (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
D (DATA IN) VIH
VIL
MCM54100A•MCM5L4100A
17
MOTOROLA DRAM
TEST MODE — FAST PAGE MODE READ CYCLE
tCAC
tCAC
tCLZ tCLZ
tOFF tOFF
tOFF
tCLZ
tRAC
tCAC
tRRH
tAA tAA
tAA
tRCH
tRCS tRCS
tRCH
tRCS
tCAH
tRAL
tASC
tCAH
tASC
tRAH
tASR tASC
tCAH
tCAS
tRSH
tCAS
tCAS
tRCD
tCRP tRHCP
tRP
tRASP
ROW
ADD COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
VALID
DATA OUT VALID
DATA OUT VALID
DATA OUT
tCP
tRCH
tCPA
tPC
tCP
tCSH
tRAD
tCPA
Q (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
TEST MODE — FAST PAGE MODE EARLY WRITE CYCLE
tDH
tDS
tDH
tDS
tDH
tDS
tWCH
tWP
tWP
tWP
tRAD
tCAH
tRAL
tASC
tCAH
tASC
tRAH
tASR
tASC
tCAH
tCAS
tRSH
tCAS
tCAS
tRCD
tCRP
tRHCP
tRP
tRASP
VALID
DATA IN VALID
DATA IN VALID
DATA IN
ROW
ADD COLUMN
ADDRESS COLUMN
ADDRESS COLUMN
ADDRESS
tCP
tWCS
tWCS tWCS
tPC
tWCH
tWCH
tCP
HIGH–Z
Q (DATA OUT)
W
CAS
RAS
ADDRESSES
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Q (DATA IN) VIH
VIL
MCM54100A•MCM5L4100A
18 MOTOROLA DRAM
TEST MODE BLOCK DIAGRAM
B
H
G
F
E
D
C
A
ADDRESSES
B0 A10R, A10C, A0C
B1 A10R, A10C, A0C
B2 A10R, A10C, A0C
B3 A10R, A10C, A0C
B4 A10R, A10C, A0C
B5 A10R, A10C, A0C
B6 A10R, A10C, A0C
B7 A10R, A10C, A0C
ADDRESSES
NORMAL
TEST MODE
CC
V
OUT
D
TEST MODE
NORMAL
ADDRESSES
TEST MODE
IN
DNORMAL
ADDRESSES
H
G
F
E
D
C
B
A
512K BLOCK
B0
512K BLOCK
B1
512K BLOCK
B2
512K BLOCK
B3
512K BLOCK
B4
512K BLOCK
B5
512K BLOCK
B6
512K BLOCK
B7
ORDERING INFORMATION
(Order by Full Part Number)
Motorola Memory Prefix
Part Number
Package (N = 300 mil SOJ, T = 300 mil TSOP)
Full Part Numbers — MCM54100AN60 MCM54100AN60R2 MCM54100AT60 MCM54100AT60R2
MCM54100AN70 MCM54100AN70R2 MCM54100AT70 MCM54100AT70R2
MCM54100AN80 MCM54100AN80R2 MCM54100AT80 MCM54100AT80R2
MCM5L4100AN60 MCM5L4100AN60R2 MCM5L4100AT60 MCM5L4100AT60R2
MCM5L4100AN70 MCM5L4100AN70R2 MCM5L4100AT70 MCM5L4100AT70R2
MCM5L4100AN80 MCM5L4100AN80R2 MCM5L4100AT80 MCM5L4100AT80R2
Speed (60 = 60 ns, 70 = 70 ns, 80 = 80 ns)
MCM 54100A or 5L4100A X XX XX
Shipping Method (R2 = Tape and Reel, Blank = Rails)
MCM54100A•MCM5L4100A
19
MOTOROLA DRAM
PACKAGE DIMENSIONS
N PACKAGE
300 MIL SOJ
CASE 822–03
0.25 (0.010) T B
MS
0.18 (0.007) T A
MS
1.27 BSC
2.54 BSC
5
26 DETAIL Z
D 20 PL
22 18 14
139
1
KDETAIL Z
H BRK
C
E
S RAD
N
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION A & B DO NOT INCLUDE MOLD
PROTRUSION. MOLD PROTRUSION SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIM R TO BE DETERMINED AT DATUM -T-.
5. FOR LEAD IDENTIFICATION PURPOSES, PIN
POSITIONS 6, 7, 8, 19, 20, & 21 ARE NOT USED.
6. 822-01 AND -02 OBSOLETE, NEW STANDARD
822-03.
G
L
F
P
R
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
E
F
G
H
K
L
M
N
P
R
S
17.02
7.50
3.26
0.39
2.24
0.67
—
0.89
0
°
0.89
8.39
6.61
0.77
17.27
7.74
3.75
0.50
2.48
0.81
0.50
1.14
10
°
1.14
8.63
6.98
1.01
0.670
0.295
0.128
0.015
0.088
0.026
—
0.035
0
°
0.035
0.330
0.260
0.030
0.680
0.305
0.148
0.020
0.098
0.032
0.020
0.045
10
°
0.045
0.340
0.275
0.040
0.050 BSC
0.100 BSC
-A-
0.10 (0.004)
SEATING
PLANE
-T-
-B-
M
M
0.18 (0.007) T B
MS
MCM54100A•MCM5L4100A
20 MOTOROLA DRAM
T PACKAGE
300 MIL TSOP
CASE 892–01
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÉÉÉÉÉ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
ÇÇÇÇ
K
RAD T
RAD V
W
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE MOLD PROTRUSION
IS 0.006 (0.15) PER SIDE.
D
F
J
N
BASE METAL
DETAIL A
ROTATED 905 CW SECTION B-B
T Z0.008 (0.20) M S
MIN MINMAX MAX
MILLIMETERS INCHES
DIM
A
B
C
D
F
G
J
K
L
N
R
S
17.05
7.52
0.33
0.33
0.12
0.41
0.02
0.11
9.05
17.25
7.72
1.27
0.48
0.43
0.20
0.58
0.18
0.16
9.39
0.671
0.296
0.013
0.013
0.005
0.016
0.001
0.004
0.356
0.679
0.304
0.050
0.019
0.017
0.008
0.023
0.007
0.006
0.370
L
4. DIMENSION D DOES NOT INCLUDE DAM BAR
PROTRUSIONS. ALLOWABLE PROTRUSION IS
0.007 (0.18), TOTAL, IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
—
1.27 BSC
—
0.050 BSC
2.54 BSC 0.100 BSC
0.10 REF 0.004 REF
0.10 REF 0.004 REF
W0
°
5
°
0
°
5
°
26
A-Z-
R 4X G 16X
DETAIL A
C
S 10X
T Y0.008 (0.20) M S
0.004 (0.10)
SEATING
PLANE
-T-
22 18 14
1 5 9 13
B
-Y-
B B
T
V
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty , representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit,
and specifically disclaims any and all liability , including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different
applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does
not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in
systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of
the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Af firmative Action Employer.
How to reach us:
USA /EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki,
P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315
MFAX: RMFAX0@email.sps.mot.com – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park,
INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298
MCM54100A/D
*MCM54100A/D*
◊
