MOTOROLA Order this document by MCM54100A/D SEMICONDUCTOR TECHNICAL DATA Advance Information MCM54100A MCM5L4100A 4M x 1 CMOS Dynamic RAM Fast Page Mode N PACKAGE 300 MIL SOJ CASE 822-03 The MCM54100A is a 0.7 CMOS high-speed dynamic random access memory. It is organized as 4,194,304 one-bit words and fabricated with CMOS silicon-gate process technology. Advanced circuit design and fine line processing provide high performance, improved reliability, and low cost. The MCM54100A requires only 11 address lines; row and column address inputs are multiplexed. The device is packaged in a standard 300 mil J lead small outline package and a 300 mil thin small outline package (TSOP). * * * * * * * * * Three-State Data Output Fast Page Mode Test Mode TTL-Compatible Inputs and Outputs RAS-Only Refresh CAS Before RAS Refresh Hidden Refresh 1024 Cycle Refresh: MCM54100A = 16 ms Fast Access Time (tRAC): MCM54100A-60 and MCM5L4100A-60 = 60 ns (Max) MCM54100A-70 and MCM5L4100A-70 = 70 ns (Max) MCM54100A-80 and MCM5L4100A-80 = 80 ns (Max) * Low Active Power: MCM54100A-60 and MCM5L4100A-60 = 660 mW (Max) MCM54100A-70 and MCM5L4100A-70 = 550 mW (Max) MCM54100A-80 and MCM5L4100A-80 = 468 mW (Max) * Low Standby Power Dissipation: MCM54100A and MCM5L400A = 11 mW (Max, TTL Levels) MCM54100A = 5.5 mW (Max, CMOS Levels) MCM5L4100A = 1.1 mW (Max, CMOS Levels) T PACKAGE 300 MIL TSOP CASE 892-01 PIN ASSIGNMENT D 1 26 VSS W 2 25 Q RAS 3 24 CAS NC 4 23 NC A10 5 22 A9 A0 9 18 A8 A1 10 17 A7 A2 11 16 A6 A3 12 15 A5 VCC 13 14 A4 PIN NAMES A0 - A10 . . . . . . . . . . . . . . Address Input D . . . . . . . . . . . . . . . . . . . . . . . . Data Input Q . . . . . . . . . . . . . . . . . . . . . Data Output W . . . . . . . . . . . . . . . Read/Write Enable RAS . . . . . . . . . . . . Row Address Strobe CAS . . . . . . . . . Column Address Strobe VCC . . . . . . . . . . . Power Supply (+ 5 V) VSS . . . . . . . . . . . . . . . . . . . . . . . Ground NC . . . . . . . . . . . . . . . . . . No Connection This document contains information on a new product. Specifications and information herein are subject to change without notice. REV 4 10/95 Motorola, Inc. 1995 MOTOROLA DRAM MCM54100A*MCM5L4100A 1 BLOCK DIAGRAM W CAS #2 CLOCK GENERATOR A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 RAS COLUMN ADDRESS BUFFERS (11) DATA IN BUFFER D DATA OUT BUFFER Q COLUMN DECODER REFRESH CONTROLLER SENS AMP I/O GATING REFRESH COUNTER (10) 4096 ROW ADDRESS BUFFERS (11) ROW DECODER 1024 #1 CLOCK GENERATOR MEMORY ARRAY SUBSTRATE BIAS GENERATOR VCC VSS ABSOLUTE MAXIMUM RATINGS (See Note) Rating Symbol Value Unit VCC - 1 to + 7 V Vin, Vout - 1 to + 7 V Data Output Current Iout 50 mA Power Dissipation PD 700 mW Operating Temperature Range TA 0 to + 70 C Power Supply Voltage Voltage Relative to VSS for Any Pin Except VCC This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to these high-impedance circuits. Storage Temperature Range Tstg - 55 to + 150 C NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED OPERATING CONDITIONS. Exposure to higher than recommended voltages for extended periods of time could affect device reliability. MCM54100A*MCM5L4100A 2 MOTOROLA DRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (All voltages referenced to VSS) Parameter Supply Voltage (Operating Voltage Range) Symbol Min Typ Max Unit VCC 4.5 5.0 5.5 V VSS 0 0 0 Logic High Voltage, All Inputs VIH 2.4 -- 6.5 V Logic Low Voltage, All Inputs VIL - 1.0 -- 0.8 V Symbol Min Max Unit Notes mA 1, 2 -- -- -- 120 100 85 -- 2.0 -- -- -- 120 100 85 -- -- -- 70 70 60 -- -- 1.0 200 -- -- -- 120 100 85 DC CHARACTERISTICS Characteristic VCC Power Supply Current ICC1 MCM54100A-60 and MCM5L4100A-60, tRC = 110 ns MCM54100A-70 and MCM5L4100A-70, tRC = 130 ns MCM54100A-80 and MCM5L4100A-80, tRC = 150 ns VCC Power Supply Current (Standby) (RAS = CAS = VIH) ICC2 VCC Power Supply Current During RAS Only Refresh Cycles (CAS = VIH) MCM54100A-60 and MCM5L4100A-60, tRC = 110 ns MCM54100A-70 and MCM5L4100A-70, tRC = 130 ns MCM54100A-80 and MCM5L4100A-80, tRC = 150 ns ICC3 VCC Power Supply Current During Fast Page Mode Cycle (RAS = VIL) MCM54100A-60 and MCM5L4100A-60, tPC = 45 ns MCM54100A-70 and MCM5L4100A-70, tPC = 45 ns MCM54100A-80 and MCM5L4100A-80, tPC = 50 ns ICC4 VCC Power Supply Current (Standby) (RAS = CAS = VCC - 0.2 V) ICC5 MCM54100A MCM5L4100A VCC Power Supply Current During CAS Before RAS Refresh Cycle MCM54100A-60 and MCM5L4100A-60, tRC = 110 ns MCM54100A-70 and MCM5L4100A-70, tRC = 130 ns MCM54100A-80 and MCM5L4100A-80, tRC = 150 ns ICC6 VCC Power Supply Current, Battery Backup Mode -- MCM5L4100A Only (tRC = 125 s; CAS = CAS Before RAS Cycling or 0.2 V; W = VCC - 0.2 V; Din = VCC - 0.2 V or 0.2 V or OPEN; A0 - A10 = VCC - 0.2 V or 0.2 V) tRAS = 300 ns to 1 s tRAS = Min to 300 ns ICC7 -- -- 400 300 mA mA 1, 2 mA 1, 2 mA A mA 1 A 1, 3 Input Leakage Current (0 V Vin 6.5 V) Ilkg(I) - 10 10 A Output Leakage Current (CAS = VIH, 0 V Vout 5.5 V) Ilkg(O) - 10 10 A Output High Voltage (IOH = - 5 mA) VOH 2.4 -- V Output Low Voltage (IOL = 4.2 mA) VOL -- 0.4 V NOTES: 1. Current is a function of cycle rate and output loading; maximum currents are specified cycle time (minimum) with the output open. 2. Column address can be changed once or less while RAS = VIL and CAS = VIH. 3. tRAS (max) = 1 s is only applied to refresh of battery-back up. tRAS (max) = 10 s is applied to functional operating CAPACITANCE (f = 1.0 MHz, TA = 25C, VCC = 5 V, Periodically Sampled Rather Than 100% Tested) Characteristic Input Capacitance A0 - A10, D Symbol Max Unit Cin 5 pF RAS, CAS, W 7 I/O Capacitance (CAS = VIH to Disable Output) Q Cout NOTE: Capacitance measured with a Boonton Meter or effective capacitance calculated from the equation: C = I t/V. MOTOROLA DRAM 7 pF MCM54100A*MCM5L4100A 3 AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4) MCM54100A-60 MCM5L4100A-60 Symbol MCM54100A-70 MCM5L4100A-70 MCM54100A-80 MCM5L4100A-80 Parameter Std Alt Min Max Min Max Min Max Unit Notes Random Read or Write Cycle Time tRELREL tRC 110 -- 130 -- 150 -- ns 5 Read-Write Cycle Time tRELREL tRWC 140 -- 155 -- 175 -- ns 5 Fast Page Mode Cycle Time tCELCEL tPC 45 -- 45 -- 50 -- ns Fast Page Mode Read-Write Cycle Time tCELCEL tPRWC 65 -- 70 -- 75 -- ns Access Time from RAS tRELQV tRAC -- 60 -- 70 -- 80 ns 6, 7 Access Time from CAS tCELQV tCAC -- 20 -- 20 -- 20 ns 6, 8 Access Time from Column Address tAVQV tAA -- 30 -- 35 -- 40 ns 6, 9 Access Time from Precharge CAS tCEHQV tCPA -- 40 -- 40 -- 45 ns 6 CAS to Output in Low-Z tCELQX tCLZ 0 -- 0 -- 0 -- ns 6 Output Buffer and Turn-Off Delay tCEHQZ tOFF 0 20 0 20 0 20 ns 10 tT tT 3 50 3 50 3 50 ns RAS Precharge Time tREHREL tRP 45 -- 50 -- 60 -- ns RAS Pulse Width tRELREH tRAS 60 10 k 70 10 k 80 10 k ns RAS Pulse Width (Fast Page Mode) tRELREH tRASP 60 200 k 70 200 k 80 200 k ns RAS Hold Time tCELREH tRSH 20 -- 20 -- 20 -- ns CAS Hold Time tRELCEH tCSH 60 -- 70 -- 80 -- ns CAS Precharge to RAS Hold Time tCEHREH tRHCP 40 -- 40 -- 45 -- ns CAS Pulse Width tCELCEH tCAS 20 10 k 20 10 k 20 10 k ns RAS to CAS Delay Time tRELCEL tRCD 20 40 20 50 20 60 ns 11 tRELAV tRAD 15 30 15 35 15 40 ns 12 CAS to RAS Precharge Time tCEHREL tCRP 5 -- 5 -- 5 -- ns CAS Precharge Time tCEHCEL tCP 10 -- 10 -- 10 -- ns tAVREL tASR 0 -- 0 -- 0 -- ns Transition Time (Rise and Fall) RAS to Column Address Delay Time Row Address Setup Time Row Address Hold Time tRELAX tRAH 10 -- 10 -- 10 -- ns NOTES: (continued) 11. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 12. An initial pause of 200 s is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. 13. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 14. AC measurements tT = 5.0 ns. 15. The specification for tRC (min) is used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is ensured. 16. Measured with a current load equivalent to 2 TTL (- 200 A, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and VOL = 0.8 V. 17. Assumes that tRCD tRCD (max). 18. Assumes that tRCD tRCD (max). 19. Assumes that tRAD tRAD (max). 10. tOFF (max) defines the time at which the output achieves the open circuit condition and is not referenced to output voltage levels. 11. Operation within the tRCD (max) limit ensures that tRAC (max) can be met. tRCD (max) is specified as a reference point only; if tRCD is greater than the specified tRCD (max) limit, then access time is controlled exclusively by tCAC. 12. Operation within the tRAD (max) limit ensures that tRAC (max) can be met. tRAD (max) is specified as a reference point only; if tRAD is greater than the specified tRAD (max), then access time is controlled exclusively by tAA. MCM54100A*MCM5L4100A 4 MOTOROLA DRAM READ, WRITE, AND READ-WRITE CYCLES (Continued) MCM54100A-60 MCM5L4100A-60 Symbol Parameter MCM54100A-70 MCM5L4100A-70 MCM54100A-80 MCM5L4100A-80 Std Alt Min Max Min Max Min Max Unit Column Address Setup Time tAVCEL tASC 0 -- 0 -- 0 -- ns Column Address Hold Time tCELAX tCAH 15 -- 15 -- 15 -- ns Column Address to RAS Lead Time tAVREH tRAL 30 -- 35 -- 40 -- ns Read Command Setup Time tWHCEL tRCS 0 -- 0 -- 0 -- ns Read Command Hold Time Referenced to CAS tCEHWX tRCH 0 -- 0 -- 0 -- ns 13 Read Command Hold Time Referenced to RAS tREHWX tRRH 0 -- 0 -- 0 -- ns 13 Write Command Hold Time Referenced to CAS tCELWH tWCH 10 -- 15 -- 15 -- ns Write Command Pulse Width tWLWH tWP 10 -- 15 -- 15 -- ns Write Command to RAS Lead Time tWLREH tRWL 20 -- 20 -- 20 -- ns Write Command to CAS Lead Time tWLCEH tCWL 20 -- 20 -- 20 -- ns Data in Setup Time tDVCEL tDS 0 -- 0 -- 0 -- ns 14 tCELDX tDH 15 -- 15 -- 15 -- ns 14 tRVRV tRFSH -- -- 16 128 -- -- 16 128 -- -- 16 128 ms Write Command Setup Time tWLCEL tWCS 0 -- 0 -- 0 -- ns 15 CAS to Write Delay tCELWL tCWD 20 -- 20 -- 20 -- ns 15 RAS to Write Delay tRELWL tRWD 60 -- 70 -- 80 -- ns 15 tAVWL tAWD 30 -- 35 -- 40 -- ns 15 CAS Precharge to Write Delay Time (Page Mode) tCEHWL tCPWD 40 -- 40 -- 40 -- ns 15 CAS Setup Time for CAS Before RAS Refresh tRELCEL tCSR 5 -- 5 -- 5 -- ns CAS Hold Time for CAS Before RAS Refresh tRELCEH tCHR 15 -- 15 -- 15 -- ns RAS Precharge to CAS Active Time tREHCEL tRPC 0 -- 0 -- 0 -- ns CAS Precharge Time for CAS Before RAS Counter Time tCEHCEL tCPT 30 -- 40 -- 40 -- ns Write Command Setup Time (Test Mode) tWLREL tWTS 10 -- 10 -- 10 -- ns Write Command Hold Time (Test Mode) tRELWH tWTH 10 -- 10 -- 10 -- ns Write to RAS Precharge Time (CAS Before RAS Refresh) tWHREL tWRP 10 -- 10 -- 10 -- ns Write to RAS Hold Time (CAS Before RAS Refresh) tRELWL tWRH 10 -- 10 -- 10 -- ns Data in Hold Time Refresh Period MCM54100A MCM5L4100A Column Address to Write Delay Time Notes NOTES: 13. Either tRRH or tRCH must be satisfied for a read cycle. 14. These parameters are referenced to CAS leading edge in early write cycles and to W leading edge in read-write cycles. 15. tWCS, tRWD, tCWD, tAWD, and tCPWD are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if tCWD t CWD (min), tRWD t RWD (min), tAWD t AWD (min), and tCPWD t CPWD (min) (page mode), the cycle is a read-write cycle and the data out will contain data read from the selected cell. If neither of these sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. MOTOROLA DRAM MCM54100A*MCM5L4100A 5 READ CYCLE tRC tRAS RAS t RP VIH VIL t CSH t CRP CAS t CRP t RCD t RSH t CAS VIH t CP VIL t RAL t CAH t RAD t ASR ADDRESSES VIH t ASC ROW ADDRESS VIL COLUMN ADDRESS t RAH t RCH t RCS W t RRH VIH VIL t CAC t AA t CLZ t OFF t RAC D (DATA OUT) VOH HIGH-Z VALID DATA VOL EARLY WRITE CYCLE t RC t RAS RAS VIH VIL t RCD t CRP CAS t RSH t CSH t CP VIL t RAL t CAH t RAD VIH VIL t ASC ROW ADDRESS COLUMN ADDRESS t RAH t CWL t WCS W t CRP t CAS VIH t ASR ADDRESSES t RP t WCH t WP VIH VIL t RWL t DS D (DATA IN) D (DATA OUT) VIH VIL VOH t DH VALID DATA HIGH-Z VOL MCM54100A*MCM5L4100A 6 MOTOROLA DRAM READ-WRITE CYCLE t RWC t RAS RAS VIH VIL t RSH t RCD t CRP CAS t RP t RWL VIL VIH ROW ADDRESS VIL t CWL t RAL t ASC t CAH COLUMN ADDRESS t RAD t ASR t RAH t AWD t RWD t WP t CWD W VIH VIL t RCS D (DATA IN) t CP VIH t CSH ADDRESSES t CRP t CAS t DH t DS VIH VALID DATA VIL t CAC t AA t OFF t RAC D (DATA OUT) VOH HIGH-Z VALID DATA VOL t CLZ FAST PAGE MODE READ CYCLE t RASP RAS VIH VIL t RSH t CAS t CAS t CAS t CP t CP t CP VIH VIL t ASC t ASR ADDRESSES t PC t CSH t RCD t CRP CAS t RP t RHCP VIH VIL t CAH ROW ADDRESS t ASC COLUMN ADDRESS t CAH t CAH t ASC t RAL COLUMN ADDRESS COLUMN ADDRESS t RAH t RCS W t RCS t RCS t RCH VIH VIL t CAC t AA t AA t AA t CPA t CPA VOH VALID DATA VOL t CLZ MOTOROLA DRAM t CAC t CAC t RAC D (DATA OUT) t RRH t RCH t RCH t RAD t OFF VALID DATA t OFF t OFF t CLZ VALID DATA t CLZ MCM54100A*MCM5L4100A 7 FAST PAGE MODE EARLY WRITE CYCLE t RASP RAS t RP t RHCP VIH VIL t RCD t PC t CRP CAS VIL t ASC t ASC t RAH VIH VIL COLUMN ADDRESS D (DATA OUT) COLUMN ADDRESS t WCH t WCS t WCH t WP VIL t DS t DS t DH t DH VALID DATA VIL t WCH t WP t WP VIH t CAH COLUMN ADDRESS t WCS VIH t RAL t ASC t CAH t CAH ROW ADDRESS t DS D (DATA IN) t CP t CP VIH t RAD t WCS W t CAS t CP t ASR ADDRESSES t RSH t CAS t CAS t DH VALID DATA VOH VALID DATA HIGH-Z VOL FAST PAGE MODE READ-WRITE CYCLE RAS t RP t RASP VIH VIL t CSH t CRP CAS VIL t ASC VIH VIL ROW ADDRESS COLUMN ADDRESS t RAD t RCS t RAL t ASC t ASC t CAH t CAH t RAH t CAH COLUMN ADDRESS tCWD tCWD VIL tDS t RWL t CWL t AWD t AWD VALID DATA VIL tDH tCPWD tDH t CAC t CAC t AA t CPA t AA t CPA VALID DATA t OFF t WP VALID DATA tCLZ tCLZ VOH MCM54100A*MCM5L4100A 8 t WP VALID DATA t RAC VOL tDS tDS t WP tCPWD tDH VIH t CAC D (DATA OUT) tCWD t CWL VIH tRWD D (DATA IN) COLUMN ADDRESS t CWL t AWD W t CP t CAS t CAS VIH t ASR ADDRESSES t CAS t RCD t RSH t PRWC t CP t CP tCLZ t AA VALID DATA t OFF VALID DATA t OFF MOTOROLA DRAM RAS ONLY REFRESH CYCLE (W and A10 are Don't Care) t RC RAS t RP t RAS VIH VIL t CRP CAS t RPC VIH VIL t RAH t ASR A0 TO A9 D (DATA OUT) VIH ROW ADDRESS VIL VOH HIGH-Z VOL CAS BEFORE RAS REFRESH CYCLE (A0 - A10 are Don't Care) t RC RAS t RAS VIH VIL t CP CAS tCSR t RPC t CHR VIH VIL t WRP W t RP t WRH VIH VIL t OFF D (DATA OUT) VOH HIGH-Z VOL MOTOROLA DRAM MCM54100A*MCM5L4100A 9 HIDDEN REFRESH CYCLE (READ) t RAS t RC t RP t RAS VIH RAS VIL t CRP t RCD t RSH t CHR t CP VIH CAS VIL t ASR ADDRESSES t RAL t CAH t ASC t RAD t RAH VIH ROW ADDRESS VIL COLUMN ADDRESS t RCS t WRP t RRH t WRH VIH W VIL t CAC t AA t OFF t RAC D (DATA OUT) VOH VALID DATA VOL t CLZ HIDDEN REFRESH CYCLE (EARLY WRITE) t RC t RAS t RAS RAS VIH VIL t CRP CAS t RCD t RSH t CP VIL t RAD t RAH VIH VIL t RAL t ASC t CAH COLUMN ADDRESS ROW ADDRESS t RWL t WCH W t CHR VIH t ASR ADDRESSES t RP t WRP t WRH t WCS VIH VIL t WP t DS D (DATA IN) D (DATA OUT) VIH VIL VOH VOL MCM54100A*MCM5L4100A 10 t DH VALID DATA HIGH-Z MOTOROLA DRAM CAS BEFORE RAS REFRESH COUNTER TEST CYCLE t RAS RAS VIH VIL t CSR CAS t RP t RSH t CAS t CPT t CHR VIH VIL t ASC ADDRESSES VIH t CAH COLUMN ADDRESS VIL t CAC t RAL Q (DATA OUT) t OFF t AA READ CYCLE VOH VALID DATA HIGH-Z VOL tCLZ t WRP W t WRH t RRH t RCH t RCS VIH VIL EARLY WRITE CYCLE Q (DATA OUT) VOH HIGH-Z VOL t WRP W t WRH t RWL t CWL t WCH t WCS t WP VIH VIL t DH t DS D (DATA IN) VIH VALID DATA VIL t CAC tCLZ READ-WRITE CYCLE Q (DATA OUT) VOH VALID DATA HIGH-Z VOL t WRH t AA t WRP W t OFF t CWL t RWL t AWD VIH VIL t RCS tCWD D (DATA IN) VIH VALID DATA VIL tDS MOTOROLA DRAM t WP tDH MCM54100A*MCM5L4100A 11 DEVICE INITIALIZATION On power-up, an initial pause of 200 microseconds is required for the internal substrate generator to establish the correct bias voltage. This must be followed by a minimum of eight active cycles of the row address strobe (clock) to initialize all dynamic nodes within the RAM. During an extended inactive state (greater than 16 milliseconds or 128 milliseconds in case of low power device, with the device powered up), a wakeup sequence of eight active cycles is necessary to ensure proper operation. ADDRESSING THE RAM The eleven address pins on the device are time multiplexed at the beginning of a memory cycle by two clocks, row address strobe (RAS) and column address strobe (CAS), into two separate 11-bit address fields. A total of twenty-two address bits, eleven rows and eleven columns, will decode one of the 4,194,304 bit locations in the device. RAS active transition is followed by CAS active transition (active = V IL, t RCD minimum) for all read or write cycles. The delay between RAS and CAS active transitions, referred to as the multiplex window, gives a system designer flexibility in setting up the external addresses into the RAM. The external CAS signal is ignored until an internal RAS signal is available. This "gate" feature on the external CAS clock enables the internal CAS line as soon as the row address hold time (tRAH) specification is met (and defines tRCD minimum). The multiplex window can be used to absorb skew delays in switching the address bus from row to column addresses and in generating the CAS clock. There are three other variations in addressing the 4M RAM: RAS only refresh cycle, CAS before RAS refresh cycle, and page mode. READ CYCLE The DRAM may be read with four different cycles: "normal" random read cycle, page mode read cycle, read-write cycle, and page mode read-write cycle. The normal read cycle is outlined here, while the other cycles are discussed in separate sections. The normal read cycle begins as described in ADDRESSING THE RAM, with RAS and CAS active transitions latching the desired bit location. The write (W) input level must be high (V IH), t RCS (minimum) before the CAS active transition, to enable read mode. Both the RAS and CAS clocks trigger a sequence of events that are controlled by several delayed internal clocks. The internal clocks are linked in such a manner that the read access time of the device is independent of the address multiplex window; however, CAS must be active before or at t RCD maximum to guarantee valid data out (Q) at t RAC (access time from RAS active transition). If the t RCD maximum is exceeded, read access time is determined by the CAS clock active transition (t CAC). The RAS and CAS clocks must remain active for a mini- mum time of t RAS and t CAS, respectively, to complete the read cycle. W must remain high throughout the cycle, and for time tRRH or tRCH after RAS or CAS inactive transition, respectively, to maintain the data at that bit location. Once RAS transitions to inactive, it must remain inactive for a minimum time of tRP to precharge the internal device circuitry for the next active cycle. Q is valid, but not latched, as long as the MCM54100A*MCM5L4100A 12 CAS clock is active. When the CAS clock transitions to inactive, the output will switch to High-Z (three-state). WRITE CYCLE The user can write to the DRAM with any of four cycles: early write, late write, page mode early write, and page mode read-write. Early and late write modes are discussed here, while page mode write operations are covered elsewhere. A write cycle begins as described in ADDRESSING THE RAM. Write mode is enabled by the transition of W to active (V IL). Early and late write modes are distinguished by the active transition of W, with respect to CAS. Minimum active time tRAS and t CAS, and precharge time t RP apply to write mode, as in the read mode. An early write cycle is characterized by W active transition at minimum time t WCS before CAS active transition. Data in (D) is referenced to CAS in an early write cycle. RAS and CAS clocks must stay active for t RWL and t CWL, respectively, after the start of the early write operation to complete the cycle. Q remains in three-state condition throughout an early write cycle because W active transition precedes or coincides with CAS active transition, keeping data-out buffers disabled. This feature can be utilized on systems with a common I/O bus, provided all writes are performed with early write cycles, to prevent bus contention. A late write cycle occurs when W active transition is made after CAS active transition. W active transition could be delayed for almost 10 microseconds after CAS active transition, (tRCD + tCWD + tRWL + 2tT) tRAS, if other timing minimums (tRCD, tRWL, and tT) are maintained. D is referenced to W active transition in a late write cycle. Output buffers are enabled by CAS active transition but Q may be indeterminate; see note 15 of AC Operating Conditions table. RAS and CAS must remain active for t RWL and t CWL, respectively, after W active transition to complete the write cycle. READ-WRITE CYCLE A read-write cycle performs a read and then a write at the same address, during the same cycle. This cycle is basically a late write cycle, as discussed in the WRITE CYCLE section, except W must remain high for tCWD minimum after the CAS active transition, to guarantee valid Q before writing the bit. PAGE MODE CYCLES Page mode allows fast successive data operations at all 2048 column locations on a selected row of the 4M dynamic RAM. Read access time in page mode (t CAC) is typically half the regular RAS clock access time, t RAC. Page mode operation consists of keeping RAS active while toggling CAS between V IH and V IL. The row is latched by RAS active transition, while each CAS active transition allows selection of a new column location on the row. A page mode cycle is initiated by a normal read, write, or read-write cycle, as described in prior sections. Once the timing requirements for the first cycle are met, CAS transitions to inactive for minimum of t CP, while RAS remains low (V IL). The second CAS active transition while RAS is low initiates the first page mode cycle (t PC or t PRWC). Either a read, write, or read-write operation can be performed in a page mode cycle, subject to the same conditions as in normal operation (previously described). These operations can be intermixed MOTOROLA DRAM in consecutive page mode cycles and performed in any order. The maximum number of consecutive page mode cycles is limited by tRASP. Page mode operation is ended when RAS transitions to inactive, coincident with or following CAS inactive transition. cycle. The output buffer remains at the same state it was in during the previous cycle (hidden refresh). W must be inactive for time t WRP before and time t WRH after RAS active transi- tion to prevent switching the device into test mode. Hidden Refresh REFRESH CYCLES The dynamic RAM design is based on capacitor charge storage for each bit in the array. This charge will tend to degrade with time and temperature. Each bit must be periodically refreshed (recharged) to maintain the correct bit state. Bits in the MCM54100A require refresh every 16 milliseconds, while refresh time for the MCM5L4100A is 128 milliseconds. This is accomplished by cycling through the 1024 row addresses in sequence within the specified refresh time. All the bits on a row are refreshed simultaneously when the row is addressed. Distributed refresh implies a row refresh every 15.6 microseconds for the MCM54100A, and 124.8 microseconds for the MCM5L4100A. Burst refresh, a refresh of all 1024 rows consecutively, must be performed every 16 milliseconds on the MCM54100A and 128 milliseconds on the MCM5L4100A. A normal read, write, or read-write operation to the RAM will refresh all the bits (4096) associated with the particular row decoded. Three other methods of refresh, RAS-only refresh, CAS before RAS refresh, and hidden refresh are available on this device for greater system flexibility. RAS-Only Refresh RAS-only refresh consists of RAS transition to active, latching the row address to be refreshed, while CAS remains high (VIH) throughout the cycle. An external counter is employed to ensure that all rows are refreshed within the specified limit. CAS Before RAS Refresh CAS before RAS refresh is enabled by bringing CAS active before RAS. This clock order activates an internal refresh counter that generates the row address to be refreshed. External address lines are ignored during the automatic refresh MEMORY CYCLE Hidden refresh allows refresh cycles to occur while maintaining valid data at the output pin. Holding CAS active at the end of a read or write cycle, while RAS cycles inactive for tRP and back to active, starts the hidden refresh. This is essentially the execution of a CAS before RAS refresh from a cycle in progress (see Figure 1). W is subject to the same conditions with respect to RAS active transition (to prevent test mode entry) as in CAS before RAS refresh. CAS BEFORE RAS REFRESH COUNTER TEST The internal refresh counter of this device can be tested with a CAS before RAS refresh counter test. This test is performed with a read-write operation. During the test, the internal refresh counter generates the row address, while the external address supplies the column address. The entire array is refreshed after 1024 cycles, as indicated by the check data written in each row. See CAS before RAS refresh counter test cycle timing diagram. The test can be performed after a minimum of 8 CAS before RAS initialization cycles. Test procedure: 1. Write 0s into all memory cells with normal write mode. 2. Select a column address, read 0 out and write 1 into the cell by performing the CAS before RAS refresh counter test, read-write cycle. Repeat this operation 1024 times. 3. Read the 1s which were written in step two in normal read mode. 4. Using the same starting column address as in step two, read 1 out and write 0 into the cell by performing the CAS before RAS refresh counter test, read-write cycle. Repeat this operation 1024 times. 5. Read 0s which were written in step four in normal read mode. 6. Repeat steps one through five using complement data. CAS BEFORE RAS REFRESH CYCLE CAS BEFORE RAS REFRESH CYCLE RAS CAS Q HIGH-Z VALID DATA-OUT Figure 1. Hidden Refresh Cycle MOTOROLA DRAM MCM54100A*MCM5L4100A 13 TEST MODE The internal organization of this device (512K x 8) allows it to be tested as if it were a 512K x 1 DRAM. Nineteen of the twenty-two addresses are used when operating the device in test mode. Row address A0, and column addresses A0 and A10 are ignored by the device in test mode. A test mode cycle reads and/or writes data to a bit in each of eight 512K blocks (B0 - B7) in parallel. External data out is determined by the internal test mode logic of the device. See the following truth table and test mode block diagram. W, CAS before RAS timing puts the device in "Test Mode" as shown in the test mode timing diagram. A CAS before RAS or a RAS only refresh cycle puts the device back into normal mode. Refresh is performed in test mode by using a W, CAS before RAS refresh cycle which uses internal refresh address counter. TEST MODE TRUTH TABLE D B0 B1 B2 B3 B4 B5 B6 B7 Q 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 -- Any Other 0 TEST MODE AC OPERATING CONDITIONS AND CHARACTERISTICS (VCC = 5.0 V 10%, TA = 0 to 70C, Unless Otherwise Noted) READ, WRITE, AND READ-WRITE CYCLES (See Notes 1, 2, 3, and 4) MCM54100A-60 MCM5L4100A-60 Symbol Parameter MCM54100A-70 MCM5L4100A-70 MCM54100A-80 MCM5L4100A-80 Std Alt Min Max Min Max Min Max Unit Notes Random Read or Write Cycle Time tRELREL tRC 115 -- 135 -- 155 -- ns 5 Fast Page Mode Cycle Time tCELCEL tPC 50 -- 50 -- 55 -- ns Access Time from RAS tRELQV tRAC -- 65 -- 75 -- 85 ns 6, 7 Access Time from CAS tCELQV tCAC -- 25 -- 25 -- 25 ns 6, 8 tAVQV tAA -- 35 -- 40 -- 45 ns 6, 9 Access Time from Precharge CAS tCEHQV tCPA -- 45 -- 45 -- 50 ns 6 RAS Pulse Width tRELREH tRAS 65 10 k 75 10 k 85 10 k ns RAS Pulse Width (Fast Page Mode) tRELREH tRASP 65 200 k 75 200 k 85 200 k ns RAS Hold Time tCELREH tRSH 25 -- 25 -- 25 -- ns Access Time from Column Address CAS Hold Time tRELCEH tCSH 65 -- 75 -- 85 -- ns CAS Precharge to RAS Hold Time tCEHREH tRHCP 45 -- 45 -- 50 -- ns CAS Pulse Width tCELCEH tCAS 25 10 k 25 10 k 25 10 k ns tAVREH tRAL 35 -- 40 -- 45 -- ns Column Address to RAS Lead Time NOTES: 1. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH and VIL. 2. An initial pause of 200 s is required after power-up followed by 8 RAS cycles before proper device operation is guaranteed. 3. The transition time specification applies for all input signals. In addition to meeting the transition rate specification, all input signals must transition between VIH and VIL (or between VIL and VIH) in a monotonic manner. 5. The specifications for tRC (min) and tRWC (min) are used only to indicate cycle time at which proper operation over the full temperature range (0C TA 70C) is ensured. 6. Measured with a current load equivalent to 2 TTL (- 200 A, + 4 mA) loads and 100 pF with the data output trip points set at VOH = 2.0 V and VOL = 0.8 V. 7. Assumes that tRCD tRCD (max). 8. Assumes that tRCD tRCD (max). 9. Assumes that tRAD tRAD (max). MCM54100A*MCM5L4100A 14 MOTOROLA DRAM WRITE, CAS BEFORE RAS REFRESH CYCLE (TEST MODE ENTRY) (D and A0 - A10 are Don't Care) tRC tRAS RAS VIL tCHR tRPC tCP CAS tCSR VIH VIL tWTH tWTS W tRP VIH VIH VIL tOFF Q (DATA OUT) VOH HIGH-Z VOL MOTOROLA DRAM MCM54100A*MCM5L4100A 15 TEST MODE -- READ CYCLE t RC RAS VIH VIL t CSH t RCD t CRP CAS t ASR VIH t RAD tRAH t RAL t CAH tASC ROW ADDRESS VIL COLUMN ADDRESS tRCS W tRRH t RCH VIH t CAC VIL tAA t Q (DATA OUT) t CRP t RSH t CAS VIH VIL ADDRESSES t RP t RAS VOH t CLZ t OFF RAC HIGH-Z VALID DATA VOL TEST MODE -- EARLY WRITE CYCLE t RC RAS t RP t RAS VIH VIL t RCD t CRP CAS t CAS VIH VIL t ASR VIH ADDRESSES VIL t RAD tRAH ROW ADDRESS t CRP t RAL t CAH tASC COLUMN ADDRESS t WCS W t RSH tCSH t CWL t WCH t WP VIH VIL t RWL VIH D (DATA IN) VALID DATA VIL t DS Q (DATA OUT) VOH t DH HIGH-Z VOL MCM54100A*MCM5L4100A 16 MOTOROLA DRAM TEST MODE -- FAST PAGE MODE READ CYCLE t RASP RAS t RP VIH t PC VIL t t t CP CSH RCD t CRP CAS t CP t CAS VIH t t CAS t RSH RHCP t CAS VIL t t ASR VIH ADDRESSES t CAH t RAH t ASC ROW ADD VIL t ASC COLUMN ADDRESS t RAL t CAH t ASC COLUMN ADDRESS t RCS RCS COLUMN ADDRESS t RCS t RCH t RCH t RAD W t CAH t RRH t RCH VIH VIL t AA t CAC t VOH Q (DATA OUT) VOL t AA t RAC t CAC t CPA VALID DATA OUT t CLZ t AA t CAC CPA VALID DATA OUT t CLZ t OFF VALID DATA OUT t CLZ t OFF t OFF TEST MODE -- FAST PAGE MODE EARLY WRITE CYCLE t RASP RAS t RP VIH t RHCP VIL t CRP t PC t CAS RCD t CAS VIH VIL t ASC ROW ADD t CAH t ASC COLUMN ADDRESS t WCH tWCS tWCS COLUMN ADDRESS t WCH t WCH tWCS t WP t WP VIH RAL t CAH t ASC COLUMN ADDRESS t RAD W t CAS t t CAH t RAH VIH t CAS t ASR VIL ADDRESSES t RSH tCP tCP t WP VIL t DS VIH Q (DATA IN) VIL VOH Q (DATA OUT) VOL MOTOROLA DRAM t DH VALID DATA IN t t DH DS VALID DATA IN t DS t DH VALID DATA IN HIGH-Z MCM54100A*MCM5L4100A 17 TEST MODE BLOCK DIAGRAM ADDRESSES 512K BLOCK B0 V CC A A NORMAL 512K BLOCK B1 512K BLOCK B2 TEST MODE B B C C ADDRESSES D 512K BLOCK B3 D D OUT NORMAL D IN E 512K BLOCK B4 E 512K BLOCK B5 F 512K BLOCK B6 G TEST MODE F G ADDRESSES B0 B1 B2 B3 B4 B5 B6 B7 A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C A10R, A10C, A0C TEST MODE H 512K BLOCK B7 NORMAL H ADDRESSES ORDERING INFORMATION (Order by Full Part Number) MCM 54100A or 5L4100A X XX XX Motorola Memory Prefix Shipping Method (R2 = Tape and Reel, Blank = Rails) Part Number Speed (60 = 60 ns, 70 = 70 ns, 80 = 80 ns) Package (N = 300 mil SOJ, T = 300 mil TSOP) Full Part Numbers -- MCM54100AN60 MCM54100AN70 MCM54100AN80 MCM5L4100AN60 MCM5L4100AN70 MCM5L4100AN80 MCM54100A*MCM5L4100A 18 MCM54100AN60R2 MCM54100AN70R2 MCM54100AN80R2 MCM54100AT60 MCM54100AT70 MCM54100AT80 MCM54100AT60R2 MCM54100AT70R2 MCM54100AT80R2 MCM5L4100AN60R2 MCM5L4100AN70R2 MCM5L4100AN80R2 MCM5L4100AT60 MCM5L4100AT70 MCM5L4100AT80 MCM5L4100AT60R2 MCM5L4100AT70R2 MCM5L4100AT80R2 MOTOROLA DRAM PACKAGE DIMENSIONS N PACKAGE 300 MIL SOJ CASE 822-03 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION A & B DO NOT INCLUDE MOLD PROTRUSION. MOLD PROTRUSION SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIM R TO BE DETERMINED AT DATUM -T-. 5. FOR LEAD IDENTIFICATION PURPOSES, PIN POSITIONS 6, 7, 8, 19, 20, & 21 ARE NOT USED. 6. 822-01 AND -02 OBSOLETE, NEW STANDARD 822-03. F 26 22 18 14 5 9 13 DETAIL Z N D 20 PL 1 0.18 (0.007) T M A S H BRK -AG M 0.18 (0.007) P L -BM E C K DETAIL Z MOTOROLA DRAM 0.10 (0.004) -T- SEATING PLANE R 0.25 (0.010) S RAD M T B S M T B S DIM A B C D E F G H K L M N P R S MILLIMETERS MIN MAX 17.02 17.27 7.74 7.50 3.75 3.26 0.50 0.39 2.48 2.24 0.81 0.67 1.27 BSC 0.50 -- 1.14 0.89 2.54 BSC 10 0 0.89 1.14 8.39 8.63 6.61 6.98 0.77 1.01 INCHES MIN MAX 0.670 0.680 0.295 0.305 0.128 0.148 0.015 0.020 0.088 0.098 0.026 0.032 0.050 BSC -- 0.020 0.035 0.045 0.100 BSC 0 10 0.035 0.045 0.330 0.340 0.260 0.275 0.030 0.040 MCM54100A*MCM5L4100A 19 T PACKAGE 300 MIL TSOP CASE 892-01 BASE METAL RAD V RAD T N EEEEE CCCC EEEEE CCCC EEEEE CCCC EEEEE CCCC EEEEE F W L J D K 0.008 (0.20) DETAIL A ROTATED 905 CW M T Z S SECTION B-B DETAIL A 26 22 18 14 NOTES: 1. DIMENSIONS AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.006 (0.15) PER SIDE. 4. DIMENSION D DOES NOT INCLUDE DAM BAR PROTRUSIONS. ALLOWABLE PROTRUSION IS 0.007 (0.18), TOTAL, IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. B B 1 5 B 9 13 -Y- A -ZC S 10X 0.008 (0.20) 0.004 (0.10) -T- R 4X M T Y S DIM A B C D F G J K L N R S T V W MILLIMETERS MIN MAX 17.05 17.25 7.52 7.72 -- 1.27 0.48 0.33 0.43 0.33 1.27 BSC 0.12 0.20 0.58 0.41 0.02 0.18 0.11 0.16 2.54 BSC 9.39 9.05 0.10 REF 0.10 REF 5 0 INCHES MIN MAX 0.671 0.679 0.296 0.304 -- 0.050 0.013 0.019 0.013 0.017 0.050 BSC 0.005 0.008 0.016 0.023 0.001 0.007 0.004 0.006 0.100 BSC 0.356 0.370 0.004 REF 0.004 REF 0 5 SEATING PLANE G 16X Motorola reserves the right to make changes without further notice to any products herein. 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Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 MFAX: RMFAX0@email.sps.mot.com - TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298 MCM54100A*MCM5L4100A 20 *MCM54100A/D* MCM54100A/D MOTOROLA DRAM