©1990 Burr-Brown Corporation PDS-1081E Printed in U.S.A. August, 1997
OPA177
FEATURES
●LOW OFFSET VOLTAGE: 25µV max
●LOW DRIFT: 0.3µV/°C
●HIGH OPEN-LOOP GAIN: 130dB min
●LOW QUIESCENT CURRENT: 1.5mA typ
●REPLACES INDUSTRY-STANDARD OP
AMPS: OP-07, OP-77, OP-177, AD707,
ETC.
APPLICATIONS
●PRECISION INSTRUMENTATION
●DATA ACQUISITION
●TEST EQUIPMENT
●BRIDGE AMPLIFIER
●THERMOCOUPLE AMPLIFIER
Precision
OPERATIONAL AMPLIFIER
14kΩ
500Ω
Trim
8
V+
7
Trim
1
+In
3
–In
2
V–
4
25Ω
30Ω
V
6
O
20µA
500Ω
DESCRIPTION
The OPA177 precision bipolar op amp feature very
low offset voltage and drift. Laser-trimmed offset,
drift and input bias current virtually eliminate the need
for costly external trimming. The high performance
and low cost make them ideally suited to a wide range
of precision instrumentation.
The low quiescent current of the OPA177 dramati-
cally reduce warm-up drift and errors due to thermo-
electric effects in input interconnections. It provides
an effective alternative to chopper-stabilized amplifi-
ers. The low noise of the OPA177 maintains accuracy.
OPA177 performance gradeouts are available. Pack-
aging options include 8-pin plastic DIP
and SO-8 surface-mount packages.
®
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
OPA177
OPA177
SBOS008
2
®
OPA177
OPA177 SPECIFICATIONS
At VS = ±15V, TA = +25°C, unless otherwise noted.
OPA177F OPA177G
PARAMETER CONDITION MIN TYP MAX MIN TYP MAX UNITS
OFFSET VOLTAGE
Input Offset Voltage 10 25 20 60 µV
Long-Term Input Offset(1) 0.3 0.4 µV/Mo
Voltage Stability
Offset Adjustment Range RP = 20kΩ±3✻mV
Power Supply Rejection Ratio VS = ±3V to ±18V 115 125 110 120 dB
INPUT BIAS CURRENT
Input Offset Current 0.3 1.5 ✻2.8 nA
Input Bias Current 0.5 ±2✻±2.8 nA
NOISE
Input Noise Voltage 1Hz to 100Hz(2) 85 150 ✻✻nVrms
Input Noise Current 1Hz to 100Hz 4.5 ✻pArms
INPUT IMPEDANCE
Input Resistance Differential Mode(3) 26 45 18.5 ✻MΩ
Common-Mode 200 ✻GΩ
INPUT VOLTAGE RANGE
Common-Mode Input Range(4) ±13 ±14 ✻✻ V
Common-Mode Rejection VCM = ±13V 130 140 115 ✻dB
OPEN-LOOP GAIN RL ≥ 2kΩ
Large Signal Voltage Gain VO = ±10V(5) 5110 12,000 2000 6000 V/mV
OUTPUT
Output Voltage Swing RL ≥ 10kΩ±13.5 ±14 ✻✻ V
R
L ≥ 2kΩ±12.5 ±13 ✻✻ V
R
L ≥ 1kΩ±12 ±12.5 ✻✻ V
Open-Loop Output Resistance 60 ✻Ω
FREQUENCY RESPONSE
Slew Rate RL ≥ 2kΩ0.1 0.3 ✻✻ V/µs
Closed-Loop Bandwidth G = +1 0.4 0.6 ✻✻ MHz
POWER SUPPLY
Power Consumption VS = ±15V, No Load 40 60 ✻✻ mW
VS = ±3V, No Load 3.5 4.5 ✻✻ mW
Supply Current VS = ±15V, No Load 1.3 2 ✻✻ mA
At VS = ±15V, –40°C ≤ TA ≤ +85°C, unless otherwise noted.
OFFSET VOLTAGE
Input Offset Voltage 15 40 20 100 µV
Average Input Offset 0.1 0.3 0.7 1.2 µV/°C
Voltage Drift
Power Supply Rejection Ratio VS = ±3V to ±18V 110 120 106 115 dB
INPUT BIAS CURRENT
Input Offset Current 0.5 2.2 ✻4.5 nA
Average Input Offset Current 1.5 40 ✻85 pA/°C
Drift(6)
Input Bias Current 0.5 ±4✻±6nA
Average Input Bias Current 8 40 15 60 pA/°C
Drift(6)
INPUT VOLTAGE RANGE
Common-Mode Input Range ±13 ±13.5 ✻✻ V
Common-Mode Rejection VCM = ±13V 120 140 110 ✻dB
OPEN-LOOP GAIN
Large Signal Voltage Gain RL≥2kΩ, VO=±10V 2000 6000 1000 4000 V/mV
OUTPUT
Output Voltage Swing RL ≥ 2kΩ±12 ±13 ✻✻ V
POWER SUPPLY
Power Consumption VS=±15V, No Load 60 75 ✻✻ mW
Supply Current VS=±15V, No Load 2 25 ✻✻ mA
✻ Same as specification for product to left.
NOTES: (1) Long-Term Input Offset Voltage Stability refers to the averaged trend line of VOS vs time over extended periods after the first 30 days of operation. Excluding
the initial hour of operation, changes in VOS during the first 30 operating days are typically less than 2µV. (2) Sample tested. (3) Guaranteed by design. (4) Guaranteed
by CMRR test condition. (5) To insure high open-loop gain throughout the ±10V output range, AOL is tested at –10V ≤ VO ≤ 0V, 0V ≤ VO ≤ +10V, and –10V ≤ VO ≤ +10V.
(6) Guaranteed by end-point limits.
3
®
OPA177
The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumes
no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject to change
without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrant
any BURR-BROWN product for use in life support devices and/or systems.
PIN CONFIGURATION
Top View DIP/SOIC
ABSOLUTE MAXIMUM RATINGS
ELECTROSTATIC
DISCHARGE SENSITIVITY
Any integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. ESD can cause damage ranging
from subtle performance degradation to complete device
failure. Precision integrated circuits may be more suscep-
tible to damage because very small parametric changes
could cause the device not to meet published specifications.
Burr-Brown’s standard ESD test method consists of five
1000V positive and negative discharges (100pF in series
with 1.5kΩ) applied to each pin.
Failure to observe proper handling procedures could result
in small changes to the OPA177’s input bias current.
1
2
3
4
8
7
6
5
Offset Trim
–In
+In
V–
Offset Trim
V+
V
No Internal Connection
O
Power Supply Voltage ....................................................................... ±22V
Differential Input Voltage ................................................................... ±30V
Input Voltage ....................................................................................... ±VS
Output Short Circuit ................................................................. Continuous
Operating Temperature:
Plastic DIP (P), SO-8 (S).............................................. –40°C to +85°C
θ
JA (PDIP) ................................................................................. 100°C/W
θ
JA (SOIC)................................................................................. 160°C/W
Storage Temperature:
Plastic DIP (P), SO-8 (S)............................................ –65°C to +125°C
Junction Temperature.................................................................... +150°C
Lead Temperature (soldering, 10s) P packages ........................... +300°C
(soldering, 3s) S package............................... +260°C
PACKAGE
DRAWING TEMPERATURE
PRODUCT PACKAGE NUMBER(1) RANGE
OPA177FP 8-Pin Plastic DIP 006 –40°C to +85°C
OPA177GP 8-Pin Plastic DIP 006 –40°C to +85°C
OPA177GS SO-8 Surface-Mount 182 –40°C to +85°C
NOTE: (1) For detailed drawing and dimension table, please see end of data
sheet, or Appendix C of Burr-Brown IC Data Book.
PACKAGE/ORDERING INFORMATION
4
®
OPA177
TYPICAL PERFORMANCE CURVES
At TA = +25°C, VS = ±15V, unless otherwise noted.
10 30 50 700204060
30
25
20
15
10
5
0
Absolute Change in Input
Offset Voltage (µV)
Time (s)
OFFSET VOLTAGE CHANGE
DUE TO THERMAL SHOCK
80
Device Immersed in 70°C Inert Liquid
Plastic DIP
CLOSED-LOOP RESPONSE vs FREQUENCY
100
80
60
40
20
0
–20 10 100 1k 10k 100k 1M 10M
Closed-Loop Gain (dB)
Frequency (Hz)
3
2
1
0
–1
–2
–3
Offset Voltage Change (µV)
0 30 60 90 120
Time from Power Supply Turn-On (s)
WARM-UP OFFSET VOLTAGE DRIFT
15 45 75 105
17.5
15
12.5
10
7.5
5
2.5
0
V
OUT
(V)
0 6 12 18 24 30 36
I
OUT
(mA)
MAXIMUM V
OUT
vs I
OUT
(Positive Swing)
V
S
= ±18V
V
S
= ±15V
V
S
= ±12V
V
S
= ±15V
–17.5
–15
–12.5
–10
–7.5
–5
–2.5
0
V
OUT
(V)
0 –2 –4 –6 –8 –10 –12
–I
OUT
(mA)
MAXIMUM V
OUT
vs I
OUT
(Negative Swing)
V
S
= ±18V
V
S
= ±15V
V
S
= ±12V
V
S
= ±15V
1
0.1
0.01
0.001
THD + N (%)
1k 10k 100k
Frequency (Hz)
TOTAL HARMONIC DISTORTION AND NOISE
vs FREQUENCY
A = 20dB, 3Vrms, 10kΩ load
30kHz low pass filtered
Inverting
Noninverting
5
®
OPA177
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
150
140
130
120
110
100
90
80
CMRR (dB)
1 10 100 1k 10k 100k
Frequency (Hz)
CMRR vs FREQUENCY
OPEN-LOOP GAIN/PHASE vs FREQUENCY
160
140
120
100
80
60
40
20
0
Open-Loop Gain (dB)
0.01 1 10 100 1k 10k 100k 1M0.1
Frequency (Hz)
0
45
90
135
180
Phase Shift (Degrees)
Phase
Gain
2
1
0
–1
–2–40 –15 10 35 60 85
Temperature (°C)
INPUT BIAS AND INPUT OFFSET CURRENT
vs TEMPERATURE
Input Bias and Input Offset Current (nA)
I
B
I
OS
150
130
110
90
70
50
Power Supply Rejection (dB)
1 10 100 1k 10k0.1 Frequency (Hz)
POWER SUPPLY REJECTION
vs FREQUENCY
1k
100
10
1
Input Noise Voltage (nV/√Hz)
1
Frequency (Hz)
INPUT NOISE VOLTAGE DENSITY vs FREQUENCY
10 100 1k 10k
R = 0
S
R = R = 200k
Thermal noise of
source resistors
included.
S1 S2 Ω
10
1
0.1
0.01
RMS Noise (µV)
100 1k 10k 100k
Bandwidth (Hz)
TOTAL NOISE vs BANDWIDTH
(0.1Hz to Frequency Indicated)
6
®
OPA177
TYPICAL PERFORMANCE CURVES (CONT)
At TA = +25°C, VS = ±15V, unless otherwise noted.
40
35
30
25
20
15
Output Short-Circuit Current (mA)
01234
Time from Output Being Shorted (min)
OUTPUT SHORT-CIRCUIT CURRENT vs TIME
SC
I –
SC
I +
20
15
10
5
0
Maximum Output (V)
100 10k
Load Resistance to Ground ( )
MAXIMUM OUTPUT VOLTAGE vs LOAD RESISTANCE
1k
Ω
Negative
Output
Positive
Output
32
28
24
20
16
12
8
4
0
Peak-to-Peak Amplitude (V)
1k 10k 100k 1M
Frequency (Hz)
MAXIMUM OUTPUT SWING vs FREQUENCY
G = +1
R = 2k
L
Ω
100
10
1
Power Consumption (mW)
0 10203040
Total Supply Voltage (V)
POWER CONSUMPTION vs POWER SUPPLY
7
®
OPA177
APPLICATIONS INFORMATION
The OPA177 is unity-gain stable, making it easy to use and
free from oscillations in the widest range of circuitry. Ap-
plications with noisy or high impedance power supply lines
may require decoupling capacitors close to the device pins.
In most cases 0.1µF ceramic capacitors are adequate.
The OPA177 has very low offset voltage and drift. To
achieve highest performance, circuit layout and mechanical
conditions must be optimized. Offset voltage and drift can
be degraded by small thermoelectric potentials at the op amp
inputs. Connections of dissimilar metals will generate ther-
mal potential which can mask the ultimate performance of
the OPA177. These thermal potentials can be made to cancel
by assuring that they are equal in both input terminals.
1. Keep connections made to the two input terminals close
together.
2. Locate heat sources as far as possible from the critical
input circuitry.
3. Shield the op amp and input circuitry from air currents
such as cooling fans.
OFFSET VOLTAGE ADJUSTMENT
The OPA177 has been laser-trimmed for low offset voltage
and drift so most circuits will not require external adjust-
ment. Figure 1 shows the optional connection of an external
potentiometer to adjust offset voltage. This adjustment should
not be used to compensate for offsets created elsewhere in a
system since this can introduce excessive temperature drift.
INPUT PROTECTION
The inputs of the OPA177 are protected with 500Ω series
input resistors and diode clamps as shown in the simplified
circuit diagram. The inputs can withstand ±30V differential
inputs without damage. The protection diodes will, of course,
conduct current when the inputs are overdriven. This may
disturb the slewing behavior of unity-gain follower applica-
tions, but will not damage the op amp.
NOISE PERFORMANCE
The noise performance of the OPA177 is optimized for
circuit impedances in the range of 2kΩ to 50kΩ. Total noise
in an application is a combination of the op amp’s input
voltage noise and input bias current noise reacting with
circuit impedances. For applications with higher source
impedance, the OPA627 FET-input op amp will generally
provide lower noise. For very low impedance applications,
the OPA27 will provide lower noise.
INPUT BIAS CURRENT CANCELLATION
The input stage base current of the OPA177 is internally
compensated with an equal and opposite cancellation cur-
rent. The resulting input bias current is the difference
between the input stage base current and the cancellation
current. This residual input bias current can be positive or
negative.
When the bias current is cancelled in this manner, the input
bias current and input offset current are approximately the
same magnitude. As a result, it is not necessary to balance
the DC resistance seen at the two input terminals (Figure 2).
A resistor added to balance the input resistances may actu-
ally increase offset and noise.
FIGURE 1. Optional Offset Nulling Circuit.
OPA177 V
2
3
18
Trim Range is approximately ±3.0mV
V+
20kΩ
OUT
V
IN
Op Amp
(a)
R
B
OPA177
(b)
No bias current
cancellation resistor needed
Conventional op amp with
external bias current
cancellation resistor.
OPA177 with no external
bias current cancellation
resistor.
= R
2
|| R
1
R
2
R
1
R
2
R
1
FIGURE 2. Input Bias Current Cancellation.
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
OPA177FP ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA177FPG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA177GP ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA177GPG4 ACTIVE PDIP P 8 50 Green (RoHS &
no Sb/Br) CU NIPDAU N / A for Pkg Type
OPA177GS ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA177GS/2K5 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA177GS/2K5E4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA177GS/2K5G4 ACTIVE SOIC D 8 2500 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA177GSE4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
OPA177GSG4 ACTIVE SOIC D 8 75 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Feb-2009
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
OPA177GS/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA177GS/2K5 SOIC D 8 2500 346.0 346.0 29.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,and other changes to its products and services at any time and to discontinue any product or service without notice. Customers shouldobtain the latest relevant information before placing orders and should verify that such information is current and complete. All products aresold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standardwarranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except wheremandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products andapplications using TI components. To minimize the risks associated with customer products and applications, customers should provideadequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right,or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Informationpublished by TI regarding third-party products or services does not constitute a license from TI to use such products or services or awarranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectualproperty of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompaniedby all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptivebusiness practice. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additionalrestrictions.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids allexpress and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is notresponsible or liable for any such statements.TI products are not authorized for use in safety-critical applications (such as life support) where a failure of the TI product would reasonablybe expected to cause severe personal injury or death, unless officers of the parties have executed an agreement specifically governingsuch use. Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications, andacknowledge and agree that they are solely responsible for all legal, regulatory and safety-related requirements concerning their productsand any use of TI products in such safety-critical applications, notwithstanding any applications-related information or support that may beprovided by TI. Further, Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products insuch safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products arespecifically designated by TI as military-grade or "enhanced plastic." Only products designated by TI as military-grade meet militaryspecifications. Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely atthe Buyer's risk, and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use.TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products aredesignated by TI as compliant with ISO/TS 16949 requirements. Buyers acknowledge and agree that, if they use any non-designatedproducts in automotive applications, TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers amplifier.ti.com Audio www.ti.com/audioData Converters dataconverter.ti.com Automotive www.ti.com/automotiveDLP® Products www.dlp.com Broadband www.ti.com/broadbandDSP dsp.ti.com Digital Control www.ti.com/digitalcontrolClocks and Timers www.ti.com/clocks Medical www.ti.com/medicalInterface interface.ti.com Military www.ti.com/militaryLogic logic.ti.com Optical Networking www.ti.com/opticalnetworkPower Mgmt power.ti.com Security www.ti.com/securityMicrocontrollers microcontroller.ti.com Telephony www.ti.com/telephonyRFID www.ti-rfid.com Video & Imaging www.ti.com/videoRF/IF and ZigBee® Solutions www.ti.com/lprf Wireless www.ti.com/wireless
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2009, Texas Instruments Incorporated
