TMXF281553BAL-3C-DB - Agere Systems, Inc.

Data Sheet

June 2002

TMXF28155 Supermapper

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

1 Feat ures

■Versatile IC supports 155/51 Mbits/s SONET/SDH

interface solutions for T3, DS2, T1/E1/J1, and DS0/

E0/J0 applications.

■Implementation supports both linear (1 + 1, unpro-

tected) and ring (U PS R) networ k topolog ies .

■Provides full termination of up to 21 E1, 28 T1, or

28 J1.

■Low-power 3.3 V supply.

■–40 °C to +85 °C industrial temperature range.

■456-pin ball grid array (PBGA) package, 35 mm2 with

a 1.27 mm ball pitch.

■Complies with Telcordia ™, ITU, ANSI ®, ETSI, and

Japanese TTC standards: GR-253-CORE, GR-499,

(ATT) TR-6241 1, ITU-T G.707, G.704, G.706, G.783,

G.962, G.964, G.965, Q.542, T1.105, JT-G704,

JT-G706, JT-G707, JT-I431-a, ETS 300 417-1-1,

ETS 300 011, T1.107, T1.404.

1.1 SONET/SDH Interface

■Termination of a single 155 Mbits/s STS-3/STM-1 or

single 51 Mbits/s STS-1/STM-0.

■Built-in clock and data recovery circuit at

155 Mbits/s STS-3/STM-1 interface (can be dese-

lected if external clock recovery is provided).

■Supports overhead processing for all transport and

path overhead bytes.

■Optional insertion and extraction of overhead bytes

via a serial transport overhead access channel. Con-

figurable as dedicated DCC channels.

■Software-controlled linear 1 + 1 protection via dedi-

cated interface to protection card.

■Full path termination and SPE extraction/insertion.

■SON ET/SDH compliant condition and alarm report-

ing.

■Built-in diagnostic loopback modes.

■8 kHz line frame sync output.

1.2 STS/STM Pointer Interpreter

■Interprets STS/AU/TU-3 pointers.

■Synchronizes 8 kHz frame and 2 kHz superframe to

system/shelf timing reference by setting the transmit

STS-3/STM-1 pointers to a fixed value of 522.

■Monitors/terminates SPE path overhead.

1.3 Telecom Bus Interface

■Telecom bus interface to mate devices including

clock, data[8 ], pari ty, SPE-, J0-, J1-, and V1 tim ing

indicator.

■Line and path RDI and REI signals passed to mate

devices.

■Three Supermapper devices, two configured as mate

devices, provide full termination of an

STS-3/STM-1. A three-chip solution to terminate

84 DS1s/J1s or 63 E1s.

1.4 VT Termination/Generation (x28/x21)

■Monitors/terminates VT path overhead for

28 VT1.5/TU-11 or 21 VT2/TU-12.

■Synchronizes VT/TU SPE to system/shelf timing ref-

erence by setting the transmit VT/TU pointers to

fixed values for asynchronous mapping or by dynam-

ically changing the transmit VT/TU pointers for byte

synchronous mapping.

■Fixed pointer generation in transmit side for asyn-

chronous mapping.

■Dynamic pointer generation in transmit side for byte-

synchronous mapping.

1.5 Mapping/Multiplex ing M odes (x28/x21)

■Maps DS3 clear channel or framed signal into STS-1

or TUG-3.

■Maps T1/E1/J1 into VT/TU (including DS1 into

TU-12).

■Supports asynchronous, byte-synchronous, and bit-

synchronous mapping.

2Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

1 Features (continued)

■Supports UPSR applications via the dedicated ring

interface and an external tributary selector.

■Supports all valid T1/E1/J1 multiplexing structures

into STS-1 and STS-3/STM-1:

— STS-3/STS-1/SPE/VTG/VTx

— STM-1/AU-3/TUG-2/TU-1x/VC-1x

— STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x

■Allows grooming of VTs/TUs in granularity of TUG-2s

within the STS-3/STM-1 signal.

■Supports J2 trace identifier monitoring/insertion.

■Configurable VT/TU slot selection for DS1, E1, and

J1 insertion and drop.

■Automatic receive monitor functions include VT/TU

RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.

■Complies with GR-253-CORE, GR-499, ITU-T

G.707, G.704, G.783, T1.105, JT-G707, ETS 300

417-1-1.

1.6 M13 Features

■Configurable multiplexer/demultiplexer for 28 DS1

signals, 21 E1 signals, or 7 DS2 signals to/from a

DS3 signal.

■Operates in either M23 or C-bit parity mode.

■Provisionable time-slot selection for DS1, E1, and

DS2 insertion or drop.

■Full alarm monitoring and generation (LOS, BPV,

EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit

parity er rors , FEBE ) .

■HDLC transmitter with 128-byte data buffer and

HDLC receiver with 128-byte data FIFO for the C-bit

parity path maintenance data link.

■DS3, DS2, DS1, and E1 loopback and loopback

request generation.

■Complies with T1.102, T1.107, T1.231, T1.403,

T1.404, GR 499, G.747, and G.775.

1.7 DS3/DS2/DS1/E1 Cross Connect

■Highly configurable interconnect for up to 28 DS1 or

21 E1 signals to/from the framer, external pins, M13,

or VT mappers.

■Supports up to seven DS2 signals to/from the exter-

nal pins or M13.

■Sources may be broadcast, looped back, or routed

to/from a test-pattern generator or monitor.

■Any DS1 or E1 channel may be routed through the

jitter attenuator.

■DS3 may be configured for the M13 to interconnect

with the SPE, or for the external I/O to interconnect

with the M13 or SPE.

1.8 Jitter Attenuation

■PLL-free receive operation using built-in digital jitter

attenuator (in VT/VC mode or M13 mode).

■Configurable to meet jitter and MTIE requirements.

1.9 PDH Interfaces

■One DS3, 7x DS2.

■x28/x21 framed or unframed DS1 or E1 interfaces.

■One additional dedicated protection channel for

DS2/DS1/E1.

1.10 T1/E1/J1 Framin g Fe atures (x28/x21)

■x28/x21 T1 /E1 /J 1 chan nel s.

■Line coding: B8ZS, HDB3, ZCS, AMI, and

CMI (JJ20-11).

■T1 framing modes: ESF, D4, SLC ®-96, T1 DM DDS,

and SF (Ft only).

■E1 framing: G.704 basic and CRC-4 multiframe con-

sistent with G.706.

■J1 framing modes: JESF (Japan).

■Supports T1 and E1 unframed and transparent trans-

mission format.

■T1 signaling modes: transparent; register and sys-

tem access for ESF 2-state, 4-state, and 16-state;

D4 2-state, 4-state, and 16-state; SLC-96 2-state,

4-state, and 16-state; J-ESF handling groups main-

tenance and signaling; VT 1.5 SPE 2-state, 4-state,

16-state.

■E1 signaling modes: transparent; register and sys-

tem access for entire TS16 multiframe structure as

per ITU G.732.

■Signaling debounce and change of state interrupt.

■V5.2 Sa7 processing.

3Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

1 Features (continued)

■Alarm reporting and performance monitoring per

AT&T ®, ANSI, ITU- T, and ETS I stand ards .

■Facility data link features:

— HDLC or transparent access for either ESF or

DDS + FDL frame formats.

— Regis ter /stack access for SLC-96 transmit and re-

ceive data.

— Extended superframe (ESF): automatic transmis-

sion of the ESF performance report messages

(PRM). Automatic transmission of the ANSI

T1.403 ESF performance report messages. Auto-

matic detection and transmission of the ANSI

T1.403 ESF FDL bit-oriented codes.

— Register/stack access for all CEPT Sa bits trans-

mit and receive data.

■HDLC features:

— HDLC or transparent mode.

— Programmable logical channel assignment: any

time sl ot, an y bit f or I SDN D- chan n el, al so inse rt s/

extracts C-channels for V5.1, V5.2 interfaces.

— 64 logical channels in both transmit and receive di-

rection (any framing form at).

— Maximum channel data rate: 64 kbits/s.

— Minimum channel data rate: 4 kbits/s (DS1-FDL or

E1 Sa bit).

— 128-byte FIFO per channel in both transmit and re-

ceive direction.

— Tx to Rx loopback supported.

■System interfaces:

— Concentration highway interface: single clock and

frame sync signals; programmable clock rates at

2.048 MHz, 4.096 MHz, 8.192 MHz, and

16.384 MHz; programmable data rates at

2.048 Mbits/s, 4.096 Mbits/s, and 8.192 Mbits/s;

programmable clock edges and bit/byte offsets.

— Parallel system bus interface at 19.44 MHz for

data and signaling: single clock and frame sync

signals.

— Time-division multiplex data rate serial interface at

1.544 MHz or 2.048 MHz. Twenty-eight receive

data, clock, and frame sync signals. Twenty-eight

transmit data signals with a global clock and frame

sync.

— Network serial multiplexed interface minimal pin

count serial interface at 51.84 MHz optimized for

data and IMA applications.

1.11 System Test and Maintena nce

■A variety of loopback modes implemented on

SONET/SDH side, as well as on framer level.

■Built-in test pattern generator and monitor config-

urable for simultaneously testing E1, DS1, DS2, and

DS3 (one channel each).

1.12 Microprocessor Interface

■20-bit address and 16-bit data interface with 16 MHz

to 60 MHz read and write access.

■Compatible with most industry-standard processors.

1.13 Chip Testing an d Maintenance

■IEEE ® 1149.1 JTAG boundary scan.

1.14 Interface to Other Agere Devices

Seamless interface to the following Agere Systems’

device:

■TADM042G5.

4Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

Agere Sy st ems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

Features ...................................................................................................................................................................1

Product Description .............. ....... ...... .................... ...... ....... ...... ...... ....... ...... ....... ...... .............................................6

Preface .....................................................................................................................................................................6

Interface Specifications .......................................................................................................................................10

Pin Information .......................................................................................................................................................10

Electrical Characteristics ........................................................................................................................................35

Timing Characteristics ............................................................................................................................................39

Ordering Information ...............................................................................................................................................63

Register Description ............................................................................................................................................64

Microprocessor Interface and Global Control and Status Registers .......................................................................64

TMUX Registers .....................................................................................................................................................77

SPE Mapper Regist ers ................... ................... ....... ...... ....... ...... ................... ....... ...... ....... ..................................135

VT/TU Mapper Registers ... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ..................................157

M13/M23 MUX/DeMUX Registers ........................................................................................................................200

28-Channel Framer Registers ..............................................................................................................................242

Cross Connect (XC) Registers .............................................................................................................................326

Digital Jitter Attenuation Controller Registers .......................................................................................................336

Test-Pattern Generation/Detection Registers .......................................................................................................342

Functional Descriptions .....................................................................................................................................360

Microprocessor Interface Functional Description .................................................................................................360

TMUX Functional Description ...............................................................................................................................365

SPE Mapper Functional Description .....................................................................................................................402

VT/TU Mapper Functional Description .................................................................................................................431

M13/M23 MUX/DeMUX Block Functional Description ..........................................................................................462

28-Channel Framer Block Functional Description ................................................................................................482

Cross Connect (XC) Block Functional Description ...............................................................................................549

Digital Jitter Attenuation Controller Functional Description ..................................................................................577

Test-Pattern Generation/Detection Functional Description ..................................................................................581

Philosophies .........................................................................................................................................................589

Applications ........................................................................................................................................................594

Application Scripts ................................................................................................................................................620

Superframer .... ............ ............. ............. ............. ............. ....... ............ ............. ............. .........................................782

Change History ...................................................................................................................................................783

6Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

Product Description

2 Preface

Table of Con t ents

Contents Page

2 Preface ............................................................................................................................................. ....... ...... ..... 6

2.1 Major Categories............................................................................................................................................7

2.2 Naming Convention for Registers and Parameters........................................................................................7

2.3 Overview ........................................................................................................................................................8

Figures Page

Figure 1. Functional Diagram of Supermapper .........................................................................................................8

7Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

2 Preface (continued)

The objective of this data sheet is to define the func-

tionality of the Supermapper for hardware and software

developers. The information contained in this data

sheet is preliminary, and may change without notice;

the reader must therefore ascertain that the latest ver-

sion is used when a product is under development.

The latest version of this data sheet can be accessed

at:

http://www.agere.com/enterprise_metro_access/

mappers_muxes.html

2.1 Major Categories

This data sheet is divided into six major categories with

subsections as follows:

■Features

■Product Description:

— Features

— Preface

— Overview

■Interface Specifications:

— Pin Information

— Electrical Characteristics

— Timing Characteristics

— Ordering Information

■Register Descriptions:

— Microprocessor Interface Registers

— TMUX Registers

— SPE Mapper Registers

— VT/UT Mapper Registers

— M13/M23 MUX/deM UX Regi st er s

— 28-Channel Framer Registers

— Cross Connect (XC) Registers

— Digital Jitter Attenuation Registers

— Test Pattern Generation/Detection Registers

■Functional Descriptions:

— Microprocessor Interface Description

— TMUX Registers Description

— SPE Mapper Registers Description

— VT/UT Mapper Registers Description

— M13/M23 MUX/deMUX Registers Description

— 28-Channel Framer Registers Description

— Cross Connect (XC) Registers Description

— Digital Jitter Attenuation Registers Description

— Test Pattern Generation/Detection Registers De-

scription

■Applications:

— Application Block Diagrams and Descriptions

2.2 Naming Convention for Registers and

Parameters

There are many provisioning registers for controlling

the Supermapper . A naming convention for all registers

and parameters (bit names) is followed throughout this

data sheet. A prefix is attached to the base name of

each register or parameter, depending on which func-

tional section the register or parameter is associated

with:

■SMPR_, for the Microprocessor Interface

■TMUX_, for the TMUX

■SPE_, for the SPE Mapper

■VT_, for the VT/VC Mapper

■M13_, for the M13/M23 MUX/deMUX

■FRM_, for the 28-Channel Framer

■XC_, for the Cross Connect

■DJA_, for the Digital Jitter Attenuator

■TPG_ and TPM_, for the Test-Pattern Generator/

Detection

A suffix is appended to the base name of three com-

mon parameters:

■_IS, for interrupt signal.

■_IM, for interrupt mask.

■_SWRS, for software reset.

8Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

2 Preface (continued)

2.3 Overview

The SONET/SDH Supermapper device integrates the SONET/SDH line, path, and tributary termination functions

with M13 multiplex functions and the primary rate framing function. The Supermapper is designed to drive an

OC-3/STM-1 optical signal directly or to allow for modular growth in terminal or add/drop applications.

The device provides a versatile interface for all STS-3/STM-1 and STS-1 termination applications in point-to-point

scenarios and for ring applications. This chip can be used in tributary shelf applications for up to 28 T1 or J1 or 21

E1 line cards, providing all possible mappings into SONET/SDH, and it can be used for DS3/DS2 applications.

Because of the flexibility of the mappings, software upgrades from M13 mapped connections to VT/TU mapped

connections are possible.

A single Supermapper is capable of processing the aggregate bandwidth of one STS-1 or DS3. By communicating

to two other mate devices via the telecom bus interface, the Supermapper is capable of terminating a full

STS-3/STM-1 signal.

Figure 1. Functional Diagram of Supermapper

M13

MUX

TMUX

STS3/

STM1/

STS1/

AU-3

FRM

x28/x21

DS1/J1/E1

x28/x21

VT/TU

VTMPR

DS1/J1/E1

DS2

DS3

TPG/TPM

x28/x21

DS1/E1

DJA

CDR

SPEMPR

STS1/AU3/AU4

MPU

Int er f ace an d Control

Switching Modes:

PSB - x28/x21 DS1/J1/E1

x672 DS0/E 0

CHI - x672 D S0/ E0

Transport Modes:

DS1/J1/E1 (X29) - x28/x21 + prot.

DS2 - x7 + prot.

NSMI Modes:

DS1/J1/E1 x28/x21

DS3 - x1

STS1 - x1

(x1) DS3

Multifunction System I/O

155.52 Mb/STS-3/STM-1

51.84 Mb/STS-1/AU-3

MSP 1 + 1

155.52 Mb/STS-3/STM-1

51.84 Mb/STS-1/AU-3

Clock/Sync

LOPOH

(Supports UPSR )

TOAC POAC

MPU IF

DS1/E1/DS2

AIS Clks

TCB and TDL

RCB and RDL

148

30 DS3 PLL IF

8PLL Interface

Telecom Bus

(To two a dditional Supermappers)

High-Speed IF

System

Interfaces

9Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

10 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

Interface Spe cific ations

3 Pin In fo rm a tion

Table of Con t ents

Contents Page

3 Pin Information ..................................................................................................................................................10

3.1 456-Pin PBGA Pin Diagram .........................................................................................................................11

3.2 Pin Assignments...........................................................................................................................................11

3.3 Pin Descriptions ...........................................................................................................................................17

3.3.1 High-Speed I/O Pin Descriptions ...................................................................................................... 17

3.3.2 Protection Switch I/O Pin Description ............................................................................................... 18

3.3.3 Telecom Bus (Low-Speed I/O) Pin Description ................................................................................ 18

3.3.4 TOAC and POAC .............................................................................................................................. 21

3.3.5 Miscellaneous Signals ...................................................................................................................... 22

3.3.6 DS3 Port ........................................................................................................................................... 22

3.3.7 M13 Multiplexer/Demultiplexer Receive Section ............................................................................... 24

3.3.8 Low-Order Path Overhead Access Channel ..................................................................................... 25

3.3.9 Framer PLL ....................................................................................................................................... 29

3.3.10 Test Pins ..... ...... .................... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ............................. 32

3.4 Outline Diagram ...........................................................................................................................................34

3.4.1 456-Pin PBGA .................................................................................................................................. 34

Figures Page

Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)..........................................................................................11

Figure 3. Protection Switch......................................................................................................................................18

Figure 4. DS1/E1 to DXC Block Diagram................................................................................................................25

Tables Page

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order........................................................................11

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name................................................................................14

Table 3. High-Speed I/O Pin Descriptions...............................................................................................................17

Table 4. Protection Switch I/O Pin Description ........................................................................................................18

Table 5. Telecom Bus (Low-Speed I/O) Pin Description..........................................................................................19

Table 6. TOAC and POAC........ .................... ...... ....... ...... ....... ................... ...... ....... ...... ...........................................21

Table 7. Miscellaneous Signals ...............................................................................................................................22

Table 8. DS3 Port ....................................................................................................................................................23

Table 9. DS3 Port, C-Bit, and Datalink Access........................................................................................................24

Table 10. M13 Multiplexer/Demultiplexer Receive Section......................................................................................24

Table 11. Low-Order Path Overhead Access Channel............................................................................................25

Table 12. Multifunction System Interface Transmit Path Direction ..........................................................................26

Table 13. Framer PLL..............................................................................................................................................29

Table 14. Microprocessor Interfaces........................................................................................................................30

Table 15. General-Purpose Interface.......................................................................................................................31

Table 16. Test Pins ..................................................................................................................................................32

Table 17. CDR Power..............................................................................................................................................32

Table 18. LVDS Control Pins ...................................................................................................................................32

11Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

3.1 456-Pin PBGA Pin Diagram

5-8931(F)

Figure 2. Pin Diagram of 456-Pin PBGA (Bottom View)

3.2 Pin Assignments

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 VDD A21 VSS B15 LINETXDATA2 C9 LINERXSYNC24

A2 VSS A22 VDD B16 LINETXSYNC4 C10 LINERXCLK25

A3 LINERXDATA17 A23 LINETXSYNC12 B17 LINETXSYNC5 C11 LINERXCLK26

A4 LINERXDATA18 A24 LINETXSYNC13 B18 LINETXSYNC6 C12 LINERXCLK27

A5 VDD A25 VSS B19 LINETXCLK7 C13 LINERXDATA28

A6 VSS A26 VDD B20 LINETXDATA8 C14 LINETXSYNC2

A7 LINERXDATA21 B1 VSS B21 LINETXSYNC10 C15 LINETXCLK3

A8 LINERXSYNC23 B2 LINERXCLK15 B22 LINETXDATA10 C16 LINETXCLK4

A9 LINERXCLK24 B3 LINERXSYNC18 B23 LINETXDATA11 C17 LINETXCLK5

A10 VDD B4 LINERXSYNC19 B24 LINETXDATA12 C18 LINETXDATA6

A11 VSS B5 LINERXSYNC20 B25 LINETXCLK13 C19 LINETXSYNC8

A12 LINERXDATA27 B6 LINERXDATA20 B26 VSS C20 LINETXCLK9

A13 LINERXSYNC29 B7 LINERXSYNC22 C1 LINERXSYNC15 C21 LINETXCLK10

A14 LINETXDATA1 B8 LINERXCLK23 C2 LINERXDATA14 C22 LINETXCLK11

A15 LINETXSYNC3 B9 LINERXDATA24 C3 LINERXCLK17 C23 LINETXCLK12

A16 VSS B10 LINERXDATA25 C4 LINERXCLK18 C24 LINETXCLK14

A17 VDD B11 LINERXDATA26 C5 LINERXCLK19 C25 LINETXSYNC15

A18 LINETXCLK6 B12 LINERXSYNC28 C6 LINERXCLK20 C26 LINETXDATA14

A19 LINETXDATA7 B13 LINERXCLK29 C7 LINERXCLK21 D1 LINERXSYNC14

A20 LINETXSYNC9 B14 LINETXCLK1 C8 LINERXDATA22 D2 LINERXDATA13

BALL

CORNER

12 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin S ignal Name

D3 LINERXCLK14 E21 LINETXDATA13 J25 LINETXDATA21 N1 LINERXDATA3

D4 VSS E22 VDD J26 LINETXCLK21 N2 LINERXCLK3

D5 LINERXDATA19 E23 LINETXDATA16 K1 VDD N3 LINERXSYNC4

D6 LINERXSYNC21 E24 LINETXCLK16 K2 LINERXSYNC7 N4 LINERXSYNC3

D7 LINERXCLK22 E25 LINETXSYNC17 K3 LINERXCLK7 N5 SCAN_EN

D8 LINERXDATA23 E26 VDD K4 LINERXDATA6 N11 VSS

D9 LINERXSYNC25 F1 VSS K5 LINERXSYNC16 N12 VSS

D10 LINERXSYNC26 F2 LINERXSYNC12 K22 DS3NEGDATAIN N13 VSS

D11 LINERXSYNC27 F3 LINERXCLK12 K23 LINETXSYNC23 N14 VSS

D12 LINERXCLK28 F4 LINERXDATA11 K24 LINETXCLK22 N15 VSS

D13 LINERXDATA29 F5 LINERXDATA15 K25 LINETXDATA22 N16 VSS

D14 LINETXSYNC1 F22 LINETXSYNC14 K26 VDD N22 DS3DATAOUTCLK

D15 LINETXCLK2 F23 LINETXSYNC18 L1 VSS N23 LINETXDATA26

D16 LINETXDATA3 F24 LINETXCLK17 L2 LINERXSYNC6 N24 LINETXDATA25

D17 LINETXDATA4 F25 LINETXDATA17 L3 LINERXCLK6 N25 LINETXCLK26

D18 LINETXDATA5 F26 VSS L4 LINERXDATA5 N26 LINETXSYNC26

D19 LINETXSYNC7 G1 LINERXSYNC11 L5 VDD P1 LINERXSYNC2

D20 LINETXCLK8 G2 LINERXDATA10 L11 VSS P2 LINERXCLK2

D21 LINETXDATA9 G3 LINERXCLK11 L12 VSS P3 LINERXDATA1

D22 LINETXSYNC11 G4 LINERXCLK10 L13 VSS P4 LINERXDATA2

D23 VSS G5 VSS L14 VSS P5 IDDQ

D24 LINETXCLK15 G22 VSS L15 VSS P11 VSS

D25 LINETXSYNC16 G23 LINETXCLK19 L16 VSS P12 VSS

D26 LINETXDATA15 G24 LINETXCLK18 L22 VDD P13 VSS

E1 VDD G25 LINETXSYNC19 L23 LINETXSYNC24 P14 VSS

E2 LINERXDATA12 G26 LINETXDATA18 L24 LINETXCLK23 P15 VSS

E3 LINERXCLK13 H1 LINERXDATA9 L25 LINETXDATA23 P16 VSS

E4 LINERXSYNC13 H2 LINERXCLK9 L26 VSS P22 DS3NEGDATAOUT

E5 VDD H3 LINERXSYNC10 M1 LINERXSYNC5 P23 LINETXSYNC27

E6 LINERXSYNC17 H4 LINERXSYNC9 M2 LINERXDATA4 P24 LINETXSYNC28

E7 VSS H5 LINERXDATA16 M3 LINERXCLK5 P25 LINETXCLK27

E8 TDLDATA H22 RDLDATA M4 LINERXCLK4 P26 LINETXDATA27

E9 TDLCLK H23 LINETXDATA20 M5 SCAN_MODE R1 RLSDATA7

E10 DS2AISCLK H24 LINETXDATA19 M11 VSS R2 LINERXSYNC1

E11 VDD H25 LINETXCLK20 M12 VSS R3 RLSDATA6

E12 TCBDATA H26 LINETXSYNC20 M13 VSS R4 LINERXCLK1

E13 TCBCLK J1 LINERXCLK8 M14 VSS R5 TCK

E14 TCBSYNC J2 LINERXSYNC8 M15 VSS R11 VSS

E15 RCBDATA J3 LINERXDATA8 M16 VSS R12 VSS

E16 VDD J4 LINERXDATA7 M22 DS3POSDATAIN R13 VSS

E17 RCBCLK J5 LINERXCLK16 M23 LINETXCLK25 R14 VSS

E18 RCBSYNC J22 DS3DATAINCLK M24 LINETXCLK24 R15 VSS

E19 RDLCLK J23 LINETXSYNC22 M25 LINETXSYNC25 R16 VSS

E20 VSS J24 LINETXSYNC21 M26 LINETXDATA24 R22 DS3POSDATAOUT

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

13Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

R23 LINETXCLK28 W5 TMSN AB19 RXDATAEN AD11 RPSC155N

R24 LINETXCLK29 W22 TXDATAEN AB20 VSS AD12 REF14

R25 LINETXDATA28 W23 DATA4 AB21 MODE2_PLL AD13 TPSC155N

R26 LINETXSYNC29 W24 DATA7 AB22 VDD AD14 ECSEL

T1 VSS W25 DATA5 AB23 ADDR19 AD15 TSTSFTLD

T2 RLSDATA4 W26 DATA6 AB24 INTN AD16 DS1XCLK

T3 RLSDATA3 Y1 TLSDATA2 AB25 DATA15 AD17 MPMODE

T4 RLSDATA5 Y2 TLSDATA3 AB26 VDD AD18 DSN

T5 VDD Y3 TLSDATA1 AC1 RLSSYNC52 AD19 ADDR3

T11 VSS Y4 TLSDATA4 AC2 RLSC52 AD20 ADDR7

T12 VSS Y5 VSS AC3 TLSC52 AD21 ADDR10

T13 VSS Y22 VSS AC4 VSS AD22 VDDD_PLL

T14 VSS Y23 DATA8 AC5 TPOACSYNC AD23 VSSS_PLL

T15 VSS Y24 DATA11 AC6 AUTO_AIS1 AD24 CLKIN_PLL

T16 VSS Y25 DATA9 AC7 RHSCP AD25 ADDR16

T22 VDD Y26 DATA10 AC8 THSSYNCP AD26 ADDR15

T23 LINETXDATA29 AA1 VSS AC9 VDDA_CDR AE1 VSS

T24 RSTN AA2 TLSCLK AC10 RPSC155P AE2 TTOACDATA

T25 PMRST AA3 TLSPAR AC11 REF10 AE3 RPOACCLK

T26 VSS AA4 TLSDATA0 AC12 TPSC155P AE4 TPOACCLK

U1 VDD AA5 RTOACSYNC AC13 LOPOHCLKIN AE5 LOSEXT

U2 RLSDATA1 AA22 ADDR13 AC14 LOPOHDATAIN AE6 AUTO_AIS2

U3 RLSDATA0 AA23 DATA12 AC15 ETOGGLE AE7 RHSDN

U4 RLSDATA2 AA24 DATA14 AC16 TSTMUX0 AE8 THSCN

U5 TDI AA25 DATA13 AC17 E1XCLK AE9 THSDN

U22 PHASEDETDOWN AA26 VSS AC18 CSN AE10 RPSD155N

U23 DTN AB1 VDD AC19 ADDR0 AE11 CTAPTH

U24 PAR1 AB2 TLSSPE AC20 ADDR4 AE12 RESLO

U25 PAR0 AB3 TLSV1 AC21 ADDR8 AE13 TPSD155N

U26 VDD AB4 TLSJ0J1V1 AC22 ADDR12 AE14 BYPASS

V1 RLSSPE AB5 VDD AC23 VSS AE15 EXDNUP

V2 RLSPAR AB6 TTOACCLK AC24 ADDR17 AE16 TSTMUX1

V3 RLSJ0J1V1 AB7 VSS AC25 APS_INTN AE17 MPCLK

V4 RLSCLK AB8 TRSTN AC26 ADDR18 AE18 ADSN

V5 TDO AB9 IC3STATEN AD1 RTOACCLK AE19 ADDR1

V22 PHASEDETUP AB10 CTAPRH AD2 TLSSYNC52 AE20 ADDR5

V23 DATA0 AB11 VDD AD3 RTOACDATA AE21 ADDR9

V24 DATA3 AB12 VSSA_CDR AD4 RPOACDATA AE22 ADDR11

V25 DATA1 AB13 CTAPRP AD5 TPOACDATA AE23 VDDS_PLL

V26 DATA2 AB14 LOPOHVALIDIN AD6 AUTO_AIS3 AE24 MODE1_PLL

W1 TLSDATA6 AB15 LOPOHCLKOUT AD7 RHSFSYNCN AE25 ADDR14

W2 TLSDATA7 AB16 VDD AD8 RHSCN AE26 VSS

W3 TLSDATA5 AB17 LOPOHDATAOUT AD9 THSSYNCN AF1 VDD

W4 RLSV1 AB18 LOPOHVALIDOUT AD10 RPSD155P AF2 VSS

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

14 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin S ignal Name

AF3 TTOACSYNC AF9 THSDP A15 TSTMODE AF21 VSS

AF4 RPOACSYNC AF10 VDD A16 VSS AF22 VDD

AF5 VDD AF11 VSS A17 VDD AF23 VSSA_PLL

AF6 VSS A12 REWSHI A18 RWMN AF24 MODE0_PLL

AF7 RHSDP AF13 TPSD155P A19 ADDR2

AF8 THSCP AF14 TSTPHASE AF20 ADDR6

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name

Signal Name Pin Signal Name Pin S ignal Name Pin Signal Name Pin

ADDR0 AC19 CTAPRP AB13 ECSEL AD14 LINERXCLK24 A9

ADDR1 AE19 CTAPTH AE11 ETOGGLE AC15 LINERXCLK25 C10

ADDR2 AF19 DATA0 V23 EXDNUP AE15 LINERXCLK26 C11

ADDR3 AD19 DATA1 V25 IC3STATEN AB9 LINERXCLK27 C12

ADDR4 AC20 DATA2 V26 IDDQ P5 LINERXCLK28 D12

ADDR5 AE20 DATA3 V24 INTN AB24 LINERXCLK29 B13

ADDR6 AF20 DATA4 W23 LINERXCLK1 R4 LINERXDATA1 P3

ADDR7 AD20 DATA5 W25 LINERXCLK2 P2 LINERXDATA2 P4

ADDR8 AC21 DATA6 W26 LINERXCLK3 N2 LINERXDATA3 N1

ADDR9 AE21 DATA7 W24 LINERXCLK4 M4 LINERXDATA4 M2

ADDR10 AD21 DATA8 Y23 LINERXCLK5 M3 LINERXDATA5 L4

ADDR11 AE22 DATA9 Y25 LINERXCLK6 L3 LINERXDATA6 K4

ADDR12 AC22 DATA10 Y26 LINERXCLK7 K3 LINERXDATA7 J4

ADDR13 AA22 DATA11 Y24 LINERXCLK8 J1 LINERXDATA8 J3

ADDR14 AE25 DATA12 AA23 LINERXCLK9 H2 LINERXDATA9 H1

ADDR15 AD26 DATA13 AA25 LINERXCLK10 G4 LINERXDATA10 G2

ADDR16 AD25 DATA14 AA24 LINERXCLK11 G3 LINERXDATA11 F4

ADDR17 AC24 DATA15 AB25 LINERXCLK12 F3 LINERXDATA12 E2

ADDR18 AC26 DS1XCLK AD16 LINERXCLK13 E3 LINERXDATA13 D2

ADDR19 AB23 DS2AISCLK E10 LINERXCLK14 D3 LINERXDATA14 C2

ADSN AE18 DS3DATAINCLK J22 LINERXCLK15 B2 LINERXDATA15 F5

APS_INTN AC25 DS3DATAOUTCLK N22 LINERXCLK16 J5 LINERXDATA16 H5

AUTO_AIS1 AC6 DS3NEGDATAIN K22 LINERXCLK17 C3 LINERXDATA17 A3

AUTO_AIS2 AE6 DS3NEGDATAOUT P22 LINERXCLK18 C4 LINERXDATA18 A4

AUTO_AIS3 AD6 DS3POSDATAIN M22 LINERXCLK19 C5 LINERXDATA19 D5

BYPASS AE14 DS3POSDATAOUT R22 LINERXCLK20 C6 LINERXDATA20 B6

CLKIN_PLL AD24 DSN AD18 LINERXCLK21 C7 LINERXDATA21 A7

CSN AC18 DTN U23 LINERXCLK22 D7 LINERXDATA22 C8

CTAPRH AB10 E1XCLK AC17 LINERXCLK23 B8 LINERXDATA23 D8

Table 1. Pin Assignments for 456-Pin PBGA by Pin Number Order (continued)

15Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Signal Name Pin Signal Name Pin Signal Name P in Signal Name Pin

LINERXDATA24 B9 LINETXCLK7 B19 LINETXDATA19 H24 LOPOHCLKOUT AB15

LINERXDATA25 B10 LINETXCLK8 D20 LINETXDATA20 H23 LOPOHDATAIN AC14

LINERXDATA26 B11 LINETXCLK9 C20 LINETXDATA21 J25 LOPOHDATAOUT AB17

LINERXDATA27 A12 LINETXCLK10 C21 LINETXDATA22 K25 LOPOHVALIDIN AB14

LINERXDATA28 C13 LINETXCLK11 C22 LINETXDATA23 L25 LOPOHVALIDOUT AB18

LINERXDATA29 D13 LINETXCLK12 C23 LINETXDATA24 M26 LOSEXT AE5

LINERXSYNC1 R2 LINETXCLK13 B25 LINETXDATA25 N24 MODE0_PLL AF24

LINERXSYNC2 P1 LINETXCLK14 C24 LINETXDATA26 N23 MODE1_PLL AE24

LINERXSYNC3 N4 LINETXCLK15 D24 LINETXDATA27 P26 MODE2_PLL AB21

LINERXSYNC4 N3 LINETXCLK16 E24 LINETXDATA28 R25 MPCLK AE17

LINERXSYNC5 M1 LINETXCLK17 F24 LINETXDATA29 T23 MPMODE AD17

LINERXSYNC6 L2 LINETXCLK18 G24 LINETXSYNC1 D14 PAR0 U25

LINERXSYNC7 K2 LINETXCLK19 G23 LINETXSYNC2 C14 PAR1 U24

LINERXSYNC8 J2 LINETXCLK20 H25 LINETXSYNC3 A15 PHASEDETDOWN U22

LINERXSYNC9 H4 LINETXCLK21 J26 LINETXSYNC4 B16 PHASEDETUP V22

LINERXSYNC10 H3 LINETXCLK22 K24 LINETXSYNC5 B17 PMRST T25

LINERXSYNC11 G1 LINETXCLK23 L24 LINETXSYNC6 B18 RCBCLK E17

LINERXSYNC12 F2 LINETXCLK24 M24 LINETXSYNC7 D19 RCBDATA E15

LINERXSYNC13 E4 LINETXCLK25 M23 LINETXSYNC8 C19 RCBSYNC E18

LINERXSYNC14 D1 LINETXCLK26 N25 LINETXSYNC9 A20 RDLCLK E19

LINERXSYNC15 C1 LINETXCLK27 P25 LINETXSYNC10 B21 RDLDATA H22

LINERXSYNC16 K5 LINETXCLK28 R23 LINETXSYNC11 D22 REF10 AC11

LINERXSYNC17 E6 LINETXCLK29 R24 LINETXSYNC12 A23 REF14 AD12

LINERXSYNC18 B3 LINETXDATA1 A14 LINETXSYNC13 A24 RESHI AF12

LINERXSYNC19 B4 LINETXDATA2 B15 LINETXSYNC14 F22 RESLO AE12

LINERXSYNC20 B5 LINETXDATA3 D16 LINETXSYNC15 C25 RHSCN AD8

LINERXSYNC21 D6 LINETXDATA4 D17 LINETXSYNC16 D25 RHSCP AC7

LINERXSYNC22 B7 LINETXDATA5 D18 LINETXSYNC17 E25 RHSDN AE7

LINERXSYNC23 A8 LINETXDATA6 C18 LINETXSYNC18 F23 RHSDP AF7

LINERXSYNC24 C9 LINETXDATA7 A19 LINETXSYNC19 G25 RHSFSYNCN AD7

LINERXSYNC25 D9 LINETXDATA8 B20 LINETXSYNC20 H26 RLSC52 AC2

LINERXSYNC26 D10 LINETXDATA9 D21 LINETXSYNC21 J24 RLSCLK V4

LINERXSYNC27 D11 LINETXDATA10 B22 LINETXSYNC22 J23 RLSDATA0 U3

LINERXSYNC28 B12 LINETXDATA11 B23 LINETXSYNC23 K23 RLSDATA1 U2

LINERXSYNC29 A13 LINETXDATA12 B24 LINETXSYNC24 L23 RLSDATA2 U4

LINETXCLK1 B14 LINETXDATA13 E21 LINETXSYNC25 M25 RLSDATA3 T3

LINETXCLK2 D15 LINETXDATA14 C26 LINETXSYNC26 N26 RLSDATA4 T2

LINETXCLK3 C15 LINETXDATA15 D26 LINETXSYNC27 P23 RLSDATA5 T4

LINETXCLK4 C16 LINETXDATA16 E23 LINETXSYNC28 P24 RLSDATA6 R3

LINETXCLK5 C17 LINETXDATA17 F25 LINETXSYNC29 R26 RLSDATA7 R1

LINETXCLK6 A18 LINETXDATA18 G26 LOPOHCLKIN AC13 RLSJ0J1V1 V3

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name (continued)

16 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Signal Name Pin Signal Name Pin S ignal Name Pin Signal Name Pin

RLSPAR V2 TLSPAR AA3 VDD AB11 VSS N12

RLSSPE V1 TLSSPE AB2 VDD AB16 VSS N13

RLSSYNC52 AC1 TLSSYNC52 AD2 VDD AB22 VSS N14

RLSV1 W4 TLSV1 AB3 VDD AB26 VSS N15

RPOACCLK AE3 TMSN W5 VDD AF1 VSS N16

RPOACDATA AD4 TPOACCLK AE4 VDD AF5 VSS P11

RPOACSYNC AF4 TPOACDATA AD5 VDD AF10 VSS P12

RPSC155N AD11 TPOACSYNC AC5 VDD AF17 VSS P13

RPSC155P AC10 TPSC155N AD13 VDD AF22 VSS P14

RPSD155N AE10 TPSC155P AC12 VDD AF26 VSS P15

RPSD155P AD10 TPSD155N AE13 VDDA_CDR AC9 VSS P16

RSTN T24 TPSD155P AF13 VDDD_PLL AD22 VSS R11

RTOACCLK AD1 TRSTN AB8 VDDS_PLL AE23 VSS R12

RTOACDATA AD3 TSTMODE AF15 VSS A2 VSS R13

RTOACSYNC AA5 TSTMUX0 AC16 VSS A6 VSS R14

RWN AF18 TSTMUX1 AE16 VSS A11 VSS R15

RXDATAEN AB19 TSTPHASE AF14 VSS A16 VSS R16

SCAN_EN N5 TSTSFTLD AD15 VSS A21 VSS T1

SCAN_MODE M5 TTOACCLK AB6 VSS A25 VSS T11

TCBCLK E13 TTOACDATA AE2 VSS B1 VSS T12

TCBDATA E12 TTOACSYNC AF3 VSS B26 VSS T13

TCBSYNC E14 TXDATAEN W22 VSS D4 VSS T14

TCK R5 VDD A1 VSS D23 VSS T15

TDI U5 VDD A5 VSS E7 VSS T16

TDLCLK E9 VDD A10 VSS E20 VSS T26

TDLDATA E8 VDD A17 VSS F1 VSS Y5

TDO V5 VDD A22 VSS F26 VSS Y22

THSCN AE8 VDD A26 VSS G5 VSS AA1

THSCP AF8 VDD E1 VSS G22 VSS AA26

THSDN AE9 VDD E5 VSS L1 VSS AB7

THSDP AF9 VDD E11 VSS L11 VSS AB20

THSSYNCN AD9 VDD E16 VSS L12 VSS AC4

THSSYNCP AC8 VDD E22 VSS L13 VSS AC23

TLSC52 AC3 VDD E26 VSS L14 VSS AE1

TLSCLK AA2 VDD K1 VSS L15 VSS AE26

TLSDATA0 AA4 VDD K26 VSS L16 VSS AF2

TLSDATA1 Y3 VDD L5 VSS L26 VSS AF6

TLSDATA2 Y1 VDD L22 VSS M11 VSS AF11

TLSDATA3 Y2 VDD T5 VSS M12 VSS AF16

TLSDATA4 Y4 VDD T22 VSS M13 VSS AF21

TLSDATA5 W3 VDD U1 VSS M14 VSS AF25

TLSDATA6 W1 VDD U26 VSS M15 VSSA_CDR AB12

TLSDATA7 W2 VDD AB1 VSS M16 VSSA_PLL AF23

TLSJ0J1V1 AB4 VDD AB5 VSS N11 VSSS_PLL AD23

Table 2. Pin Assignments for 456-Pin PBGA by Signal Name (continued)

17Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

3.3 Pin Descriptions

3.3.1 High-Speed I/O Pin Descriptions

The high-speed I/O consists of five LVDS signals (10 pins) that connect the Supermapper to an external OC-3

optics device. It exchanges an STS-3 or STM-1 signal between the TMUX and an OC-3 transceiver . The Super-

mapper is capable of recovering a clock from the receive data, or it can accept a clock recovered externally by the

optics device. If internal clock recovery is used, the Supermapper uses THSCP/N as a reference.

The high-speed I/O may also run at 52.84 Mbits/s in applications that terminate an STS-1 or EC-1 signal. In this

case, the (electrical) line signals are typically terminated by a line interface unit (LIU) chip. The operating speed of

the high-speed I/O is determined by TMUX_RCV_TX_MODE.

Table 3. High-Speed I/O Pin Descriptions

Pin Symbol Type I/O Description

AF7,

AE7 RHSDP

RHSDN LVDS I Receive Hig h-Sp eed Dat a. 155.52 Mbits/s serial data input in STS-1 or

STM-1 format, or 51.84 Mbits/s data in STS-1 format. If RHSD is not used

(in a slave Supermapper, for example), the P input should be pulled high

through a 1 kΩ resistor and the N input pulled low through a 1 kΩ resistor .

RHSD is typically provided by an OC-3 receiver, an STS-1 line interface

unit, or a higher-order (e.g., STS-12) demultiplexing chip.

AC7,

AD8 RHSCP

RHSCN LVDS I Receive Hig h-Sp eed Clo ck. 155.52 MHz or 51.84 MHz clock for STS-3

or STS-1 input data. Typically supplied by an external OC-3 optoelec-

tronic device, or an STS-1/EC1 line interface unit, synchronous with

RHSD. If the internal clock recovery (CDR) feature is enabled, RHC is not

required and should be connected to a 1 kΩ resis tors to VDD (RHCP

input) and VSS (RHCN input).

AF8,

AE8 THSCP

THSCN LVDS I Transmit High-Speed Clock. T ransmit 155.52 MHz or 51.84 MHz clock.

Master clock for the transmit sections of the TMUX, telecom bus, SPE,

and VT mappers. THSC is also used as a reference clock for the receive

CDR, if it is being used.

AC8,

AD9 THSSYNCP

THSSYNCN LVDS I Transmit High-Speed Frame Synchronization. An optional input that

may be used to specify the position of the transmit STS-3, STM-1, or

STS-1 frame. THSSYNC marks the position of bit 1 of the A1 byte, i.e.,

the first bit of the overhead in the THSD output. If THSSYNC is not used,

the P input should be pulled high through a 1 kΩ resistor , and the N input

pulled low through a 1 kΩ resistor. A typical application for this pin may

be to synchronize a group of Supermappers so that their STS-3 outputs

may be multiplexed into an STS-12 signal.

AF9,

AE9 THSDP

THSDN LVDS O Transmit High-Speed Data. Transmit output for STS-3, STM-1, or STS-

1 serial data. Typically connected to an OC-3 module or an LIU, if operat-

ing in STS-1 mode. May also be connected to a higher-order multiplexing

device, for example, STS-12.

18 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

3.3.2 Protection Switch I/O Pin Description

The protection switch I/O provides additional copies of the high-speed interface signals so that various protection

schemes may be implemented. The protection interface may be used when the high-speed interface is operating in

both STS-3 and STS-1 modes. If the protection port is not used, the input clock and data may be left unconnected,

tied to power (P inputs), or ground (N inputs) through 1 kΩ resistors. Unused protection outputs should be left

unconnected.

Table 4. Protection Switch I/O Pin Description

Figure 3. Protection Switch

3.3.3 Telecom Bus (Low-Speed I/O) Pin Description

The telecom bus on the Supermapper is used for interconnecting STS-1 signals. It has two 8-bit data buses, one

for upstream data and one for downstream data, plus clock and frame indication signals for each bus. The telecom

bus can operate at 19.44 MHz (space for three STS-1 signals) or 6.48 MHz (space for 1 STS-1 signal).

Supermappers in OC-3 applications are typically connected using the telecom bus, and the bus is configured to

operate at 19.44 MHz.

Pin Symbol Type I/O Description

AD10,

AE10 RPSD155P

RPSD155N LVDS I Receive Protection Data. Receive side high-speed serial data input

from protection board.

AC10,

AD11 RPSC155P

RPSC155N LVDS I Receive Protection Clock. Receive side high-speed clock input from

protection board.

AF13,

AE13 TPSD155P

TPSD155N LVDS O Transmit Protection Data. Transmit side high-speed serial data output

to protection board.

AC12,

AD13 TPSC155P

TPSC155N LVDS O Transmit Protection Clock. Tran sm it si de hig h- sp eed clock output to

protection board.

STS-3 TRANSMIT

FRAMER

STS-3 RECEIVE

FRAMER

RPSMUXSEL1

HIGH-SPEED

PROTECTION

INPUT HIGH-SPEED

PROTECTION

OUTPUT

HIGH- SPEED I/O

TPSMUXSEL2

TPSMUXSEL3

19Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Table 5. Telecom Bus (Low-Speed I/O) Pin Description

Pin Symbol Type I/O Description

R1, R3, T4, T2,

T3, U4, U2, U3 RLSDATA[7:0] — I/O Receive Low-Speed Data [7:0], Parallel Data Bus. Used

to connect the downstream STS-1 signals from the master

to the slave devices. In master mode, RLSDATA is an out-

put bus, 8 bits wide. It contains all the received data for dis-

tribution to the two slave devices. Connect to

RLSDATA[7:0] on the slave devices. In slave mode, these

pins are inputs and should be connected to the

RLSDATA[7:0] outputs on the master. RLSDATA contains

three byte-interleaved STS-1 time slots. The slot used by

each SPE mapper in the slaves and the master device is

determined by programing the SPE_RSTS3_TMSLOT reg-

ister bits.

V4 RLSCLK — I/O Receive Low-Speed Clock. This is a 19.44 MHz or

6.48 MHz clock for the receive low-sp eed data bits. In

19.44 MHz master mode, this is a 19.44 MHz clock output

for distribution to the two slave devices. Connect to

RLSCLK on the slaves. RLSCLK is an input signal on slave

devices.

Note: As outputs, these pins have 6 mA drive capability.

V2 RLSPAR — I/O Receive Low-Speed Parity. Receive data parity bit, may

be configured for odd or even parity generated on

RLSDATA[7:0]. The default is odd parity; it may be set to

even by setting bit 2 of the register at 0x4001B an output in

master mode and an input in slave mode. Connect the

RSLPAR (output) on the master to The RLSPAR (input)

pin s on the slaves.

V1 RLSSPE — I/O Receive Low-Speed SPE Marker. Receive synchronous

payload envelope timing indicator. It is high while there is

SPE data on the RLSDATA[7:0] output bus. Connect to

RLSSPE on the slaves. RLSSPE is an input on slave

devices.

V3 RLSJ0J1V1 — I/O Receive Low-Speed J0/J1/V1 Marker. On the master

device, this is an output that is high while J0-1, J1

(1, 2, and 3), and V1 (1, 2, and 3) bytes are present on the

RLSDATA bus. Connect to RLSJ0J1V1 on the slaves,

which is an input.

W4 RLSV1 — I/O Receive Low-Speed V1 Marker. Receive V1 tim ing indi ca-

tor . On the master , this is an output that is high while the V1

bytes (1, 2, and 3) are present on RLSDATA[7:0] output

bus. Connect to RLSV1 on the slaves.

20 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Table 5. Telecom Bus (Low-Speed I/O) Pin Description (continued)

Pin Symbol Type I/O Description

W2, W1, W3, Y4,

Y2, Y1, Y3, AA4 TLSDATAI[7:0] — I/O Transmit Low-Speed Data [7:0]. This is a parallel data

bus. It is used to connect the upstream STS-1 signals from

the slave devices to the master device. In master mode,

TLSDATA is an input bus, 8 bits wide. It contains all the

transmit STS-1 data from the slave devices. In slave mode,

these pins are outputs and should be connected to the

TLSDATA[7:0] inputs on the master. TLSDATA contains

three byte-interleaved STS-1 time slots. The slot used by

each SPE mapper in the slaves and the master device is

determined by programing the SPE_TSTS3_TMSLOT reg-

ister bits.

AA2 TLSCLK — I/O Transmit Low-Speed Clock. This is a 19.44 MHz or

6.48 MHz clock for the TLSDATA[7:0] bits. TLSCLK is an

output on a master Supermapper and an input on a slave.

Note: As outputs, these pins have 6 mA drive capability.

AA3 TLSPAR — I/O Transmit Low-Speed Parity. This parity bit is generated

on the TLSDATA[7:0] bits output from slave devices and

input to the master Supermapper. May be configured for

odd or even parity generation or for checking.

AB2 TLSSPE — I/O Transmit Low-Speed SPE Marker. High while the STS-1

payloads are present on the TLSDATA[7:0] bus. Low while

the STS-1 overhead is present on the TLSDATA[7:0] bus.

An output from the master and input on the slaves.

AB4 TLSJ0J1V1 — I/O Transmit Low-S peed J0/J1/ V1 Mar ker. Transmit J0, J1,

or V1 timing indicator. High while the J0, J1, or V1 bits are

pres en t o n t he T L S DATA[7:0] bu s. A n o u tpu t on t h e m as t er

and input on slaves.

AB3 TLSV1 — I/O Transmit Low-Speed V1 Marker 3. Transmit V1 timing

indicator. High while the V1 bits are present on the

TLSDATA[7:0] bus. An output on the master and input on

slaves.

AC2 RLSC52 — I/O Receive Low-Speed Clock. Wh en in outp ut (maste r)

mode, it is the receive side of the 51.84 MHz clock output,

synchronous to the receive high-speed input clock (data).

When in input (slave) mode, it receives a 51.84 MHz clock

input, synchronous to the receive high-speed input clock

(data).

Note: As outputs, these pins have 6 mA drive capability.

AC1 RLSSYNC52 — I/O Receive Low-Speed Sync. When in output (master) mode,

it is the receive side frame sync output synchronous to a

51.84 MHz output. When in input mode, it is the receive

side frame sync input synchronous to a 51.84 MHz input.

21Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Table 5. Telecom Bus (Low-Speed I/O) Pin Description (continued)

3.3.4 TOAC and POAC

The transport and path overhead access channels (TOAC and POAC) allow parts of the SONET/SDH overhead to

be examined externally (receive direction) or overwritten (transmit direction) through serial data ports. Each port

has clock and data lines and a synchronization signal that marks the last bit of the frame so that the rest of the

overhead bytes can be identified.

The receive TOAC and POAC channels contain all of the respective overheads bytes. The transmit channels con-

tain space for all the overhead bytes, but whether they are actually transmitted depends on how the device is pro-

grammed. Some overhead bytes cannot be modified; some may be modified only through the CPU port; some may

be modified only through the overhead access channels; and some may be modified either through the CPU port,

or through the overhead access channels.

Pin Symbol Type I/O Description

AC3 TLSC52 — I/O T ransmit Low-S peed Clock. When in output (master) mode,

it is the transmit side 51.84 MHz clock output synchronous to

transmit high-speed input clock. When in input mode, it

receives a 51.84 MHz clock input synchronous to transmit

high-speed input clock

Note: TLSCLK is used as the master clock for the T1/E1

framer and should therefore is provided even if the

TMUX SPE and VT mappers are not used.

AD2 TLSSYNC52 — I/O Transmit Low-Speed Sync. When in output (master) mode,

it is the transmit side frame sync output synchronous to

51.84 MHz output. When in input (slave) mode, it receives

the transmit side frame sync input synchronous to 51.84 MHz

input.

Table 6. TOAC and POAC

Pin Symbol Type I/O Description

AD1 RTOACCLK — O Receive TOAC Clock. Receive side serial access channel

clock output for the transport overhead bytes.

AD3 RTOACDATA — O Receive TOAC Data. Receive side serial access channel

data output for the transport overhead bytes.

AA5 RTOACSYNC — O Receive TOAC Sync hronization. Rec eive side sync outpu t

for TOAC channel. Active-high during the LSB of the last

byte.

AB6 TTOACCLK — O Transmit T OAC Clock. Transmit side serial access channel

clock output for the transport overhead bytes.

AE2 TTOACDATA — I

Pull-down Transmit TOAC Data. Transmit side serial access channel

data input for the transport overhead bytes.

AF3 TTOACSYNC — O Transmit TOAC Synchronization. Transmit si de sy nc out-

put for TOAC channel. Active-high during the LSB of the last

byte.

22 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

3.3.5 Miscellaneous Signals

Table 7. Miscellaneous Signals

3.3.6 DS3 Port

If a DS3 output is required in a Supermapper application and the DS3 signal has been recovered (demapped) from

an STS-1, then it is necessary to smooth the DS3 recovered clock. The DS3 clock extracted from the STS-1 clock

will have considerable jitter introduced when the SONET overhead is removed and pointer adjustments are made.

A phase-locked loop is recommended for this purpose. The Supermapper contains a phase comparator that can

be used in conjunction with an external low-pass filter and voltage-controlled crystal oscillator to implement the

PLL.

Pin Symbol Type I/O Description

Path Overhead Access Channel (POAC)

AE3 RPOACCLK — O Receive POAC Clock. Receive side serial access channel

clock output for the path overhead bytes.

AD4 RPOACDATA — O Receive POAC Data. Receive side serial access channel

data output for the path overhead bytes.

AF4 RPOACSYNC — O Receive POAC Synchronization. Receive side sync output

for POAC channel. Active-high during the last bit of the last

byte of the POAC frame.

AE4 TPOACCLK — O Transmit POAC Clock. T ransmit side serial access chan-

nel clock output for the path overhead bytes.

AD5 TPOACDATA — I

Pull-down Transmit POAC Data. Transmit side serial access channel

data input for the path overhead bytes.

AC5 TPOACSYNC — O Transmit POAC Synchronization. Transmit side sync out-

put for POAC channel. Active-high during the last bit of the

last byte.

Pin Symbol Type I/O Description

AE5 LOSEXT — I

Pull-up Loss of Signal External. External loss of signal input. If

external clock and data recovery is used on the high-speed

I/O port, it may be connected to this input, which can be con-

figured to assert the LOS register bit normally associated with

the internal LOS detection in the internal CDR block. The

polarity of LOS may be programmed active-high or low.

AD6, AE6,

AC6 AUTO_AIS — I/O AIS Enable [3:1]. Control signal for automatic AIS insertion

on each STS1. The STS-1 AIS is applied down stream on the

telecom bus, i.e., it is an output from masters and an input to

slaves. Active-high.

Input when slave mode.

Output when master mode.

If not used, leave open.

AD7 RHSFSYNCN — O Receive High-Spee d Frame Synchronization. Receive

side frame sync output indicating the frame location of the

high-speed data input. May be used as an 8 kHz timing refer-

ence for network synchronization to the receive high-speed

data input (STS- 3 or STS-1 ).

Table 6. TOAC and POAC (continued)

23Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Table 8. DS3 Port

Pin Symbol Type I/O Description

V22 PHASEDETUP — O Phase Detector Up. Phase error signal out to external fil-

ter and VCXO. This output will generate an error signal

when the VCXO output is slower than the reference sig-

nal.

U22 PHASEDETDOWN — O Phase Detector Down. Phase error signal out to external

filter and VCXO. This output will generate an error signal

when the VCXO output is faster that the reference signal.

R22 DS3POSDATAOUT — O Positive Data Output. Serial DS3 positive data out to

LIU when the DS3 output port is operating in dual-rail

mode. Nonreturn-to-zero DS3 data output when the DS3

output is operating in single-ended mode.

P22 DS3NEGDATAOUT — O Negative Data Output. Serial DS3 negative data output

to LIU when the DS3 port is operating in dual-rail mode.

In single-rail mode, this output is not used and may be left

unconnected.

N22 DS3DATAOUTCLK — I

Pull-down DS3 Data Out Clock. 44.736 MHz DS3 clock input. If the

Supermapper is being used to map DS3 data to and from

STS-1, then this clock will be supplied by the external

VCXO that is associated with the DS3 clock recovery

PLL. In other DS3 modes (e.g., M13), this input will be

supplied by an external crystal oscillator, usually associ-

ated with a DS3 LIU . If th e DS3 p ort i s not us ed, th is inpu t

may be tied to ground or left open, since it is equipped

with an internal pulldown resistor.

M22 DS3POSDATAIN — I

Pull-down Positive Data Input. If the DS3 port is configured in dual-

rail mode, then this input is serial positive data from an

external DS3 LIU. If the DS3 port is configured in single-

rail mode, then this input is serial nonreturn-to-zero data

from the external LIU.

K22 DS3NEGDATAIN — I

Pull-down Negative Data In. In dual-rail mode, this is negative data

from an external DS3 LIU. In single-rail mode, it may be

connected to the bipolar violation output of the external

DS3 LIU, left unconnected, or tied to ground.

J22 DS3DATAINCLK — I

Pull-down DS3 Data In Clock. This is a 44.736 MHz clock input

from the clock recovery in the external DS3 LIU.

24 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Table 9. DS3 Port, C Bit, and Datalink Access

3.3.7 M13 Multiplexer/Demultiplexer Receive Section

Two groups of signals are defined in this section. The first group are reference clocks, used internally in the jitter

attenuation and AIS generation processes. Note that these are typically supplied by free-running crystal oscillators.

The outputs below provide access to the received C bits and data link bits extracted from the received DS3 frame.

These operate in the same way if the source of the DS3 signal is from an SPE or from the external DS3 port.

Pin Symbol Type I/O Description

E14 TCBSYNC — O Transmit C-Bit Sync. In the C-bit parity mode, 10 C bits may

optionally be input for multiplexing into the transmit DS3 frame

through the TCBDATA input. The TCBSYNC output is low, except

during the rising edge of TCBCLK that is used to input C2.

E13 TCBCLK — O Transmit C-Bit Clock. A gapped clock (nominally 93.983 kHz) for

accepting selected C bits on input M13_CBDATA.

E12 TCBDATA — I

Pull-down Transmit C-Bit Data. In the C-b i t p a r ity m o de , th e ne t w or k re qu i r e-

ments bit (C2) and the unused C bits (C4, C5, C6, C16, C17, C18,

C19, C20, and C21) may optionally be input for multiplexing into

the transmit DS3 frame through this input.

E9 TDLCLK — O Transmit Data Link Clock. A gapped clock (nominally

28.195 kHz) for accepting path maintenance data link C bits on

in put TDLDATA.

E8 TDLDATA — I

Pull-down Transmit Data Link Data. The path maintenance data link C bits

(C13, C14, and C15) may optionally be input for multiplexing into

the transmit DS3 frame through this input.

Table 10. M13 Multiplexer/Demultiplexer Receive Section

Pin Symbol Type I/O Description

AC17 E1XCLK — I

Pull-down E1 Reference Clock. This clock is used as a reference for the jitter

attenuator when it is operating in the E1 mode. It must have a fre-

quency of 2.048 MHz, 32.768 MHz, or 65.536 MHz and a stability of

50 ppm. It is also used to generate an E1 AIS (all ones). May be left

unconnected or tied to ground if no E1 options are being used.

AD16 DS1XCLK — I

Pull-down DS1 Reference Clock. This clock is used as a reference for the jit-

ter attenuator when it is operating in the DS1 or the J1 mode. It must

have a frequency of 1.544 MHz, 24.704 MHz, or 49.408 MHz and a

stability of ±32 ppm. This clock signal is also used to generate DS1

AIS signals. May be left unconnected or tied to ground; if not, no

DS1 options are being used.

E10 DS2AISCLK — I

Pull-down DS2 Reference Clock. A 6.312 MHz ± 30 ppm input. In the M23

mode, this clock is used to generate DS2 AIS. May be left uncon-

nected or tied to ground if no DS2 options are being used. Note that

C-bit parity mode does not require a DS2 reference clock.

E18 RCBSYNC — O Receive C-Bit Sync. Ten C bits are output on RCD after they are

demultiplexed from the received DS3 signal. The RCS output is low ,

except during the rising edge of RCD that is used to output C2.

25Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

3.3.8 Low-Order Path Overhead Access Channel

Each VT has a low-order path overhead, and this interface allows access to all LOPOH bits for all VTs. Note that

the purpose of doing this is slightly different from the transport and path overhead access. These are used to cross

couple the bits between links in a protection scheme, rather than provide access for examination or modification of

the overhead, although that is possible too.

Table 11. Low-Order P ath Overhead Access Channel

Figure 4. DS1/E1 to DXC Block Diagram

Pin Symbol Type I/O Description

E17 RCBCLK — O Receive C-Bit Clock. A gapped clock (nominally 93.983 kHz) for

outputting selected C bits on RCD.

E15 RCBDATA — O Receive C-Bit Data. The received network requirements bit (C2)

and the received unused C bits (C4, C5, C6, C16, C17, C18, C19,

C20, and C21) are output after they are demultiplexed from the

received DS3 signal.

E19 RDLCLK — O Receive Data Link Clock. A gapped clock (nominally 28.195 kHz)

for outputting path maintenance data link C bits on RDLD.

H22 RDLDATA — O Receive Data Link Data. The received path maintenance data link

C bits (C13, C14, and C15) that are demultiplexed from the received

DS3 signal.

Pin Symbol Type I/O Description

Transmit Direction

AC13 LOPOHCLKIN — I Pull-down 6.48 MHz Low-Order Path Overhead Clock.

AC14 LOPOHDATAIN — I Pull-down Low-Order Path Overhead Data. (O bits, V5, J2,

Z6/N2, Z7, and K4 byte.)

AB14 LOPOHVALIDIN — I Pull-down Valid LOPOH_DATA.

Receive Direction

AB15 LOPOHCLKOUT — O 6.48 MHz Low-Order Path Overhead Clock.

AB17 LOPOHDATAOUT — O Low-Order Path Overhead Data. (O bits,V5, J2,

Z6/N2, and Z7/K4 byte.)

AB18 LOPOHVALIDOUT — O Valid VTMPR_LOPOH_DATA Output.

Table 10. M13 Multiplexer/Demultiplexer Receive Section (continued)

VT MAPPER VT MAPPER

LOPOH

OUTPUTS

LOPOH

INPUTS

LOPOH

OUTPUTS

LOPOH

INPUTS

TELECOM BU S

DS1/E1 TO DXC

26 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Table 12. Multifunction System Interface Transmit Path Direction

Pin Symbol Type I/O Description

C13, A12,

B11, B10, B9,

D8, C8, A7,

B6, D5, A4,

A3, H5, F5,

C2, D2, E2,

F4, G2, H1,

J3, J4, K4, L4,

M2, N1, P4,

LINERXDATA[28:1] — I

Pull-

down

Line Receive Dat a [28:1] . Configurable inputs to the

internal cross connect. The use depends on the applica-

tion. Generally, these inputs are used for the received

positive-rail or single-rail DS1/E1 line data input. If operat-

ing in dual-rail mode, the negative rail will be expected on

LINERXSYNC[28:1]. Using dual-rail mode implies that the

internal B8ZS or HDB3 decoders are enabled, and line

code violations can be detected and counted inside the

Supermapper.

These data inputs may be assigned, using the cross con-

nect block, to the DS1 or E1 inputs on the VT mapper,

M13 or DS1/E1 framers. It is also possible to use the

inputs for DS2 data, in which case they may be assigned

to the M23 multiplexer inputs.

D13 LINERXDATA29 — I

Pull-

down

Receive Data 29. Configurable input to the internal cross

connect. May be used as an additional line receive data

input, for a protection channel. Other possible uses are as

follows:

Global transmit line clock input. Externally supplied

1.544 MHz or 2.048 MHz low jitter clock phase-locked to

the TDM system clock. Used for transmit line clock on the

DS1/E1 framers. This is not normally used because the

DS1/E1 framer has a PLL that can generate a

1.544 MHz clock from the TDM system clock (CHI clock).

This applies in PSB and CHI modes.

Receive data input. If NSMI mode is used, this will be a

51.84 Mbits/s serial data input.

D12, C12,

C1 1, C10, A9,

B8, D7, C7,

C6, C5, C4,

C3, J5, B2,

D3, E3, F3,

G3, G4, H2,

J1, K3, L3,

M3, M4, N2,

P2, R4

LINERXCLK[28:1] — I/O

Pull-

down

Receive Clock [28:1]. Configurable inputs/output s to the

internal cross connect. Typically a line clock associated

with the corresponding LINERXDATA input. It can there-

fore be running at DS1, E1, or DS2 rate. The cross con-

nect is used to assign these inputs to the VT mapper,

M13, or DS1/E1 framers.

B13 LINERXCLK29 — I/O

Pull-

down

Receive Clock 29. May be used as additional receive

clock input for a DS1/E1 protection channel. Also has

special use as a master clock. In CHI mode, it is the

receive clock input (2.048 MHz, 4.096 MHz, 8.192 MHz,

or 16.384 MHz). In PSB mode, it is the receive clock input

(19.44 MHz). In NSMI mode, it is the receive clock output.

(51.84 MHz).

27Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Pin Symbol Type I/O Description

B12, D11,

D10, D9, C9,

A8, B7, D6,

B5, B4, B3,

E6, K5, C1,

D1, E4, F2,

G1, H3, H4,

J2, K2, L2,

M1, N3, N4,

P1, R2

LINERXSYNC[28:1] — I Line Receive Sync hronous[28:1]. Multifunction input.

Channel assignment may be configured through the inter-

nal cross connect. Can be used as the negative rail of a

DS1/E1 signal in conjunction with LINERXDATA[28:1],

when operating in dual-rail mode. In CHI mode, these

inputs are used for receive TDM highways that may run at

2.048, 4.096, or 8.192 Mbits/s. In parallel system bus

mode, the receive system data bus inputs are assigned to

LINERXSYNC 16:1. The PSB is a 16-bit wide bus that

operates at 19.44 MHz.

A13 LINERXSYNC29 — I/O Line Receive Synchronous 29. Multifun cti on inp ut.

Channel assignment may be configured through the inter-

nal cross connect. Can be used as the negative rail of a

DS1/E1 signal in conjunction with LINERXDA TA 29, when

operati ng in dual- ra il mode.

In CHI and PSB modes, this input is used as the receive

system frame synchronization input. In NSMI mode, it is

the receive frame sync output.

R25, P26,

N23, N24,

M26, L25,

K25, J25,

H23, H24,

G26, F25,

E23, D26,

C26, E21,

B24, B23,

B22, D21,

B20, A19,

C18, D18,

D17, D16,

B15, A14

LINETXDATA[28:1] — I/O Line Transmi t Da t a [2 8:1] Configurable outputs from the

internal cross connect. Used for transmit positive-rail or

singl e- rail D S1/ E1 l ine dat a out put s. May be co nne cte d to

the DS1/E1 outputs from the VT mapper, M13 MUX, or

DS1/E1 frame line outputs. May also be used as a DS2

output.

T23 LINETXDATA29 — O L ine Transmit Data 29. Configurable output from the

internal cross connect. An extra DS1 or E1 transmit port

that may be used for protection or as a timing reference

output.

Table 12. Multifunction System Interface Transmit Path Direction (continued)

28 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Pin Symbol Type I/O Description

R23, P25,

N25, M23,

M24, L24,

K24, J26,

H25, G23,

G24, F24,

E24, D24,

C24, B25,

C23, C22,

C21, C20,

D20, B19,

A18, C17,

C16, C15,

D15, B14

LINETXCLK[28:1] — I/O Line Transmit Clock [28:1]. Configurab le outp uts from

the internal cross connect. Can be used as the clock sig-

nals for LINETXDATA[28:1] in DS1, E1, and DS2 modes.

R24 LINETXCLK29 — I/O Line Transmit Clock 29. Configurable output to the inter-

nal cross connect for the protection or timing reference

channel. Also used as the transmit global system clock

input for CHI (2.048 MHz, 4.096 MHz, 8.192 MHz, or

16.384 MHz), PSB (19.44 MHz), and NSMI (51.84 MHz)

modes.

P24, P23,

N26, M25,

L23, K23, J23,

J24, H26,

G25, F23,

E25, D25,

C25, F22,

A24, A23,

D22, B21,

A20, C19,

D19, B18,

B17, B16,

A15, C14,

D14

LINETXSYNC[28:1] — I/O Line Transmit Synchronous [28:1]. Configurable inputs/

outputs to the internal cross connect. An output when

used as the negative rail of a DS1 or E1 output port oper-

ating in dual-rail mode. In CHI mode, these pins may be

used as output TDM highways. In PSB mode, bits 16:1

are used for the transmit data bus, and bits 28:17 are not

used. These pins may also be used as DS2 I/O to the

M12 block as follows: 7:1—Tx data out. 14:8—Tx clock in.

21:16—Rx data in. 28:22—Rx clock in.

R26 LINETXSYNC29 — I/O Line Transmit Synchronous 29. Configurab le inp ut/o ut-

put to the internal cross connect. An output when used as

the negative rail of a DS1 or E1 output port operating in

dual-rail mode. In CHI and PSB modes, it is used as the

transmit system frame synchronization input. In NSMI

mode, it is the transmit system frame sync output.

AB19 RXDATAEN — O NS MI Rece ive Enable . Receive data enable for NSMI

mode.

W22 TXDATAEN — O NMSI Transmit Enable. Transmit data enable for NSMI

mode.

Table 12. Multifunction System Interface Transmit Path Direction (continued)

29Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

3.3.9 Framer PLL

The DS1/E1 framer has a phase-locked loop that may be used to generate a transmit line clock at 1.544 MHz or

2.048 MHz. The reference signal for this PLL may be chosen from a number of possible sources, all typically syn-

chronized to the system clock (CHI transmit/receive clock, for example). In order to ensure reliable performance,

this PLL has its own isolated power pins. The PLL also has a number of test control pins that are used for factory

testing only.

The PLL is active when framer bit PLL_BYPAS = 0. When PLL_BYPAS = 1, the PLL is bypassed and an external

clock at the system interface is used as the line clock. An example would be when the framers are programmed for

a CHI interface at 2.048 MHz and the frames are programmed for E1, the PLL may be bypassed and the CHI sys-

tem clock may be used as the line clock.

Table 13. Framer PLL

Pin Symbol Type I/O Description

AD22 VDDD_PLL VDD —Digital VDD for PLL.

AE23 VDDS_PLL VDD —Analog VDD for PLL.

AF23 VSSA_PLL VSS —Analog VSS for PLL.

AD23 VSSS_PLL VSS —Digital VSS for PLL.

AD24 CLKIN_PLL — I

Pull-down Clock In PLL. Phase locked-loop reference clock input. Fre-

quency should be consistent with the MODE_PLL pins in the

PLL Mode1 table below. A 1.544 MHz clock for DS1 transmit

outputs is generated synchronous to this clock.

AB21 MODE2_PLL — I/O PLL Mode 2. Control bit that should be tied to the appropriate

state depending on the frequency of CLKIN_PLL consistent

with the PLL Mode1 table below. This pin is also used during

factory testing as an output.

AF24 MODE0_PLL — I

Pull-down PLL Mode 0. PLL control input 0.

AE24 MODE1_PLL — I

Pull-down PLL Mode 1. PLL control input 1. The PLL mode inputs should

be hardwired to the logic levels shown in the table below,

depending on the frequency of the reference supplied to

CLKIN_PLL.

Mode2

Mode1

Mode0

CLKIN_PLL

Reserved

51.840 MHz

26.624 MHz

19.440 MHz

16.348 MHz

8.1940 MHz

4.0960 MHz

30 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

Table 14. Microprocessor Interfaces

Pin Symbol Type I/O Description

AE17 MPCLK — I Processor Clock. This is the synchronous microprocessor

clock (when MPMODE = 1). The maximum clock frequency

is 60 MHz. This clock is required to properly sample address,

data, and control signals from the microprocessor in both

asynchronous and synchronous modes of operation. This

clock must be within the range of 16 MHz—60 MHz.

AD17 MPMODE — I Control Port Mode. If the microprocessor interface is syn-

chronous, CPM should be set to 1. If the microprocessor

interface is asynchronous, CPM should be set to 0.

AC18 CSN — I

Pull-up Chip Select. Active-low chip select. For synchronous mode,

it should be stable beyond a certain setup time before the ris-

ing clock edge when AS is active. For asynchronous mode, it

should be stable before DS is asserted.

AE18 ADSN — I Address Strobe . Active-low address strobe that is a 1 PCK

cycle wide pulse for synchronous mode and active for the

entire read/write cycle for asynchronous mode. Address bus

signals, A[19:0], are transparently latched into Supermapper

when AS is low. The address bus should remain valid for the

duration of AS.

AF18 RWN — I Read/Write Cycle Selection. RW is set high for a read oper-

ation, or set low for write operation.

AD18 DSN — I Data Strobe. DS is not used for synchronous mode. For

asynchronous mode, write operation, DS becomes active

after data is stable. For read operation, it is similar to AS.

AB23, AC26,

AC24, AD25,

AD26, AE25,

AA22, AC22,

AE22, AD21,

AE21, AC21,

AD20, AF20,

AE20, AC20,

AD19, AF19,

AE19, AC19

ADDR[19:0] — I Address [19:0]. A19 is the most significant and A0 the least

significant bit for addressing all the internal SM registers dur-

ing CPU access cyc les.

Note: The Supermapper is little endian; the least significant

byte is stored in the lowest address and the most sig-

nificant byte is stored in the highest address. Care

must be exercis ed in co nnecti on to mic ropr oces so rs

that use big-endian byte ordering.

AB25, AA24,

AA25, AA23,

Y24, Y26,

Y25, Y23,

W24, W26,

W25, W23,

V24, V26,

V25, V23

DATA[15:0] — I/O Data [15:0]. Data bus for all transfers between the CPU and

the internal SM registers. The pins are inputs during write

cycles and outputs during read cycles. DATA15 is the MSB,

and DATA0 is the LSB.

U24, U25 PAR[1:0] — I/O CPU Port Parity [1:0]. Byte-wide parity bits for data. CPP[1]

is the parity for D[15:8], and CPP[0] is the parity for D[7:0].

31Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Table 15. General-Purpose Interface

Pin Symbol Type I/O Description

U23 DTN — O

Open Drain Data Transfer Acknowledge. In synchronous CPU mode,

DTA goes low at the fourth cycle for write or the fifth cycle for

read, resulting in a fixed two wait-states for writes and three

wait-states for reads. In asynchronous µP mode, after qualifi-

cation of AS and DS by TLSC52 clock, DTA goes low for two

TLSC52 clock cycles for writes and three TLSC52 clock

cycles for reads. DT A goes high, along with the rising edge of

AS.

AB24 INTN — O

Open Drain Interrupt. Supermapper interrupt request, active-low. An

open-drain output should be connected to an external pull-up

resistor.

AC25 APS_INTN — O

Open Drain APS Interrupt . Automatic protection switch interrupt request,

active-low. An open-drain output should be connected to an

external pull-up resistor .

Pin Symbol Type I/O Description

T24 RSTN — I

Pull-up Reset. Global reset, active-low. Initializes all internal registers

to their default state.

T25 PMRST — I/O

Pull-down Performance Monitor Reset. May be configured as an input

and then used to directly reset all the counters associated with

DS1/E1 performance monitoring. If an internal PM reset is

used, PMRST is configured as an output that indicates when a

PM reset occurred.

R5 TCK — I Test Clock. This signal provides timing for the boundary scan

and TAP controller. This signal should be static, except during

boundary-scan testing.

U5 TDI — I

Pull-up Test Data In. Data input for the boundary scan; sampled on

the rising edge of TCK.

W5 TMSN — I

Pull-up Test Mode Select (Active-Low ). Controls boundary-scan test

operations. TMS is sampled on the rising edge of TCK.

AB8 TRSTN — I

Pull-down Test Reset (Active-Low). This signal is an asynchronous

reset for the TAP controller.

V5 TDO — O Test Data Out. Updated on the falling edge of TCK. The TDO

output is high impedance, except when scanning out test data.

AB9 IC3STATEN — I

Pull-up Global Output Enable. All output and bidirectional buffers will

be high impedance when this input is low . Normally pulled high

internally.

Table 14. Microprocessor Interfaces (continued)

32 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

3.3.10 Test Pins

These pins are for factory test purposes only and must be connected as stated below for normal operation. They

are used to establish special configurations for testing, inserting test data, etc. For normal operation, they should

be left unconnected; each is equipped with a pull-up or pull-down to the inactive (normal operation) state.

Table 16. Test Pins

Table 17. CDR Power

Pin Symbol Type I/O Description

N5 SCAN_EN — I

Pull-down Test Only. Scan enable (active-high).

M5 SCAN_MODE — I

Pull-down Test Only. Serial scan input for testing (active-high).

P5 IDDQ — I

Pull up Test Only. IDDQ input (active-high).

AE14 BYPASS — I

Pull-down Test Only. Enables functional bypassing of the clock synthe-

sis with a test clock (active-high).

AF14 TSTPHASE — I

Pull-down Test Only. Controls bypass of 32 PLL-generated phases with

32 low-speed phases, generated by test logic (active-high).

AD14 ECSEL — I

Pull-down Test Only. Enables external test control of 155 MHz clock

phase selection through ETOGGLE and EXDNUP inputs

(active-high).

AC15 ETOGGLE — I

Pull-down Test Only. Moves 155 MHz clock selection one phase per

positive pulse > 20 ns. Active + pulse.

AE15 EXDNUP — I

Pull-down Test Only. Direction of phase changes.

0 = down.

1 = up.

AF15 TSTMODE — I

Pull-down Test Only. Enables CDR test mode.

AD15 TSTSFTLD — I

Pull-down Test Only. Enables CDR test mode shift register.

AE16,

AC16 TSTMUX[1:0] — O Test Only. CDR test mode output.

Pin Symbol Type I/O Description

AC9 VDDA_CDR — I Analog Power. Isolated analog power supply VDD for CDR.

AB12 VSSA_CDR — I Analog Ground. Isolated analog power supply VSS for CDR.

Table 18. LVDS Control Pins

Pin Symbol Type I/O Description

AF12

AE12 RESHI

RESLO —IResistor 1, 2. A 100 Ω 1% resistor should be connected between

these two pins as a reference for the LVDS input buffer termination.

AC11 REF10 — I Voltage Reference 1. 1.0 V reference voltage input.

AD12 REF14 — I Voltage Reference 2. 1.4 V reference voltage input.

33Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

3 Pin Information (continued)

Pin Symbol Type I/O Description

AB10 CTAPRH — — Center Tap 1. For RHSD P/N and RHSC P/N. An optional 0.1 µF

capacitor connected between CTAP pin and ground will improve the

common-mode rejection of the LVDS input buffers.

AE11 CTAPTH — — Center Tap 2. For THSD P/N and THSC P/N. An optional 0.1 µF

capacitor connected between CTAP pin and ground will improve the

common-mode rejection of the LVDS input buffers.

AB13 CTAPRP — — Center Tap 3. For RPSD155 P/N and RPSC155 P/N. An optional

0.1 µF capacitor connected between CTAP pin and ground will

improve the common-mode rejection of the LVDS input buffers.

Table 18. LVDS Control Pins (continued)

34 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

3 Pin Information (continued)

3.4 Outline Diagram

3.4.1 456-Pin PBGA

Dimensions are in millimeters.

5-6216(F)r.1

0.56 ± 0.06 1.17 ± 0.05 2.33 ± 0.21

SEATING PLANE

SOLDER BALL

0.60 ± 0.10

0.20

PWB

MOLD

COMPOUND

35.00 ± 0.20

35.00

± 0.20

+0.70

–0.00

30.00

+0.70

–0.00

30.00

A1 BALL

IDENTI FIER ZONE

25 SPACES @ 1.27 = 31.75

1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 2620

11 13 15 17 2119 23 25

CENTER ARRAY

FOR THERM AL

ENHANCEMENT

(OPTIONAL)

25 SPACES

@ 1.27 = 31.75

A1 BAL L

CORNER

0.75 ± 0.15

35Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

4 Electr ic al Ch ar ac te ri st ics

Table of Con t en ts

Contents Page

4 Electrical Characteristics .................................................................................................................................. 35

4.1 Absolute Maximum Ratings..........................................................................................................................36

4.2 Handling Precautions ...................................................................................................................................36

4.3 Operating Conditions....................................................................................................................................37

4.4 Logic Interface Characteristics.....................................................................................................................37

4.5 LVDS Interface Characteristics ....................................................................................................................38

Figures Page

Figure 5. Single-Ended Input Specification .............................................................................................................37

Tables Page

Table 19. Absolute Maximum Ratings .....................................................................................................................36

Table 20. Power Consumption.................................................................................................................................36

Table 21. Handling Precaution.................................................................................................................................36

Table 22. Recommended Operating Conditions......................................................................................................37

Table 23. Logic Interface Characteristics.................................................................................................................37

Table 24. LVDS Interface Characteristics................................................................................................................38

36 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

4 Elec trical Char ac te ristics (continued)

4.1 Absolute Maximum Ratings

Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso-

lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess

of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended

periods can adversely affect device reliability.

* When measuring power consumption of the Supermapper, the following blocks are powered on: TMUX, SPEMPR, VTMPR , DJA, FRAME R.

MPCLK = 25 MHz.

4.2 Handling Precautions

Although electrostatic discharge (ESD) protection circuitry has been designed into this device, proper precautions

must be taken to avoid exposure to ESD and electrical overstress (EOS) during all handling, assembly, and test

operations. Agere employs both a human-body model (HBM) and a charged-device model (CDM) qualification

requirement in order to determine ESD susceptibility limits and protection design evaluation. ESD voltage thresh-

olds are dependent on the circuit parameters used in each of the models, as defined by JEDEC's JESD22-A114

(HBM) and JESD22-C101 (CDM) standards.

Table 19. Absolute Maximum Ratings

Parameter Symbol Min Max Unit

dc Supply Voltage Range VDD –0.5 4.6 V

Storage Temperature Range Tstg –65 125 °C

Ambient Operating Temperature Range TA–40 85 °C

Maximum Voltage (digital input pins) — — 5.25 V

Minimum Voltage (digital input pins) — –0.3 — V

Table 20. Power Consumption

Parameter Typical Power* Unit

VDD = 3.5 V, TA = 25 °C 3.185 W

VDD = 3.3 V, TA = 25 °C 2.772 W

VDD = 3.0 V, TA = 25 °C 2.190 W

Table 21. Handling Precaution

Device Minimum HBM Threshold Minimum CDM Threshold

Corner Non-Corner

TMXF28155 2000 V 500 V 500 V

37Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

4 Electr ic al Ch ar ac te ri st ics (continued)

4.3 Operating Cond itions

The following tables list the voltages required for proper operation of the TMXF28155 device, along with their toler-

ances.

Table 22. Recommended Operating Conditions

* Internal reference voltage is used if S MP R_LVD S_RE F_SEL = 1 (Table 80 on page 72), or else external voltage is used.

4.4 Logic Interface Characteristics

Table 23. Logic Interface Characteristics

The input specification for the remaining (nonbalanced) inputs are specified in Figure 5.

5-6032(F)r.2

Figure 5. Single-Ended Input Specification

Parameter Symbol Min Typ Max Unit

Power VDD 3.14 3.3 3.47 V

Ground VSS —0.0 — V

Input Voltage, High VIH VDD – 1.0 — 5.25 V

Input Voltage, Low VIL VSS —1.0V

1.0 V: LVDS Reference* LVDS_REF10 — 1.0 — V

1.4 V: LVDS Reference* LVDS_REF14 — 1.4 — V

Parameter Symbol Test Conditions Min Max Unit

Input Leakag e IL——1.0µA

Output Current:

Low

High IOL

IOH —

——

—4.0

4.0 mA

Output Voltage:

Low

High VOL

VOH —

—VSS

VDD – 0.5 0.5

3.465 V

Input Capaci tanc e CI— —1.5pF

VIL

38 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

4 Elec trical Char ac te ristics (continued)

4.5 LVDS Interface Character is tics

3.3 V ± 5% VDD, 0 °C—125 °C, slow—fast process.

Table 24. LVDS Interface Characteristics

* Buffer will not produce output transition when input is open-circuited.

Parameter Symbol Test Conditions Min Typ Max Unit

Input Buffer Par ameters

Input Voltage Range, VIA or VIB VIVGPD < 925 mV, dc—1 MHz 0.0 1.2 2.4 V

Input Differential Threshold VIDTH VGPD < 925 mV, 311 MHz –100 — 100 mV

Input Differential Hysteresis VHYST (+VIDTH) – (–VIDTH)———*mV

Receiver Differential Input

Impedance RIN With build-in termination,

center-tapped 80 100 130 Ω

Output Buffer Parameters

Output Voltage:

Low (VOA or VOB)

High (VOA or VOB)VOL

VOH RLOAD = 100 Ω ± 1%

RLOAD = 100 Ω ± 1% —

0.925 —

—1.475

—V

Output Differential Voltage VOD RLOAD = 100 Ω ± 1% 0.25 — 0.40 V

Output Offset Voltage VOS RLOAD = 100 Ω ± 1% 1.125 — 1.275 V

Output Impedance, Single Ended ROVCM = 1.0 V and 1.4 V 40 50 60 Ω

RO Mismatch Between A and B ∆ROVCM = 1.0 V and 1.4 V — — 10 %

Change in Differential Voltage

Between Complementary States ∆VOD RLOAD = 100 Ω ± 1% — — 25 mV

Change in Output Offset Voltage

Between Complementary States ∆VOS RLOAD = 100 Ω ± 1% — — 25 mV

Output Current ISA, ISB Driver shorted to VSS 6.8 — 24 mA

Output Current ISAB Dr ivers shorted together — — 12 mA

39Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics

Table of Con t en ts

Contents Page

5 Timing Characteristics ...................................................................................................................................... 39

5.1 TMUX Block Timing......................................................................................................................................41

5.2 DS3 Timing...................................................................................................................................................45

5.3 M13 Timing...................................................................................................................................................46

5.4 VT Mapper Timing........................................................................................................................................47

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing ............................................................... 47

5.5 Concentration Highway (CHI) Timing...........................................................................................................48

5.6 Parallel System Bus Timing .........................................................................................................................49

5.7 NSMI Timing (6-Pin) (to/from Framer)..........................................................................................................50

5.8 NSMI Timing (7-Pin) (to/from Framer)..........................................................................................................50

5.9 CHI Interface Timing ....................................................................................................................................51

5.10 PSB Interface Timing .................................................................................................................................52

5.11 Framer DS1/E1 Interface Timing................................................................................................................53

5.12 DJA DS1/E1 Interface Timing ....................................................................................................................54

5.13 M13 DS1/E1 Interface Timing ....................................................................................................................55

5.14 Microprocessor Interface Timing................................................................................................................56

5.14.1 Sync hrono us Mode ............... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ............................. 56

5.14.2 Asyn ch ronou s Mode .......................... ...... ....... ...... ...... ....... ................... ....... ...... ....... ...................... 59

5.15 General-Purpose Interface Timing.............................................................................................................62

6 Ordering Information ........................................................................................................................................ 63

Figures Page

Figure 6. Generic Clock Timing...............................................................................................................................41

Figure 7. Generic Interface Data Timing .................................................................................................................43

Figure 8. DS3DATAOUTCLK Timing ......................................................................................................................45

Figure 9. VT Mapper Transmit Path Overhead Detailed Timing .............................................................................47

Figure 10. VT Mapper Receive Path Overhead Detailed Timing ............................................................................47

Figure 11. CHI Transmit I/O Timing.........................................................................................................................48

Figure 12. CHI Receive I/O Timing..........................................................................................................................48

Figure 13. Parallel System Bus Interface Transmit I/O Timing................................................................................49

Figure 14. Parallel System Bus Interface Receive I/O Timing.................................................................................49

Figure 15. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)..................................56

Figure 16. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)..................................57

Figure 17. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0) .............59

Figure 18. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)................................61

Tables Page

Table 25. High-Speed Input Clock Specifications....................................................................................................41

Table 26. Output Clock Specifications.....................................................................................................................42

Table 27. Input Timing Specifications......................................................................................................................43

Table 28. Output Timing Specifications ...................................................................................................................45

Table 29. DS3 Input Clock Specifications................................................................................................................45

Table 30. Input Timing Specifications......................................................................................................................45

Table 31. Output Timing Specifications ...................................................................................................................45

Table 32. M13 Clock Specifications.........................................................................................................................46

Table 33. Input Timing Specifications......................................................................................................................46

Table 34. Output Timing Specifications ...................................................................................................................46

Table 35. VT Mapper Receive Path Overhead Detailed Timing..............................................................................47

40 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table of Conten ts (continued)

Tables Page

Table 36. CHI Transmit Timing Characteristics .......................................................................................................48

Table 37. CHI Receive Timing Characteristics ........................................................................................................48

Table 38. PSB Interface Transmit Timing Characteristics .......................................................................................49

Table 39. PSB Interface Receive Timing Characteristics ........................................................................................49

Table 40. NSMI Input/Output Clock Specifications..................................................................................................50

Table 41. Input Timing Specifications......................................................................................................................50

Table 42. Output Timing Specifications ...................................................................................................................50

Table 43. NSMI Output Clock Specifications...........................................................................................................50

Table 44. NSMI Input Timing Specifications............................................................................................................51

Table 45. NSMI Output Timing Specifications .........................................................................................................51

Table 46. CHI Interface Clock Specifications...........................................................................................................51

Table 47. CHI Interface Input Ti ming Specifications................................................................................................51

Table 48. CHI Interface Output Timing Specifications.............................................................................................52

Table 49. PSB Interface Clock Specifications..........................................................................................................52

Table 50. PSB Interface Input Timing Specifications...............................................................................................52

Table 51. PSB Interface Output Timing Specifications............................................................................................52

Table 52. Framer DS1/E1 Interface Clock Specifications........................................................................................53

Table 53. Framer DS1/E1 Interface Input Timing Specifications.............................................................................53

Table 54. Framer DS1/E1 Interface Output Timing Specifications ..........................................................................53

Table 55. DJA DS1/E1 Interface Clock Specifications ............................................................................................54

Table 56. DJA DS1/E1 Interface Input Timing Specifications..................................................................................54

Table 57. DJA DS1/E1 Interface Output Timing Specifications...............................................................................54

Table 58. M13 DS1/E1 Interface Clock Specifications ...........................................................................................55

Table 59. M13 DS1/E1 Interface Input Timing Specifications..................................................................................55

Table 60. M13 DS1/E1 Interface Output Timing Specifications...............................................................................55

Table 61. Microprocessor Interface Synchronous Write Cycle Specifications.........................................................57

Table 62. Microprocessor Interface Synchronous Read Cycle Specifications.........................................................58

Table 63. Microprocessor Interface Asynchronous Write Cycle Specifications.......................................................60

Table 64. Microprocessor Interface Asynchronous Read Cycle Specifications.......................................................62

Table 65. Input Timing Specifications......................................................................................................................62

Table 66. Output Timing Specifications ...................................................................................................................63

41Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.1 TMUX Block Ti ming

The TMUX (STS-N/STM-1) timing parameters can be grouped separately for clocks, inputs, and outputs. Table 25

shows the input clock specifications for this device. The rise and fall times refer to the transition times from 10% to

90% of full swing.

For definitions of the signal names, see Section 3, Pin Information on page 10.

Table 25. High-Speed Input Clock Specifications

Note: When the true and complement inputs are float ing, the input buffer will not oscillate.

5-9077(F)

Figure 6. Generic Clock Timing

Symbol Parameter Signal Name 155 Clock 51 Clock Unit

Min Nominal Max Min Nominal Max

FCK Operating

Frequency THSCP/N — 155.52 ± 30 ppm — — 51.84 ± 50 ppm — MHz

RHSCP/N — 155.52 ± 30 ppm — — 51.84 ± 50 ppm — MHz

RPSC155P/N — 155.52 ± 30 ppm — — MHz

tCK Clock

Period THSCP/N — 6.43 ± 0.4% — — 19.29 ± 0.4% — ns

RHSCP/N — 6.43 ± 0.5% — — 19.29 ± 0.5% — ns

RPSC155P/N — 6.43 ± 0.5% — — ns

tCLKHI Clock Pulse

High Time THSCP/N 2.5 — 3.9 7.8 — 11.6 ns

RHSCP/N 2.5 — 3.9 7.8 — 11.6 ns

RPSC155P/N 2.5 — 3.9 — ns

tR Rise Time THSCP/N — — 1.5 — — 5.0 ns

RHSCP/N — — 1.5 — — 5.0 ns

RPSC155P/N — — 1.5 — ns

tF Fall Time THSCP/N — — 1.5 — — 5.0 ns

RHSCP/N — — 1.5 — — 5.0 ns

RPSC155P/N — — 1.5 — ns

tCLKHI

tCK

42 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

The output clock specifications are shown in Table 26.

Table 26. Output Clock Specifications

* The specifications for the table are with all loopbacks disabled.

Note: Any of the telecom signals being used as inputs (slave Supermapper) need to meet these same output clock

specifications.

Signal Name Reference CLK*Frequency Clock Pulse High

Time (tCLKHI)Test

Condition Max Rise

Time (tR)Max Fall

Time (tF)Unit

TLSCLK THSCP/N 19.44 MHz 24.43—27.00 CL = 50 pF 3.5 3.5 ns

TTOACCLK THSCP/N 5.184 MHz 91.62—101.30 CL = 15 pF 3.5 3.5 ns

RLSCLK RHSCP/N or

Internal CDR Clock 19.44 MHz 24.43—27.00 CL = 50 pF 3.5 3.5 ns

RTOACCLK RHSCP/N or

Internal CDR Clock 5.184 MHz 91.62—101.30 CL = 15 pF 3.5 3.5 ns

TPSC155P/N THSCP/N 155.5 MHz 3.119—3.311 CL = 15 pF 1.5 1.5 ns

TPOACCLK THSCP/N 5.184 MHz 91.62—101.30 CL = 15 pF 3.5 3.5 ns

RPOACCLK RHSCP/N 5.184 MHz 91.62—101.30 CL = 15 pF 3.5 3.5 ns

TLSC52 THSCP/N 51.84 MHz 9.162—10.130 CL = 30 pF 3.0 3.0 ns

RLSC52 RHSCP/N 51.84 MHz 9.162—10.130 CL = 30 pF 3.0 3.0 ns

43Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

Table 27. Input Timing Specifications

* Register 0x00010, bit 2, SMPR_RETIME_CKLK_EDGE.

Figure 7. Generic Interface Dat a Timing

Input Name Reference CLK Min Setup Time (tS) Min Hold Time (tH)Unit

Transmit Signals

THSSYNCP /N THSC ↑3.5 0.0 ns

TLSDATA[7:0] TLSCLK ↑5.0 0.0 ns

TLSPAR TLSCLK ↑5.0 0.0 ns

TLSSPE TLSCLK ↓5.0 0.0 ns

TLSJ0J1V1 TLSCLK ↓5.0 0.0 ns

TLSV1 TLSCLK ↓5.0 0.0 ns

TLSSYNC52 TLSC52 ↓4.0 2.5 ns

TTOACDATA TTOACCLK ↑10.0 3.5 ns

TPOACDATA TPOACCLK ↑10.0 1.0 ns

Receive Signals

RHSDP/N RHSCP/N ↑↓*2.0 0.0 ns

RPSD155P/N RPSC155P/N↑2.0 0.0 ns

RLSDATA[7:0] RLSCLK ↓4.0 0.0 ns

RLSPAR RLSCLK ↓4.0 0.0 ns

RLSSPE RLSCLK ↓4.0 0.0 ns

RLSJ0J1V1 RLSCLK ↓4.0 0.0 ns

RLSV1 RLSCLK ↓4.0 0.0 ns

RLSSYNC52 RLSC52 ↓4.0 3.0 ns

Miscellaneous Signals

LOSEXT NA ASYNC ASYNC —

AUTO_AIS[3:1] NA ASYNC ASYNC —

CLOCK

DATA

CLOCK

DATA

tSU tH

tPD

44 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table 28. Output Timing Specifications

* Register 0x00010, bit 1, SMPR_TELECOMBUS_EDGE.

† Propagation delay skew, tPLH – tPHL, is ± 200 ps. Negative propagation delay indicates that output comes out ahead of reference clock.

Output Name Reference CLK Test

Conditions Propagation Delay†Unit

tPD

Min Max

Transmit Signals

THSDP/N THSCP/N ↑CL = 15 pF 2.6 8.0 ns

TPSD155P/N TPSC155P/N↑CL = 15 pF 0.6 2.9 ns

TLSDATA[7:0] TLSCLK ↑↓* CL = 50 pF 4.0 12.0 ns

TLSPAR TLSCLK ↑↓* CL = 50 pF 4.0 12.0 ns

TLSSPE TLSCLK ↑CL = 50 pF 4.0 10.5 ns

TLSJ0J1V1 TLSCLK ↑CL = 50 pF 4.0 10.5 ns

TLSV1 TLSCLK ↑CL = 50 pF 4.0 10.5 ns

TLSSYNC52 TLSC52 ↑CL = 30 pF 0.0 2.0 ns

TTOACSYNC TTOACCLK ↑CL = 15 pF –2.0 30.0 ns

TPOACSYNC TPOACCLK ↑CL = 15 pF –2.0 30.0 ns

Receive Signals

RLSDATA[7:0] RLSCLK ↑CL = 50 pF 5.5 12.0 ns

RLSPAR RLSCLK ↑CL = 50 pF 5.5 12.0 ns

RLSSPE RLSCLK ↑CL = 50 pF 5.5 12.0 ns

RLSJOJ1V1 RLSCLK ↑CL = 50 pF 5.5 12.0 ns

RLSVI RLSCLK ↑CL = 50 pF 5.5 12.0 ns

RLSSYNC52 RLSC52 ↑CL = 30 pF 0.5 3.0 ns

RTOACSYNC RTOACCLK ↑CL = 15 pF –2.0 30.0 ns

RTOACDATA RTOACCLK ↑CL = 15 pF –2.0 30.0 ns

RPOACSYNC RPOACCLK ↑CL = 15 pF –2.0 30.0 ns

RPOACDATA RPOACCLK ↑CL = 15 pF –2.0 30.0 ns

RHSFSYNCN RLSCLK ↑CL = 30 pF –1.0 8.0 ns

Miscellaneous Signals

AUTO_AIS[3:1] NA — ASYNC ASYNC —

45Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.2 DS3 Timing

Table 29. DS3 Input Clock Specifications

Figure 8. DS3DATAOUTCLK Timing

Table 30. Input Timing Specifications

* Register 0x100A1, bit 0, M13_RDS3_EDGE, see Table 299 on page 227. Register 0x30019, bit 5, SPE_TDS3CLK_EDGE, see Table 163 on

page 143.

Table 31. Output Timing Specifications

Symbol Parameter Signal Name Min Max Unit

FCK Clock Fre quen cy DS3D ATAIN C LK

DS3DATAOUTCLK — 44.736 ± 50 ppm MHz

tCK Clock Period DS3DATAINCLK

DS3DATAOUTCLK — 22.353 ns

tCLKHI Clock Pulse High Time DS3DATAINCLK

DS3DATAOUTCLK 6

616

12 ns

tRRise Time DS3DATAINCLK

DS3DATAOUTCLK 02ns

tFFall Time DS3DATAINCLK

DS3DATAOUTCLK 02ns

Input Name Reference CLK Min Setup Time (tS) Min Hold Time (tH) Unit

DS3POSDATAIN DS3DATAINCLK ↑↓* 40ns

DS3NEGDATAIN DS3DATAINCLK ↑↓*4 0 ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

DS3POSDATAOUT DS3DATAOUTCLK ↑CL = 15 pF 2 6.5 ns

DS3NEGDATAOUT DS3DATAOUTCLK ↑CL = 15 pF 2 6.5 ns

WCLKHI

WCK

46 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

5.3 M13 Timin g

Table 32. M13 Clock Specifications

Table 33. Input Timing Specifications

Table 34. Output Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency TCBCLK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

2.048

1.544

—

93.983 gapped

28.195 gapped

32.768

24.704

6.312

93.983

28.195

—

65.536

49.408

—

kHz

MHz

kHz

tCLKHI Clock Pulse

High Time TCBCLK

TDLCLK

RCBCLK

RDLCLK

212.19

223.53

250.77

tRRise Time TCBCLK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

tFFall Time TCBCLK

TDLCLK

E1XCLK

DS1XCLK

DS2AISCLK

RCBCLK

RDLCLK

—

Input Name Reference CLK Setup Time (tS) Hol d Time (tH)Unit

Min Max Min Max

TCBDATA TCBCLK ↑50 — 0 — ns

TDLDATA TDLCLK ↑50 — 0 — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

TCBSYNC TCBCLK ↑CL = 15 pF 0.5 10 ns

RCBSYNC RCBCLK ↑CL = 15 pF 0.5 10 ns

RCBDATA RCBCLK ↑CL = 15 pF 0.5 10 ns

RDLDATA RDLCLK ↑CL = 15 pF 2 10 ns

47Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.4 VT Mapper Ti ming

5.4.1 VT Mapper Lower-Order Path Overhead Interface Timing

Table 35. VT Mapper Receive Path Overhead Detailed Timing

* tSD, tHD ⇒ LOPOH_CLK ↓.

† tSV, tHV ⇒ LOPOH_CLK ↓.

‡ tPDV, tPDD ⇒ LOPOH_CLK ↑.

5-9078(F)

Figure 9. VT Mapper Transmit Path Overhead Detailed T iming

5-9079(F)

Figure 10. VT Mapper Receive Path Overhead Detailed Timing

Symbol Parameter Min Max Unit

FCK Clock Frequency 6.48 6.48 MHz

tCK Clock Period 154 154 ns

tCLKHI Clock Pulse High Time 50 75 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tSD * LOPOH Data Setup Time 5 — ns

tHD * LOPOH Data Hold Time 2.0 — ns

tSV †LOPOH Valid Signal Setup Time 5 — ns

tHV †LOPOH Valid Signal Hold Time 3.7 — ns

tPDV ‡Clock to LOPOH Valid Signal Out 2.0 10.0 ns

tPDD ‡Clock to LOPOH Data Out 2.0 10.0 ns

LOPOHCLKIN

LOPOHVALIDIN

LOPOHDATAIN

tPDV

tPDD

LOPOHCLKOUT

LOPOHVALIDOUT

LOPOHDATAOUT

tCK

48 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

5.5 Concentration Highway (CHI) Timing

Table 36 and Table 37 with Figure 11 and Figure 12, respectively, illustrate the detailed CHI timing for clock, data,

and frame synchronization.

Table 36. CHI Transmit Timing Characteristics

* Fck can be either 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.

† tS, tH, and tPD,⇒ LINETXCLK29 ↑↓ (Register 0x80050, bit 4, FRM_TFSCKE, see Table 359 on page 261).

5-9080(F)

Figure 11. CHI Transmit I/O Timing

Table 37. CHI Receive Timing Characteristics

CK can be either 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.

† LINERXSYNC29 ↑↓ (Register 0x80150, bit 13, FRM_RFSCKE, see Tab le 3 67 on pag e 2 65 ).

5-9081(F)

Figure 12. CHI Receive I/O Timing

Symbol Parameter Min Max Unit

FCK Clock Freq uen cy * 2.048 16.38 4 M Hz

tCK Clock Peri od 488.2 61.04 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tS†Frame Sync Setup Time 35 — ns

tH†Frame Sync Hold Time 0 — ns

tPD†Clock to CHI Data Delay — 25 ns

Symbol Parameter Min Max Unit

FCK Clock Frequency* 2.048 16.384 MHz

tCK Clock Period 488.2 61.04 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tSSYNC†Frame Sync Setup Time 30 — ns

tHSYNC†Frame Sync Hold T ime 3.4 — ns

tSDATA†CHI Data Setup Time 25 — ns

tHDATA†CHI Data Hold Time 0 —ns

LINETXCLK29

LINETXSYNC29

LINETXSYNC[28:1]

CLOCK

FRAME SYNC

DATA

1/2t

HDATA

LINERXCLK29

LINERXSYNC29

LINERXSYNC[28:1]

CLOCK

FRAME SYNC

DATA

SSYNC

HSYNC

SDATA

1/2 t

49Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.6 Parallel System Bus Timing

Table 38 and Table 39 with Figure 13 and Figure 14, respectively, show the transmit and receive timing. In the

transmit direction (to the system interface), the frame sync is sampled and the data is clocked out on the rising

edge of the clock. In the receive direction (from the switch), the data and frame sync are sampled on the rising

edge of the clock.

Table 38. PSB Interface Transmit Timing Characteristics

* LINETXCLK29 ↑↓ (Register 0x80050, bit 4, FR M _T FSC KE , se e Table 359 on page 261).

5-9082(F)

Figure 13. Parallel System Bus Interface Transmit I/O Timing

Table 39. PSB Interface Receive Timing Characteristics

* LINERXCLK29 ↑↓ (Register 0x80150, bit 13, FRM_RFSCKE, see Tab l e 3 67 on pag e 265).

5-9083(F)

Figure 14. Parallel System Bus Interface Receive I/O Timing

Symbol Parameter Min Max Unit

FCK Clock Frequency 19.44 19.44 MHz

tCK Clock Period 51.44 51.44 ns

tRClock Rise T ime 0 3 ns

tFClock Fall Time 0 3 ns

tS*Frame Sync Setup Time 8 — ns

tH*Frame Sync Hold Time 0 — ns

tPD*Clock to PSB Out Delay 3 10 ns

Symbol Parameter Min Max Unit

FCK Clock Freq uen cy 19.4 4 19.44 MHz

tCK Clock Peri od 51.44 51.4 4 ns

tRClock Rise Time 0 3 ns

tFClock Fall Time 0 3 ns

tSSYNC* Frame Sync Setup Ti me 8 — ns

tHSYNC* Frame Sync Hold Time 0 — ns

tSDATA* PSB to Clock Setup Time 8 — ns

tHDATA* PSB Hold Time from Clock 2.8 —ns

DEV #0, TS #1, DEV #0, TS #1,

tPD

STUFFED TS STUFFED TS

6 (3) STUFFED TS IN DS1 (E1)

tHtS

LINETXCLK29

LINETXSYNC29

LINETXSYNC[16:1]

CLOCK

FRAME SYNC

DATA LINK #0 LINK #1

tCK

DATA SAMPLED

tSDATA tHDATA

DEV #0, TS #1, DEV #0, TS #1,

STUFFED TS STUFFED TS

tHSYNCtSSYNC

LINERXCLK29

LINERXSYNC29

LINERXSYNC[16:1]

CLOCK

FRAME SYNC

DATA LINK #0 LINK #1

tCK

50 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

5.7 NSMI Tim ing (6-Pin) (to/from Framer)

Table 40. NSMI Input/Output Clock Specifications

Table 41. Input Timing Specifications

Table 42. Output Timing Specifications

5.8 NSMI Timing (7-Pin) (to/from Framer)

Table 43. NSMI Output Clock Specifications

Symbol Parameter Signal Name I/O Min Nom Max Unit

FCK Clock

Frequency LINE_TXCLK29

LINE_RXCLK29 Output

Input –50 ppm

–50 ppm 51.84

51.84 50 ppm

50 ppm MHz

MHz

tCK = 1/FCK Clock

Period LINE_TXCLK29

LINE_RXCLK29 Output

Input —

—19.29

19.29 —

—ns

tCKHI Clock Pulse

High Time LINE_TXCLK29

LINE_RXCLK29 Output

Input 6

6—

—12

12 ns

tRRise Time LI NE_TXCLK29

LINE_RXCLK29 Output

Input —

——

—3

3ns

tFFall Time LINE_TXCLK29

LINE_RXCLK29 Output

Input —

——

—3

3ns

Input Name Reference CLK Setup Time (tS)Hold Time (t

H)Unit

Min Max Min Max

LINE_RXDATA29 LINE_RXCLK29 ↑3—0—ns

LINE_RXSYNC29 LINE_RXCLK29 ↑ 3 — 0.5 — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINE_TXDATA29 LINE_TXCLK29 ↑CL = 15 pF 0.1 3.0 ns

LINE_TXSYNC29 LINE_TXCLK29 ↑CL = 15 pF 0.1 5.0 ns

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

–50 ppm

51.84/44.736

50 ppm

MHz

tCK = 1/FCK Clock

Period LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

19.29/22.35

—

tCKHI Clock Pulse

High T ime LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

1/2 tck

—

tRRise T ime LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

tFFall Time LINE_TXCLK29

LINE_RXCLK29

RXDATAEN

—

51Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

Table 44. NSMI Input Timing Specifications

Table 45. NSMI Output Timing Specifications

5.9 CHI Interface Timing

Table 47. CHI Interface Input Timing Specifications

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

MinMaxMinMax

LINE_RXDATA29 LINE_RXCLK29 ↑3.0 — 0 — ns

LINE_RXSYNC29 LINE_RXCLK29 ↑ 3.0 — 0.5 — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINE_TXDATA29 LINE_TXCLK29 ↑CL = 15 pF 0.1 3.0 ns

LINE_TXSYNC29 LINE_TXCLK29 ↑CL = 15 pF 0.1 5.0 ns

TXDATAEN LINETXCLK29 ↑CL = 15 pF –0.6 0.2 ns

Table 46. CHI Interface Clock Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency LINERXDATA29

LINERXCLK29

LINETXCLK29

–130 ppm

–50 ppm

1.544

or 2.048

2.048

or 4.096

or 8.192

or 16.384

2.048

or 4.096

or 8.192

or 16.384

130 ppm

50 ppm

MHz

tCK = 1/FCK Clock

Period LINERXDATA29

LINERXCLK29

LINETXCLK29

— 647.67 or 488.28

488.28, or 244.14

or 122.07, or 61.04

488.28, or 244.14

or 122.07, or 61.04

—ns

tCKHI Clock Pulse

High Time LINERXDATA29

LINERXCLK29

LINETXCLK29

— 1/2 tck

1/2 tck

—ns

tRRise Time LINERXDATA29

LINERXCLK29

LINETXCLK29

—

tFFall Time LINE RXD ATA29

LINERXCLK29

LINETXCLK29

—

Input Name Reference CLK Setup Time (tS) Hold Time (tH)Unit

MinMaxMinMax

LINERXSYNC[28:1] LINERXCLK[28:1] ↑↓ 25 — 0 — ns

LINERXSYNC29 LINERXCLK29 ↑↓ 30 — 3.4 — ns

LINETXSYNC29 LINETXCLK29 ↑↓ 35 — 1.6 — ns

52 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table 48. CHI Interface Output Timing Specifications

5.10 PSB Interface Timing

Table 50. PSB Interface Input Timing Spec ifications

Table 51. PSB Interface Output Timing Specifications

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINETXSYNC[28:1] LINETXCLK29 ↑↓ CL = 15 pF — 25 ns

Table 49. PSB Interface Clock Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency LINERXDATA29

LINERXCLK29

LINETXCLK29

–130 ppm

–50 ppm

1.544

or 2.048

19.44

130 ppm

50 ppm

MHz

tCK = 1/FCK Clock

Period LINERXDATA29

LINERXCLK29

LINETXCLK29

— 647.67

or 488.28

51.44

—ns

tCKHI Clock Pulse

High Time LINERXDATA29

LINERXCLK29

LINETXCLK29

— 1/2 tck

1/2 tck

—ns

tRRise Time LINERXDATA29

LINERXCLK29

LINETXCLK29

—

tFFall Time LINERXDATA29

LINERXCLK29

LINETXCLK29

—

Input Name Reference CLK Setup Time ( tS) Hold Time (tH)Unit

Min Max Min Max

LINERXSYNC[16:1] LINERXCLK29 ↑↓ 8—2.8—ns

LINERXSYNC29 LINERXCLK29 ↑↓ 8—0—ns

LINETXSYNC29 LINETXCLK29 ↑↓ 8—0—ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINETXSYNC[16:1] LINETXCLK29 ↑↓ CL = 15 pF 3 10 ns

53Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.11 Framer DS1/E1 Interface Timing

Table 52. Framer DS1/E1 Interface Clock Specifications

Table 53. Framer DS1/E1 Interface Input Timing Specifications

Table 54. Framer DS1/E1 Interface Output Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency TLSC52

LINERXCLK[29:1]

LINETXCLK[29:1]

–50 ppm

–130 ppm

–50 ppm

–130 ppm

–50 ppm

51.84

1.544

or 2.048

1.544

or 2.048

50 ppm

130 ppm

50 ppm

130 ppm

50 ppm

MHz

tCK = 1/Fck Clock

Period TLSC52

LINERXCLK[29:1]

LINETXCLK[29:1]

—19.29

647.67

or 488.28

647.67

or 488.28

—ns

tCKHI Clock Pulse

High Time TLSC52

LINERXCLK[29:1]

LINETXCLK[29:1]

— 1/2 tck

1/2 tck

—ns

tRRise Time TLSC52

LINERXCLK[29:1]

LINETXCLK[29:1]

—

tFFall Time TLSC52

LINERXCLK[29:1]

LINETXCLK[29:1]

—

Input Name Reference CLK Setup T ime (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[29:1] LINERXCLK[29:1] ↑↓ 12.0 — 9.0 — ns

LINERXSYNC[29:1] LINERXCLK[29:1] ↑↓ 12.0 — 9.0 — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINETXDATA[29:1] LINETXCLK[29:1] ↑↓ CL = 15 pF 0.5 10 ns

LINETXSYNC[29:1] LINETXCLK[29:1] ↑↓ CL = 15 pF 0.5 11 ns

54 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

5.12 DJA DS1/E1 Interface Timing

Table 55. DJA DS1/E1 Interface Clock Specifications

Table 56. DJA DS1/E1 Interface Input Timing Specifications

Table 57. DJA DS1/E1 Interface Output Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency LINERXCLK[29:1]

LINETXCLK[29:1]

–130 ppm

–50 ppm

–130 ppm

–50 ppm

1.544

or 2.048

1.544

or 2.048

130 ppm

50 ppm

130 ppm

50 ppm

MHz

tCK = 1/Fck Clock

Period LINERXCLK[29:1]

LINETXCLK[29:1]

— 647.67

or 488.28

647.67

or 488.28

—ns

tCKHI Clock Pulse

High Time LINERXCLK[29:1]

LINETXCLK[29:1]

— 1/2 tck

1/2 tck

—ns

tRRise Time LINERXCLK[29:1]

LINETXCLK[29:1]

—

tFFall Ti me LINERXCLK[29:1]

LINETXCLK[29:1]

—

Input Name Reference CLK Setup T ime (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[29:1] LINERXCLK[29:1] ↑↓ NA — NA — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINETXDATA[29:1] LINETXCLK[29:1] ↑↓ CL = 15 pF –4.0 4.0 ns

55Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.13 M13 DS1/E1 Interface Ti ming

Table 58. M13 DS1/E1 Interface Clock Specifications

Table 59. M13 DS1/E1 Interface Input Timing Speci fications

Table 60. M13 DS1/E1 Interface Output Timing Specifications

Symbol Parameter Signal Name Min Nom Max Unit

FCK Clock

Frequency LINERXCLK[29:1]

LINETXCLK[29:1]

–130 ppm

–50 ppm

–130 ppm

–50 ppm

1.544

or 2.048

1.544

or 2.048

130 ppm

50 ppm

130 ppm

50 ppm

MHz

tCK = 1/Fck Clock

Period LINERXCLK[29:1]

LINETXCLK[29:1]

— 647.67

or 488.28

647.67

or 488.28

—ns

tCKHI Clock Pulse

High Time LINERXCLK[29:1]

LINETXCLK[29:1]

— 1/2 tck

1/2 tck

—ns

tRRise Time LINERXCLK[29:1]

LINETXCLK[29:1]

—

tFFall Ti me LINERXCLK[29:1]

LINETXCLK[29:1]

—

Input Name Reference CLK Setup T ime (tS) Hold Time (tH)Unit

Min Max Min Max

LINERXDATA[29:1] LINERXCLK[29:1] ↑↓ 12.0 — 8.0 — ns

Output Name Reference CLK Test Conditions Propagation Delay tPD Unit

Min Max

LINETXDATA[29:1] LINETXCLK[29:1] ↑↓ CL = 15 pF –5.0 2.0 ns

56 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

5.14 Microprocessor Interface Timing

5.14.1 Synchronous Mode

The synchronous microprocessor interface mode is selected when MPMODE (pin AD17) = 1. Interface timing for

the synchronous mode write cycle is given in Figure 15 and in Table 61, and for the read cycle in Figure 16 and in

Table 62.

5-7659(F)a

Figure 15. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)

MPCLK 16 MHz minimum to 60* MHz maximum frequency.

ADDR [19:0] The address will be available throughout the entire cycle.

DATA[15:0] Data will be available during cycle T1.

RWN (Input) The read (H) write (L) signal is always high except during a write cycle.

CSN (Input) Chip select is an active-low signal.

DTN (Output) Data transfer acknowledge is active-low for one clock and then driven high before entering a high-

impedance state. (This is done with an I/O pad using the input as feedback to qualify the 3-state

term.) DTN will become 3-stated when CSN is high. Typically, DTN is active 4 or 5 MPCLK cycles

after ADSN is low.

ADSN (Input) Address strobe is active-low. ADSN must be 1 MPCLK clock period wide.

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. For example, a 9 ns

setup time would limit MPCLK to 40 MHz for reliable DTN detection.

MPCLK

ADDR[19:0]

CSN

ADSN

RWN

DATA[15:0]

DTN

(60 MHz MAX)

(INPUT)

tADSNVS

tWS

tDTNVPD

tWS

tCSNVS

tWS

TCLK T1 T2 T3 Tn – 2 Tn – 1 Tn

tAIPD

tAPD

tDTNIPD

HIGH ZHIGH Z tADSNVDTF

57Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

Table 61. Microprocessor Interface Synchronous Write Cycle Specifications

(See Figure 15 on page 56 for the timing diagram.)

5-7660(F).a

Figure 16. Microprocessor Interface Synchronous Read Cycle (MPMODE (Pin AD17) = 1)

MPCLK 16 MHz minimum to 60* MHz maximum frequency.

ADDR [19:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns

high.

DATA [15:0] Read data is stable in Tn – 1.

RWN (Input) The read (H) write (L) signal is always high during the read cycle.

CSN (Input) Chip select is an active-low signal.

DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one

clock and then driven high before entering a high-impedance state. (This is done with an I/O pad

using the input as feedback to qualify the 3-state term.) DT will become 3-stated when CS is high.

Typically, DTN is active 4 or 5 MPCLK cycles after ADSN is low.

ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. For example, a 9 ns

setup time would limit MPCLK to 40 MHz for reliable DTN detection.

Symbol Parameter Setup (Min) Hold (Min) Delay (Max) Unit

TCLK MPCLK 16 MHz Min—60* MHz Max Frequency — — — ns

tWS ADDR, RWN, DATA (write) Valid to MPCLK 3.5 0 — ns

tAPD MPCLK to ADDR, RWN, DATA, CSN (write) Invalid — 5 — ns

tCSNVS CSN Valid to MPCLK 3.5 0 — ns

tADSNVS ADSN Valid to MPCLK 5.5 0 — ns

tAIPD MPCLK to ADSN Invalid — 5 — ns

tDTNVPD MPCLK to DTN Valid — — 16 ns

tDTNIPD MPCLK to DTN Invalid — — 16 ns

tADSNVDTF ADSN Valid to DT Falling — — 1000 ns

MPCLK

ADDR[19:0]

CSN

ADSN

RWN

(60 M Hz MAX )

tADSNSU tSNIPD

tCSNSU

tAVS

T0 T1 T2 Tn – 4 Tn – 3 T n – 2 Tn – 1 Tn

DTN

DATA[15:0]

(OUTPUT)

tDAIPD

tDTNVPD

tDTNIPD

tADSNVDTF HIGH Z

HIGH Z

tAPD

58 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table 62. Microprocessor Interface Synchronous Read Cycle Specifications

(See Figure 16 on page 57 for the timing diagram.)

Symbol Parameter Setup

(Min) Hold

(Min) Delay

(Max) Unit

TCLK MPCLK 16 MHz Min—60* MHz Max

Frequency ————ns

tAVS ADDR Valid to MPCLK 3.5 0 — — ns

tAPD MPCLK to ADDR Invalid — 5 — — ns

tCSNSU CSN Active to MPCLK 3.5 0 — — ns

tADSNSU ADSN Valid to MPCLK 5.5 0 — — ns

tSNIPD MPCLK to ADSN Inactive — 5 — — ns

tDVPD MPCLK to DTN Valid — — 4 16 ns

tDIPD MPCLK to DTN Invalid — — 4 16 ns

tDAIPD MPCLK to DATA 3-state — — — 10 ns

tADSNVDTF ADSN Valid to DT Falling — — — 1000 ns

* If DTN is used, then the maximum frequency for MPCLK is determined by the processor’s setup specification for DTN. For example, a 9 ns

setup time would limit MPCLK to 40 MHz for reliable DTN detec tion.

59Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5.14.2 Asynchronous Mode

The asynchronous microprocessor interface mode is selected when MPMODE (pin AC18) = 0. Interface timing for

the asynchronous mode write cycle is given in Figure 17 and in Table 63, and for the read cycle in Figure 18 and in

Table 64.

5-7661(F).ar.1

Figure 17. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0)

ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-

able throughout the entire cycle.

DATA [15:0] Write data is asynchronously passed from the host bus to the internal bus. Data will be available

throughout the entire cycle.

RWN (Input) The read (H) write (L) signal is always high except during a write cycle.

CSN (Input) Chip select is an active-low signal.

DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN.

DTN is driven high until the internal transaction is done. DTN is driven high again when either ADSN

or DSN is deasserted. DTN will become 3-stated when CSN is high.

ADSN (Input) Address strobe is active-low. ADSN must be a minimum of one MPCLK clock period wide.

DSN (Input) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

(INPUT)

tAVADSF

tDVDSF

tCSFDTR tDSFDTF

tADSRDTR tCSRDT3

tDSRDI

tDSRRWR

tDSNRAI

tADSRAI

tAICSR

tRWFDSF

tAVDSF

HIGH Z HIGH Z

tCSFDSF

60 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table 63. Microprocessor Interface Asynchronous Write Cycle Specifications

(See Figure 17 on page 59 for the timing diagram.)

Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select

(CSN) may be connected and driven from the same source. In this configuration, the setup and hold times

for ADSN must be satisfied.

Symbol Parameter Typical Interval Max Interval Unit

tCSFDSF CSN Fall to DSN Fall 0 — ns

tAICSR ADDR Invalid to CSN Rise 0 — ns

tAVADSF ADDR Valid to ADSN Fall 0 — ns

tADSRAI ADSN Rise to ADDR Invalid 0 — ns

tAVDSF ADDR Valid to DSN Fall 0 — ns

tDSNRAI DSN Rise to ADDR Invalid 0 — ns

tRWFDSF RWN Fall to DSN Fall 0 — ns

tDSRRWR DSN Rise to RWN Rise 0 — ns

tDVDSF DATA Valid to DSN Fall 0 — ns

tDSRDI DSN Rise to DATA Invalid 0 — ns

tCSFDTR CSN Fall to DTN Rise 20 — ns

tDSFDTF DSN Fall to DTN Fall 120 1000 ns

tADSRDTR ADSN Rise to DTN Rise 20 — ns

tCSRDT3 CSN Rise to DTN 3-state 10 — ns

61Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

5-7662(F).ar.1

Figure 18. Microprocessor Interface Asynchronous Read Cycle (MPMODE (Pin AC18) = 0)

ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-

able throughout the entire cycle.

DAT A [15:0] Read data on the internal bus is only valid for one clock cycle; therefore, a latch is necessary to meet

the correct timing on the host bus.

RWN (Input) The read (H) write (L) signal is always high during a read cycle.

CSN (Input) Chip select is an active-low signal.

DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN,

DSN, and ADSN. DTN is driven high while the internal bus transaction is in progress. There is no

need to provide synchronization to outgoing signals in this mode. DTN is driven high and then placed

in a high-impedance state when either ADSN or DSN is deasserted. DTN will become 3-stated when

CSN is high.

ADSN (Input) Address strobe is active-low.

DSN (Input) Data strobe is active-low.

ADDR[19:0]

CSN

ADSN

DSN

DTN

DATA[15:0]

tADSRD3

tCSRDT3

tADSRDTR

tCSFDSF

RWN

tAVADSF

tAVDSF

tAICSR

tADSRAI

tDSNRAI

tDTVDV

tDSFDTF

tCSFDTR

HIGH Z

62 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

5 Timing Characteristics (continued)

Table 64. Microprocessor Interface Asynchronous Read Cycle Specifications

(See Figure 18 on page 61 for the timing diagram.)

1. DSN can be asserted up to 20 ns (1 clk at 50 MHz) prev ious to CSN.

2. ADDR can be asserted up to 60 ns (3 clk at 50 MHz) into cycle from ASDN.

3. DTN fall is variable depending on the block selected for access.

4. Leading edges of ADSN and DSN determine the falling edge of DTN.

5. Rising edge of ADSN determines the rising edge of DTN.

6. Data toggle 20 ns (1 clk at 50 MHz) previous to CSN.

Note: Specifications are valid for 50 MHz MPCLK with MPMODE = 0. Address strobe (ADSN) and chip select

(CSN) may be connected and driven from the same source. In this configuration, the setup and hold times

for ADSN must be satisfied.

5.15 General-Purpos e Interface Timing

Table 65. Input Timing Specifications

Symbol Parameter Typical Interval Max Interval Unit

tCSFDSF CSN Fall to DSN Fall 01—ns

tAICSR ADDR Invalid to CSN Rise 0 — ns

tAVADSF ADDR Valid to ADSN Fall 0 602ns

tADSRAI ADSN Rise to ADDR Invalid 0 — ns

tAVDSF ADDR Valid to DSN Fall 0 — ns

tDSNRAI DSN Rise to ADDR Invalid 0 — ns

tCSFDTR CSN Fall to DTN Rise 20 — ns

tDSFDTF DSN Fall to DTN Fall 100 10003, 4 ns

tADSRDTR ADSN Rise to DTN Rise 205—ns

tCSRDT3 CSN Rise to DTN 3-state 10 — ns

tDTVDV DTN Valid to DATA Valid 06—ns

tADSRD3 ADSN Rise to DATA 3-state 20 — ns

Input Name Reference CLK Min Setup Time (tS) Min Hold Time (tH)Unit

JTAG Signals

TDI TCLK ↑15.0 2.0 ns

TMSN TCLK ↑15.0 2.0 ns

TRSTN NA ASYNC ASYNC —

SCAN_EN NA ASYNC ASYNC —

SCAN_MODE NA ASYNC ASYNC —

Miscellaneous Signals

RSTN NA ASYNC ASYNC —

PMRST NA ASYNC ASYNC —

IC3STATEN NA ASYNC ASYNC —

IDDQ NA ASYNC ASYNC —

63Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

5 Timing Characteristics (continued)

Table 66. Output Timing Specifications

* Propagation delay skew, tPLH – tPHL, is ±200 ps.

6 Ordering Info rma tion

Output Name Reference CLK Test Conditions Propagation Delay* (tPD)Unit

Min Max

Transmit Signals

TDO TLCK ↓CL = 25 pF 3.0 20.0 ns

Miscellaneous Signals

PMRST NA — ASYNC ASYNC —

Device Code Package Temperature Comcode

TMXF281553BAL-3C-DB 456-pin PBGA –40 °C to +85 °C 700002098

64 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers

Table of Con t ents

Contents Page

7 Microprocessor Interface and Global Control and Status Registers ................................................................ 64

7.1 Supermapper Global Control and Status Registers.....................................................................................65

7.2 Microprocessor Interface Register Map .......................................................................................................75

Tables Page

Table 67. SMPR_VCR, Supermapper Version Control Register (RO) ....................................................................65

Table 68. SMPR_SYMR[4], Supermapper Symbol Register4 SMPR (RO).............................................................65

Table 69. SMPR_SYMR[3], Supermapper Symbol Register3 (RO)........................................................................65

Table 70. SMPR_SYMR[2], Supermapper Symbol Register2 (RO)........................................................................65

Table 71. SMPR_SYMR[1], Supermapper Symbol Register1 (RO)........................................................................65

Table 72. SMPR_SYMR[0], Supermapper Symbol Register0 (RO)........................................................................65

Table 73. SMPR_ISR, Supermapper Interrupt Status Register (RO)......................................................................66

Table 74. SMPR_IMR, Supermapper Interrupt Mask Register (RW) ......................................................................67

Table 75. SMPR_GTR, Global Trigger Register (RW).............................................................................................68

Table 76. SMPR_MSRR, Block Software Reset Register (RW)..............................................................................68

Table 77. SMPR_GCR, Global Control Register (RW)............................................................................................70

Table 78. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW)..................................................................71

Table 79. SMPR_FCR, Framer Control Register (RW)...........................................................................................71

Table 80. SMPR_CLCR, CDR, and LVDS Control Register (RW)...........................................................................72

Table 81. SMPR_CPCR, Clock and Power Control Register (RW).........................................................................73

Table 82. SMPR_PMRCHR, PM Reset Count High Register (RW)........................................................................73

Table 83. SMPR_PMRCLR, PM Reset Count Low Register (RW)..........................................................................74

Table 84. SMPR_TX_LINE_EN1.............................................................................................................................74

Table 85. SMPR_SR, Scratch Register (RW)..........................................................................................................74

Table 86. Microprocessor Interface Register Map...................................................................................................75

65Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

7.1 Supermapper Global Control and Status Registers

This section gives a brief description of each register bit and its functionality. The abbreviations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).

Table 67. SMPR_VCR, Supermapper Version Control Register (RO)

Table 68. SMPR_SYMR[4], Supermapper Symbol Register4 SMPR (RO)

Table 69. SMPR_SYMR[3], Supermapper Symbol Register3 (RO)

Table 70. SMPR_SYMR[2], Supermapper Symbol Register2 (RO)

Table 71. SMPR_SYMR[1], Supermapper Symbol Register1 (RO)

Table 72. SMPR_SYMR[0], Supermapper Symbol Register0 (RO)

Address Bit Name Function Reset Default

0x00000 15:11 RSVD Reserved. 0x0000

10:8 SMPR_VERSION[2:0] Supermapper Version Number. SMPR version

changed.

7:0 SMPR_ID[7:0] SMPR ID Number.

Address Bit Name Func tion Reset Default

0x00001 15:8 T Supermapper Symbol Bit. 0x544D

7:0 M Supermapper Symbol Bit.

Address Bit Name Func tion Reset Default

0x00002 15:8 X Supermapper Symbol Bit. 0x5846

7:0 F Supermapper Symbol Bit.

Address Bit Name Func tion Reset Default

0x00003 15:8 2 Superma pper Symbol Bit. 0x3238

7:0 8 Supermapper Symbol Bit.

Address Bit Name Function Reset Default

0x00004 15:8 1 Supermapper Symbol Bit. 0x3135

7:0 5 Supermapper Symbol Bit.

Address Bit Name Function Reset Default

0x00005 15:8 5 Supermapper Symbol Bit. 0x350D

7:0 CR Supermapper Symbol Bit.

66 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 73. SMPR_ISR, Supermapper Interrupt Status Register (RO)

Address Bit Name Function Reset

Default

0x00008 15 SMPR_APS_IS APS Interrupt. Active-high signal indicating an interrupt

event has occurred in the automatic protection switch (APS)

block, which is within the TMUX block.

0x0000

14:10 RSVD Reserved.

9 SMPR_PARITY_IS Microprocessor Interface Data Bus Parity Error Inter-

rupt. Active-high signal indicating a microprocessor data

bus parity error has occurred. Summary of errors detected

in PAR[1] and PAR[0] parity detectors.

8 SMPR_PMRESET_IS Performance Monitor Reset Interrupt. Active-high signal

indicating a 1 s event has occurred.

7SMPR_TPG_ISTPG Interrupt. Active-high signal indicating an interrupt

event has occurred in the test pattern generation block.

6SMPR_DJA_ISDJA Interrupt. Active-high signal indicating an interrupt

event has occurred in the digital jitter attenuation block.

5 SMPR_FRM_IS FRM Interrupt. Active-high signal indicating an interrupt

event has occurred in the framer block. However , on device

powerup, this bit is erroneously set. A device initialization

routine containing the following sequence should clear the

interrupt:

■Power up the framer block by selecting one of the clock

options in address 0x00012.

■Set and clear the framer software reset bit, bit 5 of

addres s 0x 0000 E.

■Power down the framer block in address 0x00012.

4SMPR_XC_ISXC Interrupt. Active-high signal indicating an interrupt

event has occurred in the cross connect block.

3 SMPR_M13_IS M 13 Inte rrup t. Active-high signal indicating an interrupt

event has occurred in the M13 multiplexer/demultiplexer

block.

2 SMPR_VTMPR_IS VTMPR Interrupt. Active-high signal indicating an interrupt

event has occurred in the VT mapper block.

1 SMPR_SPEMPR_IS SPEMPR Interrupt. Active-high signal indicating an inter-

rupt event has occurred in the SPE mapper block.

0SMPR_TMUX_ISTMUX Interrupt. Active-high signal indicating an interrupt

event has occurred in the TMUX block.

67Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 74. SMPR_IMR, Supermapper Interrupt Mask Register (RW)

Address Bit Name Function Reset

Default

0x00009 15 SMPR_APS_IM APS Interrupt Mask. When this bit is set to 1, the compos-

ite interrupt bit will be inhibited from contributing to the inter-

rupt pin APS_INTN.

0x83FF

14:10 RSVD Reserved.

9SMPR_PARITY_IMMicroprocessor Interface Data Bus Parity Error Inter-

rupt Mask. When this bit is set to 1, the composite interrupt

bit will be inhibited from contributing to the interrupt pin

INTN.

8 SMPR_PMRESET_IM Performance Monitor Reset Inte rrupt Mask. When this

bit is set to 1, the composite interrupt bit will be inhibited

from contributing to the interrupt pin INTN.

7SMPR_TPG_IMTPG Interrupt Mask. When this bit is set to 1, the compos-

ite interrupt bit will be inhibited from contributing to the inter-

rupt pin INTN.

6 SMPR_DJA_IM DJA Interrupt Mask. When this bit is set to 1, the compos-

ite interrupt bit will be inhibited from contributing to the inter-

rupt pin INTN.

5 SMPR_FRM_IM FRM Interrupt Mask. When this bit is set to 1, the compos-

ite interrupt bit will be inhibited from contributing to the inter-

rupt pin INTN.

4SMPR_XC_IMXC Inte rrup t Mask. When this bit is set to 1, the composite

interrupt bit will be inhibited from contributing to the interrupt

pin INTN.

3 SMPR_M13_IM M 13 In terru pt Mask. When this bit is set to 1, the compos-

ite interrupt bit will be inhibited from contributing to the inter-

rupt pin INTN.

2 SMPR_VTMPR_IM VTMPR Interrupt Mask. When this bit is set to 1, the com-

posite interrupt bit will be inhibited from contributing to the

interrupt pin INTN.

1 SMPR_SPEMPR_IM SPEMPR Interrupt Mask. When this bit is set to 1, the

composite interrupt bit will be inhibited from contributing to

the interrupt pin INTN.

0SMPR_TMUX_IMTMUX Interrupt Mask. When this bit is set to 1, the com-

posite interrupt bit will be inhibited from contributing to the

interrupt pin INTN.

68 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 75. SMPR_GTR, Global Trigger Register (RW)

Table 76. SMPR_MSRR, Block Software Reset Register (RW)

Address Bit Name Function Reset

Default

0x0000D 15:10 RSVD Reserved. 0x0000

9 SMPR_BER_INSRT Bit Error Rate Insertion. When this bit is set to 1, this bit

indicates to the Supermapper that a bit error has to be

inserted in the appr op riate frame .

8 SMPR_PMRESET Performance Monitor Reset. When this bit is set to 1, the

PMRESET signal will transition from a logic 0 to a logic 1

state. It will stay at a logic 1 state for a minimum of 100 ns.

(Self-clearing.)

7:1 RSVD Reserved.

0 SMPR_SWRS Supermapper Software Reset. When this bit is set to 1, it

will create a software reset of the device. This reset has the

same effect as the hardware reset. All microprocessor reg-

isters are reset to their default states, and all internal data

path state machines are reset. (Self-clearing.)

Address Bit Name Function Reset

Default

0x0000E 15:8 RSVD Reserved. 0x0000

7SMPR_TPG_SWRSTPG Bloc k S o ftw ar e R e se t. When this bit is set to 1, it will

create a software reset for the test-pattern generation

macro. This reset has the same effect as the hardware

reset and chip-level software reset. All microprocessor reg-

isters within the macro are reset to their default states. All

internal data path state machines within the block are also

reset.

6 SMPR_DJA_SWRS DJA Block Software Reset. When this bit is set to 1, it will

create a software reset for the digital jitter attenuation block.

This reset has the same effect as the hardware reset and

chip-level software reset. All microprocessor registers

within the macro are reset to their default states. All internal

data path state machines within the block are also reset.

5 SMPR_FRM_SWRS FRM Block Software Reset. When this bit is set to 1, it will

create a software reset for the framer block. This reset has

the same effect as the hardware reset and chip-level soft-

ware reset. All microprocessor registers within the block are

reset to their default states. All internal data path state

machines within the block are also reset.

69Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 76. SMPR_MSRR, Block Software Reset Register (RW) (continued)

Address Bit Name Function Reset

Default

0x0000E 4 SMPR_XC_SWRS XC Block Software Reset. When this bit is set to 1, it

will create a software reset for the cross connect block.

This reset has the same effect as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All inter-

nal data path state machines within the block are also

reset.

0x0000

3 SMPR_M13_SWRS M13 Blo ck Software Reset. When this bit is set to 1, it

will create a software reset for the M13 multiplexer/

demultiplexer block. This reset has the same effect as

the hardware reset and chip-level software reset.

All microprocessor registers within the block are reset to

their default states. All internal data path state machines

within the blo ck are also re se t.

2 SMPR_VTMPR_SWRS VTMPR Block Software Reset. When this bit is set to 1,

it will create a software reset for the VTMPR block. This

reset has the same effect as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All inter-

nal data path state machines within the block are also

reset.

1 SMPR_SPEMPR_SWRS SPEMPR Block Software Reset. When this bit is set

to 1, it will create a software reset for the SPEMPR block.

This reset has the same effect as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All inter-

nal data path state machines within the block are also

reset.

0 SMPR_TMUX_SWRS TMUX Block Software Reset. When this bit is set to 1, it

will create a software reset for the TMUX block. This

reset has the same effect as the hardware reset and

chip-level software reset. All microprocessor registers

within the block are reset to their default states. All inter-

nal data path state machines within the block are also

reset.

70 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 77. SMPR_GCR, Global Control Register (RW)

Address Bit Name Function Reset

Default

0x0000F 15:10 RSVD Reserved. 0x0000

9:8 SMPR_PMMODE[1:0] Performance Monitor Mode:

00 = PMRST comes from external pin.

10 = PMRST comes from external pin.

01 = PMRST comes from internal 1 s counter.

Note: Please see Table 82 and Table 83.

11 = PMRST is software controlled using the

SMPR_PMREST register bit 8 (Table 75 on

page 68).

7:5 RSVD Reserved.

4 SMPR_PARITY_EVEN_ODD Even or Odd Parity Indication on the Microproces-

sor Data Bus. This bit controls the parity setting and

checking on the microprocessor data bus:

0 = even parity on microprocessor byte data/parity bus.

1 = odd parity on microprocessor byte data/parity bus.

3SMPR_OH_DEFLTOverhead Default. This bit controls the filling of the

unused overhead bytes:

0 = filling the unused overhead bits with 0.

1 = filling the unused overhead bits with 1.

2 SMPR_FXD_STFF_DEFLT Fixed Stuff Default. This bit controls the filling of the

fixed stuff bytes:

0 = filling the fixed stuff bytes with 0.

1 = filling the fixed stuff bytes with 1.

1 SMPR_COR_COW Clear-On-Read or Clear-On-Write. This bit controls

the way clearing is perfo rmed on all delta and event

bits in all registers:

0 = the delta and event bit is cleared by writing a 1 to

it.

Note: The clear-on-write (COW) feature does not

apply to all registers in the 28-channel framer

block. The only framer block register that has

COW is transmit FDL link register 8 (address

0x8L TD7). All other registers in the framer block

are only clear-on-read.

1 = the delta and event bits are cleared when a micro-

processor read is performed on this delta and

event bit.

0 SMPR_SAT_ROLLOVER Saturate or Rollover. This bit controls if error

counters hold their values or roll over when they reach

their maximum values:

0 = error counters roll over when reaching maximum

values.

1 = error counters hold their values when reaching

maximum values.

71Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 78. SMPR_TSCR, TMUX, and SPEMPR Control Register (RW)

Table 79. SMPR_FCR, Framer Control Register (RW)

Address Bit Name Function Reset

Default

0x00010 15:4 RSVD Reserved. 0x0000

3 MPU_RHDZTHD_LB Forces Received High-Speed Data to Transmit

High-Speed Data Loopback Prior to the CDR.

2 SMPR_RETIME_CLK_EDGE Retime Clock Edge for the Received High-Speed

Data. This bit controls on which clock edge, positive

or negative, the received high-speed data is to be

retimed.

1 = the re ceiv ed da ta wil l be cl ocke d int o the de vice

on the negative clock edge.

0 = the re ceiv ed da ta wil l be cl ocke d int o the de vice

on the positive clock edge.

1 SMPR_TELECOMBUS_EDGE Telecom Bus Edge. The SPE mapper is enabled

to use a time slot on the telecom bus. This bit

selects the clock edge for the data signals transmit-

ted to the telecom bus during the selected time slot.

0 = clock telecom bus signals out on the falling

edge.

1 = clock telecom bus signals out on the rising

edge.

0 SMPR_TMUX_MASTER_SLAVE SMPR/TMUX Master Slave. This bit controls if the

TMUX block in this Supermapper is the master

device in the system module that this Supermapper

is on, or if it is a slave device.

0 = this Supermapper/TMUX is a slave device in the

module.

1 = this Supermapper/TMUX is a master device in

the module.

Address Bit Name Function Reset

Default

0x00012 15:3 RSVD Reserved. 0x0000

2:0 SMPR_FRM_CLK_SEL[2:0] Framer Clock Selection. Selects the source of the

framer high-speed clock the selected clock needs

to be faster than the aggregate throughput of the

framer block for prope r operat ion .

000 = framer is powered down. No clock required.

001 = framer receives TLSC52 (pin AC3) clock

input.

010 = framer receives DS1XCLK (pin AD16) clock

input.

011 = framer receives E1XCLK (pin AC17) clock

input.

72 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 80. SMPR_CLCR, CDR, and LVDS Control Register (RW)

Address Bit Name Function Reset

Default

0x00013 15:11 RSVD Reserved. 0x000C

10 SMPR_MPU_CDR_MODE CDR Mode Selection. This bit controls the operating

mode of the internal CDR, whether it operates at

155 MHz or 51 MHz.

0 = 155 MHz mode.

1 = 51 MHz mode.

9 SMPR_MPU_CG_PWRDN PLL Powerdown Selection. This bit controls whether

the internal framer PLL is powered on or off.

0 = internal PLL powered on.

1 = internal PLL powered off.

8 SMPR_LVDS_REF_SEL LVDS Reference Voltage Selection. This bit controls

which reference voltage, internal or external, is used to

power the LVDS buffers.

0 = external reference voltage is used.

1 = internal reference voltage is used.

7:4 RSVD Reserved.

3 SMPR_RXPWRDN CDR Channel Powerdown. This bit co ntrol s the power

to the CDR data channel.

0 = channel is active, power is on.

1 = channel is inactive, power to the channel is turned

off.

2 SMPR_PLLPWRDN CDR Phase-Lock Loop Powerdown. This bit controls

the power to the CDR PLL circuit.

0 = PLL is active, power to the PLL is turned on.

1 = PLL is inactive, power to the PLL is turned off.

1 SMPR_MRESET CDR Master Reset. This bit is used for the CDR i nit ial-

ization. It can also be used in test mode to reset test cir-

cuitry.

0 = no reset.

1 = reset mode.

0 SMPR_CDR_SEL CDR Selection. This bit controls if the TMUX receives

its high-s pee d recei ve cl ock and data from the on- chip

CDR block or from the pins (bypass the CDR).

0 = bypass CDR. Receives clock and data directly from

pins.

1 = use CDR. Receives clock and data through CDR.

73Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 81. SMPR_CPCR, Clock and Power Control Register (RW)

Table 82. SMPR_PMRCHR, PM Reset Count High Register (RW)

Address Bit Name Function Reset

Default

0x00014 15:9 RSVD Reserved. 0x0000

8SMPR_M13_TCLKM13 MUX/Tx Clock Enable.

0 = M13 MUX/Tx clock is powered down and inactive.

1 = M13 MUX/Tx clock is powered up and active.

7 SMPR_M13_RCLK M13 DeMUX Rx Clock Enable.

0 = M13 deMUX/Rx clock is powered down and inactive.

1 = M13 deMUX/Rx clock is powered up and active.

6 SMPR_DJA_CLK Digital Jitter Attenuation Clock Enable.

0 = DJA DPLL is powered down and inactive.

1 = DJA DPLL is powered up and active.

5SMPR_VTMPR_TCLKVT Mapper Tx Clock Enable.

0 = VT mapper Tx clock is powered down and inactive.

1 = VT mapper Tx clock is powered up and active.

4 SMPR_VTMPR_RCLK VT Mapper Rx Clock Enable.

0 = VT mapper Rx clock is powered down and inactive.

1 = VT mapper Rx clock is powered up and active.

3 SMPR_SPEMPR_TCLK SPE Mapper T x Clock Enable.

0 = SPE mapper Tx clock is powered down and inactive.

1 = SPE mapper Tx clock is powered up and active.

2 SMPR_SPEMPR_RCLK SPE Mapper Rx Clock Enable.

0 = SPE mapper Rx clock is powered down and inactive.

1 = SPE mapper Rx clock is powered up and active.

1 SMPR_TMUX_TCLK TMUX Tx Clock Enable.

0 = TMUX Tx clock is powered down and inactive.

1 = TMUX Tx clock is powered up and active.

0 SMPR_TMUX_RCLK TMUX Rx Clock Enable.

0 = TMUX Rx clock is powered down and inactive.

1 = TMUX Rx clock is powered up and active.

Address Bit Name Function Reset

Default

0x00016 15:11 RSVD Reserved. 0x01F8

10:0 SMPR_PMRESET_HIGH_COUNT[10:0] Performance Monitor Counter Preset.

The preset value of this register deter-

mines the frequency of the internal PM

counter. User should preload an appropri-

ate value based on the microprocessor

interface clock rate in order to reach the

desired PMRST rate.

74 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 83. SMPR_PMRCLR, PM Reset Count Low Register (RW)

Table 84. SMPR_TX_LINE_EN1

Table 85. SMPR_SR, Scratch Register (RW)

Address Bit Name Function Reset

Default

0x00017 15:0 SMPR_PMRESET_LOW_COUNT[15:0] Performance Monitor Counter Preset.

The preset value of this register determines

the frequency of the internal PM counter.

User should preload an appropriate value

based on the microprocessor interface

clock rate in order to reach the desired

PMRST rat e.

0x0000

Address Bit Name Function Reset

Default

0x00018 15:0 SMPR_TX_LINE_EN[16:1] 3-State Control for LINETXDATA,

LINETXCLK, and LINETXSYNC Output

Pins.

0x0000

0x00019 15:13

12:0 RSVD

SMPR_TX_LINE_EN[29:17] Reserved.

3-State Control for LINETXDATA,

LINETXCLK, and LINETXSYNC Output

Pins.

—

0x0000

Address Bit Name Function Reset

Default

0x0001F 15:0 SMPR_SCRATCH_REGISTER[15:0] Scratch Register. This register is for test

and diagnostics purpose.

Read/write operations can be performed on

all bits. No SMPR control and status will be

affected by any read/write operations to

this register.

0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

75Agere Systems Inc.

7 Microprocessor Interface and Global Control and Status Registers (continued)

7.2 Microprocess or Inter fa ce Reg is ter Ma p

Table 86. Microprocessor Interface Register Map

Note: Shading denotes reserved bits.

Address Symbol Bit

15 Bit

14 Bit

13 Bit

12 Bit

11 Bit

10 Bit

9Bit

8Bit

7Bit

6Bit

5Bit

4Bit

3Bit

2Bit

1Bit

Supermapper Version Control Register—RO

0x00000

page 65 SMPR_VCR SMPR_VERSION[2:0] SMPR_ID[7:0]

Supermapper Symbol Register—RO

0x00001

page 65 SMPR_SYMR4 0x54 = T 0x4D = M

0x00002

page 65 SMPR_SYMR3 0x58 = X 0x46 = F

0x00003

page 65 SMPR_SYMR2 0x32 = 2 0x38 = 8

0x00004

page 65 SMPR_SYMR1 0x31 = 1 0x35 = 5

0x00005

page 65 SMPR_SYMR0 0x35 = 5 0x0D = CR

0x00006

—

0x00007

RSVD

Supermapper Interrup t Status Register—RO

0x00008

page 66 SMPR_ISR SMPR_APS_IS SMPR_

PARITY_IS SMPR_

PMRESET_IS SMPR_TPG_IS SMPR_DJA_IS SMPR_FRM_

IS SMPR_XC_IS SMPR_M13_

IS SMPR_VTMPR_

IS SMPR_

SPEMPR_IS SMPR_TMUX_

Supermapper Interrup t Mask Register—R/W

0x00009

page 67 SMPR_IMR SMPR_APS_IM SMPR_

PARITY_IM SMPR_

PMRESET_IM SMPR_TPG_IM SMPR_DJA_

IM SMPR_FRM_

IM SMPR_XC_IM SMPR_M13_

IM SMPR_VTMPR_

IM SMPR_

SPEMPR_IM SMPR_TMUX_

0x0000A

—

0x0000C

RSVD

Global Trigger Register —R/W

0x0000D

page 68 SMPR_GTR SMPR_BER_

INSRT SMPR_

PMRESET SMPR_SWRS

Block Software Reset Register—R/W

0x0000E

page 68 SMPR_MSRR SMPR_TPG_SWRS SMPR_DJA_

SWRS SMPR_FRM_

SWRS SMPR_XC_

SWRS SMPR_M13_

SWRS SMPR_VTMPR_

SWRS SMPR_SPEMPR_

SWRS SMPR_TMUX_

SWRS

Global Control Register (SMPR_GCR)—R/W

0x0000F

page 70 SMPR_GCR SMPR_PMMODE[1:0] SMPR_PARITY_

EVEN_ODD SMPR_OH_

DEFLT SMPR_FXD_

STFF_DEFLT SMPR_COR_

COW SMPR_SAT_

ROLLOVER

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

76 Agere Systems Inc.

7 Microprocessor Interface and Global Control and Status Registers (continued)

Table 86. Microprocessor Interface Register Map (continued)

Note: Shading denotes reserved bits.

Address Symbol Bit

15:13 Bit

12:11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMUX and SPEMOR CONTROL Register—R/W

0x00010

page 71 SMPR_TSCR MPU_

RHDZTHD_LB SMPR_RETIME_

CLK_EDGE SMPR_TELECOMBUS_

EDGE SMPR_TMUX_

MASTER_SLAVE

0x00011 RSVD

FRAMER Control Register—R/W

0x00012

page 71 SMPR_FCR SMPR_FRM_CLK_SEL[2:0]

CDR and LVDS Control Register—R/W

0x00013

page 72 SMPR_CLCR SMPR_MPU_

CDR_MODE SMPR_MPU_

CG_PWRDN SMPR_LVDS_

REF_SEL SMPR_RXPWRDN SMPR_

PLLPWRDN SMPR_MRESET SMPR_CDR_SEL

Clock and Power Control Register—R/W

0x00014

page 73 SMPR_CPCR SMPR_M13_

TCLK SMPR_M13_

RCLK SMPR_DJA_

CLK SMPR_VTMPR_

TCLK SMPR_VTMPR_

RCLK SMPR_SPEMPR_

TCLK SMPR_SPEMPR_

RCLK SMPR_TMUX_TCLK SMPR_TMUX_RCLK

0x00015 RSVD

PM Reset Count Register High—R/W

0x00016

page 73 SMPR_PMRCHR SMPR_PMRESET_HIGH_COUNT[10:0]

PM Reset Count Register Low—R/W

0x00017

page 74 SMPR_PMRCLR SMPR_PMRESET_LOW_COUNT[15:0]

0x00018

page 74 TX_LINE_EN1 SMPR_TX_LINE_EN[16:1]

0x00019

page 74 TX_LINE_EN2 SMPR_TX_LINE_EN[29:17]

Scratch Register—R/W

0x0001F

page 74 SMPR_SR SMPR_SCRATCH_REGISTER[15:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

77Agere Systems Inc.

8 TMUX Regist er s

Table of Con t en ts

Contents Page

8 TMUX Registers ............................................................................................................................................... 77

8.1 TMUX Register Descriptions........................................................................................................................79

8.2 TMUX Register Map...................................................................................................................................126

Tables Page

Table 87. TMUX_ID_R, TMUX Identification Register (RO)....................................................................................79

Table 88. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)....................................................................79

Table 89. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W) ............................................................79

Table 90. TMUX_TX_DLT, Delta/Event (COR/COW) ..............................................................................................80

Table 91. TMUX_RPS_DLT, Delta/Event (COR/COW)............................................................................................80

Table 92. TMUX_RHS_DLT, Delta/Event (COR/COW) ...........................................................................................81

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)...............................................................................83

Table 94. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0).............................89

Table 95. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)..........................90

Table 96. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)..........................90

Table 97. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0)....................91

Table 98. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0).............93

Table 99. TMUX_TX_STATE, State Parameters (RO) ............................................................................................93

Table 100. TMUX_RPS_STATE, State and Value Parameters (RO).......................................................................93

Table 101. TMUX_RHS_STATE, State and Value Parameters (RO) ......................................................................94

Table 102. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO)..........................................................94

Table 103. TMUX_RHS_CTL, Receive High-Speed Control Parameters (R/W).....................................................96

Table 104. TMUX_RLS_BITBLK_CTL, Receive Low-Speed Control Parameters (R/W)........................................96

Table 105. TMUX_RLS_MODE_CTL, Receive Low-Speed Control Parameters (R/W) .........................................97

Table 106. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W)...............................................98

Table 107. TMUX_LOSDETCNT, Receive Low-Speed Control Parameters (R/W).................................................99

Table 108. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W) ........................100

Table 109. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W)........................101

Table 110. TMUX_C2EXP[1—2_3], Continuous N-Times Detect Control Parameters (R/W)...............................102

Table 111. TMUX_RF1MON, Receive Monitor Values (RO)..................................................................................102

Table 112. TMUX_RAPSMON, Receive Monitor Values (RO) ..............................................................................102

Table 113. TMUX_RS1MON, Receive Monitor Values (RO).................................................................................102

Table 114. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO)..........................................................103

Table 115. TMUX_TLS_CTL, Transmit Low-Speed Control Parameters (R/W)....................................................104

Table 116. TMUX_THS_PORT_CTL, Transmit High-Speed Port Control Parameters (R/W)...............................105

Table 117. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W).........................................105

Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) ...............................107

Table 119. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W) ................................ 111

Table 120. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)............................... 111

Table 121. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)..................................................112

Table 122. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W)...........................................112

Table 123. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W)...............................................112

Table 124. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) ................................112

Table 125. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W) ..................114

Table 126. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W).................115

Table 127. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)................................115

Table 128. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W).............................117

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

78 Agere Systems Inc.

8 TMUX Registers (continued)

Table of Conten ts (continued)

Tables Page

Table 129. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W) ...........................118

Table 130. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W).............................118

Table 131. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W).....................................119

Table 132. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W)..............................119

Table 133. TMUX_B3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W)......................................120

Table 134. TMUX_B1ECNT, Receive B1 Error Counts (RO) ................................................................................120

Table 135. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0, Receive B2 Error Counts (RO)........................121

Table 136. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO) ......................................................................121

Table 137. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO)......................122

Table 138. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO)......................................................................122

Table 139. TMUX_RPTR_INCCNT[1—3], Receive Pointer Increment Count (RO)..............................................123

Table 140. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO)...........................................123

Table 141. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W)....................................................123

Table 142. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO).......................................................123

Table 143. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W) ....................................................................123

Table 144. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W) .....................................124

Table 145. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W) .....................................124

Table 146. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W) .....................................124

Table 147. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO).............................................124

Table 148. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO).............................................124

Table 149. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO).............................................124

Table 150. TMUX_TJ1VALUE_1[1—32], J1 Byte Transmit Insert for STS #1 (R/W)............................................125

Table 151. TMUX_TJ1VALUE_2[1—32], J1 Byte Transmit Insert for STS #2 (R/W)............................................125

Table 152. TMUX_TJ1VALUE_3[1—32], J1 Byte Transmit Insert for STS #3 (R/W)............................................125

Table 153. TMUX Register Map ............................................................................................................................126

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

79Agere Systems Inc.

8 TMUX Registers (continued)

8.1 TMUX Register Descrip tions

This section provides a brief description of each register bit and its functionality. The abbreviations after each regis-

ter indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).

Table 87. TMUX_ID_R, TMUX Identification Register (RO)

Table 88. TMUX_ONESHOT, TMUX One-Shot Register 0 to 1 (R/W)

Table 89. TMUX_RCV_TX_MODE, TMUX Receive/Transmit Mode (R/W)

Address Bit Name Function Reset

Default

0x40000 15:11 RSVD Reserved. 0x0

10:8 TMUX_VERSION[2:0] Block Version Number. Block version register will

change each time the device is changed. 0x0

7:0 TMUX_ID[7:0] Block ID Number. 0x04

Address Bit Name Function Reset

Default

0x40002 15:8 RSVD Reserved. 0x00

7 TMUX_B3SFCLEAR B3 Signal Fail Clear . Allows the signal fail algorithm to be

forced into the normal state. 0

6 TMUX_B3SFSET B3 Signal Fail Set. Allows the signal fail algorithm to be

forced into the failed state. 0

5 TMUX_B3SDCLEAR B3 Signal Degra de Clear. Allows the signal degrade

algorithm to be forced into the normal state. 0

4 TMUX_B3SDSET B3 Signal Degrade Set. Allows the signal degrade algo-

rithm to be forced into the degra ded sta te. 0

3 TMUX_SFCLEAR Signal Fail Clear. Allows the signal fail algorithm to be

forced into the normal state. 0

2 TMUX_SFSET Signal Fail Set. Allows the signal fail algorithm to be

forced into the failed state. 0

1 TMUX_SDCLEAR Signal Degrade Clear. Allows the signal degrade algo-

rithm to be forced into the normal state. 0

0 TMUX_SDSET Signal Degrade Set. Allows the signal degrade algorithm

to be forced into the degraded state. 0

Address Bit Name Function Reset

Default

0x40003 15:1 RSVD Reserved. 0x000

0 TMUX_STS1MODE STS-1 Mode Control Bit. A 1 indicates that the received

and transmitted high-speed data is STS-1 data operating

at 52 MHz. A 0 indicates that the received and transmitted

high-speed data operates at 155 MHz.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

80 Agere Systems Inc.

8 TMUX Registers (continued)

Table 90. TMUX_TX_DLT, Delta/Event (COR/COW)

Table 91. TMUX_RPS_DLT, Delta/Event (COR/COW)

Address Bit Name Function Reset

Default

0x40004 15:7 RSVD Reserved. 0x000

6:4 TMUX_TLSPARE[3:1] Transmit Low-Speed Parity Error Event (Input Port Num-

ber). This event bit indicates a byte transfer parity error was

detected on the respective STS-1/AU-3 input. The mask bits

are TMUX_TLSPARM[3:1] (Table 94 on page 89).

3 TMUX_TPOAC_PE Transmit Path Overhead Access Channel (TPOAC) Par-

ity Error Even t. This event bit indicates a parity error was

detected on the incoming transmit path overhead access

channel. The mask bit is TMUX_TPOAC_PM (Table 94 on

page 89).

2 TMUX_TTOAC_PE Transmit Transport Overhead Access Channel (TTOAC)

Parity Error Event. This event bit indicates a parity error

was detected on the incoming transmit transport overhead

access channel. The mask bit is TMUX_TTOAC_PM

(Table 94 on page 89).

1 TMUX_THSILOFD Transmit High-Speed Input Loss of Frame Delta. Th is

delta bit indicates a change of state for the transmit loss of

frame bit TMUX_THSILOF (Table 99 on page 93). The mask

bit is TMUX_THSILOFM (Table 94 on page 89).

0 TMUX_THSILOCD Transmit High-Speed Input Loss of Clock Delta. This

delta bit indicates a change of state for the transmit loss of

high-speed clock bit TMUX_THSILOC (Table 99 on

page 93). The mask bit is TMUX_THSILOCM (Table 94 on

page 89).

Address Bit Name Function Reset

Default

0x40005 15:6 RSVD Reserved. 0x000

5 TMUX_RPSLOFD Receive Protection High-Speed Loss of Frame Delta.

This delta bit indicates a change in state of TMUX_RPSLOF

(Table 100 on page 93). The mask bit is TMUX_RPSLOFM

(Table 95 on page 90).

4 TMUX_RPSOOFD Receive Protection High-Speed Out of Frame Delta. This

delta bit indicates a change in state of TMUX_RPSOOF

(Table 100). The mask bit is TMUX_RPSOOFM (Table 95).

3 TMUX_RPSILOCD Receive Protection High-Speed Loss of Input Clock

Delta. This delta bit indicates a change in state of the

TMUX_RPSILOC (Table 100) state bit. T he mask bi t is

TMUX_RPSILOCM (Table 95).

2TMUX_RPSB2EReceive Prote ct ion High -Spee d B2 Error Even t. This

event bit indicates a B2 error was detected in the receive pro-

tection input. The mask bit is TMUX_RPSB2M (Table 95).

1 TMUX_RPSLREIE Rece ive Prote ct ion High -Spee d Lin e REI Event. This

event bit indicates a line REI error was detected in the

receive protection input. The mask bit is TMUX_RPSLREIM

(Table 95).

0RSVDReserved. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

81Agere Systems Inc.

8 TMUX Registers (continued)

Table 92. TMUX_RHS_DLT, Delta/Event (COR/COW)

Address Bit Name Function Reset

Default

0x40006 15 RSVD Reserved. 0

14 TMUX_RS1BABE Receive S1 Babble Event. This event bit indicates an inconsis-

tent S1 value is being received. The event is triggered if

TMUX_CNTDS 1FRAM E[3:0] (Table 108 on page 100) co nsec-

utive frames pass without a validated message occurring. The

mask bit is TMUX_RS1BABM (Table 96 on page 90).

13 TMUX_RS1MOND Receive S1 Monitor Delta. This delta bit indicates a change of

state for TMUX_RS1MON[7:0] (Table 113 on page 102). A new

S1 value is detected after TMUX_CNTDS1[3:0] (Table 108 on

page 100) consecutive occurrences of a consistent new value

in the S1 byte. The mask bit is TMUX_RS1MONM.

12 TMUX_RLRDIMOND Receive Line RDI Monitor Delta. This delta bit indicates a

change in state for TMUX_RLRDIMON (Table 101 on page 94)

when the pattern 110 is detected/not detected

TMUX_CNTDK2[3:0] (Table 108 on page 100) consecutive

times in the incoming STS-3/STM-1 frame. The mask bit is

TMUX_RLRDIMONM (Table 96 on page 90).

11 TMUX_RLAISMOND Receive Line AIS Monitor Delta. This delta bit indicates a

change in state for TMUX_RLAISMON (Table 101 on page 94)

when the pattern 111 is detected/not detected

TMUX_CNTDK2[3:0] consecutive times in the incoming STS-3/

STM-1 frame. The mask bit is TMUX_RLAISMONM (Table 96

on page 90).

10 TMUX_RK2MOND Receive K2 Monitor Delta. This delta bit indicates a change in

state for TMUX_K2MON[2:0] (Table 112 on page 102). A new

K2 value is detected after TMUX_CNTDK2[3:0] consecutive

occurrences of a consistent new value in the three least signifi-

cant bits of the incoming K2 byte. Note that this delta bit may be

coincid ent with TMUX_RLR DIMOND and

TMUX_RLAISMOND. The mask bit is TMUX_RK2MONM

(Table 96 on page 90).

9 TMUX_RAPSBABE Receive APS Babble Event. This event bit indicates when an

inconsistent APS value has been detected

TMUX_CNTDK1K2[3:0] (Table 108 on page 100) times in the

incoming TMUX_CNTDK1K2FRAME[3:0] (Table 108 on

page 100) consecutive frames. The mask bit is

TMUX_RAPSBABM (Table 96 on page 90).

8 TMUX_RAPSMOND Receive APS Monitor Delta. This delta bit indicates a change

in state in the received APS value TMUX_RAPSMON[12:0]

(Table 112 on page 102) when a new consistent value is

detected TMUX_CNTDK1K2[3:0] times in the K1 and K2[7:3]

bits. The mask bit is TMUX_RAPSMONM (Table 96 on

page 90).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

82 Agere Systems Inc.

8 TMUX Registers (continued)

Table 92. TMUX_RHS_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40006 7 TMUX_RF1MOND Receive F1 Monitor Delta. This delta bit indicates a change in

state of TMUX_RF1MON0[7:0] and TMUX_RF1MON1[7:0]

(Table 111 on page 102) when a consistent new value is

detected in the incoming F1 byte for TMUX_CNTDF1[3:0]

(Table 108 on page 100) continuous frames. The current value is

stored in TMUX_RF1MON0[7:0], and the previous value is

stored in TMUX_RF1MON0[7:0]. The mask bit is

TMUX_RF1MONM (Table 96 on page 90).

6 TMUX_RTIMSD Receive Section Trace Identifier Mismatch Delta. This delta

bit indicates a change in state in the received 16-byte J0

sequence of bytes if the J0 mode is programmed to receive a 16-

byte sequence. The mask bit is TMUX_RTIMSM (Table 96 on

page 90).

5 TMUX_RHSSFD Receive High-Speed Signal Fail BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER algo-

rithm state bit TMUX_RHSSF (Table 101 on page 94). The mask

bit for this delta bit is TMUX_RHSSFM (Table 96 on page 90).

4 TMUX_RHSSDD Receive High-Speed Signal Degrade BER Algorithm Delta.

This delta bit indicates a change of state for the signal degrade

BER algorithm state bit TMUX_RHSSD (Table 101 on page 94).

The mask bit is TMUX_RHSSDM (Table 96 on page 90).

3 TMUX_RHSLOSD Receive High-Speed Loss of Signal Delta. This delta bit

indicates a change in state of either TMUX_RHSLOS (Table 101

on page 94) or TMUX_RHSLOSEXTI (Table 101 on page 94).

TMUX_RHSLOSEXTI is an external input from a device pin.

TMUX_RHSLOS is an internally generated state bit based on

monitoring for a consecutive 0/1s pattern in the data input. The

mask bit is TMUX_RHSLOSM (Table 96 on page 90).

2 TMUX_RHSLOFD Receive High-Speed Loss of Frame Delta. This delta bit indi-

cates a change in state of TMUX_RHSLOF (Table 101 on

page 94). The mask bit is TMUX_RHSLOFM (Table 96 on

page 90).

1 TMUX_RHSOOFD Receive High-Speed Out of Frame Delta. This delta bit indi-

cates a change in state of TMUX_RHSOOF (Table 101 on

page 94). The mask bit is TMUX_RHSOOFM (Table 96 on

page 90).

0 TMUX_RHSILOCD Receive High-Speed Loss of Input Clock Delta. This delta bit

indicates a change in state of the TMUX_RHSILOC (Table 101

on page 94) state bit. The mask bit is TMUX_RHSILOCM

(Table 96 on page 90).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

83Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW)

Address Bit Name Function Reset

Default

0x40007 15 TMUX_RSFB3D1 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of state for the signal fail BER algo-

rithm state bit TMUX_RSFB31 (Table 102 on page 94) at the

path level for port 1. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RSFB3M1

(Table 97 on page 91).

14 TMUX_RSDB3D1 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER

algorithm state bit TMUX_RSDB31 (Table 102 on page 94)

at the path level for port 1. Only port 1 information is valid in

AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RSDB3M1 (Table 97 on page 91).

13 TMUX_RUNEQPE1 Receive Path Unequipped Event. This event bit ind ic ate s

that the current value of the received C2 (signal label) byte,

TMUX_C2MON1[7:0] (Table 114 on page 103), has a value

0x00, indicating unequipped payload on port 1. Only port 1

information is valid in AU-4 mode and in STS-1 mode. The

mask bit is TMUX_RUNEQPM1 (Table 97 on page 91).

12 TMUX_RPLMPE1 Receive Path Payload Label Mismatch Event. This event

bit indicates that the current value of the received C2 (signal

label) byte, TMUX_C2MON1[7:0], differs from the expected

C2 value, TMUX_C2EXP1[7:0] (Table 110 on page 102), for

port 1. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RPLMPM1 (Table 97

on page 91).

11 TMUX_RN1MOND1 Receive N1 Monitor Delta. This delta bit indicates a change

in state in TMUX_ N 1M ON 1[7:0] (Table 114 on page 103).

The N1 current value is updated when a consecutive and

consistent value is detected in the incoming N1 byte for

TMUX_CNTDN1[3:0] (Table 109 on page 101) frames on

port 1. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RN1MONM1 (Table 97

on page 91).

10 TMUX_RK3MOND1 Receive K3 Monitor Delta. This delta bit indicates a change

in state in TMUX_ K3 MO N1[7:0] (Table 114 on page 103),

which is updated when a consecutive and consistent value is

detected in the incoming K3 byte for TMUX_CNTDK3[3:0]

(Table 109 on page 101) frames on port 1. Only port 1 infor-

mation is valid in AU-4 mode and in STS-1 mode. The mask

bit is TMUX_RK3MONM1 (Table 97 on page 91).

9 TMUX_RF3MOND1 Receive F3 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F3MON01[7:0]

(Table 114 on page 103), which is updated when a consecu-

tive and consistent value is detected in the incoming F3 byte

for TMUX_CNTDF3[3:0] (Table 109 on page 101) frames on

port 1. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RF3MONM1 (Table 97

on page 91).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

84 Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40007 8 TMUX_RF2MOND1 Receive F2 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F2MON01[7:0]

(Table 114 on page 103), which is updated when a consecu-

tive and consistent value is detected in the incoming F2 byte

for TMUX_CNTDF2[3:0] (Table 109 on page 101) frames on

port 1. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RF2MONM1 (Table 97

on page 91).

7 TMUX_RRDIPD1 Receive Path RDI (Remote Defect Indication) Monitor

Delta. This delta bit indicates a change in state in

TMUX_RDIP MON1[2:0] (Table 114 on page 103), that

occurs when a consecutive and consistent new value is

detected in the incoming G1[3:1] bits for

TMUX_CNTDRDIP[3:0] (Table 109 on page 101) frames on

port 1. The device monitors either G1 bit 3 or G1[3:1],

dependi ng on TM UX_ REP RDI_ MO DE (Tab le 105 on

page 97). Only port 1 information is valid in AU-4 mode and

in STS-1 mode. The mask bit is TMUX_RRDIPM1 (Table 97

on page 91).

6 TMUX_RC2MOND1 Receive C2 (Signal Label) Monitor Delta. This delta bit

indicates a change in state in TMUX_C2MON1[7:0]

(Table 114 on page 103), which is updated when a consecu-

tive and consistent value is detected in the incoming C2 byte

for TMUX_CNTDC2[3:0] (Table 109 on page 101) frames on

port 1. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RC2MONM1 (Table 97

on page 91).

5 TMUX_RTIMPD1 Receive Path Trace Identifier Mismatch Delta. This delta

bit indicates a change in state in the received 16-byte J1

sequence on port 1 if the J1 mode is programmed to receive

a 16-byte sequence. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RTIMPM1

(Table 97 on page 91).

4 TMUX_RNDFE1 Receive New Data Flag Event. This event bit indicates that

the incoming pointer has the new data flag enabled, causing

a jump in the current pointer location for port 1. Only port 1

information is valid in AU-4 mode and in STS-1 mode. The

mask bit is TMUX_RNDFM1 (Table 97 on page 91).

3 TMUX_RDECE1 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indication was

received on port 1. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RDECM1

(Table 97 on page 91).

2 TMUX_RINCE1 Receive Pointer Increment Event. This event bit indicates

that a valid incoming pointer increment indication was

received on port 1. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RINCM1

(Table 97 on page 91).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

85Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x4007 1 TMUX_RPAISD1 Rec eive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS1 (Table 102 on page 94) state bit,

which designates that the port 1 pointer interpreter is in the

alarm indication signal state. Only port 1 information is valid in

AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RPAISM1 (Tab le 97 on page 91).

0 TMUX_RLOPD1 Receive Loss of Pointer Delta. This delta bit indicates a

change in state of the TMUX_RLOP1 (Table 102 on page 94)

state bit, which designates that the port 1 pointer interpreter is

in the loss of pointer state. Only port 1 information is valid in

AU-4 mode. The mask bit is TMUX_RLOPM1 (Table 97 on

page 91).

0x40008 15 TMUX_RSFB3D2 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of state for the signal fail BER algorithm

state bit TMUX_RSFB32 (Table 102 on page 94) at the path

level for port 2. Only port 1 information is valid in AU-4 mode

and in STS-1 mode. The mask bit is TMUX_RSFB3M2

(Table 97 on page 91).

14 TMUX_RSDB3D2 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER

algorithm state bit TMUX_RSDB32 (Table 102 on page 94) at

the path level for port 2. Only port 1 information is valid in AU-

4 mode and in STS-1 mode. The mask bit is

TMUX_RHSSDB3M2.

13 TMUX_RUNEQPD2 Receive Path Unequipped Delta. This delta bit indicates that

the current value of the received C2 (signal label) byte,

TMUX_C2MON2[7:0] (Table 114 on page 103), has a value

0x00, indicating unequipped payload for port 2. Only port 1

information is valid in AU-4 mode and in STS-1 mode. The

mask bit is TMUX_RUNEQPM2 (Table 97 on page 91).

12 TMUX_RPLMPD2 Receiv e Path P ayloa d Labe l Mism atch D elta. This event bit

indicates that the current value of the received C2 (signal

label) byte, TMUX_C2MON2[7:0], differs from the expected

C2 value, TMUX_C2EXP2[7:0] (Table 110 on page 102) for

port 2. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RPLMPM2 (Table 97 on

page 91).

11 TMUX_RN1MOND2 Receive N1 Monitor Delta. This delta bit indicates a change

in state in TMUX_ N 1M ON 2[7:0 ] (Table 114 on page 103).

The N1 current value is updated when a consecutive and con-

sistent value is detected in the incoming N1 byte for

TMUX_CNTDN1[3:0] (Table 109 on page 101) frames on port

2. Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RN1MONM2 (Table 97 on

page 91).

10 TMUX_RK3MOND2 Receive K3 Monitor Delta. This delta bit indicates a change

in state in TMUX_ K3 MO N2[7:0] (Table 114 on page 103),

which is updated when a consecutive and consistent value is

detected in the incoming K3 byte for TMUX_CNTDK3[3:0]

(Table 109 on page 101) frames on port 2. Only port 1 infor-

mation is valid in AU-4 mode and in STS-1 mode. The mask

bit is TMUX_RK3MONM2 (Table 97 on page 91).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

86 Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40008 9 TMUX_RF3MOND2 Receive F3 (Path User Byte) Monitor Delta. This delta bit indi-

cates a change in state in TMUX_F3MON02[7:0] (Table 114 on

page 103), which is updated when a consecutive and consistent

value is detected in the incoming F3 byte for

TMUX_CNTDF3[3:0] (Table 109 on page 101) frames on port 2.

Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RF3MONM2 (Table 97 on

page 91).

8 TMUX_RF2MOND2 Receive F2 (Path User Byte) Monitor Delta. This delta bit indi-

cates a change in state in TMUX_F2MON02[7:0] (Table 114 on

page 103), which is updated when a consecutive and consistent

value is detected in the incoming F2 byte for

TMUX_CNTDF2[3:0] (Table 109 on page 101) frames on port 2.

Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RF2MONM2 (Table 97 on

page 91).

7 TMUX_RRDIPD2 Receive Path RDI (Remote Defect Indication) Monitor Delta.

This delta bit indicates a change in state in

TMUX_ RDIPMO N2[ 2:0] (Table 114 on page 103), whi ch occu rs

when a consecutive and consistent new value is detected in the

incoming G1[3:1] bits for TMUX_CNTDRDIP[3:0] (Table 109 on

page 101) frames on port 2. The device monitors either G1 bit 3

or G1[3:1], depending on TMUX_REPRDI_MODE (Table 105

on page 97). Only port 1 information is vali d in AU-4 mode and

in STS-1 mode. The mask bit is TMUX_RRDIPM2 (Table 97 on

page 91).

6 TMUX_RC2MOND2 Receive C2 (Signal Label) Monitor Delta. This delta bit indi-

cates a change in state in TMUX_C2MON2[7:0] (Tab le 114 on

page 103), which is updated when a consecutive and consistent

value is detected in the incoming C2 byte for

TMUX_CNTDC2[3:0] (Table 109 on page 101) frames on port 2.

Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RC2MONM2 (Table 97 on

page 91).

5 TMUX_RTIMPD2 Receive Path Trace Identifier Mismatch Delta. This delta bit

indicates a change in state in the received 16-byte J1 sequence

for port 2 if the J1 mode is programmed to receive a 16-byte

sequence. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask b it is TMUX_RTIMPM2 (Table 97 on

page 91).

4 TMUX_RNDFE2 Receive New Data Flag Event. This event bit indicates that the

incoming pointer has the new data flag enabled for port 2, caus-

ing a jump in the current pointer location. Only port 1 information

is valid in AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RNDFM2 (Table 97 on page 91 ).

3 TMUX_RDECE2 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indication was received

on por t 2. Only port 1 inf ormation is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RDECM2 (Table 97 on

page 91). However, increment and decrement event indication

should be ignored during loss of pointer (LOP) condition.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

87Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40008 2 TMUX_RINCE2 Receive Pointer Increment Event. This event bit indicates

that a valid incoming pointer increment indication was

received on port 2. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RINCM2

(Table 97 on page 91). However, increment and decrement

event indication should be ignored during loss of pointer

(LOP) condition.

1 TMUX_RPAISD2 Receive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS2 (Table 102 on page 94) state bi t,

which designates that the port 2 pointer interpreter is in the

alarm indication signal state. Only port 1 information is valid

in AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RPAISM2 (Table 97 on page 91).

0 TMUX_RLOPD2 Receive Loss of Pointer Delta. This delta bit indicates a

change in state of the TMUX_RLOP2 (Table 102 on

page 94) state bit, which designates that the port 2 pointer

interpreter is in the loss of pointer state. Only port 1 informa-

tion is valid in AU-4 mode. The mask bit is TMUX_RLOPM2

(Table 97 on page 91).

0x40009 15 TMUX_RSFB3D3 Receive Path Signal Fail BER Algorithm Delta. This delta

bit indicates a change of state for the signal fail BER algo-

rithm state bit TMUX_RSFB32 (Table 102 on page 94) at the

path level for port 3. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RSFB3M3

(Table 97 on page 91).

14 TMUX_RSDB3D3 Receive Path Signal Degrade BER Algorithm Delta. This

delta bit indicates a change of state for the signal fail BER

algorithm state bit TMUX_RSDB32 (Table 102 on page 94)

at the path level for port 3. Only port 1 information is valid in

AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RSDB3M3 (Table 97 on page 91).

13 TMUX_RUNEQPE3 Receive Path Unequipped Event. This event bit indicates

that the current value of the received C2 (signal label) byte,

TMUX_C2MON3[7:0] (Table 114 on page 103), has a value

0x00, indicating unequipped payload for port 3. Only port 1

information is valid in AU-4 mode and in STS-1 mode. The

mask bit is TMUX_RUNEQPM3 (Table 97 on page 91).

12 TMUX_RPLMPE3 Receive Path Payload Label Mismatch Event. This event

bit indicates that the current value of the received C2 (signal

label) byte, TMUX_C2MON3[7:0], differs from the expected

C2 value, TMUX_C2EXP3[7:0] (Table 110 on page 102) fo r

port 3. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RPLMPM3 (Table 97

on page 91).

11 TMUX_RN1MOND3 Rece ive N1 Mo nito r Delt a. This delta bit indicates a change

in state in TMUX_N1MON3[7:0] (Table 114 on page 103).

The N1 current value is updated when a consecutive and

consistent value is detected in the incoming N1 byte for

TMUX_CNTDN1[3:0] (Table 109 on page 101) frames on

port 3. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RN1MONM3 (Table 97

on page 91).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

88 Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Address Bit Name Function Reset

Default

0x40009 10 TMUX_RK3MOND3 Receive K3 Monitor Delta. This delta bit indicates a change in

state in TMUX_K3MON3[7:0] (Table 114 on page 103), which

is updated when a consecutive and consistent value is

detected in the incoming K3 byte for TMUX_CNTDK3[3:0]

(Table 109 on page 101) frames on port 2. Only port 1 informa-

tion is valid in AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RK3MONM3 (Table 97 on page 91).

9 TMUX_RF3MOND3 Receive F3 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F3MON03[7:0]

(Table 1 14 on page 103), which is updated when a consecutive

and consistent value is detected in the incoming F3 byte for

TMUX_CNTDF3[3:0] (Table 109 on page 101) frames on port

3. Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RF3MONM3 (Table 97 on

page 91).

8 TMUX_RF2MOND3 Receive F2 (Path User Byte) Monitor Delta. This delta bit

indicates a change in state in TMUX_F2MON03[7:0]

(Table 1 14 on page 103), which is updated when a consecutive

and consistent value is detected in the incoming F2 byte for

TMUX_CNTDF2[3:0] (Table 109 on page 101) frames on port

3. Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RF2MONM3 (Table 97 on

page 91).

7 TMUX_RDIPD3 Receive Path RDI (Remote Defect Indication) Monitor

Delta. This delta bit indicates a change in state in

TMUX_RDIP MON3[2:0] (Table 114 on page 103), which

occurs when a consecutive and consistent new value is

detected in the incoming G1[3:1] bits for

TMUX_CNTDRDIP[3:0] (Table 109 on page 101) frames on

port 3. The device monitors either G1 bit 3 or G1[3:1], depend-

ing on TMUX_REPRDI_MODE (Table 105 on page 97). On ly

port 1 information is valid in AU-4 mode and in STS-1 mode.

The mask bit is TMUX_RRDIPM3 (Table 97 on page 91).

6 TMUX_RC2MOND3 Receive C2 (Signal Label) Monitor Delta. This delta bit indi-

cates a change in state in TMUX_C2MON3[7:0] (Tab le 114 on

page 103), which is updated when a consecutive and consis-

tent value is detected in the incoming C2 byte for

TMUX_CNTDC2[ 3:0] (Table 109 on page 101) frames on port

3. Only port 1 information is valid in AU-4 mode and in STS-1

mode. The mask bit is TMUX_RC2MONM3 (Table 97 on

page 91).

5 TMUX_RTIMPD3 Receive Path Trace Identifier Mismatch Delta. This delta bit

indicates a change in state in the received 16-byte J1

sequence for port 3 if the J1 mode is programmed to receive a

16-byte sequence. Only port 1 information is valid in AU-4

mode and in STS-1 mode. The mask bit is TMUX_RTIMPM3

(Table 97 on page 91).

4 TMUX_RNDFE3 Receive New Data Flag Event. This event bit indicates that

the incoming pointer has the new data flag enabled, causing a

jump in the current pointer location for port 3. Only port 1 infor-

mation is valid in AU-4 mode and in STS-1 mode. The mask bit

is TMUX_RNDFM3 (Table 97 on page 91).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

89Agere Systems Inc.

8 TMUX Registers (continued)

Table 93. TMUX_RPOH[1—3]_DLT, Delta/Event (COR/COW) (continued)

Note: In Table 94, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 94. TMUX_TX_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Note: In Table 95, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Address Bit Name Fu nction Reset

Default

0x40009 3 TMUX_RDECE3 Receive Pointer Decrement Event. This event bit indicates

that a valid incoming pointer decrement indication was received

on port 3. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RDECM3 (Table 97 on

page 91).

2 TMUX_RINCE3 Receive Pointer Increment Event. This event bit indicates that

a valid incoming pointer increment indication was received on

port 3. Only port 1 information is valid in AU-4 mode and in

STS-1 mode. The mask bit is TMUX_RINCM3 (Table 97 on

page 91).

1 TMUX_RPAISD3 Receive Path AIS Delta. This delta bit indicates a change in

state of the TMUX_RPAIS3 (Table 102 on page 94) state bit,

which designates that the port 3 pointer interpreter is in the

alarm indication signal state. Only port 1 information is valid in

AU-4 mode and in STS-1 mode. The mask bit is

TMUX_RPAISM3 (Table 97 on page 91).

0TMUX_RLOPD3Receive Loss of Pointer Delta. This delta bit indicates a

change in state of the TMUX_RLOP3 (Table 102 on page 94)

state bit, which designates that the port 3 pointer interpreter is in

the loss of pointer state. Only port 1 information is valid in AU-4

mode. The mask bit is TMUX_RLOPM3 (Table 97 on page 91).

Address Bit Name Function Reset

Default

0x4000A 15:7 RSVD Reserved. 0x000

6:4 TMUX_TLSPARM[3:1] Transmit Low-Speed Parity Error Mask (Input Port

Number). See Table 90 on page 80 for description. 1

3 TMUX_TPOAC_PM Transmit Path Overhead Access Channel (TPOAC) Par-

ity Error Mask. See Table 90 for description. 1

2 TMUX_TTOAC_PM Transmit Transport Overhead Access Channel

(TTOAC) P arity Error Mask. See Table 90 for description. 1

1 TMUX_THSILOFM Transmit High-Speed Input Loss of Frame Mask. See

Table 90 for description. 1

0 TMUX_THSILOCM Transmit High-Speed Input Loss of Clock Mask. See

Table 90 for description. 1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

90 Agere Systems Inc.

8 TMUX Registers (continued)

Table 95. TMUX_RPS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Note: In Table 96, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 96. TMUX_RHS_MSK, Mask Bits for INT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Address Bit Name Function Reset

Default

0x4000B 15:6 RSVD Reserved. 0x000

5TMUX_RPSLOFMReceive Prote ct ion High -Spee d Los s of Frame Mask. See

Table 91 starting on page 80, for description of all bits in this

table.

4 TMUX_RPSOOFM Receive Protection High-Speed Out of Frame Mask. 1

3 TMUX_RPSILOCM Receive Protection High-Spee d Loss of Input Clock Mask. 1

2 TMUX_RPSB2M Rece ive Pr ote ctio n High-Sp ee d B2 Err or Mask. 1

1 TMUX_RPSLREIM Receive Pr ote ct ion High-S pee d Li ne REI Mask. 1

0RSVDReserved. 0

Address Bit Name Function Reset

Default

0x4000C 15 RSVD Reserved. 0

14 TMUX_RS1BABM Receive S1 Babble Mask. See Table 92 starting on

page 81, for a description of all bits in this table. 1

13 TMUX_RS1MONM Receive S1 Monitor Mask. 1

12 TMUX_RLRDIMONM Receive Line RDI Monitor Mask. 1

11 TMUX_RLAISMONM Receive Line AIS Monitor Mask. 1

10 TMUX_RK2MONM Receive K2 Monitor Mask. 1

9 TMUX_RAPSBABM Receive APS Babble Mask. 1

8 TMUX_RAPSMONM Receive APS Monitor Mask. 1

7TMUX_RF1MONMReceive F1 Monitor Mask. 1

6 TMUX_RTIMSM Receive Section Trace Identifier Mismatch Mask. 1

5TMUX_RHSSFMReceive High-Speed Signal Fail BER Algorithm Mask. 1

4 TMUX_RHSSDM Receive High-Speed Signal Degrade BER Algorithm

Mask. 1

3 TMUX_RHSLOSM Receive High-Speed Loss of Signal Mask. 1

2 TMUX_RHSLOFM Receive High-Speed Loss of Frame Mask. 1

1 TMUX_RHSOOFM Receive High-Speed Out of Frame Mask. 1

0 TMUX_RHSILOCM Receive High-Speed Loss of Input Clock Mask. 1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

91Agere Systems Inc.

8 TMUX Registers (continued)

Note: In Table 97, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 97. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Address Bit Name Function Reset

Default

0x4000D 15 TMUX_RSFB3M1 Receive Path Signal Fail BER Algorithm Mask. See Table 93

on page 83 for a description of all bits in this table. 1

14 TMUX_RSDB3M1 Receive Path Signal Degrade BER Algorithm Mask. 1

13 TMUX_RUNEQPM1 Receive Path Unequipped Mask. 1

12 TMUX_RPLMPM1 Receive Path Payload Label Mismatch Mask. 1

11 TMUX_RN1MONM1 Receive N1 Monitor Mask. 1

10 TMUX_RK3MONM1 Receive K3 Monitor Mask. 1

9 TMUX_RF3MONM1 Receive F3 (Path User Byte) Monitor Mask. 1

8 TMUX_RF2MONM1 Receive F2 (Path User Byte) Monitor Mask. 1

7 TMUX_RRDIPM1 Receive Path RDI (Remote Defect Indication) Monitor Mask. 1

6 TMUX_RC2MONM1 Receive C2 (Signal Label) Monitor Mask. 1

5 TMUX_RTIMPM1 Receive Path Trace Identifier Mismatch Mask. 1

4 TMUX_RNDFM1 Receive New Data Flag Mask. 1

3TMUX_RDECM1Receive Pointer Decrement Mask. 1

2 TMUX_RINCM1 Receive Pointer Increment Mask. 1

1 TMUX_RPAISM1 Receive Path AIS Mask. 1

0 TMUX_RLOPM1 Receive Loss of Pointer Mask. 1

0x4000E 15 TMUX_RSFB3M2 Receive Path Signal Fail BER Algorithm Mask. 1

14 TMUX_RSDB3M2 Receive Path Signal Degrade BER Algorithm Mask. 1

13 TMUX_RUNEQPM2 Receive Path Unequipped Mask. 1

12 TMUX_RPLMPM2 Receive Path Payload Label Mismatch Mask. 1

11 TMUX_RN1MONM2 Receive N1 Monitor Mask. 1

10 TMUX_RK3MONM2 Receive K3 Monitor Mask. 1

9 TMUX_RF3MONM2 Receive F3 (Path User Byte) Monitor Mask. 1

8 TMUX_RF2MONM2 Receive F2 (Path User Byte) Monitor Mask. 1

7 TMUX_RRDIPM2 Receive Path RDI (Remote Defect Indication) Monitor Mask. 1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

92 Agere Systems Inc.

8 TMUX Registers (continued)

Note: In Table 97, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 97. TMUX_RPOH[1—3]_MSK, Mask Bits for Interrupt Signal (R/W) (Mask = 1, No Mask = 0) (continued)

Address Bit Name Function Reset

Default

0x4000E 6 TMUX_RC2MONM2 Receive C2 (Signal Label) Monitor Mask. See Table 93 on

page 83 for a description of all bits in this table. 1

5TMUX_RTIMPM2Receive Path Trace Identifier Mismatch Mask. 1

4 TMUX_RNDFM2 Receive New Data Flag Mask. 1

3TMUX_RDECM2Receive Pointer Decrement Mask. 1

2 TMUX_RINCM2 Receive Pointer Increment Mask. 1

1 TMUX_RPAISM2 Receive Path AIS Mask. 1

0TMUX_RLOPM2Receive Loss of Pointer Mask. 1

0x4000F 15 TMUX_RSFB3M3 Receive Path Signal Fail BER Algorithm Mask. 1

14 TMUX_RSDB3M3 Receive Path Signal Degrade BER Algorithm Mask. 1

13 TMUX_RUNEQPM3 Receive Path Unequipped Mask. 1

12 TMUX_RPLMPM3 Receive Path Payload Label Mismatch Mask. 1

11 TMUX_RN1MONM3 Receive N1 Monitor Mask. 1

10 TMUX_RK3MONM3 Receive K3 Monitor Mask. 1

9 TMUX_RF3MONM3 Receive F3 (Path User Byte) Monitor Mask. 1

8 TMUX_RF2MONM3 Receive F2 (Path User Byte) Monitor Mask. 1

7 TMUX_RRDIPM3 Receive Path RDI (Remote Defect Indication) Monitor

Mask. 1

6 TMUX_RC2MONM3 Receive C2 (Signal Label) Monitor Mask. 1

5TMUX_RTIMPM3Receive Path Trace Identifier Mismatch Mask. 1

4 TMUX_RNDFM3 Receive New Data Flag Mask. 1

3TMUX_RDECM3Receive Pointer Decrement Mask. 1

2 TMUX_RINCM3 Receive Pointer Increment Mask. 1

1 TMUX_RPAISM3 Receive Path AIS Mask. 1

0TMUX_RLOPM3Receive Loss of Pointer Mask. 1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

93Agere Systems Inc.

8 TMUX Registers (continued)

Note: In Table 98, the mask bits are set to suppress an interrupt when the corresponding event has occurred or

change in state has taken place.

Table 98. TMUX_APSINT_MSK, Mask Bits for APSINT Interrupt Signal (R/W) (Mask = 1, No Mask = 0)

Note: When state bits are set in Table 99, the corresponding function has occurred.

Table 99. TMUX_TX_STATE, State Parameters (RO)

Note: When state bits are set in Table 100, the corresponding function has occurred.

Table 100. TMUX_RPS_STATE, State and Value Parameters (RO)

Address Bit Name Function Reset

Default

0x40011 15:8 RSVD Reserved. 0x000

7 TMUX_RHSSF_APSM Receive High-Speed Signal Fail BER Algorithm

APSINT Mask. See Table 92 on page 81 for descrip-

tion.

6 TMUX_RHSSD_APSM Receive High-Speed Signal Degrade BER Algo-

rithm APSINT Mask. See Table 92 for descript ion. 1

5 TMUX_RAPSMON_APSM Receive APS Monitor APSINT Mask. See Table 93

for description. 1

4 TMUX_RLAISMON_APSM Receive Line AIS Monitor APSINT Mask. See

Table 92 for descri ption. 1

3 TMUX_RHSLOS_APSM Receive High-Speed Loss of Signal APSINT Mask.

See Table 92 for descri ption. 1

2 TMUX_RHSLOF_APSM Receive High-Speed Loss of Frame APSINT Mask.

See Table 92 for descri ption. 1

1 TMUX_RHSOOF_APSM Receive High-Speed Out of Frame APSINT Mask.

See Table 92 for descri ption. 1

0 TMUX_RHSILOC_APSM Receive High-Speed Loss of Input Clock APSINT

Mask. See Table 92 for de scription. 1

Address Bit Name Function Reset

Default

0x40012 15:2 RSVD Reserved. 0x000

1 TMUX_THSILOF Transmit High-Speed Input Loss of Frame State. See

Table 90 on page 80 for description. 0

0 TMUX_THSILOC Transmit High-Speed Input Los s of Clock State. See

Table 90 for description. 0

Address Bit Name Function Reset

Default

0x40013 15:6 RSVD Reserved. 0x000

5TMUX_RPSLOFReceive Protection High-Speed Loss of Frame State. See

Table 91 on page 80 for description. 0

4 TMUX_RPSOOF Receive Protection High-Speed Out of Frame State. See

Table 91 for description. 0

3 TMUX_RPSILOC Receive Protection High-Speed Loss of Input Cloc k State.

See Table 91 for description. 0

2:0 RSVD Reserved. 000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

94 Agere Systems Inc.

8 TMUX Registers (continued)

Note: When state bits are set in Table 101, the corresponding function has occurred.

Table 101. TMUX_RHS_STATE, State and Value Parameters (RO)

Note: When state bits are set in Table 102, the corresponding function has occurred.

Address Bit Name Function Reset

Default

0x40014 15:13 RSVD Reserved. 000

12 TMUX_RLRDIMON Receive Line RDI Monitor State. See Table 92 on

page 81 for description. 0

11 TMUX_RLAISMON Receive Line AIS Monitor State. See Table 92 for

description. 0

10:8 RSVD Reserved. 000

7 TMUX_RHSLOSEXTI Reflects LOSEXT Pin (AE5) Input. —

6TMUX_RTIMSReflects Section-Level T race Identifier Mismatch State. —

5 TMUX_RHSSF Receive High-Speed Signal Fail BER Algorithm State.

See Table 92 for description. 0

4TMUX_RHSSDReceive High-Speed Signal Degrade BER Algorithm

State. See Table 92 for descri ption. 0

3 TMUX_RHSLOS Receive High-Speed Loss of Signal State. See Table 92

for description. 0

2 TMUX_RHSLOF Receive High-Speed Loss of Frame State. See Table 92

for description. 0

1 TMUX_RHSOOF Receive High-Speed Out of Frame State. See Table 92

for description. 0

0 TMUX_RHSILOC Receive High-Speed Loss of Input Clock State. See

Table 92 for descri ption. 0

Table 102. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO)

Address Bit Name Function Reset

Default

0x40015 15 TMUX_RSFB31 Receive Path Signal Fail BER Algorithm State.

See Table 93 on page 83 for description. 0

14 TMUX_RSDB31 Receive Path Signal Degrade BER Algorithm

State. See Table 93 for description. 0

13 TMUX_RUNEQP1 Receive Path Unequipped State. See Table 93

for description. 0

12 TMUX_RPLMP1 Receive Path Payload Label Mismatch State.

See Table 93 for description. 0

11:6 RSVD Reserved. 0x00

5 TMUX_RTIMP1 Receive Path Trace Identifier Mismatch State.

See Table 93 for description. 0

4:2 RSVD Reserved. 000

1 TMUX_RPAIS1 Receive Path AIS State. See Table 93 for descrip-

tion. 0

0TMUX_RLOP1Receive Loss of Pointer State. See Table 93 for

description. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

8 TMUX Registers (continued)

95Agere Systems Inc.

Address Bit Name Function Reset

Default

0x40016 15 TMUX_RSFB32 Receive Path Signal Fail BER Algorithm State.

See Tab le 93 on page 83 for description. 0

14 TMUX_RSDB32 Receive Path Signal Degrade BER Algorithm

State. See Table 93 for description. 0

13 TMUX_RUNEQP2 Receive Path Unequipped State. See Table 93

for descri pti on. 0

12 TMUX_RPLMP2 Receive Path Payload Label Mismatch State.

See Table 93 for description . 0

11:6 RSVD Reserved. 0x000

5 TMUX_RTIMP2 Receive Path Trace Identifier Mismatch State.

See Table 93 for description . 0

4RSVDReserved. 0

3:2 TMUX_CONCAT_STATE2[1:0] Concatenation Poi nter State Machine State.

State bits indicate the state of the concatenation

state machine (LOPC = 10, AISC = 01,

CONC = 00) for port 2. These values only have

meaning in the AU-4 mode with the

TMUX_RCONCATMODE bit (Table 105 on

page 97) set to the concatenation mode (1).

1 TMUX_RPAIS2 Receive Path AIS State. See Table 93 for descrip-

tion. 0

0TMUX_RLOP2Receive Loss of Pointer State. See Table 93 for

description. 0

0x40017 15 TMUX_RSFB33 Receive Path Signal Fail BER Algorithm State.

See Table 93 for description . 0

14 TMUX_RSDB33 Receive Path Signal Degrade BER Algorithm

State. See Table 93 for description. 0

13 TMUX_RUNEQP3 Receive Path Unequipped State. See Table 93

for descri pti on. 0

12 TMUX_RPLMP3 Receive Path Payload Label Mismatch State.

See Table 93 for description . 0

11:6 RSVD Reserved. 0x000

5 TMUX_RTIMP3 Receive Path Trace Identifier Mismatch State.

See Table 93 for description . 0

4RSVDReserved. 0

3:2 TMUX_CONCAT_STATE3[1:0] Concatenation Poi nter State Machine State.

State bits indicate the state of the concatenation

state machine (LOPC = 10, AISC = 01,

CONC = 00) for port 3. These values only have

meaning in the AU-4 mode and the

TMUX_RCONCATMODE bit (Table 105 on

page 97) set to the concatenation mode (1).

1 TMUX_RPAIS3 Receive Path AIS State. See Table 93 for descrip-

tion. 0

0TMUX_RLOP3Receive Loss of Pointer State. See Table 93 for

description. 0

Table 102. TMUX_RPOH[1—3]_STATE, State and Value Parameters (RO) (continued)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

96 Agere Systems Inc.

8 TMUX Registers (continued)

Table 103. TMUX_RHS_CTL, Receive High-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40019 15:4 RSVD Reserved. 0x000

3 TMUX_LOSEXT_LEVEL Controls External LOSEXT Polarity.

0 = active-low.

1 = active-high.

2 TMUX_RPSMUXSEL1 Receive Protection Switch Control. Control bit, when

set to a logic 1, causes the receive protection switch data

and clock inputs to be selected; otherwise, the normal

receive high-speed data input is selected.

1 TMUX_THS2RHSLB Transmit High-Speed to Receive High-Speed Loop-

back Control. Control bit, when set to a logic 1, causes

the transmit output STS-3/STM-1 (AU-4) signal to be

looped back to the receive input; otherwise, the loopback

is disabled.

0 TMUX_RHSDSCR Receive High-Speed Descramble Enable. Control bit,

when set to a logic 1, causes the input STS-3/STM-1

(AU-4) signal to be descrambled; otherwise, the signal is

not descrambled.

Table 104. TMUX_RLS_BITBLK_CTL, Receive Low-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001A 15:9 RSVD Reserved. 0x00

8:7 TMUX_RCV_SS_EXP[1:0] Expected Receive Pointer Size Bits V alue. Expected

value of incoming pointer SS bits. 00

6 TMUX_RCV_SS_ENB Receive Size Bits Enable. Control bit, when set to a logic

0, causes the received size bits to be ignored by the

pointer interpreter; otherwise, the received size bits must

equal the expected size bits or the received pointer value

will b e invali d.

5RSVDReserved. 0

4TMUX_BITBLKG1Receive Bit/Block Error Count Control. Control bit,

when set to a logic 0, causes the receive error counter to

count bit errors; otherwise, count block errors (a block

equals one frame) occur .

3 TMUX_BITBLKM1 Receive Bit/Block Error Count Control. Control bit,

when set to a logic 0, causes the receive error counter to

count bit errors; otherwise, count block errors (a block

equals one frame) occur .

2 TMUX_BITBLKB3 Receive Bit/Block Error Count Control. Control bit,

when set to a logic 0, causes the receive error counter to

count bit errors; otherwise, count block errors (a block

equals one frame) occur .

1 TMUX_BITBLKB2 Receive Bit/Block Error Count Control. Control bit,

when set to a logic 0, causes the receive error counter to

count bit errors; otherwise, count block errors (a block

equals one frame) occur .

0 TMUX_BITBLKB1 Receive Bit/Block Error Count Control. Control bit,

when set to a logic 0, causes the receive error counter to

count bit errors; otherwise, count block errors (a block

equals one frame) occur.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

97Agere Systems Inc.

8 TMUX Registers (continued)

Table 105. TMUX_RLS_MODE_CTL, Receive Low-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001B 15:14 RSVD Reserved. 00

13 TMUX_RPAIS_INS Receive Force Path AIS Insertion. Control bit, when

set to a logic 1, causes the receive low-speed signal to

carry PAIS as well as asserting all AUTO_AIS[1—3]

(pins AC6, AE6, and AD6) (Table 3 on page 17) out-

puts.

12 TMUX_8ORMAJORITY Receive Control Bit for Pointer Justifications. Con-

trol bit, when set to a logic 1, causes the pointer inter-

preter to accept an increment or decrement only if 8 out

of 10 bits are correct; otherwise, it will accept an incre-

ment or decrement based on majority vote only.

11 TMUX_SDB1B2SEL Receive Signal Degrade Algorithm Input Selection.

Control bit, when set to a logic 1, causes the B2 erro rs

to contribute to the signal degrade calculation; other-

wise, the B1 error count is used.

10 TMUX_SFB1B2SEL Receive Signal Fail Algorithm Input Selection. Con-

trol bit, when set to a logic 1, causes the B2 errors to

contribute to the signal degrade calculation; otherwise,

the B1 error count is used.

9:7 TMUX_J1MONMODE[2:0] Receive J1 Monitor Mode. There are six modes, as

defined in Sec ti on, J1 Mon ito r, on page 383. 000

6:4 TMUX_J0MONMODE[2:0] Receive J0 Monitor Mode. There are six modes, as

defin ed in Section 17.5.5, J0 Monitor, on page 376. 000

3 TMUX_S1MODE4 Receive S1 Monitor Mode. Control bit, when set to a

logic 1, causes the most significant nibble of the S1 byte

to be monitored; otherwise, the entire S1 byte is moni-

tored.

2 TMUX_RLSPAROEG Receive Low-Speed Parity Odd or Even Generation.

Control bit, when set to a logic 1, forces the output parity

bit to be even; otherwise, the parity is odd.

1 TMUX_RCONCATMODE Receive Concatenation Mode. Control bit, when set to

a logic 1, causes the input pointer interpreter to operate

in concatenation mode. This mode is most likely used in

AU-4 mode; otherwise, three independent pointers are

expected.

0 TMUX_REPRDI_MODE Receive Enhanced Path RDI Mode. Control bit, when

set to a logic 1, causes the receive path RDI monitor to

monitor the enhanced (3-bit found in G1[3:1]) value of

path RDI; otherwise, a 1-bit value (G1[3]) is monitored.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

98 Agere Systems Inc.

8 TMUX Registers (continued)

Table 106. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W)

Address Bit Name Function Res et

Default

0x4001C 15 TMUX_R_M1_BIT7 Receive M1 MSB Mode. Control bit, when set to a

logic 1, causes the most significant bit in the M1 byte to

be ignored for line REI accumulation; otherwise, the

MSB is included.

14 TMUX_RSDB3_AISINH Receive B3 Signal Degrade AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm from

causing the ass ert ion of the AUTO_AIS output; othe r-

wise, the assoc ia ted fail ure cau se s asser ti on of the cor-

responding AUTO_AIS output signal.

13 TMUX_RSFB3_AISINH Receive B3 Signal Fail AIS Inhibit. Control bit, when

set to a logic 1, inhibits the associated alarm from caus-

ing the assertion of the AUTO_AIS output; otherwise, the

associated failure causes assertion of the corresponding

AUTO_AIS output signal.

12:10 TMUX_RTIMP_AISINH[3:1] Receive Path Trace Identifier Mismatch AIS Inhibit

Bits. Control bits, when set to a logic 1, inhibit the asso-

ciated alarm from causing the assertion of the

AUTO_AIS output; otherwise, the associated failure

causes assertion of the corresponding AUTO_AIS output

signal.

9 TMUX_RUNEQP_AISINH Receive Path Unequip AIS Inhibit. Control bit, when

set to a logic 1, inhibits the associated alarm from caus-

ing the assertion of the AUTO_AIS output; otherwise, the

associated failure causes assertion of the corresponding

AUTO_AIS output signal.

8 TMUX_RPLMP_AISINH Receive Path Payload Label Mismatch AIS Inhibit.

Control bit, when set to a logic 1, inhibits the associated

alarm from causing the assertion of the AUTO_AIS out-

put; otherwise, the associated failure causes assertion of

the corresponding AUTO_AIS output signal.

7 TMUX_RHSSD_AISINH Receive High-Speed S ignal Degra de AIS Inhibit. Con-

trol bit, when set to a logic 1, inhibits the associated

alarm from causing AIS generation; otherwise, the asso-

ciated failure causes AIS generation on all STS-1/AU-3

outputs as well as the assertion of AUTO_AIS outputs.

6 TMUX_RHSSF_AISINH Receive High-Speed Signal Fail AIS Inhibit. Control

bit, when set to a logic 1, inhibits the associated alarm

from causing AIS generation; otherwise, the associated

failure causes AIS generation on all STS-1/AU-3 outputs

as well as the assertion of AUTO_AIS outputs.

5 TMUX_RPAISLOP_AISINH Receive Path AIS or LOP AIS Inhibit. Co ntro l bit, when

set to a logic 1, inhibits the associated alarm from caus-

ing AIS generation; otherwise, the associated failure

causes AIS generation on all STS-1/AU-3 outputs as

well as the assertion of AUTO_AIS outputs.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

99Agere Systems Inc.

8 TMUX Registers (continued)

Table 106. TMUX_RAISINH_CTL, Receive Low-Speed Control Parameters (R/W) (continued)

Table 107. TMUX_LOSDETCNT, Receive Low-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001C 4 TMUX_RLAISMON_AISINH Receive Line AIS Monitor AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm

from causing AIS generation; otherwise, the associ-

ated failure causes AIS generation on all STS-1/AU-3

outputs as well as the assertion of AUTO_AIS out-

puts.

3 TMUX_RLOF_AISINH Receive Loss-of-Frame AIS Inhibit. Control bit,

when set to a logic 1, inhibits the associated alarm

from causing AIS generation; otherwise, the associ-

ated failure causes AIS generation on all STS-1/AU-3

outputs as well as the assertion of AUTO_AIS out-

puts.

2 TMUX_ROOF_AISINH Receive High-Speed Out of Frame AIS Inhibit.

Control bit, when set to a logic 1, inhibits the associ-

ated alarm from causing AIS generation; otherwise,

the associated failure causes AIS generation on all

STS-1/AU-3 outputs as well as the assertion of

AUTO_AIS outp uts.

1 TMUX_RHSLOS_AISINH Receive High-Speed Loss-of-Signal AIS Inhibit.

Control bit, when set to a logic 1, inhibits the associ-

ated alarm from causing AIS generation; otherwise,

the associated failure causes AIS generation on all

STS-1/AU-3 outputs as well as the assertion of

AUTO_AIS outputs .

0 TMUX_RILOC_AISINH Receive Input Loss-of-Clock AIS Inhibit. Control

bit, when set to a logic 1, inhibits the associated alarm

from causi ng the asserti on of the AUTO_AIS outp uts ;

otherwise, the associated failure causes assertion of

all AUTO_AIS output signals.

Address Bit Name Function Reset

Default

0x4001D 15:14 RSVD Reserved. 00

13:11 TMUX_FORCEC2DEF[2:0] Force TMUX_RPLMP Defects. These bits (one for

each STS -1 in an STS -3) wil l force TMUX _RP LMP

defects on certain conditions as shown in Table 536

on page 385 (STS Signal Label Defect Conditions).

000

10:0 TMUX_LOSDETCNT[10:0] Loss-of-Signal Detection Count. Control bits are the

number of consecutive all-0s/1s patterns detected to

declare LOS state in the unscrambled STS-3/STM-1

(AU-4) input frame. A value of 0x02D equals 2.3 µs

while a value of 0x798 equals 100 µs.

0x02D

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

100 Agere Systems Inc.

8 TMUX Registers (continued)

Table 108. TMUX_CNTD_TOH_[A—B], Continuous N-Times Detect Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4001E 15:12 TMUX_CNTDK1K2FRAME[3:0] Continuous N-Times Detect for APS Frame

Bytes. Sets the number of CNTD frames within

which an inconsistent APS value is detected in the

incoming STS-3/STM-1 (AU-4). This value is used in

the APS babble algorithm. The valid range for this

to a value of 0x3.

0xC

11:8 TMUX_CNTDK1K2[3:0] Continuous N-Times Detect for APS (K1, K2[7:3])

Bytes. Sets the number of CNTD occurrences of a

consistent APS value in the incoming STS-3/STM-1

(AU-4) frame. The valid range for this register is

0x3—0xF. Invalid values will be mapped to a value

of 0x3.

0x3

7:4 TMUX_CNTDF1[3:0] Continuous N-Times Detect for F1 Byte. Sets the

number of CNTD occurrences of a consistent F1

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this register is 0x3—0xF. Invalid

values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDJ0[3:0] Continuous N-Times Detect for J0 Byte. Sets the

number of CNTD occurrences of a consistent J0

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this register is 0x3—0xF. Invalid

values will be mapped to a value of 0x3.

0x3

0x4001F 15:14 RSVD Reserved. 00

13:12 TMUX_CTDLOPCNT[1:0] Continuous N-Times Detect for Loss of Pointe r

State. Control bits are the number of consecutive

conditions for invalid pointer and invalid concatena-

tion indication (pointer interpretation). Valid values

are the following: 00 = 8, 01 = 9, 10 = 10, and 11 = 8.

0x0

11:8 TMUX_CNTDS1FRAME[3:0] Continuous N-Times Detect for S1 Frame Bytes.

Sets the number of CNTD frames within which an

inconsistent S1 value is detected in the incoming

STS-3/STM-1 (AU-4). This value is used in the S1

babble algorithm. The valid range for this register is

0x3—0xF. Invalid values will be mapped to a value

of 0x3.

0x3

7:4 TMUX_CNTDS1[3:0] Continuous N-Times Detect for S1 Byte. Sets the

number of CNTD occurrences of a consistent S1

value in the incoming STS-3/STM-1 (AU-4) frame.

The valid range for this register is 0x3—0xF. Invalid

values will be mapped to a value of 0x3.

0x3

3:0 TMUX_CNTDK2[3:0] Continuous N-Times Detect for K2[2:0] Byte. Sets

the number of CNTD occurrences of a consistent

K2[2:0] value in the incoming STS-3/STM-1 (AU-4)

frame. The valid range for this register is 0x3—0xF.

Invalid values will be mapped to a value of 0x3.

0xC

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

101Agere Systems Inc.

8 TMUX Registers (continued)

Table 109. TMUX_CNTD_POH_[A—B], Continuous N-Times Detect Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40020 15:12 TMUX_CNTDF2[3:0] Continuous N-Times Detect for F2 Byte. Sets the num-

ber of CNTD occurrences of a consistent F2 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

11:8 TMUX_CNTDRDIP[3:0] Continuous N-Times Detect for G1[3:1] Byte. Sets the

number of CNTD occurrences of a consistent G1[3:1]

value in th e incoming STS-3/STM-1 (AU-4) frame. The

valid range for this register is 0x3—0xF. Invalid values will

be mapped to a value of 0x3.

0x3

7:4 TMUX_CNTDC2[3:0] Continuous N-Times Detect for C2 Byte. Sets the num-

ber of CNTD occurrences of a consistent C2 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

3:0 TMUX_CNTDJ1[3:0] Continuous N-Times Detect for J1 Byte. Sets the num-

ber of CNTD occurrences of a consistent J1 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

0x40021 15:13 RSVD Reserved. 000

12 TMUX_CTDB1SEL Continuous N-Times AUTO AIS Select. Control bit,

when set to a logic 1, causes TOH CNTD counters to be

reset whenever the AUTO_AIS signal is asserted.

11:8 TMUX_CNTDN1[3:0] Continuous N-Times Detect for N1 Byte. Sets the num-

ber of CNTD occurrences of a consistent N1 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

7:4 TMUX_CNTDK3[3:0] Continuous N-Times Detect for K3 Byte. Sets the num-

ber of CNTD occurrences of a consistent K3 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

3:0 TMUX_CNTDF3[3:0] Continuous N-Times Detect for F3 Byte. Sets the num-

ber of CNTD occurrences of a consistent F3 value in the

incoming STS-3/STM-1 (AU-4) frame. The valid range for

this register is 0x3—0xF. Invalid values will be mapped to

a value of 0x3.

0x3

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

102 Agere Systems Inc.

8 TMUX Registers (continued)

Table 110. TMUX_C2EXP[1—2_3], Continuous N-Time s Detect Control Parameters (R/W)

Table 111. TMUX_RF1MON, Receive Monitor Values (RO)

Table 11 2. TMUX_RAPSMON, Receive Monitor Values (RO)

Table 113. TMUX_RS1MON, Receive Monitor Values (RO)

Address Bit Name Function Reset

Default

0x40022 15:8 RSVD Reserved. 0x00

7:0 TMUX_C2EXP1[7:0] Expected C2 Byte for Port 1. Should be programmed to

contain expected signal label (C2) for port 1. 0x00

0x40023 15:8 TMUX_C2EXP3[7:0] Expected C2 Byte for Port 3. Should be programmed to

contain expected signal label (C2) for port 3. 0x00

7:0 TMUX_C2EXP2[7:0] Expected C2 Byte for Port 2. Should be programmed to

contain expected signal label (C2) for port 2. 0x00

Address Bit Name Function Reset

Default

0x40024 15:8 TMUX_RF1MON1[7:0] Rece ive F1 Pre vious Mo nitor Value. See Secti on 17.5 .7,

F1 Monitor, on page 377. 0x00

7:0 TMUX_RF1MON0[7:0] Receive F1 Current Monitor Value. See Section 17.5.7,

F1 Monitor, on page 377. 0x00

Address Bit Name Function Reset

Default

0x40025 15:3 TMUX_

RAPSMON[12:0] Receive APS Monitor Value. See Section 17.5.9, Auto-

matic Protection Switch (APS) Monitor, on page 377. 0x00

2:0 TMUX_K2MON[2:0] Receive K2 Monitor Value. See Section 17.5.9, Auto-

matic Protection Switch (APS) Monitor, on page 377. 0x0

Address Bit Name Function Reset

Default

0x40026 15:8 RSVD Reserved. 0x00

7:0 TMUX_RS1MON[7:0] Rece ive S1 Mon ito r Value . See Section 17.5.12, Sync

Status Monitor, on page 378. 0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

103Agere Systems Inc.

8 TMUX Registers (continued)

Table 114. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO)

Address Bit Name Function Reset

Default

0x40027 15:11 RSVD Reserved. 0x00

10:8 TMUX_RDIPMON1[2:0] Receive Path RDI Monitor Value for Port 1. See RDI-P

Detection Section on page 385.0x0

7:0 TMUX_C2MON1[7:0] Receive C2 Monit or Value for Port 1. See Signal Label

C2 Byte Monitor Section on page 384.0x00

0x40028 15:8 TMUX_F2MON11[7:0] Receive F2 Previous Monitor Value for Port 1. See

Path User Byte F2 Monitor Section on page 386.0x00

7:0 TMUX_F2MON01[7:0] Receive F2 Current Monitor Value for Port 1. See Path

User Byte F2 Monitor Section on page 386.0x00

0x40029 15:8 TMUX_F3MON11[7:0] Receive F3 Previous Monitor Value for Port 1. See

Path User Byte F3 Monitor Section on page 386.0x00

7:0 TMUX_F3MON01[7:0] Receive F3 Current Monitor Value for Port 1. See Path

User Byte F3 Monitor Section on page 386.0x00

0x4002A 15:8 TMUX_N1MON1[7:0] Rece i v e N1 M o ni to r Value for Por t 1. See N1 Byte Mon-

itor Section on page 387.0x00

7:0 TMUX_K3MON1[7:0] Receive K3 Monitor Value for Port 1. See K3 Byte Mon-

itor Section on page 387.0x00

0x4002B 15:11 RSVD Reserved. 0x00

10:8 TMUX_RDIPMON2[2:0] Receive Path RDI Monitor Value for Port 2. See RDI-P

Detection Section on page 385.0x0

7:0 TMUX_C2MON2[7:0] Receive C2 Monit or Value for Port 2. See Signal Label

C2 Byte Monitor Section on page 384.0x00

0x4002C 15:8 TMUX_F2MON12[7:0] Receive F2 Previous Monitor Value for Port 2. See

Path User Byte F2 Monitor Section on page 386.0x00

7:0 TMUX_F2MON02[7:0] Receive F2 Current Monitor Value for Port 2. See Path

User Byte F2 Monitor Section on page 386.0x00

0x4002D 15:8 TMUX_F3MON12[7:0] Receive F3 Previous Monitor Value for Port 2. See

Path User Byte F3 Monitor Section on page 386.0x00

7:0 TMUX_F3MON02[7:0] Receive F3 Current Monitor Value for Port 2. See Path

User Byte F3 Monitor Section on page 386.0x00

0x4002E 15:8 TMUX_N1MON2[7:0] Rece i v e N1 M o ni to r Value for Por t 2. See N1 Byte Mon-

itor Section on page 387.0x00

7:0 TMUX_K3MON2[7:0] Receive K3 Monitor Value for Port 2. See K3 Byte Mon-

itor Section on page 387.0x00

0x4002F 15:11 RSVD Reserved. 0x00

10:8 TMUX_RDIPMON3[2:0] Receive Path RDI Monitor Value for Port 3. See RDI-P

Detection Section on page 385.0x0

7:0 TMUX_C2MON3[7:0] Receive C2 Monit or Value for Port 3. See Signal Label

C2 Byte Monitor Section on page 384.0x00

0x40030 15:8 TMUX_F2MON13[7:0] Receive F2 Previous Monitor Value for Port 3. See

Path User Byte F2 Monitor Section on page 386.0x00

7:0 TMUX_F2MON03[7:0] Receive F2 Current Monitor Value for Port 3. See Path

User Byte F2 Monitor Section on page 386.0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

104 Agere Systems Inc.

8 TMUX Registers (continued)

Table 114. TMUX_RPOHMON[1—3][A—D], Receive Monitor Values (RO) (continued)

Table 115. TMUX_TLS_CTL, Transmit Low-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40031 15:8 TMUX_F3MON13[7:0] Receive F3 Previous Monitor Value for Port 3. See

Path User Byte F3 Monitor Secti on o n page 386.0x00

7:0 TMUX_F3MON03[7:0] Receive F3 Current Monitor Value for Port 3. See Pat h

User Byte F3 Monitor Section on page 386.0x00

0x40032 15:8 TMUX_N1MON3[7:0] Receive N1 Monitor V alue for Port 3. See N1 Byte Mon-

itor Section on page 387.0x00

7:0 TMUX_K3MON3[7:0] Receive K3 Monitor Value for Port 3. See K3 Byte Mon-

itor Section on page 387.0x00

Address Bit Name Function Reset

Default

0x40033 15:7 RSVD Reserved. 0x000

6:4 TMUX_TLS_UNEQP[3:1] Transmit Low-Speed Unequipped Insert Control.

Control bit, when set to a logic 1, causes an unequip

signal to be generated in the selected STS-1/AU-3 time

slot in the STS-3/STM-1 (AU-4) output signal; normal

data is sent when set to a logic 0. Only

TMUX_TLS_UNEQP1 is used in AU-4 mode.

3:1 TMUX_TLS_PAISINS[3:1] Transmit Low-Speed Path AIS Insert Control. Con-

trol bit, when set to a logic 1, causes path AIS to be

inserted into the selected STS-1/TUG-3 time slot in the

STS-3/STM-1 (AU-4) output signal; normal data is sent

when set to a logic 0. Only TMUX_TLS_PAISINS1 is

used in AU-4 mode.

0 TMUX_TLSVOEPAR T ransmit Low- Speed Verify Odd or Even Pari ty. Con-

trol bit, when set to a logic 0, causes odd parity to be

verified per byte transfer per STS-1/AU-3 input; other-

wise, even parity is verified.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

105Agere Systems Inc.

8 TMUX Registers (continued)

Table 116. TMUX_THS_PORT_CTL, Transmit High-Speed Port Control Parameters (R/W)

Table 117. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40034 15:4 RSVD Reserved. 0x000

3 TMUX_TPSMUXSEL3 T ransmit High-Speed Protection MUX Selection. Control

bit, when set to a logic 1, causes the receive side working

input STS-3/STM-1 (AU-4) signal to be selected; otherwise,

the signal coming in from the transmit low-speed side (tele-

com bus) and POH MUX is selected. The output of this

MUX is sent to a transport overhead MUX and eventually

out the TPSD155P/N (pins AF13, AE13) and TPSC155P/N

(pins AC12, AD13) outputs.

2 TMUX_TPSMUXSEL2 T ransmit High-Speed Protection MUX Selection. Control

bit, when set to a logic 1, causes the receive side protection

input STS-3/STM-1 (AU-4) signal to be selected; otherwise,

the signal coming in from the transmit low-speed side (tele-

com bus) and POH MUX is selected. The output of this

MUX is sent to a transport overhead MUX and eventually

out the THSDP/N (pins AF9, AE9) output.

1 TMUX_RHS2THSLB Receive High-Speed to T r ansmit High-Speed Loopback

Control. Control bit, when set to a logic 1, causes the

receive STS-3/STM-1 (AU-4) input signal to be looped back

to the transmit high-speed output; loopback is disabled

when set to a logic 0.

0 TMUX_THSSCR Transmi t H igh -Speed Scramble En able . Control bit,

when set to a logic 1, causes the output STS-3/STM-1

(AU-4) signal to be scrambled; the signal is not scrambled if

set to a logic 0.

Address Bit Name Function Reset

Default

0x40035 15:13 RSVD Reserved. 0x0

12 TMUX_TCONCATMODE T r ansmit a Concatenated Signal. Control bit, when set

to a logic 1, causes the outgoing STS-3/STM-1 signal to

be concatenated; otherwise, the outgoing signal is three

independent STS-1s (for a 155 MHz signal).

11 TMUX_TPREIRDISEL Transmit MUX Selection Control for Outgoing Path

REI and RDI. Control bit, when set to a logic 1, causes

the path REI and RDI signals to be selected from the

protection boar d ; other wise, they are deriv ed from the

receive side of the same TMUX.

10 TMUX_TLREIRDISEL Transmit MUX Selection Control for Outgoing Line

REI and RDI. Control bit, when set to a logic 1, causes

the line REI and RDI signals to be selected from the pro-

tection board; otherwise, they are derived from the

receive side of the same TMUX.

9:8 TMUX_TSS[1:0] Transmit SS (Bits). These bits are inserted into the out-

going pointer value (but not in the concatenation values). 00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

106 Agere Systems Inc.

8 TMUX Registers (continued)

Table 117. TMUX_THS_TOH_CTL, Transmit High-Speed Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

0x40035 7 TMUX_THSLREIINH Transmit Line REI Inhibit. Control bit, when set to a logic 1,

disables hardware insertion of line REI (B2 errors) in the outgo-

ing STM-1 (AU-4) frame M1 byte; a logic 0 enables hardware

insertion of line REI.

6 TMUX_THSLAISINS Transmit High-Speed Line AIS Ins ertion. Control bit, when

set to a logic 1, causes line AIS to be inserted into the outgoing

STS-3/STM-1 (AU-4) signal; otherwise, line AIS is not sent.

5 TMUX_THSAPSINS T ransmit APS Value Insert (Control). Control bit, when set to

a logic 1, inserts the value in TMUX_TAPSINS[12:0]

(Table 123 on page 112) into the outgoing K1 and K2[7:3]

bytes in the STS-3/STM-1 (AU-4) frame; a logic 0 inserts the

default value based on SMPR_OH_DEFLT (Table 77 on

page 70).

4 TMUX_THSK2INS Transmit K2[2:0] Insert (Control). Control bit, when set to a

logic 1, inserts the value in TMUX_TK2INS[2:0] (Table 123 on

page 112) into the outgoing K2 byte in the STS-3/STM-1 (AU-

4) frame; a logic 0 inserts the default value based on RDI_L.

3 TMUX_THSS1INS Transmit S1 Insert (Control). Control bit, when set to a

logic 1, inserts the value in TMUX_TS1INS[7:0] (Table 122 on

page 112) into the outgoing S1 byte in the STS-3/STM-1 (AU-

4) frame; a logic 0 allows insertion from the TTOAC channel or

a default value.

2 TMUX_THSF1INS Transmit F1 Insert (Control). Control bit, when set to a logic

1, inserts the value in TMUX_TF1INS[7:0] (Table 122 on

page 112) into the outgoing S1 byte in the STS-3/STM-1 (AU-

4) frame; a logic 0 allows insertion from the TTOAC channel or

a default value.

1 TMUX_THSZ0INS Transmit Z0-2 and Z0-3 Insert (Control). Control bit, when

set to a logic 1, inserts the values in TMUX_TZ02INS[7:0]

(Table 121 on page 112) and TMUX_TZ03INS[7:0] (Table 121

on page 112) into the outgoing Z0-2 and Z0-3 bytes in the

STS-3/STM-1 (AU-4) frame; a logic 0 inserts the default value

based on SMPR_OH_DEFLT.

0TMUX_THSJ0INSTransmit J0 Insert (Control). Control bit, when set to a logic

1, inserts the 16-byte sequence TMUX_TJ0DINS[16—1][7:0]

(Table 143 on page 123) into the outgoing STS-3/STM-1 (AU-

4) frame; a logic 0 inserts the default value based on

SMPR_OH_DEFLT.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

107Agere Systems Inc.

8 TMUX Registers (continued)

Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40036 15:9 RSVD Reserved. 0x00

8 TMUX_THSPREIINH1 T ransmit Path REI Inhibit for Port 1. Control bit, when set to

a logic 1, disables hardware insertion of path REI (B3 errors)

in the outgoing STM-1 (AU-4) frame G1 byte; a logic 0

enables hardware insertion of path REI. Only port 1 control is

valid in AU-4 mode .

7 TMUX_TPOHTHRU1 Transmit High-Speed Path Overhead Insertion from Low-

Speed Input (Telecom Bus). Contr ol bit, when set to a logic

1, causes all path overhead bytes, and H1, H2, and H3, to be

passed through from the low-speed telecom bus to the high-

speed output signal. Only port 1 control is valid in AU-4 mode.

6 TMUX_THSN1INS1 Transmit N1 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS1[7:0]

(Table 124 on page 112) into the outgoing N1 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

5 TMUX_THSK3INS1 Transmit K3 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TK3INS1[7:0]

(Table 124 on page 112) into the outgoing K3 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

4 TMUX_THSF3INS1 Transmit F3 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TF3INS1[7:0]

(Table 124 on page 112) into the outgoing F3 byte in the STS-

3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

3 TMUX_THSF2INS1 Transmit F2 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TF2INS1[7:0]

(Table 124 on page 112) into the outgoing F2 byte in the STS-

3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

2 TMUX_THSRDIPINS1 Transmit Path RDI Insert (Control) for Port 1. Control bit,

when set to a logic 1, inserts the value in

TMUX_TRDIPINS1[2:0] (Table 124 on page 112) into the out-

going G1[3:1] bits in the STS-3/STM-1 (AU-4) frame; a logic 0

allows insertion from the TPOAC channel or a default value.

Only port 1 control is valid in AU-4 mode.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

108 Agere Systems Inc.

8 TMUX Registers (continued)

Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

0x40036 1 TMUX_THSC2INS1 Transmit C2 Insert (Control) for Port 1. Control bit, when

set to a logic 1, inserts the value in TMUX_TC2INS1[7:0]

(Table 124 on page 112) into the outgoing C2 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

0 TMUX_THSJ1INS1 T ransmit J1 Insert (Control) for Port 1. Control bit, when set

to a logic 1, inserts the 64-byte sequence

TMUX_TJ1DINS1[64—1][7:0] (Table 150 on page 125) into

the outgoing STS-3/STM-1 (AU-4) frame; a logic 0 allows

insertion from the TPOAC channel or a default value. Only

port 1 control is valid in AU-4 mode.

0x40037 15:9 RSVD Reserved. 0

8 TMUX_THSPREIINH2 T ransmit Path REI Inhibit for Port 2. Control bit, when set to

a logic 1, disables hardware insertion of path REI (B3 errors)

in the outgoing STS-3/STM-1 (AU-4) frame G1 byte; a logic 0

enables hardware insertion of path REI. Only port 1 control is

valid in AU-4 mode.

7 TMUX_TPOHTHRU2 Transmit High-Speed Path Overhead Insertion from Low-

Speed Input (Telecom Bus). Control bit, when set to a logic

1, causes all path overhead bytes for port 2, and H1, H2 and

H3, to be passed through from the low-speed telecom bus to

the high-speed output signal. Only port 1 control is valid in

AU-4 mode.

6 TMUX_THSN1INS2 Transmit N1 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS2[7:0]

(Table 124 on page 112) into the outgoing N1 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

5 TMUX_THSK3INS2 Transmit K3 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TK3INS2[7:0]

(Table 124 on page 112) into the outgoing K3 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

4 TMUX_THSF3INS2 Transmit F3 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inse rts the value in TMUX_TF3INS2[7:0]

(Table 124 on page 112) into the outgoing F3 byte in the STS-

3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

109Agere Systems Inc.

8 TMUX Registers (continued)

Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

0x40037 3 TMUX_THSF2INS2 Transmit F2 Insert (Control) for Port 2. Con trol bit, when

set to a logic 1, inserts the value in TMUX_TF2INS2[7:0]

(Table 124 on page 112) into the outgoing F2 byte in the STS-

3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

2 TMUX_THSRDIPINS2 Transmit Path RDI Insert (Control) for Port 2. Control bit,

when set to a logic 1, inserts the value in

TMUX_TRDIPINS2[2:0] (Table 124 on page 112) into the out-

going G1[3:1] bits in the STS-3/STM-1 (AU-4) frame; a logic 0

allows insertion from the TPOAC channel or a default value.

Only port 1 control is valid in AU-4 mode.

1 TMUX_THSC2INS2 Transmit C2 Insert (Control) for Port 2. Control bit, when

set to a logic 1, inserts the value in TMUX_TC2INS2[7:0]

(Table 124 on page 112) into the outgoing C2 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

0 TMUX_THSJ1INS2 T ransmit J1 Insert (Control) for Port 2. Control bit, when set

to a logic 1, inserts the 64-byte sequence

TMUX_TJ1DINS2[64—1][7:0] (Table 151 on page 125) into

the outgoing STS-3/STM-1 (AU-4) frame; a logic 0 allows

insertion from the TPOAC channel or a default value. Only

port 1 control is valid in AU-4 mode.

0x40038 15:9 RSVD Reserved. 0x00

8 TMUX_THSPREIINH3 T ransmit Path REI Inhibit for Port 3. Control bit, when set to

a logic 1, disables hardware insertion of path REI (B3 errors)

in the outgoing STS-3/STM-1 (AU-4) frame G1 byte; a logic 0

enables hardware insertion of path REI. Only port 1 control is

valid in AU-4 mode .

7 TMUX_TPOHTHRU3 Transmit High-Speed Path Overhead Insertion from Low-

Speed Input (Telecom Bus). Contr ol bit, when set to a logic

1, causes all path overhead bytes for port 3, and H1, H2, and

H3, to be passed through from the low-speed telecom bus to

the high-speed output signal. Only port 1 control is valid in

AU-4 mode.

6 TMUX_THSN1INS3 Transmit N1 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TN1INS3[7:0]

(Table 124 on page 112) into the outgoing N1 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

5 TMUX_THSK3INS3 Transmit K3 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TK3INS3[7:0]

(Table 124 on page 112) into the outgoing K3 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from the

TPOAC channel or a default value. Only port 1 control is valid

in AU-4 mode.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

110 Agere Systems Inc.

8 TMUX Registers (continued)

Table 118. TMUX_THS_POH[1—3]_CTL, Transmit High-Speed Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

0x40038 4 TMUX_THSF3INS3 Transmit F3 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TF3INS3[7:0]

(Table 124 on page 112) into the outgoing F3 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from

the TPOAC channel or a default value. Only port 1 control is

valid in AU-4 mode.

3 TMUX_THSF2INS3 Transmit F2 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TF2INS3[7:0]

(Table 124 on page 112) into the outgoing F2 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from

the TPOAC channel or a default value. Only port 1 control is

valid in AU-4 mode.

2 TMUX_THSRDIPINS3 Transmit Path RDI Insert (Control) for Port 3. Control bit,

when set to a logic 1, inserts the value in

TMUX_TRDIPINS3[2:0] (Table 124 on page 112) into the

outgoing G1[3:1] bits in the STS-3/STM-1 (AU-4) frame; a

logic 0 allows insertion from the TPOAC channel or a default

value. Only port 1 control is valid in AU-4 mode.

1 TMUX_THSC2INS3 Transmit C2 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the value in TMUX_TC2INS3[7:0]

(Table 124 on page 112) into the outgoing C2 byte in the

STS-3/STM-1 (AU-4) frame; a logic 0 allows insertion from

the TPOAC channel or a default value. Only port 1 control is

valid in AU-4 mode.

0 TMUX_THSJ1INS3 Transmit J1 Insert (Control) for Port 3. Control bit, when

set to a logic 1, inserts the 64-byte sequence

TMUX_TJ1DINS3[64—1][7:0] (Table 152 on page 125) into

the outgoing STS-3/STM-1 (AU-4) frame; a logic 0 allows

insertion from the TPOAC channel or a default value. Only

port 1 control is valid in AU-4 mode.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

111Agere Systems Inc.

8 TMUX Registers (continued)

Table 119. TMUX_TLRDI_CTL, Transmit High-Speed Line RDI Control Parameters (R/W)

Table 120. TMUX_TPRDI_CTL, Transmit High-Speed Path RDI Control Parameters (R/W)

Address Bit Name Function Reset Default

0x4003A 15:7 RSVD Reserved. 0x000

6 TMUX_TRHSSD_LRDIINH Transmit Receive High -Speed Signal

Degrade L-RDI Inhibit. Control bit, when

set to a logic 1, causes the associated fail-

ure not to contribute to the automatic inser-

tion of RDI-L; otherwise, the associated

alarm contributes to the generation of RDI-L.

5 TMUX_TRHSSF_LRDIINH Transmit Receive High-Speed Signal Fail

L-RDI Inhibit. Control bit, when set to a

logic 1, causes the associated failure not to

contribute to the automatic insertion of

RDI-L; otherwise, the associated alarm con-

tributes to the generation of RDI-L.

4 TMUX_TRLAISMON_LRDIINH Transmit Receive Line AIS Line RDI

Inhibit. Same as above. 0

3 TMUX_TRHSLOF_LRDIINH Transmit Receive High-Speed Loss-of-

Frame Line RDI Inhibit. Same as above . 0

2 TMUX_TRHSOOF_LRDIINH Transmit Receive High-Speed Out of

Frame Line RDI Inhibit. Same as above . 0

1 TMUX_TRHSLOS_LRDIINH Transmit Receive High-Speed Loss-of-

Signal Line RDI Inhibit. Same as abo ve . 0

0 TMUX_TRILOC_LRDIINH Transmit Receive Input Loss-of-Clock

Line RDI Inhibit. Same as abo ve. 0

Address Bit Name Function Reset

Default

0x4003B 15:8 RSVD Reserved. 0x000

7:5 TMUX_TRTIM_PRDIINH[3:1] Transmit Receive Trace Identifier Mismatch Path

RDI Inhibit. When a 1, causes the associated failure not

to contribute to the automatic insertion of RDI-P; other-

wise, the associated alarm contributes to the generation

of RDI-P.

4 TMUX_TRUEQ_PRDIINH T ransmit Receive Unequipped Path RDI Inhibit.

When a 1, causes the associated failure not to contrib-

ute to the automatic insertion of RDI-P; otherwise, the

associated alarm contributes to the generation of RDI-P.

3 TMUX_TRPLM_PRDIINH T ransmit Receive Payload Label Mismatch Path RDI

Inhibit. When a 1, causes the associated failure not to

contribute to the automatic insertion of RDI-P; other-

wise, the associated alarm contributes to the generation

of RDI-P.

2 TMUX_TRLOP_PRDIINH Transmit Receive Loss of Pointer RDI Inhibit. When

a 1, causes the associated failure not to contribute to

the automatic insertion of RDI-P; otherwise, the associ-

ated alarm contributes to the generation of RDI-P.

1 TMUX_TRPAIS_PRDIINH Transmit Receive Path AIS RDI Inhibit. Same as

above. 0

0 TMUX_TEPRDI_MODE Transmit Enhanced RDI Mode. When a 1, causes the

enhanced 3-bit path RDI value to be transmitted in

G1[3:1]; otherwise, a 1-bit value (G1[3]) is sent.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

112 Agere Systems Inc.

8 TMUX Registers (continued)

Table 121. TMUX_TZ0_INS_VAL, Transmit TOH and POH Insert Values (R/W)

Table 122. TMUX_TS1_F1_INS_VAL, Transmit TOH and POH Insert Values (R/W)

Table 123. TMUX_TAPS_INS_VAL, Transmit TOH and POH Insert Values (R/W)

Address Bit Name Function Reset

Default

0x4003C 15:8 TMUX_TZ03INS[7:0] Transmit Z0-3 Data Insert Value. Register value is

inserted into the STS-3/STM-1 (AU-4) output Z0-3 byte

if TMUX_THSZ0INS (Tab le 117 on page 105) is

asserted.

0x00

7:0 TMUX_TZ02INS[7:0] Transmit Z0-2 Data Insert Value. Register value is

inserted into the STS-3/STM-1 (AU-4) output Z0-2 byte

if TMUX_THSZ0INS is asserted.

0x00

Address Bit Name Function Reset

Default

0x4003D 15:8 TMUX_TS1INS[7:0] Transmit S1 Data Insert Value. Register value is

inserted into the STS-3/STM-1 (AU-4) output S1 byte if

TMUX_THSS1INS (Table 117 on page 105) is asserted.

0x00

7:0 TMUX_TF1INS[7:0] Transmit F1 Data Insert Value. Register value is

inserted into the STS-3/STM-1 (AU-4) output F1 byte if

TMUX_THSF1INS (Table 117 on page 105) is asse rt ed.

0x00

Address Bit Name Function Reset

Default

0x4003E 15:3 TMUX_TAPSINS[12:0] Transmit APS Data Insert Value. Re gi ster value is

inserted into the STS-3/STM-1 (AU-4) output K1[7:0] and

K2[7:3] bits if TMUX_THSAPSINS (Table 117 on

page 105) is asserted.

0x00

2:0 TMUX_TK2INS[2:0] Transmit K2 Data Insert Value. Register value is inserted

into the STS-3/STM-1 (AU-4) output K2[2:0] bits if

TMUX_THSK2INS (Table 117 on page 105) is asserted.

000

Table 124. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W)

Address Bit Na me Function Reset

Default

0x4003F 15:11 RSVD Reserved. 0x00

10:8 TMUX_TRDIPINS1[2:0] Transmit Path RDI Data Insert Value for Port 1. Register

value is inserted into the STS-3/STM-1 (AU-4) output

G1[3:1] bits if TMUX_THSRDIPINS1 (Tab le 118 on

page 107) is asserted, regardless of the value of

TMUX_TEPRDI_ MODE ( Table 120 on page 111).

000

7:0 TMUX_TC2INS1[7:0] Transmit C2 Data Insert Value for Port 1. Register value

is inserted into the STM-1 (AU-4) output C2 byte if

TMUX_THSC2INS1 (Table 118 on page 107) is asserted.

0x00

0x40040 15:8 TMUX_TF3INS1[7:0] T ransmit F3 Data Insert V alue for Port 1. Register value is

inserted into the STM-1 (AU-4) output F3 byte if

TMUX_THSF3INS1 (Table 118 on page 107) is asserted.

0x00

7:0 TMUX_TF2INS1[7:0] T ransmit F2 Data Insert V alue for Port 1. Register value is

inserted into the STM-1 (AU-4) output F2 byte if

TMUX_THSF2INS1 (Table 118 on page 107) is asserted.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

8 TMUX Registers (continued)

113Agere Systems Inc.

Address Bit Name Function Reset

Default

0x40041 15:8 TMUX_TN1INS1[7:0] Transmit N1 Data Insert Value for Port 1. Register value

is inserted into the STM-1 (AU-4) output N1 byte if

TMUX_THSN1IN S1 (Table 118 on page 107) is asserted.

0x00

7:0 TMUX_TK3INS1[7:0] Transmit K3 Data Insert Value for Port 1. Register value

is inserted into the STM-1 (AU-4) output K3 byte if

TMUX_THSK3INS1 (Table 118 on page 107) is asserted.

0x00

0x40042 15:11 RSVD Reserved. 0x00

10:8 TMUX_TRDIPINS2[2:0] Transmit Path RDI Data Insert Value for Port 2. Register

value is inserted into the STS-3/STM-1 (AU-4) output

G1[3:1] bits if TMUX_THSRDIPINS2 (Table 118 on

page 107) is asser ted, regardless of the value of

TMUX_TEPRDI_MODE.

000

7:0 TMUX_TC2INS2[7:0] Transmit C2 Data Insert Value for Port 2. Register value

is inserted into the STM-1 (AU-4) output C2 byte if

TMUX_THS C2IN S1 is asse rted.

0x00

0x40043 15:8 TMUX_TF3INS2[7:0] T ransmit F3 Data Insert V alue for Port 2. Register value is

inserted into the STM-1 (AU-4) output F3 byte if

TMUX_THSF3INS1 is asserted.

0x00

7:0 TMUX_TF2INS2[7:0] T ransmit F2 Data Insert V alue for Port 2. Register value is

inserted into the STM-1 (AU-4) output F2 byte if

TMUX_THSF2INS1 is asserted.

0x00

0x40044 15:8 TMUX_TN1INS2[7:0] Transmit N1 Data Insert Value for Port 2. Register value

is inserted into the STM-1 (AU-4) output N1 byte if

TMUX_THSN1IN S1 (Table 118 on page 107) is asserted.

0x00

7:0 TMUX_TK3INS2[7:0] Transmit K3 Data Insert Value for Port 2. Register value

is inserted into the STM-1 (AU-4) output K3 byte if

TMUX_THSK3INS1 (Table 118 on page 107) is asserted.

0x00

0x40045 15:11 RSVD Reserved. 0x00

10:8 TMUX_TRDIPINS3[2:0] Transmit Path RDI Data Insert Value for Port 3. Register

value is inserted into the STS-3/STM-1 (AU-4) output

G1[3:1] bits if TMUX_THSRDIPINS3 (Table 118 on

page 107) is asser ted, regardless of the value of

TMUX_TEPRDI_MODE.

000

7:0 TMUX_TC2INS3[7:0] Transmit C2 Data Insert Value for Port 3. Register value

is inserted into the STM-1 (AU-4) output C2 byte if

TMUX_THSC2IN S1 (Table 118 on page 107) is asserted.

0x00

0x40046 15:8 TMUX_TF3INS3[7:0] T ransmit F3 Data Insert V alue for Port 3. Register value is

inserted into the STM-1 (AU-4) output F3 byte if

TMUX_THSF3INS1 (Table 118 on page 107) is asserted.

0x00

7:0 TMUX_TF2INS3[7:0] T ransmit F2 Data Insert V alue for Port 3. Register value is

inserted into the STM-1 (AU-4) output F2 byte if

TMUX_THSF2INS1 (Table 118 on page 107) is asserted.

0x00

0x40047 15:8 TMUX_TN1INS3[7:0] Transmit N1 Data Insert Value for Port 3. Register value

is inserted into the STM-1 (AU-4) output N1 byte if

TMUX_THS N1IN S1 is asse rted.

0x00

7:0 TMUX_TK3INS3[7:0] Transmit K3 Data Insert Value for Port 3. Register value

is inserted into the STM-1 (AU-4) output K3 byte if

TMUX_THSK3INS1 is asserted.

0x00

Table 124. TMUX_TPOH[1—3]_INS_[A—C], Transmit TOH and POH Insert Values (R/W) (continued)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

114 Agere Systems Inc.

8 TMUX Registers (continued)

Table 125. TMUX_TBERINS_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40048 15:13 RSVD Reserved. 0x0

12 TMUX_TPSLREIINS Transmit Protection Signal Line REI Insert. Con-

trol bit, when set to a logic 1, causes one line REI

error in the outgoing protection STS-3/STM-1 (AU-4)

signal when there is a rising edge observed on the

SMPR_BER_INSRT (Table 75 on page 68) input

signal.

11 TMUX_TPSB2EIINS Transmit Protection Signal B2 Error Insert. Con-

trol bit , whe n se t t o a lo gi c 1, cau s es one B2 er ro r in

the outgoing protection STS-3/STM-1 (AU-4) signal

when there is a rising edge observed on the

SMPR_BER_INSRT (Table 75 on page 68) input

signal.

10:8 TMUX_TPREIINS[3:1] Transmit Path REI Error Insert. Control bit, when

set to a logic 1, causes one path REI error in the out-

going STS-3/STM-1 (AU-4) signal. Only port 1 con-

trol is vali d in AU-4 mode.

7:5 TMUX_THSB3ERRINS[3:1] Transmit High-Speed B3 Error Insert. Control bit,

when set to a logic 1, causes the output B3 byte in

the outgoing STS-3/STM-1 (AU-4) signal to be

inverted when there is a rising edge observed on the

SMPR_BER_INSRT (Table 75 on page 68) input

signal. Only port 1 control is valid in AU-4 mode.

4 TMUX_TLREIINS Transmit High-Speed Line REI Insert. Control bit,

when set to a logic 1, causes one line REI error in

the outgoing STS-3/STM-1 (AU-4) signal.

3:1 TMUX_THSB2ERRINS[3:1] Transmit High-Speed B2 Error Insert. Control bit,

when set to a logic 1, causes the output B2 bytes in

the outgoing STS-3/STM-1 (AU-4) signal to be

inverted when there is a rising edge observed on the

SMPR_BER_INSRT (Table 75 on page 68) input

signal.

000

0 TMUX_THSB1ERRINS Transmit High-Speed B1 Error Insert. Control bit,

when set to a logic 1, causes the output B1 byte in

the outgoing STS-3/STM-1 (AU-4) signal to be

inverted when there is a rising edge observed on the

SMPR_BER_INSRT (Table 75 on page 68) input

signal.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

115Agere Systems Inc.

8 TMUX Registers (continued)

Table 126. TMUX_THS_ERR_CTL, Transmit High-Speed Error Insertion Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x40049 15:10 RSVD Reserved. 0x00

9 TMUX_TAPSBABINS Transmit APS Babble Insert. When 1, causes an

inconsistent APS byte (K1[7:0], K2[7:3]) to be inserted

into the outgoing STS-3/STM-1 (AU-4) frame.

8:6 TMUX_TH1H2INVEN[3:1] Transmit H1 H2 Corrupt Enable. When 1, causes the

output H1 and H2 bytes of the STS-3/STM-1 (AU-4) sig-

nal to be corrupted on a per STS-1 basis. In the AU-4

mode, only con tr ol bit 1 is used.

000

5 TMUX_TH1H2INVORNDF Transmit H1 H2 Corrupt or NDF. When 0, causes an

invalid pointer to be inserted into the output H1 and H2

bytes; otherwise, a continuous NDF condition (1001) is

sent.

4:0 TMUX_TA2ERRINS[4:0] Transmit Frame Error Insert Value. These bits specify

the number of consecutive frames when a frame error is

inserted in the outgoing A2 byte. This number of errored

frames is sent each time a rising edge is observed on

the SMPR_BER_INSRT (Table 75 on page 68) input

signal.

0x0

Table 127. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4004A 15 TMUX_RTOAC_D412MODE Receive TOAC DCC4 to DCC12 Only Mode. When

1, causes the RTOAC data signal to carry only a par-

ity byte followed by DCC4 to DCC12 bytes. The

clock rate is 640 kHz. If this control bit is a logic 0

and TMUX_RTOAC_D13MODE is a logic 0, then the

receive TOAC channel is in full access mode.

14 TMUX_RTOAC_D13MODE Receive TOAC DCC1 to DCC3 Only Mode. When

1, causes the RTOAC data signal to carry only a par-

ity byte followed by DCC1 to DCC3 bytes. The clock

rate is 260 kHz. If this control bit is a logic 0 and

TMUX_RTOAC_D412MODE is a logic 0, then the

receive TOAC channel is in full access mode.

13 TMUX_RTOAC_OEPINS Receive TOAC Odd or Even Parity Insert. When 1,

forces receive the output TOAC parity bit to be even;

otherwise, the parity is odd.

12:10 RSVD Reserved. 000

9 TMUX_TTOAC_D412MODE Transmit TOAC DCC4 to DCC12 Only Mode.

When 1, causes DCC4 to DCC12 in the outgoing

frame to be inserted from the TTOAC channel. The

TTOAC clock rate is 640 kHz. If this control bit is a

logic 0 and TMUX_TTOAC_D13MODE is a logic 0,

then the transmit TOAC channel is in full access

mode.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

8 TMUX Registers (continued)

116 Agere Systems Inc.

0x4004A 8 TMUX_TTOAC_D13MODE Transmit TOAC DCC1 to DCC3 Only Mode.

When 1, causes DCC1 to DCC3 in the outgoing

frame to be inserted from the TTOAC channel. The

TTOAC clock rate is 260 kHz. If this control bit is a

logic 0 and TMUX_TTOAC_D13MODE is a logic 0,

then the transmit TOAC channel is in full access

mode.

7TMUX_TTOAC_AVAILTransmit TOAC Available Byte Control. When 1,

causes the incoming TOAC values for undefined

bytes (bold-faced bytes in Table 535 on page 379) to

be inserted into the outgoing STS-3/STM-1 frame.

Other wis e, thei r values depend on

SMPR_OH _D EFLT (Table 77 on page 70).

6 TMUX_TTOAC_S1 Transmit TOAC S1 Byte Control. When 1, causes

the incoming TOAC S1 value to be inserted into the

S1 byte of the outgoing STS-3/STM-1 frame if the

TMUX_THSS1INS (Table 117 on page 105) control

bit is deasserted. If the S1 is not inserted from regis-

ter control or from the transmit TOAC channel, then

its value depends on SMPR_OH_DEFLT.

5 TMUX_TTOAC_F1 Transmit TOAC F1 Byte Control. When 1, causes

the incoming TOAC F1 value to be inserted into the

F1 byte of the outgoing STS-3/STM-1 frame if the

TMUX_THSF1INS (Table 117 on page 105) control

bit is desasserted. If the F1 is not inserted from reg-

ister control or from the transmit TOAC channel, then

its value depends on SMPR_OH_DEFLT.

4 TMUX_TTOAC_E2 Transmit TOAC E1 Byte Control. When 1, causes

the incoming TOAC E1 value to be inserted into the

E1 byte of the outgoing STS-3/STM-1 frame. Other-

wise, the E1 value depends on SMPR_OH_DEFLT.

3 TMUX_TTOAC_E1 Transmit TOAC E1 Byte Control. When 1, causes

the incoming TOAC E1 value to be inserted into the

E1 byte of the outgoing STS-3/STM-1 frame. Other-

wise, the E1 value depends on SMPR_OH_DEFLT.

2TMUX_TTOAC_D4TO12Transmit TOAC D4 to D12 Byte Control. When 1,

causes the TTOAC values to be inserted into the D4

to D12 bytes of the outgoing frame. If this control bit

is a logic 0, then the outgoing D4 to D12 values

depend on SMPR_OH_DEFLT.

1 TMUX_TTOAC_D1TO3 Transmit TOAC D1 to D3 Byte Control. When 1,

causes the TTOAC values to be inserted into the D1

to D3 bytes of the outgoing frame. If this control bit is

a logic 0, then the outgoing D1 to D3 values depend

on SMPR_OH_DEFLT.

0 TMUX_TTOAC_OEPMON Transmit TOAC Odd or Even Parity Monitor.

When 1, forces the input TOAC parity checker to

check for odd parity; otherwise, even parity is

checked on the transmit TOAC channel.

Table 127. TMUX_TOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)

Address Bit Name Function Reset

Default

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

117Agere Systems Inc.

8 TMUX Registers (continued)

Table 128. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W)

Address Bit Name Function Reset

Default

0x4004B 15:14 TMUX_RPOAC_SEL[1:0] Receive POAC STS-1 Port Selection. Designates which

STS-1 inserts its path overhead bytes into the receive

POAC channel. A value of 00 disables POAC, 01 desig-

nates STS-1 #1, 10 designates STS-1 #2, and 11 desig-

nates STS-1 #3.

13 TMUX_RPOAC_OEPINS Receive POAC Odd or Even Parity Insert. Wh en 1,

forces receive the output POAC parity bit to be even; oth-

erwise, the parity is odd.

12:10 RSVD Reserved. 000

9:8 TMUX_TPOAC_SEL[1:0] Transmit POAC STS-1 Port Selection. Designates which

STS-1 obtains path overhead bytes from the transmit

POAC channel. A value of 00 disables POAC, 01 desig-

nate STS-1 #1, 10 designates STS-1 #2, and 11 desig-

nates STS-1 #3.

7RSVDReserved. 0

6 TMUX_TPOAC_N1 Transmit POAC N1 Byte Control. When 1, causes the

incoming POAC N1 value to be inserted into the N1 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSN1INS (Table 118 on page 107) control bit is

desasserted. If the N1 is not inserted from register control

or from the transmit POAC channel, then its value

depends on SMPR_OH_DEFLT (Table 77 on page 70).

5 TMUX_TPOAC_K3 Transmit POAC K3 Byte Control. When 1, causes the

incoming POAC K3 value to be inserted into the K3 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSK3 INS (Table 118 on page 107) control bit is

desasserted. If the K3 is not inserted from register control

or from the transmit POAC channel, then its value

depends on SMP R_O H_ DEF LT.

4 TMUX_TPOAC_F3 Transmit POAC F3 Byte Control. When 1, causes the

incoming POAC F3 value to be inserted into the F3 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSF3INS (Table 118 on page 107) control bit is

desasserted. If the F3 is not inserted from register control

or from the transmit POAC channel, then its value

depends on SMP R_O H_ DEF LT.

3 TMUX_TPOAC_F2 Transmit POAC F2 Byte Control. When 1, causes the

incoming POAC F2 value to be inserted into the F2 byte of

the selected TPOAC STS-1 if the corresponding

TMUX_THSF2INS (Table 118 on page 107) control bit is

desasserted. If the F2 is not inserted from register control

or from the transmit POAC channel, then its value

depends on SMPR_OH_DEFLT (Table 77 on page 70).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

118 Agere Systems Inc.

8 TMUX Registers (continued)

Table 128. TMUX_RPOAC_CTL, Receive/Transmit TOAC/POAC Control Parameters (R/W) (continued)

Table 129. TMUX_TFRAMEOFFSET, Transmit High-Speed Offset Control Parameters (R/W)

)

Address Bit Name Function Reset

Default

0x4004B 2 TMUX_TPOAC_C2 Transmit POAC C2 Byte Control. When 1, causes

the incoming POAC C2 value to be inserted into the

C2 byte of the selected TPOAC STS-1 if the corre-

spondi ng TMUX _THSC 2INS (Table 118 on page 107)

control bit is desasserted. If the C2 is not inserted from

then its value depends on SMPR_OH_DEFLT.

1TMUX_TPOAC_J1Transmit POAC J1 Byte Control. Control bit, when

set to a logic 1, causes the incoming POAC J1 value to

be inserted into the J1 byte of the selected TPOAC

STS-1 if the corresponding TMUX_THSJ1INS

(Table 118 on page 107) control bit is desasserted. If

the J1 is not inserted from register control or from the

transmit POAC channel, then its value depends on

SMPR_OH_ DEFLT.

0 TMUX_TPOAC_OEPMON T r ansmit TOAC Odd or Even Parity Monitor. Control

bit, when set to a logic 1, forces the input TOAC parity

checker to check for odd parity; otherwise, even parity

is checked on the transmit TOAC channel.

Address Bit Name Function Reset

Default

0x4004D 15:13 TMUX_TLBITCNT[2:0] Transmit Load Bit Count. Allows the outp ut

STS-3/STM-1 (AU-4) frame to have any relationship to

the input frame sync pulse (THSSJ0J1V1I).

000

12:11 TMUX_TLSTSCNT[1:0] Transmit Load STS-1 Count. Same as abo ve . 00

10:4 TMUX_TLCOLCNT[6:0] Transmit Load Column Count. Same as abo ve . 000 0000

3:0 TMUX_TLROWCNT[3:0] Transmit Load Row Count . Same as above. 0000

Table 130. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W)

Address Bit Name Function Reset

Default

0x4004E

0x4004F 15:0

2:0 TMUX_SDNSSET[18:3]

TMUX_SDNSSET[2:0] Signal Degrade Ns Set. Number of frames in a

monitoring block for signal degrade (SD). 0x00000

0x4004F 15

14:7 RSVD

TMUX_SDMSET[7:0] Reserved.

Signal Degrade M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad blocks is above this threshold, then SD

is set.

0x00

6:3 TMUX_SDLSET[3:0] Signal Degrade L Set. Error threshold for determining

if a monitoring block is bad. 0x0

0x40050 15:0 TMUX_SDBSET[15:0] Signal Degrade B Set. Number of monitoring blocks. 0x0000

0x40051

0x40052 15:0

2:0 TMUX_SDNSCLEAR[18:3]

TMUX_SDNSCLEAR[2:0] Signal Degrade Ns Clear. Number of frames in a

monitoring block for SD. 0x00000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

8 TMUX Registers (continued)

119Agere Systems Inc.

Table 131. TMUX_SF_CTL[1—6], B1/B2 Signal Fail Set/Clear Control Registers (R/W)

0x40052 15

14:7 RSVD

TMUX_SDMCLEAR[7:0] Reserved.

Signal Degrade M Clear. Threshold of the number of

bad monitoring blocks in an observation interval. If the

number of bad blocks is below this threshold, then SD is

cleared.

0x00

6:3 TMUX_SDLCLEAR[3:0] Signal Degrad e L Clear. Error threshold for

determining if a monitoring block is bad. 0x0

0x40053 15:0 TMUX_SDBCLEAR[15:0] Signal Degrade B Clear. Number of monitoring blocks. 0x0000

Address Bit Name Function Reset

Default

0x40054

0x40055 15:0

2:0 TMUX_SFNSSET[18:3]

TMUX_SFNSSET[2:0] Signal Fail Ns Set. Number of frames in a monitoring

block for signal fail (SF). 0x00000

0x40055 15

14:7 RSVD

TMUX_SFMSET[7:0] Reserved.

Signal Fail M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the num-

ber of bad blocks is above this threshold, then SF is

set.

0x00

6:3 TMUX_SFLSET[3:0] Signal Fail L Set. Error threshold for determining if a

monitoring block is bad. 0x0

0x40056 15:0 TMUX_SFBSET[15:0] Signal Fail B Set. Number of monitoring blocks. 0x0000

0x40057

0x40058 15:0

2:0 TMUX_SFNSCLEAR[18:3]

TMUX_SFNSCLEAR[2:0] Signal Fail Ns Clear . Number of frames in a monitoring

block for SF. 0x00000

0x40058 15

14:7 RSVD

TMUX_SFMCLEAR[7:0] Reserved.

Signal Fail M Clear. Threshold of the number of bad

monitoring blocks in an observation interval. If the num-

ber of bad blocks is below this threshold, then SF is

cleared.

0x00

0x40058 6:3 TMUX_SFLCLEAR[3:0] Signal Fail L Clear. Error thresh old for dete rmin ing if a

monitoring block is bad. 0x0

0x40059 15:0 TMUX_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks. 0x0000

Table 132. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W)

Address Bit Name Function Reset

Default

0x4005A

0x4005B 15:0

2:0 TMUX_B3SDNSSET[18:3]

TMUX_B3SDNSSET[2:0] B3 Signal Degrade Ns Set. Number of frames in a

monitoring block for signal degrade (SD). 0x0000

0x4005B 15

14:7 RSVD

TMUX_B3SDMSET[7:0] Reserved.

B3 Signal Degrade M Set. Thresho l d o f t h e nu m be r

of bad monitoring blocks in an observation interval. If

the number of bad blocks is above this threshold,

then SD is set.

0x00

0x4005B 6:3 TMUX_B3SDLSET[3:0] B3 Signal Degrade L Set. Error threshold for deter-

mining if a monitoring block is bad. 0x0

0x4005C 15:0 TMUX_B3SDBSET[15:0] B3 Signal Degrade B Set. Number of monitoring

blocks. 0x0000

Table 130. TMUX_SD_CTL[1—6], B1/B2 Signal Degrade Set/Clear Control Registers (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

8 TMUX Registers (continued)

120 Agere Systems Inc.

Table 133. TMUX_B3SF_CTL[1—6], B3 Signal Fail Set/Clear Control Registers (R/W)

Table 134. TMUX_B1ECNT, Receive B1 Error Counts (RO)

0x4005D

0x4005E 15:0

2:0 TMUX_B3SDNSCLEAR[18:3]

TMUX_B3SDNSCLEAR[2:0] B3 Signal Degrade Ns Clear . Number of frames in a

monitoring block for SD. 0x0000

0x4005E 15

14:7 RSVD

TMUX_B3SDMCLEAR[7:0] Reserved.

B3 Signal Degrade M Clear. Threshold of the num-

ber of bad monitoring blocks in an observation inter-

val. If the number of bad blocks is below this

threshold, then SD is cleared.

0x00

6:3 TMUX_B3SDLCLEAR[3:0] B3 Signal Degrade L Clear. Error threshold for

determining if a monitoring block is bad. 0x0

0x4005F 15:0 TMUX_B3SDBCLEAR[15:0] B3 Signal Degrade B Clear. Number of monitoring

blocks. 0x0000

Address Bit Name Function Reset

Default

0x40060

0x40061 15:0

2:0 TMUX_B3SFNSSET[18:3]

TMUX_B3SFNSSET[2:0] B3 Signal Fail Ns Set. Number of frames in a

monitoring block for SF. 0x00000

0x40061 15

14:7 RSVD

TMUX_B3SFMSET[7:0] Reserved.

B3 Signal Fail M Set. Threshold of the number of

bad monitoring blocks in an observation interval. If

the number of bad blocks is above this threshold,

then SF is set .

0x00

6:3 TMUX_B3SFLSET[3:0] B3 Signal Fail L Set. Error threshold for determin-

ing if a monitoring block is bad. 0x0

0x40062 15:0 TMUX_B3SFBSET[15:0] B3 Signal Fail B Set. Number of monitoring blocks. 0x0000

0x40063

0x40064 15:0

2:0 TMUX_B3SFNSCLEAR[18:3]

TMUX_B3SFNSCLEAR[2:0] B3 Signal Fail Ns Clear. Number of frames in a

monitoring block for SF. 0x00000

0x40064 15

14:7 RSVD

TMUX_B3SFMCLEAR[7:0] Reserved.

B3 Signal Fail M Clear . Threshold of the number of

bad monitoring blocks in an observation interval. If

the number of bad blocks is below this threshold,

then SF is clear ed .

0x00

0x40064 6:3 TMUX_B3SFLCLEAR[3:0] B3 Signal Fail L Clear. Error threshold for deter-

mining if a monitoring block is bad. 0x0

0x40065 15:0 TMUX_B3SFBCLEAR[15:0] B3 Signal Fail B Clear. Number of monitoring

blocks. 0x0000

Address Bit Name Function Reset

Default

0x40066 15:0 TMUX_B1ECNT[15:0] Receive High-Speed B1 Erro r Count . Counts the number

of B1 errors in the received STS-3/STM-1 (AU-4) frame.

This counter can either count actual BIP errors or block

errors ; se e TMUX_ BIT BL KB1 (Table 105 on page 97). This

counter holds at its maximum value or rolls over depending

on the value of SMPR_SAT_ROLLOVER (Table 77 on

page 70), and transfers its internal count to a holding regis-

ter whe n SMPR_PMRESET (Table 75 on page 68) tra ns i -

tions from a logic 0 to 1.

0x0000

Table 132. TMUX_B3SD_CTL[1—6], B3 Signal Degrade Set/Clear Control Registers (R/W) (continued)

Address Bit Name Function Reset

Default

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

121Agere Systems Inc.

8 TMUX Registers (continued)

Table 135. TMUX_B2ECNT_17_16 and TMUX_B2ECNT_15_0 , Receive B2 Error Counts (RO)

Table 136. TMUX_B3ECNT[1—3], Receive B3 Error Counts (RO)

Address Bit Name Function Reset

Default

0x40067 15:2 RSVD Reserved. 0x000

0x40067

—

0x40068

1:0

15:0

TMUX_B2ECNT[17:16]

—

TMUX_B2ECNT[15:0]

Receive High-Speed B2 Error Count. Coun ts the

number of B2 errors in the received STS-3/STM-1

(AU-4) frame. This counter can either count actual

BIP errors or block errors; see TMUX_BITBLKB2

(Table 105 on page 97). This counter holds at its

maximum value or rolls over depending on the value

of SMPR_SA T_ROLLOVER, and transfers its internal

count to a holding register when SMPR_PMRESET

transitions from a logic 0 to 1.

0x00000

Address Bit Name Function Reset

Default

0x40069 15:0 TMUX_B3ECNT1[15:0] Receive High-Speed B3 Error Count for Port 1. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU-4) frame for port 1. Only counter value 1 is valid in

AU-4 mode. This counter can either count actual BIP errors

or block errors; see TMUX_BITBLKB3 (Table 105 on

page 97). This counter holds at its maximum value or rolls

over depending on the value of SMPR_SAT_ROLLOVER

(Table 77 on page 70), and transfers its internal count to a

holding re gister when SM PR_PMRES ET (Table 75 on

page 68) transitions from a logic 0 to 1.

0x0000

0x4006A 15:0 TMUX_B3ECNT2[15:0] Receive High-Speed B3 Error Count for Port 2. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU-4) frame for port 2. Only counter value 1 is valid in

AU-4 mode. This counter can either count actual BIP errors

or block errors; see TMUX_BITBLKB3 (Table 105 on

page 97). This counter holds at its maximum value or rolls

over depending on the value of SMPR_SAT_ROLLOVER,

and transfers its internal count to a holding register when

SMPR_PMRESET transitions from a logic 0 to 1.

0x0000

0x4006B 15:0 TMUX_B3ECNT3[15:0] Receive High-Speed B3 Error Count for Port 3. Counts

the number of B3 errors in the receive STS-3/STM-1

(AU-4) frame for port 3. Only counter value 1 is valid in

AU-4 mode. This counter can either count actual BIP errors

or block errors; see TMUX_BITBLKB3 (Table 105 on

page 97). This counter holds at its maximum value or rolls

over depending on the value of SMPR_SAT_ROLLOVER,

and transfers its internal count to a holding register when

SMPR_PMRESET transitions from a logic 0 to 1.

0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

122 Agere Systems Inc.

8 TMUX Registers (continued)

Table 137. TMUX_M1ECNT_17_16 and TMUX_M1ECNT_15_0, Receive M1 Error Counts (RO)

Table 138. TMUX_G1ECNT[1—3], Receive G1 Error Counts (RO)

Address Bit Name Function Reset

Default

0x4006C 15:2 RSVD Reserved. 0x000

0x4006C

—

0x4006D

1:0

15:0

TMUX_M1ECNT[17:16]

—

TMUX_M1ECNT[15:0]

Receive Line REI Count. Counts the number of errors

received in the M1 byte of the receive

STS-3/STM-1 (AU-4) frame. This counter can either

count actual errors or block errors; see

TMUX_BITBLKM1 (Table 105 on page 97). This

counter holds at its maximum value or rolls over

depending on the value of SMPR_SAT_ROLLOVER,

and transfers its internal count to a holding register

when SMPR_PMRESET t ran si tio ns fr om a l og ic 0 t o 1.

0x00000

Address Bit Name Function Reset

Default

0x4006E 15:0 TMUX_G1ECNT1[15:0] Receive Path REI Count for Port 1 . Counts the number of

B3 errors received in the G1[7:4] bits of port 1 in the

received STS-3/STM-1 (AU-4) frame. This counter can

either count actual errors or block errors; see

TMUX_BITBLKB3 (Table 105 on page 97). This counter

holds at its maximum value or rolls over depending on the

value of SMPR_SAT_ROLLOVER (Table 77 on page 70),

and transfers its internal count to a holding register when

SMPR_PMRESET (Table 75 on page 68) transitions from a

logic 0 to 1.

0x0000

0x4006F 15:0 TMUX _G1E CNT2[15:0] Receive Pa th REI Count for Port 2. Counts the number of

B3 errors received in the G1[7:4] bits of port 2 in the

received STS-3/STM-1 (AU-4) frame. This counter can

either count actual errors or block errors; see

TMUX_BITBLKB3 (Table 105 on page 97). This counter

holds at its maximum value or rolls over depending on the

value of SMPR_SA T_ROLLOVER, and transfers its internal

count to a holding register when SMPR_PMRESET transi-

tions from a logic 0 to 1.

0x0000

0x40070 15:0 TMUX_G1ECNT3[15:0] Receive Path REI Count for Port 3 . Counts the number of

B3 errors received in the G1[7:4] bits of port 3 in the

received STS-3/STM-1 (AU-4) frame. This counter can

either count actual errors or block errors; see

TMUX_BITBLKB3 (Table 105 on page 97). This counter

holds at its maximum value or rolls over depending on the

value of SMPR_SA T_ROLLOVER, and transfers its internal

count to a holding register when SMPR_PMRESET transi-

tions from a logic 0 to 1.

0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

123Agere Systems Inc.

8 TMUX Registers (continued)

Table 139. TMUX_RPTR_INCCNT[1—3], Receive Pointer Increment Count (RO)

Table 140. TMUX_RPTR_DECCNT[1—3], Receive Pointer Decrement Count (RO)

Table 141. TMUX_RJ0EXPECTED[1—8], Expected J0 Byte Sequence (R/W)

Table 142. TMUX_RJ0CAPTURED[1—8], Captured J0 Receive Value (RO)

Table 143. TMUX_TJ0VALUE[1—8], J0 Byte Transmit Insert (R/W)

Address Bit Name Function Reset

Default

0x40074

—

0x40076

15:11 RSVD Reserved. 0x000

10:0 TMUX_RPTR_INC1[10:0]—

TMUX_RPTR_INC3[10:0] Receive Pointer Increment Count. Counts the

number of increments in the incoming pointer val-

ues. This counter holds at its maximum value or

rolls over depending on the value of

SMPR_SAT_ROLLOVER (Table 77 on page 70),

and transfers its internal count to a holding register

when SMPR_PMRESET (Table 75 on page 68)

transitions from a logic 0 to 1.

0x000

Address Bit Name Function Reset

Default

0x40077

—

0x40079

15:11 RSVD Reserved. 0x000

10:0 TMUX_RPTR_DEC1[10:0]—

TMUX_RPTR_DEC3[10:0] Receive Pointer Decrement Count. Counts the

number of decrements in the incoming pointer values.

This counter holds at its maximum value or rolls over

depending on the value of SMPR_SAT_ROLLOVER,

and transfers its internal count to a holding register

when SMPR_PMRESET transitions from a logic 0

to 1.

0x000

Address Bit Name Function Reset

Default

0x400A0

—

0x400A7

15:0 TMUX_EXPJ0DMON[16—1][7:0] Expected Receive J0 Value. Registers con-

tain either the programmed expected J0

16-byte sequence or the previously captured

J0 sequence, depending on the J0 mode.

0x0000

Address Bit Name Function Reset

Default

0x400A8

—

0x400AF

15:0 TMUX_J0DMON[16—1][7:0] Received J0 Value. Registers capture a 16-byte

sequence from the J0 byte of the receive input signal. 0x0000

Address Bit Name Function Reset

Default

0x400B0

—

0x400B7

15:0 TMUX_TJ0DINS[16—1][7:0] Transmit J0 Data Insert. Registers allow a 16-byte

sequence to be inserted into the J0 byte of the

STS-3/STM-1 (AU-4) output signal.

0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

124 Agere Systems Inc.

8 TMUX Registers (continued)

Table 144. TMUX_RJ1EXPECTED1_[1—32], Expected J1 Byte Value for Port 1 (R/W)

Table 145. TMUX_RJ1EXPECTED2_[1—32], Expected J1 Byte Value for Port 2 (R/W)

Table 146. TMUX_RJ1EXPECTED3_[1—32], Expected J1 Byte Value for Port 3 (R/W)

Table 147. TMUX_RJ1CAPTURED1_[1—32], Captured J1 Value for STS #1 (RO)

Table 148. TMUX_RJ1CAPTURED2_[1—32], Captured J1 Value for STS #2 (RO)

Table 149. TMUX_RJ1CAPTURED3_[1—32], Captured J1 Value for STS #3 (RO)

Address Bit Name Function Reset

Default

0x400E0

—

0x400FF

15:0 TMUX_EXPJ1DMON1[64—1][7:0] Expected Receive J1 Value for Port 1. Reg-

isters contain either the programmed

expected J1 16-byte/64-byte sequence or the

previously captured J1 sequence, depending

on the J1 mode.

0x0000

Address Bit Name Function Reset

Default

0x40100

—

0x4011F

15:0 TMUX_EXPJ1DMON2[64—1][7:0] Expected Receive J1 Value for Port 2. Reg-

isters contain either the programmed

expected J1 16-byte/64-byte sequence or the

previously captured J1 sequence, depending

on the J1 mode.

0x0000

Address Bit Name Function Reset

Default

0x40120

—

0x4013F

15:0 TMUX_EXPJ1DMON3[64—1][7:0] Expected Receive J1 Value for Port 3. Regis-

ters contain either the programmed expected

J1 16-byte/64-byte sequence or the previously

captured J1 sequence, depending on the J1

mode.

0x0000

Address Bit Name Function Reset

Default

0x40140

—

0x4015F

15:0 TMUX_J1DMON1[64—1][7:0] Receive J1 Monitor Data for Port 1. Registers

capture a 16-byte/64-byte sequence from the port

1, J1 byte of the STS-3/STM-1 (AU-4) input signal.

Only port 1 information is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x40160

—

0x4017F

15:0 TMUX_J1DMON2[64—1][7:0] Receive J1 Monitor Data for Port 2. Registers

capture a 64-byte sequence from the port 2, J1 byte

of the STS-3/STM-1 (AU-4) input signal. Only port 1

information is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x40180

—

0x4019F

15:0 TMUX_J1DMON3[64—1][7:0] Receive J1 Monitor Data for Port 3. Registers

capture a 64-byte sequence from the port 3 J1

byte of the STS-3/STM-1 (AU-4) input signal.

Only port 1 information is valid in AU-4 mode.

0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

125Agere Systems Inc.

8 TMUX Registers (continued)

Table 150. TMUX_TJ1VALUE_1[1—32], J1 Byte Tr ansmit Insert for STS #1 (R/W)

Table 151. TMUX_TJ1VALUE_2[1—32], J1 Byte Tr ansmit Insert for STS #2 (R/W)

Table 152. TMUX_TJ1VALUE_3[1—32], J1 Byte Tr ansmit Insert for STS #3 (R/W)

Address Bit Name Function Reset

Default

0x401A0

—

0x401BF

15:0 TMUX_TJ1DINS[64—1][7:0] T ransmit J1 Data Insert for Port 1. Registers allow

a 64-byte sequence to be inserted into the port 1, J1

byte of the STS-3/STM-1 (AU-4) output signal. Only

port 1 information is valid in AU-4 mode.

0x0000

Address Bit Name Function Reset

Default

0x401C0

—

0x401DF

15:0 TMUX_TJ1DINS2[64—1][7:0] Transmit J1 Data Insert for Port 2. Registers

allow a 64-byte sequence to be inserted into the

port 2, J1 byte of the STS-3/STM-1 (AU-4) output

signal. Only port 1 information is valid in AU-4

mode.

0x0000

Address Bit Name Function Reset

Default

0x401E0

—

0x401FF

15:0 TMUX_TJ1DINS3[64—1][7:0] Transmit J1 Data Insert for Port 3. Registers

allow a 64-byte sequence to be inserted into the

port 2, J1 byte of the STS-3/STM-1 (AU-4) output

signal. Only port 1 information is valid in AU-4

mode.

0x0000

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

126 Agere Systems Inc.

8 TMUX Registers (continued)

8.2 TMUX Register Map

Table 153. TMUX Register Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ID and Version—RO

0x40000

page 79 TMUX_

ID_R TMUX_VERSION[2: 0] TMUX _ID[7:0] = 0X04

One-Shot (0 to 1 Transition Control Bit Parameters—R/W)

0x40002

page 79 TMUX_

ONESHOT TMUX_

B3SFCLEAR TMUX_

B3SFSET TMUX_

B3SDCLEAR TMUX_

B3SDSET TMUX_

SFCLEAR TMUX_

SFSET TMUX_

SDCLEAR TMUX_

SDSET

Receive/Transmit Mod e —R/W

0x40003

page 79 TMUX_

RCV_TX_

MODE

TMUX_

STS1MODE

Del ta and Event Param eters—COR/COW

0x40004

page 80 TMUX_

TX_DLT TMUX_

TLSPARE3 TMUX_

TLSPARE2 TMUX_

TLSPARE1 TMUX_

TPOAC_PE TMUX_

TTOAC_PE TMUX_

THSILOFD TMUX_

THSILOCD

0x40005

page 80 TMUX_

RPS_

DLT

TMUX_

RPSLOFD TMUX_

RPSOOFD TMUX_

RPSILOCD TMUX_

RPSB2E TMUX_

RPSLREIE

0x40006

page 81 TMUX_

RHS_DLT TMUX_

RS1BABE TMUX_

RS1MOND TMUX_

RLRDIMOND TMUX_

RLAISMOND TMUX_

RK2MOND TMUX_

RAPSBABE TMUX_

RAPSMOND TMUX_

RF1MOND TMUX_

RTIMSD TMUX_

RHSSFD TMUX_

RHSSDD TMUX_

RHSLOSD TMUX_

RHSLOFD TMUX_

RHSOOFD TMUX_

RHSILOCD

0x40007

page 83 TMUX_

RPOH1_

DLT

TMUX_

RSFB3D1 TMUX_

RSDB3D1 TMUX_

RUNEQPE1 TMUX_

RPLMPE1 TMUX_

RN1MOND1 TMUX_

RK3MOND1 TMUX_

RF3MOND1 TMUX_

RF2MOND1 TMUX_

RRDIPD1 TMUX_

RC2MOND1 TMUX_

RTIMPD1 TMUX_

RNDFE1 TMUX_

RDECE1 TMUX_

RINCE1 TMUX_

RPAISD1 TMUX_

RLOPD1

0x40008

page 87 TMUX_

RPOH2_

DLT

TMUX_

RSFB3D2 TMUX_

RSDB3D2 TMUX_

RUNEQPE2 TMUX_

RPLMPE2 TMUX_

RN1MOND2 TMUX_

RK3MOND2 TMUX_

RF3MOND2 TMUX_

RF2MOND2 TMUX_

RRDIPD2 TMUX_

RC2MOND2 TMUX_

RTIMPD2 TMUX_

RNDFE2 TMUX_

RDECE2 TMUX_

RINCE2 TMUX_

RPAISD2 TMUX_

RLOPD2

0x40009

page 87 TMUX_

RPOH3_

DLT

TMUX_

RSFB3D3 TMUX_

RSDB3D3 TMUX_

RUNEQPE3 TMUX_

RPLMPE3 TMUX_

RN1MOND3 TMUX_

RK3MOND3 TMUX_

RF3MOND3 TMUX_

RF2MOND3 TMUX_

RDIPD3 TMUX_

RC2MOND3 TMUX_

RTIMPD3 TMUX_

RNDFE3 TMUX_

RDECE3 TMUX_

RINCE3 TMUX_

RPAISD3 TMUX_

RLOPD3

Interrupt Mask Parameters for INT Pin—R/W

0x4000A

page 89 TMUX_

TX_

MSK

TMUX_

TLSPARM3 TMUX_

TLSPARM2 TMUX_

TLSPARM1 TMUX_

TPOAC_

TMUX_

TTOAC_PM TMUX_

THSILOFM TMUX_

THSILOCM

0x4000B

page 90 TMUX_

RPS_MSK TMUX_

RPSLOFM TMUX_

RPSOOFM TMUX_

RPSILOCM TMUX_

RPSB2M TMUX_

RPSLREIM

0x4000C

page 90 TMUX_

RHS_MSK TMUX_

RS1BABM TMUX_

RS1MONM TMUX_

RLRDIMONM TMUX_

RLAISMONM TMUX_

RK2MONM TMUX_

RAPSBABM TMUX_

RAPSMONM TMUX_

RF1MONM TMUX_

RTIMSM TMUX_

RHSSFM TMUX_

RHSSDM TMUX_

RHSLOSM TMUX_

RHSLOFM TMUX_

RHSOOFM TMUX_

RHSILOCM

0x4000D

page 91 TMUX_

RPOH1_

MSK

TMUX_

RSFB3M1 TMUX_

RSDB3M1 TMUX_

RUNEQPM1 TMUX_

RPLMPM1 TMUX_

RN1MONM1 TMUX_

RK3MONM1 TMUX_

RF3MONM1 TMUX_

RF2MONM1 TMUX_

RRDIPM1 TMUX_

RC2MONM1 TMUX_

RTIMPM1 TMUX_

RNDFM1 TMUX_

RDECM1 TMUX_

RINCM1 TMUX_

RPAISM1 TMUX_

RLOPM1

0x4000E

page 91 TMUX_

RPOH2_

MSK

TMUX_

RSFB3M2 TMUX_

RSDB3M2 TMUX_

RUNEQPM2 TMUX_

RPLMPM2 TMUX_

RN1MONM2 TMUX_

RK3MONM2 TMUX_

RF3MONM2 TMUX_

RF2MONM2 TMUX_

RRDIPM2 TMUX_

RC2MONM2 TMUX_

RTIMPM2 TMUX_

RNDFM2 TMUX_

RDECM2 TMUX_

RINCM2 TMUX_

RPAISM2 TMUX_

RLOPM2

0x4000F

page 92 TMUX_

RPOH3_

MSK

TMUX_

RSFB3M3 TMUX_

RSDB3M3 TMUX_

RUNEQPM3 TMUX_

RPLMPM3 TMUX_

RN1MONM3 TMUX_

RK3MONM3 TMUX_

RF3MONM3 TMUX_

RF2MONM3 TMUX_

RRDIPM3 TMUX_

RC2MONM3 TMUX_

RTIMPM3 TMUX_

RNDFM3 TMUX_

RDECM3 TMUX_

RINCM3 TMUX_

RPAISM3 TMUX_

RLOPM3

Interrup t Mask Parameters for APSINT Pin—R/W

0x40011

page 93 TMUX_

APSINT_

MSK

TMUX_

RHSSF_

APSM

TMUX_

RHSSD_

APSM

TMUX_

RAPSMON_

APSM

TMUX_

RLAISMON_

APSM

TMUX_

RHSLOS_

APSM

TMUX_

RHSLOF_

APSM

TMUX_

RHSOOF_

APSM

TMUX_

RHSILOC_

APSM

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

127Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

State and Value Parameters —RO

0x40012

page 93 TMUX_TX_

STATE TMUX_

THSILOF TMUX_

THSILOC

0x40013

page 93 TMUX_RPS_

STATE TMUX_

RPSLOF TMUX_

RPSOOF TMUX_

RPSILOC

0x40014

page 94 TMUX_RHS_

STATE TMUX_

RLRDIMON TMUX_

RLAISMON TMUX_

RHSLOSEXTI TMUX_

RTIMS TMUX_

RHSSF TMUX_

RHSSD TMUX_

RHSLOS TMUX_

RHSLOF TMUX_

RHSOOF TMUX_

RHSILOC

0x40015

page 94 TMUX_RPOH1_

STATE TMUX_

RSFB31 TMUX_

RSDB31 TMUX_

RUNEQP1 TMUX_

RPLMP1 TMUX_

RTIMP1 TMUX_

RPAIS1 TMUX_

RLOP1

0x40016

page 95 TMUX_RPOH2_

STATE TMUX_

RSFB32 TMUX_

RSDB32 TMUX_

RUNEQP2 TMUX_

RPLMP2 TMUX_

RTIMP2 TMUX_CONCAT_

STATE2[1:0] TMUX_

RPAIS2 TMUX_

RLOP2

0x40017

page 95 TMUX_RPOH3_

STATE TMUX_

RSFB33 TMUX_

RSDB33 TMUX_

RUNEQP3 TMUX_

RPLMP3 TMUX_

RTIMP3 TMUX_CONCAT_

STATE3[1:0] TMUX_

RPAIS3 TMUX_

RLOP3

Receive High-Speed Control Parameters—R/W

0x40019

page 96 TMUX_RHS_

CTL TMUX_

LOSEXT_

LEVEL

TMUX_

RPSMUXSEL1 TMUX_

THS2RHSLB TMUX_

RHSDSCR

Receive Low-Speed C ontrol Parameters—R/W

0x4001A

page 96 TMUX_RLS_

BITBLK_CTL TMUX_RCV_SS_EXP[1:0] TMUX_

RCV_SS_

ENB

TMUX_

BITBLKG1 TMUX_

BITBLKM1 TMUX_

BITBLKB3 TMUX_

BITBLKB2 TMUX_

BITBLKB1

0x4001B

page 97 TMUX_RLS_

MODE_CTL TMUX_

RPAIS_

INS

TMUX_

8ORMAJORITY TMUX_

SDB1B2SEL TMUX_

SFB1B2SEL TMUX_J1MONMODE[2:0] TMUX_J0MONMODE[2:0] TMUX_

S1MODE4 TMUX_

RLSPAROEG TMUX_

RCONCATMODE TMUX_

REPRDI_

MODE

0x4001C

page 98 TMUX_

RAISINH_CTL TMUX_

R_M1_

BIT7

TMUX_

RSDB3_

AISINH

TMUX_

RSFB3_

AISINH

TMUX_RTIMP_AISINH[3:1] TMUX_

RUNEQP_

AISINH

TMUX_

RPLMP_

AISINH

TMUX_

RHSSD_

AISINH

TMUX_

RHSSF_

AISINH

TMUX_

RPAISLOP_

AISINH

TMUX_

RLAISMON_

AISINH

TMUX_

RLOF_

AISINH

TMUX_

ROOF_

AISINH

TMUX_

RHSLOS_

AISINH

TMUX_

RILOC_

AISINH

0x4001D

page 99 TMUX_

LOSDETCNT TMUX_FORCEC2DEF[2:0] TMUX_LOSDETCNT[10:0]

Continuous N-Times Detect Values—R/W

0x4001E

page 100 TMUX_CNTD_

TOH_A TMUX_CNTDK1K2FRAME[3:0] TMUX_CNTDK1K2[3:0] TMUX_CNTDF1[3:0] TMUX_CNTDJ0[3:0]

0x4001F

page 100 TMUX_CNTD_

TOH_B TMUX_CTDLOPCNT[1:0] TMUX_CNTDS1FRAME[3:0] TMUX_CNTDS1[3:0] TMUX_CNTDK2[3:0]

0x40020

page 101 TMUX_CNTD_

POH_A TMUX_CNTDF2[3:0] TMUX_CNTDRDIP[3:0] TMUX_C2[3:0] TMUX_CNTDJ1[3:0]

0x40021

page 101 TMUX_CNTD_

POH_B TMUX_

CTDB1SEL TMUX_CNTDN1[3:0] TMUX_CNTDK3[3:0] TMUX_CNTDF3[3:0]

0x40022

page 102 TMUX_C2EXP1 TMUX_C2EXP1[7:0]

0x40023

page 102 TMUX_

C2EXP2_3 TMUX_C2EXP3[7:0] TMUX_C2EXP2[7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

128 Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive Monitor Values—RO

0x40024

page 102 TMUX_RF1MON TMUX_RF1MON1[7:0] TMUX_RF1MON0[7:0]

0x40025

page 102 TMUX_RAPSMON TMUX_RAPSMON[12:0] TMUX_K2MON[2:0]

0x40026

page 102 TMUX_RS1MON TMUX_RS1MON[7:0]

0x40027

page 103 TMUX_RPOHMON1A TMUX_RDIPMON1[2:0] TMUX_C2MON1[7:0]

0x40028

page 103 TMUX_RPOHMON1B TMUX_F2MON11[7:0] TMUX_F2MON01[7:0]

0x40029

page 103 TMUX_RPOHMON1C TMUX_F3MON11[7:0] TMUX_F3MON01[7:0]

0x4002A

page 103 TMUX_RPOHMON1D TMUX_N1MON1[7:0] TMUX_K3MON1[7:0]

0x4002B

page 103 TMUX_RPOHMON2A TMUX_RDIPMON2[2:0] TMUX_C2MON2[7:0]

0x4002C

page 103 TMUX_RPOHMON2B TMUX_F2MON12[7:0] TMUX_F2MON02[7:0]

0x4002D

page 103 TMUX_RPOHMON2C TMUX_F3MON12[7:0] TMUX_F3MON02[7:0]

0x4002E

page 103 TMUX_RPOHMON2D TMUX_N1MON2[7:0] TMUX_K3MON2[7:0]

0x4002F

page 103 TMUX_RPOHMON3A TMUX_RDIPMON3[2:0] TMUX_C2MON3[7:0]

0x40030

page 103 TMUX_RPOHMON3B TMUX_F2MON13[7:0] TMUX_F2MON03[7:0]

0x40031

page 104 TMUX_RPOHMON3C TMUX_F3MON13[7:0] TMUX_F3MON03[7:0]

0x40032

page 104 TMUX_RPOHMON4D TMUX_N1MON3[7:0] TMUX_K3MON3[7:0]

Transmit Low-Speed Control Parameters—R/W

0x40033

page 104 TMUX_TLS_CTL TMUX_TLS_UNEQP[3:1] TMUX_TLS_PAISINS[3:1] TMUX_

TLSVOEPAR

Transmit High-Speed Por t Control Parameters—R/W

0x40034

page 105 TMUX_THS_PORT_CTL TMUX_TPSMUXSEL3 TMUX_

TPSMUXSEL2 TMUX_

RHS2THSLB TMUX_THSSCR

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

129Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit High-Speed Control Parameters—R/W

0x40035

page 105 TMUX_THS_

TOH_CTL TMUX_

TCONCA

MODE

TMUX_TPR

EIRDISEL TMUX_TLR

EIRDISEL TMUX_TSS[1:0] TMUX_THS

LREIINH TMUX_THS

LAISINS TMUX_THS

APSINS TMUX_

THSK2INS TMUX_

THSS1INS TMUX_

THSF1INS TMUX_

THSZ0INS TMUX_

THSJ0INS

0x40036

page 107 TMUX_THS_

POH1_CTL TMUX_THS

PREIINH1 TMUX_TP

OHTHRU1 TMUX_THS

N1INS1 TMUX_THS

K3INS1 TMUX_THS

F3INS1 TMUX_TH

SF2INS1 TMUX_

THSRDIPINS1 TMUX_

THSC2INS1 TMUX_

THSJ1INS1

0x40037

page 108 TMUX_THS_

POH2_CTL TMUX_THS

PREIINH2 TMUX_TP

OHTHRU2 TMUX_THS

N1INS2 TMUX_THS

K3INS2 TMUX_THS

F3INS2 TMUX_TH

SF2INS2 TMUX_

THSRDIPINS2 TMUX_

THSC2INS2 TMUX_

THSJ1INS2

0x40038

page 109 TMUX_THS_

POH3_CTL TMUX_THS

PREIINH3 TMUX_TP

OHTHRU3 TMUX_THS

N1INS3 TMUX_THS

K3INS3 TMUX_THS

F3INS3 TMUX_TH

SF2INS3 TMUX_

THSRDIPINS3 TMUX_

THSC2INS3 TMUX_

THSJ1INS3

Tr ansmit High-Speed Line RDI Control Parameters—R/W

0x4003A

page 111 TMUX_TLRDI_

CTL TMUX_

TRSD_

LRDIINH

TMUX_

TRSF_

LRDIINH

TMUX_TRL

AISMON_

LRDIINH

TMUX_

TRLOF_

LRDIINH

TMUX_

TROOF_

LRDIINH

TMUX_

TRLOS_

LRDIINH

TMUX_

TRILOC_

LRDIINH

Transmit High-Speed Path RDI Control Parameters—R/W

0x4003B

page 111 TMUX_TPRDI_

CTL TMUX_TIM_PRDIINH[3:1] TMUX_

TRUEQ_

PRDIINH

TMUX_

TRPLM_

PRDIINH

TMUX_

TRLOP_

PRDIINH

TMUX_

TRPAIS_

PRDIINH

TMUX_

TEPRDI_

MODE

Transmit TOH and POH Insert Values —R/W

0x4003C

page 112 TMUX_TZ0_INS_

VAL TMUX_TZ03INS[7:0] TMUX_TZ02INS[7:0]

0x4003D

page 112 TMUX_TS1_F1_

INS_VAL TMUX_TS1INS[7:0] TMUX_TF1INS[7:0]

0x4003E

page 112 TMUX_TAPS_

INS_VAL TMUX_TAPSINS[12:0] TMUX_TK2INS[2:0]

0x4003F

page 112 TMUX_TPOH1_

INS_A TMUX_TRDIPINS1[2:0] TMUX_TC2INS1[7:0]

0x40040

page 112 TMUX_TPOH1_

INS_B TMUX_TF3INS1[7:0] TMUX_TF2INS1[7:0]

0x40041

page 112 TMUX_TPOH1_

INS_C TMUX_TN1INS1[7:0] TMUX_TK3INS1[7:0]

0x40042

page 112 TMUX_TPOH2_

INS_A TMUX_TRDIPINS2[2:0] TMUX_TC2INS2[7:0]

0x40043

page 112 TMUX_TPOH2_

INS_B TMUX_TF3INS2[7:0] TMUX_TF2INS2[7:0]

0x40044

page 112 TMUX_TPOH2_

INS_C TMUX_TN1INS2[7:0] TMUX_TK3INS2[7:0]

0x40045

page 112 TMUX_TPOH3_

INS_A TMUX_TRDIPINS3[2:0] TMUX_TC2INS3[7:0]

0x40046

page 112 TMUX_TPOH3_

INS_B TMUX_TF3INS3[7:0] TMUX_TF2INS3[7:0]

0x40047

page 112 TMUX_TPOH3_

INS_C TMUX_TN1INS3[7:0] TMUX_TK3INS3[7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

130 Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit High-Speed Erro r Insertion Control Parame ters—R/W

0x40048

page 114 TMUX_

TBERINS_CTL TMUX_TP

SLREIINS TMUX_TP

SB2EINS TMUX_TPREIINS[3:1] TMUX_THSB3ERRINS[3:1] TMUX_

TLREIINS TMUX_THSB2ERRINS[3:1] TMUX_THS

B1ERRINS

0x40049

page 115 TMUX_THS_ERR_

CTL TMUX_TAP

SBABINS TMUX_TH1H2INVEN[3:1] TMUX_

TH1H2INV

ORNDF

TMUX_TA2ERRINS[4:0]

Receive/Transmit TOAC/POAC Control Parameters—R/W

0x4004A

page 115 TMUX_TOAC_CTL TMUX_

RTOAC_

D412MODE

TMUX_

RTOAC_

D13MODE

TMUX_

RTOAC_

OEPINS

TMUX_

TTOAC_

D412MODE

TMUX_

TTOAC_

D13MODE

TMUX_

TTOAC_

AVAIL

TMUX_

TTOAC_S1 TMUX_

TTOAC_F1 TMUX_

TTOAC_E2 TMUX_

TTOAC_E1 TMUX_

TTOAC_

D4TO12

TMUX_

TTOAC_

D1TO3

TMUX_

TTOAC_

OEPMON

0x4004B

page 117 TMUX_RPOAC_

CTL TMUX_RPOAC_SEL[1:0] TMUX_

RPOAC_

OEPINS

TMUX_TPOAC_SEL[1:0] TMUX_

TPOAC_N1 TMUX_

TPOAC_K3 TMUX_

TPOAC_F

TMUX_

TPOAC_F

TMUX_

TPOAC_C2 TMUX_

TPOAC_J1 TMUX_

TPOAC_

OEPMON

Transmit High-Speed Offset Control Parameters—R/W

0x4004D

page 118 TMUX_

TFRAMEOFFSET TMUX_TLBITCNT[2:0] TMUX_TLSTSCNT[1:0] TMUX_TLCOLCNT[6:0] TMUX_TLROWCNT[3:0]

B1/B2 Signal Degrade Set/Clear Control Registers—R/W

0x4004E

page 118 TMUX_SD_CTL1 TMUX_SDNSSET[18:3]

0x4004F

page 118 TMUX_SD_CTL2 TMUX_SDMSET[7:0] TMUX_SDLSET[3:0] TMUX_SDNSSET[2:0]

0x40050

page 118 TMUX_SD_CTL3 TMUX_SDBSET[15:0]

0x40051

page 118 TMUX_SD_CTL4 TMUX_SDNSCLEAR[18:3]

0x40052

page 118 TMUX_SD_CTL5 TMUX_SDMCLEAR[7:0] TMUX_SDLCLEAR[3:0] TMUX_SDNSCLEAR[2:0]

0x40053

page 119 TMUX_SD_CTL6 TMUX_SDBCLEAR[15:0]

B1/B2 Signal Fail Set/Clear Control Registers—R/W

0x40054

page 119 TMUX_SF_CTL1 TMUX_SFNSSET[18:3]

0x40055

page 119 TMUX_SF_CTL2 TMUX_SFMSET[7:0] TMUX_SFLSET[3:0] TMUX_SFNSSET[2:0]

0x40056

page 119 TMUX_SF_CTL3 TMUX_SFBSET[15:0]

0x40057

page 119 TMUX_SF_CTL4 TMUX_SFNSCLEAR[18:3]

0x40058

page 119 TMUX_SF_CTL5 TMUX_SFMCLEAR[7:0] TMUX_SFLCLEAR[3:0] TMUX_SFNSCLEAR[2:0]

0x40059

page 119 TMUX_SF_CTL6 TMUX_SFBCLEAR[15:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

131Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

B3 Signal Degrade Set/Clear Control Registers—R/W

0x4005A

page 119 TMUX_B3SD_CTL1 TMUX_B3SDNSSET[18:3]

0x4005B

page 119 TMUX_B3SD_CTL2 TMUX_B3SDMSET[7:0] TMUX_B3SDLSET[3:0] TMUX_B3SDNSSET[2:0]

0x4005C

page 119 TMUX_B3SD_CTL3 TMUX_B3SDBSET[15:0]

0x4005D

page 119 TMUX_B3SD_CTL4 TMUX_B3SDNSCLEAR[18:3]

0x4005E

page 119 TMUX_B3SD_CTL5 TMUX_B3SDMCLEAR[7:0] TMUX_B3SDLCLEAR[3:0] TMUX_B3SDNSCLEAR[2:0]

0x4005F

page 120 TMUX_B3SD_CTL6 TMUX_B3SDBCLEAR[15:0]

B3 Signal Fail Set/Clear Control Registers—R/W

0x40060

page 120 TMUX_B3SF_CTL1 TMUX_B3SFNSSET[18:3]

0x40061

page 120 TMUX_B3SF_CTL2 TMUX_B3SFMSET[7:0] TMUX_B3SFLSET[3:0] TMUX_B3SFNSSET[2:0]

0x40062

page 120 TMUX_B3SF_CTL3 TMUX_B3SFBSET[15:0]

0x40063

page 120 TMUX_B3SF_CTL4 TMUX_B3SFNSCLEAR[18:3]

0x40064

page 120 TMUX_B3SF_CTL5 TMUX_B3SFMCLEAR[7:0] TMUX_B3SFLCLEAR[3:0] TMUX_B3SFNSCLEAR[2:0]

0x40065

page 120 TMUX_B3SF_CTL6 TMUX_B3SFBCLEAR[15:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

132 Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive B1, B2, B3, M1, G1, and N1 Error Counts—RO

0x40066

page 120 TMUX_B1ECNT TMUX_B1ECNT[15:0]

0x40067

page 121 TMUX_B2ECNT_17_16 TMUX_B2ECNT[17:16]

0x40068

page 121 TMUX_B2ECNT_15_0 TMUX_B2ECNT[15:0]

0x40069

page 121 TMUX_B3ECNT1 TMUX_B3ECNT1[15:0]

0x4006A

page 121 TMUX_B3ECNT2 TMUX_B3ECNT2[15:0]

0x4006B

page 121 TMUX_B3ECNT3 TMUX_B3ECNT3[15:0]

0x4006Cp

age 122 TMUX_M1ECNT_17_16 TMUX_M1ECNT[17:16]

0x4006Dp

age 122 TMUX_M1ECNT_15_0 TMUX_M1ECNT[15:0]

0x4006E

page 122 TMUX_G1ECNT1 TMUX_G1ECNT1[15:0]

0x4006F

page 122 TMUX_G1ECNT2 TMUX_G1ECNT2[15:0]

0x40070

page 122 TMUX_G1ECNT3 TMUX_G1ECNT3[15:0]

Receive Pointer Increment and Decrement Counts—RO

0x40074

page 123 TMUX_RPTR_INCCNT1 TMUX_RPTR_INC1[10:0]

0x40075

page 123 TMUX_RPTR_INCCNT2 TMUX_RPTR_INC2[10:0]

0x40076

page 123 TMUX_RPTR_INCCNT3 TMUX_RPTR_INC3[10:0]

0x40077

page 123 TMUX_RPTR_DECCNT1 TMUX_RPTR_DEC1[10:0]

0x40078

page 123 TMUX_RPTR_DECCNT2 TMUX_RPTR_DEC2[10:0]

0x40079

page 123 TMUX_RPTR_DECCNT3 TMUX_RPTR_DEC3[10:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

133Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Expected J0 Receive Value—R/W

0x400A0

—

0x400A7

page 123

TMUX_RJ0EXPECTED[1—8] TMUX_EXPJ0DMON[2][7:0]

—

TMUX_EXPJ0DMON[16][7:0]

TMUX_EXPJ0DMON[1][7:0]

—

TMUX_EXPJ0DMON[15][7:0]

Captured J0 Receive Value—RO

0x400A8

—

0x400AF

page 123

TMUX_RJ0CAPTURED[1—8] TMUX_J0DMON[2][7:0]

—

TMUX_J0DMON[16][7:0]

TMUX_J0DMON[1][7:0]

—

TMUX_J0DMON[15][7:0]

J0 Byte Transmit Insert—R/W

0x400B0

—

0x400B7

page 123

TMUX_TJ0VALUE[1—8] TMUX_TJ0DINS[2][7:0]

—

TMUX_TJ0DINS[16][7:0]

TMUX_TJ0DINS[1][7:0]

—

TMUX_TJ0DINS[15][7:0]

Expected J1 Receive Value for STS #1—R/W

0x400E0

—

0x400FF

page 124

TMUX_RJ1EXPECTED_1[1—32] TMUX_EXPJ1DMON1[2][7:0]

—

TMUX_EXPJ1DMON1[64][7:0]

TMUX_EXPJ1DMON1[1][7:0]

—

TMUX_EXPJ1DMON1[63][7:0]

Expected J1 Receive Value for STS #2—R/W

0x40100

—

0x4011F

page 124

TMUX_RJ1EXPECTED_2[1—32] TMUX_EXPJ1DMON2[2][7:0]

—

TMUX_EXPJ1DMON2[64][7:0]

TMUX_EXPJ1DMON2[1][7:0]

—

TMUX_EXPJ1DMON2[63][7:0]

Expected J1 Receive Value for STS #3—R/W

0x40120

—

0x4013F

page 124

TMUX_RJ1EXPECTED_3[1—32] TMUX_EXPJ1DMON3[2][7:0]

—

TMUX_EXPJ1DMON3[64][7:0]

TMUX_EXPJ1DMON3[1][7:0]

—

TMUX_EXPJ1DMON3[63][7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

134 Agere Systems Inc.

8 TMUX Registers (continued)

Table 153. TMUX Register Map (continued)

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Captured J1 Receive Value for STS #1—RO

0x40140

—

0x4015F

page 124

TMUX_RJ1CAPTURED_1[1—32] TMUX_J1DMON1[2][7:0]

—

TMUX_J1DMON1[64][7:0]

TMUX_J1DMON1[1][7:0]

—

TMUX_J1DMON1[63][7:0]

Captured J1 Receive Value for STS #2—RO

0x40160

—

0x4017F

page 124

TMUX_RJ1CAPTURED_2[1—32] TMUX_J1DMON2[2][7:0]

—

TMUX_J1DMON2[64][7:0]

TMUX_J1DMON2[1][7:0]

—

TMUX_J1DMON2[63][7:0]

Captured J1 Receive Value for STS #3—RO

0x40180

—

0x4019F

page 124

TMUX_RJ1CAPTURED_3[1—32] TMUX_J1DMON3[2][7:0]

—

TMUX_J1DMON3[64][7:0]

TMUX_J1DMON3[1][7:0]

—

TMUX_J1DMON3[63][7:0]

J1 Byte Transmit Insert for STS #1—R/W

0x401A0

—

0x401BF

page 125

TMUX_TJ1VALUE_1[1—32] TMUX_TJ1DINS1[2][7:0]

—

TMUX_TJ1DINS1[64][7:0]

TMUX_TJ1DINS1[1][7:0]

—

TMUX_TJ1DINS1[63][7:0]

J1 Byte Transmit Insert for STS #2—R/W

0x401C0

—

0x401DF

page 125

TMUX_TJ1VALUE_2[1—32] TMUX_TJ1DINS2[2][7:0]

—

TMUX_TJ1DINS2[64][7:0]

TMUX_TJ1DINS2[1][7:0]

—

TMUX_TJ1DINS2[63][7:0]

J1 Byte Transmit Insert for STS #3—R/W

0x401E0

—

0x401FF

page 125

TMUX_TJ1VALUE_3[1—32] TMUX_TJ1DINS3[2][7:0]

—

TMUX_TJ1DINS3[64][7:0]

TMUX_TJ1DINS3[1][7:0]

—

TMUX_TJ1DINS3[63][7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

135Agere Systems Inc.

9 SPE Mapper Registers

Table of Co nten ts

Contents Page

9 SPE Mapper Registers .................................................................................................................................. 135

9.1 SPE Mapper Register Descriptions ...........................................................................................................136

9.2 SPE Mapper Register Map ........................................................................................................................153

Tables Page

Table 154. SPE_VERSION_R, SPE Version and Identification Register (RO).....................................................136

Table 155. SPE_ONESHOT, One Shot (R/W) ......................................................................................................136

Table 156. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW).....................................................136

Table 157. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) ..................................................................................138

Table 158. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO)........................140

Table 159. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Rx Control for Alarm and OH Functions (R/W) .................141

Table 160. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W) ..........................................142

Table 161. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)................................................143

Table 162. SP E_ RMON1—SPE_ RMON5, Rec ei ve Monito r Values (RO).......................... ................... ....... ...... ..143

Table 163. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Control for Mapping Functions (R/W) ..........................143

Table 164. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W)..........................146

Table 165. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W) .........................................148

Table 166. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W) ............................................................148

Table 167. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W)...................................................149

Table 168. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signal Degrade BER Algorithm Parameters (R/W)....149

Table 169. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W) ............150

Table 170. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO)..150

Table 171. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO)............151

Table 172. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO).....................................151

Table 173. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W) .....................................151

Table 174. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W).............................151

Table 175. SPE_SCRATCH_R, Scratch Pad (R/W)..............................................................................................151

Table 176. SPE_SPE_RX_THRES_CTL_DS3, Receive Elastic Store Threshold Control for DS3 (R/W)............152

Table 177. SPE_SPE_TX_THRES_CTL_DS3, Tr ansmit Elastic Store Threshold Control for DS3 (R/W) ...........152

Table 178. SPE_SPE_OV_UN_FIFO_THRES FIFO Overflow and Underflow Thresholds (R/W)........................152

Table 179. SPE Mapper Register Map..................................................................................................................153

136 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

9.1 SPE Mapper Register Descriptions

This section gives a brief description of each register bit and its functionality. The abbreviations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).

Table 154. SPE_VERSION_R, SPE Version and Identification Register (RO)

Table 155. SPE_ONESHOT, One Shot (R/W)

Note: In Table 156, the mask bits for these delta and event bits are in Table 157 on page 138, state bits are in

Table 158 on page 140, and monitor values are in Table 162 on page 143.

Address Bit Name Function Reset

Default

0x30000 15:11 RSVD Reserved. 0x00

10:8 SPE_VERSION[2:0] Block Version Number. Block version register will change

each time the device is changed. 0x0

7:0 SPEMPR_ID[7:0] Block ID Number. 0x03

Address Bit Name Function Reset

Default

0x30002 15:5 RSVD Reserved. 0x000

4 SPE_BIPOL_ERR Bipolar Violation Error. A single bipolar violation error for

DS3 output is transmitted each time this bit transitions from a

0 to 1.

3 SPE_SFCLEAR Signal Fail Clear. Allows the signal fail algorithm to be

forced into the normal state. 0

2SPE_SFSETSignal Fail Set. Allows the signal fail algorithm to be forced

into the failed state. 0

1 SPE_SDCLEAR Signal Degrade Clear. Allows the signal degrade algorithm

to be forced into the normal state. 0

0SPE_SDSETSignal Degrade Set. Allows the signal degrade algorithm to

be forced into the degraded state. 0

Table 156. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW)

Address Bit Name Function Res et

Default

0x30003 15 SPE_RX_ESOVUN_E Receive Elastic Store Overflow/Underflow Event Bit. Logic

1 indicates an elastic store overflow or underflow, based on

the SPE_RX_OVUN_FLOW_THRES threshold.

14 RSVD Reserved. —

13 SPE_TX_ESOVUN_E Transmit Elastic Store Overflow/Underflow Event Bit.

Logic 1 indicates an elastic store overflow or underflow , based

on the SPE_TX_OVUN_FLOW_THRES threshold.

12:5 RSVD Reserved. —

4 SPE_K3DMOND K3 Data Monitor Delta Bit. The mask bit is SPE_K3DMONM. 0

3 SPE_N1DMOND N1 Data Monitor Delta Bit. Th e mas k bit is SPE_ N1 DMONM . 0

2 SPE_C2DMOND C2 Data Monitor Delta Bit. Th e mas k bit is SPE_ C2 DMONM . 0

1 SPE_F2DMOND F2 Data Monitor Delta Bit. The mask bit is SPE_F2DMONM. 0

0 SPE_F3DMOND F3 Data Monitor Delta Bit. The mask bit is SPE_F3DMONM. 0

137Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

0x30004 15:1

1RSVD Reserved.0x00

10 SPE_PRDIDMOND Path RDI Delta. Delta bit indicates a change of state for the

path RDI state bit SPE_PRDIDMON. The delta bit is cleared

when read. The mask bit for this delta bit is

SPE_PRDIDMONM.

9 SPE_RNDFE Pointer Interpreter New Data Flag Event Bit. The mas k bit

is SPE_RNDFM. 0

8SPE_RDECEPointer Interpreter Decrement Event Bit. The mask bit is

SPE_RDECM. However, increment and decrement event indi-

cations should be ignored during LOP condition.

7 SPE_RINCE Pointer Interpreter Increment Event Bit. The mask bit is

SPE_RINCM. However, increment and decrement event indi-

cations should be ignored during LOP condition.

6 SPE_RAISD Delta Bit for the AIS Alarm Detect State Bit. The mask bit is

SPE_RAISM. 0

5SPE_RLOPDDelta Bit for the Los s of Pointer Alarm St ate Bit. The mask

bit is SPE _RLOP M. 0

4SPE_SFB3DSignal Fail BER Algorithm Delta. Indicates a change of

state for the signal fail BER algorithm state bit SFB3. This bit

clears when read. The mask bit is SPE_SFB3M.

3SPE_SDB3DSignal Degrade BER Algorithm Delta. Indicate s a change of

state for the signal degrade BER algorithm state bit SDB3.

This bit clears when read. The mask bit is SPE_SDB3M.

2 SPE_RUNEQD Delta Bit for the Unequipped Alarm State Bit. The mask bit

is SPE_RUNEQM. 0

1SPE_RPLMDDelta Bit for the Payload Label Mismatch Alarm State Bit.

The mask bit is SPE_RPLMM. 0

0 SPE_RTIMD Trace Indicator Mismatch Event Bit (J1 Byte). The mask bit

is SPE_RTIMM. 0

Table 156. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) (continued)

Address Bit Name Function Res et

Default

138 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

0x30005 15 RSVD Reserved. 0

14 SPE_RSY52LOSD Delta Bit for Loss of Sync 52 Signal from Telecom Bus. 0

13 SPE_RV1LOSD Delta Bit for Loss of V1 Sync Signal from Telecom Bus. 0

12 SPE_RSPELOSD Delta Bit for Loss of SPE Sync Signal from Telecom Bus. 0

11 SPE_RJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. 0

10 SPE_RDS3LOCD Delta Bit for Loss of DS3 External Clock from External

Pin. 0

9 SPE_RC52LOCD Delta Bit for Loss of 52 MHz Clock from Telecom Bus. 0

8 SPE_RLSLOCD Delta Bit for Loss of 19 MHz Clock from Telecom Bus. 0

7RSVDReserved. 0

6 SPE_TSY52LOSD Delta Bit for Loss of Sync 52 Signal from Telecom Bus. 0

5 SPE_TV1LOSD Delta Bit for Loss of V1 Sync Signal from Telecom Bus. 0

4 SPE_TSPELOSD Delta Bit for Loss of SPE Sync Signal from Telecom Bus. 0

3 SPE_TJ0J1V1LOSD Delta Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. 0

2 SPE_TDS3LOCD Delta Bit for Loss of DS3 External Clock from External

Pin. 0

1 SPE_TC52LOCD Delta Bit for Loss of 52 MHz Clock from Telecom Bus. 0

0 SPE_TLSLOCD Delta Bit for Loss of 19 MHz Clock from Telecom Bus. 0

Table 157. SPE_MASK1—SPE_MASK3, Mask Bits (R/W)

Address Bit Name Function Reset

Default

0x30006 15 SPE_RX_ESOVUN_IM Receive Elastic Store Overflow/Underflow Mask Bit. If

set to a logic 1, SPE_RX_ESO VUNL_E will not contribute

to the interrupt.

14 RSVD Reserved. —

13 SPE_TX_ESOVUN_IM Transmit Elastic Store Overflow/Underflow Mask Bit. If

set to a logic 1, SPE_RX_ESOVUN_E will not contribute to

the interrupt.

12:7 RSVD Reserved. —

6 SPE_RDATA_PM Received Data Parity Error Mask. Active-high. 1

5 SPE_TPOAC_PM Transmit POAC Parity Error Mask. Active-high. 1

4 SPE_K3DMONM K3 Data Monitor Mask Bit. Active-high. 1

3 SPE_N1DMONM N1 Data Monitor Mask Bit. Active-high. 1

2 SPE_C2DMONM C2 Data Monitor Mask Bit. Active-high. 1

1 SPE_F2DMONM F2 Data Monitor Mask Bit. Active-high. 1

0 SPE_F3DMONM F3 Data Monitor Mask Bit. Active-high. 1

Table 156. SPE_EVENT1—SPE_EVENT3, SPE Deltas/Events (COR/COW) (continued)

Address Bit Name Function Res et

Default

139Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

0x30007 15:11 RSVD Reserved. 00000

10 SPE_PRDIDMONM Path RDI Mask Bit. Active-high. 1

9 SPE_RNDFM Pointer Interpreter New Data Flag M ask Bit. Active-high. 1

8SPE_RDECMPointer Interpreter Decrement Mask Bit. Active-high. 1

7 SPE_RINCM Pointer Interpreter Increment Mask Bit. Active-high. 1

6 SPE_RAISM Mask Bit for the AIS Alarm Detect State Bit. Active-high. 1

5 SPE_RLOPM Mask Bit for the Loss of Pointer Alarm State Bit. Active-

high. 1

4 SPE_SFB3M Signal Fail Mask Bit. Active-high. 1

3SPE_SDB3MSignal Degrade Mask Bit. Active-high. 1

2 SPE_RUNEQM Mask Bit for the Unequipped Alarm State Bit. Active-

high. 1

1SPE_RPLMMMask Bit for the Payload Label Mismatch Alarm State

Bit. Active-high. 1

0SPE_RTIMMTrace Indicator Mismatch Mask Bits. Active-high. 1

0x30008 15 RSVD Reserved. 0

14 SPE_RSY52LOSM Mask Bit for Loss of Sync 52 Signal from Telecom Bus.

Active-high. 1

13 SPE_RV1LOSM Mask Bit for Loss of V1 Sync Signal from Telecom

Bus. Active-high. 1

12 SPE_RSPELOSM Mask Bit for Loss of SPE Sync Signal from Telecom

Bus. Active-high. 1

11 SPE_RJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. Active-high. 1

10 SPE_RDS3LOCM Mask Bit for Loss of DS3 External Clock from External

PIN. Active-high. 1

9 SPE_RC52LOCM Mask Bit for Loss of 52 MHz Clock from Telecom Bus.

Active-high. 1

8 SPE_RLSLOCM Mask Bit for Loss of 19 MHz Clock from Telecom Bus.

Active-high. 1

0x30008 7 RSVD Reserved. 0

6 SPE_TSY52LOSM Mask Bit for Loss of Sync 52 Signal from Telecom Bus.

Active-high. 1

5 SPE_TV1LOSM Mask Bit for Loss of V1 Sync Signal from Telecom

Bus. Active-high. 1

4 SPE_TSPELOSM Mask Bit for Loss of SPE Sync Signal from Telecom

Bus. Active-high. 1

3 SPE_TJ0J1V1LOSM Mask Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. Active-high. 1

2 SPE_TDS3LOCM Mask Bit for Loss of DS3 External Clock from External

PIN. Active-high. 1

1 SPE_TC52LOCM Mask Bit for Loss of 52 MHz Clock from Telecom Bus.

Active-high. 1

0 SPE_TLSLOCM Mask Bit for Loss of 19 MHz Clock from Telecom Bus.

Active-high. 1

Table 157. SPE_MASK1—SPE_MASK3, Mask Bits (R/W) (continued)

Address Bit Name Function Reset

Default

140 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 158. SPE_STATE1—SPE_STATE2, Receive/Transmit State and Value Parameters (RO)

Address Bit Name Function Reset

Default

0x30009 15:7 RSVD Reserved. 0x000

6SPE_RAISPath AIS Stat e Bit. 0

5SPE_RLOPPath Loss of Pointer State Bit. 0

4 SPE_SFB3 Signal Fail State Bit. 0

3SPE_SDB3Signal Degrade State Bit. 0

2 SPE_RUNEQ Path Unequipped State Bit. 0

1 SPE_RPLM Pa th Payload Label Mismatch State Bit. 0

0SPE_RTIMPath Trace Indicator Mismatch State Bit. 0

0x3000A 15 RSVD Reserved. 0

14 SPE_RSY52LOS State Bit for Loss of Sync 52 Signal from Telecom Bus. 0

13 SPE_RV1LOS State Bit for Loss of V1 Sync Signal from Telecom Bus. 0

12 SPE_RSPELOS State Bit for Loss of SPE S ync Signal from Telecom Bus. 0

11 SPE_RJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. 0

10 SPE_RDS3LOC State Bit for Los s of DS3 External Cloc k from External

PIN. 0

9 SPE_RC52LOC Stat e Bit for Loss of 52 MHz Clock from Telecom Bus. 0

8 SPE_RLSLOC State Bit for Loss of 19 MHz Clock from Telecom Bus. 0

7 RSVD Reserved. 0

6 SPE_TSY52LOS State Bit for Loss of Sync 52 Signal from Telecom Bus. 0

5 SPE_TV1LOS State Bit for Loss of V1 Sync Signal from Telecom Bus. 0

4 SPE_TSPELOS State Bit for Loss of S PE Sync Signal from Telecom Bus. 0

3 SPE_TJ0J1V1LOS State Bit for Loss of J0J1V1 Sync Signal from Telecom

Bus. 0

2 SPE_TDS3LOC State Bit for Loss of DS3 Ex ter nal Clock from External

Pin. 0

1SPE_TC52LOCState Bit for L oss of 52 MHz Clock from Telecom Bus. 0

0 SPE_TLSLOC State Bit for Lo ss of 19 MHz Clock from Telecom Bus. 0

141Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

)

Table 159. SPE_RAOH_CTL1—SPE_RAOH_CTL3, Rx Control for Alarm and OH Functions (R/W)

Address Bit Name Function Reset

Default

0x3000B 15:8 RSVD Reserved. 0x00

7 SPE_RD_OEPAR Received Data Odd/Even Parity Check. If 0, odd

parity check for received data; if 1, even parity check. 0

6:4 SPE_J1MONMODE[2:0] J1 Monitoring Mode. There are four monitoring modes

as defined in the document. 000

3 SPE_RPRDI_MODE Receive ERDI Mode. When 1, 3-bit enhanced ERDI

mode is supported; when 0, the 1-bit RDI mode is

supported.

2 SPE_G1BITBLKCNT G1 Error Count in Bit or Block. When 0, G1(7:4)

chec k logic will count bit errors; other wise, it counts

block erro rs.

1 SPE_B3BITBLKCNT B3 Error Count in Bit or Block. When 0, B3 check

logic will count bit errors; otherwise, it counts block

errors.

0 SPE_RPOAC_OEPINS Receive POAC Odd or Even Parity Insert. When 1,

the output POAC parity bit is even; otherwise, the parity

is odd.

0x3000C 15:12 RSVD Reserved. 0x0

11:10 SPE_CNTDLOPCNT[1:0] Continuous N-Times Detect for Loss of Pointer.

Two-bit programmable integration constant for the

pointer interpreter.

9RSVDReserved. 0

8 SPE_8ORMAJORITY TU-3 Pointer Interpreter Mode Control. When 1, the

pointer interpreter transitions into the INC and DEC

states based on 8 of the 10 I and D bits. Otherwise, the

pointer interpreter transitions into the INC and DEC

states based on majority rule.

7 SPE_PAISINS Path AIS Software Insertion. When 1, path AIS

insertion is enabled. 0

6 SPE_PAIS_AISINH Path AIS State Bit Inhibit Signal for Gene rating P ath

AIS. When 1, the inhibit is o n. 0

5 SPE_PAIS_LOPINH Loss of Pointer Inhibit Signal for Generating Path

AIS. When 1, the inhibit is o n. 0

4 SPE_PAIS_SFB3INH Signal Fail Inhibit Signal for Generating Path AIS.

When 1, the inhibit is on. 0

3 SPE_PAIS_SDB3INH Signal Degrade Inhibit Signal for Generating Path

AIS. When 1, the inhibit is o n. 0

2 SPE_PAIS_UNEQINH Path Unequipped Inhibit Signal for Generating Path

AIS. When 1, the inhibit is o n. 0

1 SPE_PAIS_PLMINH Path Label Mismatch Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

0 SPE_PAIS_TIMINH Path Trace Indicator Mismatch Inhibit Signal for

Generating Path AIS. When 1, the inhibit is on. 0

142 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 160. SPE_CNTD1—SPE_CNTD2, Continuous N-Times Detect Values (R/W)

0x3000D 15 RSVD Reserved. —

14 SPE_PH_DET_INV Phase Dete ction VCO Invert. When set to a 1, the

phase detection algorithm uses an invert VCO. 0

13:7 RSVD Reserved. —

6 SPE_AIS_LOSSY52INH Loss of Sync 52 State Bit Inhibit Signal for Generat-

ing Path AIS. When 1, the inhibit is on. 0

5 SPE_AIS_LOSV1INH Loss of V1 Sync Inhibit Signal for Generating Path

AIS. When 1, the inhibit is on. 0

4 SPE_AIS_LOSSPEINH Loss of SPE S ync Inhibit Sig nal for Ge nera ting Pa th

AIS. When 1, the inhibit is on. 0

3 SPE_AIS_LOSJ0J1V1INH Loss of J0J1V1 Sync Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

2 SPE_AIS_LOCDS3INH Loss of Ext DS3 Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

1 SPE_AIS_LOC52INH Loss of 52 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

0 SPE_AIS_LOCINH Loss of 19 MHz Clock Inhibit Signal for Generating

Path AIS. When 1, the inhibit is on. 0

Address Bit Name Function Reset

Default

0x3000F 15:12 SPE_CNTDC2[3:0] Continuous N-Times Detect for C2 Byte. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

11:8 SPE_CNTDF3[3:0] Continuous N-Times Detect for F3 Byte. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

7:4 SPE_CNTDF2[3:0] Continuous N-Times Detect for F2 Byte. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

3:0 SPE_CNTDJ1[3:0] Continuou s N-Times Detect for J1 Byte s. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

0x30010 15:12 SPE_CNTDN1[3:0] Continuous N-Times Detect for N1 Byte. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

11:8 SPE_CNTDPRDI[3:0] Continuous N-Times Detect for G1 Byte. The valid range

for this register is 0x3—0xF. Invalid values will be mapped to

a va lue of 0x3.

0x3

7:4 SPE_CNTDK3[3:0] Continuou s N-Times Detect for K3[6:4] Byte. The valid

range for this register is 0x3—0xF. Invalid values will be

mapped to a value of 0x3.

0x3

3:0 RSVD Reserved. 0x0

Table 159. SPE_RAOH_CTL1—SPE_RAOH_ CTL3, Rx Control fo r Alarm and O H Func tions (R/W) (continued)

Address Bit Name Function Reset

Default

143Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

Table 161. SPE_ROHC2, Receive Overhead Expected Value for C2 Byte (R/W)

Tab le 162. SP E_ RMO N1— SP E_ RMO N5, Rece ive Mo nit or Val ues (RO )

Address Bit Name Function Reset

Default

0x30011 15:8 RSVD Reserved. 0x00

7:0 SPE_C2DEXP[7:0] Programmable Expected Value for C2 Byte. The

programmed value is checked against the actual received

value to determine payload label mismatch error.

0x00

Address Bit Name Function Reset

Default

0x30012 15:3 RSVD Reserved. 0x000

2:0 SPE_PRDIDMON[2:0] Received Byte G1[3:1] Monitor Value. 0x0

0x30013 15:8 SPE_N1DMON[7:0] Received Byte N1[7:0] Monitor Value. 0x00

7:0 SPE_K3DMON[7:0] Received Byte K3[7:0] Monitor Value. 0x00

0x30014 15:8 SPE_F2DMON1[7:0] Received Byte F2[7:0] Previous Monitor Value. 0x00

7:0 SPE_F2DMON0[7:0] Received Byte F2[7:0] Current Monitor Value. 0x00

0x30015 15:8 SPE_F3DMON1[7:0] Received Byte F3[7:0] Previous Monitor Value. 0x00

7:0 SPE_F3DMON0[7:0] Received Byte F3[7:0] Current Monitor Value. 0x00

0x30016 15:8 RSVD Reserved. 0x00

7:0 SPE_C2DMON[7:0] Received Byte C2[7:0] Monitor Value. 0x00

Table 163. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Contr ol for Mapping Functions (R/W)

Address Bit Name Function Reset

Default

0x30018 15 SPE_T_STS1_MODE Transmit STS-1 Mode. When 1, STS-1 mode is

selected for transmit data; when 0, STS-3/STM-1. 0

14 SPE_T_NSMI_MODE Transmit Serial STS-1 SPE Mode. When 1, serial

data is accepted through an external serial interface

and mapped to STS-1 SPE.

13:12 SPE_TDS3SRCTYP[1:0] Transmit DS3 Source Type. Two-bit value selects

one of three DS3 input sources.

00 or 01 = DS3 data from M13 block.

10 = DS3 data from loopback (Rx to Tx).

11 = DS3 data from external clear channel.

11 SPE_T_VT_DS3 Transmit VT or DS3 Input. When 1, VT input data is

selected; when 0, DS3 input data is selected. 0

10 SPE_T_AU3_TUG3 Transmit AU-3/STS-1 or TUG-3 Mapping. When 1,

AU-3/STS-1 mapping is selected; when 0, TUG-3 map-

ping is selected.

144 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

0x30018 9:8 SPE_TSTS3TMSLOT[1:0] Transmit STS-3 Time-Slot Value. Two-bit value

selects one of three STS-1 time slots within an STS-3

in the transmit direction.

00 = no output.

01 = STS-1/TUG-3 data for slot 1 in STS-3/STM-1.

10 = STS-1/TUG-3 data for slot 2 in STS-3/STM-1.

11 = STS-1/TUG-3 data for slot 3 in STS-3/STM-1.

7 SPE_R_STS1_MODE Receive STS-1 Mode. When 1, STS-1 mode is

selected for receive data. When 0, STS-3/STM-1. 0

6 SPE_R_NSMI_MODE Receive Serial STS-1 SPE Mode. When 1, serial data

demapped from STS-1 SPE is sent out to an external

serial interface.

5:4 SPE_RDS3OUTTYP[1:0] Receive DS3 Output Type. Two-bit value selec ts one

of three DS3 output devices.

00 or 01 = DS3 data to M13 block.

10 = DS3 data to loopback (RX to TX).

11 = DS3 data to external clear channel.

3SPE_R_VT_DS3Receive VT or DS3 Output. When 1, VT data is out-

put; when 0, DS3 data is output. 0

2 SPE_R_AU3_TUG3 Receive AU-3/STS-1 or TUG-3 Demapping. When 1,

AU-3/STS-1 demapping is selected; when 0, TUG-3

demapping is selected.

1:0 SPE_RSTS3TMSLOT[1:0] Rece ive ST S-3 T ime -S lot. Selects one of three STS-1

time slots within an STS-3/STM-1 frame in the receive

direction.

00 = no selection.

01 = STS-1/TUG-3 data from slot 1 in STS-3/STM-1.

10 = STS-1/TUG-3 data from slot 2 in STS-3/STM-1.

11 = STS-1/TUG-3 data from slot 3 in STS-3/STM-1.

0x30019 15:13 SPE_T_NSMI_BIT[2:0] Transmit Seri al Sync P os ition W ith in a Byte Bound -

ary. Selects one of eight positions for the bit sync of the

serial transmit data stream (previously known as the

NSMI inter face data) .

0x0

12:10 SPE_R_NSMI_BIT[2:0] Receive Serial Sync Position Within a Byte Bound-

ary. Selects one of eight positions for the bit sync of the

serial receive data stream (previously known as the

NSMI inter face data) .

0x0

9:8 RSVD Reserved. 0x0

7 SPE_JITTER_FIFO Jitter FIFO Mode. When set to a 1, the SPE mapper

uses an extra FIFO to reduce jitter on the clear

channel.

6RSVDReserved. —

5 SPE_TDS3CLK_EDGE External DS3 Clock Edge Select for DS3 Input Data

Retiming.

0 = negative edge is selected.

1 = positive edge is selected.

0x0

Table 163. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Contr ol for Mapping Functions (R/W) (continued)

Address Bit Name Function Reset

Default

145Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

Table 163. SPE_MAP_CTL1—SPE_MAP_CTL3, Tx/Rx Contr ol for Mapping Functions (R/W) (continued)

Address Bit Name Function Reset

Default

0x30019 4 SPE_PHDETUP_INV Phase Detector Up Signal Invert. When 1, the phase

detector up signal required for an external PLL in DS3

mode is inverted from its current phase.

0x0

3 SPE_PHDETDN_INV Phase Detector Down Signal Invert. When 1, the

phase detector down signal required for an external

PLL in DS3 mode is inverted from its current phase.

0x0

2 SPE_TDS3BPV_IN Transmit DS3 BPV/Data In. When 1,

DS3NEGDATAIN (K22) input pin is used as external

B3ZS bipolar violation indication instead of negative

input pulse.

0x00

1 SPE_TDS3_BIPOLAR Transmit DS3 Bipolar/Unipolar. Whe n 1, the DS3

input is bipolar; when 0, the DS3 input is unipolar. 0x00

0 SPE_RDS3_BIPOLAR Receive DS3 Bipolar/Unipolar. When 1, the DS3 out-

put is bipolar; when 0, the DS3 output is unipolar. 0x00

0x3001A 15 RSVD Reserved. —

14:8 SPE_T_NSMI_COL[6:0] Transmit Serial Sync Position. Selects one of

90 positions aligned with 90 SONET columns within

SONET row 9 for the bit sync of the serial transmit data

stream (prev iou sl y kn own as the NSM I inter fac e data ).

0x0

7RSVDReserved. —

6:0 SPE_R_NSMI_COL[6:0] Receive Serial Sync Position. Selects one of 90 posi-

tions aligned with 90 SONET columns within SONET

row 9 for the bit sync of the serial transmit data stream

(previously known as the NSMI interface data).

0x0

146 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 164. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W)

Address Bit Name Function Reset

Default

0x3001B 15:10 RSVD Reserved. 0x00

9SPE_TD_OEPARTransmit Data Odd/Even Parity Generate. When 0, odd

parity is generated for transmit data; when 1, even parity is

generated.

8 SPE_ TREIRDISEL REI and RDI Input Select. Control bit, when 1, inserts

REI/RDI value from the protected channel REI/RDI lines;

otherwise, the value is inserted from the direct feedback

(receive to transmit) lines.

7 SPE_TAISPINS Force Path AIS in the Output. Active-high. 0

6SPE_TN1INSTransmit N1 Insert Control. Control bit, when 1, inserts

the value in SPE_TN1DINS[7:0] (Table 167 on page 149)

into the outgoing N1 byte in the STS-1 frame; otherwise,

the insert value depends on SPE_TPOAC_N1 (Table 164

on page 146) control bit.

5SPE_TK3INSTransmit K3 Insert Control. Control bit, when 1, inserts

the value in SPE_TK3DINS[7:0] (Table 167 on page 149)

into the outgoing K3 bytes; otherwise, the insert value

depends on SP E_TP O AC_ K3 (Table 164 on page 146)

control bit.

4SPE_TH4INSTransmit H4 Insert Control. Control bit, when 1, inserts

the overhead default value SMPR_OH_DEFLT (Table 77

on page 70) into the outgoing H4 bytes; otherwise, the

insert value depends on SPE_TPOAC_H4 (Table 164 on

page 146) control bit.

3 SPE_TF3INS Tran smit F3 Inser t Control. Control bit, when 1, inserts

the value in SPE_TF3DINS[7:0] (Table 167 on page 149)

into the outgoing F3 byte in the STS-1 frame; otherwise,

the insert value depends on SPE_TPOAC_F3 (Table 164

on page 146) control bit.

2 SPE_TF2INS Tran smit F2 Inser t Control. Control bit, when 1, inserts

the value in SPE_TF2DINS[7:0] (Table 167 on page 149)

into the outgoing F2 byte in the STS-1 frame; otherwise,

the insert value depends on SPE_TPOAC_F2 (Table 164

on page 146) control bit.

1 SP E_ TC 2INS Transmit C2 Insert Control. Control bit, when 1, inserts

the value in SPE_TC2DINS[7:0] (Table 167 on page 149)

into the outgoing C2 byte in the STS-1 frame; otherwise,

the insert value depends on SPE_TPOAC_C2 (Table 164

on page 146) control bit.

0SPE_TJ1INSTransmit J1 Insert Control. Control bit, when 1, inserts

the value in SPE_TJ1DINS[1—64][7:0] (Table 173 on

page 151) into the outgoing J1 bytes; otherwise, the insert

value depends on SPE_TPOAC_J1 (Table 164 on

page 146) control bit.

147Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

Table 164. SPE_TAOH_CTL1—SPE_TAOH_CTL3, Tx Control for Alarm/OH Functions (R/W) (continued)

Address Bit Name Function Reset

Default

0x3001C 15:8 RSVD Reserved. 0x00

7 SPE_TPOAC_OEPMON Transmit POAC Odd or Even Parity Monitor. When 1,

even parity is checked for transmit POAC channels; other-

wise, odd parit y is chec ke d.

6 SPE_TPOAC_N1 Transmit POAC N1 Byte Control. Control bit, when 0,

inserts the default value into the N1 byte in the transmit

frame. When 1, the TPOAC value is inserted in the N1 byte.

5 SPE_TPOAC_K3 Transmit POAC K3 Byte Control. Control bit, when 0,

inserts the default value into the K3 byte in the transmit

frame. When 1, the TPOAC value is inserted in the K3 byte.

4 SPE_TPOAC_H4 Transmit POAC H4 Byte Control. Control bit, when 0,

inserts the default value into the H4 byte in the transmit

frame. When 1, the TPOAC value is inserted in the H4 byte.

3 SPE_TPOAC_F3 Transmit POAC F3 Byte Control. Control bit, when 0,

inserts the default value into the F3 byte in the transmit

frame. When 1, the TPOAC value is inserted in the F3 byte.

2 SPE_TPOAC_F2 Transmit POAC F2 Byte Control. Control bit, when 0,

inserts the default value into the F2 byte in the transmit

frame. When 1, the TPOAC value is inserted in the F2 byte.

1 SPE_TPOAC_C2 Transmit POAC C2 Byte Control. Control bit, when 0,

inserts the default value into the C2 byte in the transmit

frame. When 1, the TPOAC value is inserted in the C2 byte.

0 SPE_TPOAC_J1 Transmit POAC J1 Byte Control. Control bit, when 0,

inserts the default value into the J1 byte in the transmit

frame. When 1, the TPOAC value is inserted in the J1 byte.

0x3001D 15:8 SPE_NPI_BYTE2[7:0] Transmit NPI Byte 2. Programmable value for NPI byte 2

to be inserted into the NPI byte location. 0

7:0 SPE_NPI_BYTE1[7:0] Transmit NPI Byte 1. Programmable value for NPI byte 1

to be inserted into the NPI byte location. 0

148 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 165. SPE_TRDIREI_CTL, Transmit Path RDI and REI Control Register (R/W)

Table 166. SPE_TERRINS_CTL, Transmit Error Insertion Control (R/W)

Address Bit Name Function Reset

Default

0x3001E 15:8 RSVD Reserved. 0x00

7 SPE_TPRDIINS Transmit RDI Software Insert. When 1, the value in

SPE_TG1DINS[3:1] is inserted into G1[3:1] in the trans-

mit frame; otherwise, hardware insert is enabled for RDI-

P inserti on.

6 SPE_TTIM_PRDIINH Transmit Trace Indicator Mismatch RDI Inhibit. Con-

trol bit, when 1, the TIM failure will not contribute to the

automatic insertion of RDI-P; otherwise, the associated

alarm contributes to the generation of RDI-P.

5 SPE_TPLM_PRDIINH Transmit Path Label Mismatch RDI Inhibit. Control bit,

when 1, the PLM failure will not contribute to the auto-

matic insertion of RDI-P; otherwise, the associated alarm

contributes to the generation of RDI-P.

4 SPE_TUNEQ_PRDIINH Transmit Path Unequipped RDI Inhibit. Control bit,

when 1, the unequipped failure will not contribute to the

automatic insertion of RDI-P; otherwise, the associated

alarm contributes to the generation of RDI-P.

3 SPE_TLOP_PRDIINH Transmit Loss of Pointer RDI Inhibit. Control bit, when

1, the loss of pointer failure will not contribute to the auto-

matic insertion of RDI-P; otherwise, the associated alarm

contributes to the generation of RDI-P.

2 SPE_TPAIS_PRDIINH Transmit Path AIS RDI Inhibit. Control bit, when 1, the

path AIS failure will not contribute to the automatic inser-

tion of RDI-P; otherwise, the associated alarm contrib-

utes to the generation of RDI-P.

1 SPE_TPRDI_MODE Transmit PRDI Mode. When 1, 3-bit enhanced ERDI

mode is supported; when 0, the 1-bit RDI mode is

supported.

0 SPE_ TREIP_INH T ransmit REI-P Inhibit. When 1, inhibits automatic inser-

tion of REI-P. 0

Address Bit Name Function Reset

Default

0x3001F 15:3 RSVD Reserved. 0x000

2 SPE_BERR_INS Bit Error Insert Control Bit. When 1, bit errors will be

inserted on selected signals (whose error insert bits are set)

each time a pulse occurs on the BER_INS line.

1 SPE_TB3ERRINS Transmit B3 Error Insertion. When 1, the B3 output will be

inverted. 0

0 SPE_TREIERRINS Transmit G1 Error Insert. When 1, an error will be inserted

continuously into the outgoing G1[7:4] bits, until reset to 0. 0

149Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

Table 167. SPE_TOHINS1—SPE_TOHINS4, Transmit OH Insert Value (R/W)

Table 168. SPE_SIGDEG_CTL1—SPE_SIGDEG_CTL6, Signa l Degrade BER Algorithm Parameters (R/W)

Address Bit Name Function Reset

Default

0x30020 15:8 SPE_TF3DINS[7:0] Transmit F3 Byte Value. This value is inserted into the

transmit F3 byte. 0x00

7:0 SPE_TF2DINS[7:0] Transmit F2 Byte Value. This value is inserted into the

transmit F2 byte. 0x00

0x30021 15:8 SPE_TC2DINS[7:0] Transmit C2 Byte Value. This value is inserted into the

transmit C2 byte. 0x00

7:0 SPE_TK3DINS[7:0] Transmit K3 Byte Value. This value is inserted into the

transmit K3 byte. 0x00

0x30022 15:8 SPE_TG1DINS[7:0] Transmit G1 Byte Value. This value is inserted into the

transmit G1 byte. 0x00

7:0 SPE_TN1DINS[7:0] Transmit N1 Byte Value. This value is inserted into the

transmit N1 byte. 0x00

0x30023 15:8 RSVD Reserved. 0x00

7:0 SPE_TH4DINS[7:0] Transmit H4 Byte Value. This value is inserted into the

transmit H4 byte. 0x00

Address Bit Name Function Reset

Default

0x30024

0x30025 15:0

2:0 SPE_SDNSSET[18:3]

SPE_SDNSSET[2:0] Signal Degrade Ns Set. Number of frames in a

monitoring block for SD. 0x0000

0x30025 15 RSVD Reserved. 0

14:7 SPE_SDMSET[7:0] Signal Degrade M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad blocks is above this threshold, then signal

degrade (SD) is set.

0x00

6:3 SPE_SDLSET[3:0] Signal Degr ade L S et. Error threshold for determining a

bad monitoring block. 0x0

0x30026 15:0 SPE_SDBSET[15:0] Signal Degrade B Set. Number of monitoring blocks. 0x0000

0x30027

0x30028 15:0

2:0 SPE_SDNSCLEAR[18:3]

SPE_SDNSCLEAR[2:0] Signal Degrade Ns Clear. Number of frames in a

monitoring block for SD. 0x0000

0x30028 15 RSVD Reserved. 0

14:7 SPE_SDMCLEAR[7:0] Signal Degrade M Clear. Threshold of the number of

bad monitoring blocks in an observation interval. If the

number of bad blocks is below this threshold, then SD is

cleared.

0x00

6:3 SPE_SDLCLEAR[3:0] Signal Degrade L Clear. E rror threshold for determining

a bad monitoring block. 0x0

0x30029 15:0 SPE_SDBCLEAR[15:0] Signal Degrade B Clear. Number of monitoring blocks. 0x0000

150 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 169. SPE_SIGFAIL_CTL1—SPE_SIGFAIL_CTL6, Signal Fail BER Algorithm Parameters (R/W)

Table 170. SPE_ERRCNT1—SPE_ERRCNT6, B3, G1, Bipolar Violation, and Excess Zero Error Count (RO)

Address Bit Name Function Reset

Default

0x3002A

0x3002B 15:0

2:0 SPE_SFNSSET[18:3]

SPE_SFNSSET[2:0] Signal Fail Ns Set. Number of frames in a monitoring

block for SF. 0x0000

0x3002B 15 RSVD Reserved. 0

14:7 SPE_SFMSET[7:0] Signal Fail M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad blocks is above this threshold, then signal

fail (SF) is set.

0x00

6:3 SPE_SFLSET[3:0] Signal Fail L Set. Error threshold for determining a bad

monitoring block. 0x0

0x3002C 15:0 SPE_SFBSET[15:0] Signal Fail B Set. Number of monitoring blocks. 0x0000

0x3002D

0x3002E 15:0

2:0 SPE_SFNSCLEAR[18:3]

SPE_SFNSCLEAR[2:0] Signal Fail Ns Clear. Number of frames in a monitoring

block for SF. 0x0000

0x3002E 15 RSVD Reserved. 0

14:7 SPE_SFMCLEAR[7:0] Signal Fail M Clear. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad blocks is below this threshold, then SF is

cleared.

0x00

6:3 SPE_SFLCLEAR[3:0] Signal Fail L Clear. Error threshold for determining a

bad monitoring block. 0x0

0x3002F 15:0 SPE_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks. 0x0000

Address Bit Name Function Reset

Default

0x30030 15:0 SPE_B3ECNT[15:0] B3 Error Count. The value of internal running counter

is transferred into this holding register coincident with

the end of a performance monitor interval.

0x0000

0x30031 15:0 SPE_G1ECNT[15:0] G1 Error Count. The value of internal running counter

is transferred into this holding register coincident with

the end of a performance monitor interval.

0x0000

0x30033

0x30034

15:8

7:0

15:0

RSVD

SPE_BIPOL_CNT[23:16]

SPE_BIPOL_CNT[15:0]

Reserved.

Bipolar Coding Violation Occurrence Count. The

value of internal running counter is transferred into this

holding register coincident with the end of a

performance monitor interval.

0x000000

0x30035

0x30036

15:8

7:0

15:0

RSVD

SPE_EXZ_CNT[23:16]]

SPE_EXZ_CNT[15:0]

Reserved.

Excess Zero Occurrence Count. The value of

internal running counter is transferred into this holding

monitor interval.

0x000000

151Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

9 SPE Mapper Registers (continued)

Table 171. SPE_PTRCNT1—SPE_PTRCNT3, Receive Pointer Increment and Decrement Count (RO)

Table 172. SPE_RJ1MON_R1—SPE_RJ1MON_R32, Receive J1 Monitor Values (RO)

Table 173. SPE_TJ1DINS_R1—SPE_TJ1DINS_R32, Transmit J1 Insert Values (R/W)

Table 174. SPE_RJ1DEXP_R1—SPE_RJ1DEXP_R32, Receive J1 Expected Values (R/W)

Table 175. SPE_SCRATCH_R, Scratch Pad (R/W)

Address Bit Name Function Rese t

Default

0x30037 15:10 RSVD Reserved. 0x00

9:0 SPE_STORED_PTR[9:0] Store d TU-3 Pointer Location. 0x000

0x30038 15:11 RSVD Reserved. 0x00

10:0 SPE_RPTR_INC[10:0] Pointer Increment Count from Pointer

Interpreter Block. The value of internal running

counter is transferred into this holding register

coincident with the end of a performance monitor

interval.

0x000

0x30039 15:11 RSVD Reserved. 0x00

10:0 SPE_RPTR_DEC[10:0] Pointer Decrement Count from Pointer

Interpreter Block. The value of internal running

counter is transferred into this holding register

coincident with the end of a performance monitor

interval.

0x000

Address Bit Name Function Reset

Default

0x30042

—

0x30061

15:0 SPE_RJ1DMON[1—64][7:0] Receive J1 Monitor V alue. These registers capture

a 64-byte sequence from the J1 byte of each frame. 0x00

Address Bit Name Function Reset

Default

0x30062

—

0x30081

15:0 SPE_TJ1DINS[1—64][7:0] Transmit J1 Insert Value. These registers allow a

64-byte sequence to be inserted into the J1 byte of

each frame.

0x00

Address Bit Name Function Reset

Default

0x30082

—

0x300A1

15:0 SPE_RJ1DEXP[1—64][7:0] Receive J1 Expected V alue. These registers hold a

programmable 64-byte expected sequence for the J1

byte of each frame.

0x00

Address Bit Name Function Reset

Default

0x300A2 15:10

9:0 RSVD

SPE_SCRATCH[9:0] Reserved.

Scratch Register. Allows the control system to ver-

ify read and write operations to the device without

affecting device operation.

0x0000

152 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

9 SPE Mapper Registers (continued)

Table 176. SPE_SPE_RX_THRES_CTL_DS3, Receive Elastic Store Threshold Control for DS3 (R/W)

Address Bit Name Function Reset

Default

0x300A3 15 RSVD Reserved. 0

14:8 SPE_RX_HIGH_THRES_DS3[6:0] Receive Elastic Store High Threshold for

DS3. Programmable threshold controlling posi-

tive justifications.

0x4D

7RSVDReserved. 0

6:0 SPE_RX_LOW_THRES_DS3[6:0] Receive Elastic Store Low Threshold for

DS3. Programmable threshold controlling nega-

tive justifications.

0x4A

Table 177. SPE_SPE_TX_THRES_CTL_DS3, Transmit Elastic Store Threshold Control for DS3 (R/W)

Address Bit Name Function Reset

Default

0x300A4 15 RSVD Reserved. 0

14:8 SPE_TX_HIGH_THRES_DS3[6:0] Transmit Elastic Store High Threshold for

DS3. Programmable threshold controlling posi-

tive justifications.

0x38

7RSVDReserved. 0

6:0 SPE_TX_LOW_THRES_DS3[6:0] Transmit Elastic Store Low Threshold for

DS3. Programmable threshold controlling nega-

tive justifications.

0X36

Table 178. SPE_SPE_OV_UN_FIFO_THRES FIFO Overflow and Underflow Thresholds (R/W)

Address Bit Name Function Reset

Default

0x300B0 15:7 RSVD Reserved.0

6:0 SPE_RX_OVUN_FLOW_THRES[6:0] Receive FIFO Overflow/Underflow

Threshold. Programmable threshold con-

trolling overflow/underflow event. If the write

minus the read address falls below this

value, then the overflow/underflow event will

be a 1. If the write minus the read address is

above this half of this value, then the over-

flow/unde rf low event wil l be a 1.

0x1E

0x300B1 15:7 RSVD Reserved.0

6:0 SPE_TX_OVUN_FLOW_THRES[6:0] Transmit FIFO Overflow/Underflow

Threshold. Programmable threshold con-

trolling overflow/underflow event. If the write

minus the read address falls below this

value, then the overflow/underflow event will

be a ‘1’. If the write minus the read address

is above this half of this value, then the over-

flow/underflow event will be a 1.

0x1E

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

153Agere Systems Inc.

9 SPE Mapper Registers (continued)

9.2 SPE Mapper Register Map

Note: In Table 179, the reset default of all reserved bits is 0. Shading denotes reserved bits.

Table 179. SPE Mapper Register Map

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

SPE Version and Identification Registers—RO

0x30000

Page 136 SPE_

VERSION_R SPE_VERSION[2:0] SPEMPR_ID[7:0]

0x30001

Page 136 RSVD

One Shot (0 to 1 transition) Control Bit Parameters—R/W

0x30002

Page 136 SPE_

ONESHOT SPE_

BIPOL_ERR SPE_

SFCLEAR SPE_

SFSET SPE_

SDCLEAR SPE_SDSET

Delta and Event Parameters—COR/COW

0x30003

Page 136 SPE_EVENT1 SPE_RX_

ESOVUN_

SPE_TX_

ESOVUBN_

SPE_

K3DMOND SPE_

N1DMOND SPE_

C2DMOND SPE_

F2DMOND SPE_

F3DMOND

0x30004

Page 137 SPE_EVENT2 SPE_PRDI

DMOND SPE_RNDFE SPE_RDECE SPE_RINCE SPE_RAISD SPE_

RLOPD SPE_SFB3D SPE_SDB3D SPE_

RUNEQD SPE_

RPLMD SPE_RTIMD

0x30005

Page 137 SPE_EVENT3 SPE_RSY5

2LOSD SPE_

RV1LOSD SPE_

RSPELOSD SPE_RJ0J1

V1LOSD SPE_RDS3

LOCD SPE_

RC52LOCD SPE_

RLSLOCD SPE_

TSY52LOSD SPE_

TV1LOSD SPE_

TSPELOSD SPE_TJ0J1V

1LOSD SPE_

TDS3LOCD SPE_

TC52LOCD SPE_

TLSLOCD

Interrupt Mask Parameters for INT Pins—R/W

0x30006

Page 138 SPE_MASK1 SPE_RX_

ESOVUN_

SPE_TX_

ESOVUN_

SPE_

RDATA_PM SPE_

TPOAC_PM SPE_

K3DMONM SPE_

N1DMONM SPE_

C2DMONM SPE_

F2DMONM SPE_

F3DMONM

0x30007

Page 138 SPE_MASK2 SPE_PRDI

DMONM SPE_RNDFM SPE_

RDECM SPE_RINCM SPE_RAISM SPE_

RLOPM SPE_

SFB3M SPE_

SDB3M SPE_

RUNEQM SPE_

RPLMM SPE_

RTIMM

0x30008

Page 138 SPE_MASK3 SPE_RSY5

2LOSM SPE_

RV1LOSM SPE_

RSPELOSM SPE_RJ0J1

V1LOSM SPE_RDS3

LOCM SPE_

RC52LOCM SPE_

RLSLOCM SPE_

TSY52LOSM SPE_

TV1LOSM SPE_

TSPELOSM SPE_TJ0J1V

1LOSM SPE_

TDS3LOCM SPE_

TC52LOCM SPE_

TLSLOCM

State and Value Parameter s—RO

0x30009

Page 140 SPE_STATE1 SPE_RAIS SPE_RLOP SPE_SFB3 SPE_SDB3 SPE_

RUNEQ SPE_RPLM SPE_RTIM

0x3000A

Page 140 SPE_STATE2 SPE_

RSY52LOS SPE_

RV1LOS SPE_

RSPELOS SPE_RJ0J1

V1LOS SPE_

RDS3LOC SPE_

RC52LOC SPE_

RLSLOC SPE_

TSY52LOS SPE_

TV1LOS SPE_

TSPELOS SPE_

TJ0J1V1LOS SPE_

TDS3LOC SPE_

TC52LOC SPE_

TLSLOC

Receive Control Parameters for Alarm and Overhead Functions—R/W

0x3000B

Page 141 SPE_RAOH_

CTL1 SPE_RD_

OEPAR SPE_J1MONMODE[2:0] SPE_RPRDI_

MODE SPE_G1BTB

LKCNT SPE_B3BT

BLKCNT SPE_RPOAC_

OEPINS

0x3000C

Page 141 SPE_RAOH_

CTL2 SPE_CNTDLOPCNT[1:0] SPE_8ORMA

JORITY SPE_

PAISINS SPE_PAIS_

AISINH SPE_PAIS_

LOPINH SPE_PAIS_

SFB3INH SPE_PAIS_

SDB3INH SPE_PAIS_

UNEQINH SPE_PAIS_

PLMINH SPE_PAIS_

TIMINH

0x3000D

Page 142 SPE_RAOH_

CTL3 SPE_PH_

DET_INV SPE_AIS_

LOSSY52INH SPE_AIS_

LOSV1INH SPE_AIS_

LOSSPEINH SPE_AIS_LO

SJ0J1V1INH SPE_AIS_

LOCDS3INH SPE_AIS_

LOC52INH SPE_AIS_

LOCINH

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

154 Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 179. SPE Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 B it 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Continuous N-Times Detect Values—R/W

0x3000E RSVD

0x3000F

Page 142 SPE_CNTD1 SPE_CNTDC2[3:0] SPE_CNTDF3[3:0] SPE_CNTDF2[3:0] SPE_CNTDJ1[3:0]

0x30010

Page 142 SPE_CNTD2 SPE_CNTDN1[3:0] SPE_CNTDPRDI[3:0] SPE_CNTDK3[3:0]

Receive Overhead Expected Value for C2 Byte—R/W

0x30011

Page 143 SPE_ROHC2 SPE_C2DEXP[7:0]

Receive Monitor Values—RO

0x30012

Page 143 SPE_RMON1 SPE_PRDIDMON[2:0]

0x30013

Page 143 SPE_RMON2 SPE_N1DMON[7:0] SPE_K3DMON[7:0]

0x30014

Page 143 SPE_RMON3 SPE_F2DMON1[7:0] SPE_F2DMON0[7:0]

0x30015

Page 143 SPE_RMON4 SPE_F3DMON1[7:0] SPE_F3DMON0[7:0]

0x30016

Page 143 SPE_RMON5 SPE_C2DMON[7:0]

0x30017 RSVD

Transmit/Receive Cont rol Parameters for Mapping Functions—R/W

0x30018

Page 143 SPE_MAP_CTL1 SPE_T_ST

S1_MODE SPE_T_NS

MI_MODE SPE_TDS3SRCTYP[1:0] SPE_T_

VT_DS3 SPE_T_

AU3_TUG3 SPE_TSTS3TMSLOT[1:0] SPE_R_

STS1_MODE SPE_R_

NSMI_MODE SPE_RDS3OUTTYP[1:0] SPE_R_

VT_DS3 SPE_R_

AU3_TUG3 SPE_RSTS3TMSLOT[1:0]

0x30019

Page 144 SPE_MAP_CTL2 SPE_T_NSMI_BIT[2:0] SPE_R_NSMI_BIT[2:0] SPE_JITTER_

FIFO SPE_

TDS3CLK_

EDGE

SPE_

PHDETUP_

INV

SPE_PHD

ETDN_

INV

SPE_TDS3

BPV_IN SPE_TDS3_

BIPOLAR SPE_RDS3_

BIPOLAR

0x3001A

Page 144 SPE_MAP_CTL3 SPE_T_NSMI_COL[6:0] SPE_R_NSMI_COL[6:0]

Transmit Control Parameters for Alarm and Overhead Functions—R/W

0x3001B

Page 146 SPE_TAOH_

CTL1 SPE_TD_

OEPAR SPE_TREIR

DISEL SPE_

TAISPINS SPE_

TN1INS SPE_

TK3INS SPE_

TH4INS SPE_

TF3INS SPE_

TF2INS SPE_

TC2INS SPE_

TJ1INS

0x3001C

Page 146 SPE_TAOH_

CTL2 SPE_TPOAC

_OEPMON SPE_

TPOAC_N1 SPE_

TPOAC_K3 SPE_

TPOAC_H4 SPE_

TPOAC_

SPE_

TPOAC_F2 SPE_

TPOAC_C2 SPE_

TPOAC_J1

0x3001D

Page 147 SPE_TAOH_

CTL3 SPE_NPI_BYTE2[7:0] SPE_NPI_BYTE1[7:0]

Transmit Path RDI and REI Control Parameters—R/W

0x3001E

Page 148 SPE_TRDIREI_

CTL SPE_

TPRDIINS SPE_

TTIM_

PRDIINH

SPE_

TPLM_

PRDIINH

SPE_

TUNEQ_

PRDIINH

SPE_

TLOP_

PRDIINH

SPE_

TPAIS_

PRDIINH

SPE_

TPRDI_

MODE

SPE_

TREIP_INH

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

155Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 179. SPE Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Erro r Insertion Control Parameters—R/W

0x3001F

Page 148 SPE_TERRINS_CTL SPE_BERR_INS SPE_TB3ERRINS SPE_TREIERRINS

Transmit OH Insert Value—R/W

0x30020

Page 149 SPE_TOHINS1 SPE_TF3DINS[7:0] SPE_TF2DINS[7:0]

0x30021

Page 149 SPE_TOHINS2 SPE_TC2DINS[7:0] SPE_TK3DINS[7:0]

0x30022

Page 149 SPE_TOHINS3 SPE_TG1DINS[7:0] SPE_TN1DINS[7:0]

0x30023

Page 149 SPE_TOHINS4 SPE_TH4DINS[7:0]

Signal Degrade Set/Clear Control Registers—R/W

0x30024

Page 149 SPE_SIGDEG_CTL1 SPE_SDNSSET[18:3]

0x30025

Page 149 SPE_SIGDEG_CTL2 SPE_SDMSET[7:0] SPE_SDLSET[3:0] SPE_SDNSSET[2:0]

0x30026

Page 149 SPE_SIGDEG_CTL3 SPE_SDBSET[15:0]

0x30027

Page 149 SPE_SIGDEG_CTL4 SPE_SDNSCLEAR[18:3]

0x30028

Page 149 SPE_SIGDEG_CTL5 SPE_SDMCLEAR[7:0] SPE_SDLCLEAR[3:0] SPE_SDNSCLEAR[2:0]

0x30029

Page 149 SPE_SIGDEG_CTL6 SPE_SDBCLEAR[15:0]

Signal Fail Set/Clear Control Registers—R/W

0x3002A

Page 150 SPE_SIGFAIL_CTL1 SPE_SFNSSET[18:3]

0x3002B

Page 150 SPE_SIGFAIL_CTL2 SPE_SFMSET[7:0] SPE_SFLSET[3:0] SPE_SFNSSET[2:0]

0x3002C

Page 150 SPE_SIGFAIL_CTL3 SPE_SFBSET[15:0]

0x3002D

Page 150 SPE_SIGFAIL_CTL4 SPE_SFNSCLEAR[18:3]

0x3002E

Page 150 SPE_SIGFAIL_CTL5 SPE_SFMCLEAR[7:0] SPE_SFLCLEAR[3:0] SPE_SFNSCLEAR[2:0]

0x3002F

Page 150 SPE_SIGFAIL_CTL6 SPE_SFBCLEAR[15:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

156 Agere Systems Inc.

9 SPE Mapper Registers (continued)

Table 179. SPE Mapper Register Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

B3 and G1 Error Counts—RO

0x30030

Page 150 SPE_ERRCNT1 SPE_B3ECNT[15:0]

0x30031

Page 150 SPE_ERRCNT2 SPE_G1ECNT[15:0]

0x30032

Page 150 RSVD

Bipolar Violation and Excess Zero Counts for DS3—RO

0x30033

Page 150 SPE_ERRCNT3 SPE_BIPOL_CNT[23:16]

0x30034

Page 150 SPE_ERRCNT4 SPE_BIPOL_CNT[15:0]

0x30035 Page 150 SPE_ERRCNT5 SPE_EXZ_CNT[23:16]

0x30036 Page 150 SPE_ERRCNT6 SPE_EXZ_CNT[15:0]

Receive Pointer Increment and Decrement Counts—RO

0x30037 Page 151 SPE_PTRCNT1 SPE_STORED_PTR[9:0]

0x30038 SPE_PTRCNT2 SPE_RPTR_INC[10:0]

0x30039 Page 151 SPE_PTRCNT3 SPE_RPTR_DEC[10:0]

0x3003A—0x30041 RSVD

J1 Byte Receive Monitor—RO

0x30042—0x30061

Page 151 SPE_RJ1MON_R1—

SPE_RJ1MON_R32 SPE_RJ1DMON[2][7:0]—SPE_RJ1DMON[64][7:0] SPE_RJ1DMON[1][7:0]

—

SPE_RJ1DMON[63][7:0]

J1 Byte Transmit Insert—R/W

0x30062—0x30081

Page 151 SPE_TJ1DINS_R1—

SPE_TJ1DINS_R32 SPE_TJ1DINS[2][7:0]—SPE_TJ1DINS[64][7:0] SPE_TJ1DINS[1][7:0]

—

SPE_TJ1DINS[63][7:0]

J1 Byte Expected Values—R/W

0x30082—0x300A1

Page 151 SPE_RJ1DEXP_R1—

SPE_RJ1DEXP_R32 SPE_RJ1DEXP[2][7:0]—SPE_RJ1DEXP[64][7:0] SPE_RJ1DEXP[1][7:0]

—

SPE_RJ1DEXP[63][7:0]

Scratc h Registe r—R/W

0x300A2 Page 151 SPE_SCRATCH_R SPE_SCRATCH[9:0]

0x300A3 Page 151 SPE_RX_THRES_CTL_DS3 SPE_RX_HIGH_THRES_DS3[6:0] SPE_RX_LOW_THRES_DS3[6:0]

0x300A4 Page 151 SPE_TX_THRES_CTL_DS3 SPE_TX_HIGH_THRES_DS3[6:0] SPE_TX_LOW_THRES_DS3[6:0]

0x300B0 Page 152 SPE_OV_UN_FIFO_THRES SPE_RX_OVUN_FLOW_THRES[6:0]

0x300B1 Page 152 SPE_OV_UN_FIFO_THRES SPE_TX_OVUN_FLOW_THRES[6:0]

0x300A3—0x301FF RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

157Agere Systems Inc.

10 VT/TU Mapper Registers

Table of Con t en ts

Contents Page

10 VT/TU Mapper Registers ........... ...... ....... ................... ....... ...... ...... ....... ...... ....... ...... .........................................157

10.1 VT/TU Mapper Register Descriptions.......................................................................................................158

10.2 VT/TU Mapper Register Map ...................................................................................................................175

Tables Page

Table 180. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO)...............................................158

Table 181. VT_GDELTA, VT Global Deltas (COR/COW)......................................................................................158

Table 182. VT_REVENT_DELTA[1—28], Receive Event and Delta Per Channel (COR/COW) ...........................159

Table 183. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW) .............................159

Table 184. VT_TEVENT_DELTA[1—28], Transmit Event and Delta Per Channel (COR/COW)...........................160

Table 185. VT_GMASK, VT Global Masks (R/W)..................................................................................................160

Table 186. VT_RMASK[1—28], Receive Masks Per Channel (R/W) ....................................................................161

Table 187. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)..........................................162

Table 188. VT_TMASK[1—28], Transmit Masks Per Channel (R/W)....................................................................162

Table 189. VT_GSTATE, VT Global State (RO) ....................................................................................................162

Table 190. VT_RSTATE[1—28], Receive State Per Channel (RO).......................................................................163

Table 191. VT_RAPSSTATE[1—28], Receive APS State Per Channel (RO)........................................................163

Table 192. VT_TSTATE[1—28], Transmit State Per Channel (RO) ......................................................................163

Table 193. VT_GCTL1, VT Global Control Register 1 (R/W) ................................................................................164

Table 194. VT_GCTL2, VT Global Control Register 2 (R/W) ................................................................................164

Table 195. VT_GCTL3, VT Global Control Register 3 (R/W) ................................................................................165

Table 196. VT_GCTL4, VT Global Control Register 4 (R/W) ................................................................................165

Table 197. VT_GCTL5, VT Global Control Register 5 (R/W) ................................................................................166

Table 198. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W) ..........................................................167

Table 199. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W) ..........................................................167

Table 200. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W) ..........................................................167

Table 201. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W) ..........................................................167

Table 202. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W) ..........................................................168

Table 203. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W) ..........................................................168

Table 204. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W) ..........................................................168

Table 205. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W)...................................................................168

Table 206. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W)...................................................................168

Table 207. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W)...................................................................168

Table 208. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W)...................................................................169

Table 209. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W)...................................................................169

Table 210. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W)...................................................................169

Table 211. VT_TCTL[1—28], Transmit Control Per Channel (R/W) ......................................................................170

Table 212. VT_TTUOH_CTL[1—28], Transmit TU Overhead Control Per Channel (R/W) ...................................171

Table 213. VT_TAPSRIVAL[1—28], Transmit APS and Remote Indication Per Channel (R/W)...........................171

Table 214. VT_TSWOW[1—28], Transmit Software Overwrite Per Channel (R/W)..............................................171

Table 215. VT_TSIG_CTL[1—28], Transmit Signaling Control Per Channel (R/W)..............................................172

Table 216. VT_J2BYTE_INS_R[1—28][1—16], J2 Insert Values Per Channel (R/W)...........................................172

Table 217. VT_RCTL[1—28], Receive Control Per Channel (R/W) ......................................................................172

Table 218. VT_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO) .....................................173

Table 219. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Count Per Channel (RO).............................................173

Table 220. VT_RREIV_CNT[1—28], Receive REI-V Error Count Per Channel (RO) ...........................................173

Table 221. VT_RPTR_CNT[1—28], Receive Pointer and Count Per Channel (RO).............................................174

Table 222. VT_J2BYTE_EXP_R[1—28][1—16], J2 Expected Values Per Channel (R/W, RO)............................174

Table 223. VT_THRES_CTL[1—28], Transmit Elastic Store Threshold Control (R/W).........................................174

Table 224. VT/TU Mapper Register Map...............................................................................................................175

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

158 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

10.1 VT/TU Mapper Reg ister Descr ip tions

The following tables describe the functions of all bits in the register map. For each address, the register bits are

indicated as either read/write (R/W) or read only (RO), and the value of the bits on reset is given.

Table 180. VT_VERSION_R, VT Mapper Ready, Version, and Identification (RO)

Table 181. VT_GDELTA, VT Global Deltas (COR/COW)

Address Bit Name Function Reset

Default

0x20000 15 VT_RDY VT/TU Mapper Ready. A 1 indicates that the VT/TU map-

per is ready for microprocessor reads and writes. 0x0

14:11 RSVD Reserved. 0x0

10:8 VT_VERSION[2:0] Block Version Number. These bits identify the version

number of the VT/TU mapper. NA

7:0 VT_ID[7:0] Block ID Number. VT_ID returns a fixed value (0x02)

when read. 0x02

Address Bit Name Function Reset

Default

0x20001 15:3 RSVD Reserved. 0x000

2VT_SD_DVT/TU Signal Degrade Delta Bit. Logic 1 indicates a

change in the signal degrade condition based on the inter-

nal bit error rate detec tor.

0x1

1VT_SF_DVT/TU Signal Fail Delta Bit. Logic 1 indicates a change in

the signal fail condition based on the internal bit error rate

detector.

0x1

0VT_H4LOMF_DH4 Mismatch Delta Bit. Logic 1 indicates a change in the

H4 loss of multiframe condition. 0x1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

159Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 182. VT_REVENT_DELTA[1—28], Receive Event and Delta Per Channel (COR/COW)

Table 183. VT_LOPOHFAIL_EVENT, Low-Order Path Overhead Failure Event (COR/COW)

Address Bit Name Function Reset

Default

0x20002

—

0x2001D

15 RSVD Reserved. 0

14 VT_RX_VTREI_E[1—28] Receive REI-V Event Bit. Logic 1 indicates that

REI-V was received. 0x0

13 VT_RX_BIP2ERR_E[1—28] Receive BIP-2 Error Even t Bit. Logic 1 indicates

that BIP-2 errors have been detected. 0x0

12 VT_RX_ESOVFL_E[1—28] Receive Elastic Store Overflow Event Bit.

Logic 1 indicates an elastic store overflow. 0x0

11 VT_APS_D[1—28] ERDI-V Delta Bit. Logic 1 indicates a VTAPS

change of value. 0x1

10 VT_ERDI_D[1—28] ERDI-V Delta Bit. Logic 1 indicates an ERDI-V

change of value. 0x1

9 VT_RDI_D[1—28] RDI-V Delta Bit. Logic 1 indicates an RDI-V change

of value. 0x1

8 VT_RFI_D[1—28] RFI-V Delta Bit. Logic 1 indicates an RFI-V change

of value. 0x1

7RSVDReserved. 0

6 VT_LOPS_D[1—28] VT Loss of Phase Sync Delta Bit. Logic 1 indi-

cates a change of VTLOPS state. 0x1

5VT_J2TIM_D[1—28]J2 Trace Identifier Mismatch. Logic 1 indicates a

change of J2TIM state. 0x1

4VT_PLM_D[1—28]VT Payload Label Mismatch Delta Bit. Logic 1

indicates a change of VTPLM state. 0x1

3 VT_UNEQ_D[1—28] VT Unequip Delta Bit. Logic 1 indicates a change

of VTUNEQ state. 0x1

2 VT_SIZERR_D[1—28] VT Size Er ror Delt a Bit. Logic 1 indicates a change

of VTSIZERR state. 0x1

1 VT_AIS_D[1—28] AIS-V Delta Bit. Logic 1 indicates a change of

VTAIS state. 0x0

0 VT_LOP_D[1—28] LOP-V Delta Bit. Logic 1 indicates a change of

VTLOP state. 0x1

Address Bit Name Function Reset

Default

0x2001E 15:1 RSVD Reserved. 0x000

0VT_LOPOH_FAIL_ELow-Order Path Overhead Fa ilure Event Bit.

Logic 1 indicates that a failure has occurred on the

LOPOH serial access channel.

0x0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

160 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 184. VT_TEVENT_DELTA[1—28], Transmit Event and Delta Per Channel (COR/COW)

Tab le 185. VT_G MA SK, VT Global Mas ks (R/W )

Address Bit Name Function Reset

Default

0x2001F

—

0x2003A

15:5 RSVD Reserved. 0x000

4 VT_TX_ESOVFL_E[1—28] T r ansmit Elastic Store Overflow Event Bit. Logic

1 indicates an elastic store overflow. 0x0

3RSVDReserved. 0

2 VT_LOFS_D[1—28] Loss of Frame Sync Delta Bit. Logic 1 indicates a

change of VT_LOF S [1— 28] (Table 192 on

page 163) state.

0x1

1 VT_TX_AIS_D[1—28] T ransmit AIS Delta Bit. Logic 1 indicates a change

of VT_TX_AIS[1—28] (Table 192 on page 163)

state.

0x0

0 VT_TX_LOC_D[1—28] Transmit Loss of Clock Delta Bit. Logi c 1 indi-

cates a change of VT_TX_LOC[1—28] (Table 192

on page 163) state.

0x1

Address Bit Name Function Reset

Default

0x2003B 15:3 RSVD Reserved. 0x000

2VT_SD_MVT/TU Signal Degrade Mask Bit. If set to a logic 1,

VT_SD_D (Table 181 on page 158) will not contribute t o

the interrupt.

0x1

1VT_SF_MVT/TU Signal Fail Mask Bit. If set to a logic 1, VT_SF_D

(Table 181 on page 158) will not contribute to the inter-

rupt.

0x1

0VT_H4LOMF_MH4 Mismatch Mask Bit. If set to a logic 1,

VT_H4LOMF_D (Table 181 on page 158) will not con-

tribute to the interrupt.

0x1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

161Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 186. VT_RMASK[1—28], Receive Masks Per Channel (R/W)

Note: The event and delta bits for these mask bits are in Table 182 on page 159.

Address Bit Name Function Reset

Default

0x2003C

—

0x20057

15 RSVD Reserved. 0

14 VT_RX_VTREI_M[1—28] Receive REI-V Mask Bit. If set to a logic 1,

VT_RX_VTREI_E[1—28] will not contribute to the inter-

rupt.

0x1

13 VT_RX_BIP2ERR_M[1—28] Receive BIP- 2 Er ror Mask Bit. If set to a logic 1,

VT_RX_BIP2ERR_E[1—28] will not contribute to the

interrupt.

0x1

12 VT_RX_ESOVFL_M[1—28] Receive Elastic Store Overflow Mask Bit. If set to a

logic 1, VT_RX_ESOVFL_E[1—28] will not contribute to

the interrupt.

0x1

11 VT_APS_M[1—28] VT APS Mask Bit. If set to a logic 1, VT_APS_D[1—28]

will not contribute to the interrupt. 0x1

10 VT_ERDI_M[1—28] ERDI-V Mask Bit. If set to a logic 1, VT_ERDI_D[1—28]

will not contribute to the interrupt. 0x1

9 VT_RDI_M[1—28] RDI-V Mask Bit. If set to a logic 1, VT_RDI_D[1—28] will

not contribute to the interrupt. 0x1

8VT_RFI_M[1—28]RFI-V Mask Bit. If set to a logic 1, VT_RFI_D[1—28] will

not contribute to the interrupt. 0x1

7RSVDReserved. 0

6 VT_LOPS_M[1—28] VT Loss of Phase Sync Mask Bit. If set to a logic 1,

VT_LOPS_D[1—28] will not contribute to the interrupt. 0x1

5 VT_J2TIM_M[1—28] J2 Mismatch Mask Bit. If set to a logic 1,

VT_J2TIM_D[1—28] will not contribute to the interrupt. 0x1

4 VT_PLM_M[1—28] VT Payload Label Mismatch Mask Bit. If set to a logic

1, VT_PLM_D[1—28] will not contribute to the interrupt. 0x1

3 VT_UNEQ_M[1—28] VT Unequip Mask Bit. If set to a logic 1,

VT_UNEQ_D[1—28] will not contribute to the interrupt. 0x1

2 VT_SIZERR_M[1—28] VT Size Error Mask Bit. If set to a logic 1,

VT_SIZERR_D[1—28] will not contribute to the interrupt. 0x1

1VT_AIS_M[1—28]AIS-V Mask Bit. If set to a logic 1, VT_AIS_D[1—28] will

not contribute to the interrupt. 0x1

0 VT_LOP_M[1—28] LOP-V Mask Bit. If set to a logic 1, VT_LOP_D[1—28]

will not contribute to the interrupt. 0x1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

162 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 187. VT_LOPOHFAIL_MASK, Low-Order Path Overhead Failure Mask (R/W)

Table 188. VT_TMASK[1—28], Transmit Masks Per Channel (R/W)

Table 189. VT_GSTATE, VT Global State (RO)

Address Bit Name Function Reset

Default

0x20058 15:1 RSVD Reserved. 0x000

0 VT_LOPOH_FAIL_M Low-Order Path Overhead Failure Mask Bit. If set to a

logic 1, VT_LOPOH_F AIL_E (Table 183 on page 159) will

not contribute to the interrupt.

0x1

Address Bit Name Function Reset

Default

0x20059

—

0x20074

15:5 RSVD Reserved. 0x000

4 VT_TX_ESOVFL_M[1—28] T ransmit Elastic Store Overflow Mask Bit. If set to

a logic 1, VT_TX_ESOVFL_E[1—28] (Table 184 on

page 160) will not contribute to the interrupt.

0x1

3RSVDReserved. 0

2 VT_LOFS_M[1—28] Loss of Frame Sync Mask Bit. If set to a logic 1,

VT_LOFS_D[1—28] (Table 184 on page 160) will

not contribute to the interrupt.

0x1

1 VT_TX_AIS_M[1—28] Transmit AIS Mask Bit. If set to a logic 1,

VT_TX_AIS_D[1—28] (Table 184 on page 160) will

not contribute to the interrupt.

0x1

0 VT_TX_LOC_M[1—28] Transmit Loss of Clock Mask Bit. If set to a logic

1, VT_TX_LO C_ D[1—2 8] (Table 184 on page 160)

will not contribute to the interrupt.

0x1

Address Bit Name Function Reset

Default

0x20075 15:3 RSVD Reserved. 0x000

2VT_SDVT/TU Signal Degrade. Logic 1 indicates a signal

degrade condition on the selected channel. 0x1

1VT_SFVT/TU Signal Fail. Logic 1 indicates a signal fail

condition on the selected channel. 0x1

0 VT_H4LOMF H4 Loss of Multiframe. Logic 1 indicates a loss of

H4 multiframe alignment. 0x1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

163Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 190. VT_RSTATE[1—28], Receive State Per Channel (RO)

Table 191. VT_RAPSSTATE[1—28], Receive APS State Per Channel (RO)

Table 192. VT_TSTATE[1—28], Transmit State Per Channel (RO)

Address Bit Name Function Reset

Default

0x20076

—

0x20091

15:13 VT_ERDI[1—28][2:0] Enhanced RDI-V V alue. Th ese b it s are t he st or ed ER DI- V

bits received in the Z7 byte. 0x000

12:10 VT_LAB[1—28][2:0] VT Signal Label. These bits are the stored VT signal label

bits rece ived in the V5 byte. 0x000

9 VT_RDI[1—28] RDI-V Value. This bit is the accepted RDI-V bit received in

the V5 byte. 0x00

8VT_RFI[1—28]RFI-V Value. This bit is the accepted RFI-V bit received in

the V5 byte. 0x00

7RSVDReserved. 0

6VT_LOPS[1—28]VT Loss of Phase Sync. Logic 1 indicates a loss of P-bit

phase synchronization. 0x1

5 VT_J2TIM[1—28] J2 Trace Identifier Mismatch. Logic 1 indicates a mis-

match between the expected trace and the detected trace. 0x1

4VT_PLM[1—28]VT Payload Label Mismatch. Logic 1 indicates PLM-V. 0x1

3 VT_UNEQ[1—28] VT Unequip. Logic 1 indicates UNEQ-V. 0x1

2 VT_SIZERR[1—28] VT Siz e Err or. Logic 1 indicates a VT size error. 0x1

1 VT_AIS[1—28] AIS-V. Logic 1 indicates AIS-V. 0x0

0 VT_LOP[1—28] LOP-V. Logic 1 indicates LOP-V. 0x1

Address Bit Name Function Reset

Default

0x20092

—

0x200AD

15:4 RSVD Reserved. 0x000

3:0 VT_APS[1—28][3:0] VT APS Value. These bits are the stored VT APS bits

received in the Z7/K4 byte. 0x0

Address Bit Name Function Reset

Default

0x200AE

—

0x200C9

15:3 RSVD Reserved. 0x000

2 VT_LOFS[1—28] Loss of Frame Sync. Logic 1 indicates DS1/E1 loss of

frame sync. 0x1

1 VT_TX_AIS[1—28] Transmit AIS. Logic 1 indicates DS1/E1 AIS. 0x0

0 VT_TX_LOC[1—28] Transmit Loss of Clock. Logic 1 indicates DS1/E1 loss

of clock. 0x1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

164 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 193. VT_GCTL1, VT Global Control Register 1 (R/W)

Table 194. VT_GCTL2, VT Global Control Register 2 (R/W)

Address Bit Name Function Reset

Default

0x200CA 15 RSVD Reserved. 0

14:8 VT_RX_GRP_TYPE[6:0] Receive Group Type. VT/TU group type selection.

Logic 1 selects VT1.5/TU-11 and logic 0 selects

VT2/TU-12 group type. Group 1 is the LSB.

0x7F

7RSVDReserved. 0

6:0 VT_TX_GRP_TYPE[6:0] Transmit Group Type. VT/TU group type select ion.

Logic 1 selects VT1.5/TU-11 and logic 0 selects

VT2/TU-12 group type. Group 1 is the LSB.

0x7F

Address Bit Name Function Reset

Default

0x200CB 15:11 RSVD Reserved. 0x00

10 VT_LOPS_AIS_INH VT/TU Loss of Phase Sync. Contribution to AIS inhibit

control. 0x0

9 VT_J2TIM_ERDI_INH J2 Trace Identifier Mismatch. Contribution to ERDI

inhibit co ntr ol . 0x0

8 VT_J2TIM_RDI_INH J2 T race Identifier Mismatch. Contribution to RDI inhibit

control. 0x0

7 VT_J2TIM_AIS_INH J2 Trace Identifier Mismatch. Contribution to AIS inhibit

control. 0x0

6 VT_LOMF_AIS_INH Loss of Multiframe. Contribution to AIS inhibit control. 0x0

5 VT_PLM_AIS_INH Payload Label Mismatch . Contribution to AIS inhibit con-

trol. 0x0

4 VT_UNEQ_AIS_INH UNEQ-V. Contribution to AIS inhibit control. 0x0

3RSVDReserved. 0

2VT_UPSRUnidirectional Path Switch Ring M ode Control. Logic 1

activates the UPSR mode of operation. When the device

is programmed for UPSR mode, the transmitted REI-V,

RDI-V, RFI-V, and ERDI-V are based on the receive con-

ditions. Otherwise, the transmitted LOPOH is a copy of

the received overhead bytes.

0x0

1VT_8ORMAJORITYVT Po in te r Interpre te r Mo de Cont ro l. Logic 1 tells the

pointer interpreter to transition into the inc and dec states

based on 8 of the 10 I and D bits. Otherwise, the pointer

interpreter transitions into the inc and dec states based on

majori ty ru le.

0x1

0 VT_BIT_BLOCK_CNT Performance Monitor Count Mode Control. Logic 1

activates BIP-2, TC-BIP-2, REI, and TC-CRC-7 counts

based on single bit errors. Otherwise, errors are counted

on a block basis.

0x1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

165Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 195. VT_GCTL3, VT Global Control Register 3 (R/W)

Table 196. VT_GCTL4, VT Global Control Register 4 (R/W)

Address Bit Name Function Reset

Default

0x200CC 15:8 RSVD Reserved. 0x00

7:4 VT_LOPS_NTIME[3:0] VT/TU Loss of Phase Sync NTIME Detection Control.

This nibble is programmed to provision the number of

consecutive errored phase indications required to transi-

tion into the VT_LOPS[1—28] (Table 190 on page 163)

state. This is only valid in byte-synchronous mode.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x6

3:0 VT_H4_NTIME[3:0] H4 Multiframe Indication NTIME Detection Control.

This nibble is programmed to provision the number of

consecutive errored multiframe indications required to

transition into the VT_H4LOMF (Table 189 on page 162)

state.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x6

Address Bit Name Function Reset

Default

0x200CD 15:11 VT_Z6_NTIME[3:0] Z6 Byte Monitor NTIME Detection Control. This nibble

is programmed to provision the number of consecutive

consistent Z6 bytes required to accept a new value.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x3

10:8 VT_J2_NTIME[3:0] J2 Byte Monitor NTIME Detection Control. This nibb le

is programmed to provision the number of consecutive

consistent J2 sequences required for the J2 byte monitor

to transition in and out of J2TIM.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x3

7:4 VT_INV_NTIME[3:0] Pointer Interpreter Invalid Pointer NTIME Detection

Control. This nibble is programmed to provision the

number of invalid pointers required for the pointer inter-

preter to go into the VT_LOP[1—28] (Table 190 on

page 163) state.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x8

3:0 VT_NDF_NTIME[3:0] Pointer Interpreter NDF Pointer NTIME Detection

Control. This nibble is programmed to provision the

number of consecutive NDF pointers required for the

pointer interpreter to go into the VT_LOP state.

Note: The valid range of values is 0x1—0xF. A value of

0x0 will be mapped to 0x1.

0x8

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

166 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 197. VT_GCTL5, VT Global Control Register 5 (R/W)

Address Bit Name Function Reset

Default

0x200CE 15:12 VT_APS_NTIME[3:0] APS NTIME Detection Control. This nibble is programmed

to provision the number of consecutive consistent new values

required to accept a new VT_APS[1—28][3:0] (Table 191 on

page 163).

Note: The valid range of values is 0x1—0xF. A value of 0x0

will be mapped to 0x1.

0x3

11:8 VT_LAB_NTIME[3:0] VT Signal Label NTIME Detection Control. This nibble is

programmed to provision the number of consecutive consis-

tent new values required to accept a new

VT_LAB[1—28][2:0] (Table 190 on page 163).

Note: The valid range of values is 0x1—0xF. A value of 0x0

will be mapped to 0x1.

0x3

7:4 VT_ERDI_NTIME[3:0] ERDI-V NTIME Detection Control. This nibble is pro-

grammed to provision the number of consecutive consistent

new values required to accept a new VT_ERDI[1—28][2:0]

(Table 190 on page 163).

Note: The valid range of values is 0x1—0xF. A value of 0x0

will be mapped to 0x1.

0x3

3:0 VT_RDI_NTIME[3:0] RDI-V NTIME Detection Control. This nibble is programmed

to provision the number of consecutive consistent new values

required to accept a new VT_RDI[1—28] (Table 190 on

page 163).

Note: The valid range of values is 0x1—0xF. A value of 0x0

will be mapped to 0x1.

0x3

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

167Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 198. VT_SIGDEG_CTL1, Signal Degrade Control Register 1 (R/W)

Table 199. VT_SIGDEG_CTL2, Signal Degrade Control Register 2 (R/W)

Table 200. VT_SIGDEG_CTL3, Signal Degrade Control Register 3 (R/W)

Table 201. VT_SIGDEG_CTL4, Signal Degrade Control Register 4 (R/W)

Address Bit Name Function Reset

Default

0x200CF 15:12 RSVD Reserved. 0x00

11 VT_SFCLEAR VT Signal Fail Clear . Allows the signal fail algorithm to be

forced into the normal state. This is a one-shot which is

activated by a 0 to 1 transition.

0x0

10 VT_SFSET VT Signal Fail Set. Allows the signal fail algorithm to be

forced into the failed state. This is a one-shot which is

activated by a 0 to 1 transition.

0x0

9 VT_SDCLEAR Signal Degrade Clear. Allows the signal degrade algo-

rithm to be forced into the normal state. This is a one-shot

which is activated by a 0 to 1 transition.

0x0

8VT_SDSETSignal Degrade Set. Allows the signal degrade algorithm

to be forced into the failed state. This is a one-shot which

is activated by a 0 to 1 transition.

0x0

7:5 RSVD Reserved. 000

4:0 VT_BER_CH_SEL[4:0] Bit Error Rate Monitor Channel Select. Selects which

channel (1—28/21) is being monitored by the internal

BER monitor. Valid inputs are 00001—11100.

0x00

Address Bit Name Function Reset

Default

0x200D0 15:0 VT_SDNSSET[18:3] Signal Degrade Ns Set. Number of frames in a monitor-

ing block for SD. 0x0000

Address Bit Name Function Reset

Default

0x200D1 15 RSVD Reserved. 0

14:7 VT_SDMSET[7:0] Signal Degrade M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the number

of bad blocks is above this threshold, then signal degrade

SD is set.

0x00

6:3 VT_SDLSET[3:0] Signal Degrade L Set. Error threshold for determining if a

monitoring block is bad. 0x0

2:0 VT_SDNSSET[2:0] Signal Degrade Ns Set. Number of frames in a monitor-

ing block for SD. 0x0

Address Bit Name Function Reset

Default

0x200D2 15:0 VT_SDBSET[15:0] Signal Degrade B Set. Number of monitoring blocks. 0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

168 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 202. VT_SIGDEG_CTL5, Signal Degrade Control Register 5 (R/W)

Table 203. VT_SIGDEG_CTL6, Signal Degrade Control Register 6 (R/W)

Table 204. VT_SIGDEG_CTL7, Signal Degrade Control Register 7 (R/W)

Table 205. VT_SIGFAIL_CTL1, Signal Fail Control Register 1 (R/W)

Table 206. VT_SIGFAIL_CTL2, Signal Fail Control Register 2 (R/W)

Table 207. VT_SIGFAIL_CTL3, Signal Fail Control Register 3 (R/W)

Address Bit Name Function Reset

Default

0x200D3 15:0 VT_SDNSCLEAR[18:3] Signal Degrade Ns Clear. Number of frames in a moni-

toring blo ck for SD. 0x0000

Address Bit Name Function Reset

Default

0x200D4 15 RSVD Reserved. 0

14:7 VT_SDMCLEAR[7:0] Signal Degrade M Clear . Threshold of the number of bad

monitoring blocks in an observation interval. If the number

of bad blocks is below this threshold, then SD is cleared.

0x00

6:3 VT_SDLCLEAR[3:0] Signal Degrade L Clear. Error threshold for determining

if a monitoring block is bad. 0x0

2:0 VT_SDNSCLEAR[2:0] Signal Degrade Ns Clear. Number of frames in a moni-

toring block for SD. 0x0

Address Bit Name Function Reset

Default

0x200D5 15:0 VT_SDBCLEAR[15:0] Signal Degrade B Clear. Number of monitoring blocks. 0x0000

Address Bit Name Function Reset

Default

0x200D6 15:0 VT_SFNSSET[18:3] Signal Fail Ns Set. Number of frames in a monitoring block

for SF. 0x0000

Address Bit Name Function Reset

Default

0x200D7 15 RSVD Reserved. 0

14:7 VT_SFMSET[7:0] Signal Fail M Set. Threshold of the number of bad

monitoring blocks in an observation interval. If the number

of bad blocks is above this threshold, then SF is set.

0x00

6:3 VT_SFLSET[3:0] Signal Fail L Set. Error threshold for determining if a

monitoring block is bad. 0x0

2:0 VT_SFNSSET[2:0] Signal Fail Ns Set. Number of frames in a monitoring

block for SF. 0x0

Address Bit Name Function Reset

Default

0x200D8 15:0 VT_SFBSET[15:0] Signal Fail B Set. Number of monitoring blocks. 0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

169Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 208. VT_SIGFAIL_CTL4, Signal Fail Control Register 4 (R/W)

Table 209. VT_SIGFAIL_CTL5, Signal Fail Control Register 5 (R/W)

Table 210. VT_SIGFAIL_CTL6, Signal Fail Control Register 6 (R/W)

Address Bit Name Function Reset

Default

0x200D9 15:0 VT_SFNSCLEAR[18:3] Signal Fail Ns Clear. Number of frames in a monitoring

block for SF. 0x0000

Address Bit Name Function Reset

Default

0x200DA 15 RSVD Reserved. 0

14:7 VT_SFMCLEAR[7:0] Signal Fail M Clear. Threshold of the number of bad

monitoring blocks in an observation interval. If the

number of bad blocks is below this threshold, then SF is

cleared.

0x00

6:3 VT_SFLCLEAR[3:0] Signal Fail L Clear. Error threshold for determining if a

monitoring block is bad. 0x0

2:0 VT_SFNSCLEAR[2:0] Signal Fail Ns Clear. Number of frames in a monitoring

block for SF. 0x0

Address Bit Name Function Reset

Default

0x200DB 15:0 VT_SFBCLEAR[15:0] Signal Fail B Clear. Number of monitoring blocks. 0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

170 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 211. VT_TCTL[1—28], Transmit Control Per Cha nnel (R/W)

Address Bit Name Function Reset

Default

0x200DC

—

0x200F7

15:13 RSVD Reserved. 0x0

12 VT_TX_ERDI_EN[1—28] T ransmit Path Enhanced RDI-V Enable. Logic 1

enables enha nc ed RDI- V. 0x0

11 VT_ERDI_EN[1—28] Enhanced RDI-V Source Selection. Logic 1

activates so ft w a re ov er write of t h e ER DI -V bits of

the Z7 byte. Otherwise, insertion is based on the

LOPOH serial channel or automatic generation.

0x0

10 VT_RDI_EN[1—28] RDI-V Source Selection. Logic 1 activates soft-

ware overwrite of the RDI-V bit of the V5 byte.

Otherwise, insertion is based on the LOPOH

serial channel or automatic generation.

0x0

9 VT_RFI_EN[1—28] RFI-V Source Selection. Logic 1 activates soft-

ware overwrite of the RFI-V bit of the V5 byte. If

VT_V5_INS[1—28] = 0 (Table 212 on page 171)

and the mapping is set to byte synchronous DS1,

a logic 0 enables automatic insertion of RFI-V. If

VT_V5_INS[1—28] = 1, a logic 0 inserts RFI-V

based on the LOPOH serial channel.

0x0

8 VT_REI_EN[1—28] REI-V Enable. Logic 1 activates automatic gener-

ation of REI-V. If VT_V5_INS[1—28] = 0, the gen-

eration is based on the received BIP-2 errors.

Otherwise, insertion is based on the LOPOH

serial channel.

0x0

7RSVDReserved. 0

6 VT_AIS_INS[1—28] AIS-V Insertion Control. Logic 1 forces AIS-V to

be transmitted in the specified channel. 0x0

5 VT_TX_CLKEDGE[1—28] Transmit Path DS1/E1 Clock Edge Selection.

Logic 1 forces the DS1/E1 signals to be retimed

using the rising edge of the associated clock.

Logic 0 forces the DS1/E1 signals to be retimed

using the falling edge of the associated clock.

0x0

4 VT_LB_SEL[1—28] Tributary Loopback Selection. Logic 1 acti-

vates tributary loopback. 0x0

3:0 VT_TX_MAPTYPE[1—28][3:0] Transmit Mapping Mode Control. See

Table 570 on page 448.0x6

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

171Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 212. VT_TTUOH_CTL[1—28], Transmit TU Overhead Control Per Channel (R/W)

Table 213. VT_TAPSRIVAL[1—28], Transmit APS and Remote Indication Per Channel (R/W)

Table 214. VT_TSWOW[1—28], Transmit Software Overwrite Per Channel (R/W)

Address Bit Name Function Reset

Default

0x200F8

—

0x20113

15:11 RSVD Reserved. 0x00

10:9 VT_O_INS[1—28][1:0] O Bit Insertion Control. See Table 578 on page 453.0x0

8:7 VT_Z7_INS[1—28][1:0] Z7 Byte Insertion Control. See Table 577 on page 452.0x0

6:5 VT_Z6_INS[1—28][1:0] Z6 Byte Insertion Control. See Table 576 on page 452.0x0

4:3 VT_J2_INS[1—28][1:0] J2 Byte Insertion Control. See Table 575 on page 452.0x0

2 VT_V5_INS[1—28] V5 Byte Insertion Control. Logic 1 forces the V5 byte to

be programmed via the LOPOH serial channel. See

Table 571 on page 450.

0x0

1:0 VT_BIP2ERR_

INS[1—28][1:0] BIP-2 Error Insertion Control. See Table 572 on

page 450.0x0

Address Bit Name Function Reset

Default

0x20114

—

0x2012F

15:12 RSVD Reserved. 0x0

11:8 VT_APS_

INS[1—28][3:0] APS Software Overwrite Value. This nibble is pro-

grammed to utilize APS bits in the Z7/K4 byte. This nibble

will be transmitted in bits 1:4 of the Z7/K4 byte.

0x0

7:5 RSVD Reserved. 0x0

4:2 VT_ERDI_

INS[1—28][2:0] Enhanced RDI-V Software Overwrite Values. If

VT_ERDI_EN[1—28] (Table 211 on pa ge 170 ) is a logic 1,

these bits are written into the ERDI-V locations of the Z7

byte.

0x0

1 VT_RDI_INS[1—28] RDI-V Sof tware Ov erwri te Valu es. If VT_RDI_EN[1—28]

(Table 211 on page 170) is a logic 1, this value will be writ-

ten into the RDI-V location of the V5 byte.

0x0

0VT_RFI_INS[1—28]RFI-V Software Overwrite Values. If VT_RFI_EN[1—28]

(Table 211 on page 170) is a logic 1, this value will be writ-

ten into the RFI-V location of the V5 byte.

0x0

Address Bit Name Function Reset

Default

0x20130

—

0x2014B

15:8 VT_OBIT_

INS[1—28][7:0] Overhead Values for Software Overwrite in Asynchro-

nous Mappings. This byte is programmed to utilize the

overhead bits in asynchronous VT/TU mappings.

VT_OBIT_INS[7:4] will be transmitted in the byte following

J2, and VT_OBIT_INS[3:0] will be transmitted in the byte

followi ng Z6/N2.

0x00

7:0 VT_Z6BYTE_

INS[1—28][7:0] Z6 Software Ov erwrite V a lues. This byte is programmed

into the outgoing Z6/N2 location when

VT_Z6_INS[1—28][1:0] (Table 212 on page 171) = 01.

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

172 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 215. VT_TSIG_CTL[1—28], Transmit Signaling Control Per Channel (R/W)

Table 216. VT_J2BYTE_INS_R[1—28][1—16], J2 Insert Values Per Channel (R/W)

Address Bit Name Function Reset

Default

0x2014C

—

0x20167

15:11 RSVD Reserved. 000000

10 VT_USE_FBIT[1—28] Frame Bit Use Control. Logic 1 provisions use

of the F bit in the outgoing VT/TU. Otherwise,

the F bit is forced to the value of bit

SMPR_OH_DEFLT (Table 77 on page 70) in

the microprocessor interface on the outgoing

VT/TU.

0x1

9 VT_USE_PBIT[1—28] Phase Bit Use Control. Logic 1 provisions use

of the P bits in the outgoing VT/TU. Otherwise,

the P bits are forced to the value of bit

SMPR_OH_DEFLT in the microprocessor inter-

face on the outgoing VT/TU.

0x1

8 VT_USE_SBIT[1—28] Signaling Bit Use Control. Logic 1 provisions

use of the S bits in the outgoing VT/TU. Other-

wise, the S bits are forced to the value of bit

SMPR_OH_DEFLT in the microprocessor inter-

face on the outgoing VT/TU.

0x1

7:5 RSVD Reserved. 000

4:0 VT_TXSIG_CH_SEL[1—28][4:0] T ransmit Input Channel Selection. These bits

are programmed wi th the same value as the

cross connect for each individual channel. The

bits are only used in byte-synchronous mode

and can be set to 0xXX for all other modes. If an

invalid value is programmed, UNEQ-V will be

transmitted in the specified channel. Invalid

decimal values are 0, 29, 30, and 31.

0x00

Address Bit Name Function Reset

Default

0x20168

—

0x20327

15:8 RSVD Reserved. 0x00

7:0 VT_J2BYTE_

INS[1—28][1—16][7:0] J2 Software Overwrite Values. These values are written

into the outgoing J2 byte when VT_J2_INS[1—28][1:0] = 01

(Table 212 on page 171).

0x00

Table 217. VT_RCTL[1—28], Receive Control Per Channel (R/W)

Address Bit Name Function Reset

Default

0x20328

—

0x20343

15 VT_SF_ESF[1—28] DS1 Frame Type for Byte-Synchronous

Mode. Logic 1 provisions an SF frame format.

Otherwise, an ESF frame format is provisioned.

0x0

14 VT_WR_FBIT[1—28] F-Bit Provisioning Control. See Table 568 on

page 446.0x0

13 VT_SYNC_PBIT[1—28] P-Bit Pr ovisioning Control. See Table 568 on

page 446.0x0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

10 VT/TU Mapper Registers (continued)

173Agere Systems Inc.

Table 218. VT_RTUOH_CTL[1—28], Receive TU Overhead Control Per Channel (RO)

Table 219. VT_RBIP2_CNT[1—28], Receive BIP-2 Error Count Per Channel (RO)

Table 220. VT_RREIV_CNT[1—28], Receive REI-V Error Count Per Channel (RO)

0x20328

—

0x20343

12:8 VT_RXSIG_CH_SEL[1—28][4:0] Receive Output Cha nnel Selection. These bits

are programmed with the same value as the

cross connect for each individual channel. The

bits are only used in byte-synchronous mod e

and can be set to 0xXX for all other modes. If an

invalid value is programmed, UNEQ-V will be

transmitted in the specified channel. Invalid deci-

mal values are 0, 29, 30, and 31. See Table 568

on page 446.

0x00

7:5 VT_J2MON_MODE[1—28][2:0] J2 Trace Monitoring Mode Control. See Sec-

tion 19.11, J2 Byte Monitor and Termination

(J2MON), on page 444.

0x00

4 VT_RX_ERDI_EN[1—28] Receive Path Enhanced RDI-V Enable. Logic 1

enables enhanced RDI-V. 0x0

3:0 VT_RX_MAPTYPE[1—28][3:0] Receive Demapping Mode Control. See

Table 567 on page 443.0x6

Address Bit Name Function Reset

Default

0x20344

—

0x2035F

15:8 VT_Z6_BYTE[1—28][7:0] Received Z6/N2 Byte Value. Accepted Z6/N2 value. 0x00

7:0 VT_OBITS[1—28][7:0] Received O Bits Value. Accepted overhead bits in

asynchronous and bit-synchronous modes.

VT_OBITS[7:4] are the O bits received in the byte follow-

ing J2, and VT_OBITS[3:0] are the O bits received in the

byte following Z6/N2.

0x00

Address Bit Name Function Reset

Default

0x20360

—

0x2037B

15:12 RSVD Reserved. 0x0

11:0 VT_BIP2ERR_CNT[1—28][11:0] BIP-2 Error Count. BIP-2 error count updated on

a 0 to 1 transition of SMPR_PMRESET (Table 75

on page 68).

0x000

Address Bit Name Function Reset

Default

0x2037C

—

0x20397

15:11 RSVD Reserved. 0x00

10:0 VT_REI_CNT[1—28][10:0] REI-V Error Count. REI-V error count updated

on a 0 to 1 transition of SMPR_PMRESET. 0x000

Table 217. VT_RCTL[1—28], Receive Control Per Channel (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

174 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 221. VT_RPTR_CNT[1—28], Receive Pointer and Count Per Channel (RO)

Table 222. VT_J2BYTE_EXP_R[1—28][1—16], J2 Expected Values Per Channel (R/W, RO)

Address Bit Name Function Reset

Default

0x20398

—

0x203B3

15:8 VT_STORED_PTR[1—28][7:0] Store VT/TU Pointer Location. This value indi-

cates the stored location of the V5 byte within the

VT/TU mapping.

0x00

7:4 VT_PTR_DEC[1—28][3:0] VT Pointer Decrement Count. VT pointer decre-

ment count updated on a 0 to 1 transition of

SMPR_PMRESET.

0x0

3:0 VT_PTR_INC[1—28][3:0] VT Pointer Increment Count. VT pointer incre-

ment count updated on a 0 to 1 transition of

SMPR_PMRESET.

0x0

Address Bit Name Function Reset

Default

0x203B4

—

0x20573

15:8 VT_J2BYTE_EXP[1—28][1—16][7:0] J2 Expected Values. This value is pro-

grammed by the user as an expected value

for the J2 byte. The hardware will compare

this value to the incoming J2 sequence

when VT_J2MON_MODE[1—28][2:0] =

011 or 100 (Table 217 on page 172).

0x00

7:0 VT_J2BYTE_

DET[1—28][1—16][7:0] J2 Detected Values. Ac ce pte d J2

sequence or value. 0x00

Table 223. VT_THRES_CTL[1—28], Transmit Elastic Store Threshold Control (R/W)

Address Bit Name Function Reset

Default

0x20574

—

0x2058F

15 RSVD Reserved. 0x0

14:8 VT_HIGH_THRES[1—28][6:0] Transmit Elastic Store High Threshold.

Programmable threshold controlling posi-

tive justifications.

0x28

7RSVDReserved. 0x0

6:0 VT_LOW_THRES[1—28][6:0] Transmit Elastic Store Low Threshold.

Programmable threshold controlling nega-

tive justifications.

0x27

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

175Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

10.2 VT/TU Mapper Reg ister Map

Table 224. VT/TU Mapper Register Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Mapper ID—RO

0x20000

Page 158 VT_VERSION_R VT_

RDY VT_VERSION[2:0] VT_ID[7:0]

VT Global Events—COR/COW

0x20001

Page 158 VT_GDELETA VT_SD_D VT_SF_D VT_H4LOMF_D

Receive Delta and Event Parameters—COR/COW

For the following addresses, reference Table 182 on page 159.

0x20002 VT_REVENT_DELTA1 VT_RX_VTREI_E1 VT_RX_BIP2ERR_E1 VT_RX_ESOVFL_E1 VT_APS_D1 VT_ERDI_D1 VT_RDI_D1 VT_RFI_D1 VT_LOPS_D1 VT_J2TIM_D1 VT_PLM_D1 VT_UNEQ_D1 VT_SIZERR_D1 VT_AIS_D1 VT_LOP_D1

0x20003 VT_REVENT_DELTA2 VT_RX_VTREI_E2 VT_RX_BIP2ERR_E2 VT_RX_ESOVFL_E2 VT_APS_D2 VT_ERDI_D2 VT_RDI_D2 VT_RFI_D2 VT_LOPS_D2 VT_J2TIM_D2 VT_PLM_D2 VT_UNEQ_D2 VT_SIZERR_D2 VT_AIS_D2 VT_LOP_D2

0x20004 VT_REVENT_DELTA3 VT_RX_VTREI_E3 VT_RX_BIP2ERR_E3 VT_RX_ESOVFL_E3 VT_APS_D3 VT_ERDI_D3 VT_RDI_D3 VT_RFI_D3 VT_LOPS_D3 VT_J2TIM_D3 VT_PLM_D3 VT_UNEQ_D3 VT_SIZERR_D3 VT_AIS_D3 VT_LOP_D3

0x20005 VT_REVENT_DELTA4 VT_RX_VTREI_E4 VT_RX_BIP2ERR_E4 VT_RX_ESOVFL_E4 VT_APS_D4 VT_ERDI_D4 VT_RDI_D4 VT_RFI_D4 VT_LOPS_D4 VT_J2TIM_D4 VT_PLM_D4 VT_UNEQ_D4 VT_SIZERR_D4 VT_AIS_D4 VT_LOP_D4

0x20006 VT_REVENT_DELTA5 VT_RX_VTREI_E5 VT_RX_BIP2ERR_E5 VT_RX_ESOVFL_E5 VT_APS_D5 VT_ERDI_D5 VT_RDI_D5 VT_RFI_D5 VT_LOPS_D5 VT_J2TIM_D5 VT_PLM_D5 VT_UNEQ_D5 VT_SIZERR_D5 VT_AIS_D5 VT_LOP_D5

0x20007 VT_REVENT_DELTA6 VT_RX_VTREI_E6 VT_RX_BIP2ERR_E6 VT_RX_ESOVFL_E6 VT_APS_D6 VT_ERDI_D6 VT_RDI_D6 VT_RFI_D6 VT_LOPS_D6 VT_J2TIM_D6 VT_PLM_D6 VT_UNEQ_D6 VT_SIZERR_D6 VT_AIS_D6 VT_LOP_D6

0x20008 VT_REVENT_DELTA7 VT_RX_VTREI_E7 VT_RX_BIP2ERR_E7 VT_RX_ESOVFL_E7 VT_APS_D7 VT_ERDI_D7 VT_RDI_D7 VT_RFI_D7 VT_LOPS_D7 VT_J2TIM_D7 VT_PLM_D7 VT_UNEQ_D7 VT_SIZERR_D7 VT_AIS_D7 VT_LOP_D7

0x20009 VT_REVENT_DELTA8 VT_RX_VTREI_E8 VT_RX_BIP2ERR_E8 VT_RX_ESOVFL_E8 VT_APS_D8 VT_ERDI_D8 VT_RDI_D8 VT_RFI_D8 VT_LOPS_D8 VT_J2TIM_D8 VT_PLM_D8 VT_UNEQ_D8 VT_SIZERR_D8 VT_AIS_D8 VT_LOP_D8

0x2000A VT_REVENT_DELTA9 VT_RX_VTREI_E9 VT_RX_BIP2ERR_E9 VT_RX_ESOVFL_E9 VT_APS_D9 VT_ERDI_D9 VT_RDI_D9 VT_RFI_D9 VT_LOPS_D9 VT_J2TIM_D9 VT_PLM_D9 VT_UNEQ_D9 VT_SIZERR_D9 VT_AIS_D9 VT_LOP_D9

0x2000B VT_REVENT_DELTA10 VT_RX_VTREI_E10 VT_RX_BIP2ERR_E10 VT_RX_ESOVFL_E10 VT_APS_D10 VT_ERDI_D10 VT_RDI_D10 VT_RFI_D10 VT_LOPS_D10 VT_J2TIM_D10 VT_PLM_D10 VT_UNEQ_D10 VT_SIZERR_D10 VT_AIS_D10 VT_LOP_D10

0x2000C VT_REVENT_DELTA11 VT_RX_VTREI_E11 VT_RX_BIP2ERR_E11 VT_RX_ESOVFL_E11 VT_APS_D11 VT_ERDI_D11 VT_RDI_D11 VT_RFI_D11 VT_LOPS_D11 VT_J2TIM_D11 VT_PLM_D11 VT_UNEQ_D11 VT_SIZERR_D11 VT_AIS_D11 VT_LOP_D11

0x2000D VT_REVENT_DELTA12 VT_RX_VTREI_E12 VT_RX_BIP2ERR_E12 VT_RX_ESOVFL_E12 VT_APS_D12 VT_ERDI_D12 VT_RDI_D12 VT_RFI_D12 VT_LOPS_D12 VT_J2TIM_D12 VT_PLM_D12 VT_UNEQ_D12 VT_SIZERR_D12 VT_AIS_D12 VT_LOP_D12

0x2000E VT_REVENT_DELTA13 VT_RX_VTREI_E13 VT_RX_BIP2ERR_E13 VT_RX_ESOVFL_E13 VT_APS_D13 VT_ERDI_D13 VT_RDI_D13 VT_RFI_D13 VT_LOPS_D13 VT_J2TIM_D13 VT_PLM_D13 VT_UNEQ_D13 VT_SIZERR_D13 VT_AIS_D13 VT_LOP_D13

0x2000F VT_REVENT_DELTA14 VT_RX_VTREI_E14 VT_RX_BIP2ERR_E14 VT_RX_ESOVFL_E14 VT_APS_D14 VT_ERDI_D14 VT_RDI_D14 VT_RFI_D14 VT_LOPS_D14 VT_J2TIM_D14 VT_PLM_D14 VT_UNEQ_D14 VT_SIZERR_D14 VT_AIS_D14 VT_LOP_D14

0x20010 VT_REVENT_DELTA15 VT_RX_VTREI_E15 VT_RX_BIP2ERR_E15 VT_RX_ESOVFL_E15 VT_APS_D15 VT_ERDI_D15 VT_RDI_D15 VT_RFI_D15 VT_LOPS_D15 VT_J2TIM_D15 VT_PLM_D15 VT_UNEQ_D15 VT_SIZERR_D15 VT_AIS_D15 VT_LOP_D15

0x20011 VT_REVENT_DELTA16 VT_RX_VTREI_E16 VT_RX_BIP2ERR_E16 VT_RX_ESOVFL_E16 VT_APS_D16 VT_ERDI_D16 VT_RDI_D16 VT_RFI_D16 VT_LOPS_D16 VT_J2TIM_D16 VT_PLM_D16 VT_UNEQ_D16 VT_SIZERR_D16 VT_AIS_D16 VT_LOP_D16

0x20012 VT_REVENT_DELTA17 VT_RX_VTREI_E17 VT_RX_BIP2ERR_E17 VT_RX_ESOVFL_E17 VT_APS_D17 VT_ERDI_D17 VT_RDI_D17 VT_RFI_D17 VT_LOPS_D17 VT_J2TIM_D17 VT_PLM_D17 VT_UNEQ_D17 VT_SIZERR_D17 VT_AIS_D17 VT_LOP_D17

0x20013 VT_REVENT_DELTA18 VT_RX_VTREI_E18 VT_RX_BIP2ERR_E18 VT_RX_ESOVFL_E18 VT_APS_D18 VT_ERDI_D18 VT_RDI_D18 VT_RFI_D18 VT_LOPS_D18 VT_J2TIM_D18 VT_PLM_D18 VT_UNEQ_D18 VT_SIZERR_D18 VT_AIS_D18 VT_LOP_D18

0x20014 VT_REVENT_DELTA19 VT_RX_VTREI_E19 VT_RX_BIP2ERR_E19 VT_RX_ESOVFL_E19 VT_APS_D19 VT_ERDI_D19 VT_RDI_D19 VT_RFI_D19 VT_LOPS_D19 VT_J2TIM_D19 VT_PLM_D19 VT_UNEQ_D19 VT_SIZERR_D19 VT_AIS_D19 VT_LOP_D19

0x20015 VT_REVENT_DELTA20 VT_RX_VTREI_E20 VT_RX_BIP2ERR_E20 VT_RX_ESOVFL_E20 VT_APS_D20 VT_ERDI_D20 VT_RDI_D20 VT_RFI_D20 VT_LOPS_D20 VT_J2TIM_D20 VT_PLM_D20 VT_UNEQ_D20 VT_SIZERR_D20 VT_AIS_D20 VT_LOP_D20

0x20016 VT_REVENT_DELTA21 VT_RX_VTREI_E21 VT_RX_BIP2ERR_E21 VT_RX_ESOVFL_E21 VT_APS_D21 VT_ERDI_D21 VT_RDI_D21 VT_RFI_D21 VT_LOPS_D21 VT_J2TIM_D21 VT_PLM_D21 VT_UNEQ_D21 VT_SIZERR_D21 VT_AIS_D21 VT_LOP_D21

0x20017 VT_REVENT_DELTA22 VT_RX_VTREI_E22 VT_RX_BIP2ERR_E22 VT_RX_ESOVFL_E22 VT_APS_D22 VT_ERDI_D22 VT_RDI_D22 VT_RFI_D22 VT_LOPS_D22 VT_J2TIM_D22 VT_PLM_D22 VT_UNEQ_D22 VT_SIZERR_D22 VT_AIS_D22 VT_LOP_D22

0x20018 VT_REVENT_DELTA23 VT_RX_VTREI_E23 VT_RX_BIP2ERR_E23 VT_RX_ESOVFL_E23 VT_APS_D23 VT_ERDI_D23 VT_RDI_D23 VT_RFI_D23 VT_LOPS_D23 VT_J2TIM_D23 VT_PLM_D23 VT_UNEQ_D23 VT_SIZERR_D23 VT_AIS_D23 VT_LOP_D23

0x20019 VT_REVENT_DELTA24 VT_RX_VTREI_E24 VT_RX_BIP2ERR_E24 VT_RX_ESOVFL_E24 VT_APS_D24 VT_ERDI_D24 VT_RDI_D24 VT_RFI_D24 VT_LOPS_D24 VT_J2TIM_D24 VT_PLM_D24 VT_UNEQ_D24 VT_SIZERR_D24 VT_AIS_D24 VT_LOP_D24

0x2001A VT_REVENT_DELTA25 VT_RX_VTREI_E25 VT_RX_BIP2ERR_E25 VT_RX_ESOVFL_E25 VT_APS_D25 VT_ERDI_D25 VT_RDI_D25 VT_RFI_D25 VT_LOPS_D25 VT_J2TIM_D25 VT_PLM_D25 VT_UNEQ_D25 VT_SIZERR_D25 VT_AIS_D25 VT_LOP_D25

0x2001B VT_REVENT_DELTA26 VT_RX_VTREI_E26 VT_RX_BIP2ERR_E26 VT_RX_ESOVFL_E26 VT_APS_D26 VT_ERDI_D26 VT_RDI_D26 VT_RFI_D26 VT_LOPS_D26 VT_J2TIM_D26 VT_PLM_D26 VT_UNEQ_D26 VT_SIZERR_D26 VT_AIS_D26 VT_LOP_D26

0x2001C VT_REVENT_DELTA27 VT_RX_VTREI_E27 VT_RX_BIP2ERR_E27 VT_RX_ESOVFL_E27 VT_APS_D27 VT_ERDI_D27 VT_RDI_D27 VT_RFI_D27 VT_LOPS_D27 VT_J2TIM_D27 VT_PLM_D27 VT_UNEQ_D27 VT_SIZERR_D27 VT_AIS_D27 VT_LOP_D27

0x2001D VT_REVENT_DELTA28 VT_RX_VTREI_E28 VT_RX_BIP2ERR_E28 VT_RX_ESOVFL_E28 VT_APS_D28 VT_ERDI_D28 VT_RDI_D28 VT_RFI_D28 VT_LOPS_D28 VT_J2TIM_D28 VT_PLM_D28 VT_UNEQ_D28 VT_SIZERR_D28 VT_AIS_D28 VT_LOP_D28

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

176 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Delta and Event Parameters—COR/COW

0x2001E

Page 159 VT_LOPOHFAIL_EVENT VT_LOPOH_FAIL_E

For the following addresses, reference Table 184 on page 160.

0x2001F VT_TEVENT_DELTA1 VT_TX_ESOVFL_E1 VT_LOFS_D1 VT_TX_AIS_D1 VT_TX_LOC_D1

0x20020 VT_TEVENT_DELTA2 VT_TX_ESOVFL_E2 VT_LOFS_D2 VT_TX_AIS_D2 VT_TX_LOC_D2

0x20021 VT_TEVENT_DELTA3 VT_TX_ESOVFL_E3 VT_LOFS_D3 VT_TX_AIS_D3 VT_TX_LOC_D3

0x20022 VT_TEVENT_DELTA4 VT_TX_ESOVFL_E4 VT_LOFS_D4 VT_TX_AIS_D4 VT_TX_LOC_D4

0x20023 VT_TEVENT_DELTA5 VT_TX_ESOVFL_E5 VT_LOFS_D5 VT_TX_AIS_D5 VT_TX_LOC_D5

0x20024 VT_TEVENT_DELTA6 VT_TX_ESOVFL_E6 VT_LOFS_D6 VT_TX_AIS_D6 VT_TX_LOC_D6

0x20025 VT_TEVENT_DELTA7 VT_TX_ESOVFL_E7 VT_LOFS_D7 VT_TX_AIS_D7 VT_TX_LOC_D7

0x20026 VT_TEVENT_DELTA8 VT_TX_ESOVFL_E8 VT_LOFS_D8 VT_TX_AIS_D8 VT_TX_LOC_D8

0x20027 VT_TEVENT_DELTA9 VT_TX_ESOVFL_E9 VT_LOFS_D9 VT_TX_AIS_D9 VT_TX_LOC_D9

0x20028 VT_TEVENT_DELTA10 VT_TX_ESOVFL_E10 VT_LOFS_D10 VT_TX_AIS_D10 VT_TX_LOC_D10

0x20029 VT_TEVENT_DELTA11 VT_TX_ESOVFL_E11 VT_LOFS_D11 VT_TX_AIS_D11 VT_TX_LOC_D11

0x2002A VT_TEVENT_DELTA12 VT_TX_ESOVFL_E12 VT_LOFS_D12 VT_TX_AIS_D12 VT_TX_LOC_D12

0x2002B VT_TEVENT_DELTA13 VT_TX_ESOVFL_E13 VT_LOFS_D13 VT_TX_AIS_D13 VT_TX_LOC_D13

0x2002C VT_TEVENT_DELTA14 VT_TX_ESOVFL_E14 VT_LOFS_D14 VT_TX_AIS_D14 VT_TX_LOC_D14

0x2002D VT_TEVENT_DELTA15 VT_TX_ESOVFL_E15 VT_LOFS_D15 VT_TX_AIS_D15 VT_TX_LOC_D15

0x2002E VT_TEVENT_DELTA16 VT_TX_ESOVFL_E16 VT_LOFS_D16 VT_TX_AIS_D16 VT_TX_LOC_D16

0x2002F VT_TEVENT_DELTA17 VT_TX_ESOVFL_E17 VT_LOFS_D17 VT_TX_AIS_D17 VT_TX_LOC_D17

0x20030 VT_TEVENT_DELTA18 VT_TX_ESOVFL_E18 VT_LOFS_D18 VT_TX_AIS_D18 VT_TX_LOC_D18

0x20031 VT_TEVENT_DELTA19 VT_TX_ESOVFL_E19 VT_LOFS_D19 VT_TX_AIS_D19 VT_TX_LOC_D19

0x20032 VT_TEVENT_DELTA20 VT_TX_ESOVFL_E20 VT_LOFS_D20 VT_TX_AIS_D20 VT_TX_LOC_D20

0x20033 VT_TEVENT_DELTA21 VT_TX_ESOVFL_E21 VT_LOFS_D21 VT_TX_AIS_D21 VT_TX_LOC_D21

0x20034 VT_TEVENT_DELTA22 VT_TX_ESOVFL_E22 VT_LOFS_D22 VT_TX_AIS_D22 VT_TX_LOC_D22

0x20035 VT_TEVENT_DELTA23 VT_TX_ESOVFL_E23 VT_LOFS_D23 VT_TX_AIS_D23 VT_TX_LOC_D23

0x20036 VT_TEVENT_DELTA24 VT_TX_ESOVFL_E24 VT_LOFS_D24 VT_TX_AIS_D24 VT_TX_LOC_D24

0x20037 VT_TEVENT_DELTA25 VT_TX_ESOVFL_E25 VT_LOFS_D25 VT_TX_AIS_D25 VT_TX_LOC_D25

0x20038 VT_TEVENT_DELTA26 VT_TX_ESOVFL_E26 VT_LOFS_D26 VT_TX_AIS_D26 VT_TX_LOC_D26

0x20039 VT_TEVENT_DELTA27 VT_TX_ESOVFL_E27 VT_LOFS_D27 VT_TX_AIS_D27 VT_TX_LOC_D27

0x2003A VT_TEVENT_DELTA28 VT_TX_ESOVFL_E28 VT_LOFS_D28 VT_TX_AIS_D28 VT_TX_LOC_D28

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

177Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Global Interrupt Masks—R/W

0x2003B

Page 160 VT_GMASK VT_SD_M VT_SF_M VT_H4LOMF_

Receive Interrupt Masks—R/W

For the following addresses, reference Table 186 on page 161.

0x2003C VT_RMASK1 VT_RX_VTREI_M1 VT_RX_BIP2ERR_M1 VT_RX_ESOVFL_M1 VT_APS_M1 VT_ERDI_M1 VT_RDI_M1 VT_RFI_M1 VT_LOPS_M1 VT_J2TIM_M1 VT_PLM_M1 VT_UNEQ_M1 VT_SIZERR_M1 VT_AIS_M1 VT_LOP_M1

0x2003D VT_RMASK2 VT_RX_VTREI_M2 VT_RX_BIP2ERR_M2 VT_RX_ESOVFL_M2 VT_APS_M2 VT_ERDI_M2 VT_RDI_M2 VT_RFI_M2 VT_LOPS_M2 VT_J2TIM_M2 VT_PLM_M2 VT_UNEQ_M2 VT_SIZERR_M2 VT_AIS_M2 VT_LOP_M2

0x2003E VT_RMASK3 VT_RX_VTREI_M3 VT_RX_BIP2ERR_M3 VT_RX_ESOVFL_M3 VT_APS_M3 VT_ERDI_M3 VT_RDI_M3 VT_RFI_M3 VT_LOPS_M3 VT_J2TIM_M3 VT_PLM_M3 VT_UNEQ_M3 VT_SIZERR_M3 VT_AIS_M3 VT_LOP_M3

0x2003F VT_RMASK4 VT_RX_VTREI_M4 VT_RX_BIP2ERR_M4 VT_RX_ESOVFL_M4 VT_APS_M4 VT_ERDI_M4 VT_RDI_M4 VT_RFI_M4 VT_LOPS_M4 VT_J2TIM_M4 VT_PLM_M4 VT_UNEQ_M4 VT_SIZERR_M4 VT_AIS_M4 VT_LOP_M4

0x20040 VT_RMASK5 VT_RX_VTREI_M5 VT_RX_BIP2ERR_M5 VT_RX_ESOVFL_M5 VT_APS_M5 VT_ERDI_M5 VT_RDI_M5 VT_RFI_M5 VT_LOPS_M5 VT_J2TIM_M5 VT_PLM_M5 VT_UNEQ_M5 VT_SIZERR_M5 VT_AIS_M5 VT_LOP_M5

0x20041 VT_RMASK6 VT_RX_VTREI_M6 VT_RX_BIP2ERR_M6 VT_RX_ESOVFL_M6 VT_APS_M6 VT_ERDI_M6 VT_RDI_M6 VT_RFI_M6 VT_LOPS_M6 VT_J2TIM_M6 VT_PLM_M6 VT_UNEQ_M6 VT_SIZERR_M6 VT_AIS_M6 VT_LOP_M6

0x20042 VT_RMASK7 VT_RX_VTREI_M7 VT_RX_BIP2ERR_M7 VT_RX_ESOVFL_M7 VT_APS_M7 VT_ERDI_M7 VT_RDI_M7 VT_RFI_M7 VT_LOPS_M7 VT_J2TIM_M7 VT_PLM_M7 VT_UNEQ_M7 VT_SIZERR_M7 VT_AIS_M7 VT_LOP_M7

0x20043 VT_RMASK8 VT_RX_VTREI_M8 VT_RX_BIP2ERR_M8 VT_RX_ESOVFL_M8 VT_APS_M8 VT_ERDI_M8 VT_RDI_M8 VT_RFI_M8 VT_LOPS_M8 VT_J2TIM_M8 VT_PLM_M8 VT_UNEQ_M8 VT_SIZERR_M8 VT_AIS_M8 VT_LOP_M8

0x20044 VT_RMASK9 VT_RX_VTREI_M9 VT_RX_BIP2ERR_M9 VT_RX_ESOVFL_M9 VT_APS_M9 VT_ERDI_M9 VT_RDI_M9 VT_RFI_M9 VT_LOPS_M9 VT_J2TIM_M9 VT_PLM_M9 VT_UNEQ_M9 VT_SIZERR_M9 VT_AIS_M9 VT_LOP_M9

0x20045 VT_RMASK10 VT_RX_VTREI_M10 VT_RX_BIP2ERR_M10 VT_RX_ESOVFL_M10 VT_APS_M10 VT_ERDI_M10 VT_RDI_M10 VT_RFI_M10 VT_LOPS_M10 VT_J2TIM_M10 VT_PLM_M10 VT_UNEQ_M10 VT_SIZERR_M10 VT_AIS_M10 VT_LOP_M10

0x20046 VT_RMASK11 VT_RX_VTREI_M11 VT_RX_BIP2ERR_M11 VT_RX_ESOVFL_M11 VT_APS_M11 VT_ERDI_M11 VT_RDI_M11 VT_RFI_M11 VT_LOPS_M11 VT_J2TIM_M11 VT_PLM_M11 VT_UNEQ_M11 VT_SIZERR_M11 VT_AIS_M11 VT_LOP_M11

0x20047 VT_RMASK12 VT_RX_VTREI_M12 VT_RX_BIP2ERR_M12 VT_RX_ESOVFL_M12 VT_APS_M12 VT_ERDI_M12 VT_RDI_M12 VT_RFI_M12 VT_LOPS_M12 VT_J2TIM_M12 VT_PLM_M12 VT_UNEQ_M12 VT_SIZERR_M12 VT_AIS_M12 VT_LOP_M12

0x20048 VT_RMASK13 VT_RX_VTREI_M13 VT_RX_BIP2ERR_M13 VT_RX_ESOVFL_M13 VT_APS_M13 VT_ERDI_M13 VT_RDI_M13 VT_RFI_M13 VT_LOPS_M13 VT_J2TIM_M13 VT_PLM_M13 VT_UNEQ_M13 VT_SIZERR_M13 VT_AIS_M13 VT_LOP_M13

0x20049 VT_RMASK14 VT_RX_VTREI_M14 VT_RX_BIP2ERR_M14 VT_RX_ESOVFL_M14 VT_APS_M14 VT_ERDI_M14 VT_RDI_M14 VT_RFI_M14 VT_LOPS_M14 VT_J2TIM_M14 VT_PLM_M14 VT_UNEQ_M14 VT_SIZERR_M14 VT_AIS_M14 VT_LOP_M14

0x2004A VT_RMASK15 VT_RX_VTREI_M15 VT_RX_BIP2ERR_M15 VT_RX_ESOVFL_M15 VT_APS_M15 VT_ERDI_M15 VT_RDI_M15 VT_RFI_M15 VT_LOPS_M15 VT_J2TIM_M15 VT_PLM_M15 VT_UNEQ_M15 VT_SIZERR_M15 VT_AIS_M15 VT_LOP_M15

0x2004B VT_RMASK16 VT_RX_VTREI_M16 VT_RX_BIP2ERR_M16 VT_RX_ESOVFL_M16 VT_APS_M16 VT_ERDI_M16 VT_RDI_M16 VT_RFI_M16 VT_LOPS_M16 VT_J2TIM_M16 VT_PLM_M16 VT_UNEQ_M16 VT_SIZERR_M16 VT_AIS_M16 VT_LOP_M16

0x2004C VT_RMASK17 VT_RX_VTREI_M17 VT_RX_BIP2ERR_M17 VT_RX_ESOVFL_M17 VT_APS_M17 VT_ERDI_M17 VT_RDI_M17 VT_RFI_M17 VT_LOPS_M17 VT_J2TIM_M17 VT_PLM_M17 VT_UNEQ_M17 VT_SIZERR_M17 VT_AIS_M17 VT_LOP_M17

0x2004D VT_RMASK18 VT_RX_VTREI_M18 VT_RX_BIP2ERR_M18 VT_RX_ESOVFL_M18 VT_APS_M18 VT_ERDI_M18 VT_RDI_M18 VT_RFI_M18 VT_LOPS_M18 VT_J2TIM_M18 VT_PLM_M18 VT_UNEQ_M18 VT_SIZERR_M18 VT_AIS_M18 VT_LOP_M18

0x2004E VT_RMASK19 VT_RX_VTREI_M19 VT_RX_BIP2ERR_M19 VT_RX_ESOVFL_M19 VT_APS_M19 VT_ERDI_M19 VT_RDI_M19 VT_RFI_M19 VT_LOPS_M19 VT_J2TIM_M19 VT_PLM_M19 VT_UNEQ_M19 VT_SIZERR_M19 VT_AIS_M19 VT_LOP_M19

0x2004F VT_RMASK20 VT_RX_VTREI_M20 VT_RX_BIP2ERR_M20 VT_RX_ESOVFL_M20 VT_APS_M20 VT_ERDI_M20 VT_RDI_M20 VT_RFI_M20 VT_LOPS_M20 VT_J2TIM_M20 VT_PLM_M20 VT_UNEQ_M20 VT_SIZERR_M20 VT_AIS_M20 VT_LOP_M20

0x20050 VT_RMASK21 VT_RX_VTREI_M21 VT_RX_BIP2ERR_M21 VT_RX_ESOVFL_M21 VT_APS_M21 VT_ERDI_M21 VT_RDI_M21 VT_RFI_M21 VT_LOPS_M21 VT_J2TIM_M21 VT_PLM_M21 VT_UNEQ_M21 VT_SIZERR_M21 VT_AIS_M21 VT_LOP_M21

0x20051 VT_RMASK22 VT_RX_VTREI_M22 VT_RX_BIP2ERR_M22 VT_RX_ESOVFL_M22 VT_APS_M22 VT_ERDI_M22 VT_RDI_M22 VT_RFI_M22 VT_LOPS_M22 VT_J2TIM_M22 VT_PLM_M22 VT_UNEQ_M22 VT_SIZERR_M22 VT_AIS_M22 VT_LOP_M22

0x20052 VT_RMASK23 VT_RX_VTREI_M23 VT_RX_BIP2ERR_M23 VT_RX_ESOVFL_M23 VT_APS_M23 VT_ERDI_M23 VT_RDI_M23 VT_RFI_M23 VT_LOPS_M23 VT_J2TIM_M23 VT_PLM_M23 VT_UNEQ_M23 VT_SIZERR_M23 VT_AIS_M23 VT_LOP_M23

0x20053 VT_RMASK24 VT_RX_VTREI_M24 VT_RX_BIP2ERR_M24 VT_RX_ESOVFL_M24 VT_APS_M24 VT_ERDI_M24 VT_RDI_M24 VT_RFI_M24 VT_LOPS_M24 VT_J2TIM_M24 VT_PLM_M24 VT_UNEQ_M24 VT_SIZERR_M24 VT_AIS_M24 VT_LOP_M24

0x20054 VT_RMASK25 VT_RX_VTREI_M25 VT_RX_BIP2ERR_M25 VT_RX_ESOVFL_M25 VT_APS_M25 VT_ERDI_M25 VT_RDI_M25 VT_RFI_M25 VT_LOPS_M25 VT_J2TIM_M25 VT_PLM_M25 VT_UNEQ_M25 VT_SIZERR_M25 VT_AIS_M25 VT_LOP_M25

0x20055 VT_RMASK26 VT_RX_VTREI_M26 VT_RX_BIP2ERR_M26 VT_RX_ESOVFL_M26 VT_APS_M26 VT_ERDI_M26 VT_RDI_M26 VT_RFI_M26 VT_LOPS_M26 VT_J2TIM_M26 VT_PLM_M26 VT_UNEQ_M26 VT_SIZERR_M26 VT_AIS_M26 VT_LOP_M26

0x20056 VT_RMASK27 VT_RX_VTREI_M27 VT_RX_BIP2ERR_M27 VT_RX_ESOVFL_M27 VT_APS_M27 VT_ERDI_M27 VT_RDI_M27 VT_RFI_M27 VT_LOPS_M27 VT_J2TIM_M27 VT_PLM_M27 VT_UNEQ_M27 VT_SIZERR_M27 VT_AIS_M27 VT_LOP_M27

0x20057 VT_RMASK28 VT_RX_VTREI_M28 VT_RX_BIP2ERR_M28 VT_RX_ESOVFL_M28 VT_APS_M28 VT_ERDI_M28 VT_RDI_M28 VT_RFI_M28 VT_LOPS_M28 VT_J2TIM_M28 VT_PLM_M28 VT_UNEQ_M28 VT_SIZERR_M28 VT_AIS_M28 VT_LOP_M28

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

178 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

T ra nsm it Interr upt Masks—R /W

0x20058

Page 162 VT_LOPOHFAIL_MASK VT_LOPOH_FAIL_M

For the following addresses, reference Table 188 on page 162.

0x20059 VT_TMASK1 VT_TX_ESOVFL_M1 VT_LOFS_M1 VT_TX_AIS_M1 VT_TX_LOC_M1

0x2005A VT_TMASK2 VT_TX_ESOVFL_M2 VT_LOFS_M2 VT_TX_AIS_M2 VT_TX_LOC_M2

0x2005B VT_TMASK3 VT_TX_ESOVFL_M3 VT_LOFS_M3 VT_TX_AIS_M3 VT_TX_LOC_M3

0x2005C VT_TMASK4 VT_TX_ESOVFL_M4 VT_LOFS_M4 VT_TX_AIS_M4 VT_TX_LOC_M4

0x2005D VT_TMASK5 VT_TX_ESOVFL_M5 VT_LOFS_M5 VT_TX_AIS_M5 VT_TX_LOC_M5

0x2005E VT_TMASK6 VT_TX_ESOVFL_M6 VT_LOFS_M6 VT_TX_AIS_M6 VT_TX_LOC_M6

0x2005F VT_TMASK7 VT_TX_ESOVFL_M7 VT_LOFS_M7 VT_TX_AIS_M7 VT_TX_LOC_M7

0x20060 VT_TMASK8 VT_TX_ESOVFL_M8 VT_LOFS_M8 VT_TX_AIS_M8 VT_TX_LOC_M8

0x20061 VT_TMASK9 VT_TX_ESOVFL_M9 VT_LOFS_M9 VT_TX_AIS_M9 VT_TX_LOC_M9

0x20062 VT_TMASK10 VT_TX_ESOVFL_M10 VT_LOFS_M10 VT_TX_AIS_M10 VT_TX_LOC_M10

0x20063 VT_TMASK11 VT_TX_ESOVFL_M11 VT_LOFS_M11 VT_TX_AIS_M11 VT_TX_LOC_M11

0x20064 VT_TMASK12 VT_TX_ESOVFL_M12 VT_LOFS_M12 VT_TX_AIS_M12 VT_TX_LOC_M12

0x20065 VT_TMASK13 VT_TX_ESOVFL_M13 VT_LOFS_M13 VT_TX_AIS_M13 VT_TX_LOC_M13

0x20066 VT_TMASK14 VT_TX_ESOVFL_M14 VT_LOFS_M14 VT_TX_AIS_M14 VT_TX_LOC_M14

0x20067 VT_TMASK15 VT_TX_ESOVFL_M15 VT_LOFS_M15 VT_TX_AIS_M15 VT_TX_LOC_M15

0x20068 VT_TMASK16 VT_TX_ESOVFL_M16 VT_LOFS_M16 VT_TX_AIS_M16 VT_TX_LOC_M16

0x20069 VT_TMASK17 VT_TX_ESOVFL_M17 VT_LOFS_M17 VT_TX_AIS_M17 VT_TX_LOC_M17

0x2006A VT_TMASK18 VT_TX_ESOVFL_M18 VT_LOFS_M18 VT_TX_AIS_M18 VT_TX_LOC_M18

0x2006B VT_TMASK19 VT_TX_ESOVFL_M19 VT_LOFS_M19 VT_TX_AIS_M19 VT_TX_LOC_M19

0x2006C VT_TMASK20 VT_TX_ESOVFL_M20 VT_LOFS_M20 VT_TX_AIS_M20 VT_TX_LOC_M20

0x2006D VT_TMASK21 VT_TX_ESOVFL_M21 VT_LOFS_M21 VT_TX_AIS_M21 VT_TX_LOC_M21

0x2006E VT_TMASK22 VT_TX_ESOVFL_M22 VT_LOFS_M22 VT_TX_AIS_M22 VT_TX_LOC_M22

0x2006F VT_TMASK23 VT_TX_ESOVFL_M23 VT_LOFS_M23 VT_TX_AIS_M23 VT_TX_LOC_M23

0x20070 VT_TMASK24 VT_TX_ESOVFL_M24 VT_LOFS_M24 VT_TX_AIS_M24 VT_TX_LOC_M24

0x20071 VT_TMASK25 VT_TX_ESOVFL_M25 VT_LOFS_M25 VT_TX_AIS_M25 VT_TX_LOC_M25

0x20072 VT_TMASK26 VT_TX_ESOVFL_M26 VT_LOFS_M26 VT_TX_AIS_M26 VT_TX_LOC_M26

0x20073 VT_TMASK27 VT_TX_ESOVFL_M27 VT_LOFS_M27 VT_TX_AIS_M27 VT_TX_LOC_M27

0x20074 VT_TMASK28 VT_TX_ESOVFL_M28 VT_LOFS_M28 VT_TX_AIS_M28 VT_TX_LOC_M28

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

179Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive State Param eter s—RO

0x20075

Page 162 VT_GSTATE VT_SD VT_SF VT_H4LOMF

For the following addresses, reference Table 190 on page 163.

0x20076 VT_RSTATE1 VT_ERDI(1)[2:0] VT_LAB(1)[2:0] VT_RDI(1) VT_RFI1 VT_LOPS1 VT_J2TIM1 VT_PLM1 VT_UNEQ1 VT_SIZERR1 VT_AIS1 VT_LOP1

0x20077 VT_RSTATE2 VT_ERDI(2)[2:0] VT_LAB(2)[2:0] VT_RDI(2) VT_RFI2 VT_LOPS2 VT_J2TIM2 VT_PLM2 VT_UNEQ2 VT_SIZERR2 VT_AIS2 VT_LOP2

0x20078 VT_RSTATE3 VT_ERDI(3)[2:0] VT_LAB(3)[2:0] VT_RDI(3) VT_RFI3 VT_LOPS3 VT_J2TIM3 VT_PLM3 VT_UNEQ3 VT_SIZERR3 VT_AIS3 VT_LOP3

0x20079 VT_RSTATE4 VT_ERDI(4)[2:0] VT_LAB(4)[2:0] VT_RDI(4) VT_RFI4 VT_LOPS4 VT_J2TIM4 VT_PLM4 VT_UNEQ4 VT_SIZERR4 VT_AIS4 VT_LOP4

0x2007A VT_RSTATE5 VT_ERDI(5)[2:0] VT_LAB(5)[2:0] VT_RDI(5) VT_RFI5 VT_LOPS5 VT_J2TIM5 VT_PLM5 VT_UNEQ5 VT_SIZERR5 VT_AIS5 VT_LOP5

0x2007B VT_RSTATE6 VT_ERDI(6)[2:0] VT_LAB(6)[2:0] VT_RDI(6) VT_RFI6 VT_LOPS6 VT_J2TIM6 VT_PLM6 VT_UNEQ6 VT_SIZERR6 VT_AIS6 VT_LOP6

0x2007C VT_RSTATE7 VT_ERDI(7)[2:0] VT_LAB(7)[2:0] VT_RDI(7) VT_RFI7 VT_LOPS7 VT_J2TIM7 VT_PLM7 VT_UNEQ7 VT_SIZERR7 VT_AIS7 VT_LOP7

0x2007D VT_RSTATE8 VT_ERDI(8)[2:0] VT_LAB(8)[2:0] VT_RDI(8) VT_RFI8 VT_LOPS8 VT_J2TIM8 VT_PLM8 VT_UNEQ8 VT_SIZERR8 VT_AIS8 VT_LOP8

0x2007E VT_RSTATE9 VT_ERDI(9)[2:0] VT_LAB(9)[2:0] VT_RDI(9) VT_RFI9 VT_LOPS9 VT_J2TIM9 VT_PLM9 VT_UNEQ9 VT_SIZERR9 VT_AIS9 VT_LOP9

0x2007F VT_RSTATE10 VT_ERDI(10)[2:0] VT_LAB(10)[2:0] VT_RDI(10) VT_RFI10 VT_LOPS10 VT_J2TIM10 VT_PLM10 VT_UNEQ10 VT_SIZERR10 VT_AIS10 VT_LOP10

0x20080 VT_RSTATE11 VT_ERDI(11)[2:0] VT_LAB(11)[2:0] VT_RDI(11) VT_RFI11 VT_LOPS11 VT_J2TIM11 VT_PLM11 VT_UNEQ11 VT_SIZERR11 VT_AIS11 VT_LOP11

0x20081 VT_RSTATE12 VT_ERDI(12)[2:0] VT_LAB(12)[2:0] VT_RDI(12) VT_RFI12 VT_LOPS12 VT_J2TIM12 VT_PLM12 VT_UNEQ12 VT_SIZERR12 VT_AIS12 VT_LOP12

0x20082 VT_RSTATE13 VT_ERDI(13)[2:0] VT_LAB(13)[2:0] VT_RDI(13) VT_RFI13 VT_LOPS13 VT_J2TIM13 VT_PLM13 VT_UNEQ13 VT_SIZERR13 VT_AIS13 VT_LOP13

0x20083 VT_RSTATE14 VT_ERDI(14)[2:0] VT_LAB(14)[2:0] VT_RDI(14) VT_RFI14 VT_LOPS14 VT_J2TIM14 VT_PLM14 VT_UNEQ14 VT_SIZERR14 VT_AIS14 VT_LOP14

0x20084 VT_RSTATE15 VT_ERDI(15)[2:0] VT_LAB(15)[2:0] VT_RDI(15) VT_RFI15 VT_LOPS15 VT_J2TIM15 VT_PLM15 VT_UNEQ15 VT_SIZERR15 VT_AIS15 VT_LOP15

0x20085 VT_RSTATE16 VT_ERDI(16)[2:0] VT_LAB(16)[2:0] VT_RDI(16) VT_RFI16 VT_LOPS16 VT_J2TIM16 VT_PLM16 VT_UNEQ16 VT_SIZERR16 VT_AIS16 VT_LOP16

0x20086 VT_RSTATE17 VT_ERDI(17)[2:0] VT_LAB(17)[2:0] VT_RDI(17) VT_RFI17 VT_LOPS17 VT_J2TIM17 VT_PLM17 VT_UNEQ17 VT_SIZERR17 VT_AIS17 VT_LOP17

0x20087 VT_RSTATE18 VT_ERDI(18)[2:0] VT_LAB(18)[2:0] VT_RDI(18) VT_RFI18 VT_LOPS18 VT_J2TIM18 VT_PLM18 VT_UNEQ18 VT_SIZERR18 VT_AIS18 VT_LOP18

0x20088 VT_RSTATE19 VT_ERDI(19)[2:0] VT_LAB(19)[2:0] VT_RDI(19) VT_RFI19 VT_LOPS19 VT_J2TIM19 VT_PLM19 VT_UNEQ19 VT_SIZERR19 VT_AIS19 VT_LOP19

0x20089 VT_RSTATE20 VT_ERDI(20)[2:0] VT_LAB(20)[2:0] VT_RDI(20) VT_RFI20 VT_LOPS20 VT_J2TIM20 VT_PLM20 VT_UNEQ20 VT_SIZERR20 VT_AIS20 VT_LOP20

0x2008A VT_RSTATE21 VT_ERDI(21)[2:0] VT_LAB(21)[2:0] VT_RDI(21) VT_RFI21 VT_LOPS21 VT_J2TIM21 VT_PLM21 VT_UNEQ21 VT_SIZERR21 VT_AIS21 VT_LOP21

0x2008B VT_RSTATE22 VT_ERDI(22)[2:0] VT_LAB(22)[2:0] VT_RDI(22) VT_RFI22 VT_LOPS22 VT_J2TIM22 VT_PLM22 VT_UNEQ22 VT_SIZERR22 VT_AIS22 VT_LOP22

0x2008C VT_RSTATE23 VT_ERDI(23)[2:0] VT_LAB(23)[2:0] VT_RDI(23) VT_RFI23 VT_LOPS23 VT_J2TIM23 VT_PLM23 VT_UNEQ23 VT_SIZERR23 VT_AIS23 VT_LOP23

0x2008D VT_RSTATE24 VT_ERDI(24)[2:0] VT_LAB(24)[2:0] VT_RDI(24) VT_RFI24 VT_LOPS24 VT_J2TIM24 VT_PLM24 VT_UNEQ24 VT_SIZERR24 VT_AIS24 VT_LOP24

0x2008E VT_RSTATE25 VT_ERDI(25)[2:0] VT_LAB(25)[2:0] VT_RDI(25) VT_RFI25 VT_LOPS25 VT_J2TIM25 VT_PLM25 VT_UNEQ25 VT_SIZERR25 VT_AIS25 VT_LOP25

0x2008F VT_RSTATE26 VT_ERDI(26)[2:0] VT_LAB(26)[2:0] VT_RDI(26) VT_RFI26 VT_LOPS26 VT_J2TIM26 VT_PLM26 VT_UNEQ26 VT_SIZERR26 VT_AIS26 VT_LOP26

0x20090 VT_RSTATE27 VT_ERDI(27)[2:0] VT_LAB(27)[2:0] VT_RDI(27) VT_RFI27 VT_LOPS27 VT_J2TIM27 VT_PLM27 VT_UNEQ27 VT_SIZERR27 VT_AIS27 VT_LOP27

0x20091 VT_RSTATE28 VT_ERDI(28)[2:0] VT_LAB(28)[2:0] VT_RDI(28) VT_RFI28 VT_LOPS28 VT_J2TIM28 VT_PLM28 VT_UNEQ28 VT_SIZERR28 VT_AIS28 VT_LOP28

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

180 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive APS Value Parameters—RO

For the following addresses, reference Table 191 on page 163.

0x20092 VT_RAPSSTATE1 VT_APS(1)[3:0]

0x20093 VT_RAPSSTATE2 VT_APS(2)[3:0]

0x20094 VT_RAPSSTATE3 VT_APS(3)[3:0]

0x20095 VT_RAPSSTATE4 VT_APS(4)[3:0]

0x20096 VT_RAPSSTATE5 VT_APS(5)[3:0]

0x20097 VT_RAPSSTATE6 VT_APS(6)[3:0]

0x20098 VT_RAPSSTATE7 VT_APS(7)[3:0]

0x20099 VT_RAPSSTATE8 VT_APS(8)[3:0]

0x2009A VT_RAPSSTATE9 VT_APS(9)[3:0]

0x2009B VT_RAPSSTATE10 VT_APS(10)[3:0]

0x2009C VT_RAPSSTATE11 VT_APS(11)[3:0]

0x2009D VT_RAPSSTATE12 VT_APS(12)[3:0]

0x2009E VT_RAPSSTATE13 VT_APS(13)[3:0]

0x2009F VT_RAPSSTATE14 VT_APS(14)[3:0]

0x200A0 VT_RAPSSTATE15 VT_APS(15)[3:0]

0x200A1 VT_RAPSSTATE16 VT_APS(16)[3:0]

0x200A2 VT_RAPSSTATE17 VT_APS(17)[3:0]

0x200A3 VT_RAPSSTATE18 VT_APS(18)[3:0]

0x200A4 VT_RAPSSTATE19 VT_APS(19)[3:0]

0x200A5 VT_RAPSSTATE20 VT_APS(20)[3:0]

0x200A6 VT_RAPSSTATE21 VT_APS(21)[3:0]

0x200A7 VT_RAPSSTATE22 VT_APS(22)[3:0]

0x200A8 VT_RAPSSTATE23 VT_APS(23)[3:0]

0x200A9 VT_RAPSSTATE24 VT_APS(24)[3:0]

0x200AA VT_RAPSSTATE25 VT_APS(25)[3:0]

0x200AB VT_RAPSSTATE26 VT_APS(26)[3:0]

0x200AC VT_RAPSSTATE27 VT_APS(27)[3:0]

0x200AD VT_RAPSSTATE28 VT_APS(28)[3:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

181Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit State Parameters—RO

For the following addresses, reference Table 192 on page 163.

0x200AE VT_TSTATE1 VT_LOFS1 VT_TX_AIS1 VT_TX_LOC1

0x200AF VT_TSTATE2 VT_LOFS2 VT_TX_AIS2 VT_TX_LOC2

0x200B0 VT_TSTATE3 VT_LOFS3 VT_TX_AIS3 VT_TX_LOC3

0x200B1 VT_TSTATE4 VT_LOFS4 VT_TX_AIS4 VT_TX_LOC4

0x200B2 VT_TSTATE5 VT_LOFS5 VT_TX_AIS5 VT_TX_LOC5

0x200B3 VT_TSTATE6 VT_LOFS6 VT_TX_AIS6 VT_TX_LOC6

0x200B4 VT_TSTATE7 VT_LOFS7 VT_TX_AIS7 VT_TX_LOC7

0x200B5 VT_TSTATE8 VT_LOFS8 VT_TX_AIS8 VT_TX_LOC8

0x200B6 VT_TSTATE9 VT_LOFS9 VT_TX_AIS9 VT_TX_LOC9

0x200B7 VT_TSTATE10 VT_LOFS10 VT_TX_AIS10 VT_TX_LOC10

0x200B8 VT_TSTATE11 VT_LOFS11 VT_TX_AIS11 VT_TX_LOC11

0x200B9 VT_TSTATE12 VT_LOFS12 VT_TX_AIS12 VT_TX_LOC12

0x200BA VT_TSTATE13 VT_LOFS13 VT_TX_AIS13 VT_TX_LOC13

0x200BB VT_TSTATE14 VT_LOFS14 VT_TX_AIS14 VT_TX_LOC14

0x200BC VT_TSTATE15 VT_LOFS15 VT_TX_AIS15 VT_TX_LOC15

0x200BD VT_TSTATE16 VT_LOFS16 VT_TX_AIS16 VT_TX_LOC16

0x200BE VT_TSTATE17 VT_LOFS17 VT_TX_AIS17 VT_TX_LOC17

0x200BF VT_TSTATE18 VT_LOFS18 VT_TX_AIS18 VT_TX_LOC18

0x200C0 VT_TSTATE19 VT_LOFS19 VT_TX_AIS19 VT_TX_LOC19

0x200C1 VT_TSTATE20 VT_LOFS20 VT_TX_AIS20 VT_TX_LOC20

0x200C2 VT_TSTATE21 VT_LOFS21 VT_TX_AIS21 VT_TX_LOC21

0x200C3 VT_TSTATE22 VT_LOFS22 VT_TX_AIS22 VT_TX_LOC22

0x200C4 VT_TSTATE23 VT_LOFS23 VT_TX_AIS23 VT_TX_LOC23

0x200C5 VT_TSTATE24 VT_LOFS24 VT_TX_AIS24 VT_TX_LOC24

0x200C6 VT_TSTATE25 VT_LOFS25 VT_TX_AIS25 VT_TX_LOC25

0x200C7 VT_TSTATE26 VT_LOFS26 VT_TX_AIS26 VT_TX_LOC26

0x200C8 VT_TSTATE27 VT_LOFS27 VT_TX_AIS27 VT_TX_LOC27

0x200C9 VT_TSTATE28 VT_LOFS28 VT_TX_AIS28 VT_TX_LOC28

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

182 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

VT Global Control Parameters—R/W

0x200CA

Page 164 VT_GCTL1 VT_RX_GRP_TYPE[6:0] VT_TX_GRP_TYPE[6:0]

0x200CB

Page 164 VT_GCTL2 VT_LOPS_AIS_INH VT_J2TIM_ERDI_INH VT_J2TIM_RDI_INH VT_J2TIM_AIS_INH VT_LOMF_AIS_INH VT_PLM_AIS_INH VT_UNEQ_AIS_INH VT_UPSR VT_8ORMAJORITY VT_BIT_BLOCK_CNT

0x200CC

Page 165 VT_GCTL3 VT_LOPS_NTIME[3:0] VT_H4_NTIME[3:0]

0x200CD

Page 165 VT_GCTL4 VT_Z6_NTIME[3:0] VT_J2_NTIME[3:0] VT_INV_NTIME[3:0] VT_NDF_NTIME[3:0]

0x200CE

Page 166 VT_GCTL5 VT_APS_NTIME[3:0] VT_LAB_NTIME[3:0] VT_ERDI_NTIME[3:0] VT_RDI_NTIME[3:0]

Signal Degrade Control—R/W

0x200CF

Page 167 VT_SIGDEG_CTL1 VT_SFCLEAR VT_SFSET VT_SDCLEAR VT_SDSET VT_BER_CH_SEL[4:0]

0x200D0

Page 167 VT_SIGDEG_CTL2 VT_SDNSSET[18:3]

0x200D1

Page 167 VT_SIGDEG_CTL3 VT_SDMSET[7:0] VT_SDLSET[3:0] VT_SDNSSET[2:0]

0x200D2

Page 167 VT_SIGDEG_CTL4 VT_SDBSET[15:0]

0x200D3

Page 168 VT_SIGDEG_CTL5 VT_SDNSCLEAR[18:3]

0x200D4

Page 168 VT_SIGDEG_CTL6 VT_SDMCLEAR[7:0] VT_SDLCLEAR[3:0] VT_SDNSCLEAR[2:0]

0x200D5

Page 168 VT_SIGDEG_CTL7 VT_SDBCLEAR[15:0]

Signal Fail Control—R/W

0x200D6

Page 168 VT_SIGFAIL_CTL1 VT_SFNSSET[18:3]

0x200D7

Page 168 VT_SIGFAIL_CTL2 VT_SFMSET[7:0] VT_SFLSET[3:0] VT_SFNSSET[2:0]

0x200D8

Page 168 VT_SIGFAIL_CTL3 VT_SFBSET[15:0]

0x200D9

Page 169 VT_SIGFAIL_CTL4 VT_SFNSCLEAR[18:3]

0x200DA

Page 169 VT_SIGFAIL_CTL5 VT_SFMCLEAR[7:0] VT_SFLCLEAR[3:0] VT_SFNSCLEAR[2:0]

0x200DB

Page 169 VT_SIGFAIL_CTL6 VT_SFBCLEAR[15:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

183Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Control Parameters—R/W

For the following addresses, reference Table 211 on page 170.

0x200DC VT_TCTL1 VT_TX_ERDI_EN1 VT_ERDI_EN1 VT_RDI_EN1 VT_RFI_EN1 VT_REI_EN1 VT_AIS_INS1 VT_TX_CLKEDGE1 VT_LB_SEL1 VT_TX_MAPTYPE(1)[3:0]

0x200DD VT_TCTL2 VT_TX_ERDI_EN2 VT_ERDI_EN2 VT_RDI_EN2 VT_RFI_EN2 VT_REI_EN2 VT_AIS_INS2 VT_TX_CLKEDGE2 VT_LB_SEL2 VT_TX_MAPTYPE(2)[3:0]

0x200DE VT_TCTL3 VT_TX_ERDI_EN3 VT_ERDI_EN3 VT_RDI_EN3 VT_RFI_EN3 VT_REI_EN3 VT_AIS_INS3 VT_TX_CLKEDGE3 VT_LB_SEL3 VT_TX_MAPTYPE(3)[3:0]

0x200DF VT_TCTL4 VT_TX_ERDI_EN4 VT_ERDI_EN4 VT_RDI_EN4 VT_RFI_EN4 VT_REI_EN4 VT_AIS_INS4 VT_TX_CLKEDGE4 VT_LB_SEL4 VT_TX_MAPTYPE(4)[3:0]

0x200E0 VT_TCTL5 VT_TX_ERDI_EN5 VT_ERDI_EN5 VT_RDI_EN5 VT_RFI_EN5 VT_REI_EN5 VT_AIS_INS5 VT_TX_CLKEDGE5 VT_LB_SEL5 VT_TX_MAPTYPE(5)[3:0]

0x200E1 VT_TCTL6 VT_TX_ERDI_EN6 VT_ERDI_EN6 VT_RDI_EN6 VT_RFI_EN6 VT_REI_EN6 VT_AIS_INS6 VT_TX_CLKEDGE6 VT_LB_SEL6 VT_TX_MAPTYPE(6)[3:0]

0x200E2 VT_TCTL7 VT_TX_ERDI_EN7 VT_ERDI_EN7 VT_RDI_EN7 VT_RFI_EN7 VT_REI_EN7 VT_AIS_INS7 VT_TX_CLKEDGE7 VT_LB_SEL7 VT_TX_MAPTYPE(7)[3:0]

0x200E3 VT_TCTL8 VT_TX_ERDI_EN8 VT_ERDI_EN8 VT_RDI_EN8 VT_RFI_EN8 VT_REI_EN8 VT_AIS_INS8 VT_TX_CLKEDGE8 VT_LB_SEL8 VT_TX_MAPTYPE(8)[3:0]

0x200E4 VT_TCTL9 VT_TX_ERDI_EN9 VT_ERDI_EN9 VT_RDI_EN9 VT_RFI_EN9 VT_REI_EN9 VT_AIS_INS9 VT_TX_CLKEDGE9 VT_LB_SEL9 VT_TX_MAPTYPE(9)[3:0]

0x200E5 VT_TCTL10 VT_TX_ERDI_EN10 VT_ERDI_EN10 VT_RDI_EN10 VT_RFI_EN10 VT_REI_EN10 VT_AIS_INS10 VT_TX_CLKEDGE10 VT_LB_SEL10 VT_TX_MAPTYPE(10)[3:0]

0x200E6 VT_TCTL11 VT_TX_ERDI_EN11 VT_ERDI_EN11 VT_RDI_EN11 VT_RFI_EN11 VT_REI_EN11 VT_AIS_INS11 VT_TX_CLKEDGE11 VT_LB_SEL11 VT_TX_MAPTYPE(11)[3:0]

0x200E7 VT_TCTL12 VT_TX_ERDI_EN12 VT_ERDI_EN12 VT_RDI_EN12 VT_RFI_EN12 VT_REI_EN12 VT_AIS_INS12 VT_TX_CLKEDGE12 VT_LB_SEL12 VT_TX_MAPTYPE(12)[3:0]

0x200E8 VT_TCTL13 VT_TX_ERDI_EN13 VT_ERDI_EN13 VT_RDI_EN13 VT_RFI_EN13 VT_REI_EN13 VT_AIS_INS13 VT_TX_CLKEDGE13 VT_LB_SEL13 VT_TX_MAPTYPE(13)[3:0]

0x200E9 VT_TCTL14 VT_TX_ERDI_EN14 VT_ERDI_EN14 VT_RDI_EN14 VT_RFI_EN14 VT_REI_EN14 VT_AIS_INS14 VT_TX_CLKEDGE14 VT_LB_SEL14 VT_TX_MAPTYPE(14)[3:0]

0x200EA VT_TCTL15 VT_TX_ERDI_EN15 VT_ERDI_EN15 VT_RDI_EN15 VT_RFI_EN15 VT_REI_EN15 VT_AIS_INS15 VT_TX_CLKEDGE15 VT_LB_SEL15 VT_TX_MAPTYPE(15)[3:0]

0x200EB VT_TCTL16 VT_TX_ERDI_EN16 VT_ERDI_EN16 VT_RDI_EN16 VT_RFI_EN16 VT_REI_EN16 VT_AIS_INS16 VT_TX_CLKEDGE16 VT_LB_SEL16 VT_TX_MAPTYPE(16)[3:0]

0x200EC VT_TCTL17 VT_TX_ERDI_EN17 VT_ERDI_EN17 VT_RDI_EN17 VT_RFI_EN17 VT_REI_EN17 VT_AIS_INS17 VT_TX_CLKEDGE17 VT_LB_SEL17 VT_TX_MAPTYPE(17)[3:0]

0x200ED VT_TCTL18 VT_TX_ERDI_EN18 VT_ERDI_EN18 VT_RDI_EN18 VT_RFI_EN18 VT_REI_EN18 VT_AIS_INS18 VT_TX_CLKEDGE18 VT_LB_SEL18 VT_TX_MAPTYPE(18)[3:0]

0x200EE VT_TCTL19 VT_TX_ERDI_EN19 VT_ERDI_EN19 VT_RDI_EN19 VT_RFI_EN19 VT_REI_EN19 VT_AIS_INS19 VT_TX_CLKEDGE19 VT_LB_SEL19 VT_TX_MAPTYPE(19)[3:0]

0x200EF VT_TCTL20 VT_TX_ERDI_EN20 VT_ERDI_EN20 VT_RDI_EN20 VT_RFI_EN20 VT_REI_EN20 VT_AIS_INS20 VT_TX_CLKEDGE20 VT_LB_SEL20 VT_TX_MAPTYPE(20)[3:0]

0x200F0 VT_TCTL21 VT_TX_ERDI_EN21 VT_ERDI_EN21 VT_RDI_EN21 VT_RFI_EN21 VT_REI_EN21 VT_AIS_INS21 VT_TX_CLKEDGE21 VT_LB_SEL21 VT_TX_MAPTYPE(21)[3:0]

0x200F1 VT_TCTL22 VT_TX_ERDI_EN22 VT_ERDI_EN22 VT_RDI_EN22 VT_RFI_EN22 VT_REI_EN22 VT_AIS_INS22 VT_TX_CLKEDGE22 VT_LB_SEL22 VT_TX_MAPTYPE(22)[3:0]

0x200F2 VT_TCTL23 VT_TX_ERDI_EN23 VT_ERDI_EN23 VT_RDI_EN23 VT_RFI_EN23 VT_REI_EN23 VT_AIS_INS23 VT_TX_CLKEDGE23 VT_LB_SEL23 VT_TX_MAPTYPE(23)[3:0]

0x200F3 VT_TCTL24 VT_TX_ERDI_EN24 VT_ERDI_EN24 VT_RDI_EN24 VT_RFI_EN24 VT_REI_EN24 VT_AIS_INS24 VT_TX_CLKEDGE24 VT_LB_SEL24 VT_TX_MAPTYPE(24)[3:0]

0x200F4 VT_TCTL25 VT_TX_ERDI_EN25 VT_ERDI_EN25 VT_RDI_EN25 VT_RFI_EN25 VT_REI_EN25 VT_AIS_INS25 VT_TX_CLKEDGE25 VT_LB_SEL25 VT_TX_MAPTYPE(25)[3:0]

0x200F5 VT_TCTL26 VT_TX_ERDI_EN26 VT_ERDI_EN26 VT_RDI_EN26 VT_RFI_EN26 VT_REI_EN26 VT_AIS_INS26 VT_TX_CLKEDGE26 VT_LB_SEL26 VT_TX_MAPTYPE(26)[3:0]

0x200F6 VT_TCTL27 VT_TX_ERDI_EN27 VT_ERDI_EN27 VT_RDI_EN27 VT_RFI_EN27 VT_REI_EN27 VT_AIS_INS27 VT_TX_CLKEDGE27 VT_LB_SEL27 VT_TX_MAPTYPE(27)[3:0]

0x200F7 VT_TCTL28 VT_TX_ERDI_EN28 VT_ERDI_EN28 VT_RDI_EN28 VT_RFI_EN28 VT_REI_EN28 VT_AIS_INS28 VT_TX_CLKEDGE28 VT_LB_SEL28 VT_TX_MAPTYPE(28)[3:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

184 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit TU OH Control Parameters—R/W

For the following addresses, reference Table 212 on page 171.

0x200F8 VT_TTUOH_CTL1 VT_O_INS(1)[1:0] VT_Z7_INS(1)[1:0] VT_Z6_INS(1)[1:0] VT_J2_INS(1)[1:0] VT_V5_INS1 VT_BIP2ERR_INS(1)[1:0]

0x200F9 VT_TTUOH_CTL2 VT_O_INS(2)[1:0] VT_Z7_INS(2)[1:0] VT_Z6_INS(2)[1:0] VT_J2_INS(2)[1:0] VT_V5_INS2 VT_BIP2ERR_INS(2)[1:0]

0x200FA VT_TTUOH_CTL3 VT_O_INS(3)[1:0] VT_Z7_INS(3)[1:0] VT_Z6_INS(3)[1:0] VT_J2_INS(3)[1:0] VT_V5_INS3 VT_BIP2ERR_INS(3)[1:0]

0x200FB VT_TTUOH_CTL4 VT_O_INS(4)[1:0] VT_Z7_INS(4)[1:0] VT_Z6_INS(4)[1:0] VT_J2_INS(4)[1:0] VT_V5_INS4 VT_BIP2ERR_INS(4)[1:0]

0x200FC VT_TTUOH_CTL5 VT_O_INS(5)[1:0] VT_Z7_INS(5)[1:0] VT_Z6_INS(5)[1:0] VT_J2_INS(5)[1:0] VT_V5_INS5 VT_BIP2ERR_INS(5)[1:0]

0x200FD VT_TTUOH_CTL6 VT_O_INS(6)[1:0] VT_Z7_INS(6)[1:0] VT_Z6_INS(6)[1:0] VT_J2_INS(6)[1:0] VT_V5_INS6 VT_BIP2ERR_INS(6)[1:0]

0x200FE VT_TTUOH_CTL7 VT_O_INS(7)[1:0] VT_Z7_INS(7)[1:0] VT_Z6_INS(7)[1:0] VT_J2_INS(7)[1:0] VT_V5_INS7 VT_BIP2ERR_INS(7)[1:0]

0x200FF VT_TTUOH_CTL8 VT_O_INS(8)[1:0] VT_Z7_INS(8)[1:0] VT_Z6_INS(8)[1:0] VT_J2_INS(8)[1:0] VT_V5_INS8 VT_BIP2ERR_INS(8)[1:0]

0x20100 VT_TTUOH_CTL9 VT_O_INS(9)[1:0] VT_Z7_INS(9)[1:0] VT_Z6_INS(9)[1:0] VT_J2_INS(9)[1:0] VT_V5_INS9 VT_BIP2ERR_INS(9)[1:0]

0x20101 VT_TTUOH_CTL10 VT_O_INS(10)[1:0] VT_Z7_INS(10)[1:0] VT_Z6_INS(10)[1:0] VT_J2_INS(10)[1:0] VT_V5_INS10 VT_BIP2ERR_INS(10)[1:0]

0x20102 VT_TTUOH_CTL11 VT_O_INS(11)[1:0] VT_Z7_INS(11)[1:0] VT_Z6_INS(11)[1:0] VT_J2_INS(11)[1:0] VT_V5_INS11 VT_BIP2ERR_INS(11)[1:0]

0x20103 VT_TTUOH_CTL12 VT_O_INS(12)[1:0] VT_Z7_INS(12)[1:0] VT_Z6_INS(12)[1:0] VT_J2_INS(12)[1:0] VT_V5_INS12 VT_BIP2ERR_INS(12)[1:0]

0x20104 VT_TTUOH_CTL13 VT_O_INS(13)[1:0] VT_Z7_INS(13)[1:0] VT_Z6_INS(13)[1:0] VT_J2_INS(13)[1:0] VT_V5_INS13 VT_BIP2ERR_INS(13)[1:0]

0x20105 VT_TTUOH_CTL14 VT_O_INS(14)[1:0] VT_Z7_INS(14)[1:0] VT_Z6_INS(14)[1:0] VT_J2_INS(14)[1:0] VT_V5_INS14 VT_BIP2ERR_INS(14)[1:0]

0x20106 VT_TTUOH_CTL15 VT_O_INS(15)[1:0] VT_Z7_INS(15)[1:0] VT_Z6_INS(15)[1:0] VT_J2_INS(15)[1:0] VT_V5_INS15 VT_BIP2ERR_INS(15)[1:0]

0x20107 VT_TTUOH_CTL16 VT_O_INS(16)[1:0] VT_Z7_INS(16)[1:0] VT_Z6_INS(16)[1:0] VT_J2_INS(16)[1:0] VT_V5_INS16 VT_BIP2ERR_INS(16)[1:0]

0x20108 VT_TTUOH_CTL17 VT_O_INS(17)[1:0] VT_Z7_INS(17)[1:0] VT_Z6_INS(17)[1:0] VT_J2_INS(17)[1:0] VT_V5_INS17 VT_BIP2ERR_INS(17)[1:0]

0x20109 VT_TTUOH_CTL18 VT_O_INS(18)[1:0] VT_Z7_INS(18)[1:0] VT_Z6_INS(18)[1:0] VT_J2_INS(18)[1:0] VT_V5_INS18 VT_BIP2ERR_INS(18)[1:0]

0x2010A VT_TTUOH_CTL19 VT_O_INS(19)[1:0] VT_Z7_INS(19)[1:0] VT_Z6_INS(19)[1:0] VT_J2_INS(19)[1:0] VT_V5_INS19 VT_BIP2ERR_INS(19)[1:0]

0x2010B VT_TTUOH_CTL20 VT_O_INS(20)[1:0] VT_Z7_INS(20)[1:0] VT_Z6_INS(20)[1:0] VT_J2_INS(20)[1:0] VT_V5_INS20 VT_BIP2ERR_INS(20)[1:0]

0x2010C VT_TTUOH_CTL21 VT_O_INS(21)[1:0] VT_Z7_INS(21)[1:0] VT_Z6_INS(21)[1:0] VT_J2_INS(21)[1:0] VT_V5_INS21 VT_BIP2ERR_INS(21)[1:0]

0x2010D VT_TTUOH_CTL22 VT_O_INS(22)[1:0] VT_Z7_INS(22)[1:0] VT_Z6_INS(22)[1:0] VT_J2_INS(22)[1:0] VT_V5_INS22 VT_BIP2ERR_INS(22)[1:0]

0x2010E VT_TTUOH_CTL23 VT_O_INS(23)[1:0] VT_Z7_INS(23)[1:0] VT_Z6_INS(23)[1:0] VT_J2_INS(23)[1:0] VT_V5_INS23 VT_BIP2ERR_INS(23)[1:0]

0x2010F VT_TTUOH_CTL24 VT_O_INS(24)[1:0] VT_Z7_INS(24)[1:0] VT_Z6_INS(24)[1:0] VT_J2_INS(24)[1:0] VT_V5_INS24 VT_BIP2ERR_INS(24)[1:0]

0x20110 VT_TTUOH_CTL25 VT_O_INS(25)[1:0] VT_Z7_INS(25)[1:0] VT_Z6_INS(25)[1:0] VT_J2_INS(25)[1:0] VT_V5_INS25 VT_BIP2ERR_INS(25)[1:0]

0x20111 VT_TTUOH_CTL26 VT_O_INS(26)[1:0] VT_Z7_INS(26)[1:0] VT_Z6_INS(26)[1:0] VT_J2_INS(26)[1:0] VT_V5_INS26 VT_BIP2ERR_INS(26)[1:0]

0x20112 VT_TTUOH_CTL27 VT_O_INS(27)[1:0] VT_Z7_INS(27)[1:0] VT_Z6_INS(27)[1:0] VT_J2_INS(27)[1:0] VT_V5_INS27 VT_BIP2ERR_INS(27)[1:0]

0x20113 VT_TTUOH_CTL28 VT_O_INS(28)[1:0] VT_Z7_INS(28)[1:0] VT_Z6_INS(28)[1:0] VT_J2_INS(28)[1:0] VT_V5_INS28 VT_BIP2ERR_INS(28)[1:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

185Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit APS and Remote Indication—R/W

For the following addresses, reference Table 213 on page 171.

0x20114 VT_TAPSRIVAL1 VT_APS_INS(1)[3:0] VT_ERDI_INS(1)[2:0] VT_RDI_INS1 VT_RFI_INS1

0x20115 VT_TAPSRIVAL2 VT_APS_INS(2)[3:0] VT_ERDI_INS(2)[2:0] VT_RDI_INS2 VT_RFI_INS2

0x20116 VT_TAPSRIVAL3 VT_APS_INS(3)[3:0] VT_ERDI_INS(3)[2:0] VT_RDI_INS3 VT_RFI_INS3

0x20117 VT_TAPSRIVAL4 VT_APS_INS(4)[3:0] VT_ERDI_INS(4)[2:0] VT_RDI_INS4 VT_RFI_INS4

0x20118 VT_TAPSRIVAL5 VT_APS_INS(5)[3:0] VT_ERDI_INS(5)[2:0] VT_RDI_INS5 VT_RFI_INS5

0x20119 VT_TAPSRIVAL6 VT_APS_INS(6)[3:0] VT_ERDI_INS(6)[2:0] VT_RDI_INS6 VT_RFI_INS6

0x2011A VT_TAPSRIVAL7 VT_APS_INS(7)[3:0] VT_ERDI_INS(7)[2:0] VT_RDI_INS7 VT_RFI_INS7

0x2011B VT_TAPSRIVAL8 VT_APS_INS(8)[3:0] VT_ERDI_INS(8)[2:0] VT_RDI_INS8 VT_RFI_INS8

0x2011C VT_TAPSRIVAL9 VT_APS_INS(9)[3:0] VT_ERDI_INS(9)[2:0] VT_RDI_INS9 VT_RFI_INS9

0x2011D VT_TAPSRIVAL10 VT_APS_INS(10)[3:0] VT_ERDI_INS(10)[2:0] VT_RDI_INS10 VT_RFI_INS10

0x2011E VT_TAPSRIVAL11 VT_APS_INS(11)[3:0] VT_ERDI_INS(11)[2:0] VT_RDI_INS11 VT_RFI_INS11

0x2011F VT_TAPSRIVAL12 VT_APS_INS(12)[3:0] VT_ERDI_INS(12)[2:0] VT_RDI_INS12 VT_RFI_INS12

0x20120 VT_TAPSRIVAL13 VT_APS_INS(13)[3:0] VT_ERDI_INS(13)[2:0] VT_RDI_INS13 VT_RFI_INS13

0x20121 VT_TAPSRIVAL14 VT_APS_INS(14)[3:0] VT_ERDI_INS(14)[2:0] VT_RDI_INS14 VT_RFI_INS14

0x20122 VT_TAPSRIVAL15 VT_APS_INS(15)[3:0] VT_ERDI_INS(15)[2:0] VT_RDI_INS15 VT_RFI_INS15

0x20123 VT_TAPSRIVAL16 VT_APS_INS(16)[3:0] VT_ERDI_INS(16)[2:0] VT_RDI_INS16 VT_RFI_INS16

0x20124 VT_TAPSRIVAL17 VT_APS_INS(17)[3:0] VT_ERDI_INS(17)[2:0] VT_RDI_INS17 VT_RFI_INS17

0x20125 VT_TAPSRIVAL18 VT_APS_INS(18)[3:0] VT_ERDI_INS(18)[2:0] VT_RDI_INS18 VT_RFI_INS18

0x20126 VT_TAPSRIVAL19 VT_APS_INS(19)[3:0] VT_ERDI_INS(19)[2:0] VT_RDI_INS19 VT_RFI_INS19

0x20127 VT_TAPSRIVAL20 VT_APS_INS(20)[3:0] VT_ERDI_INS(20)[2:0] VT_RDI_INS20 VT_RFI_INS20

0x20128 VT_TAPSRIVAL21 VT_APS_INS(21)[3:0] VT_ERDI_INS(21)[2:0] VT_RDI_INS21 VT_RFI_INS21

0x20129 VT_TAPSRIVAL22 VT_APS_INS(22)[3:0] VT_ERDI_INS(22)[2:0] VT_RDI_INS22 VT_RFI_INS22

0x2012A VT_TAPSRIVAL23 VT_APS_INS(23)[3:0] VT_ERDI_INS(23)[2:0] VT_RDI_INS23 VT_RFI_INS23

0x2012B VT_TAPSRIVAL24 VT_APS_INS(24)[3:0] VT_ERDI_INS(24)[2:0] VT_RDI_INS24 VT_RFI_INS24

0x2012C VT_TAPSRIVAL25 VT_APS_INS(25)[3:0] VT_ERDI_INS(25)[2:0] VT_RDI_INS25 VT_RFI_INS25

0x2012D VT_TAPSRIVAL26 VT_APS_INS(26)[3:0] VT_ERDI_INS(26)[2:0] VT_RDI_INS26 VT_RFI_INS26

0x2012E VT_TAPSRIVAL27 VT_APS_INS(27)[3:0] VT_ERDI_INS(27)[2:0] VT_RDI_INS27 VT_RFI_INS27

0x2012F VT_TAPSRIVAL28 VT_APS_INS(28)[3:0] VT_ERDI_INS(28)[2:0] VT_RDI_INS28 VT_RFI_INS28

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

186 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Software Overwrite Parameters—R/W

For the following addresses, reference Table 214 on page 171.

0x20130 VT_TSWOW1 VT_OBIT_INS(1)[7:0] VT_Z6BYTE_INS(1)[7:0]

0x20131 VT_TSWOW2 VT_OBIT_INS(2)[7:0] VT_Z6BYTE_INS(2)[7:0]

0x20132 VT_TSWOW3 VT_OBIT_INS(3)[7:0] VT_Z6BYTE_INS(3)[7:0]

0x20133 VT_TSWOW4 VT_OBIT_INS(4)[7:0] VT_Z6BYTE_INS(4)[7:0]

0x20134 VT_TSWOW5 VT_OBIT_INS(5)[7:0] VT_Z6BYTE_INS(5)[7:0]

0x20135 VT_TSWOW6 VT_OBIT_INS(6)[7:0] VT_Z6BYTE_INS(6)[7:0]

0x20136 VT_TSWOW7 VT_OBIT_INS(7)[7:0] VT_Z6BYTE_INS(7)[7:0]

0x20137 VT_TSWOW8 VT_OBIT_INS(8)[7:0] VT_Z6BYTE_INS(8)[7:0]

0x20138 VT_TSWOW9 VT_OBIT_INS(9)[7:0] VT_Z6BYTE_INS(9)[7:0]

0x20139 VT_TSWOW10 VT_OBIT_INS(10)[7:0] VT_Z6BYTE_INS(10)[7:0]

0x2013A VT_TSWOW11 VT_OBIT_INS(11)[7:0] VT_Z6BYTE_INS(11)[7:0]

0x2013B VT_TSWOW12 VT_OBIT_INS(12)[7:0] VT_Z6BYTE_INS(12)[7:0]

0x2013C VT_TSWOW13 VT_OBIT_INS(13)[7:0] VT_Z6BYTE_INS(13)[7:0]

0x2013D VT_TSWOW14 VT_OBIT_INS(14)[7:0] VT_Z6BYTE_INS(14)[7:0]

0x2013E VT_TSWOW15 VT_OBIT_INS(15)[7:0] VT_Z6BYTE_INS(15)[7:0]

0x2013F VT_TSWOW16 VT_OBIT_INS(16)[7:0] VT_Z6BYTE_INS(16)[7:0]

0x20140 VT_TSWOW17 VT_OBIT_INS(17)[7:0] VT_Z6BYTE_INS(17)[7:0]

0x20141 VT_TSWOW18 VT_OBIT_INS(18)[7:0] VT_Z6BYTE_INS(18)[7:0]

0x20142 VT_TSWOW19 VT_OBIT_INS(19)[7:0] VT_Z6BYTE_INS(19)[7:0]

0x20143 VT_TSWOW20 VT_OBIT_INS(20)[7:0] VT_Z6BYTE_INS(20)[7:0]

0x20144 VT_TSWOW21 VT_OBIT_INS(21)[7:0] VT_Z6BYTE_INS(21)[7:0]

0x20145 VT_TSWOW22 VT_OBIT_INS(22)[7:0] VT_Z6BYTE_INS(22)[7:0]

0x20146 VT_TSWOW23 VT_OBIT_INS(23)[7:0] VT_Z6BYTE_INS(23)[7:0]

0x20147 VT_TSWOW24 VT_OBIT_INS(24)[7:0] VT_Z6BYTE_INS(24)[7:0]

0x20148 VT_TSWOW25 VT_OBIT_INS(25)[7:0] VT_Z6BYTE_INS(25)[7:0]

0x20149 VT_TSWOW26 VT_OBIT_INS(26)[7:0] VT_Z6BYTE_INS(26)[7:0]

0x2014A VT_TSWOW27 VT_OBIT_INS(27)[7:0] VT_Z6BYTE_INS(27)[7:0]

0x2014B VT_TSWOW28 VT_OBIT_INS(28)[7:0] VT_Z6BYTE_INS(28)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

187Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Signaling Control Param eters—R/W

For the following addresses, reference Table 215 on page 172.

0x2014C VT_TSIG_CTL1 VT_USE_FBIT1 VT_USE_PBIT1 VT_USE_SBIT1 VT_TXSIG_CH_SEL(1)[4:0]

0x2014D VT_TSIG_CTL2 VT_USE_FBIT2 VT_USE_PBIT2 VT_USE_SBIT2 VT_TXSIG_CH_SEL(2)[4:0]

0x2014E VT_TSIG_CTL3 VT_USE_FBIT3 VT_USE_PBIT3 VT_USE_SBIT3 VT_TXSIG_CH_SEL(3)[4:0]

0x2014F VT_TSIG_CTL4 VT_USE_FBIT4 VT_USE_PBIT4 VT_USE_SBIT4 VT_TXSIG_CH_SEL(4)[4:0]

0x20150 VT_TSIG_CTL5 VT_USE_FBIT5 VT_USE_PBIT5 VT_USE_SBIT5 VT_TXSIG_CH_SEL(5)[4:0]

0x20151 VT_TSIG_CTL6 VT_USE_FBIT6 VT_USE_PBIT6 VT_USE_SBIT6 VT_TXSIG_CH_SEL(6)[4:0]

0x20152 VT_TSIG_CTL7 VT_USE_FBIT7 VT_USE_PBIT7 VT_USE_SBIT7 VT_TXSIG_CH_SEL(7)[4:0]

0x20153 VT_TSIG_CTL8 VT_USE_FBIT8 VT_USE_PBIT8 VT_USE_SBIT8 VT_TXSIG_CH_SEL(8)[4:0]

0x20154 VT_TSIG_CTL9 VT_USE_FBIT9 VT_USE_PBIT9 VT_USE_SBIT9 VT_TXSIG_CH_SEL(9)[4:0]

0x20155 VT_TSIG_CTL10 VT_USE_FBIT10 VT_USE_PBIT10 VT_USE_SBIT10 VT_TXSIG_CH_SEL(10)[4:0]

0x20156 VT_TSIG_CTL11 VT_USE_FBIT11 VT_USE_PBIT11 VT_USE_SBIT11 VT_TXSIG_CH_SEL(11)[4:0]

0x20157 VT_TSIG_CTL12 VT_USE_FBIT12 VT_USE_PBIT12 VT_USE_SBIT12 VT_TXSIG_CH_SEL(12)[4:0]

0x20158 VT_TSIG_CTL13 VT_USE_FBIT13 VT_USE_PBIT13 VT_USE_SBIT13 VT_TXSIG_CH_SEL(13)[4:0]

0x20159 VT_TSIG_CTL14 VT_USE_FBIT14 VT_USE_PBIT14 VT_USE_SBIT14 VT_TXSIG_CH_SEL(14)[4:0]

0x2015A VT_TSIG_CTL15 VT_USE_FBIT15 VT_USE_PBIT15 VT_USE_SBIT15 VT_TXSIG_CH_SEL(15)[4:0]

0x2015B VT_TSIG_CTL16 VT_USE_FBIT16 VT_USE_PBIT16 VT_USE_SBIT16 VT_TXSIG_CH_SEL(16)[4:0]

0x2015C VT_TSIG_CTL17 VT_USE_FBIT17 VT_USE_PBIT17 VT_USE_SBIT17 VT_TXSIG_CH_SEL(17)[4:0]

0x2015D VT_TSIG_CTL18 VT_USE_FBIT18 VT_USE_PBIT18 VT_USE_SBIT18 VT_TXSIG_CH_SEL(18)[4:0]

0x2015E VT_TSIG_CTL19 VT_USE_FBIT19 VT_USE_PBIT19 VT_USE_SBIT19 VT_TXSIG_CH_SEL(19)[4:0]

0x2015F VT_TSIG_CTL20 VT_USE_FBIT20 VT_USE_PBIT20 VT_USE_SBIT20 VT_TXSIG_CH_SEL(20)[4:0]

0x20160 VT_TSIG_CTL21 VT_USE_FBIT21 VT_USE_PBIT21 VT_USE_SBIT21 VT_TXSIG_CH_SEL(21)[4:0]

0x20161 VT_TSIG_CTL22 VT_USE_FBIT22 VT_USE_PBIT22 VT_USE_SBIT22 VT_TXSIG_CH_SEL(22)[4:0]

0x20162 VT_TSIG_CTL23 VT_USE_FBIT23 VT_USE_PBIT23 VT_USE_SBIT23 VT_TXSIG_CH_SEL(23)[4:0]

0x20163 VT_TSIG_CTL24 VT_USE_FBIT24 VT_USE_PBIT24 VT_USE_SBIT24 VT_TXSIG_CH_SEL(24)[4:0]

0x20164 VT_TSIG_CTL25 VT_USE_FBIT25 VT_USE_PBIT25 VT_USE_SBIT25 VT_TXSIG_CH_SEL(25)[4:0]

0x20165 VT_TSIG_CTL26 VT_USE_FBIT26 VT_USE_PBIT26 VT_USE_SBIT26 VT_TXSIG_CH_SEL(26)[4:0]

0x20166 VT_TSIG_CTL27 VT_USE_FBIT27 VT_USE_PBIT27 VT_USE_SBIT27 VT_TXSIG_CH_SEL(27)[4:0]

0x20167 VT_TSIG_CTL28 VT_USE_FBIT28 VT_USE_PBIT28 VT_USE_SBIT28 VT_TXSIG_CH_SEL(28)[4:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

188 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 216 on page 172.

Channel 1 Transmit J2 Value Parameters—R/W

0x20168

—

0x20177

VT_J2BYTE_INS_R[1][1]

—

VT_J2BYTE_INS_R[1][16]

VT_J2BYTE_INS(1)(1)[7:0]

—

VT_J2BYTE_INS(1)(16)[7:0]

Channel 2 Transmit J2 Value Parameters—R/W

0x20178

—

0x20187

VT_J2BYTE_INS_R[2][1]

—

VT_J2BYTE_INS_R[2][16]

VT_J2BYTE_INS(2)(1)[7:0]

—

VT_J2BYTE_INS(2)(16)[7:0]

Channel 3 Transmit J2 Value Parameters—R/W

0x20188

—

0x20197

VT_J2BYTE_INS_R[3][1]

—

VT_J2BYTE_INS_R[3][16]

VT_J2BYTE_INS(3)(1)[7:0]

—

VT_J2BYTE_INS(3)(16)[7:0]

Channel 4 Transmit J2 Value Parameters—R/W

0x20198

—

0x201A7

VT_J2BYTE_INS_R[4][1]

—

VT_J2BYTE_INS_R[4][16]

VT_J2BYTE_INS(4)(1)[7:0]

—

VT_J2BYTE_INS(4)(16)[7:0]

Channel 5 Transmit J2 Value Parameters—R/W

0x201A8

—

0x201B7

VT_J2BYTE_INS_R[5][1]

—

VT_J2BYTE_INS_R[5][16]

VT_J2BYTE_INS(5)(1)[7:0]

—

VT_J2BYTE_INS(5)(16)[7:0]

Channel 6 Transmit J2 Value Parameters—R/W

0x201B8

—

0x201C7

VT_J2BYTE_INS_R[6][1]

—

VT_J2BYTE_INS_R[6][16]

VT_J2BYTE_INS(6)(1)[7:0]

—

VT_J2BYTE_INS(6)(16)[7:0]

Channel 7 Transmit J2 Value Parameters—R/W

0x201C8

—

0x201D7

VT_J2BYTE_INS_R[7][1]

—

VT_J2BYTE_INS_R[7][16]

VT_J2BYTE_INS(7)(1)[7:0]

—

VT_J2BYTE_INS(7)(16)[7:0]

Channel 8 Transmit J2 Value Parameters—R/W

0x201D8

—

0x201E7

VT_J2BYTE_INS_R[8][1]

—

VT_J2BYTE_INS_R[8][16]

VT_J2BYTE_INS(8)(1)[7:0]

—

VT_J2BYTE_INS(8)(16)[7:0]

Channel 9 Transmit J2 Value Parameters—R/W

0x201E8

—

0x201F7

VT_J2BYTE_INS_R[9][1]

—

VT_J2BYTE_INS_R[9][16]

VT_J2BYTE_INS(9)(1)[7:0]

—

VT_J2BYTE_INS(9)(16)[7:0]

Channel 10 Transmit J2 Value Parame ters—R/W

0x201F8

—

0x20207

VT_J2BYTE_INS_R[10][1]

—

VT_J2BYTE_INS_R[10][16]

VT_J2BYTE_INS(10)(1)[7:0]

—

VT_J2BYTE_INS(10)(16)[7:0]

Channel 11 Transmit J2 Value Parameters—R/W

0x20208

—

0x20217

VT_J2BYTE_INS_R[11][1]

—

VT_J2BYTE_INS_R[11][16]

VT_J2BYTE_INS(11)(1)[7:0]

—

VT_J2BYTE_INS(11)(16)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

189Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 216 on page 172.

Channel 12 Transmit J2 Value Parameters—R/W

0x20218

—

0x20227

VT_J2BYTE_INS_R[12][1]

—

VT_J2BYTE_INS_R[12][16]

VT_J2BYTE_INS(12)(1)[7:0]

—

VT_J2BYTE_INS(12)(16)[7:0]

Channel 13 Transmit J2 Value Parameters—R/W

0x20228

—

0x20237

VT_J2BYTE_INS_R[13][1]

—

VT_J2BYTE_INS_R[13][16]

VT_J2BYTE_INS(13)(1)[7:0]

—

VT_J2BYTE_INS(13)(16)[7:0]

Channel 14 Transmit J2 Value Parameters—R/W

0x20238

—

0x20247

VT_J2BYTE_INS_R[14][1]

—

VT_J2BYTE_INS_R[14][16]

VT_J2BYTE_INS(14)(1)[7:0]

—

VT_J2BYTE_INS(14)(16)[7:0]

Channel 15 Transmit J2 Value Parameters—R/W

0x20248

—

0x20257

VT_J2BYTE_INS_R[15][1]

—

VT_J2BYTE_INS_R[15][16]

VT_J2BYTE_INS(15)(1)[7:0]

—

VT_J2BYTE_INS(15)(16)[7:0]

Channel 16 Transmit J2 Value Parameters—R/W

0x20258

—

0x20267

VT_J2BYTE_INS_R[16][1]

—

VT_J2BYTE_INS_R[16][16]

VT_J2BYTE_INS(16)(1)[7:0]

—

VT_J2BYTE_INS(16)(16)[7:0]

Channel 17 Transmit J2 Value Parameters—R/W

0x20268

—

0x20277

VT_J2BYTE_INS_R[17][1]

—

VT_J2BYTE_INS_R[17][16]

VT_J2BYTE_INS(17)(1)[7:0]

—

VT_J2BYTE_INS(17)(16)[7:0]

Channel 18 Transmit J2 Value Parameters—R/W

0x20278

—

0x20287

VT_J2BYTE_INS_R[18][1]

—

VT_J2BYTE_INS_R[18][16]

VT_J2BYTE_INS(18)(1)[7:0]

—

VT_J2BYTE_INS(18)(16)[7:0]

Channel 19 Transmit J2 Value Parameters—R/W

0x20288

—

0x20297

VT_J2BYTE_INS_R[19][1]

—

VT_J2BYTE_INS_R[19][16]

VT_J2BYTE_INS(19)(1)[7:0]

—

VT_J2BYTE_INS(19)(16)[7:0]

Channel 20 Transmit J2 Value Parameters—R/W

0x20298

—

0x202A7

VT_J2BYTE_INS_R[20][1]

—

VT_J2BYTE_INS_R[20][16]

VT_J2BYTE_INS(20)(1)[7:0]

—

VT_J2BYTE_INS(20)(16)[7:0]

Channel 21 Transmit J2 Value Parameters—R/W

0x202A8

—

0x202B7

VT_J2BYTE_INS_R[21][1]

—

VT_J2BYTE_INS_R[21][16]

VT_J2BYTE_INS(21)(1)[7:0]

—

VT_J2BYTE_INS(21)(16)[7:0]

Channel 22 Transmit J2 Value Parameters—R/W

0x202B8

—

0x202C7

VT_J2BYTE_INS_R[22][1]

—

VT_J2BYTE_INS_R[22][16]

VT_J2BYTE_INS(22)(1)[7:0]

—

VT_J2BYTE_INS(22)(16)[7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

190 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 216 on page 172.

Channel 23 Transmit J2 Value Parame ters—R/W

0x202C8

—

0x202D7

VT_J2BYTE_INS_R[23][1]

—

VT_J2BYTE_INS_R[23][16]

VT_J2BYTE_INS(23)(1)[7:0]

—

VT_J2BYTE_INS(23)(16)[7:0]

Channel 24 Transmit J2 Value Parame ters—R/W

0x202D8

—

0x202E7

VT_J2BYTE_INS_R[24][1]

—

VT_J2BYTE_INS_R[24][16]

VT_J2BYTE_INS(24)(1)[7:0]

—

VT_J2BYTE_INS(24)(16)[7:0]

Channel 25 Transmit J2 Value Parame ters—R/W

0x202E8

—

0x202F7

VT_J2BYTE_INS_R[25][1]

—

VT_J2BYTE_INS_R[25][16]

VT_J2BYTE_INS(25)(1)[7:0]

—

VT_J2BYTE_INS(25)(16)[7:0]

Channel 26 Transmit J2 Value Parame ters—R/W

0x202F8

—

0x20307

VT_J2BYTE_INS_R[26][1]

—

VT_J2BYTE_INS_R[26][16]

VT_J2BYTE_INS(26)(1)[7:0]

—

VT_J2BYTE_INS(26)(16)[7:0]

Channel 27 Transmit J2 Value Parame ters—R/W

0x20308

—

0x20317

VT_J2BYTE_INS_R[27][1]

—

VT_J2BYTE_INS_R[27][16]

VT_J2BYTE_INS(27)(1)[7:0]

—

VT_J2BYTE_INS(27)(16)[7:0]

Channel 28 Transmit J2 Value Parame ters—R/W

0x20318

—

0x20327

VT_J2BYTE_INS[28][1]

—

VT_J2BYTE_INS[28][16]

VT_J2BYTE_INS(28)(1)[7:0]

—

VT_J2BYTE_INS(28)(16)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

191Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive Control Parameters—R/W

For the following addresses, reference Table 217 on page 172.

0x20328 VT_RCTL1 VT_SF_ESF1 VT_WR_FBIT1 VT_SYNC_PBIT1 VT_RXSIG_CH_SEL(1)[4:0] VT_J2MON_MODE(1)[2:0] VT_RX_ERDI_EN1 VT_RX_MAPTYPE(1)[3:0]

0x20329 VT_RCTL2 VT_SF_ESF2 VT_WR_FBIT2 VT_SYNC_PBIT2 VT_RXSIG_CH_SEL(2)[4:0] VT_J2MON_MODE(2)[2:0] VT_RX_ERDI_EN2 VT_RX_MAPTYPE(2)[3:0]

0x2032A VT_RCTL3 VT_SF_ESF3 VT_WR_FBIT3 VT_SYNC_PBIT3 VT_RXSIG_CH_SEL(3)[4:0] VT_J2MON_MODE(3)[2:0] VT_RX_ERDI_EN3 VT_RX_MAPTYPE(3)[3:0]

0x2032B VT_RCTL4 VT_SF_ESF4 VT_WR_FBIT4 VT_SYNC_PBIT4 VT_RXSIG_CH_SEL(4)[4:0] VT_J2MON_MODE(4)[2:0] VT_RX_ERDI_EN4 VT_RX_MAPTYPE(4)[3:0]

0x2032C VT_RCTL5 VT_SF_ESF5 VT_WR_FBIT5 VT_SYNC_PBIT5 VT_RXSIG_CH_SEL(5)[4:0] VT_J2MON_MODE(5)[2:0] VT_RX_ERDI_EN5 VT_RX_MAPTYPE(5)[3:0]

0x2032D VT_RCTL6 VT_SF_ESF6 VT_WR_FBIT6 VT_SYNC_PBIT6 VT_RXSIG_CH_SEL(6)[4:0] VT_J2MON_MODE(6)[2:0] VT_RX_ERDI_EN6 VT_RX_MAPTYPE(6)[3:0]

0x2032E VT_RCTL7 VT_SF_ESF7 VT_WR_FBIT7 VT_SYNC_PBIT7 VT_RXSIG_CH_SEL(7)[4:0] VT_J2MON_MODE(7)[2:0] VT_RX_ERDI_EN7 VT_RX_MAPTYPE(7)[3:0]

0x2032F VT_RCTL8 VT_SF_ESF8 VT_WR_FBIT8 VT_SYNC_PBIT8 VT_RXSIG_CH_SEL(8)[4:0] VT_J2MON_MODE(8)[2:0] VT_RX_ERDI_EN8 VT_RX_MAPTYPE(8)[3:0]

0x20330 VT_RCTL9 VT_SF_ESF9 VT_WR_FBIT9 VT_SYNC_PBIT9 VT_RXSIG_CH_SEL(9)[4:0] VT_J2MON_MODE(9)[2:0] VT_RX_ERDI_EN9 VT_RX_MAPTYPE(9)[3:0]

0x20331 VT_RCTL10 VT_SF_ESF10 VT_WR_FBIT10 VT_SYNC_PBIT10 VT_RXSIG_CH_SEL(10)[4:0] VT_J2MON_MODE(10)[2:0] VT_RX_ERDI_EN10 VT_RX_MAPTYPE(10)[3:0]

0x20332 VT_RCTL11 VT_SF_ESF11 VT_WR_FBIT11 VT_SYNC_PBIT11 VT_RXSIG_CH_SEL(11)[4:0] VT_J2MON_MODE(11)[2:0] VT_RX_ERDI_EN11 VT_RX_MAPTYPE(11)[3:0]

0x20333 VT_RCTL12 VT_SF_ESF12 VT_WR_FBIT12 VT_SYNC_PBIT12 VT_RXSIG_CH_SEL(12)[4:0] VT_J2MON_MODE(12)[2:0] VT_RX_ERDI_EN12 VT_RX_MAPTYPE(12)[3:0]

0x20334 VT_RCTL13 VT_SF_ESF13 VT_WR_FBIT13 VT_SYNC_PBIT13 VT_RXSIG_CH_SEL(13)[4:0] VT_J2MON_MODE(13)[2:0] VT_RX_ERDI_EN13 VT_RX_MAPTYPE(13)[3:0]

0x20335 VT_RCTL14 VT_SF_ESF14 VT_WR_FBIT14 VT_SYNC_PBIT14 VT_RXSIG_CH_SEL(14)[4:0] VT_J2MON_MODE(14)[2:0] VT_RX_ERDI_EN14 VT_RX_MAPTYPE(14)[3:0]

0x20336 VT_RCTL15 VT_SF_ESF15 VT_WR_FBIT15 VT_SYNC_PBIT15 VT_RXSIG_CH_SEL(15)[4:0] VT_J2MON_MODE(15)[2:0] VT_RX_ERDI_EN15 VT_RX_MAPTYPE(15)[3:0]

0x20337 VT_RCTL16 VT_SF_ESF16 VT_WR_FBIT16 VT_SYNC_PBIT16 VT_RXSIG_CH_SEL(16)[4:0] VT_J2MON_MODE(16)[2:0] VT_RX_ERDI_EN16 VT_RX_MAPTYPE(16)[3:0]

0x20338 VT_RCTL17 VT_SF_ESF17 VT_WR_FBIT17 VT_SYNC_PBIT17 VT_RXSIG_CH_SEL(17)[4:0] VT_J2MON_MODE(17)[2:0] VT_RX_ERDI_EN17 VT_RX_MAPTYPE(17)[3:0]

0x20339 VT_RCTL18 VT_SF_ESF18 VT_WR_FBIT18 VT_SYNC_PBIT18 VT_RXSIG_CH_SEL(18)[4:0] VT_J2MON_MODE(18)[2:0] VT_RX_ERDI_EN18 VT_RX_MAPTYPE(18)[3:0]

0x2033A VT_RCTL19 VT_SF_ESF19 VT_WR_FBIT19 VT_SYNC_PBIT19 VT_RXSIG_CH_SEL(19)[4:0] VT_J2MON_MODE(19)[2:0] VT_RX_ERDI_EN19 VT_RX_MAPTYPE(19)[3:0]

0x2033B VT_RCTL20 VT_SF_ESF20 VT_WR_FBIT20 VT_SYNC_PBIT20 VT_RXSIG_CH_SEL(20)[4:0] VT_J2MON_MODE(20)[2:0] VT_RX_ERDI_EN20 VT_RX_MAPTYPE(20)[3:0]

0x2033C VT_RCTL21 VT_SF_ESF21 VT_WR_FBIT21 VT_SYNC_PBIT21 VT_RXSIG_CH_SEL(21)[4:0] VT_J2MON_MODE(21)[2:0] VT_RX_ERDI_EN21 VT_RX_MAPTYPE(21)[3:0]

0x2033D VT_RCTL22 VT_SF_ESF22 VT_WR_FBIT22 VT_SYNC_PBIT22 VT_RXSIG_CH_SEL(22)[4:0] VT_J2MON_MODE(22)[2:0] VT_RX_ERDI_EN22 VT_RX_MAPTYPE(22)[3:0]

0x2033E VT_RCTL23 VT_SF_ESF23 VT_WR_FBIT23 VT_SYNC_PBIT23 VT_RXSIG_CH_SEL(23)[4:0] VT_J2MON_MODE(23)[2:0] VT_RX_ERDI_EN23 VT_RX_MAPTYPE(23)[3:0]

0x2033F VT_RCTL24 VT_SF_ESF24 VT_WR_FBIT24 VT_SYNC_PBIT24 VT_RXSIG_CH_SEL(24)[4:0] VT_J2MON_MODE(24)[2:0] VT_RX_ERDI_EN24 VT_RX_MAPTYPE(24)[3:0]

0x20340 VT_RCTL25 VT_SF_ESF25 VT_WR_FBIT25 VT_SYNC_PBIT25 VT_RXSIG_CH_SEL(25)[4:0] VT_J2MON_MODE(25)[2:0] VT_RX_ERDI_EN25 VT_RX_MAPTYPE(25)[3:0]

0x20341 VT_RCTL26 VT_SF_ESF26 VT_WR_FBIT26 VT_SYNC_PBIT26 VT_RXSIG_CH_SEL(26)[4:0] VT_J2MON_MODE(26)[2:0] VT_RX_ERDI_EN26 VT_RX_MAPTYPE(26)[3:0]

0x20342 VT_RCTL27 VT_SF_ESF27 VT_WR_FBIT27 VT_SYNC_PBIT27 VT_RXSIG_CH_SEL(27)[4:0] VT_J2MON_MODE(27)[2:0] VT_RX_ERDI_EN27 VT_RX_MAPTYPE(27)[3:0]

0x20343 VT_RCTL28 VT_SF_ESF28 VT_WR_FBIT28 VT_SYNC_PBIT28 VT_RXSIG_CH_SEL(28)[4:0] VT_J2MON_MODE(28)[2:0] VT_RX_ERDI_EN28 VT_RX_MAPTYPE(28)[3:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

192 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive TU Overhead—RO

For the following addresses, reference Table 218 on page 173.

0x20344 VT_RTUOH_CTL1 VT_Z6_BYTE(1)[7:0] VT_OBITS(1)[7:0]

0x20345 VT_RTUOH_CTL2 VT_Z6_BYTE(2)[7:0] VT_OBITS(2)[7:0]

0x20346 VT_RTUOH_CTL3 VT_Z6_BYTE(3)[7:0] VT_OBITS(3)[7:0]

0x20347 VT_RTUOH_CTL4 VT_Z6_BYTE(4)[7:0] VT_OBITS(4)[7:0]

0x20348 VT_RTUOH_CTL5 VT_Z6_BYTE(5)[7:0] VT_OBITS(5)[7:0]

0x20349 VT_RTUOH_CTL6 VT_Z6_BYTE(6)[7:0] VT_OBITS(6)[7:0]

0x2034A VT_RTUOH_CTL7 VT_Z6_BYTE(7)[7:0] VT_OBITS(7)[7:0]

0x2034B VT_RTUOH_CTL8 VT_Z6_BYTE(8)[7:0] VT_OBITS(8)[7:0]

0x2034C VT_RTUOH_CTL9 VT_Z6_BYTE(9)[7:0] VT_OBITS(9)[7:0]

0x2034D VT_RTUOH_CTL10 VT_Z6_BYTE(10)[7:0] VT_OBITS(10)[7:0]

0x2034E VT_RTUOH_CTL11 VT_Z6_BYTE(11)[7:0] VT_OBITS(11)[7:0]

0x2034F VT_RTUOH_CTL12 VT_Z6_BYTE(12)[7:0] VT_OBITS(12)[7:0]

0x20350 VT_RTUOH_CTL13 VT_Z6_BYTE(13)[7:0] VT_OBITS(13)[7:0]

0x20351 VT_RTUOH_CTL14 VT_Z6_BYTE(14)[7:0] VT_OBITS(14)[7:0]

0x20352 VT_RTUOH_CTL15 VT_Z6_BYTE(15)[7:0] VT_OBITS(15)[7:0]

0x20353 VT_RTUOH_CTL16 VT_Z6_BYTE(16)[7:0] VT_OBITS(16)[7:0]

0x20354 VT_RTUOH_CTL17 VT_Z6_BYTE(17)[7:0] VT_OBITS(17)[7:0]

0x20355 VT_RTUOH_CTL18 VT_Z6_BYTE(18)[7:0] VT_OBITS(18)[7:0]

0x20356 VT_RTUOH_CTL19 VT_Z6_BYTE(19)[7:0] VT_OBITS(19)[7:0]

0x20357 VT_RTUOH_CTL20 VT_Z6_BYTE(20)[7:0] VT_OBITS(20)[7:0]

0x20358 VT_RTUOH_CTL21 VT_Z6_BYTE(21)[7:0] VT_OBITS(21)[7:0]

0x20359 VT_RTUOH_CTL22 VT_Z6_BYTE(22)[7:0] VT_OBITS(22)[7:0]

0x2035A VT_RTUOH_CTL23 VT_Z6_BYTE(23)[7:0] VT_OBITS(23)[7:0]

0x2035B VT_RTUOH_CTL24 VT_Z6_BYTE(24)[7:0] VT_OBITS(24)[7:0]

0x2035C VT_RTUOH_CTL25 VT_Z6_BYTE(25)[7:0] VT_OBITS(25)[7:0]

0x2035D VT_RTUOH_CTL26 VT_Z6_BYTE(26)[7:0] VT_OBITS(26)[7:0]

0x2035E VT_RTUOH_CTL27 VT_Z6_BYTE(27)[7:0] VT_OBITS(27)[7:0]

0x2035F VT_RTUOH_CTL28 VT_Z6_BYTE(28)[7:0] VT_OBITS(28)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

193Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive BIP-2 Error Count Values—RO

For the following addresses, reference Table 219 on page 173.

0x20360 VT_RBIP2_CNT1 VT_BIP2ERR_CNT(1)[11:0]

0x20361 VT_RBIP2_CNT2 VT_BIP2ERR_CNT(2)[11:0]

0x20362 VT_RBIP2_CNT3 VT_BIP2ERR_CNT(3)[11:0]

0x20363 VT_RBIP2_CNT4 VT_BIP2ERR_CNT(4)[11:0]

0x20364 VT_RBIP2_CNT5 VT_BIP2ERR_CNT(5)[11:0]

0x20365 VT_RBIP2_CNT6 VT_BIP2ERR_CNT(6)[11:0]

0x20366 VT_RBIP2_CNT7 VT_BIP2ERR_CNT(7)[11:0]

0x20367 VT_RBIP2_CNT8 VT_BIP2ERR_CNT(8)[11:0]

0x20368 VT_RBIP2_CNT9 VT_BIP2ERR_CNT(9)[11:0]

0x20369 VT_RBIP2_CNT10 VT_BIP2ERR_CNT(10)[11:0]

0x2036A VT_RBIP2_CNT11 VT_BIP2ERR_CNT(11)[11:0]

0x2036B VT_RBIP2_CNT12 VT_BIP2ERR_CNT(12)[11:0]

0x2036C VT_RBIP2_CNT13 VT_BIP2ERR_CNT(13)[11:0]

0x2036D VT_RBIP2_CNT14 VT_BIP2ERR_CNT(14)[11:0]

0x2036E VT_RBIP2_CNT15 VT_BIP2ERR_CNT(15)[11:0]

0x2036F VT_RBIP2_CNT16 VT_BIP2ERR_CNT(16)[11:0]

0x20370 VT_RBIP2_CNT17 VT_BIP2ERR_CNT(17)[11:0]

0x20371 VT_RBIP2_CNT18 VT_BIP2ERR_CNT(18)[11:0]

0x20372 VT_RBIP2_CNT19 VT_BIP2ERR_CNT(19)[11:0]

0x20373 VT_RBIP2_CNT20 VT_BIP2ERR_CNT(20)[11:0]

0x20374 VT_RBIP2_CNT21 VT_BIP2ERR_CNT(21)[11:0]

0x20375 VT_RBIP2_CNT22 VT_BIP2ERR_CNT(22)[11:0]

0x20376 VT_RBIP2_CNT23 VT_BIP2ERR_CNT(23)[11:0]

0x20377 VT_RBIP2_CNT24 VT_BIP2ERR_CNT(24)[11:0]

0x20378 VT_RBIP2_CNT25 VT_BIP2ERR_CNT(25)[11:0]

0x20379 VT_RBIP2_CNT26 VT_BIP2ERR_CNT(26)[11:0]

0x2037A VT_RBIP2_CNT27 VT_BIP2ERR_CNT(27)[11:0]

0x2037B VT_RBIP2_CNT28 VT_BIP2ERR_CNT(28)[11:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

194 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive REI-V Count Values—RO

For the following addresses, reference Table 220 on page 173.

0x2037C VT_RREIV_CNT1 VT_REI_CNT(1)[10:0]

0x2037D VT_RREIV_CNT2 VT_REI_CNT(2)[10:0]

0x2037E VT_RREIV_CNT3 VT_REI_CNT(3)[10:0]

0x2037F VT_RREIV_CNT4 VT_REI_CNT(4)[10:0]

0x20380 VT_RREIV_CNT5 VT_REI_CNT(5)[10:0]

0x20381 VT_RREIV_CNT6 VT_REI_CNT(6)[10:0]

0x20382 VT_RREIV_CNT7 VT_REI_CNT(7)[10:0]

0x20383 VT_RREIV_CNT8 VT_REI_CNT(8)[10:0]

0x20384 VT_RREIV_CNT9 VT_REI_CNT(9)[10:0]

0x20385 VT_RREIV_CNT10 VT_REI_CNT(10)[10:0]

0x20386 VT_RREIV_CNT11 VT_REI_CNT(11)[10:0]

0x20387 VT_RREIV_CNT12 VT_REI_CNT(12)[10:0]

0x20388 VT_RREIV_CNT13 VT_REI_CNT(13)[10:0]

0x20389 VT_RREIV_CNT14 VT_REI_CNT(14)[10:0]

0x2038A VT_RREIV_CNT15 VT_REI_CNT(15)[10:0]

0x2038B VT_RREIV_CNT16 VT_REI_CNT(16)[10:0]

0x2038C VT_RREIV_CNT17 VT_REI_CNT(17)[10:0]

0x2038D VT_RREIV_CNT18 VT_REI_CNT(18)[10:0]

0x2038E VT_RREIV_CNT19 VT_REI_CNT(19)[10:0]

0x2038F VT_RREIV_CNT20 VT_REI_CNT(20)[10:0]

0x20390 VT_RREIV_CNT21 VT_REI_CNT(21)[10:0]

0x20391 VT_RREIV_CNT22 VT_REI_CNT(22)[10:0]

0x20392 VT_RREIV_CNT23 VT_REI_CNT(23)[10:0]

0x20393 VT_RREIV_CNT24 VT_REI_CNT(24)[10:0]

0x20394 VT_RREIV_CNT25 VT_REI_CNT(25)[10:0]

0x20395 VT_RREIV_CNT26 VT_REI_CNT(26)[10:0]

0x20396 VT_RREIV_CNT27 VT_REI_CNT(27)[10:0]

0x20397 VT_RREIV_CNT28 VT_REI_CNT(28)[10:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

195Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive VT Pointer and Count Values—RO

For the following addresses, reference Table 221 on page 174.

0x20398 VT_RPTR_CNT1 VT_STORED_PTR(1)[7:0] VT_PTR_DEC(1)[3:0] VT_PTR_INC(1)[3:0]

0x20399 VT_RPTR_CNT2 VT_STORED_PTR(2)[7:0] VT_PTR_DEC(2)[3:0] VT_PTR_INC(2)[3:0]

0x2039A VT_RPTR_CNT3 VT_STORED_PTR(3)[7:0] VT_PTR_DEC(3)[3:0] VT_PTR_INC(3)[3:0]

0x2039B VT_RPTR_CNT4 VT_STORED_PTR(4)[7:0] VT_PTR_DEC(4)[3:0] VT_PTR_INC(4)[3:0]

0x2039C VT_RPTR_CNT5 VT_STORED_PTR(5)[7:0] VT_PTR_DEC(5)[3:0] VT_PTR_INC(5)[3:0]

0x2039D VT_RPTR_CNT6 VT_STORED_PTR(6)[7:0] VT_PTR_DEC(6)[3:0] VT_PTR_INC(6)[3:0]

0x2039E VT_RPTR_CNT7 VT_STORED_PTR(7)[7:0] VT_PTR_DEC(7)[3:0] VT_PTR_INC(7)[3:0]

0x2039F VT_RPTR_CNT8 VT_STORED_PTR(8)[7:0] VT_PTR_DEC(8)[3:0] VT_PTR_INC(8)[3:0]

0x203A0 VT_RPTR_CNT9 VT_STORED_PTR(9)[7:0] VT_PTR_DEC(9)[3:0] VT_PTR_INC(9)[3:0]

0x203A1 VT_RPTR_CNT10 VT_STORED_PTR(10)[7:0] VT_PTR_DEC(10)[3:0] VT_PTR_INC(10)[3:0]

0x203A2 VT_RPTR_CNT11 VT_STORED_PTR(11)[7:0] VT_PTR_DEC(11)[3:0] VT_PTR_INC(11)[3:0]

0x203A3 VT_RPTR_CNT12 VT_STORED_PTR(12)[7:0] VT_PTR_DEC(12)[3:0] VT_PTR_INC(12)[3:0]

0x203A4 VT_RPTR_CNT13 VT_STORED_PTR(13)[7:0] VT_PTR_DEC(13)[3:0] VT_PTR_INC(13)[3:0]

0x203A5 VT_RPTR_CNT14 VT_STORED_PTR(14)[7:0] VT_PTR_DEC(14)[3:0] VT_PTR_INC(14)[3:0]

0x203A6 VT_RPTR_CNT15 VT_STORED_PTR(15)[7:0] VT_PTR_DEC(15)[3:0] VT_PTR_INC(15)[3:0]

0x203A7 VT_RPTR_CNT16 VT_STORED_PTR(16)[7:0] VT_PTR_DEC(16)[3:0] VT_PTR_INC(16)[3:0]

0x203A8 VT_RPTR_CNT17 VT_STORED_PTR(17)[7:0] VT_PTR_DEC(17)[3:0] VT_PTR_INC(17)[3:0]

0x203A9 VT_RPTR_CNT18 VT_STORED_PTR(18)[7:0] VT_PTR_DEC(18)[3:0] VT_PTR_INC(18)[3:0]

0x203AA VT_RPTR_CNT19 VT_STORED_PTR(19)[7:0] VT_PTR_DEC(19)[3:0] VT_PTR_INC(19)[3:0]

0x203AB VT_RPTR_CNT20 VT_STORED_PTR(20)[7:0] VT_PTR_DEC(20)[3:0] VT_PTR_INC(20)[3:0]

0x203AC VT_RPTR_CNT21 VT_STORED_PTR(21)[7:0] VT_PTR_DEC(21)[3:0] VT_PTR_INC(21)[3:0]

0x203AD VT_RPTR_CNT22 VT_STORED_PTR(22)[7:0] VT_PTR_DEC(22)[3:0] VT_PTR_INC(22)[3:0]

0x203AE VT_RPTR_CNT23 VT_STORED_PTR(23)[7:0] VT_PTR_DEC(23)[3:0] VT_PTR_INC(23)[3:0]

0x203AF VT_RPTR_CNT24 VT_STORED_PTR(24)[7:0] VT_PTR_DEC(24)[3:0] VT_PTR_INC(24)[3:0]

0x203B0 VT_RPTR_CNT25 VT_STORED_PTR(25)[7:0] VT_PTR_DEC(25)[3:0] VT_PTR_INC(25)[3:0]

0x203B1 VT_RPTR_CNT26 VT_STORED_PTR(26)[7:0] VT_PTR_DEC(26)[3:0] VT_PTR_INC(26)[3:0]

0x203B2 VT_RPTR_CNT27 VT_STORED_PTR(27)[7:0] VT_PTR_DEC(27)[3:0] VT_PTR_INC(27)[3:0]

0x203B3 VT_RPTR_CNT28 VT_STORED_PTR(28)[7:0] VT_PTR_DEC(28)[3:0] VT_PTR_INC(28)[3:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

196 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 222 on page 174.

Channel 1 Receive J2 Expected/Monitor Values—R/W, RO

0x203B4

—

0x203C3

VT_J2BYTE_EXP_R[1][1]

—

VT_J2BYTE_EXP_R[1][16]

VT_J2BYTE_EXP(1)(1)[7:0]

—

VT_J2BYTE_EXP(1)(16)[7:0]

VT_J2BYTE_DET(1)(1)[7:0]

—

VT_J2BYTE_DET(1)(16)[7:0]

Channel 2 Receive J2 Expected/Monitor Values—R/W, RO

0x203C4

—

0x203D3

VT_J2BYTE_EXP_R[2][1]

—

VT_J2BYTE_EXP_R[2][16]

VT_J2BYTE_EXP(2)(1)[7:0]

—

VT_J2BYTE_EXP(2)(16)[7:0]

VT_J2BYTE_DET(2)(1)[7:0]

—

VT_J2BYTE_DET(2)(16)[7:0]

Channel 3 Receive J2 Expected/Monitor Values—R/W, RO

0x203D4

—

0x203E3

VT_J2BYTE_EXP_R[3][1]

—

VT_J2BYTE_EXP_R[3][16]

VT_J2BYTE_EXP(3)(1)[7:0]

—

VT_J2BYTE_EXP(3)(16)[7:0]

VT_J2BYTE_DET(3)(1)[7:0]

—

VT_J2BYTE_DET(3)(16)[7:0]

Channel 4 Receive J2 Expected/Monitor Values—R/W, RO

0x203E4

—

0x203F3

VT_J2BYTE_EXP_R[4][1]

—

VT_J2BYTE_EXP_R[4][16]

VT_J2BYTE_EXP(4)(1)[7:0]

—

VT_J2BYTE_EXP(4)(16)[7:0]

VT_J2BYTE_DET(4)(1)[7:0]

—

VT_J2BYTE_DET(4)(16)[7:0]

Channel 5 Receive J2 Expected/Monitor Values—R/W, RO

0x203F4

—

0x20403

VT_J2BYTE_EXP_R[5][1]

—

VT_J2BYTE_EXP_R[5][16]

VT_J2BYTE_EXP(5)(1)[7:0]

—

VT_J2BYTE_EXP(5)(16)[7:0]

VT_J2BYTE_DET(5)(1)[7:0]

—

VT_J2BYTE_DET(5)(16)[7:0]

Channel 6 Receive J2 Expected/Monitor Values—R/W, RO

0x20404

—

0x20413

VT_J2BYTE_EXP_R[6][1]

—

VT_J2BYTE_EXP_R[6][16]

VT_J2BYTE_EXP(6)(1)[7:0]

—

VT_J2BYTE_EXP(6)(16)[7:0]

VT_J2BYTE_DET(6)(1)[7:0]

—

VT_J2BYTE_DET(6)(16)[7:0]

Channel 7 Receive J2 Expected/Monitor Values—R/W, RO

0x20414

—

0x20423

VT_J2BYTE_EXP_R[7][1]

—

VT_J2BYTE_EXP_R[7][16]

VT_J2BYTE_EXP(7)(1)[7:0]

—

VT_J2BYTE_EXP(7)(16)[7:0]

VT_J2BYTE_DET(7)(1)[7:0]

—

VT_J2BYTE_DET(7)(16)[7:0]

Channel 8 Receive J2 Expected/Monitor Values—R/W, RO

0x20424

—

0x20433

VT_J2BYTE_EXP_R[8][1]

—

VT_J2BYTE_EXP_R[8][16]

VT_J2BYTE_EXP(8)(1)[7:0]

—

VT_J2BYTE_EXP(8)(16)[7:0]

VT_J2BYTE_DET(8)(1)[7:0]

—

VT_J2BYTE_DET(8)(16)[7:0]

Channel 9 Receive J2 Expected/Monitor Values—R/W, RO

0x20434

—

0x20443

VT_J2BYTE_EXP_R[9][1]

—

VT_J2BYTE_EXP_R[9][16]

VT_J2BYTE_EXP(9)(1)[7:0]

—

VT_J2BYTE_EXP(9)(16)[7:0]

VT_J2BYTE_DET(9)(1)[7:0]

—

VT_J2BYTE_DET(9)(16)[7:0]

Channel 10 Receive J2 Expected/Monitor Values—R/W, RO

0x20444

—

0x20453

VT_J2BYTE_EXP_R[10][1]

—

VT_J2BYTE_EXP_R[10][16]

VT_J2BYTE_EXP(10)(1)[7:0]

—

VT_J2BYTE_EXP(10)(16)[7:0]

VT_J2BYTE_DET(10)(1)[7:0]

—

VT_J2BYTE_DET(10)(16)[7:0]

Channel 11 Receive J2 Expected/Monitor Values—R/W, RO

0x20454

—

0x20463

VT_J2BYTE_EXP_R[11][1]

—

VT_J2BYTE_EXP_R[11][16]

VT_J2BYTE_EXP(11)(1)[7:0]

—

VT_J2BYTE_EXP(11)(16)[7:0]

VT_J2BYTE_DET(11)(1)[7:0]

—

VT_J2BYTE_DET(11)(16)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

197Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 222 on page 174.

Channel 12 Receive J2 Expected/Monitor Values—R/W, RO

0x20464

—

0x20473

VT_J2BYTE_EXP_R[12][1]

—

VT_J2BYTE_EXP_R[12][16]

VT_J2BYTE_EXP(12)(1)[7:0]

—

VT_J2BYTE_EXP(12)(16)[7:0]

VT_J2BYTE_DET(12)(1)[7:0]

—

VT_J2BYTE_DET(12)(16)[7:0]

Channel 13 Receive J2 Expected/Monitor Values—R/W, RO

0x20474

—

0x20483

VT_J2BYTE_EXP_R[13][1]

—

VT_J2BYTE_EXP_R[13][16]

VT_J2BYTE_EXP(13)(1)[7:0]

—

VT_J2BYTE_EXP(13)(16)[7:0]

VT_J2BYTE_DET(13)(1)[7:0]

—

VT_J2BYTE_DET(13)(16)[7:0]

Channel 14 Receive J2 Expected/Monitor Values—R/W, RO

0x20484

—

0x20493

VT_J2BYTE_EXP_R[14][1]

—

VT_J2BYTE_EXP_R[14][16]

VT_J2BYTE_EXP(14)(1)[7:0]

—

VT_J2BYTE_EXP(14)(16)[7:0]

VT_J2BYTE_DET(14)(1)[7:0]

—

VT_J2BYTE_DET()14(16)[7:0]

Channel 15 Receive J2 Expected/Monitor Values—R/W, RO

0x20494

—

0x204A3

VT_J2BYTE_EXP_R[15][1]

—

VT_J2BYTE_EXP_R[15][16]

VT_J2BYTE_EXP(15)(1)[7:0]

—

VT_J2BYTE_EXP(15)(16)[7:0]

VT_J2BYTE_DET(15)(1)[7:0]

—

VT_J2BYTE_DET(15)(16)[7:0]

Channel 16 Receive J2 Expected/Monitor Values—R/W, RO

0x204A4

—

0x204B3

VT_J2BYTE_EXP_R[16][1]

—

VT_J2BYTE_EXP_R[16][16]

VT_J2BYTE_EXP(16)(1)[7:0]

—

VT_J2BYTE_EXP(16)(16)[7:0]

VT_J2BYTE_DET(16)(1)[7:0]

—

VT_J2BYTE_DET(16)(16)[7:0]

Channel 17 Receive J2 Expected/Monitor Values—R/W, RO

0x204B4

—

0x204C3

VT_J2BYTE_EXP_R[17][1]

—

VT_J2BYTE_EXP_R[17][16]

VT_J2BYTE_EXP(17)(1)[7:0]

—

VT_J2BYTE_EXP(17)(16)[7:0]

VT_J2BYTE_DET(17)(1)[7:0]

—

VT_J2BYTE_DET(17)(16)[7:0]

Channel 18 Receive J2 Expected/Monitor Values—R/W, RO

0x204C4

—

0x204D3

VT_J2BYTE_EXP_R[18][1]

—

VT_J2BYTE_EXP_R[18][16]

VT_J2BYTE_EXP(18)(1)[7:0]

—

VT_J2BYTE_EXP(18)(16)[7:0]

VT_J2BYTE_DET(18)(1)[7:0]

—

VT_J2BYTE_DET(18)(16)[7:0]

Channel 19 Receive J2 Expected/Monitor Values—R/W, RO

0x204D4

—

0x204E3

VT_J2BYTE_EXP_R[19][1]

—

VT_J2BYTE_EXP_R[19][16]

VT_J2BYTE_EXP(19)(1)[7:0]

—

VT_J2BYTE_EXP(19)(16)[7:0]

VT_J2BYTE_DET(19)(1)[7:0]

—

VT_J2BYTE_DET(19)(16)[7:0]

Channel 20 Receive J2 Expected/Monitor Values—R/W, RO

0x204E4

—

0x204F3

VT_J2BYTE_EXP_R[20][1]

—

VT_J2BYTE_EXP_R[20][16]

VT_J2BYTE_EXP(20)(1)[7:0]

—

VT_J2BYTE_EXP(20)(16)[7:0]

VT_J2BYTE_DET(20)(1)[7:0]

—

VT_J2BYTE_DET(20)(16)[7:0]

Channel 21 Receive J2 Expected/Monitor Values—R/W, RO

0x204F4

—

0x20503

VT_J2BYTE_EXP_R[21][1]

—

VT_J2BYTE_EXP_R[21][16]

VT_J2BYTE_EXP(21)(1)[7:0]

—

VT_J2BYTE_EXP(21)(16)[7:0]

VT_J2BYTE_DET(21)(1)[7:0]

—

VT_J2BYTE_DET(21)(16)[7:0]

Channel 22 Receive J2 Expected/Monitor Values—R/W, RO

0x20504

—

0x20513

VT_J2BYTE_EXP_R[22][1]

—

VT_J2BYTE_EXP_R[22][16]

VT_J2BYTE_EXP(22)(1)[7:0]

—

VT_J2BYTE_EXP(22)(16)[7:0]

VT_J2BYTE_DET(22)(1)[7:0]

—

VT_J2BYTE_DET(22)(16)[7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

198 Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

For the following addresses, reference Table 222 on page 174.

Channel 23 Receive J2 Expected/Monitor Values—R/W, RO

0x20514

—

0x20523

VT_J2BYTE_EXP_R[23][1]

—

VT_J2BYTE_EXP_R[23][16]

VT_J2BYTE_EXP(23)(1)[7:0]

—

VT_J2BYTE_EXP(23)(16)[7:0]

VT_J2BYTE_DET(23)(1)[7:0]

—

VT_J2BYTE_DET(23)(16)[7:0]

Channel 24 Receive J2 Expected/Monitor Values—R/W, RO

0x20524

—

0x20533

VT_J2BYTE_EXP_R[24][1]

—

VT_J2BYTE_EXP_R[24][16]

VT_J2BYTE_EXP(24)(1)[7:0]

—

VT_J2BYTE_EXP(24)(16)[7:0]

VT_J2BYTE_DET(24)(1)[7:0]

—

VT_J2BYTE_DET(24)(16)[7:0]

Channel 25 Receive J2 Expected/Monitor Values—R/W, RO

0x20534

—

0x20543

VT_J2BYTE_EXP_R[25][1]

—

VT_J2BYTE_EXP_R[25][16]

VT_J2BYTE_EXP(25)(1)[7:0]

—

VT_J2BYTE_EXP(25)(16)[7:0]

VT_J2BYTE_DET(25)(1)[7:0]

—

VT_J2BYTE_DET(25)(16)[7:0]

Channel 26 Receive J2 Expected/Monitor Values—R/W, RO

0x20544

—

0x20553

VT_J2BYTE_EXP_R[26][1]

—

VT_J2BYTE_EXP_R[26][16]

VT_J2BYTE_EXP(26)(1)[7:0]

—

VT_J2BYTE_EXP(26)(16)[7:0]

VT_J2BYTE_DET(26)(1)[7:0]

—

VT_J2BYTE_DET(26)(16)[7:0]

Channel 27 Receive J2 Expected/Monitor Values—R/W, RO

0x20554

—

0x20563

VT_J2BYTE_EXP_R[27][1]

—

VT_J2BYTE_EXP_R[27][16]

VT_J2BYTE_EXP(27)(1)[7:0]

—

VT_J2BYTE_EXP(27)(16)[7:0]

VT_J2BYTE_DET(27)(1)[7:0]

—

VT_J2BYTE_DET(27)(16)[7:0]

Channel 28 Receive J2 Expected/Monitor Values—R/W, RO

0x20564

—

0x20573

VT_J2BYTE_EXP_R[28][1]

—

VT_J2BYTE_EXP_R[28][16]

VT_J2BYTE_EXP(28)(1)[7:0]

—

VT_J2BYTE_EXP(28)(16)[7:0]

VT_J2BYTE_DET(28)(1)[7:0]

—

VT_J2BYTE_DET(28)(16)[7:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

199Agere Systems Inc.

10 VT/TU Mapper Registers (continued)

Table 224. VT/TU Mapper Register Map (continued)

Note: Registers from 0x20590 to 0x20969 are reserved and should not be read.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Elastic Store Threshold Control—R/W

For the following addresses, reference Table 223 on page 174.

0x20574 VT_THRES_CTL1 VT_HIGH_THRES(1)[6:0] VT_LOW_THRES(1)[6:0]

0x20575 VT_THRES_CTL2 VT_HIGH_THRES(2)[6:0] VT_LOW_THRES(2)[6:0]

0x20576 VT_THRES_CTL3 VT_HIGH_THRES(3)[6:0] VT_LOW_THRES(3)[6:0]

0x20577 VT_THRES_CTL4 VT_HIGH_THRES(4)[6:0] VT_LOW_THRES(4)[6:0]

0x20578 VT_THRES_CTL5 VT_HIGH_THRES(5)[6:0] VT_LOW_THRES(5)[6:0]

0x20579 VT_THRES_CTL6 VT_HIGH_THRES(6)[6:0] VT_LOW_THRES(6)[6:0]

0x2057A VT_THRES_CTL7 VT_HIGH_THRES(7)[6:0] VT_LOW_THRES(7)[6:0]

0x2057B VT_THRES_CTL8 VT_HIGH_THRES(8)[6:0] VT_LOW_THRES(8)[6:0]

0x2057C VT_THRES_CTL9 VT_HIGH_THRES(9)[6:0] VT_LOW_THRES(9)[6:0]

0x2057D VT_THRES_CTL10 VT_HIGH_THRES(10)[6:0] VT_LOW_THRES(10)[6:0]

0x2057E VT_THRES_CTL11 VT_HIGH_THRES(11)[6:0] VT_LOW_THRES(11)[6:0]

0x2057F VT_THRES_CTL12 VT_HIGH_THRES(12)[6:0] VT_LOW_THRES(12)[6:0]

0x20580 VT_THRES_CTL13 VT_HIGH_THRES(13)[6:0] VT_LOW_THRES(13)[6:0]

0x20581 VT_THRES_CTL14 VT_HIGH_THRES(14)[6:0] VT_LOW_THRES(14)[6:0]

0x20582 VT_THRES_CTL15 VT_HIGH_THRES(15)[6:0] VT_LOW_THRES(15)[6:0]

0x20583 VT_THRES_CTL16 VT_HIGH_THRES(16)[6:0] VT_LOW_THRES(16)[6:0]

0x20584 VT_THRES_CTL17 VT_HIGH_THRES(17)[6:0] VT_LOW_THRES(17)[6:0]

0x20585 VT_THRES_CTL18 VT_HIGH_THRES(18)[6:0] VT_LOW_THRES(18)[6:0]

0x20586 VT_THRES_CTL19 VT_HIGH_THRES(19)[6:0] VT_LOW_THRES(19)[6:0]

0x20587 VT_THRES_CTL20 VT_HIGH_THRES(20)[6:0] VT_LOW_THRES(20)[6:0]

0x20588 VT_THRES_CTL21 VT_HIGH_THRES(21)[6:0] VT_LOW_THRES(21)[6:0]

0x20589 VT_THRES_CTL22 VT_HIGH_THRES(22)[6:0] VT_LOW_THRES(22)[6:0]

0x2058A VT_THRES_CTL23 VT_HIGH_THRES(23)[6:0] VT_LOW_THRES(23)[6:0]

0x2058B VT_THRES_CTL24 VT_HIGH_THRES(24)[6:0] VT_LOW_THRES(24)[6:0]

0x2058C VT_THRES_CTL25 VT_HIGH_THRES(25)[6:0] VT_LOW_THRES(25)[6:0]

0x2058D VT_THRES_CTL26 VT_HIGH_THRES(26)[6:0] VT_LOW_THRES(26)[6:0]

0x2058E VT_THRES_CTL27 VT_HIGH_THRES(27)[6:0] VT_LOW_THRES(27)[6:0]

0x2058F VT_THRES_CTL28 VT_HIGH_THRES(28)[6:0] VT_LOW_THRES(28)[6:0]

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

200 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers

Table of Con t ents

Contents Page

11 M13/M23 MUX/DeMUX Registers ...................................................................................................................200

11.1 M13 Block Register Descriptions .............................................................................................................202

11.2 M13 Register Map....................................................................................................................................231

Tables Page

Table 224. M13_ID_R, M13 Block Identification (RO)...........................................................................................202

Table 225. M13_VERSION_R, M13 Version (RO) ................................................................................................202

Table 226. M13_DELTA1, Delta (RO)....................................................................................................................202

Table 227. M13_DELTA2, Delta (RO)....................................................................................................................203

Table 228. M13_DELTA3, Delta (RO)....................................................................................................................203

Table 229. M13_DELTA4, Delta (RO)....................................................................................................................204

Table 230. M13_DELTA5, Delta (RO)....................................................................................................................205

Table 231. M13_MASK1, Mask (R/W)...................................................................................................................205

Table 232. M13_MASK2, Mask (R/W)...................................................................................................................206

Table 233. M13_MASK3, Mask (R/W)...................................................................................................................206

Table 234. M13_MASK4, Mask (R/W)...................................................................................................................207

Table 235. M13_MASK5, Mask (R/W)...................................................................................................................208

Table 236. M13_DS3_STATUS1, Status (RO) ......................................................................................................208

Table 237. M13_DS3_STATUS2, Status (RO) ......................................................................................................209

Table 238. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)....................................................................209

Table 239. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO).............................209

Table 240. M13_DS2_OOFD_R, DS2 Out-Of-Frame Delta (RO) .........................................................................210

Table 241. M13_DS2_LOFD_R, DS2 Loss-Of-Frame Delta (RO) ........................................................................210

Table 242. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO) ........................................210

Table 243. M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO).................................210

Table 244. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO)...............................................................211

Table 245. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO)....................................................211

Table 246. M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO).....................................................211

Table 247. M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO).................................................211

Table 248. M13_DS1_AIS_DETD_R[1—4], DS1 Alarm Indication Signal Delta Registers (RO)..........................212

Table 249. M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO).....................................212

Table 250. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO) ..................................................................212

Table 251. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)..................................212

Table 252. M13_DS2_OOF_R, DS2 Out-Of-Frame Status (RO)..........................................................................213

Table 253. M13_DS2_LOF_R, DS2 Loss of Frame Status (RO) ..........................................................................213

Table 254. M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO) .........................................213

Table 255. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO) ......................................213

Table 256. M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO)................................................................214

Table 257. M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO) ...........................................214

Table 258. M13_DS2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO)......................................................214

Table 259. M13_DS1_LOC_R[1—4], DS1 Loss of Clock Status Registers (RO)..................................................214

Table 260. M13_DS1_AIS_DET_R[1—4], DS1 Alarm Indication Signal Detect Status Registers (RO) ...............215

Table 261. M13_DS1_LB_DET_R[1—4], DS1 Loopback Detect Status Registers (RO)......................................215

Table 262. M13_DS1_FEAC_LB_DETD_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Delta

Registers (RO) ......................................................................................................................................215

Table 263. M13_DS1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Status

Registers (RO) ......................................................................................................................................216

Table 264. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)..............................216

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

11 M13/M23 MUX/DeMUX Registers (continued)

201Agere Systems Inc.

Table of Conten ts (continued)

Tables Page

Table 265. M13_RDL_STATUS, Receive Data-Link Status (RO)..........................................................................216

Table 266. M13_RDL_DATA_R, Receive Data-Link Data (RO) ............................................................................217

Table 267. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO)....................................................217

Table 268. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO).................................217

Table 269. M13_DS2_FORCE_OOF_R, DS2 Force Out-Of-Frame (One Shot R/W)...........................................217

Table 270. M13_CONTROL1, Control 1 (One Shot R/W) .....................................................................................218

Table 271. M13_CONTROL2, Control 2 (R/W) .....................................................................................................218

Table 272. M13_CONTROL3, Control 3 (R/W) ....................................................................................................219

Table 273. M13_SP_OFFSET_R, Sync Pulse Offset (R/W) .................................................................................219

Table 274. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W) .........................................................................219

Table 275. M13_M12_MUX_CONTROL1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W) ..................220

Table 276. M13_M12_MUX_CONTROL2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W) ..................220

Table 277. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W) ...............................................220

Table 278. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W)...................................................................220

Table 279. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W)................................................221

Table 280. M13_DS2_FINV_R, DS2 Frame Error (R/W) ......................................................................................221

Table 281. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W)..............................................................................221

Table 282. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W) ................................................................................221

Table 283. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W)...............................................221

Table 284. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W)...............222

Table 285. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W)...............222

Table 286. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W)................................................222

Table 287. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W)...............................................................223

Table 288. M13_DS3_CONTROL1, DS3 Control 1 (R/W) ....................................................................................223

Table 289. M13_DS3_CONTROL2, DS3 Control 2 (R/W) ....................................................................................224

Table 290. M13_TFEAC_CONTROL, Tx FEAC Control (R/W).............................................................................224

Table 291. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W)........................................................................225

Table 292. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W)........................................................................225

Table 293. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)......................................................................225

Table 294. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W) ..........................................................................226

Table 295. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W)....................................................226

Table 296. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)...............................................................................226

Table 297. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W)..................................................226

Table 298. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W)........................................................................................227

Table 299. M13_RDL_CONTROL, RDL Control (R/W).........................................................................................227

Table 300. M13_PM_CNT_ACT_R, Performance Counter (RO) ..........................................................................227

Table 301. M13_DS3_FERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO)......................................................227

Table 302. M13_DS3_FEBE_CNT_R[1—2], DS3 Far-End Block Error Registers (RO) .......................................228

Table 303. M13_DS3_CPERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO).........................................228

Table 304. M13_DS3_PERR_CNT_R[1—2], DS3 P-Bit Error Registers (RO)......................................................228

Table 305. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO)...........................228

Table 306. M13_DS2_FERR_CNT[7—1]_R, F-Bit Error Counter Status Registers (RO).....................................229

Table 307. M13_BPV_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO) .......................................229

Table 308. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO)........................................230

Table 309. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W) ................................................................230

Table 310. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 0 Registers

(64 Bytes x 8 Bits) (R/W).....................................................................................................................230

Table 311. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 1 Registers

(64 Bytes x 8 Bits) (R/W).....................................................................................................................230

Table 312. M13 Register Address Map .................................................................................................................231

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

202 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

11.1 M13 Block Register Descriptions

The following tables describe the functions of all bits. For each address, the register bits are indicated as either

read/write (R/W) or read only (RO), and the value of the bits on reset is given.

Table 224. M13_ID_R, M13 Block Identification (RO)

Table 225. M13_VERSION_R, M13 Version (RO)

Note: All bit description in the function column in Table 226 can be found in Table 236 on page 208.

Table 226. M13_DELTA1, Delta (RO)

Address Bit Name Function Reset

Default

0x10000 15:8 RSVD Reserved. 0x00

7:0 M13_ID[7:0] The M13_ID_R register returns a fixed value (0x01) when

read. 0x01

Address Bit Name Function Reset

Default

0x10001 15:3 RSVD Reserved. 0x000

2:0 M13_VERSION[2:0] These bits identify the version number of the M13. 0x0

Address Bit Name Function Reset

Default

0x10004 15:8 RSVD Reserved. 0x00

7 M13_RDL_IDLED This delta bit is set if M13_RDL_IDLE changes state. It

can be programmed to be either clear on read (COR) or

clear on write (COW), and it is not set to 1 again until

another state transition occurs.

6 M13_DS3_LOFD This delta bit is set if M13_DS3_LOF changes state. It

can be programmed to be either clear on read (COR) or

clear on write (COW), and it is not set to 1 again until

another state transition occurs.

5 M13_DS3_OOFD This delta bit is set if M13_DS3_OOF changes state. It

can be programmed to be either clear on read (COR) or

clear on write (COW), and it is not set to 1 again until

another state transition occurs.

4 M13_DS3_C1_DETD This delta bit is set if M13_DS3_C1_DET changes state.

It is cleared when read, and it is not set to 1 again until

another state transition occurs.

3 M13_DS3_RAI_DETD This delta bit is set if M13_DS3_RAI_DET changes state.

It can be programmed to be either clear on read (COR) or

clear on write (COW), and it is not set to 1 again until

another state transition occurs.

2 M13_DS3_AISPAT_DETD This delta bit is set if M13_DS3_AISPAT_DET changes

state. It can be programmed to be either clear on read

(COR) or clear on write (COW), and it is not set to 1

again until another state transition occurs.

1 M13_DS3_IDLEPAT_DETD This delta bit is set if M13_DS3_IDLEPAT_DET changes

state. It can be programmed to be either clear on read

(COR) or clear on write (COW), and it is not set to 1

again until another state transition occurs.

0 M13_DS3_CBZ_DETD This delta bit is set if M13_DS3_CBZ_DET changes

state. It can be programmed to be either clear on read

(COR) or clear on write (COW), and it is not set to 1

again until another state transition occurs.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

203Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 227. M13_DELTA2, Delta (RO)

Table 228. M13_DELTA3, Delta (RO)

Address Bit Name Function Reset

Default

0x10005 15:8 RSVD Reserved. 0x00

7 M13_DS1_LB_SD Delta Bit. This delta bit summarizes the state of

M13_DS1_LB_DETD[28:1] (Table 249 on page 212) bits. 0

6 M13_DS1_AIS_SD Delta Bit. This delta bit is set if any M13_DS1_AIS_DETD[28:1]

(Table 248 on page 212) bit is high. 0

5 M13_DS1_LOC_SD Delta Bit. This delta bit is set if any M13_DS1_LOCD[28:1]

(Table 247 on page 211) bit is high. 0

4 M13_RDS3_SEFD Delta Bit. This delta bit is set if M13_RDS3_SEF (Table 237 on

page 209) changes state. It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not set to

1 again until another state transition occurs.

3 M13_RDS3_ALL1_

DETD Delta Bit. This delta bit is set if M13_RDS3_ALL1_DET

(Table 237 on page 209) changes state. It can be programmed

to be either clear on read (COR) or clear on write (COW), and it

is not set to 1 again until another state transition occurs.

2 M13_RDS3_LOSD Delta Bit. This delta bit is set if M13_RDS3_LOS (Table 237 on

page 209) changes state. It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not set to

1 again until another state transition occurs.

1 M13_TDS3_LOCD Delta Bit. This delta bit is set if M13_TDS3_LOC (Table 237 on

page 209) changes state. It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not set to

1 again until another state transition occurs.

0 M13_RDS3_LOCD Delta Bit. This delta bit is set if M13_RDS3_LOC (Table 237 on

page 209) changes state. It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not set to

1 again until another state transition occurs.

Address Bit Name Function Reset

Default

0x10006 15:8 RSVD Reserved. 0x00

7 M13_DS2_RSV_SD Delta Bit. This delta bit is high if any

M13_DS2_RSV_RCVD[7:1] (Table 245 on page 211) bit is

high.

6 M13_DS2_LB_SD Delta Bit. This delta bit summarizes the state of

M13_DS2_LB_DETD[7:1] (Table 244 on page 211). 0

5 M13_DS2_RAI_SD Delta Bit. This delta bit summarizes the state of

M13_DS2_RAI_DETD[7:1] (Table 243 on page 210). 0

4 M13_DS2_AIS_SD Delta Bit. This delta bit summarizes the state of

M13_DS2_AIS_DETD[7:1] (Table 242 on page 210). 0

3 M13_DS2_LOF_SD Delta Bit. This delta bit is high if any M13_DS2_LOFD[7:1]

(Table 241 on page 210) bit is high. 0

2 M13_DS2_OOF_SD Delta Bit. This delta bit is high if any M13_DS2_OOFD[7:1]

(Table 240 on page 210) bit is high. 0

1 M13_XC_DS2_

AIS_SD Delta Bit. This delta bit is set if any

M13_XC_DS2_AIS_DETD[7:1] (Table 239 on page 209) bit is

high.

0 M13_XC_DS2_

LOC_SD Delta Bit. This delta bit is set if any M13_XC_DS2_LOCD[7:1]

(Table 238 on page 209) bit is high. 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

204 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 229. M13_DELTA4, Delta (RO)

Address Bit Name Function Reset

Default

0x10007 15:8 RSVD Reserved. 0x00

7 M13_TFEAC_DONE This bit is set when the M13 completes transmission of a

sequence of FEAC control code. It can be programmed to

be either clear on read (COR) or clear on write (COW), and

it is not set to 1 again until the event reoccurs.

6 M13_TDL_DONE This bit is set when the M13 completes transmission of a

data-link frame. It can be programmed to be either clear on

read (COR) or clear on write (COW), and it is not set to 1

again until the event reoccurs.

5 M13_TDL_BUF1_INT This bit is set when the device completes transmission of

M13_TDL_ 1DATA 63[ 7:0] (Table 311 on page 230) (the

last byte of buffer 1). It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not

set to 1 again until the event reoccurs.

4 M13_TDL_BUF0_INT This bit is set when the device completes transmission of

M13_TDL_ 0DATA 63[ 7:0] (Tab le 310 on page 230) (t h e

last byte of buffer 0). It can be programmed to be either

clear on read (COR) or clear on write (COW), and it is not

set to 1 again until the event reoccurs.

3 M13_RDL_FIFO_AFD This delta bit is set if M13_RDL_FIFO_AF (Table 237 on

page 209) changes state. It can be programmed to be

either clear on read (COR) or clear on write (COW), and it

is not set to 1 again until another state transition occurs.

2 M13_RDL_FRM_INT This bit indicates that a new data-link frame closing flag or

an abort Byte Has Been Received. It can be programmed

to be either clear on read (COR) or clear on write (COW),

and it is not set to 1 again until the event reoccurs.

1 M13_RFEAC_ALM_INT This bit indicates that a new DS3 FEAC alarm codeword

has been received. The new codeword is available in reg-

ister M13_RFEAC_CODE_R (Table 264 on page 216). For

loopback codewords, the appropriate

M13_DS1_FEAC_LB_DETx (Table 263 on page 216) and

M13_DS3_FLB_DET (Table 263 on page 216) bits in reg-

isters 0x2F through 0x32 will be set or cleared. It can be

programmed to be either clear on read (COR) or clear on

write (COW), and it is not set to 1 again until the event

reoccurs.

0 M13_RFEAC_LB_INT This bit indicates that a new DS3 FEAC loopback code-

word has been received. The new codeword is available in

the appropriate M13_DS1_FEAC_LB_DETx and

M13_DS3_FLB_DET bits will be set or cleared. It can be

programmed to be either clear on read (COR) or clear on

write (COW), and it is not set to 1 again until the event

reoccurs.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

205Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 230. M13_DELTA5, Delta (RO)

Note: All bit description in the function column in Table 231 can be found in Table 226 on page 202.

Table 231. M13_MASK1, Mask (R/W)

Address Bit Name Function Reset

Default

0x10008 15:2 RSVD Reserved. 0x0000

1 M13_DS2DMX_LOC_SD Delta Bit. This delta bit is set if any

M13_DS2DMX_LOCD[7:0] (Table 246 on page 211 ) bit

0 M13_RDL_FIFO_UFD Delta Bit. This delta bit is set if bit M13_RDL_FIFO_UF

(Table 237 on page 209) changes state. It can be pro-

grammed to be either clear on read (COR) or clear on write

(COW), and it is not set to 1 again until another state tran-

sition occurs.

Address Bit Name Function Reset

Default

0x1000A 15:8 RSVD Reserved. 0x00

7 M13_RDL_IDLEM Mask Bit. Setting this mask bit high prevents the delta

M13_RDL_IDLED from causing the block output inter-

rupt (INT) to be active.

6 M13_DS3_LOFM Mask Bit. Setting this mask bit high prevents the delta

M13_DS3_LOFD from causing the block output INT to

be active.

5 M13_DS3_OOFM Mask Bit. Setting this mask bit high prevents the delta

M13_DS3_OOFD from causing the block output INT to

be active.

4 M13_DS3_C1_DETM Mask Bit. Setting this mask bit high prevent s the delta

M13_DS3_C1_DETD from causing the block output INT

to be active.

3 M13_DS3_RAI_DETM Mask Bit. Setting this ma sk bit high prevents the delta

M13_DS3_RAI_DETD from causing the block output INT

to be active.

2 M13_DS3_AISPAT_DETM Mask Bit. Setting this mask bit high prevents the delta

M13_DS3_AISP AT_DETD from causing the block output

INT to be active.

1 M13_DS3_IDLEPAT_DETM Mask Bit. Setting this mask bit high prevents the delta

M13_DS3_IDLEPAT_DETD from causing the block out-

put INT to be active.

0 M13_DS3_CBZ_DETM Mask Bit. Setting this mask bit high prevents the delta

M13_DS3_CBZ_DETD from causing the block output

INT to be active.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

206 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Note: All bit description in the function column in Table 232 can be found in Table 227 on page 203.

Table 232. M13_MASK2, Mask (R/W)

Address Bit Name Function Reset Default

0x1000B 15:8 RSVD Reserved. 0x00

7 M13_DS1_LB_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS1_LB_SD from causing the

block output interrupt (INT) to be active.

6 M13_DS1_AIS_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13 _DS1_A IS_ SD from cau sing

the block output INT to be active.

5 M13_DS1_LOC_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13 _DS1_LO C_ SD from cau sing

the block output INT to be active.

4 M13_RDS3_SEFM Mask Bit. Setting this mask bit high prevents the

delta M13_RDS3_SEFD from causing the block

output INT to be active.

3 M13_RDS3_ALL1_DETM Mask Bit. Setting this mask bit high prevents the

delta M13_RDS3_ALL1_DETD from causing the

block output INT to be active.

2 M13_RDS3_LOSM Mask Bit. Setting this mask bit high prevents the

delta M13_RDS3_LOSD from causing the block

output INT to be active.

1 M13_TDS3_LOCM Mask Bit. Setting this mask bit high prevents the

delta M13_TDS3_LOCD from causing the block

output INT to be active.

0 M13_RDS3_LOCM Mask Bit. Setting this mask bit high prevents the

delta M13_RDS3_LOCD from causing the block

output INT to be active.

Note: All bit description in the function column in Table 233 can be found in Table 228 on page 203.

Table 233. M13_MASK3, Mask (R/W)

Address Bit Name Function Reset Default

0x1000C 15:8 RSVD Reserved. 0x00

7 M13_DS2_RSV_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_RSV_SD from causing the

block output interrupt (INT) to be active.

6 M13_DS2_LB_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_LB_SD from causing the

block output INT to be active.

5 M13_DS2_RAI_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_RAI_SD from causing the

block output INT to be active.

4 M13_DS2_AIS_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_AIS_SD from causing the

block output INT to be active.

3 M13_DS2_LOF_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_LOF_SD from causing the

block output INT to be active.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

11 M13/M23 MUX/DeMUX Registers (continued)

207Agere Systems Inc.

0x1000C 2 M13_DS2_OOF_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_DS2_OOF_SD from causing the

block output INT to be active.

1 M13_XC_DS2_AIS_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_XC_DS2_AIS_SD from causing

the block output INT to be active.

0 M13_XC_DS2_LOC_SM Mask Bit. Setting this mask bit high prevents the

summary delta M13_XC_DS2_LOC_SD from caus-

ing the block output INT to be active.

Note: All bit description in the function column in Table 234 can be found in Table 229 on page 204.

Table 234. M13_MASK4, Mask (R/W)

Address Bit Name Function Reset

Default

0x1000D 15:8 RSVD Reserved. 0x00

7 M13_TFEAC_DONEM M ask Bit. Setting this mask bit high prevents

M13_TFEAC_DONE from causing the block output inter-

rupt (INT) to be active.

6 M13_TDL_DONEM M ask Bit . Setting this mask bit high prevents

M13_TDL_DONE from causing the block output INT to be

active.

5 M13_TDL_BUF1_INTM Mask Bit. Setting this mask bit high prevents

M13_TDL_BUF1_INT from causing the block output INT to

be active.

4 M13_TDL_BUF0_INTM Mask Bit. Setting this mask bit high prevents

M13_TDL_BUF0_INT from causing the block output INT to

be active.

3 M13_RDL_FIFO_AFM M ask Bit . Setting this mask bit high prevents

M13_RDL_FIFO_AFD from causing the block output INT

to be active.

2 M13_RDL_FRM_INTM Mask Bit . Setting this mask bit high prevents

M13_RDL_FRM_INT from causing the block output INT to

be active.

1 M13_RFEAC_ALM_INTM Mask Bit . Setting this mask bit high prevents

M13_RFEAC_ALM_INT from causing the block output INT

to be active.

0 M13_RFEAC_LB_INTM Mask Bit. Setting this mask bit high prevents

M13_RFEAC_LB_INT from causing the block output INT to

be active.

Note: All bit description in the function column in Table 233 can be found in Table 228 on page 203.

Table 233. M13_MASK3, Mask (R/W) (continued)

Address Bit Name Function Reset Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

208 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 235. M13_MASK5, Mask (R/W)

Address Bit Name Function Reset

Default

0x1000E 15:2 RSVD Reserved. 00000000000000

1 M13_DS2DMX_LOC_SM M ask Bit . Setting this mask bit high prevents the

summary delta M13_DS2DMX_LOC_SD

(Table 230 on page 205) from causing the block

output interrupt (INT) to be active.

0 M13_RDL_FIFO_UFM Mask Bit. Setting this mask bit high prevents

M13_RDL_FIFO_UFD (Table 230 on page 205)

from causing the block output INT to be active.

Tab le 236. M13 _DS 3_STATUS 1, St atu s (RO)

Address Bit Name Function Reset

Default

0x1000F 15:8 RSVD Reserved. 0x00

7 M13_RDL_IDLE This bit is set if 15 consecutive ones are received on the

path maintenance data link. it is cleared when a flag byte

is rec eived.

6 M13_DS3_LOF This bit is set if M13_DS3_OOF is high continuously for 28

frame periods (approximately 3 ms). Once set,

M13_DS3_LOF is not cleared until M13_DS3_OOF is

continuously low for 28 frame periods.

5 M13_DS3_OOF The DS3 Framer Out Of Frame State Bit. (See DS3

framer section on page 476.) This bit is high while out of

frame.

4 M13_DS3_C1_DET This bit is set if the first C bit of each DS3 frame is

received high for 8 consecutive frames. Once

M13_DS3_C1_DET is set, three consecutive frames with

C1 = 0 must be received before it is cleared.

3 M13_DS3_RAI_DET If both X bits in two consecutive frames are received as 0,

the M13 sets this bit to 1. Once it is set, it is not cleared

until both X bits in two consecutive frames are received

as 1.

2 M13_DS3_AISP AT_DET The 4704 information bits in each M frame are checked for

the presence of the AIS (1010) pattern. A pattern detection

bit is set if fewer than five pattern errors are received in

each of two consecutive frames. Once a bit is set, it is not

cleared until at least 16 pattern errors are received in each

of two consecutive frames.

1 M13_DS3_IDLEPA T_DET The 4704 information bits in each M frame are checked for

the presence of the idle (1100) pattern. A pattern detection

bit is set if fewer than five pattern errors are received in

each of two consecutive frames. Once a bit is set, it is not

cleared until at least 16 pattern errors are received in each

of two consecutive frames.

0 M13_DS3_CBZ_DET This bit is set if every C bit in three consecutive DS3

frames is 0. It is cleared if the three C bits in a single

M-sub fra me are all 1.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

209Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Tab le 237. M13 _DS 3_STATUS 2, St atu s (RO)

Table 238. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)

Table 239. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)

Address Bit Name Function Reset

Default

0x10010 15:7 RSVD Reserved. 000000000

6 M13_RDL_FIFO_UF This bit is 1 if the receive HDLC FIFO is underflow. 0

5 M13_RDL_FIFO_AF This bit is 1 if the number of unread bytes in the receive

HDLC FIFO is greater than the fill-up level set by bits

M13_RDL_FILL[1:0] (Table 299 on page 227).

4 M13_RDS3_SEF This bit is 1 if there are three or more F-bit errors in

16 consecutive F bits. It is not terminated until the signal is

in-frame and there are less than three F-bit errors in 16

consecutive F bits.

3 M13_RDS3_ALL1_

DET This bit is 1 if the input data is 0 for fewer than 9 out of

8192 cloc k per io ds . 0

2 M13_RDS3_LOS This bit is 1 if there are 175 ± 75 contiguous pulse positions

with no pulses of either positive or negative polarity at the

DS3 input. An LOS is cleared upon detecting an average

pulse density of at least 33% over a period of 175 ± 75

contiguous pulse positions, starting with the receipt of a

pulse.

1 M13_TDS3_LOC This bit is 1 if the SMPR_TDS3CLK signal fails to have

transitions for at least 10 periods of SMPR_RDS3CLK. A

single transition on SMPR_TDS3CLK resets this bit.

0 M13_RDS3_LOC This bit is 1 if the SMPR_RDS3CLK signal fails to have

transitions for at least 10 periods of SMPR_TDS3CLK. A

single transition on SMPR_RDS3CLK resets this bit.

Address Bit Name Function Reset

Default

0x10011 15:7 RSVD Reserved. 0x000

6:0 M13_XC_DS2_

LOCD[7:1] Delta Bits. These individual delta bits are set as the result of

the corresponding state bits M13_XC_DS2_LOC[7:1]

(Table 250 on page 212) transitioning either from 0 to 1 or from

1 to 0. They can be programmed to be either clear on read

(COR) or clear on write (COW), and they are not set to 1 again

until the event reo ccur s .

0x00

Address Bit Name Function Reset

Default

0x10012 15:7 RSVD Reserved. 0x000

6:0 M13_XC_DS2_

AIS_DETD[7:1] Delta Bits. These individual delta bits are set as the result of

the corresponding state bits M13_XC_DS2_AIS_DET[7:1]

(Table 251 on page 212) transitioning either from 0 to 1 or from

1 to 0. They can be programmed to be either clear on read

(COR) or clear on write (COW), and they are not set to 1 again

until the event reoccurs.

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

210 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 240. M13_DS2_OOFD_R, DS2 Out-Of-Frame Delta (RO)

Table 241. M13_DS2_LOFD_R, DS2 Loss-Of-Frame Delta (RO)

Table 242. M13_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detect Delta (RO)

Table 243. M13_DS2_RAI_DETD_R, DS2 Remote Alarm Indication Detection Delta (RO)

Address Bit Name Function Reset

Default

0x10013 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_OOFD[7:1] Delta Bits. These individual delta bits are set as the result of

the corresponding state bits M13_DS2_OOF[7:1] (Table 252

on page 213) transitioning either from 0 to 1 or from 1 to 0.

Delta bits can be programmed to be either clear on read

(COR) or clear on write (COW), and they are not set to 1 again

until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10014 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_LOFD[7:1] Delta Bits. These individual delta bits are set as the result of

the corresponding state bits M13_DS2_LOF[7:1] (Table 253

on page 213) transitioning either from 0 to 1 or from 1 to 0.

They can be programmed to be either clear on read (COR) or

clear on write (COW), and they are not set to 1 again until the

event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10015 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_AIS_DETD[7:1] Delta Bits. These individual delta bits are set as the result

of the corresponding state bits M13_DS2_AIS_DET[7:1]

(Table 254 on page 213) transitioning either from 0 to 1 or

from 1 to 0. Delta bits can be programmed to be either

clear on read (COR) or clear on write (COW), and they

are not set to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10016 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RAI_DETD[7:1] Delta Bits. These individual delta bits are set as the result

of the corresponding state bits M13_DS2_RAI_DET[7:1]

(Table 255 on page 213) transitioning either from 0 to 1 or

from 1 to 0. Delta bits can be programmed to be either

clear on read (COR) or clear on write (COW), and they

are not set to 1 again until the event reoccurs.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

211Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 244. M13_DS2_LB_DETD_R, DS2 Loopback Detect Delta (RO)

Table 245. M13_DS2_RSV_RCVD_R, DS2 Receive Reserved Bit Delta (RO)

Table 246. M13_DS2DMX_LOCD_R, DS2 DeMUX Loss of Clock Delta (RO)

Table 247. M13_DS1_LOCD_R[1—4], DS1 Loss of Clock Delta Registers (RO)

Address Bit Name Function Reset

Default

0x10017 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_LB_DETD[7:1] Delta Bits. These individual delta bits are set as the result

of the corresponding state bits M13_DS2_LB_DET[7:1]

(Table 256 on page 214) transitioning either from 0 to 1 or

from 1 to 0. Delta bits can be programmed to be either

clear on read (COR) or clear on write (COW), and they are

not set to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10018 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RSV_RCVD[7:1] Delta Bits. These individual delta bits are set as the

result of the corresponding state bits

M13_DS2_RSV_RCV[7:1] (Table 257 on page 214)

transitioning either from 0 to 1 or from 1 to 0. Delta bits

can be programmed to be either clear on read (COR) or

clear on write (COW), and they are not set to 1 again

until the event reoccurs. (G.747).

0x00

Address Bit Name Function Reset

Default

0x10019 15:7 RSVD Reserved. 0x000

6:0 M13_DS2DMX_LOCD[7:1] Delta Bits. These individual delta bits are set as the

result of the corresponding state bits

M13_DS2DMX_LOC[7:1] (Table 258 on page 214) tran-

sitioning either from 0 to 1 or from 1 to 0. Delta bits can

be programmed to be either clear on read (COR) or clear

on write (COW), and they are not set to 1 again until the

event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x1001E 15:4 RSVD Reserved. 0x000

0x1001F

—

0x10021

15:8 RSVD Reserved. 0x00

0x1001E

0x1001F

0x10020

0x10021

3:0

7:0

M13_DS1_LOCD[28:25]

M13_DS1_LOCD[24:17]

M13_DS1_LOCD[16:9]

M13_DS1_LOCD[8:1]

Delta Bits. These individual delta bits are set as the

result of the corresponding state bits

M13_DS1 _LO C[2 8:1] ( Table 259 on page 214) transi-

tioning either from 0 to 1 or from 1 to 0. Delta bits can

be programmed to be either clear on read (COR) or

clear on write (COW), and they are not set to 1 again

until the event reoccurs.

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

212 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 248. M13_DS1_AIS_DETD_R[1—4], DS1 Alarm Indication Signal Delta Registers (RO)

Table 249. M13_DS1_LB_DETD_R[1—4], DS1 Loopback Detect Delta Registers (RO)

Table 250. M13__XC_DS2_LOC_R, DS2 Loss of Clock Status (RO)

Table 251. M13_XC_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)

Address Bit Name Function Reset

Default

0x10022 15:4 RSVD Reserved. 0x000

0x10023

—

0x10025

15:8 RSVD Reserved. 0x00

0x10022

0x10023

0x10024

0x10025

3:0

7:0

M13_DS1_AIS_DETD[28:25]

M13_DS1_AIS_DETD[24:17]

M13_DS1_AIS_DETD[16:9]

M13_DS1_AIS_DETD[8:1]

Delta Bits. These individual delta bits are set as the

result of the corresponding state bits

M13_DS1_AIS_DET[28:1] (Table 260 on page 215)

transitioning either from 0 to 1 or from 1 to 0. Delta

bits can be programmed to be either clear on read

(COR) or clear on write (COW), and they are not set

to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x10026 15:4 RSVD Reserved. 0x000

0x10027

—

0x10029

15:8 RSVD Reserved. 0x00

0x10026

0x10027

0x10028

0x10029

3:0

7:0

M13_DS1_LB_DETD[28:25]

M13_DS1_LB_DETD[24:17]

M13_DS1_LB_DETD[16:9]

M13_DS1_LB_DETD[8:1]

Delta Bits. These individual delta bits are set as the

result of the corresponding state bits

M13_DS1_LB_DET[28:1] (Table 261 on page 215)

transitioning either from 0 to 1 or from 1 to 0. Delta

bits can be programmed to be either clear on read

(COR) or clear on write (COW), and they are not set

to 1 again until the event reoccurs.

0x00

Address Bit Name Function Reset

Default

0x1002F 15:7 RSVD Reserved. 0x000

6:0 M13_XC_DS2_LOC[7:1] A logic 1 of M13_XC_DS2_LOCy bit indicates that loss of

clock is detected on the DS2 clock input. 0x00

Address Bit Name Function Reset

Default

0x10030 15:7 RSVD Reserved. 0x000

6:0 M13_XC_DS2_AIS_DET[7:1] M13_XC_DS2_AIS_DETy Bit. The

M13_XC_DS2_AIS_DETy bit is set high if the input

XC_DS2M23DATAy is 0 for fewer than 5 clock cycles

in each of two consecutive 840 clock periods, and

cleared if there are more than four zeros in each of two

consecutive 840-bit periods.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

213Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 252. M13_DS2_OOF_R, DS2 Out-Of-Frame Status (RO)

Table 253. M13_DS2_LOF_R, DS2 Loss of Frame Status (RO)

Table 254. M13_DS2_AIS_DET_R, DS2 Alarm Indication Signal Detect Status (RO)

Table 255. M13_DS2_RAI_DET_R, DS2 Remote Alarm Indication Detect Status (RO)

Address Bit Name Function Reset

Default

0x10031 15:7 RSVD Reserved. 000000

000

6:0 M13_DS2_OOF[7:1] State Bits. This register contains the state bits for the DS2

framers. A 1 indicates out of frame. 0x7F

Address Bit Name Function Reset

Default

0x10032 15:7 RSVD Reserved. —

6:0 M13_DS2_LOF[7:1] M13_DS2_LOFy Bit. The M13_DS2_LOFy bit is set if

M13_DS2_OOFy (Table 252 on page 213 ) is high continu-

ously for 28 DS3 frame periods (approximately 3 ms). Once

set, M13_DS2_LOFy is not cleared until M13_DS2_OOFy is

continuously low for 28 DS3 frame periods. DS3 frame peri-

ods are not counted while M13_DS3_OOF = 1 (Table 236 on

page 208).

0x00

Address Bit Name Function Reset

Default

0x10033 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_AIS_DET[7:1] M13_DS2_AIS_DETy Bit. The M13_DS2_AIS_DET y bit is

set high if the input to the yth M12 demultiplexer is logic 0

for fewer than five clock cycles in each of two consecutive

840 clock periods, and cleared if there are more than four

zeros in each of two consecutive 840-bit periods.

0x00

Address Bit Name Function Reset

Default

0x10034 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RAI_DET[7:1] M13_DS2_RAI_DETy Bit. The M13_DS2_RAI_DETy bit

changes state only after the X bit in the DS1 mode

(M13_DS1_E1Ny = 1 (Table 275 on page 220)), or the RAI

bit in the E1 mode is received as the same value for four

consecutive DS2 frames. DS2 frame periods are not

counted while M13_DS3_OOF = 1 (Table 236 on

page 208). In the DS1 mode, M13_DS2_RAI_DETy is set

to the inverse of the X bit. In the E1 mode, it is set equal to

the RAI bit.

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

214 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 256. M13_DS2_LB_DET_R, DS2 Loopback Detect Status (RO)

Table 257. M13_DS2_RSV_RCV_R, DS2 Receive Reserved Bit Delta Status (RO)

Table 258. M13_DS2DMX_LOC_R, DS2 DeMUX Loss of Clock Status (RO)

Table 259. M13_DS1_LOC_R[1—4], DS1 Loss of Clock Status Registers (RO)

Address Bit Name Function Reset

Default

0x10035 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_LB_DET[7:1] M13 Mode. In the M23 mode (M13_M23_CBP = 1

(Table 272 on page 219)), the C bits in each received DS3

M-subframe are checked for loopback requests. If the third

C bit differs from the first and second C bits in the yth M-

subframe for five successive DS3 frames,

M13_DS2_LB_DETy is set to 1. M13_DS2_LB_DETy is

cleared when the third C bit does not differ from the first two

C bits in subframe y for five successive DS3 frames. In the

C-bit parity mode, M13_DS2_LB_DETy is fixed at 0.

0x00

Address Bit Name Function Reset

Default

0x10036 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RSV_RCV[7:1] M13_DS2_RSV_RCVy Bit. The M13_DS2_RSV_RCVy

bit changes state only after the reserved bit in the E1

mode (M13_DS1_E1Ny = 0) is received as the same

value for four consecutive DS2 frames. DS2 frame peri-

ods are not counted while M13_DS3_OOF = 1.

M13_DS2_RSV_RCVy is set equal to the reserved bit.

0x00

Address Bit Name Function Reset

Default

0x10037 15:7 RSVD Reserved. 0x000

6:0 M13_DS2DMX_LOC[7:1] M13_DS2DMX_LOCy Bit. A logic 1 of

M13_DS2DMX_LOCy bit indicates that loss of clock is

detected on the DS2 cloc k inp ut, XC_D S2DMXCLK y.

0x00

Address Bit Name Function Reset

Default

0x1003C

0x1003D

0x1003E

0x1003F

15:4

15:8

RSVD

Reserved.

0x000

0x00

0x1003C

0x1003D

0x1003E

0x1003F

3:0

7:0

M13_DS1_LOC[28:25]

M13_DS1_LOC[24:17]

M13_DS1_LOC[16:9]

M13_DS1_LOC[8:1]

The M13_DS1_LOCx bits indicate when loss of clock is

detected on a low-speed clock input, XC_DS1CLKx. 0x0

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

215Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 260. M13_DS1_AIS_DET_R[1—4], DS1 Alarm Indication Signal Detect Status Registers (RO)

Table 261. M13_DS1_LB_DET_R[1—4], DS1 Loopback Detect Status Registers (RO)

Table 262. M13_DS1_FEAC_LB_DETD_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Delta

Registers (RO)

Address Bit Name Function Reset

Default

0x10040

0x10041

0x10042

0x10043

15:4

15:8

RSVD

Reserved.

0x000

0x00

0x10040

0x10041

0x10042

0x10043

3:0

7:0

M13_DS1_AIS_DET[28:25]

M13_DS1_AIS_DET[24:17]

M13_DS1_AIS_DET[16:9]

M13_DS1_AIS_DET[8:1]

The M13_DS1_AIS_DETx bits indicate when AIS is

detected on a low-speed data input, XC_DS1DATAx. 0x0

0x00

Address Bit Name Function Reset

Default

0x10044

0x10045

0x10046

0x10047

15:4

15:8

RSVD

Reserved.

0x000

0x00

0x10044

0x10045

0x10046

0x10047

3:0

7:0

M13_DS1_LB_DET[28:25]

M13_DS1_LB_DET[24:17]

M13_DS1_LB_DET[16:9]

M13_DS1_LB_DET[8:1]

The M13_DS1_LB_DETx bits indicate when a loopback

request has been received through inversion of the third

C bit in received DS2 frames.

0x0

0x00

Address Bit Name Function Reset

Default

0x10049

0x1004A

0x1004B

0x1004C

0x10049

0x1004A

0x1004B

0x1004C

15:8

6:4

15:8

3:0

7:0

RSVD

M13_DS3_FLB_DETD

RSVD

M13_DS1_FEAC_LB_DETD[28:25]

M13_DS1_FEAC_LB_DETD[24:17]

M13_DS1_FEAC_LB_DETD[16:9]

M13_DS1_FEAC_LB_DETD[8:1]

Reserved.

This delta bit is set if M13_DS3_FLB_DET

(Table 263 on page 216) changes state. It can

be programmed to be either clear on read (COR)

or clear on write (COW), and it is not set to 1

again until another state transition occurs.

Reserved.

These individual delta bits are set as the result

of the corresponding state bits

M13_DS1_FEAC_LB_DET[28:1] (Table 263 on

page 216) transitioning either from 0 to 1 or from

1 to 0. Delta bits can be programmed to be

either clear on read (COR) or clear on write

(COW), and they are not set to 1 again until the

event reoc cu rs.

0x00

0x0

000

0x00

0x0

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

216 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 263. M13_DS1_FEAC_LB_DET_R[1—4], DS1 Far-End Alarm and Control Loopback Detect Status

Registers (RO)

Table 264. M13_RFEAC_CODE_R, Receive Far-End Alarm and Control Code Status (RO)

Table 265. M13_RDL_STATUS, Receive Data-Link Status (RO)

Address Bit Name Function Reset

Default

0x1004D 15:8 RSVD Reserved. 0x00

7 M13_DS3_FLB_DET When an FEAC loopback activate codeword for

DS3 is received four consecutive times, the bit is

set high. The bit is cleared when a loopback deac-

tivate codeword is received four consecutive

times.

6:4 RSVD Reserved. 000

0x1004E

0x1004F

0x10050

15:8

RSVD

Reserved.

0x00

0x1004D

0x1004E

0x1004F

0x10050

3:0

7:0

M13_DS1_FEAC_LB_DET[28:25]

M13_DS1_FEAC_LB_DET[24:17]

M13_DS1_FEAC_LB_DET[16:9]

M13_DS1_FEAC_LB_DET[8:1]

When an FEAC loopback activate codeword for

DS1 is received four consecutive times, the

appropriate bit(s) is set high. The bit(s) is cleared

when a loopback deactivate codeword for that

channel(s) is received four consecutive times.

0x0

0x00

Address Bit Name Function Reset

Default

0x10051 15:6 RSVD Reserved. 000000

0000

5:0 M13_RFEAC_CODE[5:0] M13_RFEAC_CODE[5:0] Bits. When the same codeword

is received through the FEAC channel four consecutive

times, M13 will set M13_RFEAC_CODE[5:0] =

x5x4x3x2x1x0, where the received FEAC codeword is

0x5x4x3x2x1x0 0 11111111, and it is received right to left.

0x3F

Address Bit Name Function Reset

Default

0x10052 15:5 RSVD Reserved. 0x000

4 M13_RDL_FLAG This bit is high if the closing flag or an abort byte has been

received. 0

3 M13_RDL_ABORT This bit is high if the frame was ended with an abort byte

rather than a closing flag. 0

2 M13_RDL_NOT_BYTE This bit is set if the number of bits in the frame (after removal

of stuffed zeros) is not a multiple of 8. 0

1 M13_RDL_OVFL This bit is set if at least 1 byte of the frame was overwritten by

a byte from a succeeding frame before being read. 0

0 M13_RDL_FCS_ERR This bit is set if the CRC-16 check fails and

M13_RDL_FCS = 1 (Table 299 on page 227). 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

217Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 266. M13_RDL_DATA_R, Receive Data-Link Data (RO)

Table 267. M13_RDL_FRAME_SIZE_R, Receive Data-Link Frame Size (RO)

Table 268. M13_RHDLC_STATUS_R, Receive High-Level Data-Link Control Status (RO)

Table 269. M13_DS2_FORCE_OOF_R, DS2 Force Out-Of-Frame (One Shot R/W)

Address Bit Name Function Reset

Default

0x10053 15:8 RSVD Reserved. 0x00

7:0 M13_RDL_DATA[7:0] Bytes received via the path maintenance data link are stored

in a 128-byte FIFO. They can be read out of the FIFO through

this register, M13_RDL_DATA_R. On reset, the FIFO is emp-

tied, and reading from this register returns an undetermined

value.

0xXX

Address Bit Name Function Reset

Default

0x10054 15:7 RSVD Reserved. 0x000

6:0 M13_RDL_FRAME_SIZE[6:0] The number of bytes in the frame modulo-128 is indi-

cated by this register. This is the number of bytes from

the frame that have been written into the FIFO, not the

number of bytes remaining in the FIFO. All bytes

between the opening flag and the FCS bytes are

included (unless M13_RDL_FCS (Table 299 on

page 227) is low, in which case the FCS bytes are

included in the count).

0x00

Address Bit Name Function Reset

Default

0x10055 15:8 RSVD Reserved. 0x00

7:0 M13_RHDLC_STATUS[7:0] This register provides information on the earliest HDLC

frame still in the FIFO. A value of 1 in bit 7 indicates that

the closing flag or an abort byte for the current frame

has been received; a 1 in bit 6 indicates the current

frame is corrupted; bits 5 to 1 indicate the size of the

current frame modulo-32; and bit 0 is set to 1 if there

are less than 32 bytes of the earliest frame left in the

FIFO.

0x00

Address Bit Name Function Reset

Default

0x10059 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_FORCE_OOF[7:1] M 13_D S2_ F OR CE_ OO Fy Bit s. When

M13_DS2_FORCE_OOFy transitions from 0 to 1, the

DS2 framer in M12 demultiplexer Y is forced out of

frame.

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

218 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 270. M13_CONTROL1, Control 1 (One Shot R/W)

Address Bit Name Function Reset

Default

0x1005A 15:3 RSVD Reserved. 0x000

2 M13_RDL_FRM_CLR If M13_RDL_FRM_CLR is set to 1, the portion of the earli-

est frame still in the receive HDLC FIFO will be deleted.

The user must reset M13_RDL_FRM_CLR before another

frame can be deleted. If M13_RDL_FRM_CLR is set

before the closing flag of the frame currently being read

from the FIFO has been received, all subsequent bytes of

the frame will be discarded without being written into the

FIFO.

1 M13_DS3_FORCE_OOF When this bit transitions from 0 to 1, the DS3 framer is

forced out of frame. 0

0 M13_BIPOL_ERR A single bipolar violation error is transmitted each time this

bit transitions from 0 to 1. 0

Table 271. M13_CONTROL2, Control 2 (R/W)

Address Bit Name Function Reset

Default

0x1005C 15:8 RSVD Reserved. 0x00

7 M13_BPV_IN If this bit is 1, the SMPR_RDS3NEG_BPV input is used as an

external B3ZS bipolar violation indication instead of a negative

input pulse.

6 M13_LOOP_TIME The M23 multiplexer uses the SMPR_TDS3CLK if this bit is 0;

otherwise, the SMPR_RDS3CLK is used. 0

5 M13_LOOP_T_TO_R Setting this bit to 1 causes the M23 MUX output to be looped

back to the M23 deMUX inp ut. 0

4 M13_LOOP_R_TO_T Setting this bit to 1 causes the received DS3 input to be

looped back to the transmit DS3 output. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

11 M13/M23 MUX/DeMUX Registers (continued)

219Agere Systems Inc.

Table 272. M13_CONTROL3, Control 3 (R/W)

Table 273. M13_SP_OFFSET_R, Sync Pulse Offset (R/W)

Table 274. M13_SP_D_OFFSET_R, Sync Pulse D Offset (R/W)

0x1005C 3 M13_AUTO_AIS_LOF M13_AUTO_AIS_LOF Bit. If this bit is 1, the M13 will auto-

matically insert AIS in all DS2 outputs of the M23 demulti-

plexer when M13_DS3_LOF = 1 (Table 236 on page 208),

and it will automatically insert AIS in all DS1 or E1 outputs of

M12 demultiplexer Y when M13_DS2_LOFy = 1 (Table 253

on page 213).

2 M13_AUTO_AIS_

OOF M13_AUTO_AIS_OOF Bit. If this bit is 1, the M13 will auto-

matically insert AIS in all DS2 outputs of the M23 demulti-

plexer when M13_DS3_OOF = 1 (Table 236 on page 208),

and it will automatically insert AIS in all DS1 or E1 outputs of

M12 demultiplexer Y when M13_DS2_OOFy = 1 (Table 252

on page 213).

1 M13_AUTO_FLB M13_AUTO_FLB Bit. If this bit Is 1, the device will automati-

cally loop the received DS3 input to the transmit DS3 output

when M13_DS3_FLB_DET = 1 (Table 263 on page 216), and

it will automatically select DS1/E1 output x from an M12

demultiplexer in place of the DS1/E1 output from input selec-

tor x when M13_DS1_FEAC_LB_DETx = 1 (Table 263 on

page 216).

0 M13_AUTO_LB M13_AUTO_LB Bit. When M13_AUTO_LB = 1, loopback of

DS1 channel x is activated if M13_DS1_LB_DETx = 1

(Table 261 on page 215).

Address Bit Name Function Reset

Default

0x1005D 15:2 RSVD Reserved. 0x0000

1 M13_M23_CBP M13_M23_CBP Bit. If this bit Is 1, the M13 operates in the

M23 mode; otherwise, it is in the C-bit parity mode. 0

0 M13_BIPOLAR M 13_ BIPOLAR Bit. The M13 performs B3ZS encoding and

decoding if this bit is high. 0

Address Bit Name Function Reset

Default

0x1005E 15:8 RSVD Reserved. 0x00

7:0 M13_NSMI_SP_

OFFSET[7:0] The register determines the offset value (0—255) for the trans-

mit NSMI sync pulse ahead of the M1 bit in a DS3 frame. 0x00

Address Bit Name Function Reset

Default

0x1005F 15:8 RSVD Reserved. 0x00

7:0 M13_NSMI_SP_D_

OFFSET[7:0] The register determines the offset value (0—255) for the

receive NSMI sync pulse ahead of the M1 bit in a DS3 frame. 0x00

Table 271. M13_CONTROL2, Control 2 (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

220 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 275. M13_M12_MUX_CONTROL1_R[1—7], M12 MUX CONTROL 1 Registers [1—7] (R/W)

Table 276. M13_M12_MUX_CONTROL2_R[1—7], M12 MUX CONTROL 2 Registers [1—7] (R/W)

Table 277. M13_DS2_RAI_SEND_R, DS2 Remote Alarm Indication Send (R/W)

Table 278. M13_DS2_RSV_SEND_R, DS2 Reserve Bit Send (R/W)

Address Bit Name Function Reset

Default

0x10060

0x10062

0x10064

0x10066

0x10068

0x1006A

0x1006C

15:8 RSVD Reserved. 0x00

7:6 M13_M12_MODE[1—7][1:0] 00 = the M12 MUX operates as the first stage of M13

multiplexing. The DS1/E1 clocks are inputs to the

block.

01 = the M12 MUX operates as an independent multi-

plexer. The DS1/E1 clocks are inputs to the block.

10 = the M12 MUX operates as an independent multi-

plexer. The DS1/E1 clocks are outputs from the

block.

11 = the M12 is idle.

5 M13_MUXCH2_4_INV[1—7] M13_MUXCH2_4_INV[1—7] Bits. If these bits are 1,

the second and fourth DS1 inputs to the M12 multiplex-

ers are inverted before they are MUXed into DS2 sig-

nals.

4 M13_DS1_E1N[1—7] M13_DS1_E1N[1—7] Bits. If these bits are 1, the M12

multiplexers operate on DS1 inputs; otherwise, they

operate on E1 inputs.

3:0 M13_DS1_LB_REQ[1:28] M13_DS1_LB_REQ[1:28] Bits. If these bits are 1, the

third C bit for DS1 or E1 channels is inverted in the gen-

erated DS2 frames to indicate loopback requests.

0x0

Address Bit Name Function Reset

Default

0x10061

0x10063

0x10065

0x10067

0x10069

0x1006B

0x1006D

15:8 RSVD Reserved. 0x00

7:4 M13_SEL_DS1_LB[1:28] A 1 in these bits will force deMUXed DS1 or E1 signals to

be looped back. 0x0

3:0 M13_RDS1_EDGE[1:28] A 1 in these bits means that the received DS1/E1 signals

are retimed by the rising edge of the associated clocks. A

logic 0 means that the data is retimed by the falling edge.

0x0

Address Bit Name Function Reset

Default

0x1006E 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RAI_SEND[7:1] The remote alarm indication is activated if these bits are

set to 1. 0x00

Address Bit Name Function Reset

Default

0x1006F 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_RSV_SEND[7:1] In the E1 mode, the reserved bit of DS2 is set to the

value of these bits. 0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

221Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 279. M13_DS2_MPINV_R, DS2 M Frame Alignment or Parity Error (R/W)

Table 280. M13_DS2_FINV_R, DS2 Frame Error (R/W)

Table 281. M13_DS2_P_BER_R, Parity Bit Error Rate (R/W)

Table 282. M13_DS2M12_EDGE_R, DS2 M12 Edge (R/W)

Table 283. M13_DS2_FORCE_AIS_R, DS2 Force Alarm Indication Signal (R/W)

Address Bit Name Function Reset

Default

0x10070 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_MPINV[7:1] M13_DS2_MPINV[7:1] Bits. These bits determine whether

the DS2 M frame alignment signals in the DS1 mode, or the

DS2 parity bits in the E1 mode are generated in error.

0x00

Address Bit Name Function Reset

Default

0x10071 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_FINV[7:1] M 1 3_DS2_F I NV[7 :1 ] B i t s. These bits determine whether the

DS2 M-subframe alignment signals in the DS1 mode, or the

frame alignment signal in the E1 mode are generated in error.

0x00

Address Bit Name Function Reset

Default

0x10072 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_P_BER[7:1] DS2 Parity Bits. The DS2 pa r ity b it s in t h e E1 mo de i mm e di -

ately following each 0 to 1 transition of the input

SMPR_BER_INSRT (Table 75 on page 68) ar e inver ted if

these register bits are set to 1.

0x00

Address Bit Name Function Reset

Default

0x10073 15:7 RSVD Reserved. 0x000

6:0 M13_DS2M12_EDGE[7:1] M13_DS2M12_EDGE[7:1] Bits. A 1 in these bits means

that the output DS2 signals from M12 MUXs are retimed

by the rising edge of the associated clocks; a 0 means

that the data is retimed by the falling edge.

0x00

Address Bit Name Function Reset

Default

0x10074 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_FORCE_AIS[7:1] M13_DS2_FORCE_AIS[7:1] Bits. A 1 in these bits

means that the output DS2 signals from M12 MUXs are

forced to be AIS (all ones).

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

222 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 284. M13_M12_DEMUX_CONTROL1_R[1—7], M12 DeMUX Control 1 Registers [1—7] (R/W)

Table 285. M13_M12_DEMUX_CONTROL2_R[1—7], M12 DeMUX Control 2 Registers [1—7] (R/W)

Table 286. M13_M12_DEMUX_CONTROL3, DS2 M12 DeMUX Control 3 (R/W)

Address Bit Name Function Reset

Default

0x1007B

0x1007D

0x1007F

0x10081

0x10083

0x10085

0x10087

15:8 RSVD Reserved. 0x00

7:6 M13_M12DMX_

MODE[1—7][1:0] M13_M1 2DMX _M O DE[ 1— 7][1 :0] Bits.

00 = the M12 deMUX Receives DS2 Signal From the M23

deMUX.

01 = the M12 deMUX operates as an independent demulti-

plexer.

10/11 = the M12 deMUX is idle and outputs are held low.

5 M13_DEMUXCH2_

4_INV[1—7] The second and fourth DS1 outputs from the M12 demulti-

plexers are inverted if these bits are 1. 1

4 M13_OUT_TYPE[1—7] Each DS1/E1 output selector number, x, can be expressed

as either 4y – 3, 4y – 2, 4y – 1, or 4y, where y ranges from 1

to 7. For a given y, the 4 selectors in the group output DS1

signals if M13_OUT_TYPEy = 1, or E1 signals if

M13_OUT_TYPEy = 0.

3:0 M13_TDS1_EDGE[28:1] The transmit DS1/E1 signals are retimed by the rising edge

of the associated clocks if these bits are set high; otherwise,

the data is retimed by the falling edge.

0xF

Address Bit Name Function Reset

Default

0x1007C

0x1007E

0x10080

0x10082

0x10084

0x10086

0x10088

15:4 RSVD Reserved. 0x000

3:0 M13_DS1_OUT_AIS[28:1] A logic 1 of these bits will cause the corresponding DS1

output all ones AIS. 0x0

Address Bit Name Function Reset

Default

0x10089 15:2 RSVD Reserved. 0x0000

1 M13_DS2_MODE This bit controls the DS2 framing algorithm in the DS1

mode only. Out-of-frame is declared if the F bits contain

two errors in 4 bits if M13_DS2_MODE = 0, or at least 1 F-

bit error in four consecutive M-subframe pairs if

M13_DS2_MODE = 1.

0 M13_DS2_FERR_MODE This bit controls frame error counting for the M12 demulti-

plexers in the E1 mode only. If this bit is 0, the frame error

counters increment for each frame alignment signal bit

error. Otherwise, the counter increments once for each

frame alignment signal that contains at least 1 bit error.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

223Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 287. M13_DMDS2_EDGE_R, DS2 Edge for M12 DeMUX (R/W)

Table 288. M13_DS3_CONTROL1, DS3 Control 1 (R/W)

Address Bit Name Function Reset

Default

0x1008A 15:7 RSVD Reserved. 0x000

6:0 M13_DMDS2_EDGE[7:1] M13_DMDS2_EDGE[7:1] Bits. A logic 1 of these bits

means that the input DS2 signals to M12 demultiplexers

are retimed by the rising edge of the associated clocks; a

logic 0 means that the data is retimed by the falling edge.

0x00

Address Bit Name Function Reset

Default

0x10092 15:8 RSVD Reserved. 0x00

7 M13_DS3_FINV M13_DS3_FINV Bit. For testing purposes, this bit is high

to allow the F bit to be generated with errors. 0

6 M13_DS3_MINV M13_DS3_MINV Bit. For t est in g p u rpo s es , t hi s bi t i s hi gh

to allow the M bit to be generated with errors. 0

5 M13_DS3_PINV M13_DS3_PINV Bit. For testing purposes, this bit is high

to allow the P bit to be generated with errors. 0

4 M13_DS3_FORCE_AIS M13_DS3_FORCE_AIS Bit. This bit causes the M13 to

generate DS3 AIS in place of the transmit DS3 signal

from the M23 multiplexer.

3 M13_DS3_FORCE_IDLE M13_DS3_FORCE_IDLE Bit. This bit ca uses the M13 to

generate DS3 idle (unless M13_DS3_FORCE_AIS

(Table 288 on page 223) is also set) in place of the trans-

mit DS3 signal from the M23 multiplexer.

2 M13_TDS3_FORCE_ALL1 M13_TDS3_FORCE_ALL1 Bit. This bit causes the M13

to generate unframed all ones DS3 output. 0

1 M13_M23CLK_MODE M13_M23CLK_MODE Bit. If this bit is 1, DS2 clocks

associated with DS2 signals being MUXed into DS3 are

outputs from the block; otherwise, they are inputs to the

block.

0RSVDReserved.0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

224 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 289. M13_DS3_CONTROL2, DS3 Control 2 (R/W)

Table 290. M13_TFEAC_CONTROL, Tx FEAC Control (R/W)

Address Bit Name Function Reset

Default

0x10093 15:7 RSVD Reserved. 0x000

6 M23_STUFF_MODE M23_STUFF_MODE Bit. A logic 0 on this bit will cause the

M23 stuffing to be determined by the external stuff request;

otherwis e, fix ed stu ffing is used .

5 M13_NSMI_MODE M13_NSMI_MODE Bit. A logic 1 of this bit will enable M13 to

receive and output Ds3 payload through a serial link. 0

4 M13_DS3_P_BER M13_DS3_P_BER Bit. The P bits and, in CBP mode, the CP

bits in the DS3 frame immediately following each 0 to 1 transi-

tion of the input SMPR_BER_INSERT (Table 75 on page 68)

are inverted if this bit is set to 1.

3 M13_CBIT2_ACT M13_CBIT2_ACT Bit. This bit is used only in the C-Bit parity

mode. In this mode, if it is 0, the second C bit of each DS3

frame, C2, is set to 1. Otherwise, the transmit value of C2 is

input through pin TCBDATA (E12).

2 M13_UNUSED_ACT M13_UNUSED_ACT Bit. This bit is used only in the C-bit par-

ity mode. In this mode, if it is 0, the unused C bits of each DS3

frame (the fourth through sixth and the sixteenth through

twenty-first) are set to 1. Otherwise, the transmit values of

these bits are inp ut through pin TCBDATA (E12).

1 M13_DS3_RAI_SEND M13_DS3_RAI_SEND Bit. The transmitted DS3 X bits are set

to the inverse of this bit during normal transmission. 0

0 M13_FEBE_ERR M13_FEBE_ ERR Bit. This bit is used to force errors in the

transmitted DS3 FEBE indication. If the bit is set, all DS3

frames are transmitted with the FEBE bits set to 000.

Address Bit Name Function Reset

Default

0x10094 15:8 RSVD Reserved. 0x00

7:6 M13_TFEAC_CTL[1:0] M13_TFEAC_CTL. The user can provision the M13 to trans-

mit continuous ones by setting M13_TFEAC_CTL to 00. 0x0

5:0 M13_TFEAC_

CODE[5:0] FEAC Signals. TFEAC signals are transmitted continuously

by setting M13_TFEAC_CTL to 01, and M13_TFEAC_CODE

= x5x4x3x2x1x0, where x5x4x3x2x1x0 is the appropriat e

value for the alarm or status codeword.

In order to activate a loopback, the user may set

M13_TFEAC_CTL = 11, and M13_TFEAC_CODE =

x5x4x3 x2x1x0, w here x5 x4x3x2x 1x0 is t he appr opriate value

for the loopback codeword. The M13 will then transmit 10

repetitions of the activate codeword, 0 000111 0 11111111,

followed by 10 repetitions of 0 x5x4x3x2x1x0 0 11111111.

After transmitting this 40 octet sequence, it will set

M13_TF EAC_DONE (Table 229 on page 204) to 1.

In order to deactivate a loopback, the user may set

M13_TFEAC_CTL = 10, and M13_TFEAC_CODE =

x5x4x3 x2x1x0, w here x5 x4x3x2x 1x0 is t he appr opriate value

for the loopback codeword. The M13 will then transmit 10

repetitions of the deactivate codeword, 0 011100 0 11111111,

followed by 10 repetitions of 0 x5x4x3x2x1x0 0 11111111.

After transmitting this 40 octet sequence, it will set

M13_TFE AC_ D ONE to 1 .

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

225Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 291. M13_THDLC_CONTROL1, Tx HDLC Control 1 (R/W)

Table 292. M13_THDLC_CONTROL2, Tx HDLC Control 2 (R/W)

Table 293. M13_DS2_LB_REQ_R, DS2 Loopback Request (R/W)

Address Bit Name Function Reset

Default

0x10095 15:6 RSVD Reserved. 0x000

5 M13_TDL_BUF1_END If this bit is 0, all bytes from HDLC buffer 1 and at least one

byte from HDLC buffer 0 are transmitted. If it is 1, bytes from

buffer 1 are transmitted sequentially up to and including the

byte set by M13_TDL_BYTE_END[5:0] (Table 292 on

page 225).

4 M13_TDL_BUF0_END If this bit is 0, all bytes from HDLC buffer 0 and at least one

byte from HDLC buffer 1 are transmitted. If it is 1, bytes from

buffer 0 are transmitted sequentially up to and including the

byte set by M13_TDL_BYTE_END[5:0].

3 M13_TDL_ACT If the data link is not used, the user should set

M13_TDL_ACT to 0, which causes all ones to be transmit-

ted. Otherwise, this bit should be set to 1.

2 M13_TDL_NTRNL If M13_TDL_NTRNL = 0, the data transmitted on the data

link comes directly from the M13 input pin TDLDATA (E8);

otherwise (M13_TDL_NTRNL = 1), the data link is controlled

by the internal HDLC transmitter. This bit is valid only when

M13_TDL_ACT = 1 (Table 291 on page 225).

1 M13_TDL_NTRNL_ACT Once M13_TDL_NTRNL_ACT is Set to 1, the HDLC trans-

mitter begins transmitting the first byte of the first data buffer

following the completion of the next flag byte. The user may

abort the transmission of an HDLC frame by clearing

M13_TDL_NTRNL_ACT to 0 prior to completing transmis-

sion of the last byte from the data buffers. If so, the HDLC

controller will stop transmission from the buffers and send

an abort byte (01111111). The abort byte will then be fol-

lowed by flag bytes until M13_TDL_NTRNL_ACT is again

set to 1, starting transmission of a new frame.

0 M13_TDL_FCS If M13_TDL_FCS = 1, the HDLC controller appends the two-

byte ITU-T FCS with the necessary zero stuffing before

sending the closing flag; otherwise, no FCS bytes will be

transmitted.

Address Bit Name Function Reset

Default

0x10096 15:6 RSVD Reserved. 0x000

5:0 M13_TDL_BYTE_

END[5:0] These bits define the position of the last byte to be transmitted

from the buffer. 0x00

Address Bit Name Function Reset

Default

0x10097 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_LB_

REQ[7:1] M13_DS2_LB_REQy Bits. If M13_DS2_LB_REQy = 1, the

third C bit in the yth DS3 M-subframe is transmitted as the

inverse of the first two C bits (which indicates a loopback

request for DS2 channel y).

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

226 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 294. M13_SEL_DS2_LB_R, Select DS2 Loopback (R/W)

Table 295. M13_RDS2_EDGE_R[1—2], Rx DS2 Edge Registers [1—2](R/W)

Table 296. M13_DS2_OUT_IDLE_R, DS2 Output Idle (R/W)

Table 297. M13_DS2_OUT_AIS_R, DS2 Output Alarm Indication Signal (R/W)

Address Bit Name Function Reset

Default

0x10098 15:7 RSVD Reserved. 0x000

6:0 M13_SEL_DS2_LB[7:1] M13_SE L_D S2 _LBy Bit s. If M13_SEL_DS2_LBy = 1, the

DS2 signal from time slot y in the received DS3 signal is

looped back into time slot y of the transmitted DS3 signal.

0x00

Address Bit Name Function Reset

Default

0x10099 15:7 RSVD Reserved. 0x000

6:0 M13_RDS2_EDGE[7:1] A logic 1 of these bits means that the received

DS2 signals are retimed by the rising edge of the

associated clocks. A logic 0 means that the data

is retimed by the falling edge. When used in the

demand clocking mode of the M23 mapping,

M13_RDS2_EDGE[7:1] = 1 should be set if the

delay from the output clock to the incoming data

(the maximum should be less than eight STS-1

clock cycles) i s less tha n four STS- 1 clock cy cles;

otherwise, M13_RDS2_EDGE[7:1] = 0 should be

used.

0x00

0x1009A 15:7 RSVD Reserved. 0x000

6:0 M13_DS2ALCO_RTM_EDGE[7:1] M13_DS2ALCO_RTM_EDGE[7:1] Bits. In the

demand clocking mode of the M23 mapping, this

capability, in addition to M13_RDS2_EDGE[7:1],

for retiming input DS2 data. It should normally be

set to logic 1 (default). A logic 0 is suggested only

to be used with M13_RDS2_EDGE[7:1] = 0 when

necessary.

0x7F

Address Bit Name Function Reset

Default

0x1009E 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_OUT_IDLE[7:1] M13_DS2_OUT_IDLE[7:1] Bits. If

M13_DS2_OUT_IDLEy = 1, the output from DS2 output

selection block y is held low.

0x00

Address Bit Name Function Reset

Default

0x1009F 15:7 RSVD Reserved. 0x000

6:0 M13_DS2_OUT_AIS[7:1] M13_DS2_OUT_AIS[7:1] Bits. If M13_DS2_OUT_IDLEy

= 0 (Table 296 on page 226), a logic 1 of this bit causes

DS2 AIS to be output from the DS2 output selector y; oth-

erwise, the DS2 signal from time slot y in the received DS3

signal will be output.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

227Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 298. M13_TDS2_EDGE_R, Tx DS2 Edge (R/W)

Table 299. M13_RDL_CONTROL, RDL Control (R/W)

Table 300. M13_PM_CNT_ACT_R, Performance Counter (RO)

Table 301. M13_DS3_FERR_CNT_R[1—2], DS3 F-Bit Error Registers (RO)

Address Bit Name Function Reset

Default

0x100A0 15:7 RSVD Reserved. 000000000

6:0 M13_TDS2_EDGE[7:1] A logic 1 of these bits means that the transmit DS2 sig-

nals are retimed by the rising edge of the associated

clocks. A logic 0 means that the data is retimed by the

falling edge.

0x7F

Address Bit Name Function Reset

Default

0x100A1 15:5 RSVD Reserved. 0x000

4:3 M13_RDL_FILL[1:0] The M13_RDL_FIFO_AF (Table 237 on page 209) bit is set if

the buffer reaches the fill level.

00 = sets the receive HDLC FIFO fill level to 16 bytes.

01 = sets the receive HDLC FIFO fill level to 32 bytes.

10 = sets the receive HDLC FIFO fill level to 64 bytes.

11 = sets the receive HDLC FIFO fill level to 96 bytes.

2 M13_RDL_FCS If M13_RDL_FCS = 1, the FCS bytes will be checked at HDLC

receiver. Otherwise, the FCS is not checked and the last 2

bytes of the HDLC frame are written into the FIFO.

1 M13_DS3_MODE This bit controls the DS3 framing algorithm. Out-of-frame is

declared if the F bits contain three errors in 16 bits if

M13_DS3_MODE = 0, or at least one F-bit error in four con-

secutive M-subframes if M13_DS3_MODE = 1.

0 M13_RDS3_EDGE A logic 1 of this bit means that the received DS3 data is

retimed by the rising edge of the associated clock. A logic 0

means the data is retimed by the falling edge.

Address Bit Name Function Reset

Default

0x100A5 15:1 RSVD Reserved. 0x0000

0 M13_PM_CNT_ACT This bit returns a 0 when read if all performance counter val-

ues are 0; otherwise, it is set to 1. 0

Address Bit Name Function Reset

Default

0x100A6 15:4 RSVD Reserved. 0x000

0x100A7 15:8 RSVD Reserved. 0x00

0x100A6

0x100A7 3:0

7:0 M13_DS3_FERR_CNT[11:8]

M13_DS3_FERR_CNT[7:0] This register holds the results from a counter that

increments each time an error is detected in either a

DS3 F bit or M bit.

0x0

0x00

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

228 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 302. M13_DS3_FEBE_CNT_R[1—2], DS3 Far-End Block Error Registers (RO)

Table 303. M13_DS3_CPERR_CNT_R[1—2], DS3 C-Bit Parity Error Registers (RO)

Table 304. M13_DS3_PERR_CNT_R[1—2], DS3 P-Bit Error Registers (RO)

Address Bit Name Function Reset

Default

0x100A8 15:6 RSVD Reserved. 0x000

0x100A9 15:8 RSVD Reserved. 0x00

0x100A8

0x100A9 5:0

7:0 M13_DS3_FEBE_CNT[13:8]

M13_DS3_FEBE_CNT[7:0] This register holds the results from a counter that

accumulates FEBE error indications (one error indi-

cation for each DS3 frame with at least one FEBE bit

equal to zero).

0x00

Address Bit Name Function Reset

Default

0x100AA 15:6 RSVD Reserved. 0x000

0x100AB 15:8 RSVD Reserved. 0x00

0x100AA

0x100AB 5:0

7:0 M13_DS3_CPERR_CNT[13:8]

M13_DS3_CPERR_CNT[7:0] This register is used only in the C bit parity mode. It

indicates the number of frames with two or more C-bit

parity errors.

0x00

Address Bit Name Function Reset

Default

0x100AC 15:6 RSVD Reserved. 0x000

0x100AD 15:8 RSVD Reserved. 0x00

0x100AC

0x100AD 5:0

7:0 M13_DS3_PERR_CNT[13:8]

M13_DS3_PERR_CNT[7:0] This register indicates the number of frames with at

least one P bit that disagrees with the parity of the

previou s frame.

0x00

Table 305. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO)

Address Bit Name Function Reset

Default

0x100B2

0x100B3

0x100B4

0x100B5

0x100B6

0x100B7

0x100B8

0x100B9

0x100BA

0x100BB

0x100BC

0x100BD

0x100BE

0x100BF

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

15:5

15:8

RSVD Reserved. 0x000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

11 M13/M23 MUX/DeMUX Registers (continued)

229Agere Systems Inc.

Table 306. M13_DS2_FERR_CNT[7—1]_R, F-Bit Error Counter Status Registers (RO)

Table 307. M13_BPV_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO)

0x100B2

0x100B3 4:0

7:0 M13_DS2_PERR_CNT7[12:8]

M13_DS2_PERR_CNT7[7:0] These registers are used by M12 demulti-

plexers that operate in the G.747 (E1) mode.

They indicate the number of received DS2

frames with P-bit errors.

0x00

0x100B4

0x100B5 4:0

7:0 M13_DS2_PERR_CNT6[12:8]

M13_DS2_PERR_CNT6[7:0] 0x00

0x00

0x100B6

0x100B7 4:0

7:0 M13_DS2_PERR_CNT5[12:8]

M13_DS2_PERR_CNT5[7:0] 0x00

0x00

0x100B8

0x100B9 4:0

7:0 M13_DS2_PERR_CNT4[12:8]

M13_DS2_PERR_CNT4[7:0] 0x00

0x00

0x100BA

0x100BB 4:0

7:0 M13_DS2_PERR_CNT3[12:8]

M13_DS2_PERR_CNT3[7:0] 0x00

0x00

0x100BC

0x100BD 4:0

7:0 M13_DS2_PERR_CNT2[12:8]

M13_DS2_PERR_CNT2[7:0] 0x00

0x00

0x100BE

0x100BF 4:0

7:0 M13_DS2_PERR_CNT1[12:8]

M13_DS2_PERR_CNT1[7:0] 0x00

0x00

Address Bit Name Function Reset

Default

0x100C6

—

0x100CC

15:8 RSVD Reserved. 0x00

7:0 M13_DS2_FERR_CNT[7—1][7:0] These registers hold the results from DS2 frame

alignment signal error counters. In the DS1 mode,

these counters increment each time an error is

detected in either an F bit or M bit. In the E1 mode,

the counters increment either for each frame align-

ment signal bit error (if M13_DS2_FERR_MODE

(Table 286 on page 222) is 0), or once for each

frame alignment signal that contains at least one bit

error (if M13_DS2 _FERR_MODE = 1).

0x00

Address Bit Name Function Reset

Default

0x100CD

—

0x100CF

15:8 RSVD Reserved. 0x00

7:0 M13_BPV_CNT[23:0] This register is only used in the DS3 bipolar

mode. It holds the results from a counter that

increments each time a received B3ZS bipolar

coding vi olatio n is dete cte d.

0x00

Table 305. M13_DS2_PERR_CNT[7—1]_R[1—2], P-Bit Error Counter Status Registers (RO) (continued)

Address Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

230 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 308. M13_EXZ_CNT_R[1—3], Bipolar Violation Counter Status Registers (RO)

Table 309. M13_TDL_BUFFER_R, Tx Data-Link Buffer Control (R/W)

Table 310. M13_TDL_0DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 0 Registers

(64 Bytes x 8 Bits) (R/W)

Table 311. M13_TDL_1DATA_R[0—63], Tx Data for Path Maintenance Data-Link Buffer 1 Registers

(64 Bytes x 8 Bits) (R/W)

Address Bit Name Function Reset

Default

0x100D0

—

0x100D2

15:8 RSVD Reserved. 0x00

7:0 M13_EXZ_CNT[23:0] This register is only used in the DS3 bipolar mode. It holds the

results from a counter that increments each time an excessive

zeros string is detected.

0x00

Address Bit Name Function Reset

Default

0x100FF 15:1 RSVD Reserved. 0x0000

0 M13_TDL_BUFFER If this bit is 0, data written to registers M13_TDL_0DATA_R[0—

63] address 0x10100—0x1013f (Table 309) is stored in the

path maintenance data-link buffer 0. otherwise, the data is writ-

ten to buffer 1.

Address Bit Name Function Reset

Default

0x10100

—

0x1013F

15:8 RSVD Reserved. 0x00

7:0 M13_TDL_

0DATA[0—63][7:0] This 64-byte buffer for the transmit path maintenance data link

is accessible when M13_TDL_BUFFER = 0 (Table 309). On

reset, reading from these registers returns an undetermined

value.

0xXX

Address Bit Name Function Reset

Default

0x10100

—

0x1013F

15:8 RSVD Reserved. 0x00

7:0 M13_TDL_

1DATA[0—63][7:0] This 64-byte buffer for the transmit path maintenance data link

is accessible when M13_TDL_BUFFER = 1. On reset, reading

from these registers returns an undetermined value.

0xXX

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

231Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

11.2 M13 Register Map

Table 312. M13 Register Address Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bits [15:8] Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Block-level Status—RO

0x10000

Page 202 M13_ID_R M13_ID[7:0]

0x10001

Page 202 M13_VERSION_R M13_VERSION[2:0]

0x10002

0x10003 RSVD

DS3 Deltas, Summary Deltas, FEAC, and DL Interrupts—RO

0x10004

Page 202 M13_DELTA1 M13_RDL_IDLED M13_DS3_LOFD M13_DS3_OOFD M13_DS3_C1_DETD M13_DS3_RAI_DETD M13_DS3_AISPAT_DETD M13_DS3_IDLEPAT_DETD M13_DS3_CBZ_DETD

0x10005

Page 203 M13_DELTA2 M13_DS1_LB_SD M13_DS1_AIS_SD M13_DS1_LOC_SD M13_RDS3_SEFD M13_RDS3_ALL1_DETD M13_RDS3_LOSD M13_TDS3_LOCD M13_RDS3_LOCD

0x10006

Page 203 M13_DELTA3 M13_DS2_RSV_SD M13_DS2_LB_SD M13_DS2_RAI_SD M13_DS2_AIS_SD M13_DS2_LOF_SD M13_DS2_OOF_SD M13_XC_DS2_AIS_SD M13_XC_DS2_LOC_SD

0x10007

Page 204 M13_DELTA4 M13_TFEAC_DONE M13_TDL_DONE M13_TDL_BUF1_INT M13_TDL_BUF0_INT M13_RDL_FIFO_AFD M13_RDL_FRM_INT M13_RFEAC_ALM_INT M13_RFEAC_LB_INT

0x10008

Page 205 M13_DELTA5 M13_DS2DMX_LOC_SD M13_RDL_FIFO_UFD

0x10009 RSVD

Interrupt Masks—R/W

0x1000A

Page 205 M13_MASK1 M13_RDL_IDLEM M13_DS3_LOFM M13_DS3_OOFM M13_DS3_C1_DETM M13_DS3_RAI_DETM M13_DS3_AISPAT_DETM M13_DS3_IDLEPAT_DETM M13_DS3_CBZ_DETM

0x1000B

Page 206 M13_MASK2 M13_DS1_LB_SM M13_DS1_AIS_SM M13_DS1_LOC_SM M13_RDS3_SEFM M13_RDS3_ALL1_DETM M13_RDS3_LOSM M13_TDS3_LOCM M13_RDS3_LOCM

0x1000C

Page 206 M13_MASK3 M13_DS2_RSV_SM M13_DS2_LB_SM M13_DS2_RAI_SM M13_DS2_AIS_SM M13_DS2_LOF_SM M13_DS2_OOF_SM M13_XC_DS2_AIS_SM M13_XC_DS2_LOC_SM

0x1000D

Page 207 M13_MASK4 M13_TFEAC_DONEM M13_TDL_DONEM M13_TDL_BUF1_INTM M13_TDL_BUF0_INTM M13_RDL_FIFO_AFM M13_RDL_FRM_INTM M13_RFEAC_ALM_INTM M13_RFEAC_LB_INTM

0x1000E

Page 208 M13_MASK5 M13_DS2DMX_LOC_SM M13_RDL_FIFO_UFM

DS3 Status—RO

0x1000F

Page 208 M13_DS3_STATUS1 M13_RDL_IDLE M13_DS3_LOF M13_DS3_OOF M13_DS3_C1_DET M13_DS3_RAI_DET M13_DS3_AISPAT_DET M13_DS3_IDLEPAT_DET M13_DS3_CBZ_DET

0x10010

Page 209 M13_DS3_STATUS2 M13_RDL_FIFO_UF M13_RDL_FIFO_AF M13_RDS3_SEF M13_RDS3_ALL1_DET M13_RDS3_LOS M13_TDS3_LOC M13_RDS3_LOC

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

232 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Individual DS2 and DS1 Deltas—RO

0x10011

Page 209 M13_XC_DS2_LOCD_R M13_XC_DS2_LOCD[7:1]

0x10012

Page 209 M13_XC_DS2_AIS_DETD_R M13_XC_DS2_AIS_DETD[7:1]

0x10013

Page 210 M13_DS2_OOFD_R M13_DS2_OOFD[7:1]

0x10014

Page 210 M13_DS2_LOFD_R M13_DS2_LOFD[7:1]

0x10015

Page 210 M13_DS2_AIS_DETD_R M13_DS2_AIS_DETD[7:1]

0x10016

Page 210 M13_DS2_RAI_DETD_R M13_DS2_RAI_DETD[7:1]

0x10017

Page 211 M13_DS2_LB_DETD_R M13_DS2_LB_DETD[7:1]

0x10018

Page 211 M13_DS2_RSV_RCVD_R M13_DS2_RSV_RCVD[7:1]

0x10019

Page 211 M13_DS2DMX_LOCD_R M13_DS2DMX_LOCD[7:1]

0x1001A

—

0x1001D

RSVD

0x1001E

Page 211 M13_DS1_LOCD_R1 M13_DS1_LOCD[28:25]

0x1001F

Page 211 M13_DS1_LOCD_R2 M13_DS1_LOCD[24:17]

0x10020

Page 211 M13_DS1_LOCD_R3 M13_DS1_LOCD[16:9]

0x10021

Page 211 M13_DS1_LOCD_R4 M13_DS1_LOCD[8:1]

0x10022

Page 212 M13_DS1_AIS_DETD_R1 M13_DS1_AIS_DETD[28:25]

0x10023

Page 212 M13_DS1_AIS_DETD_R2 M13_DS1_AIS_DETD[24:17]

0x10024

Page 212 M13_DS1_AIS_DETD_R3 M13_DS1_AIS_DETD[16:9]

0x10025

Page 212 M13_DS1_AIS_DETD_R4 M13_DS1_AIS_DETD[8:1]

0x10026

Page 212 M13_DS1_LB_DETD_R1 M13_DS1_LB_DETD[28:25]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

233Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10027

Page 212 M13_DS1_LB_DETD_R2 M13_DS1_LB_DETD[24:17]

0x10028

Page 212 M13_DS1_LB_DETD_R3 M13_DS1_LB_DETD[16:9]

0x10029

Page 212 M13_DS1_LB_DETD_R4 M13_DS1_LB_DETD[8:1]

0x1002A

—

0x1002E

RSVD

DS2 and DS1 Status—RO

0x1002F

Page 212 M13_XC_DS2_LOC_R M13_XC_DS2_LOC[7:1]

0x10030

Page 212 M13_XC_DS2_AIS_DET_R M13_XC_DS2_AIS_DET[7:1]

0x10031

Page 213 M13_DS2_OOF_R M13_DS2_OOF[7:1]

0x10032

Page 213 M13_DS2_LOF_R M13_DS2_LOF[7:1]

0x10033

Page 213 M13_DS2_AIS_DET_R M13_DS2_AIS_DET[7:1]

0x10034

Page 213 M13_DS2_RAI_DET_R M13_DS2_RAI_DET[7:1]

0x10035

Page 214 M13_DS2_LB_DET_R M13_DS2_LB_DET[7:1]

0x10036

Page 214 M13_DS2_RSV_RCV_R M13_DS2_RSV_RCV[7:1]

0x10037

Page 214 M13_DS2DMX_LOC_R M13_DS2DMX_LOC[7:1]

0x10038

—

0x1003B

RSVD

0x1003C

Page 214 M13_DS1_LOC_R1 M13_DS1_LOC[28:25]

0x1003D

Page 214 M13_DS1_LOC_R2 M13_DS1_LOC[24:17]

0x1003E

Page 214 M13_DS1_LOC_R3 M13_DS1_LOC[16:9]

0x1003F

Page 214 M13_DS1_LOC_R4 M13_DS1_LOC[8:1]

0x10040

Page 215 M13_DS1_AIS_DET_R1 M13_DS1_AIS_DET[28:25]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

234 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10041

Page 215 M13_DS1_AIS_DET_R2 M13_DS1_AIS_DET[24:17]

0x10042

Page 215 M13_DS1_AIS_DET_R3 M13_DS1_AIS_DET[16:9]

0x10043

Page 215 M13_DS1_LB_DET_R4 M13_DS1_AIS_DET[8:1]

0x10044

Page 215 M13_DS1_LB_DET_R1 M13_DS1_LB_DET[28:25]

0x10045

Page 215 M13_DS1_LB_DET_R2 M13_DS1_LB_DET[24:17]

0x10046

Page 215 M13_DS1_LB_DET_R3 M13_DS1_LB_DET[16:9]

0x10047

Page 215 M13_DS1_LB_DET_R4 M13_DS1_LB_DET[8:1]

0x10048 RSVD

FEAC Loopback Individual Deltas—RO

0x10049

Page 215 M13_DS1_FEAC_LB_DETD_R1 M13_DS3_FLB_DETD M13_DS1_FEAC_LB_DETD[28:25]

0x1004A

Page 215 M13_DS1_FEAC_LB_DETD_R2 M13_DS1_FEAC_LB_DETD[24:17]

0x1004B

Page 215 M13_DS1_FEAC_LB_DETD_R3 M13_DS1_FEAC_LB_DETD[16:9]

0x1004C

Page 215 M13_DS1_FEAC_LB_DETD_R4 M13_DS1_FEAC_LB_DETD[8:1]

FEAC Status, RDL Status, and RDL FIFO—RO

0x1004D

Page 216 M13_DS1_FEAC_LB_DET_R1 M13_DS3_FLB_DET M13_DS1_FEAC_LB_DET[28:25]

0x1004E

Page 216 M13_DS1_FEAC_LB_DET_R2 M13_DS1_FEAC_LB_DET[24:17]

0x1004F

Page 216 M13_DS1_FEAC_LB_DET_R3 M13_DS1_FEAC_LB_DET[16:9]

0x10050

Page 216 M13_DS1_FEAC_LB_DET_R4 M13_DS1_FEAC_LB_DET[8:1]

0x10051

Page 216 M13_RFEAC_CODE_R M13_RFEAC_CODE[5:0]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

235Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10052

Page 216 M13_RDL_STATUS M13_RDL_FLAG M13_RDL_ABORT M13_RDL_NOT_

BYTE M13_RDL_OVFL M13_RDL_FCS_

ERR

0x10053

Page 217 M13_RDL_DATA_R M13_RDL_DATA[7:0]

0x10054

Page 217 M13_RDL_FRAME_SIZE_R M13_RDL_FRAME_SIZE[6:0]

0x10055

Page 217 M13_RHDLC_STATUS_R M13_RHDLC_STATUS[7:0]

0x10056

—

0x10058

RSVD

One Shot Signals—R/Wl

0x10059

Page 217 M13_DS2_FORCE_OOF_R M13_DS2_FORCE_OOF[7:1]

0x1005A

Page 218 M13_CONTROL1 M13_RDL_FRM_

CLR M13_DS3_

FORCE_OOF M13_BIPOL_

ERR

0x1005B RSVD

Block-level Controls—R/W

0x1005C

Page 218 M13_CONTROL2 M13_BPV_IN M13_LOOP_TIME M13_LOOP_T_

TO_R M13_LOOP_

R_TO_T M13_AUTO_

AIS_LOF M13_AUTO_AIS_

OOF M13_AUTO_FLB M13_AUTO_LB

0x1005D

Page 219 M13_CONTROL3 M13_M23_CBP M13_BIPOLAR

0x1005E

Page 219 M13_SP_OFFSET_R M13_NSMI_SP_OFFSET[7:0]

0x1005F

Page 219 M13_SP_D_OFFSET_R M13_NSMI_SP_D_OFFSET[7:0]

M12 MUX’s Control—R/W

0x10060

Page 220 M13_M12_MUX_CONTROL1_R1 M13_M12_MODE1[1:0] M13_MUXCH2_

4_INV1 M13_DS1_E1N1 M13_DS1_LB_REQ[4:1]

0x10061

Page 220 M13_M12_MUX_CONTROL2_R1 M13_SEL_DS1_LB[4:1] M13_RDS1_EDGE[4:1]

0x10062

Page 220 M13_M12_MUX_CONTROL1_R2 M13_M12_MODE2[1:0] M13_MUXCH2_

4_INV2 M13_DS1_E1N2 M13_DS1_LB_REQ[8:5]

0x10063

Page 220 M13_M12_MUX_CONTROL2_R2 M13_SEL_DS1_LB[8:5] M13_RDS1_EDGE[8:5]

0x10064

Page 220 M13_M12_MUX_CONTROL1_R3 M13_M12_MODE3[1:0] M13_MUXCH2_

4_INV3 M13_DS1_E1N3 M13_DS1_LB_REQ[12:9]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

236 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x10065

Page 220 M13_M12_MUX_CONTROL2_R3 M13_SEL_DS1_LB[12:9] M13_RDS1_EDGE[12:9]

0x10066

Page 220 M13_M12_MUX_CONTROL1_R4 M13_M12_MODE4[1:0] M13_MUXCH2_4_INV4 M13_DS1_E1N4 M13_DS1_LB_REQ[16:13]

0x10067

Page 220 M13_M12_MUX_CONTROL2_R4 M13_SEL_DS1_LB[16:13] M13_RDS1_EDGE[16:13]

0x10068

Page 220 M13_M12_MUX_CONTROL1_R5 M13_M12_MODE5[1:0] M13_MUXCH2_4_INV5 M13_DS1_E1N5 M13_DS1_LB_REQ[20:17]

0x10069

Page 220 M13_M12_MUX_CONTROL2_R5 M13_SEL_DS1_LB[20:17] M13_RDS1_EDGE[20:17]

0x1006A

Page 220 M13_M12_MUX_CONTROL1_R6 M13_M12_MODE6[1:0] M13_MUXCH2_4_INV6 M13_DS1_E1N6 M13_DS1_LB_REQ[24:21]

0x1006B

Page 220 M13_M12_MUX_CONTROL2_R6 M13_SEL_DS1_LB[24:21] M13_RDS1_EDGE[24:21]

0x1006C

Page 220 M13_M12_MUX_CONTROL1_R7 M13_M12_MODE7[1:0] M13_MUXCH2_4_INV7 M13_DS1_E1N7 M13_DS1_LB_REQ[28:25]

0x1006D

Page 220 M13_M12_MUX_CONTROL2_R7 M13_SEL_DS1_LB[28:25] M13_RDS1_EDGE[28:25]

0x1006E

Page 220 M13_DS2_RAI_SEND_R M13_DS2_RAI_SEND[7:1]

0x1006F

Page 220 M13_DS2_RSV_SEND_R M13_DS2_RSV_SEND[7:1]

0x10070

Page 221 M13_DS2_MPINV_R M13_DS2_MPINV[7:1]

0x10071

Page 221 M13_DS2_FINV_R M13_DS2_FINV[7:1]

0x10072

Page 221 M13_DS2_P_BER_R M13_DS2_P_BER[7:1]

0x10073

Page 221 M13_DS2M12_EDGE_R M13_DS2M12_EDGE[7:1]

0x10074

Page 221 M13_DS2_FORCE_AIS_R M13_DS2_FORCE_AIS[7:1]

0x10075

—

0x1007A

RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

237Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

M12 DeMUX’s Control—R/W

0x1007B

Page 222 M13_M12_DEMUX_CONTROL1_R1 M13_M12DMX_MODE1[1:0] M13_DEMUXCH2_4_INV1 M13_OUT_TYPE1 M13_TDS1_EDGE[4:1]

0x1007C

Page 222 M13_M12_DEMUX_CONTROL2_R1 M13_DS1_OUT_AIS[4:1]

0x1007D

Page 222 M13_M12_DEMUX_CONTROL1_R2 M13_M12DMX_MODE2[1:0] M13_DEMUXCH2_4_INV2 M13_OUT_TYPE2 M13_TDS1_EDGE[8:5]

0x1007E

Page 222 M13_M12_DEMUX_CONTROL2_R2 M13_DS1_OUT_AIS[8:5]

0x1007F

Page 222 M13_M12_DEMUX_CONTROL1_R3 M13_M12DMX_MODE3[1:0] M13_DEMUXCH2_4_INV3 M13_OUT_TYPE3 M13_TDS1_EDGE[12:9]

0x10080

Page 222 M13_M12_DEMUX_CONTROL2_R3 M13_DS1_OUT_AIS[12:9]

0x10081

Page 222 M13_M12_DEMUX_CONTROL1_R4 M13_M12DMX_MODE4[1:0] M13_DEMUXCH2_4_INV4 M13_OUT_TYPE4 M13_TDS1_EDGE[16:13]

0x10082

Page 222 M13_M12_DEMUX_CONTROL2_R4 M13_DS1_OUT_AIS[16:13]

0x10083

Page 222 M13_M12_DEMUX_CONTROL1_R5 M13_M12DMX_MODE5[1:0] M13_DEMUXCH2_4_INV5 M13_OUT_TYPE5 M13_TDS1_EDGE[20:17]

0x10084

Page 222 M13_M12_DEMUX_CONTROL2_R5 M13_DS1_OUT_AIS[20:17]

0x10085

Page 222 M13_M12_DEMUX_CONTROL1_R6 M13_M12DMX_MODE6[1:0] M13_DEMUXCH2_4_INV6 M13_OUT_TYPE6 M13_TDS1_EDGE[24:21]

0x10086

Page 222 M13_M12_DEMUX_CONTROL2_R6 M13_DS1_OUT_AIS[24:21]

0x10087

Page 222 M13_M12_DEMUX_CONTROL1_R7 M13_M12DMX_MODE7[1:0] M13_DEMUXCH2_4_INV7 M13_OUT_TYPE7 M13_TDS1_EDGE[28:25]

0x10088

Page 222 M13_M12_DEMUX_CONTROL2_R7 M13_DS1_OUT_AIS[28:25]

0x10089

Page 222 M13_M12_DEMUX_CONTROL3 M13_DS2_MODE M13_DS2_FERR_MODE

0x1008A

Page 223 M13_DMDS2_EDGE_R M13_DMDS2_EDGE[7:1]

0x1008B

—

0x10091

RSVD

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

238 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

M23 MUX Co ntrols—R/W

0x10092

Page 223 M13_DS3_CONTROL1 M13_DS3_FINV M13_DS3_MINV M13_DS3_PINV M13_DS3_FORCE_AIS M13_DS3_FORCE_

IDLE M13_TDS3_

FORCE_ALL1 M13_M23CLK_

MODE

0x10093

Page 224 M13_DS3_CONTROL2 M23_STUFF_

MODE M13_NSMI_MODE M13_DS3_P_BER M13_CBIT2_ACT M13_UNUSED_

ACT M13_DS3_RAI_

SEND M13_FEBE_ERR

0x10094

Page 224 M13_TFEAC_CONTROL M13_TFEAC_CTL[1:0] M13_TFEAC_CODE[5:0]

0x10095

Page 225 M13_THDLC_CONTROL1 M13_TDL_BUF1_

END M13_TDL_BUF0_END M13_TDL_ACT M13_TDL_NTRNL M13_TDL_

NTRNL_ACT M13_TDL_FCS

0x10096

Page 225 M13_THDLC_CONTROL2 M13_TDL_BYTE_END[5:0]

0x10097

Page 225 M13_DS2_LB_REQ_R M13_DS2_LB_REQ[7:1]

0x10098

Page 226 M13_SEL_DS2_LB_R M13_SEL_DS2_LB[7:1]

0x10099

Page 226 M13_RDS2_EDGE_R1 M13_RDS2_EDGE[7:1]

0x1009A

Page 226 M13_RDS2_EDGE_R2 M13_DS2ALCO_RTM_EDGE[7:1]

0x1009B

—

0x1009D

RSVD

M23 DeMUX Controls—R/W

0x1009E

Page 226 M13_DS2_OUT_IDLE_R M13_DS2_OUT_IDLE[7:1]

0x1009F

Page 226 M13_DS2_OUT_AIS_R M13_DS2_OUT_AIS[7:1]

0x100A0

Page 227 M13_TDS2_EDGE_R M13_TDS2_EDGE[7:1]

0x100A1

Page 227 M13_RDL_CONTROL M13_RDL_FILL[1:0] M13_RDL_FCS M13_DS3_

MODE M13_RDS3_

EDGE

0x100A2

—

0x100A4

RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

239Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Performance-Monitoring Counters —RO

0x100A5

Page 227 M13_PM_CNT_ACT_R M13_PM_CNT_ACT

0x100A6

Page 227 M13_DS3_FERR_CNT_R1 M13_DS3_FERR_CNT[11:8]

0x100A7

Page 227 M13_DS3_FERR_CNT_R2 M13_DS3_FERR_CNT[7:0]

0x100A8

Page 228 M13_DS3_FEBE_CNT_R1 M13_DS3_FEBE_CNT[13:8]

0x100A9

Page 228 M13_DS3_FEBE_CNT_R2 M13_DS3_FEBE_CNT[7:0]

0x100AA

Page 228 M13_DS3_CPERR_CNT_R1 M13_DS3_CPERR_CNT[13:8]

0x100AB

Page 228 M13_DS3_CPERR_CNT_R2 M13_DS3_CPERR_CNT[7:0]

0x100AC

Page 228 M13_DS3_PERR_CNT_R1 M13_DS3_PERR_CNT[13:8]

0x100AD

Page 228 M13_DS3_PERR_CNT_R2 M13_DS3_PERR_CNT[7:0]

0x100AE

—

0x100B1

RSVD

0x100B2

Page 229 M13_DS2_PERR_CNT7_R1 M13_DS2_PERR_CNT7[12:8]

0x100B3

Page 229 M13_DS2_PERR_CNT7_R2 M13_DS2_PERR_CNT7[7:0]

0x100B4

Page 229 M13_DS2_PERR_CNT6_R1 M13_DS2_PERR_CNT6[12:8]

0x100B5

Page 229 M13_DS2_PERR_CNT6_R2 M13_DS2_PERR_CNT6[7:0]

0x100B6

Page 229 M13_DS2_PERR_CNT5_R1 M13_DS2_PERR_CNT5[12:8]

0x100B7

Page 229 M13_DS2_PERR_CNT5_R2 M13_DS2_PERR_CNT5[7:0]

0x100B8

Page 229 M13_DS2_PERR_CNT4_R1 M13_DS2_PERR_CNT4[12:8]

0x100B9

Page 229 M13_DS2_PERR_CNT4_R2 M13_DS2_PERR_CNT4[7:0]

0x100BA

Page 229 M13_DS2_PERR_CNT3_R1 VDS2_PERR_CNT3[12:8]

0x100BB

Page 229 M13_DS2_PERR_CNT3_R2 M13_DS2_PERR_CNT3[7:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

240 Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x100BC

Page 229 M13_DS2_PERR_CNT2_R1 M13_DS2_PERR_CNT2[12:8]

0x100BD

Page 229 M13_DS2_PERR_CNT2_R2 M13_DS2_PERR_CNT2[7:0]

0x100BE

Page 229 M13_DS2_PERR_CNT1_R1 M13_DS2_PERR_CNT1[12:8]

0x100BF

Page 229 M13_DS2_PERR_CNT1_R2 M13_DS2_PERR_CNT1[7:0]

0x100C0

—

0x100C5

RSVD

0x100C6

Page 229 M13_DS2_FERR_CNT7_R M13_DS2_FERR_CNT7[7:0]

0x100C7

Page 229 M13_DS2_FERR_CNT6_R M13_DS2_FERR_CNT6[7:0]

0x100C8

Page 229 M13_DS2_FERR_CNT5_R M13_DS2_FERR_CNT5[7:0]

0x100C9

Page 229 M13_DS2_FERR_CNT4_R M13_DS2_FERR_CNT4[7:0]

0x100CA

Page 229 M13_DS2_FERR_CNT3_R M13_DS2_FERR_CNT3[7:0]

0x100CB

Page 229 M13_DS2_FERR_CNT2_R M13_DS2_FERR_CNT2[7:0]

0x100CC

Page 229 M13_DS2_FERR_CNT1_R M13_DS2_FERR_CNT1[7:0]

0x100CD

Page 229 M13_BPV_CNT_R1 M13_BPV_CNT[23:16]

0x100CE

Page 229 M13_BPV_CNT_R2 M13_BPV_CNT[15:8]

0x100CF

Page 229 M13_BPV_CNT_R3 M13_BPV_CNT[7:0]

0x100D0

Page 230 M13_EXZ_CNT_R1 M13_EXZ_CNT[23:16]

0x100D1

Page 230 M13_EXZ_CNT_R2 M13_EXZ_CNT[15:8]

0x100D2

Page 230 M13_EXZ_CNT_R3 M13_EXZ_CNT[7:0]

0x100D3

—

0x100FE

RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

241Agere Systems Inc.

11 M13/M23 MUX/DeMUX Registers (continued)

Table 312. M13 Register Address Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TDL Buffer Selection—R/W

0x100FF

Page 230 M13_TDL_BUFFER_R M13_TDL_BUFFER

TDL Buffers—R/W, When M13_TDL_BUFFER = 0

0x10100

—

0x1013F

Page 230

M13_TDL_0DATA_R[0—63] M13_TDL_0DATA[0—63][7:0]

When M13_TDL_BUFFER = 1

0x10100

—

0x1013F

Page 230

M13_TDL_1DATA_R[0—63] M13_TDL_1DATA[0—63][7:0]

0x10140

—

0x101FF

RSVD

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

242 Agere Systems Inc.

12 28-Channel Framer Registers

Table of Con t ents

Contents Page

12 28-Channel Framer Registers .........................................................................................................................242

12.1 Framer Global Register Descriptions.......................................................................................................246

12.2 Arbiter (Framer) Global Registers............................................................................................................248

12.3 Performance Monitor Global Registers....................................................................................................250

12.4 HDLC Global Configuration and Status Registers ...................................................................................257

12.5 System Interface Global Registers...........................................................................................................261

12.6 Signaling Global Registers.......................................................................................................................267

12.7 Frame Formatter (Transmit Framer) Global Register...............................................................................271

12.8 Facility Data Link Global Registers ..........................................................................................................272

12.9 Supermapper Framer Per Link Configuration and Status Registers........................................................272

12.9.1 Signaling Per Link Registers ......................................................................................................... 272

12.10 Performance Monitor Per Link Registers ...............................................................................................278

12.11 Receive Facility Data Link Configuration and Status Registers .............................................................293

12.12 Transmit Facility Data Link Configuration and Status Registers............................................................295

12.13 System Interface, Arbiter, and Frame Formatter Mapping.....................................................................298

12.14 System Interface Per Link Registers......................................................................................................299

12.15 Arbiter Framer Per Link Registers..........................................................................................................300

12.16 Frame Formatter Per Link Registers......................................................................................................305

12.17 Line Decoder/Encoder Per Link Registers.............................................................................................307

12.18 Line Encoder/Decoder Per Link Registers.............................................................................................308

12.19 HDLC Per Channel Configuration and Status Registers........................................................................309

12.20 28-Channel Framer Block Register Map................................................................................................316

Tables Page

Table 313. FRM_SFGR1, Superframer Global Register 1 (R/W)..........................................................................246

Table 314. FRM_SFGR2, Superframer Global Register 2 (R/W)..........................................................................247

Table 315. FRM_SFGR3, Superframer Global Register 3 (RO)............................................................................248

Table 316. FRM_SFGSR4, Superframer Global Register 4 (R/W)........................................................................248

Table 317. FRM_FGR1, Framer Global Register 1 (R/W).....................................................................................248

Table 318. FRM_FGR2, Framer Global Register 2 (R/W).....................................................................................249

Table 319. FRM_FGR3, Framer Global Register 3 (R/W).....................................................................................249

Table 320. FRM_FGR4, Framer Global Register 4 (COR)....................................................................................249

Table 321. FRM_FGR5, Framer Global Register 5 (COR)....................................................................................250

Table 322. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)...................................................250

Table 323. FRM_PMGR1, Performance Monitor Global Register 1 (COR)...........................................................251

Table 324. FRM_PMGR2, Performance Monitor Global Register 2 (COR)...........................................................251

Table 325. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)............................................................251

Table 326. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)............................................................252

Table 327. FRM_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W)...........................................252

Table 328. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)............................................................253

Table 329. FRM_PMGR7, Performance Monitor Global Register 7 (R/W)............................................................253

Table 330. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)............................................................253

Table 331. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)............................................................253

Table 332. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)........................................................254

Table 333. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)........................................................254

Table 334. FRM_PMGR12, Performance Monitor Global Register 12 (R/W)........................................................255

Table 335. FRM_PMGR13, Performance Monitor Global Register 13 (R/W)........................................................256

Table 336. FRM_PMGR14, Performance Monitor Global Register 14 (R/W)........................................................256

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

243Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table of Conten ts (continued)

Tables Page

Table 337. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)........................................................257

Table 338. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)........................................................257

Table 339. FRM_HGR1, Transmit HDLC Global Registe r 1 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..257

Table 340. FRM_HGR2, Transmit HDLC Global Registe r 2 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..257

Table 341. FRM_HGR3, Transmit HDLC Global Registe r 3 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..258

Table 342. FRM_HGR4, Transmit HDLC Global Registe r 4 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..258

Table 343. FRM_HGR5, Transmit HDLC Global Registe r 5 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..258

Table 344. FRM_HGR6, Transmit HDLC Global Registe r 6 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..258

Table 345. FRM_HGR7, Transmit HDLC Global Registe r 7 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..259

Table 346. FRM_HGR8, Transmit HDLC Global Registe r 8 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..259

Table 347. FRM_HGR9, Transmit HDLC Global Registe r 9 (R/W) .... ....... ...... .................... ...... ....... ...... ....... ...... ..259

Table 348. FRM_HGR10, Transmit HDLC Global Register 10 (R/W) ...................................................................259

Table 349. FRM_HGR11, Transmit HDLC Global Register 11 (RO)......................................................................259

Table 350. FRM_HGR12, Transmit HDLC Global Register 12 (R/W) ...................................................................260

Table 351. FRM_HGR13, Transmit HDLC Global Register 13 (R/W) ...................................................................260

Table 352. FRM_HGR14, Transmit HDLC Global Register 14 (R/W) ...................................................................260

Table 353. FRM_HGR15, Receive HDLC Global Register 15 (R/W) ....................................................................260

Table 354. FRM_HGR16, Receive HDLC Global Register 16 (R/W) ....................................................................260

Table 355. FRM_HGR17, Receive HDLC Global Register 17 (R/W) ....................................................................260

Table 356. FRM_HGR18, Receive HDLC Global Register 18 (R/W) ....................................................................261

Table 357. FRM_HGR19, Receive HDLC Global Register 19 (R/W) ....................................................................261

Table 358. FRM_HGR20, Receive HDLC Global Register 20 (R/W) ....................................................................261

Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W) ................................................................261

Table 360. FRM_SYSGR2, System Interface Global Register 2 (R/W) ................................................................263

Table 361. FRM_SYSGR3, System Interface Global Register 3 (R/W) ................................................................263

Table 362. FRM_SYSGR4, System Interface Global Register 4 (R/W) ................................................................264

Table 363. FRM_SYSGR5, System Interface Global Register 5 (R/W) ................................................................264

Table 364. FRM_SYSGR6, System Interface Global Register 6 (COR) ...............................................................264

Table 365. FRM_SYSGR7, System Interface Global Register 7 (COR) ...............................................................265

Table 366. FRM_SYSGR8, System Interface Global Register 8 (R/W) ................................................................265

Table 367. FRM_SYSGR9, System Interface Global Register 9 (R/W) ................................................................265

Table 368. FRM_SYSGR10—FRM_SYSGR14, System Interface Global Register 10—14 (R/W).......................266

Table 369. FRM_SYSGR15, System Interface Global Register 15 (COR) ...........................................................266

Table 370. FRM_SYSGR16, System Interface Global Register 16 (R/W) ............................................................266

Table 371. FRM_SGR1, Receive Signaling Global Register 1 (R/W) ...................................................................267

Table 372. FRM_SGR2, Receive Signaling Global Register 2 (R/W) ...................................................................267

Table 373. FRM_SGR3, Receive Signaling Global Register 3 (R/W) ...................................................................268

Table 374. FRM_SGR4, Receive Signaling Global Register 4 (RO).....................................................................268

Table 375. FRM_SGR5, Receive Signaling Global Register 5 (RO).....................................................................268

Table 376. FRM_SGR6, Receive Signaling Global Register 6 .............................................................................269

Table 377. FRM_SGR7, Receive Signaling Global Register 7 (R/W) ...................................................................269

Table 378. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)...................................................................270

Table 379. FRM_FFGR1, Transmit Framer Global Register 1 (R/W)....................................................................271

Table 380. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W) ..................................................272

Table 381. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W)..................................................272

Table 382. Receive Path Signaling Register Addressing Map ..............................................................................272

Table 383. Receive Path Signaling Registers Address Indexing...........................................................................272

Table 384. FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W).................................273

Table 385. FRM_RSLR32, Receive Signaling Link Register 32 (COR) ................................................................274

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

244 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table of Conten ts (continued)

Tables Page

Table 386. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) .................................................................274

Table 387. Transmit Path Signaling Register Addressing Map..............................................................................275

Table 388. Transmit Path Signaling Registers Address Indexing..........................................................................275

Table 389. FRM_TSLR0—FRM_TSLR31, Transmit Signaling Link Registers 0—31 (R/W).................................276

Table 390. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)................................................................277

Table 391. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W).................................................................277

Table 392. Performance Monitor Per Link Register Addressing Map....................................................................278

Table 393. Performance Monitor Per Link Register Address Indexing..................................................................279

Table 394. FRM_PMLR1, Performance Monitor Link Register 1 (R/W)................................................................279

Table 395. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)................................................................279

Table 396. FRM_PMLR3, Performance Monitor Link Register 3 (R/W)................................................................280

Table 397. FRM_PMLR4, Performance Monitor Link Register 4 (COR)...............................................................280

Table 398. FRM_PMLR5, Performance Monitor Link Register 5 (COR)...............................................................287

Table 399. FRM_PMLR6, Performance Monitor Link Register 6 (COR)...............................................................289

Table 400. FRM_PMLR7, Performance Monitor Link Register 7 (COR)...............................................................289

Table 401. FRM_PMLR8, Performance Monitor Link Register 8 (COR)...............................................................290

Table 402. FRM_PMLR9, Performance Monitor Link Register 9 (COR)...............................................................290

Table 403. FRM_PMLR10, Performance Monitor Link Register 10 (COR)...........................................................290

Table 404. FRM_PMLR11, Performance Monitor Link Register 11 (COR)............................................................290

Table 405. FRM_PMLR12, Performance Monitor Link Register 12 (COR)...........................................................290

Table 406. FRM_PMLR13, Performance Monitor Link Register 13 (COR)...........................................................291

Table 407. FRM_PMLR14, Performance Monitor Link Register 14 (COR)...........................................................292

Table 408. FRM_PMLR15, Performance Monitor Link Register 15 (COR)...........................................................292

Table 409. FRM_PMLR16, Performance Monitor Link Register 16 (COR)...........................................................292

Table 410. FRM_PMLR17, Performance Monitor Link Register 17 (COR)...........................................................292

Table 411. FRM_PMLR18, Performance Monitor Link Register 18 (COR) ...........................................................292

Table 412. FRM_PMLR19, Performance Monitor Link Register 19 (COR)...........................................................293

Table 413. FRM_PMLR20, Performance Monitor Link Register 20 (COR)...........................................................293

Table 414. Receive Facility Data Link Register Addressing Map ..........................................................................293

Table 415. Receive Path Facility Data Link Registers Address Indexing..............................................................294

Table 416. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO)......................................294

Table 417. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W).........................................................................294

Table 418. FRM_RFDLLR7, Receive FDL Link Register 7 (RO)...........................................................................294

Table 419. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)........................................................................295

Table 420. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W).........................................................................295

Table 421. Transmit Facility Data Link Register Addressing Map .........................................................................295

Table 422. Transmit Path Facility Data Link Registers Address Indexing .............................................................295

Table 423. FRM_TFDLLR1—FRM_TFDLR5, Transmit FDL Link Registers 1—5 (COR).....................................295

Table 424. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W).........................................................................296

Table 425. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W).........................................................................297

Table 426. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW) ................................................................297

Table 427. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W).........................................................................297

Table 428. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map.................................298

Table 429. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing...............................298

Table 430. FRM_SYSLR1, System Interface Link Register 1 (R/W).....................................................................299

Table 431. FRM_SYSLR2, System Interface Link Register 2 (R/W).....................................................................299

Table 432. FRM_SYSLR3—FRM_SYSLR6, System Interface Link Registers 3—6 (R/W) ..................................299

Table 433. FRM_ARLR1, Arbiter Link Register 1 (R/W)........................................................................................300

Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W)........................................................................................301

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

245Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table of Conten ts (continued)

Tables Page

Table 435. FRM_ARLR3, Arbiter Link Register 3 (R/W)........................................................................................304

Table 436. FRM_FFLR1, Frame Formatter Link Register 1 (R/W)........................................................................305

Table 437. FRM_FFLR2, Frame Formatter Link Register 2 (R/W)........................................................................306

Table 438. Line Decoder Per LInk Register Addressing Map................................................................................307

Table 439. Line Decoder Per Link Registers Address Indexing ............................................................................307

Table 440. Line Encoder Per Link Register Addressing Map ................................................................................307

Table 441. Line Encoder Per Link Registers Address Indexing.............................................................................307

Table 442. FRM_LDLR1, Line Decoder Link Register 1 (R/W) .............................................................................308

Table 443. FRM_LDLR2, Line Encoder Link Register 2 (R/W) .............................................................................308

Table 444. HDLC Per Channel Register Addressing Map.....................................................................................309

Table 445. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W).....................................................................309

Table 446. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W).....................................................................309

Table 447. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W).....................................................................310

Table 448. FRM_HCR4, Transmit HDLC Channel Register 4 (RO)......................................................................311

Table 449. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W).....................................................................311

Table 450. FRM_HCR6, Transmit HDLC Channel Register 6 (WO) .....................................................................312

Table 451. FRM_HCR7, Transmit HDLC Channel Register 7 (RO)......................................................................312

Table 452. FRM_HCR8, Receive HDLC Channel Register 8 (R/W) .....................................................................312

Table 453. FRM_HCR9, Receive HDLC Channel Register 9 (R/W) .....................................................................312

Table 454. FRM_HCR10, Receive HDLC Channel Register 10 (R/W) .................................................................313

Table 455. FRM_HCR11, Receive HDLC Channel Register 11 (RO)....................................................................314

Table 456. FRM_HCR12, Receive HDLC Channel Register 12 (R/W) .................................................................314

Table 457. FRM_HCR13, Receive HDLC Channel Register 13 (RO)...................................................................315

Table 458. FRM_HGR14, Receive HDLC Channel Register 14 (COR)................................................................315

Table 459. Framer Register Map...........................................................................................................................316

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

246 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.1 Framer Global Register Description s

Table 313. FRM_SFGR1, Superframer Global Register 1 (R/W)

Address Bit Name Function Reset Default

0x80000 15 FRM_SW_TRN Superframer Configuration Modes.

0 = transport mode.

1 = switching mode.

14:13 FRM_LC_

CNTRL[1:0] Line Encoder/Decoder Control.

00 = line encoder and line decoder blocks are not used in either

the framer Tx or Rx paths. This setting is used in the

following switching modes:

■STS-3/STS-1/DS3/DS2 to CHI/parallel system bus/SMI.

■STS-3/STS-1/DS3 to line data rate mode.

01 = line decoder is used in the Rx path and line encoder is

used in th e Tx path. This s etting is used i n the framer-only

switching modes:

■DS1 to CHI/parallel system bus/SMI channelized.

10 = line decoder is used in the Tx path and line encoder is

used in the Rx path. This setting is used in the following

transport modes:

■DS1 to DS2/DS3/ST S-1/STS-3 .

11 = reserved.

12 FRM_LOOP_

TIMING Loop Timing.

0 = superframer is programmed for normal mode.

1 = superframer is programmed for loop timing; i.e., all

received line clocks are looped back to the correspond-

ing transmit line clocks.

11 FRM_DS1_

CEPTN DS1/CEPT Terminal Count.

0 = superframer is programmed for CEPT mode, which has

a maximum of 21 operational links. Links 22 to 28 are

disabled.

1 = superframer is programmed for DS1 mode, which has a

maximum of 28 operational links.

Note: For fewer links or DS1/CEPT mixed modes, use

FRM_TC_EN and FRM_TC[7:0] (Table 318) parame-

ters to select an accurate link count.

10 FRM_PLL_

BYPAS PLL Bypass.

0 = internal PLL is used to generate the line clock in the

transmit path.

1 = the PLL is bypassed. External line clock is required in

this mode.

9:1 RSVD Reserved. Must write to 0. 0

0 FRM_LG_BUF_

MODE HDLC Buffer Mode.

0 = HDLC channel buffers are configured for 128-byte stor-

age. Up to 64 (32) channels can be supported in the

switching (transport) mode.

1 = HDLC channel buffers are combined for 512-byte stor-

age. Up to 16 (8) channels can be supported in the

switching (transport) mode.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

247Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 314. FRM_SFGR2, Superframer Global Register 2 (R/W)

Address Bit Name Function Reset

Default

0x80001 15:14 RSVD Reserved. Must write to 0. 0

13 FRM_TP_SIG_PWDN Trans mit Path Receive Signaling Powerdown. When set

to 0, the transmit path receive signaling block for the trans-

port mode is powered down.

12 FRM_RP_SIG_PWDN Receive Path Transmit Signaling Powerdown. When set

to 0, the receive path transmit signaling block for the trans-

port mode is powered down.

11 FRM_TP_RDL_PWDN T ransmit Path Receive Datalink Powerdown. When set to

0, the transmit path receive data link block for the transport

mode is powered down.

10 FRM_RP_TDL_PWDN Rece ive Pat h T r ansmi t Data link P owerdo wn. When set to

0, the receive path transmit data link block for the transport

mode is powered down.

9 FRM_TP_RH_PWDN T ransmit Path Receive HDLC Powerdown. When set to 0,

the transmit path receive HDLC block for the transport mode

is powered down.

8FRM_RP_TH_PWDNReceive Path T ransmit HDLC Powerdown. When set to 0,

the receive path transmit HDLC block for the transport mode

is powered down.

7 FRM_TS_PWDN Transmit Path System Block Powerdown. When set to 0,

the transmit path system block is powered down. 0

6 FRM_RS_PWDN Receive Path System Block Powerdown. When set to 0,

the receive path system block is powered down. 0

5 FRM_TP_PM_PWDN Transmit Path Performance Monitor Powerdown. When

set to 0, the transmit path performance monitor block is pow-

ered down.

4 FRM_RP_FF_PWDN Receive Path Frame Formatter Powerdown. When set to

0, the receive path frame formatter block is powered down. 0

3 FRM_TP_RA_PWDN Transmit Path Receive Aligner Powerdown. When set to

0, the transmit path receive aligner block is powered down. 0

2:0 RSVD Reserved. Must write to 0. 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

248 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 315. FRM_SFGR3, Superframer Global Register 3 (RO)

Table 316. FRM_SFGSR4, Superframer Global Register 4 (R/W)

12.2 Arbiter (Framer) Global Register s

Table 317. FRM_FGR1, Framer Global Register 1 (R/W)

Address Bit Name Function Reset

Default

0x80002 15 FRM_RP_SIG A 1 indicates the change of signaling state; FIFO con-

tains state change information. 0

14 FRM_AR_IS A 1 indicates the FRM_AR_IS block has generated an

interrupt. 0

13 FRM_TP_RDL_IS A 1 indicates the FRM_TP_RDL_IS block has generated

an interrupt. 0

12 FRM_TP_TDL_IS A 1 indicates the FRM_TP_TDL_IS block has generated

an interrupt. 0

11 FRM_RH_IS A 1 indicates the FRM_RH_IS block has generated an

interrupt. 0

10 FRM_TH_IS A 1 indicates the FRM_TH_IS block has generated an

interrupt. 0

9 FRM_TS_IS A 1 indicates the FRM_TS_IS block has generated an

interrupt. 0

8 FRM_RS_IS A 1 indicates the FRM_RS_IS block has generated an

interrupt. 0

7 FRM_TP_PM_IS A 1 indicates the FRM_TP_PM_IS block has generated

an interrupt. 0

6 FRM_RP_PM_IS A 1 indicates the FRM_RP_PM_IS block has generated

an interrupt. 0

5 FRM_RP_RDL_IS A 1 indicates the FRM_RP_RDL_IS block has generated

an interrupt. 0

4 FRM_RP_TDL_IS A 1 indicates the FRM_RP_TDL_IS block has generated

an interrupt. 0

3:0 RSVD Reserved. Reads 0. 0

Address Bit Name Function Reset

Default

0x80003 15 RSVD Reserved. Must write to 0. 0

14:12 FRM_VERSION[2:0] Superframer Version Number. 000

11:0 RSVD Reserved. Must write to 0. 0x000

Address Bit Name Function Re set

Default

0x80010 15 FRM_DIS_LHSCD Disable Loss of High-Speed Clock Detection.

1 = disable the loss of high-speed clock detection within

the framer.

14:0 RSVD Reserved. Must write to 0. —

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

249Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 318. FRM_FGR2, Framer Global Register 2 (R/W)

Table 319. FRM_FGR3, Framer Global Register 3 (R/W)

Table 320. FRM_FGR4, Framer Global Register 4 (COR)

Address Bit Name Function Reset

Default

0x80011 15 FRM_TC_EN Terminal Count Enable.

0 = terminal count disabled use defaults.

1 = terminal count enabled.

14:8 RSVD Reserved. Must write to 0. 0000000

7:0 FRM_TC[7:0] Terminal Count. When enabled, the link counter will count

from 1 to the terminal count. The terminal count determines

the number of links available for use. The operational links are

link 1 to the link determined by the terminal count. By default,

the count is determined by the option bit, FRM_DS1_CEPTN

(Table 313 on page 246). In an application, where there is a

mix of DS1 and CEPT links or a small number of links, the ter-

minal count may be set by enabling FRM_TC_EN and setting

the terminal count, FRM_TC[7:0].

Note: Minimum terminal count value is 4.

00011100

Address Bit Name Function Reset

Default

0x80012 15 FRM_TPSSE_IM Transmit Path System Synchronization Error Inter-

rupt Mas k. A transmit path system synchronization error

interrupt is generated when synchron ization is lost

between the receiv e system interf ace and the tra nsmi t

path line clock. FRM_TPSSE_IM is a global mask for the

interrupt status from each link. The individual link transmit

path system error interrupt status bits,

FRM_TPSSEI[28:1] are summarized in FRM_AR_IS bit

14 of FRM_SFGR3 (Table 315 on page 248).

0 = allows any synchronization error, as reported in the

synchronization status registers, to generate an inter-

rupt.

1 = masks any synchronization error, as reported in the

synchronization status registers, from generating an

interrupt.

14:0 RSVD Reserved. Must write to 0. 000000000

000000

Address Bit Name Function Reset

Default

0x80014 15:0 FRM_TPSSEI[16:1] Transmit Path System Synchr onization Error Inter-

rupt.

1 = indicates a transmit path system synchronization

error on links 16 to 1.

00X0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

250 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 321. FRM_FGR5, Framer Global Register 5 (COR)

12.3 Performance Monitor Global Registers

Table 322. FRM_PMGR1_B, Performance Monitor Global Register 1_B (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address Bit Name Function Reset

Default

0x80015 15:12 RSVD Reserved. Must write to 0. 000

11:0 FRM_TPSSEI[28:17] Transmit Path System Synchronization Error Inter-

rupt.

1 = indicates a transmit path system synchronization

error on links 28 to 17.

000000000

000

Address*Bit Name Function Reset

Default

0x80P20 15 FRM_SEC_SEL Framer PMRESET Source. The source of the performance

monitoring interval (generally one second) may be selected to

be internal to the framer block or external to the framer block.

0 = external.

1 = internal.

14 FRM_GLB_PL_CFG Global/Per-Link Configuration. This bit is used to select glo-

bal RAC/RDC or per-link RAC/RDC. This bit selects global

reframe upon excessive CRC errors or per-link reframe upon

excessive CRC errors. When FRM_GLB_PL_CFG = 0, global

RAC/RDC is selected. The configurations in FRM_RAC

(0x80P32 bits [13:11]) and FRM_RDC (0x80P32 bits [10:8])

are used for all the applicable links. Reframe upon excessive

CRC errors is determined by FRM_CRCRFEN (0x80P32,

bit 5), which affects all the applicable links. When

FRM_GLB_PL_CFG = 1, per-link RAC/RDC is selected. The

configurations in FRM_PL_RAC (0x8LP94 bits [5:3]) and

FRM_PL_RDC (0x8LP94 bits [2:0]) are used for each individ-

ual link. Reframe upon excessive CRC errors is determined by

FRM_PL_CRCRFEN (0x8LP94, bit 8) for each individual link.

13 RSVD Reserved. Must write to 0. 000

12:0 FRM_CT125[12:0] Framer Terminal Count. This is the terminal count for an

internal 125 µs timer that is multiplied by 8000 to determine

the internal performance monitoring interval. This count is

based on the TDM clock speed. The default count is based on

a 51.84 MHz clock. This terminal count is calculated by the fol-

lowing equation:

Timer terminal count = (125 µs)(fTDM clock).

0x1950

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

251Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 323. FRM_PMGR1, Performance Monitor Global Register 1 (COR)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 324. FRM_PMGR2, Performance Monitor Global Register 2 (COR)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function Reset

Default

0x80P30 15:2 RSVD Reserved. Must write to 0. 0x0000

1FRM_DETECTTest-Pattern Dete ct. A 1 indicates the pattern detector has

locked onto the pattern specified by the FRM_PTRN_SEL[3:0]

(Table 336 on page 256) configuration bits. There is only one

test-pattern detector. See O.151, Section 2. Both framed and

unframed test-pattern generation/detection are supported.

0 FRM_PTRNBER Test-Pattern Bit Error. A 1 indicates the receive framer pattern

detector has found one or more single-bit errors in the pattern on

to which it is currently locked. There is only one test-pattern BER

counter for all links.

Address*Bit Name Function Re set

Default

0x80P31 15:0 FRM_TPERR_CT[15:0] Test Pattern Error Count Register. This register con-

tains the 16-bit count of test-pattern errors. 0

Table 325. FRM_PMGR3, Performance Monitor Global Register 3 (R/W)

Address*Bit Name Function Re set

Default

0x80P32 15:14 RSVD Reserved. Must write to 0. 00

13:11 FRM_RAC[2:0] CEPT Mode RAI Activation Count†. 001

10:8 FRM_RDC[2:0] CEPT Mode RAI Deactivation Count†. RAC and RDC

can be set to meet various standards. 001

7 FRM_FSFBEEN FS Frame Bit Error Enable. Allows a signaling frame (FS)

bit error to set the FBE status bit, FRM_FBE (Table 398 on

page 287).

In DDS, a 0 means do not count TS24 framing and FS as

FBEs; a 1 means count TS24 framing and Fs as FBEs.

0 = FS bit errors disabled.

1 = FS bit errors enabled.

6FRM_CMFRFENCEPT Multiframe Reframe Enable.

0 = CEPT CRC-4 multiframe reframe disabled.

1 = CEPT CRC-4 multiframe reframe enabled. A research

for multiframe alignment is initiated upon a loss of

CEPT CRC-4 multiframe alignment.

5 FRM_CRCRFEN CRC Reframe Enable.

0 = CRC errors do not cause a reframe or LOF condition.

1 = the receive performance monitor will force a reframe

and LOF condition on excessive CRC errors.

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

† FRM_RACFRM_RDC Standard.

TMXF2815 5/ 51 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

252 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

12 28-Channel Framer Registers (continued)

Table 326. FRM_PMGR4, Performance Monitor Global Register 4 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 327. FRM_PMGR5, Performance Monitor Global Register 5—PMGR5 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

0x80P32 4:3 FRM_CEPTAISM[1:0] CEPT AIS Mode.

00 = option 0: G.775, Section I.2; G.965, Section 16.1.2.

01 = option 1: G.775, Section 5.2.

10 = option 2: G.775, Section I.2.

11 = option 3: G.775, Section I.2.

2 FRM_DS1AISM DS1 AIS Mode.

0 = option 0: T1.231, Section 6.1.2.2.3, T1.403, Section H,

G.775, Section 5.4.

1 = option 1: G.775, Section I.2.

1 FRM_ESFRAIM ESF RAI Mode.

0 = alternating eight ones followed by eight zeros.

1 = all ones.

0 FRM_RAICLR Clear RAI on Reception of DS1 Idle Signal.

0 = ignore DS1 idle signal for RAI clearing.

1 = clear failure on reception of DS1 idle signal: ANSI

T1.231, Section 6.2.2.2.1.

Address*Bit Name Function Reset

Default

0x80P33 15:0 FRM_SFSEST[15:0] SF Severely Errored Second Threshold for All SF For-

matted Channels.

Note: A bursty errored second will be recorded if the number

of events is greater than the errored second threshold

but less than the severely errored second threshold.

There is a separate threshold for ESF and SF because

of the bit error provisioning in ESF (Ft or Fs).

0x0140

Address*Bit Name Function Reset

Default

0x80P34 15:0 FRM_DCT[15:0] DS1 Excessive CRC Threshold—Default 320. This register

sets the 1 s CRC threshold at which an excessive CRC error con-

dition is reported, and the 1 s CRC threshold at which a reframe

may be for ce d.

0x0140

Table 325. FRM_PMGR3, Performance Monitor Global Register 3 (R/W) (continued)

Address*Bit Name Function Reset

Default

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

253Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 328. FRM_PMGR6, Performance Monitor Global Register 6 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 329. FRM_PMGR7, Performance Monitor Global Register 7 (R/W)

These bits enable the errored events used to determine errored and severely errored seconds in the DS1 modes.

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 330. FRM_PMGR8, Performance Monitor Global Register 8 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 331. FRM_PMGR9, Performance Monitor Global Register 9 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function Reset

Default

0x80P35 15:0 FRM_ESFSEST[15:0] ESF Severely Errored Second Threshold for All ESF

Formatted Channels. A bursty errored second will be

recorded if the number of events is greater than the errored

second threshold but less than the severely errored second

threshold.

0x0140

Address*Bit Name Function Reset

Default

0x80P36 15:9 RSVD Reserved. Must write to 0. 0x00

8FRM_DSEFDS1 Severely Errored Frame Enable. See FRM_SEFS (Table 412 on

page 293). 0

7 FRM_DLFA DS1 Loss of Frame Alignment Enable. 0

6 FRM_DRFA DS1 Remote Frame Alarm Enable. 0

5FRM_DSLIPDS1 Slip Enable. 0

4FRM_DLOSDS1 Loss of Signal Enable. 0

3FRM_DAISDS1 Alarm Indication Signal Enable. 0

2 FRM_DCRC DS1 CRC-6 Error Enable. 0

1FRM_DFSDS1 Fs Framing Bit Error Enable (SF Only). 0

0FRM_DFTDS1 Ft Framing Bit Error Enable (SF and ESF). 0

Address*Bit Name Function Reset

Default

0x80P37 15:0 FRM_CCT[15:0] CEPT Excessive CRC Threshold—Default 915. This register

sets the 1 s CRC threshold at which an excessive CRC error

condition is reported, and the 1 s CRC threshold at which a

reframe may be forced.

0x0393

Address*Bit Name Function Reset

Default

0x80P38 15:0 FRM_CSEST[15:0] CEPT Severely Errored Second Threshold for All CEPT

Formatted Channels. 0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

254 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 332. FRM_PMGR10, Performance Monitor Global Register 10 (R/W)

These bits enable the errored events used to determine errored and severely errored seconds in the CEPT modes.

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 333. FRM_PMGR11, Performance Monitor Global Register 11 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function Reset

Default

0x80P39 15 FRM_CSA6_F CEPT Sa6 = F Enable and Sa5 = 1. (Reception of AIS.) 1

14 FRM_CSA6_E CEPT Sa6 = E Enable and Sa5 = 1. (FC3 and FC4.) 1

13 FRM_CSA6_C CEPT Sa6 = C Enable and Sa5 = 1. (LOS/LFA.) 1

12 FRM_CSA6_8 CEPT Sa6 = 8 Enable and Sa5 = 1. (Loss of power.) 1

11 FRM_CSA6_1X CEPT Sa6 = 001x Event Enable. 1

10 FRM_CSA6_X1 CEPT Sa6 = 00x1 Event Enable. 1

9FRM_CEBITCEPT E bit = 0 Event Enable. 1

8FRM_CLMFACEPT Loss of Multiframe Alignment Enable. 1

7 FRM_CLFA CEPT Loss of Frame Alignment Enable. 1

6 FRM_CRFA CEPT Remote Frame Alarm Enable. 1

5FRM_CSLIPCEPT Slip Enable. 1

4FRM_CLOSCEPT Loss of Signal Enable. 1

3FRM_CAISCEPT Alarm Indication Signal Enable. 1

2 FRM_CCRC CEPT CRC-4 Error Enable. 1

1 FRM_CNOTFAS CEPT Non-FAS Bit Error Enable. 1

0FRM_CFASCEPT FAS Bit Error Enable. 1

Address*Bit Name Function Reset

Default

0x80P3A 15:0 FRM_CRET[15:0] Continuous Received E-Bit Threshold—Default 991. This

CRE bit status indication.

0x03DF

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

255Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 334. FRM_PMGR12, Performance Monitor Global Register 12 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address*Bit Name Function Reset

Defau

0x80P3B 15 FRM_CRAI_AIS Send RAI Upon Detection of AIS Enable in CEPT

Mode. 0

14 FRM_CRAI_OOF Send RAI Upon Detection of OOF Enable in CEPT

Mode. 0

13 FRM_CRAI_LOS Send RAI Upon Detection of LOS Enable in CEPT

Mode. 0

12 FRM_CRAI_SA6EQC Send RAI Upon Detection of Sa6 = (0xC) Enable in

CEPT Mode. 0

11 FRM_CRAI_SA6EQ8 Send RAI Upon Detection of Sa6 = (0x8) Enable in

CEPT Mode. 0

10 FRM_CRAI_CRCTX Send RAI Upon Detection of CRCTX Enable in CEPT

Mode. 0

9 FRM_CRAI_LTS0MFA Send RAI Upon Detection of LTS0MF A Enable in CEPT

Mode. 0

8 FRM_CRAI_LTS16MFA Send RAI Upon Detection of LTS16MFA Enable in

CEPT Mode. 0

7 FRM_CRAI_8MSEX Send RAI Upon Detection of 8 ms Timer Expiration

Enable in CEPT Mode. 0

6 SPLIT_400MS_100MS_EN Distinguishing Between CEPT CRC4 with 400 ms

Timer and 100 ms Timer Enable. When

SPLIT_400MS_100MS_EN = 0, there is no distinction

between CEPT CRC4 with 100 ms timer and 400 ms

timer. FRM_CRAI_CRCTX (0x80P3B, bit 10),

FRM_CRAI_LTS0MFA (0x80P3B, bit 9), and

FRM_CRAI_8MSEX (0x80P3B, bit 7) apply to any link that

is configured either as CEPT CRC4 with a 400 ms timer or

a 100 ms timer. When SPLIT_400MS_100MS_EN = 1,

FRM_CRAI_CRCTX (0x80P3B, bit 10),

FRM_CRAI_LTS0MFA (0x80P3B, bit 9), and

FRM_CRAI_8MSEX (0x80P3B bit, 7) apply only to links

that are configured as CEPT CRC4 witha 400 ms timer.

Links configured as CEPT CRC4 with a 100 ms timer are

determined by the configuration in bits

FRM_CRAI_CRCTX_100 ms (0x80P21, bit 10),

FRM_CRAI_LTS0MFA_100 ms (0x80P21, bit 9), and

FRM_CRAI_8MSEX_100 ms (0x80P21, bit 7).

5:3 RSVD Reserved. Must write to 0. 0

2 FRM_DSRAI_LOS Send RAI Upon Detection of LOS Enable in DS1 Mode. 0

1 FRM_DSRAI_OOF Send RAI Upon Detec tion of OO F E nable in DS1 Mode. 0

0 FRM_DSRAI_AIS Send RAI Upon Detection of AIS Enable in DS1 Mode. 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

256 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 335. FRM_PMGR13, Performance Monitor Global Register 13 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 336. FRM_PMGR14, Performance Monitor Global Register 14 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Address* Bit Name Function Reset

Default

0x80P3C 15:4 RSVD Reserved. Must write to 0. 0x000

3FRM_CFBE_MODECEPT FBE Mode.

0 = count only FBEs received in FAS frame.

1 = count FBEs received in both FAS and NOTFAS frames.

2 FRM_CEBIT_LTS0MFA Set E Bits Upon Detection of LTS0MFA Enable (CEPT

Only). 0

1 FRM_CEBIT_ESMF Set E Bits Upon Detection of an Errored CEPT_CRC4

SMF (Submultiframe) Enable. 0

0FRM_CEBIT_CRCTXSet E Bits Upon Detection of CRCTX Enable (CEPT

Only). 0

Address* Bit Name Function Reset

Default

0x80P3D 15:12 RSVD Reserved. Must write to 0. 0x0

11 FRM_PTRN_EN Enables the Detector Circuitry. FRM_PTRN_LNK[4:0]

should be set to 1 before enabling the detection circuitry. 0

10 FRM_PTRN_INV Receive Pattern Normal/Invert Mode. Selects w h eth e r t o

check for the selected pattern or its inverse.

0 = selected pattern.

1 = inverse.

9 FRM_PTRN_FRMT Receive Patter n Framed/ Unframed Mode. Selects moni-

toring for either framed or unframed test pattern.

0 = unframed.

1 = framed.

8:4 FRM_PTRN_LNK[4:0] Pattern Detector Link Select. 5-bit link selection to indi-

cate which link to monitor for test patterns. 0

3:0 FRM_PTRN_SEL[3:0] Receive Patter n Sel ect .

0000 = pattern detector deactivate.

0001 = MARK (all ones AIS).

0010 = QRSS (220 – 1 with zero suppression).

0011 = 25 – 1.

0100 = 63(26 – 1).

0101 = 511(29 – 1) (V.52).

0110 = 29 – 1.

0111 = 2047(211 – 1) (O.151).

1000 = 211 – 1 (reversed) .

1001 = 215 – 1 (O.151).

1010 = 220 – 1 (V.57).

1011 = 220 – 1 (CB113/CB114).

1100 = 223 – 1 (O.151).

1101 = 1:1 (alternating).

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

257Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 337. FRM_PMGR15, Performance Monitor Global Register 15 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

Table 338. FRM_PMGR16, Performance Monitor Global Register 16 (R/W)

* P = 0x0 for the receive path, and P = 0x1 for the transmit path.

12.4 HDLC Global Configuration and Status Reg is ters

Table 339. FRM_HGR1, Transmit HDLC Global Register 1 (R/W)

Table 340. FRM_HGR2, Transmit HDLC Global Register 2 (R/W)

Address* Bit Name Function Reset

Default

0x80P3E 15:0 FRM_LN_IS[16:1] Per-Link PM Summary Interrupts for Links 16 Down

to 1. 0x0000

Address* Bit Name Function Reset

Default

0x80P3F 15:12 RSVD Reserved. Must write to 0. 0x0

11:0 FRM_LN_IS[28:17] Per-Link PM Summary Interrupts for Links 28 Down

to 17. 0x000

Address Bit Name Function Reset

Default

0x80140 15:10 RSVD Reserved. Must write to 0. 0x00

9:0 FRM_HTTHRSH0[9:0] HDLC Transmit FIFO Threshold 0. These bits indicate

the threshold levels for the Tx FIFOs. When a channel is

enabled and the number of bytes in its FIFO decrements

to this value, its FRM_HTTHRSH (Table 448 on

page 311) bit is set (optionally causes interrupt).

FRM_HTTHRSH0[9:0] or FRM_HTTHRSH1[9:0] is

selected on a per-channel basis with the

FRM_HTTHRSEL (Table 447 on page 310) parameter.

0x000

Address Bit N ame Function Reset

Default

0x80141 15:10 RSVD Reserved. Must write to 0. 0x00

9:0 FRM_HTTHRSH1[9:0] HDLC Transmit FIFO Threshold 1. These bits indicate

the threshold levels for the Tx FIFOs. When a channel is

enabled and the number of bytes in its FIFO decrements

to this value, its FRM_HTTHRSH bit is set (optionally

causes interrupt). FRM_HTTHRSH0[9:0] or

FRM_HTTHRSH1[9:0] is selected on a per-channel basis

with the FRM_HTTHRSEL (Tabl e 447 on page 310)

parameter.

0x000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

258 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 341. FRM_HGR3, Transmit HDLC Global Register 3 (R/W)

Table 342. FRM_HGR4, Transmit HDLC Global Register 4 (R/W)

Table 343. FRM_HGR5, Transmit HDLC Global Register 5 (R/W)

Table 344. FRM_HGR6, Transmit HDLC Global Register 6 (R/W)

Address Bit Name Function Reset

Default

0x80142 15:8 RSVD Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR0[7:0] Transparent Mode Transmit Idle Char 0. These bits are

used in tra ns pare nt mo de. They repr es ent the fi rst 8-bi t pat -

tern the transmitter should send when there is no data

available in the FIFO. One of the four patterns can be

selected on a per-channel basis with the

FRM_HXPIDLE[1:0] (Table 448 on page 311) parameter.

0x00

Address Bit Name Function Reset

Default

0x80143 15:8 RSVD Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR1[7:0] Transparent Mode Transmit Idle Char 1. These bits are

used in t ran s pa re n t mo d e. T hey re pr esent the se co nd 8-b it

pattern the transmitter will send when there is no data avail-

able in the FIFO. One of the four patterns can be selected

on a per-channel basis with the FRM_HXPIDLE[1:0]

(Table 448 on page 311 ) parameter.

0x00

Address Bit Name Function Reset

Default

0x80144 15:8 RSVD Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR2[7:0] Transparent Mode Transmit Idle Char 2. These bits are

used in transparent mode. They represent the third 8-bit

pattern the transmitter will send when there is no data avail-

able in the FIFO. One of the four patterns can be selected

on a per-channel basis with the FRM_HXPIDLE[1:0]

(Table 447 on page 310) parameter.

0x00

Address Bit Name Function Reset

Default

0x80145 15:8 RSVD Reserved. Must write to 0. 0x00

7:0 FRM_TXICHAR3[7:0] Transparent Mode Transmit Idle Char 3. These bits are

used in transparent mode. They represent the fourth 8-bit

pattern the transmitter will send when there is no data avail-

able in the FIFO. One of the four patterns can be selected

on a per-channel basis with the FRM_HXPIDLE[1:0]

(Table 447 on page 310) parameter.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

259Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 345. FRM_HGR7, Transmit HDLC Global Register 7 (R/W)

Table 346. FRM_HGR8, Transmit HDLC Global Register 8 (R/W)

Table 347. FRM_HGR9, Transmit HDLC Global Register 9 (R/W)

Table 348. FRM_HGR10, Transmit HDLC Global Register 10 (R/W)

Table 349. FRM_HGR11, Transmit HDLC Global Register 11 (RO)

Address Bit Name Function Reset

Default

0x80146 15:5 RSVD Reserved. Must write to 0. 0x000

4:0 FRM_FCNT0[4:0] HDLC Flag Count 0. These values are the number of

additio nal idle fla gs to be sent betw een HDLC pac ke ts.

One of the four values can be selected on a per-channel

basis with the FRM_CFLAGS[1:0] (Table 447 on

page 310) parameter.

00000

Address Bit Name Function Reset

Default

0x80147 15:5 RSVD Reserved. Must write to 0. 0x000

4:0 FRM_FCNT1[4:0] HDLC Flag Count 1. These values are the number of

additio nal idle fla gs to be sent betw een HDLC pac ke ts.

One of the four values can be selected on a per-channel

basis with the FRM_CFLAGS[1:0] parameter.

00000

Address Bit Name Function Reset

Default

0x80148 15:5 RSVD Reserved. Must write to 0. 0x000

4:0 FRM_FCNT2[4:0] HDLC Flag Count 2. These valu es are the number of

additional idle flags to be sent between HDLC packets.

One of the four values can be selected on a per-channel

basis with the FRM_CFL AGS [1:0] (Table 447 on

page 310) parameter.

00000

Address Bit Name Function Reset

Default

0x80149 15:5 RSVD Reserved. Must write to 0. 0x000

4:0 FRM_FCNT3[4:0] HDLC Flag Count 3. These values are the number of

additio nal idle fla gs to be sent betw een HDLC pac ke ts.

One of the four values can be selected on a per-channel

basis with the FRM_CFLAGS[1:0] parameter.

00000

Address Bit Name Function Reset

Default

0x8014A 15:0 FRM_TH_IS[15:0] Transmit HDLC Interrupt Summary. This bitmap shows

what channels have interrupts. This register maps chan-

nels 15—0 to bits 15:0.

0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

260 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 350. FRM_HGR12, Transmit HDLC Global Register 12 (R/W)

Table 351. FRM_HGR13, Transmit HDLC Global Register 13 (R/W)

Table 352. FRM_HGR14, Transmit HDLC Global Register 14 (R/W)

Table 353. FRM_HGR15, Receive HDLC Global Register 15 (R/W)

Table 354. FRM_HGR16, Receive HDLC Global Register 16 (R/W)

Table 355. FRM_HGR17, Receive HDLC Global Register 17 (R/W)

Address Bit Name Function Reset

Default

0x8014B 15:0 FRM_TH_IS[31:16] Transmit HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps channels 31—16 to bits 15:0.

0x0000

Address Bit Name Function Reset

Default

0x8014C 15:0 FRM_TH_IS[47:32] Transmit HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps channels 47—32 to bits 15:0.

0x0000

Address Bit Name Function Reset

Default

0x8014D 15:0 FRM_TH_IS[63:48] Transmit HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps channels 63—48 to bits 15:0.

0x0000

Address Bit Name Function Reset

Default

0x80040 15:10 RSVD Reserved. Must write to 0. 0x00

9:0 FRM_HRTHRSH0[9:0] Indicates the Threshold Levels for the Rx FIFOs.

When a channel is enabled and its FIFO count incre-

ments to this value, its FRM_HRTHRSH (Table 455 on

page 314) status bit is set. FRM_HRTHRSH0 or

FRM_HRTHRSH1 is selected on a per-channel basis

with the FRM_RTHRSEL (Table 454 on page 313)

parameter.

0x000

Address Bit Name Function Reset

Default

0x80041 15:10 RSVD Reserved. Must write to 0. 0x00

9:0 FRM_HRTHRSH1[9:0] Indicates the Threshold Levels for the Rx FIFOs.

When a channel is enabled and its FIFO count incre-

ments to this value, its FRM_HRTHRSH status bit is

set. FRM_HRTHRSH0[9:0] or FRM_HRTHRSH1[9:0]

is selected on a per-channel basis with the

FRM_RTHRSEL (Table 454 on page 313) parameter.

0x000

Address Bit Name Function Reset

Default

0x80042 15:0 FRM_RH_IS[15:0] Receive HDLC Interrupt Summary. This bitmap

shows what channels have interrupts. This register

maps channels 15—0 to bits 15:0.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

261Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 356. FRM_HGR18, Receive HDLC Global Register 18 (R/W)

Table 357. FRM_HGR19, Receive HDLC Global Register 19 (R/W)

Table 358. FRM_HGR20, Receive HDLC Global Register 20 (R/W)

12.5 System Interface Global Registers

Address Bit Name Function Reset

Default

0x80043 15:0 FRM_RH_IS[31:16] Receive HDLC Interrupt Summary. This bitmap shows what

channels have interrupts. This register maps channels 31—16

to bits 15:0.

Address Bit Name Function Reset

Default

0x80044 15:0 FRM_RH_IS[47:32] Receive HDLC Interrupt Summary. This bitmap shows what

channels have interrupts. This register maps channels 47—32

to bits 15:0.

Address Bit Name Function Reset

Default

0x80045 15:0 FRM_RH_IS[63:48] Receive HDLC Interrupt Summary. This bitmap shows what

channels have interrupts. This register maps channels 63—48

to bits 15:0.

Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W)

Address Bit Name Function Reset

Default

0x80050 15:12 FRM_SYSMOD[3:0] System Interface Mode Associated Signaling Mode.

0000 = 2.048 Mbits/s CHI.

0001 = 4.096 Mbits/s CHI.

0010 = 8.192 Mbits/s CHI.

0100 = 19.44 Mbits/s PSB (device 0 mode).

0101 = 19.44 Mbits/s PSB (device 1 mode).

0110 = 19.44 Mbits/s PSB (device 2 mode).

1000 = SMI.

All others: Reserved.

0000

11 FRM_ASM System Interface Mode Associated Signaling Mode.

0 = CHI is configured to carry payload data only.

In PSB mode, transmit signaling is 3-stated, and receive sig-

naling ign or ed.

1 = CHI is configured to carry both payload data and signaling

information. Each time slot consists of 16 bits, where

8 bits are data and the remaining 8 bits are signaling infor-

mation. CHI must be programmed for 4.096 Mbits/s or

8.192 Mbits/s modes.

In PSB mode, transmit signaling is driven and receive signal-

ing is forwarded to the signaling block.

TMXF2815 5/ 51 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

262 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

12 28-Channel Framer Registers (continued)

0x80050 10 FRM_CMS CHI Clock Mode. This bit is only applicable in the CHI mode.

Otherwise, it should be set to 0.

0 = CHI clock and CHI data have the same rate.

1 = CHI clock is twice the rate of CHI data.

9 FRM_CHIDTS CHI Dual Time-Slot Mode. This bit is only applicable in the

CHI 4.096 Mbits/s (no ASM) and 8.192 Mbits/s (without ASM)

modes.

0 = enables 32 contiguous time slots.

1 = enables double time-slot mode in which the transmit CHI

drives data for one time slot and 3-states for the subse-

quent time slot.

8 FRM_STUFFL/

FRM_LNKSTART Stuff Position/Link Start. CHI modes only: determines the

position of the stuffed time slots in conjunction with the byte

offset.

0 = SDDDSDDDSDDDS.. . . . . . . (TS0—TS31).

1 = SDDDDDD. . . . . . . SSSSSSS (TS0—TS31).

NSMI modes only: this bit determines how links are numbered

on the NSMI. Internally, links are numbered starting at 1.

0 = NSMI link numbering starts at 0.

1 = NSMI link numbering starts at 1.

7 FRM_AISLFA Syst em AIS on Loss of Frame Alignme nt.

0 = no action.

1 = system AIS is transmitted when the receive framer or the

mapper loss of frame alignment (MFA for DS1, BFA for

CEPT) is detected.

6 FRM_AISCRCT System AIS on CEP T Timer Expiration .

0 = no action.

1 = system AIS is transmitted when the receive framer loss of

multiframe alignment timer expiration is detected. (CEPT

only.)

5 FRM_DNOTFAS CEPT Dual NOTFAS. This bit is applicable in all system

modes.

0 = FAS and NOTFAS time slots are transmitted to the sys-

tem. The receive system interface expects both FAS and

NOTFAS time slots.

1 = NOTFAS is transmitted twice to the system (in the NOT-

FAS and FAS time slots). The receive system expects

time slots 0 to carry NOTFAS that is repeated twice.

Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W) (continued)

Address Bit Name Function Reset

Default

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

12 28-Channel Framer Registers (continued)

263Agere Systems Inc.

Table 360. FRM_SYSGR2, System Interface Global Register 2 (R/W)

Table 361. FRM_SYSGR3, System Interface Global Register 3 (R/W)

0x80050 4 FRM_TFSCKE System Interface Transmit Frame Sync Clock Ed ge Select.

0 = transmit frame sync is sampled on the falling edge of

tran sm it cl oc k.

1 = transmit frame sync is sampled on the rising edge of

tran sm it cl oc k.

In PSB mode, this bit also determines the clock edge used to

drive data. The sampling point of transmit frame sync defines

the zero offset for CHI mode.

3 FRM_FSPOL Frame Sync Polarity.

0 = transmit and receive frame sync is active-low.

1 = transmit and receive frame sync is active-high.

2:0 RSVD Reserved. Must write to 0. 0

Address Bit Name Function Reset

Default

0x80051 15 FRM_HWYENA Transmit System Interface Highway Enable.

0 = transmit data is forced into a high-impedance state for all

transmitted time slots. Receive system ignores receive

data and inserts the idle code in all time slots transmitted

to the line. This allows the framer to be fully configured

before transmission.

1 = transmit and receive data is enabled.

14 FRM_RSTDONE

(Read Only) Framer Reset Status.

0 = indicates internal reset is still in process.

1 = indicates internal reset is complete.

Generally, the FRM_HWYENA bit should not be set to1 until

this bit reads 1.

13:0 RSVD Reserved. Must write to 0. 0

Address Bit Name Function Reset

Default

0x80052 15:8 FRM_STUFF[7:0] Stuffed Time-Slot Code. 7F

7:0 FRM_IDLE[7:0] CHI Time-Slot Loopback Idle Code. 7F

Table 359. FRM_SYSGR1, System Interface Global Register 1 (R/W) (continued)

Address Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

264 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 362. FRM_SYSGR4, System Interface Global Register 4 (R/W)

Table 363. FRM_SYSGR5, System Interface Global Register 5 (R/W)

Table 364. FRM_SYSGR6, System Interface Global Register 6 (COR)

Address Bit Name Function Reset

Default

0x80053 15 FRM_STSSLB CHI Time-Slot System Loopback.

0 = no action.

1 = receive CHI time slot is looped back to the system. Idle

code, FRM_IDLE[7:0] (Table 361 on page 263), is

inserted in place of the looped back time slot to the

line.

14 FRM_STSLLB CHI Time-Slot Line Loopback.

0 = no action.

1 = transmit CHI time slot is looped back to the line. Idle

code, FRM_IDLE[7:0], is inserted in place of the

looped back time slot to the system.

13 RSVD Reserved. Must write to 0. 0

12:8 FRM_TSLBA[4:0] CHI Time-Slot Loopback Address. 00000

7:5 RSVD Reserved. Must write to 0. 0

4:0 FRM_TSLBL[4:0] CHI Time-Slot Loopback Link Number. 00000

Address Bit Name Function Reset

Default

0x80054 15 FRM_TS_DPAR Transmit PSB Data Parity. This bit is only applicable in

the parallel system bus mode. Otherwise, it should be set

to zero.

0 = odd data parity is transmitted by the system.

1 = even data parity is transmitted by the system.

14 FRM_TS_SPAR Transmit Signa ling Parity. This bit applies to the signaling

information in the parallel system bus mode. It also deter-

mines the parity for CHI ASM mode. Otherwise, it should

be set to 0.

0 = odd signali ng par ity is tra ns mit ted by the sy s tem.

1 = even signaling parity is transmitted by the system.

13:0 RSVD Reserved. Must write to 0. 0

Address Bit Name Function Reset

Default

0x80055 15:0 RSVD Reserved. Must write to 0. 0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

265Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 365. FRM_SYSGR7, System Interface Global Register 7 (COR)

Table 366. FRM_SYSGR8, System Interface Global Register 8 (R/W)

Table 367. FRM_SYSGR9, System Interface Global Register 9 (R/W)

Address Bit Name Function Reset

Default

0x80056 15:1 RSVD Reserved. Must write to 0. 0x0

0 FRM_TPSB_FS_IS Transmit PSB Frame Sync Error Interrupt. A 1 indicates

a frame sync error was detected in PSB mode. The frame

sync was either detected when it should not have been

(misplaced) or was not detected when it should have been

(missing). This bit is cleared on read/write unless the condi-

tion that set it still exists after the read.

Address Bit Name Function Reset

Default

0x80057 15:1 RSVD Reserved. Must write to 0. 0

0 FRM_PSB_FS_IM Transmit PSB Frame Sync Interrupt Mask. A 1 prevents

the FRM_TPSB_FS_IS (Table 365 on page 265) status

from causing an interrupt. A 0 allows the interrupt.

Address Bit Name Function Reset

Default

0x80150 15 FRM_RS_DPAR Receive PSB Data Parity Select. This bit is only applica-

ble in the parallel system bus interface mode. Otherwise, it

should be set to 0.

0 = odd data parity is expected by the receive system.

1 = even data parity is expected by the receive system.

14 FRM_RS_SPAR Receive Signaling Parity Select. This bit applies to the

signaling information in the parallel system bus mode. It

also determines the parity for CHI ASM mode. Otherwise,

it should be set to 0.

0 = odd signaling parity is expected by the receive system.

1 = even signaling parity is expected by the receive system.

13 FRM_RFSCKE System Interface Receive Frame Sync Clock Edge

Select.

0 = receive frame sync (and data) is sampled on the falling

edge of receive clock.

1 = receive frame sync (and data) is sample on the rising

edge of receive clock.

In parallel system bus mode, this bit also determines the

clock edge used to sample data.

In CHI mode, the sample point of frame sync defines the

zero offset for the CHI.

12:0 RSVD Reserved. Must write to 0. 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

266 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 368. FRM_SYSGR10—FRM_SYSGR14, System Interface Global Register 10—14 (R/W)

Table 369. FRM_SYSGR15, System Interface Global Register 15 (COR)

Table 370. FRM_SYSGR16, System Interface Global Register 16 (R/W)

Address Bit Name Function Reset

Default

0x80151

—

0x80155

15:0 RSVD Reserved. Must write to 0. 0x0000

Address Bit Name Function Reset

Default

0x80156 15 FRM_DPAR_IS Data Parity Interrupt. In PSB mode, a 1 indicates a data parity

error was detected. This bit is cleared on read unless the con-

dition that set it still exists after the read.

14 FRM_SPAR_IS Signaling Parity Interrupt. In PSB mode, a 1 indicates a sig-

naling parity error was detected. In CHI ASM mode, a 1 indi-

cates a parity error was detected.

This bit is cleared on read unless the condition that set it still

exists after the read.

13:1 RSVD Reserved. Must write to 0. 0

0 FRM_PSB_FS_IS Receive PSB Frame Sync Interrupt. A 1 indicates a frame

sync error was detected in PSB mode. The frame sync was

either detected when it should not have been (misplaced) or

was not detected when it should have been (missing). This bit

is cleared on read unless the condition that set it still exists

after the read.

Address Bit Name Function Reset

Default

0x80157 15 FRM_DPAR_IM Data Parity Interrupt Mask. A 1 prevents the FRM_DPAR_IS

status from causing an interrupt. A 0 allows the interrupt. 1

14 FRM_SPAR_IM Signaling Parity Interrupt Mask. A 1 prevents the

FRM_SP AR_IS status from causing an interrupt. A 0 allows the

interrupt.

13:1 RSVD Reserved. Must write to 0. 0

0 FRM_PSB_FS_IM Receive PSB Frame Sync Interrupt Mask. A 1 prevents the

FRM_PSB_FS_IS status from causing an interrupt. A 0 allows

the interrupt.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

267Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.6 Signaling Global Registers

Table 371. FRM_SGR1, Receive Signaling Global Register 1 (R/W)

Table 372. FRM_SGR2, Receive Signaling Global Register 2 (R/W)

Address Bit Name Function Reset

Default

0x80060 15 FRM_R_TSAISHG System AIS for Handling Groups. When set to 1, this

configuration bit forces AIS to the system interface for

those signaling bits which correspond to a handling

group, which is out of alignment. A 0 disables this fea-

ture. This feature is only applied to those links which are

enabled for byte sync mapping and handling groups

using the per-link signaling configuration registers.

14:10 FRM_R_LINKCNT[4:0] Receive Link Count. Indicates the number of links ser-

viced by the signaling block. This value should be set to

28 when the Supermapper is interfacing with only DS1

links; it should be set to the actual number of links active

for mixed mode applications.

9 RSVD Reserved. Must write to 0. 0

8:6 FRM_TEST_BIT[2:0] Test Bits. 000

5:2 RSVD Reserved. Must write to 0. 0

1 FRM_R_AFZFBE Automatic Signaling Freeze on Framing Bit Errors.

Set to 1 in order to freeze signaling register updates

based on framing bit errors.

0 RSVD Reserved. Must write to 0.

Address Bit Name Function Reset

Default

0x80061 15 FRM_R_SCOSEN Receive Signaling Change of State FIFO Enable.

When set to 1, this configuration bit enables the mainte-

nance of the signaling change of state FIFO. When set to

0, no entries will be made into the FIFO. This bit applies

to all of the links. If an individual time slot is programmed

for no signaling, then no entries will be made for that time

slot. Also, if the signaling source in the receive path is set

to host, then no entries will be made for that time slot.

14:10 RSVD Reserved. Must write to 0. 0

9:0 FRM_R_SCOSDTH[9:0] Receive Signaling Change of State FIFO Depth

Threshold. This number can be programmed from 0 to

672. If the number of entries in the signaling change of

state FIFO exceeds the value programmed here, then

the associated interrupt status bit will be set.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

268 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 373. FRM_SGR3, Receive Signaling Global Register 3 (R/W)

Table 374. FRM_SGR4, Receive Signaling Global Register 4 (RO)

Table 375. FRM_SGR5, Receive Signaling Global Register 5 (RO)

Address Bit Name Function Reset

Default

0x80062 15:0 FRM_R_SCOSTTH[15:0] Receive Signaling Change of State FIFO Timer

Threshold. This number can be programmed from 0 to

0xFFFF. The value indicates the number of 125 µs

increments that the timer counts before interrupting the

processor . The associated interrupt status bit will be set

only if there are valid entries in the FIFO. When set to 0,

the timer is disabled and no interrupt will be generated.

The maximum timer setting is 8 s.

0x0000

Address Bit Name Function Reset

Default

0x80063 15:14 FRM_R_COSFIFOS[1:0] Receive Signaling Change of State FIFO Status.

These bits are located at the address for the signaling

change of state FIFO. These status bits have the fol-

lowing definitions:

01 = the entry being read is the last valid entry.

11 = the entry being read is not the last valid entry.

00 = the entry being read is not valid and should be

ignored.

13:9 FRM_R_COSFIFOL[4:0] COS Link Number. These bits are located at the

address for the signaling change of state FIFO. This

number indicates the particular link from which a sig-

naling change of state has been detected.

8:4 FRM_R_COSFIFOTS[4:0] COS Time-Slot Number. These bits are located at

the address for the signaling change of state FIFO.

This number indicates the particular time slot in which

a signaling change of state has been detected.

3:0 FRM_R_COSFIFOSIG[3:0] New Signaling Code. These bits are located at the

address for the signaling change of state FIFO. This

value indicates the new signaling state received.

Address Bit Name Function Reset

Default

0x80064 15:1 RSVD Reserved. 0X0000

0 FRM_R_COSDTHS Receive Signaling Change of State FIFO Depth Thresh-

old Overflow Status. This status bit reflects the actual

depth of the FIFO entries as compared to the threshold pro-

grammed by the host. When set to 1, the threshold is cur-

rently exceeded. When set to 0, the number of FIFO entries

is less than the programmed threshold.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

269Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 376. FRM_SGR6, Receive Signaling Global Register 6

Table 377. FRM_SGR7, Receive Signaling Global Register 7 (R/W)

Address Bit Name Function Reset

Default

0x80065 15:3 RSVD Reserved. Reads 0. 0

2 FRM_R_COSDTHI Receive Signaling Change of State FIFO Depth Thresh-

old Overflow Interrupt. This interrupt status bit will be set

when the programmed threshold for the FIFO capacity has

been exceeded. This interrupt bit can be reset based on a

clear-on-read protocol, which is provisioned in the Super-

mapper global registers.

1 FRM_R_COSTTHI Receive Signaling Change of State FIFO T imer Thresh-

old Interrupt. This interrupt status bit will be set when the

programmed interrupt timer has expired and there are valid

entries in the FIFO to be processed. This interrupt bit can be

reset based on a clear-on-read protocol, which is provisioned

in the Supermapper global registers.

0 FRM_R_COSOFI Receive Signaling Change of State FIFO Overflow Inter-

rupt. This interrupt status bit will be set when the signaling

change of state FIFO overflows. The contents of the FIFO

will be lost and the programmed threshold for the FIFO

capacity has been exceeded. This interrupt bit can be reset

based on a clear-on-read protocol, which is provisioned in

the Supermapper global registers.

Address Bit Name Function Reset

Default

0x80066 15:3 RSVD Reserved. Reads 0. 0

2 FRM_R_COSDTHM Receive Signaling Change of State FIFO Depth Thresh-

old Overflow Interrupt Mas k. The corresponding interrupt

status bit will cause a processor interrupt if this bit is set to 0.

The corresponding interrupt status bit will be masked from

causing a processor interrupt if this bit is set to 1.

1FRM_R_COSTTHMReceive Signaling Change of State FIFO Timer Thresh-

old Interrupt Mask. The corresponding interrupt status bit

will cause a processor interrupt if this bit is set to 0. The cor-

responding interrupt status bit will be masked from causing a

processor interrupt if this bit is set to 1.

0 FRM_R_COSOFM Receive Signaling Change of State FIFO Overflow Inter-

rupt Mask. The corresponding interrupt status bit will cause

a processor interrupt if this bit is set to 0. The corresponding

interrupt status bit will be masked from causing a processor

interrupt if this bit is set to 1.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

270 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 378. FRM_SGR8, Transmit Signaling Global Register 8 (R/W)

Address Bit Name Function Reset

Default

0x80160 15 RSVD Reserved. Must write to 0. 0

14:10 FRM_T_LINKCNT[4:0] Transmit Link Count. Indicates the number of links ser-

viced by the signaling block. This value should be set to 28

when the Supermapper is interfacing with only DS1 links; it

should be set to the actual number of links active for mixed

mode applications.

9:6 RSVD Reserved. Must write to 0. 0000

5 FRM_T_SUBZERO Substitute Zero. A 1 forces signaling data to be 0000 for

those time slots which have a signaling state mode of no

signaling. This only applies to the signaling data trans-

ferred to the VT mapper.

4 FRM_T_FAS_NOTFAS FAS/NOTFAS Transmission. Used to force alignment of

the CEPT TS16 multiframe to a FAS or NOTFAS frame. A

0 indicates alignment to a FAS frame. A 1 indicates align-

ment to a NOTFAS frame.

3:2 RSVD Reserved. Must write to 0. 0 0

1 FRM_T_AFZFBE Automatic Signaling Freeze on Fr aming Bit Errors. Set

to 1 in order to freeze signaling register updates based on

framing bit erro rs.

0RSVDReserved. Must write to 0. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

271Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.7 Frame Formatter (Transmit Framer) Global Register

Table 379. FRM_FFGR1, Transmit Framer Global Register 1 (R/W)

Address Bit Name Function Reset

Default

0x80170 15 FRM_TXFSOOF Transmit Frame Sync when Out-Of-Frame Valid in

Transport Modes Only.

0 = do not transmit FS when out of frame. (FS is present

when in frame.)

1 = transmit an arbitrary FS when out of frame.

14 FRM_TPSYSSYNC FAS/NFAS Alignment on the Receive System Data

(CEPT Mode Only).

0 = do not align the transmit framer to the incoming

system data.

1 = align the transmit framer to the incoming system data.

13:12 RSVD Reserved. Must write to 0. 0

11 FRM_PTRN_EN Tr ansmit Pattern.

0 = pattern generator off.

1 = pattern generator on.

10 FRM_PTRN_INV Transmit Pattern Normal/Invert Mode.

This bit inverts the pattern.

0 = normal.

1 = invert.

9 FRM_PTRN_FRMT Transmit Pattern Framed/Unframed Mode.

This bit selects either a framed (1) or unframed (0) pat-

tern.

8:4 FRM_PTRN_LNK[4:0] Pattern Generator Link Select.

5-bit link selection to indicate link for pattern insertion. 00001

3:0 FRM_PTRN_SEL[3:0] Transmit Patt ern Select.

0000 = pattern generator deactivated.

0001 = mark (all ones AIS).

0010 = QRSS (220 – 1 with zero suppression).

0011 = 25 – 1.

0100 = 63 (265 – 1).

0101 = 511(29 – 1) (V.52).

0110 = 29 – 1.

0111 = 2047 (211 – 1) (O.151).

1000 = 211 – 1 (reversed).

1001 = 215 – 1 (O.151).

1010 = 220 – 1 (V.57) .

1011 = 220 – 1 (CB113/CB114).

1100 = 223 – 1 (O.151 ).

1101 = 1:1 (alternating).

1110 = reserved.

1111 = reserved.

0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

272 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.8 Facility Data Link Global Registers

Table 380. FRM_FDLGR1, Receive Facility Data Link Global Register 1 (R/W)

Table 381. FRM_FDLGR2, Transmit Facility Data Link Global Register 2 (R/W)

12.9 Supermapper Framer Per Link Configuration and Status Registers

12.9.1 Signaling Per Link Registers

Table 382. Receive Path Signaling Register Addressing Map

* L and R represent hexidecimal digits used for abs olu te addressing in Table 384, Table 385, and Table 386.

Table 383. Receive Path Signaling Registers Address Indexing

Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

Address Bit Name Function Reset

Default

0x80090 15:0 RSVD Reserved. Must write to 0. 0x0000

Address Bit Name Function Reset

Default

0x801A1 15:0 RSVD Reserved. Must write to 0. 0x0000

Address Pins (ADDR15—ADDR0)

1514131211109 876543210

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP = 0 0 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0

L* R* —

Link L R Link L R Link L R Link L R

1 0x00x2 8 0x10x0160x20x0240x30x0

2 0x00x4 9 0x10x2170x20x2250x30x2

3 0x00x6100x10x4180x20x4260x30x4

4 0x00x8110x10x6190x20x6270x30x6

5 0x00xA120x10x8200x20x8280x30x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA — — —

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC — — —

— — — 15 0x1 0xE 23 0x2 0xE — — —

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

273Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 384. FRM_RSLR0—FRM_RSLR31, Receive Signaling Link Registers 0—31 (R/W)

* See Table 383 on page 272 for values of L and R.

Notes:

Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.

For DS1 links, address locations 1 through 24 will contain valid data.

For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will be

accepted and stored in signaling registers.

Address*Bit Name Function Reset

Default

0x8LR00 6:0 FRM_RPSR0[6:0] Time Slot 0 Receive Signaling Data. 0000000

0x8LR01 6:0 FRM_RPSR1[6:0] Time Slot 1 Receive Signaling Data. 0000000

0x8LR02 6:0 FRM_RPSR2[6:0] Time Slot 2 Receive Signaling Data. 0000000

0x8LR03 6:0 FRM_RPSR3[6:0] Time Slot 3 Receive Signaling Data. 0000000

0x8LR04 6:0 FRM_RPSR4[6:0] Time Slot 4 Receive Signaling Data. 0000000

0x8LR05 6:0 FRM_RPSR5[6:0] Time Slot 5 Receive Signaling Data. 0000000

0x8LR06 6:0 FRM_RPSR6[6:0] Time Slot 6 Receive Signaling Data. 0000000

0x8LR07 6:0 FRM_RPSR7[6:0] Time Slot 7 Receive Signaling Data. 0000000

0x8LR08 6:0 FRM_RPSR8[6:0] Time Slot 8 Receive Signaling Data. 0000000

0x8LR09 6:0 FRM_RPSR9[6:0] Time Slot 9 Receive Signaling Data. 0000000

0x8LR0A 6:0 FRM_RPSR10[6:0] Time Slot 10 Receive Signaling Data. 0000000

0x8LR0B 6:0 FRM_RPSR11[6:0] Time Slot 11 Receive Signaling Data. 0000000

0x8LR0C 6:0 FRM_RPSR12[6:0] Time Slot 12 Receive Signaling Data. 0000000

0x8LR0D 6:0 FRM_RPSR13[6:0] Time Slot 13 Receive Signaling Data. 0000000

0x8LR0E 6:0 FRM_RPSR14[6:0] Time Slot 14 Receive Signaling Data. 0000000

0x8LR0F 6:0 FRM_RPSR15[6:0] Time Slot 15 Receive Signaling Data. 0000000

0x8LR10 6:0 FRM_RPSR16[6:0] Time Slot 16 Receive Signaling Data. 0000000

0x8LR11 6:0 FRM_RPSR17[6:0] Time Slot 17 Receive Signaling Data. 0000000

0x8LR12 6:0 FRM_RPSR18[6:0] Time Slot 18 Receive Signaling Data. 0000000

0x8LR13 6:0 FRM_RPSR19[6:0] Time Slot 19 Receive Signaling Data. 0000000

0x8LR14 6:0 FRM_RPSR20[6:0] Time Slot 20 Receive Signaling Data. 0000000

0x8LR15 6:0 FRM_RPSR21[6:0] Time Slot 21 Receive Signaling Data. 0000000

0x8LR16 6:0 FRM_RPSR22[6:0] Time Slot 22 Receive Signaling Data. 0000000

0x8LR17 6:0 FRM_RPSR23[6:0] Time Slot 23 Receive Signaling Data. 0000000

0x8LR18 6:0 FRM_RPSR24[6:0] Time Slot 24 Receive Signaling Data. 0000000

0x8LR19 6:0 FRM_RPSR25[6:0] Time Slot 25 Receive Signaling Data. 0000000

0x8LR1A 6:0 FRM_RPSR26[6:0] Time Slot 26 Receive Signaling Data. 0000000

0x8LR1B 6:0 FRM_RPSR27[6:0] Time Slot 27 Receive Signaling Data. 0000000

0x8LR1C 6:0 FRM_RPSR28[6:0] Time Slot 28 Receive Signaling Data. 0000000

0x8LR1D 6:0 FRM_RPSR29[6:0] Time Slot 29 Receive Signaling Data. 0000000

0x8LR1E 6:0 FRM_RPSR30[6:0] Time Slot 30 Receive Signaling Data. 0000000

0x8LR1F 6:0 FRM_RPSR31[6:0] Time Slot 31 Receive Signaling Data. 0000000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

274 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 385. FRM_RSLR32, Receive Signaling Link Register 32 (COR)

* See Table 383 on page 272 for values of L and R.

Address*Bit Name Function Reset

Default

0x8LR20 15:1

2FRM_R_HGAIS[3:0] HG AIS Detection. Indicates the dete cti on of AIS in the cor -

responding HG. 0000

11:8 FRM_R_HGA[3:0] HG Alignment. Indicates the alignment status for the corre-

sponding HG. A 0 indicates no alignment. A 1 indicates align-

ment for the corresponding group.

0000

7:4 FRM_R_HGRDI[3:0] HG RDI. Indicates the detection of three consecutive zeros in

the Sp bit position of the corresponding HG. 0000

3 FRM_R_TS16A Time Slot 16 Multiframe Alignment Status. A 0 indicates

that, currently, time slot 16 multiframe alignment is not estab-

lished. A 1 indicates that, currently, time slot 16 multiframe

alignment has been established.

2 FRM_R_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multi-

frame alignment is lost, this bit will reflect the detection of AIS

in time slot 16.

1:0 RSVD Reserved. Must write to 0. 0

Table 386. FRM_RSLR33, Receive Signaling Link Register 33 (R/W)

Address*Bit Name Function Reset

Default

0x8LR21 15 FRM_R_FZCON Freeze Conversion. When set to 1, this enables the conver-

sion of certain signaling codes when the signaling buffers

have been frozen. The code translation is 00 to 01 and 0000

to 0101 for 4-state and 16-state signaling, respectively.

14:9 RSVD Reserved. Must write to 0. 0

8 FRM_R_SIGI Signaling Insertion. A 1 enables the insertion of signaling

data into the Tx line. A 0 disables the insertion of signaling

data into the Tx line. This bit is valid in the Rx path only when

in transport mode; otherwise, it should be set to 0.

7 FRM_R_RXSTOMP Rx Path Stomping . For DS1 links, this bit indicates to stomp

all robbed bit signaling on voice time slots on the correspond-

ing link. Stomping of time slot 16 for CEPT links is performed

in the system interface block.

1 = will enable stomping.

0 = will disable stomping for the corresponding link.

6RSVDReserved. Must write to 0.

5 FRM_R_SIGDEB Signaling Debounce.This bit enables signal debounce on

signaling when extracted from the Rx line. 0

4 FRM_R_HGEN Handling Group Enable . When set to 1 in combination with

selecting the source of signaling data to be the VT mapper,

this indicates to the signaling block that the signaling for this

link is byte sync mapped and uses the handling group format.

3 FRM_R_MSIGFZ Manual Signaling Freeze. Used to manually halt the signal-

ing register updates when the source of signaling data is

either the VT mapper or when the signaling is extracted from

the Rx line. A 1 halts the updates.

* See Table 383 on page 272 for values of L and R.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

12 28-Channel Framer Registers (continued)

275Agere Systems Inc.

* See Table 383 on page 272 for values of L and R.

Table 387. Transmit Path Signaling Register Addressing Map

* L and T represent hexidecimal digits used for absolute addr essing in Table 389, Table 390, and Table 391.

Read: for link 1 (pertaining to Table 388), the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3.

Table 388. Transmit Path Signaling Registers Address Indexing

0x8LR21 2 FRM_R_FGSRC F and G Source . Indicates which entity will be the source for

the F and G values used in handling the ABCD bits.

0 = hos t programmed.

1 = implied by the Tx path ASM.

The Tx path option can only be selected when the Tx path is

configured with an ASM CHI or parallel system bus interface.

Also, the Tx path option can only be selected when the Rx

path is extracting data from the receive line interface vs. byte

sync VT mapped mode.

1:0 FRM_R_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will

be the source for the ABCD bits.

00 = signaling programmed by the host.

01 = signaling extracted from the Rx line.

10 = signaling read from VT mapper in byte sync mode (valid

only for DS1).

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 TX = 1 0 SIG6 SIG5 SIG4 SIG3 SIG2 SIG1 SIG0

L* T* —

Link L T Link L T Link L T Link L T

1 0x00x3 8 0x10x1160x20x1240x30x1

2 0x00x5 9 0x10x3170x20x3250x30x3

3 0x00x7100x10x5180x20x5260x30x5

4 0x00x9110x10x7190x20x7270x30x7

5 0x00xB120x10x9200x20x9280x30x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB — — —

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD — — —

— — — 15 0x1 0xF 23 0x2 0xF — — —

Table 386. FRM_RSLR33, Receive Signaling Link Register 33 (R/W) (continued)

Address*Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

276 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 389. FRM_TSLR0—FRM_TSLR31, Transmit Signaling Link Registers 0—31 (R/W)

* See Table 388 on page 275 for values of L and T.

Notes:

Bit 0 = A, bit 1 = B, bit 2 = C, bit 3 = D, bit 5 = F, and bit 6 = G.

For DS1 links, address locations 1 through 24 will contain valid data.

For CEPT links, locations 1 through 15 and 17 through 31 will contain valid data. Writes from the system interface to address 0 and 16 will be

accepted and stored in signaling registers. For CEPT links, inserted time slot 16 X bits are written to locates 0.

Address*Bit Name Function Reset

Default

0x8LT00 6:0 FRM_TPSR0[6:0] Time Slot 0 Transmit Signaling Data. 0000000

0x8LT01 6:0 FRM_TPSR1[6:0] Time Slot 1 Transmit Signaling Data. 0000000

0x8LT02 6:0 FRM_TPSR2[6:0] Time Slot 2 Transmit Signaling Data. 0000000

0x8LT03 6:0 FRM_TPSR3[6:0] Time Slot 3 Transmit Signaling Data. 0000000

0x8LT04 6:0 FRM_TPSR4[6:0] Time Slot 4 Transmit Signaling Data. 0000000

0x8LT05 6:0 FRM_TPSR5[6:0] Time Slot 5 Transmit Signaling Data. 0000000

0x8LT06 6:0 FRM_TPSR6[6:0] Time Slot 6 Transmit Signaling Data. 0000000

0x8LT07 6:0 FRM_TPSR7[6:0] Time Slot 7 Transmit Signaling Data. 0000000

0x8LT08 6:0 FRM_TPSR8[6:0] Time Slot 8 Transmit Signaling Data. 0000000

0x8LT09 6:0 FRM_TPSR9[6:0] Time Slot 9 Transmit Signaling Data. 0000000

0x8LT0A 6:0 FRM_TPSR10[6:0] Time Slot 10 Transmit Signaling Data. 0000000

0x8LT0B 6:0 FRM_TPSR11[6:0] Time Slot 11 Transmit Signaling Data. 0000000

0x8LT0C 6:0 FRM_TPSR12[6:0] Time Slot 12 Transmit Signaling Data. 0000000

0x8LT0D 6:0 FRM_TPSR13[6:0] Time Slot 13 Transmit Signaling Data. 0000000

0x8LT0E 6:0 FRM_TPSR14[6:0] Time Slot 14 Transmit Signaling Data. 0000000

0x8LT0F 6:0 FRM_TPSR15[6:0] Time Slot 15 Transmit Signaling Data. 0000000

0x8LT10 6:0 FRM_TPSR16[6:0] Time Slot 16 Transmit Signaling Data. 0000000

0x8LT11 6:0 FRM_TPSR17[6:0] Time Slot 17 Transmit Signaling Data. 0000000

0x8LT12 6:0 FRM_TPSR18[6:0] Time Slot 18 Transmit Signaling Data. 0000000

0x8LT13 6:0 FRM_TPSR19[6:0] Time Slot 19 Transmit Signaling Data. 0000000

0x8LT14 6:0 FRM_TPSR20[6:0] Time Slot 20 Transmit Signaling Data. 0000000

0x8LT15 6:0 FRM_TPSR21[6:0] Time Slot 21 Transmit Signaling Data. 0000000

0x8LT16 6:0 FRM_TPSR22[6:0] Time Slot 22 Transmit Signaling Data. 0000000

0x8LT17 6:0 FRM_TPSR23[6:0] Time Slot 23 Transmit Signaling Data. 0000000

0x8LT18 6:0 FRM_TPSR24[6:0] Time Slot 24 Transmit Signaling Data. 0000000

0x8LT19 6:0 FRM_TPSR25[6:0] Time Slot 25 Transmit Signaling Data. 0000000

0x8LT1A 6:0 FRM_TPSR26[6:0] Time Slot 26 Transmit Signaling Data. 0000000

0x8LT1B 6:0 FRM_TPSR27[6:0] Time Slot 27 Transmit Signaling Data. 0000000

0x8LT1C 6:0 FRM_TPSR28[6:0] Time Slot 28 Transmit Signaling Data. 0000000

0x8LT1D 6:0 FRM_TPSR29[6:0] Time Slot 29 Transmit Signaling Data. 0000000

0x8LT1E 6:0 FRM_TPSR30[6:0] Time Slot 30 Transmit Signaling Data. 0000000

0x8LT1F 6:0 FRM_TPSR31[6:0] Time Slot 31 Transmit Signaling Data. 0000000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

277Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 390. FRM_TSLR33, Transmit Signaling Link Register 33 (COR)

* See Table 388 on page 275 for values of L and T.

Address*Bit Name Function Reset

Default

0x8LT20 15:4 RSVD Reserved. Must write to 0. 0x000

3 FRM_T_TS16A Time Slot 16 Multiframe Alignment Status. A 0 indicates

that, currently, time slot 16 multiframe alignment is not estab-

lished. A 1 indicates that, currently, time slot 16 multiframe

alignment has been established.

2 FRM_T_TS16AIS Time Slot 16 AIS Detection Status. If time slot 16 multi-

frame alignment is lost, this bit will reflect the detection of AIS

in time slot 16.

1:0 RSVD Reserved. Must write to 0. 00

Table 391. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W)

Address*Bit Name Function Reset

Default

0x8LT21 15 RSVD Reserved. Must write to 0. 0

14 FRM_T_ATS16RFA Automatic TS 16 Remote Frame Alarm. Enables automatic

transmission of a 1 in the Y-bit position in the transmit path

when the receive path has lost TS16 alignment.

13 RSVD Reserved. Must write to 0. 0

12 FRM_T_ASPLB Automatic Sp Loopback. When set, the Sp bit transmitted

for each individual HG will be set to 0 when the HG align-

ment is lost in the Rx path. Each Sp in the Tx path corre-

sponds to the same HG in the Rx path.

11 FRM_T_MSP Manual Sp. Used to manually force the transmission of a 0

in each of the Sp bits of the HGs on each link. 0

10 FRM_T_ZCSM Zero Code Suppression Mode. When set to 1, the signal-

ing block will give an indication to the frame formatter for

each of the data channels. This indication should disable the

zero-code suppression for the associated time slot. Signal-

ing insertion must be enabled for FRM_T_ZCSM to take

effect. FRM_T_ZCSM will not work when byte sync mapping

is enabled.

9 FRM_T_VTSIGE VT Signal ing Enable. A 1 enables the transport of signaling

to the VT mapper from the programmed signaling source in

byte sync mode. Byte sync mode cannot be enabled in con-

junction with signaling insertion (bit 8, FRM_T_SIGI). The

robbed-bit positions can be stomped while in byte sync

mode, but no signaling data can be inserted.

8 FRM_T_SIGI Signaling Insertion. A 1 enables the insertion of signaling

data into the Tx line. A 0 disables the insertion of signaling

data into the Tx line.

7RSVDReserved. Must write to 0. 0

* See Table 388 on page 275 for values of L and T.

TMXF2815 5/ 51 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

278 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

12 28-Channel Framer Registers (continued)

* See Table 388 on page 275 for values of L and T.

12.10 Performanc e Mo nitor Per Link Reg isters

The following tables describe the functions of all bits in the register map. Counters are programmable to either

roll over or saturate, and may be programmed to clear on read.

Registers are only provisionable to clear-on-read (COR).

For each address, the register bits are identified as either read/write (R/W) or read only (RO), and the value of the

bits on reset are given.

Table 392. Performance Monitor Per Link Register Addressing Map

* L and P represent hexidecimal digits used f or absolute addressing in Table 394 through Table 413.

0x8LT21 6 FRM_T_TXSTOMP Tx Path Stomping. For DS1 links, this bit indicates to stomp

all robbed-bit signaling on voice time slots on the corre-

sponding link to 0. Stomping time slot 16 for CEPT links is

done by inserting all ones using the signaling registers. A 1

will enable stomping. A 0 will disable stomping for the corre-

sponding link.

5RSVDReserved. Must write to 0. 0

4 FRM_T_HGEN Handling Group Enable. When set to 1 in combination with

(bit 9, FRM_T_VTSIGE), this bit indicates to the signaling

block that the signaling for this link is byte sync mapped and

uses the handling group format.

3 FRM_T_MSIGFZ Manual Signaling Freeze. Used to manually halt the signal-

ing register updates when the source of signaling data is

either the Rx system or the Rx line. A 1 halts the updates.

2 FRM_T_FGSRC F and G Source. Indicates which entity will be the source

for the F and G values used in handling the ABCD bits.

0 = host programmed.

1 = sourced from the Rx system interface.

The F and G program ming can be impli ed by the syst em

interface only when using the ASM CHI or the parallel sys-

tem interface.

1:0 FRM_T_SIGSRC[1:0] Signaling Data Source. Indicates which of the entities will

be the source for the ABCD bits.

00 = signaling programmed by the host.

01 = signaling extracted from the Rx line.

10 = signaling received from the system interface.

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP = 0

TXP = 1 1 0 PM5 PM4 PM3 PM2 PM1 PM0

L* P* —

Table 391. FRM_TSLR32, Transmit Signaling Link Register 32 (R/W) (continued)

Address*Bit Name Function Reset

Default

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

279Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 393. Performance Monitor Per Link Register Address Indexing

Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.

Table 394. FRM_PMLR1, Performance Monitor Link Register 1 (R/W)

* See Table 393 for values of L and P.

Table 395. FRM_PMLR2, Performance Monitor Link Register 2 (R/W)

* See Table 393 for values of L and P.

Link L P Link L P Link L P Link L P

Receive Path (P is even)

1 0x00x2 8 0x10x0160x20x0240x30x0

2 0x00x4 9 0x10x2170x20x2250x30x2

3 0x00x6100x10x4180x20x4260x30x4

4 0x00x8110x10x6190x20x6270x30x6

5 0x00xA120x10x8200x20x8280x30x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA — — —

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC — — —

— — — 15 0x1 0xE 23 0x2 0xE — — —

Transmit Path (P is odd)

1 0x00x3 8 0x10x1160x20x1240x30x1

2 0x00x5 9 0x10x3170x20x3250x30x3

3 0x00x7100x10x5180x20x5260x30x5

4 0x00x9110x10x7190x20x7270x30x7

5 0x00xB120x10x9200x20x9280x30x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB — — —

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD — — —

— — — 15 0x1 0xF 23 0x2 0xF — — —

Address*Bit Name Function Reset

Default

0x8LP80 15:0 FRM_PM_IM4[15:0] Performance Monitoring Register FRM_PMLR4 Inter-

rupt Mask. A 1 masks the corresponding status bit in the

interrupt status registers (Table 398 on page 287) from

generating an interrupt. A 0 allows an interrupt to be gener-

ated.

0xFFFF

Address*Bit Name Function Reset

Default

0x8LP81 15:0 FRM_PM_IM5[15:0] Performance Monitor Register FRM_PMLR5 Interrupt

Mask. A 1 masks the corresponding status bit in interrupt

status re gister s (Table 398 on page 287) from generating

an interrupt. A 0 allows an interrupt to be generated.

0xFFFF

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

280 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 396. FRM_PMLR3, Performance Monitor Link Register 3 (R/W)

* See Table 393 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP82 15:11 RSVD Reserved. Must write to 0. 00000

10:7 FRM_MHGALIGN[3:0] Handling Group Alignment Interrupt Mask. A 1 masks

the corresponding status bit in the interrupt status register

(Table 412 on page 293) from generating an interrupt. A 0

allows an interrupt to be generated.

0xF

6FRM_MSEFSSeverely Error ed Fra me Inte rrupt Mas k. A 1 masks the

corresponding status bit in the interrupt status register

(Table 412 on page 293) from generating an interrupt. A 0

allows an interrupt to be generated.

5FRM_MFECEPT Functional Element Status Interrupt Mas k. A 1

masks any and all of the FE status bits in Table 406 on

page 291 and Table 407 on page 292 from generating an

interrupt. A 0 allows an interrupt to be generated.

4:0 FRM_PM_IM6[15:0] Performance Monitor Register FRM_PMLR6 Interrupt

Mask. A 1 masks the corresponding status bit in the inter-

rupt status register (Table 399 on page 289) from gener-

ating an interrupt. A 0 allows an interrupt to be generated.

0x001F

Table 397. FRM_PMLR4, Performance Monitor Link Register 4 (COR)

Address*Bit Name Function Reset

Default

0x8LP83 15 FRM_SLIPO Receive Elastic Store Slip Overflow. A 1 indicates that the

receive elastic store performed a control slip due to an elastic

store overflow condition. This signal is set when the error

occurs and is cleared when it is read, if there is not another

error during the read.

14 FRM_SLIPU Receive Elastic Store Slip Underflow. A 1 indicates that the

receive elastic store performed a control slip due to an elastic

store underflow condition. This signal is set when the error

occurs and is cleared when it is read, if there is not another

error during the read.

13 FRM_OOF Out-Of-Frame. A 1 indicates that the receive framer has lost

frame alignment and is currently searching for a new frame

alignment. Section 21.6.1, Loss of Frame Alignment Criteria, on

page 495 lists the loss of frame criteria for the framing bit.

(T1.231, Section 6.1.2.2.1, G.706, Section 4.1). Excessive

(exceeding the provisionable CRC error count) CRC errors may

optionally cause a reframe.

In ESF or J-ESF, more than 320 CRC-6 errors in 1 s result in

loss of frame alignment. The CRC error count is provisionable.

In the CEPT CRC-4 multiframe formats, more than 915 CRC-4

errors in 1 s result in loss of frame alignment (G.706, Section

4.3.2). The CRC error count is provisionable.

* See Table 393 on page 279 for values of L and P.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

12 28-Channel Framer Registers (continued)

281Agere Systems Inc.

* See Table 393 on page 279 for values of L and P.

0x8LP83 12 FRM_LSFA Loss of Signaling Frame Alignment. DS1: A 1 indicates that

the receive framer is in a loss of signaling superframe alignment

in the SLC-96 framing format. This bit is a 0 in all other DS1

framing modes. SLC-96 signaling alignment is assumed to have

been lost when mul tiframe alignment is lost .

CEPT: A 1 indicates the loss of the CEPT time slot 16 channel

associated signaling multiframe structure. CEPT time slot 16

multiframe alignment is assumed lost when two consecutive

time slot 16 multiframe alignment patterns (0000) are received

in error, or when time slot 16 is all zeros for one or two multi-

frames. Time slot 16 multiframe alignment is assumed to have

occurred when the first time slot 16 multiframe alignment pat-

tern is found in time slot 16 and, optionally, the preceding time

slot 16 contained at least one. (G.732, Section 5.2; O.162, Sec-

tion 2.1.3.) This is the time slot 16 align input from the signaling

block.

11 FRM_OAIS Other Alarm Indication Signals. CEPT RTS16AIS: A 1 indi-

cates the receive framer detected time slot 16 AIS. Time slot 16

AIS is defined to be fewer than three zeros in each of two con-

secutive time slot 16 multiframe periods (G775, Section 5.1.1).

This is the time slot 16 AIS input from the signaling block.

Table 397. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

Address*Bit Name Function Reset

Default

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

282 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 397. FRM_PMLR4, Perfor mance Monitor Link Register 4 (COR) (continued)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP83 10 FRM_AIS Alarm Indication Signal. A 1 indicates the framer is currently

receiving an AIS pattern or receiving an AIS indication on the

TDM bus from the mapper.

DS1: Option 0: AIS occurs upon detection of an unframed sig-

nal with a ones density of at least 99.9% for a time between

3 ms and 75 ms. AIS is removed if the signal does not meet the

99.9% ones density or the unframed criteria for a period

between 3 ms and 75 ms. (ANSI T1.231, Section 6.1.2.2.3,

T1.403, Section H, G.775, Section 5.4.)

Option 1: AIS is detected if the signal has one or less zeros in

24 frames (3 ms/4632 bits). AIS is removed if the signal has two

or more zeros in 24 frames. (ANSI G.775, Section I.2.)

CEPT: Option 0: AIS is detected when loss of frame alignment

occurs and there are two or less zeros in a double frame period

(512 bits per double-frame period). AIS is cleared on receipt of

a signal not conforming to the AIS defect criteria. (ANSI G.775,

Section I.2; G.965, Section 16.1.2.)

Option 1: AIS is detected when there are two or fewer zeros in

each of two consecutive double-frame periods (512 bits per

double frame period). AIS is cleared when each of two consecu-

tive double frame periods contain three or more zeros or the

frame alignment signal (FAS) is found. (ANSI G.775, Section

5.2.)

Option 2: AIS is detected when there are three or less zeros in a

four frame period (0.5 ms/1024 bits) and the signal is out of

frame. AIS is cleared if there are four or more zeros in a four-

frame period or the signal is in frame alignment. (ANSI G.775,

Section I.2.)

Option 3: AIS is detected when there are one or fewer zeros in

each of two consecutive double-frame periods (512 bits per

double-frame period) and the FAS is not detected. AIS is

cleared when each of two consecutive double-frame periods

contain three or more zeros or the frame alignment signal (F AS)

is found. (ANSI G.7 75, Se cti on I.2.)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

283Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 397. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

Address*Bit Name Function Reset

Default

0x8LP83 9 FRM_ORAI Other Remote Alarm Indication. A 1 indicates the receive

framer detected another remote (yellow) alarm. This bit is a 0 in

the modes not indicated below. This bit is set when the alarm is

detected, and is cleared on a read of this register if the alarm is

not detected during the read.

J-D4 RJYA: The frame bit in frame 12 is a 1 two out of three

consecutive times.

ESF, J -ESF: CEPT RTS16MF A: Bit 6 of time slot 16 of signaling

frame 0 is a 1 for three consecutive occurrences. The alarm is

considered inactive when bit 6 of time slot 16 of signaling frame

0 is 1 in less than two consecutive occasions. This is true if time

slot 16 is not carrying a payload, e.g., common channel signal-

ing. If time slot 16 is used for common channel signaling, bit 6

will be continuously 1. In this case, it will be possible to inhibit

the remote alarm to prevent false alarm conditions. (O.162,

Section 2.1.5.) This is the y-bit input from the signaling block.

* See Table 393 on page 279 for values of L and P.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

284 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 397. FRM_PMLR4, Perfor mance Monitor Link Register 4 (COR) (continued)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP83 8 FRM_RAI Remote Alarm Indication. A 1 indic at e s the receive fram er

detected a remote (yellow) alarm or detected an RAI indication

on the TDM bus from the mapper.

D4: Bit 2 of all time slots is a 0 for one frame. (ANSI T1.403,

Section 9.1.)

DDS: Bit 6 of time slot 24 is a 0 for 12 frames.

ESF: The user should use register 0x8LP85, bit 4,

ESF_FDL_RAI/Yellow Alarm.

CEPT Basic Frame: RAI is activated when bit 3 of the NOTF AS

frame is 1 RAC consecutive times. RAI is deactivated when bit

3 of the NOTFAS frame is a 0 RDC consecutive times. RAI acti-

vation count (RAC) and RAI deactivation count (RDC) are provi-

sionable in Table 325 on page 251.

Option 0: Bit 3 of the NOTFAS frame is a 1 one consecutive

time. RAI is inactive when bit 3 is set to a 0.

Option 1: RAI is set on three consecutive ones and deactivated

on three consecutive zeros.

Option 2: Bit 3 of the NOTFAS frame is a 1 four consecutive

times. RAI is inactive when bit 3 is set to a 1 in less than two

consecutive occasions. (O.162, Section 2.1.4.)

Option 3: RAI is set on five consecutive ones and deactivated

on five consecutive zeros. (ETS 300.417-1-1.)

CEPT CRC-4 Multiframe: Reception of 1 bit A with a content

of 1. (G.965, Section 16.1.2.)

7 FRM_SA600X1E Sa6 = 00x1 Event. This bit indicates detection of an Sa6 = 00x1

event. The Sa6 code is detected synchronously to the CRC-4

multiframe and is not counted during loss of CRC-4 multiframe

alignment. This detection is not qualified by Sa5 = 1, unlike bits

6 and 8 of Table 406 on page 291.

6 FRM_SA6001XE Sa6 = 001x Event. This bit indicates detection of an Sa6 = 001x

event. The Sa6 code is detected synchronously to the CRC-4

multiframe and is not counted during loss of CRC-4 multiframe

alignment. This detection is not qualified by Sa5 = 1, unlike bits

7 and 8 of Table 406.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

285Agere Systems Inc.

12 28-Channel Framer Registers (continued)

* See Table 393 on page 279 for values of L and P.

Table 397. FRM_PMLR4, Performance Monitor Link Register 4 (COR) (continued)

Address*Bit Name Function Reset

Default

0x8LP83 5 FRM_CRCTX CRC-4 Multiframe Alignment Timer Expired. A 1 indicates

that either the 100 ms or the 400 ms interworking timer expired.

It is only active immediately after basic frame alignment is found

in CEPT CRC-4 modes. This signal is set when the error

occurs, and is cleared when it is read if there is not another

error during the read.

4 FRM_LTS0MFA Loss of Time Slot 0 CRC-4 Multiframe Alignment. A 1 indi-

cates the absence of CRC-4 multiframe alignment. This bit is

set when basic frame alignment has been found and multiframe

alignment is being searched for, or when multiframe alignment

is lost but basic frame alignment remains good, or when multi-

frame alignment is lost.

Note: This is a stored version of the status. It is cleared after

one good multiframe bit is seen .

CRC-4 multiframe alignment is assumed lost when there are

three consecutive errors in the CRC-4 multiframe alignment bits

(bit 0 of NOTFAS frames 1, 3, 5, 7, 9, and 11). Loss of CRC-4

multiframe alignment may optionally cause a research for

CRC-4 multiframe alignment without affecting the current basic

frame alignment.

CEPT with CRC-4 only. In all other modes, this bit is a 0.

3FRM_TS0MFABETime Slot 0 Multiframe Alignment Signal Bit Error. A 1

indicates that the receive framer detected an error in the CRC-4

multiframe alignment signal. A 0 indicates no errors. Bit 0 of

NOTFAS frames (1, 3, 5, 7, 9, and 11).

2FRM_SESSeverely Errored Second (G.826 Annex B). A 1 indicates the

receive framer detected a severely errored second. The events

that can cause an errored second are provisionable for DS1

links in Table 329 and for CEPT links in Table 332. The

severely errored second threshold is provisionable; DS1-SF

links in Table 326 on page 252, DS1-ESF link s in Table 328 on

page 253, and CEPT links in Table 331 on page 253.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

286 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 397. FRM_PMLR4, Perfor mance Monitor Link Register 4 (COR) (continued)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP83 1 FRM_BES Burs ty Errored Second. A 1 indicates the receive framer

detected a bursty errored second. The events that can cause an

errored second are provisionable for DS1 links in Table 329 on

page 253 and for CEPT links in Table 332 on page 254. The

severely errored second threshold is provisionable; DS1-SF

links in Table 326 on page 252, DS1-ESF links in Table 328 on

page 253, and CEPT links in Table 331 on page 253.

BES is not valid in any CEPT mode.

Note: The SES threshold must always be greater than the ES

threshold because BES lies in between (i.e., ES < BES <

SES).

0FRM_ESErrored Second (G.826 Annex B). A 1 indicates the receive

framer detected an errored second. The events that can cause

an errored second are provisionable for DS1 links in Table 329

on page 253 and for CEPT links in Table 332 on page 254.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

287Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 398. FRM_PMLR5, Performance Monitor Link Register 5 (COR)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP84 15:14 RSVD Reserved. Must write to 0. 0

13 FRM_LFV Line Format Violation. A 1 indicates the receive framer detected

a bipolar line coding or excessive zeros violation. The perfor-

mance monitor counts all pulses on the BPV signal from the frame

aligner block. This signal is set when the error occurs and is

cleared when it is read, if there is not another error during the

read. (G.703 Annex A and O.161, Section 2.)

12 FRM_FBE Frame-Bit Errored. A 1 indicates the receive framer detected a

frame bit or frame alignment pattern error. For SF formats, either

FT, or FT and FS bits are used and are programmable. This signal

is set when the error occurs and is cleared when it is read, if there

is not another error during the read. In DDS, FT and FS are alway s

counted as FBEs. The PMON is, however, configurable as to

whether TS24 is also counted as an FBE. In CEPT, FAS words

can only gene rate o ne FBE .

11 FRM_CRCE CRC Errored. A 1 indicates the receive framer detected a CRC

error. It is the occurrence of a received CRC code that is not iden-

tical to the locally calculated code. This signal is set when the error

occurs and is cleared when it is read, if there is not another error

during the read. This signal is only valid in ESF (G.704, Section

A.1) and CEPT CRC-4 (G.704, Section A.3) modes.

10 FRM_ECRCE Excessive CRC Errors. A 1 in dicat es the receiv e fram er det ected

an excessive CRC error condition. This signal is set when the

error occurs and is cleared when it is read, if there is not another

error during the read. This signal is only valid in ESF and CEPT

CRC-4 modes. The CRC error count is provisionable. In ESF, an

excessive CRC error is defined as ≥320 CRC errors in 1 s. In

CEPT, an excessive CRC error is defined as ≥915 CRC errors in

1 s.

9FRM_REBITReceived E Bit = 0. A 1 indicates the receive framer detected an

E bit = 0 in the CEPT CRC-4 modes. This signal is set when the

error occurs and is cleared when it is read if there is not another

error during the rea d. This signal is only valid in CEPT CRC- 4

modes.

8 FRM_CREBIT Continuous Received E Bits. A 1 indicates the detection of a 5 s

interval containing ≥991 E bit = 0 events in each second. The E-bit

error count is provisionable. The defaults of 991 are shown.

7FRM_LTFALoss of Transmit Frame Alignment. DS1: Always 1.

CEPT FRM_LTFA: A 1 indicates that the CEPT biframe alignment

pattern (alternating 0, 1 in bit 2 of time slot 0) received from the

system is in error. This alignment pattern is required when trans-

mitting the Si or Sa bits transparently. Detection of this condition

may optionally be disabled.

6FRM_NFANew Frame Alignment. A 1 indicates the receive framer has

reframed. 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

288 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 398. FRM_PMLR5, Perfor mance Monitor Link Register 5 (COR) (continued)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP84 5 FRM_SA7LID Sa7 Link Identification. A 1 indicates that a sequence was found

such that two out of three Sa7 bits are 0. (G.965, Section 16.1.2.) 0

4 FRM_LLBON Line Loopback On Code Detect. A 1 indicates the receive framer

detected the DS1 line loopback enable code. The activation signal

consists of repetitions on the pattern 00001 with the framing bits

replacing the pattern bits. (T1.403, Section 9.3.1.1.) Only applica-

ble in DS1 SF formats.

3 FRM_LLBOFF Line Loopback Off Code Detect. A 1 indicates the receive

framer detected the DS1 line loopback disable code. The deacti-

vation signal consists of repetitions on the pattern 001 with the

framing bits replacing the pattern bits. (T1.403, Section 9.3.1.2.)

Only applicable in DS1 SF formats.

2FRM_AUXPAuxiliary Pattern. DS1 IDLEID: Each of the 24 time slots in a

frame contain the DS1 idle signal, 00010111. (T1.231, Section

6.4.8.)

Note: For ESF, the Supermapper will only check for the idle code;

it does not look for RAI.

CEPT AUXP: A 1 indicates the detection of a valid auxiliary pat-

tern (unframed 10 . . . pattern) in the CEPT mode. When in loss of

frame alignment state, an auxiliary pattern is detected when more

than 255 10 patterns are detected in a 512-bit interval. The alarm

is disabled when three or more non-10 patterns are detected in a

512-bit interval. The search for AUXP is synchronized to the first

alternating 10 pattern found. (ETS 300 233, Section 8.2.2.2,

O.151, Section 2.4.)

1 FRM_LOS Loss of Signal. A 1 indicates that the receive line decoder has

detected a loss of signal condition. This status is only valid in the

dual-rai l mod e of opera tio n.

DS1: Loss of signal occurs when, for 100 contiguous pulse posi-

tions, there are no pulses of either the positive or negative polarity

at the line interface. The loss of signal defect is removed upon

detecting 13 pulses over 100 pulse positions following the receipt

of a pulse, and there is no 100 pulse position interval where there

were no pulses. (T1.231, Section 6.1.2.1.1, G.775, Section 4.3.)

CEPT: Loss of signal occurs when, for 100 consecutive pulse

positions, there are no pulses of either the positive or negative

polarity at the line interface. The loss of signal defect is removed

when there are pulses in a 100 consecutive pulse position period

(G.775, Section 4.2). Note that the defect is set and cleared at the

end defined sample period.

0FRM_BOMRBit-Oriented Message Received. A 1 indicates a BOM has been

received in the ESF data link bits and FRM_RBOM[7:0]

(Table 411 on page 292) should be read. A BOM is defined in

ANSI T1.403 as a 0xxxxxx0 11111111 pattern (received right-to-

left) repeated 10 consecutive times. The 0xxxxxx0 pattern is

saved in the FRM_RBOM[7:0] register (Table 411 on page 292)

upon the tenth occurrence of the BOM message.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

289Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 399. FRM_PMLR6, Performance Monitor Link Register 6 (COR)

* See Table 393 on page 279 for values of L and P.

Table 400. FRM_PMLR7, Performance Monitor Link Register 7 (COR)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP85 15:5 RSVD Reserved. 0

4 FRM_FDL_RAI ESF_FDL_RAI/Yellow Alarm. A 1 indicates the receive

framer detected the ESF_FDL_RAI/yellow alarm code in the

payload. This code is defined in ANSI T1.403-1995 as a

00000000 11111111 pattern in the facility data link (received

right-to-left). This signal is set when the pattern is detected

(10 consecutive times) and is cleared when it is read if the pat-

tern is no longer being detected.

3 FRM_FDL_PLBON ESF_FDL Payload Loopback Enable. A 1 indicates the

receive framer detected the ESF_FDL payload loopback

enable code in the payload. This code is defined in

ANSI T1.403-1995 as a 00010100 11111111 pattern in the

facility data link (received right-to-left). This signal is set when

the pattern is detected (10 consecutive times) and is cleared

when it is read if the pattern is no longer being detected. This

could also be set by FF_PLB (manual PLB indication) input.

2 FRM_FDL_PLBOFF ESF_FDL Payload Loopback Disable. A 1 indicates the

receive framer detected the ESF_FDL payload loopback dis-

able code in the payload. This code is defined in

ANSI T1.403-1995 as a 00110010 11111111 pattern in the

facility data link (received right-to-left). This signal is set when

the pattern is detected (10 consecutive times) and is cleared

when it is read if the pattern is no longer being detected.

1 FRM_FDL_LLBON ESF_FDL Line Loopback Enable. A 1 indicates the receive

framer detected the ESF_FDL line loopback enable code in

the payload. This code is defined in ANSI T1.403-1995 as a

00001110 11111111 pattern in the facility data link (received

right-to-left). This signal is set when the pattern is detected

(10 consecutive times) and is cleared when it is read if the pat-

tern is no longer being detected.

0 FRM_FDL_LLBOFF ESF_FDL Line Loopback Disable. A 1 indicates the receive

framer detected the ES F _FD L line loop bac k dis ab le co de in

the payload. This code is defined in ANSI T1.403-1995 as a

00111000 11111111 pattern in the facility data link (received

right-to-left). This signal is set when the pattern is detected

(10 consecutive times) and is cleared when it is read if the pat-

tern is no longer being detected.

Address*Bit Name Function Reset

Default

0x8LP86 15:0 FRM_BPV[15:0] Bipolar Violation Counter. This register contains the 16-bit

count of received bipolar violations, line code violations, and

excessive zeros.

0x0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

290 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 401. FRM_PMLR8, Performance Monitor Link Register 8 (COR)

* See Table 393 on page 279 for values of L and P.

Table 402. FRM_PMLR9, Performance Monitor Link Register 9 (COR)

* See Table 393 on page 279 for values of L and P.

Table 403. FRM_PMLR10, Performance Monitor Link Register 10 (COR)

* See Table 393 on page 279 for values of L and P.

Table 404. FRM_PMLR11, Performance Monitor Link Register 11 (COR)

* See Table 393 on page 279 for values of L and P.

Table 405. FRM_PMLR12, Performance Monitor Link Register 12 (COR)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LP87 15:0 FRM_FBEC[15:0] Frame Bit Error Counter.

DS1: This register contains the 16-bit count of received framing

bit errors. Framing bit errors are not counted during loss of

frame alignment. (T1.231, Section 6.1.1.2.2.)

CEPT: This register contains the 16-bit count of received frame

alignment signal errors. Optionally, bit 2 of NOTF AS frames can

be counted.

Note: A FAS with errors in two or more bit positions is only

counted once.

0x0

Address*Bit Name Function Reset

Default

0x8LP88 15:0 FRM_CEC[15:0] CRC Error Counter. This register contains the 16-bit count of

received CRC errors. CRC errors are not counted during loss of

CRC multiframe alignment.

0x0

Address*Bit Name Function Reset

Default

0x8LP89 15:0 FRM_REC[15:0] Receive E-bit Counter. This register contains the 16-bit count of

received E bit = 0 events. E bit = 0 events are not counted during

loss of CEPT CRC-4 multiframe alignment.

0x0

Address*Bit Name Function Reset

Default

0x8LP8A 15:0 FRM_CETE[15:0] Sa6 = 00x1 Event Counter. This register contains the 16-bit

count of received Sa6 = 00x1 events. The Sa6 code is detected

synchronously to the CRC-4 multiframe and is not counted dur-

ing loss of CRC-4 multiframe alignment. This detection is not

qualified by Sa5 = 1.

0x0000

Address*Bit Name Function Reset

Default

0x8LP8B 15:0 FRM_CENT[15:0] Sa6 = 001x Event Counter. This register contains the 16-bit

count of received Sa6 = 001x events. The Sa6 code is detected

synchronously to the CRC-4 multiframe and is not counted dur-

ing loss of CRC-4 multiframe alignment. This detection is not

qualified by Sa5 = 1.

0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

291Agere Systems Inc.

12 28-Channel Framer Registers (continued)

The register in Table 406 provides a status indication of functional elements (FE) exchanged between the access

digital section and the exchange termination (ET), as defined in ETS 300 233, Section 9.3 and Table 2. These are

decoded from the A, Sa5, and Sa6 bits. The Sa6 code words are synchronized to the CRC-4 multiframe.

Table 406. FRM_PMLR13, Performance Monitor Link Register 13 (COR)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function

(A, Sa5, Sa6[1:4]) Reset

Default

0x8LP8C 15:14 RSVD Reserved. Must write to 0. 00

13 FRM_FE_OP Defect FCET in the ET or FCDLd in the Digital Link Between V3

and V3 or Defect FCDLu Between V3 and V3. AIS. 0

12 FRM_FE_N Reception of AIS at V3 Reference Point of LT and FC4 Simulta-

neously. (0, 1, 1111.) 0

11 FRM_FE_M Reception of AIS at V 3 Reference Point of LT (Reaction to FCDL

or FCET). (1, 1, 1111.) 0

10 FRM_FE_L LOS at Line Side of LT (FC1). AUXP. 0

9FRM_FE_KLoss of Power at NT1 and LOS/LFA at TE Simultaneously. (1, 1,

1000.) 0

8FRM_FE_ILoss of Power at NTT. (0, 1, 1000.) 0

7FRM_FE_HSimultaneous FC3 and FC4. (0, 1, 1110.) 0

6FRM_FE_GLOS/LFA at T Reference Point of NT1. (0, 1, 1100.) 0

5FRM_FE_FLOS/LFA at V3 Reference Point of ET. (1, 0, 0000.) 0

4FRM_FE_ELOS at Line Side of NT1 or at V3 Reference Point of LT Only. (1,

1, 1110.) 0

3FRM_FE_DLOS/LFA at TE. (1, 1, 00xx.) 0

2FRM_FE_CUnintentional Loopback. (x, 0, xxxx.) 0

1FRM_FE_BNormal Operation of the ET. (x, 0, 0000.) 0

0FRM_FE_ANormal Operation of the DS. (x, 1, 00xx.) 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

292 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

The register in Table 407 provides a status indication of functional elements (FE) exchanged between the access

digital section and the exchange termination (ET), as defined in ETS 300 233, Section 9.3 and Table 3 and Table

Table 407. FRM_PMLR14, Performance Monitor Link Register 14 (COR)

* See Table 393 on page 279 for values of L and P.

Table 408. FRM_PMLR15, Performance Monitor Link Register 15 (COR)

* See Table 393 on page 279 for values of L and P.

Table 409. FRM_PMLR16, Performance Monitor Link Register 16 (COR)

* See Table 393 on page 279 for values of L and P.

Table 410. FRM_PMLR17, Performance Monitor Link Register 17 (COR)

* See Table 393 on page 279 for values of L and P.

Table 411. FRM_PMLR18, Performance Monitor Link Register 18 (COR)

* See Table 393 on page 279 for values of L and P.

Address*Bit Name Function

(A, Sa5, Sa6[1:4], E) Reset

Default

0x8LP8D 15:9 RSVD Reserved. Must write to 0. 0x000

8FRM_FE_YSimultaneous Occurrence of FE_W and FE_X. (x, 1, 0011, x.) 0

7FRM_FE_XCRC Error Detected at T Reference Point of NT1. (x, 1, 0010, x.) 0

6FRM_FE_WCRC Error Reported from TE. (x, 1, 0001, x.) 0

5FRM_FE_VCRC Error Information from ET. (x, 0, 0000, 0.) 0

4FRM_FE_UCRC Error Report from NT1 Line Side. (x, 1, xxxx, 0. ) 0

3FRM_FE_TLoopback Release Command. (x, 0, 0000, x.) 0

2FRM_FE_SLoopback Acknowledge. (1, 0, xxxx, x.) 0

1FRM_FE_RLoopback 2 Command. (1, 0, 1010, x.) 0

0FRM_FE_QLoopback 1 Command. (1, 0, 1111, x.) 0

Address*Bit Name Function Reset

Default

0x8LP8E 15:0 FRM_ESC[15:0] Errored Second Counter. This register contains the 16-bit

count of errored seconds. 0x0000

Address*Bit Name Function Reset

Default

0x8LP8F 15:0 FRM_BESC[15:0] Bursts Errored Second Counter. This register contains the

16-bit count of bursty errored seconds. 0x0000

Address*Bit Name Function Reset

Default

0x8LP90 15:0 FRM_SESC[15:0] Severely Errored S econd Counte r. This register contains the

16-bit count of severely errored seconds. 0x0000

Address*Bit Name Function Reset

Default

0x8LP91 15:8 RSVD Reserved. Must write to 0. 0x00

7:0 FRM_RBOM[7:0] Received Bit-Oriented Message (0xxxxxx0). Note that only

storing the 8 bits that contain actual data, the first eight ones are

not stored.

0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

293Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 412. FRM_PMLR19, Performance Monitor Link Register 19 (COR)

This register applies to the receive path only.

* See Table 393 on page 279 for values of L and P.

Table 413. FRM_PMLR20, Performance Monitor Link Register 20 (COR)

* See Table 393 on page 279 for values of L and P.

12.11 Receive Facility Data Link Configuration and Status Registers

Table 414. Receive Facility Data Link Register Addressing Map

* L and R represe nt hexidecimal digits used for absolute addressing in Table 416 on page 294 through Table 420 on page 295.

Address*Bit Name Function Reset

Default

0x8LP92 15:5 RSVD Reserved. Must write to 0. 0x000

4:1 FRM_HGALIGN[3:0] Indicates HG Alignment for the Associated HG on Each

Link. The status will be given for a particular link any time

that link appears on the TDM bus. A 1 in any bit position indi-

cates that alignment has been achieved. A 0 indicates align-

ment is lost or handling groups are disabled.

Note: For receive path only.

0000

0FRM_SEFSSeverely Errored Frame Status. (See ANSI T1.4 0 3

9.4.2.2.2 for ESF and T1.231 6.1.2.2.2 for SF.)

Note: For receive and transmit path.

Address*Bit Name Function Reset

Default

0x8LP93 15:13 RSVD Reserved. Must write to 0. 000

12:7 FRM_G[6:1] PRM Message Bit G6—G1. 0

6FRM_SEPRM Message Bit SE. 0

5FRM_FEPRM Message Bit FE. 0

4FRM_LVPRM Message Bit LV. 0

3FRM_SLPRM Message Bit SL. 0

2FRM_LBPRM Message Bit LB. 0

1FRM_N1PRM Message Bit N1. 0

0FRM_N0PRM Message Bit N0. 0

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 RXP = 0 1100RDL3RDL2RDL1RDL0

L* R* —

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

294 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 415. Receive Path Facility Data Link Registers Address Indexing

Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

Table 416. FRM_RFDLLR1—FRM_RFDLLR5, Receive FDL Link Registers 1—5 (RO)

* See Table 415 for values of L and R.

Table 417. FRM_RFDLLR6, Receive FDL Link Register 6 (R/W)

* See Table 415 for values of L and R.

Table 418. FRM_RFDLLR7, Receive FDL Link Register 7 (RO)

* See Table 415 for values of L and R.

Link L R Link L R Link L R Link L R

1 0x00x2 8 0x10x0160x20x0240x30x0

2 0x00x4 9 0x10x2170x20x2250x30x2

3 0x00x6100x10x4180x20x4260x30x4

4 0x00x8110x10x6190x20x6270x30x6

5 0x00xA120x10x8200x20x8280x30x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA — — —

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC — — —

— — — 15 0x1 0xE 23 0x2 0xE — — —

Address*Bit Name Function Reset

Default

0x8LRC0 15:0 FRM_RXS0[15:0] Rx Stack Data 0. 0x0

0x8LRC1 15:0 FRM_RXS1[15:0] Rx Stack Data 1. 0x0

0x8LRC2 15:0 FRM_RXS2[15:0] Rx Stack Data 2. 0x0

0x8LRC3 15:0 FRM_RXS3[15:0] Rx Stack Data 3. 0x0

0x8LRC4 15:0 FRM_RXS4[15:0] Rx Stack Data 4. 0x0

Address*Bit Name Function Reset

Default

0x8LRC5 15:1 RSVD Reserved. Must write to 0. 0x0

0 FRM_RXCRCS M CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will

be stored based on multiframe alignment. If multiframe

alignment is lost, the stack will not be made available to the

host. When set to 1, the Sa bits will be stored based on an

arbitrary multiframe alignment when only basic frame

alignment can be established.

Address*Bit Name Function Reset

Default

0x8LRC6 15:1 RSVD Reserved. Reads 0. 0x0

0FRM_RXSARx Stack Available. A 1 in di ca t es tha t the R x st ac k i s a va il a bl e

for reading. 0 indicates that the stack is being updated and

should not be read. In order to prevent a mix of old and new

data being read, the host should verify that this bit is set to 1

before continuing to read the stack.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

295Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 419. FRM_RFDLLR8, Receive FDL Link Register 8 (COR)

* See Table 415 on page 294 for values of L and R.

Table 420. FRM_RFDLLR9, Receive FDL Link Register 9 (R/W)

* See Table 415 on page 294 for values of L and R.

12.12 Transmit Facility Data Link Configura tion an d Status Registers

Table 421. Transmit Facility Data Link Register Addressing Map

* L and R represe nt hexidecimal digits used for absolute addressing in Table 423 through Table 427.

Table 422. Transmit Path Facility Data Link Registers Address Indexing

Read: for link 1, the hexidecimal digit L is 0x0 and the hexidecimal digit T is 0x3.

Table 423. FRM_TFDLLR1—FRM_TFDLR5, Transmit FDL Link Registers 1—5 (COR)

* See Table 422 for values of L and T.

Address*Bit Name Function Reset

Default

0x8LRC7 15:1 RSVD Reserved. Read s 0. 0x0

0 FRM_RXSR_IS Rx Stack Ready Interrupt. A 1 indicates that the Rx stack has

been filled with data following the format of the associated link. 0

Address*Bit Name Function Reset

Default

0x8LRC8 15:1 RSVD Reserved. Must write to 0. 0x0

0 FRM_MRXSR Mask Rx Stack Ready Interrupt. A 1 masks the Rx stack

ready interrupt. 1

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 TXP = 1 1101TDL3TDL2TDL1TDL0

L* T* —

Link L T Link L T Link L T Link L T

1 0x00x3 8 0x10x1160x20x1240x30x1

2 0x00x5 9 0x10x3170x20x3250x30x3

3 0x00x7100x10x5180x20x5260x30x5

4 0x00x9110x10x7190x20x7270x30x7

5 0x00xB120x10x9200x20x9280x30x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB — — —

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD — — —

— — — 15 0x1 0xF 23 0x2 0xF — — —

Address*Bit Name Function Reset Default

0x8LTD0 15:0 FRM_TXS0[15:0] Tx Stack Data 0. 0x0000

0x8LTD1 15:0 FRM_TXS1[15:0] Tx Stack Data 1. 0x0000

0x8LTD2 15:0 FRM_TXS2[15:0] Tx Stack Data 2. 0x0000

0x8LTD3 15:0 FRM_TXS3[15:0] Tx Stack Data 3. 0x0000

0x8LTD4 15:0 FRM_TXS4[15:0] Tx Stack Data 4. 0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

296 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 424. FRM_TFDLLR6, Transmit FDL Link Register 6 (R/W)

* See Table 422 on page 295 for values of L and T.

Address*Bit Name Function Reset

Default

0x8LTD5 15:8 RSVD Reserved. Must write to 0. 0x0

7 FRM_SA8SC Sa8 Source Control. A 1 indicates that Sa8 is sourced from the

TXFDL stack. Zero indicates that Sa8 is sourced from the time

slot 0 data of the system interface in switching mode, or from

time slot 0 data received by the transmit path receive aligner in

transp ar ent mod e.

6 FRM_SA7SC Sa7 Source Control. A 1 indicates that Sa7 is sourced from the

TXFDL stack. Zero indicates that Sa7 is sourced from the time

slot 0 data of the system interface in switching mode, or from

time slot 0 data received by the transmit path receive aligner in

transp ar ent mod e.

5 FRM_SA6SC Sa6 Source Control. A 1 indicates that Sa6 is sourced from the

TXFDL stack. Zero indicates that Sa6 is sourced from the time

slot 0 data of the system interface in switching mode, or from

time slot 0 data received by the transmit path receive aligner in

transp ar ent mod e.

4 FRM_SA5SC Sa5 Source Control. A 1 indicates that Sa5 is sourced from the

TXFDL stack. Zero indicates that Sa5 is sourced from the time

slot 0 data of the system interface in switching mode, or from

time slot 0 data received by the transmit path receive aligner in

transp ar ent mod e.

3 FRM_SA4SC Sa4 Source Control. A 1 indicates that Sa4 is sourced from the

TXFDL stack. Zero indicates that Sa4 is sourced from the time

slot 0 data of the system interface in switching mode, or from

time slot 0 data received by the transmit path receive aligner in

transp ar ent mod e.

2 FRM_TXCRCSM CEPT CRC-4 Stack Mode. When set to 0, the Sa bits will be

transmitted based on being active. If MFA is lost, the stack will

not be transmitted. When set to 1, the Sa bits will be transmitted

based on BFA (basic frame alignment) only.

1FRM_ASRCAlignment Source. A 1 indicates that the MFA and BFA will be

used to determine if a BOM or stack is transmitted. A 0 indicates

that, when enabled for insertion, BOMs and stacks will be

inserted whenever the TDM data is requested.

0FRM_DS1IDS1 Insertion. A 1 enables this block to insert the contents of

the stack into the associated DS1 link. For SLC-96 links, D bits

will be inserted given the associated stack format. For DDS

links, data-link bits will be inserted given the associated stack

format. For other DS1 link types, this bit has no effect. A 0 dis-

ables this block from inserting D bits or data link bits into the

associated link.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

297Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 425. FRM_TFDLLR7, Transmit FDL Link Register 7 (R/W)

* See Table 422 on page 295 for values of L and T.

Table 426. FRM_TFDLLR8, Transmit FDL Link Register 8 (RO/COW)

* See Table 422 on page 295 for values of L and T.

Table 427. FRM_TFDLLR9, Transmit FDL Link Register 9 (R/W)

* See Table 422 on page 295 for values of L and T.

Address*Bit Name Function Reset

Default

0x8LTD6 15:7 RSVD Reserved. Must write to 0. 0x000

6FRM_BOMETransmit Bit-Oriented Message Enable. A 1 indicates that the

BOM message register has been initialized and should be transmit-

ted on the data link of the ESF frame. The pattern will continue to

be transmitted until the enable is removed. When set to 0, the BOM

transmission will stop immediately without completing the current

pattern transmission or without completing the series of 10 pat-

terns.

5:0 FRM_TBOM[5:0] Transmit Bit-Oriented Messa ge . Indic ate s the con ten ts of the

BOM to be transmitted when enabled with FRM_BOME. A pattern

of 111110 implies a BOM of 0111110011111111 with the

right-mo st bit being tr ansmi tted first.

Address*Bit Name Function Reset

Default

0x8LTD7 15:2 RSVD Reserved. Must write to 0. 0000000

0000000

1 FRM_BOMC_IS BOM Complete Interrupt. (Clear on write.) A 1 indicates that

the BOM register contents have been transmitted 10 times over

the data link of the ESF frame.

0 FRM_TXSE_IS Tx Stack Empty Interrupt. (Clear on write.) A 1 indicates that

the Tx stack is empty. 0 indicates that the host has finished

updating the stack. The Tx data link block sets this bit when the

stack is empty, and needs to be filled if the D bits or Sa bits

require changing. If the stack is not refilled, the old data will be

retransmitted.The new data can be written anytime without

interfering with the current transmission. The stack needs to be

updated within 9 ms for an SLC-96 link or 4 ms for a CEPT link

in order for the new information to be transmitted in the next

double multiframe.

Address*Bit Name Function Reset

Default

0x8LTD8 15:2 RSVD Reserved. Must write to 0. 0000000

0000000

1 FRM_BOMC_IM Mask BOM Complete Interrupt. A 1 mask s the BOM comp lete

interrupt, FRM_BOMC. 1

0 FRM_TXSE_IM Mask Tx Stack Empty Interrupt. A 1 masks the Tx s tack

empty interrupt, FRM_TXSE. 1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

298 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.13 System Interface, Arbiter, and Frame Fo rmatter Mapping

Table 428. System Interface, Arbiter, and Frame Formatter Link Register Addressing Map

* L and P represent hexidecimal digits used for absolute addressing in Table 431 through Table 437.

Table 429. System Interface, Arbiter, and Frame Formatter Link Register Address Indexing

Read: for link 1 on the receive path, the hexidecimal digit L is 0x0 and the hexidecimal digit P is 0x2.

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

0 0 LNK4 LNK3 LNK2 LNK1 LNK0 RXP = 0/TXP = 1 1 1 1 0 0 SYS2 SYS1 SYS0

L* P* —

Link L P Link L P Link L P Link L P

Receive Path (P is even)

1 0x00x2 8 0x10x0160x20x0240x30x0

2 0x00x4 9 0x10x2170x20x2250x30x2

3 0x00x6100x10x4180x20x4260x30x4

4 0x00x8110x10x6190x20x6270x30x6

5 0x00xA120x10x8200x20x8280x30x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA — — —

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC — — —

— — — 15 0x1 0xE 23 0x2 0xE — — —

Transmit Path (P is odd)

1 0x00x3 8 0x10x1160x20x1240x30x1

2 0x00x5 9 0x10x3170x20x3250x30x3

3 0x00x7100x10x5180x20x5260x30x5

4 0x00x9110x10x7190x20x7270x30x7

5 0x00xB120x10x9200x20x9280x30x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB — — —

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD — — —

— — — 15 0x1 0xF 23 0x2 0xF — — —

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

299Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.14 System Interface Per Link Reg is ters

Table 430. FRM_SYSLR1, System Interface Link Register 1 (R/W)

* See Table 429 on page 298 for values of L and P.

Table 431. FRM_SYSLR2, System Interface Link Register 2 (R/W)

This register applies to the receive path only, inserted in the transmit system interface on demand.

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPE0 15 RSVD Reserved. Must write to 0. 0

14:8 FRM_BYOFF[6:0] CHI Byte Offset. This bit is only applicable in the CHI mode. 0000000

7RSVDReserved. Must write to 0. 0

6:4 FRM_OFF[2:0] CHI Bit Offset. 000

3:2 RSVD Reserved. Must write to 0. 0

1 FRM_HALFOFF Half Bit Offset. When set to 1, an offset of 1/2 bit is added to

offsets. 0

0 FRM_QUAROFF Quarter Bit Offset. When set to 1, an offset of 1/4 bit is

added to the offsets. CHI CMS mode only. 0

Address*Bit Name Function Reset

Default

0x8LPE1 15 FRM_CEPTMAIS Transmit CEPT TS16 AIS.

0 = no action.

1 = time slot 16 is forced to all ones.

14 FRM_CEPTAAIS Transmit CEPT TS16 AIS on Loss of MFA.

0 = no action.

1 = time slot 16 is forced to all ones when time slot 16

multiframe alignment is lost.

13 FRM_MANAIS Transmit System AIS.

0 = no action.

1 = transmit system AIS to the system.

12 FRM_CEPTSTMP Transmit System CEPT TS16 Stomp.

0 = no action.

1 = if upper or lower nibble of time slot 16 is 0000, then it is

changed to 1111 toward the transmit system interface.

11:0 RSVD Reserved. Must write to 0. 0x000

Table 432. FRM_SYSLR3—FRM_SYSLR6, System Interface Link Registers 3—6 (R/W)

Address*Bit Name Function Reset

Default

0x8LPE2 15:0 RSVD Reserved. Must w rite to 0. 0x0000

0x8LPE3 15:0 RSVD Reserved. Must w rite to 0. 0x0000

0x8LPE4 15:0 RSVD Reserved. Must w rite to 0. 0x0000

0x8LPE5 15:0 RSVD Reserved. Must w rite to 0. 0x0000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

300 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.15 Arbiter Framer Per Link Registers

Table 433. FRM_ARLR1, Arbiter Link Register 1 (R/W)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPF0 15 FRM_LNK_ENA Link Enable.

0 = link is disabled.

1 = link is enabled.

14 FRM_LNK_TRANSP Transparent Mode Selection.

Switching:

0 = the link is in a nontransparent mode. (Regenerate

framing bits and CRC bits.)

1 = the link is in transparent mode. (Flow through framing

bits and CRC bits.)

Transport:

0 = nontransparent mode (regenerate CRC bits and flow

through framing bits).

1 = transparent mode (flow through framing bits and CRC

bits).

13 FRM_LNK_RESTARTN Restart Link.

0 = Restart the link.

1 = Normal operational mode for the link.

12 FRM_LNK_REFRAME Force Reframe.

0 = normal operational mode for the link.

1 = link is forced to reframe.

11:10 RSVD Reserved. Must write to 0. 0

9 FRM_ICKEDGE Input Clock Edge Selection.

0 = sample data on rising edge of input clock.

1 = sample data on falling edge of input clock.

8:0 RSVD Reserved. Must write to 0. 000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

301Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPF1 15 FRM_ESF_CRC_EN CRC Framing Enable.

DS1 Modes: ESF CRC framing algorithm enable:

0 = ESF CRC framing disabled.

1 = ESF CRC framing enabled. (Enables inclusion of CRC

in the frame search algorithm.)

CEPT Modes: CRC-4 multiframe:

0 = multiframe reframe disabled.

1 = multiframe reframe enabled. (Enables the inclusion of

the following criteria to the CEPT loss of multiframe

criteria. Three consecutive multiframe alignment

pattern bit errors will cause a search for a new

multiframe alignment. Basic frame alignment is not

lost.)

14 FRM_FAST Fast Frame Mode.

DS1 Modes:

0 = disable quick frame recovery.

1 = enable quick frame recovery as follows:

D4 and J-D4: 36 fewer frame bits are checked.

SLC-96: Eighteen fewer FT bits are checked during the

search for FT framing.

DDS: No change.

CEPT Modes:

0 = disable quick frame recovery.

1 = this bit enables the (n + 2) framing research algorithm

as defined in the note in Recom men dation G.706,

Section 4.1.2. When an FAS is found in frame n,

frame (n + 1) is checked to ensure that it is a non-F AS

frame and frame (n + 2) is checked for F AS. Failure to

meet either of these conditions results in a new

search in frame (n + 2).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

302 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPF1 13:12 FRM_OPT[1:0] Frame Options.

DS1 Mode:

00 = the frame aligner will not frame up until all mimics are

gone.

01 = time-out algorithm is enabled. A counter is started

when, for the first time, one of the 193-bit positions

contains a sequence long enough to declare frame

but is prevented from doing so by the presence of a

mimic. The provisionable counter sets a time limit for

mimics to go away. If there are still mimics, a

candidate bit position that has met the minimum

framing requirements is chosen and frame alignment

is made to that position. See FRM_TO[7:0]

(Table 317).

Others reserved.

CEPT Mode:

00 = no change.

01 = enables an extra NOTFAS frame check. This can

prevent frame alignment on PRBS patterns which

contain a pseudoframing pattern. The CEPT framing

sequence now becomes:

Find FAS (n).

Verify NOTFAS frame (n + 1).

Verify second FAS in frame (n + 2).

Verify second NOTFAS frame (n + 3).

Others reserved.

11 FRM_FBE_MODE DDS FBE Mode.

0 = allows two FBEs to be detected in a frame in DDS

mode: one FBE for the frame bit (FT and FS) and one

FBE for the time slot 24 frame alignment signal.

1 = only 1 FBE is detected in a frame in DDS mode.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

303Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPF1 10:8 FRM_LF_CRT[2:0] Loss of Frame Criteria.

DS1 Mode:

000 = 2 errored framing bits out of 4 FT and FS bits.

001 = 2 errored framing bits out of 5 FT and FS bits.

010 = 2 errored framing bits out of 6 FT and FS bits.

011 = 3 errored framing bits out of 12 FT, Fs, and channel

24 FAS bits (DDS only).

100 = 2 errored framing bits out of 4 FT bits only.

101 = 2 errored framing bits out of 5 FT bits only.

110 = 2 errored framing bits out of 6 FT bits only.

111 = 4 errored framing bits out of 12 FT, FS, and channel

24 FAS bits (DDS only).

CEPT Mode:

000 = 3 consecutive errored FAS patterns.

x01 = 3 consecutive errored FAS patterns or 3 consecu-

tive errored NOTFAS bits (bit 2).

x10 = 3 consecutive errored frames (FAS and NOTFAS).

Others are reserved.

7RSVDReserved. Must write to 0. 0

6FRM_AUTO_AISAuto AIS.

0 = AUTO AIS is disabled.

1 = AUTO AIS is enabled.

When AUTO AIS is enabled, the receive arbiter data is

forced to 1 when out of frame.

5:4 FRM_RAIL3_DEC[1:0] Third Rail Option.

00 = third input signal to the frame aligner is ignored.

01 = third input is bipolar violations (in the CMI mode,

CRVs are also included on the RBPV input, but not

passed through the frame aligner).

10 = third rail is frame sync used to indicate time-slot

alignment. The multiframe alignment is determined

by the frame sync.

11 = third rail is frame sync used to indicate framing bit

positi on. Mul tifra me ali gnm ent is searc hed for

expedi ted by the frame sy nc .

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

304 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 434. FRM_ARLR2, Arbiter Link Register 2 (R/W) (continued)

* See Table 429 on page 298 for values of L and P.

Table 435. FRM_ARLR3, Arbiter Link Register 3 (R/W)

This register applies to the transmit path only.

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset Default

0x8LPF1 3:0 FRM_MODE[3:0] Framing Mode.

0000 = nonalign 256 bit.

0001 = CEPT basic frame.

0010 = CEPT with CRC-4 and 100 ms timer.

0011 = CMI.

0100 = CEPT with CRC-4 and 400 ms timer.

0101 = reserved. (Future J2 - G.704.)

0110 = reserved. (Future J2 - NTT Y.)

0111 = re served.

1000 = nonalign 193 bits.

1001 = SF (FT bits only).

1010 = J-ES F.

1011 = ESF.

1100 = D4.

1101 = J-D4 (SF with Japanese Yellow Alarm).

1110 = DDS.

1111 = SLC-96.

1011

Address*Bit Name Function Reset Default

0x8LPF2 15 FRM_TP_CK_

SRC_EN Framer Transmit Path Clock Source Enable.

0 = FRM_TP_CK_SRC bit is disabled. FRM_SW_TRN

(Table 313 on page 246) bit controls clock source.

1 = FRM_TP_CK_SRC bit is enabled. FRM_SW_TRN bit

is ignored.

Transmit path clock and data is selected with bits

FRM_TP_ CK_ SRC and FR M_TP _DD_ SRC.

14 FRM_TP_CK_

SRC Transmit Path Clock Source.

0 = transmit clock comes from the frame aligner (transport

applications).

1 = transmit clock comes from the system interface

(switching applications).

13 FRM_TP_DD_

SRC Transmit Path Default Data Source.

0 = transmit data comes from the frame aligner (transport

applications).

1 = transmit data comes from the system interface

(switching applications).

12:1 RSVD Reserved. Must write to 0. 0000

0FRM_SYSFSMSystem Frame Sync Mask. A 1 masks the system frame

synchronization signal in the transmit framer formatter.

Note: For those applications that have jitter on the transmit

cloc k signal relative to the system clock signal,

enable this bit so that the jitter is isolated from the

transmit framer.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

305Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.16 Frame Formatter Per Link Registers

Table 436. FRM_FFLR1, Frame Formatter Link Register 1 (R/W)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Reset

Default

0x8LPF4 15:12 RSVD Reserved. Must write to 0. 0000

11 FRM_ESFRAMD ESF Remote Alarm Indicator Mode.

0 = data link remote alarm sequence is 1111 1111 0000 0000.

1 = data link remote alarm is all ones.

10:8 FRM_ZCSMD[2:0] Zero Code Suppression Modes.

000 = ZCS off.

001 = set bit 6 (numbered 0—7) of all time slots.

011 = set bit 6 of all 0-byte time slots.

101 = set bit 6 of all voice time slots.

111 = set bit 6 of all 0-byte voice time slots.

110 = set 0-byte time slots to 1001 1000.

100, 010 = reserved.

(Signaling F and G bits identify voice time slots.)

000

7RSVDReserved. Must write to 0. 0

6 FRM_OCKEDGE Output Clock Edge Selection.

0 = data clocked out on rising clock edge.

1 = data clocked out on falling clock edge.

5:4 RSVD Reserved. Must write to 0. 0

3 FRM_AUTOPLB Automatic Payload Loopback (ESF Framing Only).

0 = ignore received payload loopback requests.

1 = automatically start payload loopback when payload loop-

back signal is received.

2 FRM_AUTOLLB Automatic Line Loopback (SF a nd ESF Framing Only).

0 = ignore received line loopback requests.

1 = automatically start line loopback when line loopback signal

is rec eived.

1 FRM_AUTOEBIT Automatic E-Bit Insertion (CEPT Framing Only).

0 = ignore E-bit insertion requests from PM.

1 = automatically insert E bits when indicated by PM.

0 FRM_AUTORAI Automatic RAI Insertion.

0 = ignore RAI insertion requests from PM.

1 = automatically insert RAI when indicated by PM.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

306 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 437. FRM_FFLR2, Frame Formatter Link Register 2 (R/W)

* See Table 429 on page 298 for values of L and P.

Address*Bit Name Function Re set

Default

0x8LPF5 15:14 FRM_TXLBMD[1:0] Transmit Loopback Modes.

00 = loopbacks off.

01 = line loopback.

10 = payload line loopback pass through. (The received payload

data, the CRC bits, and the frame al ignment bits are looped

back to the line. The data link bits are inserted.)

11 = payload line loopback regenerate. (The received payload

data is looped back to the line. The CRC bits, the frame

alignment bits, and data link bits are r egenerated and

inserted.)

13:10 RSVD Reserved. Must write to 0. 0000

9 FRM_TXLLBOFF Transmit D4 SF Line Loopback Off Code.

0 = do not transmit the D4 SF line loopback off code.

1 = transmit the D4 SF line loopback off code. (Repeated 001

patterns with the framing bits overwriting the pattern

T1.403, Section 9.3.1.2.)

8 FRM_TXLLBON Transmit D4 SF Line Loopback On Code.

0 = do not transmit the D4 SF line loopback on code.

1 = transmit the D4 SF line loopback on code. (Repeated

00001 patterns with the framing bits overwriting the pat-

tern T1.403, Section 9.3.1.1.)

7:6 RSVD Reserved. Must write to 0. 0

5 FRM_TXIID Transmit DS1 Idle ID (Fixed Pattern Defined inT1.403,

Section D.2).

Note: For ESF, the Supermapper only transmits the framed

pattern in the outgoing DS1 to send RAI along with the idle

code. Bit 2 (FRM_TXRAI) of this register has to be set.

0 = on demand idle ID off.

1 = on demand idle ID on (send idle ID).

4 FRM_TXAUXP Transmit AUXP.

0 = on demand AUXP off.

1 = on demand AUXP on (send AUXP).

3RSVDReserved. —

2 FRM_TXRAI Transmit RAI.

0 = on demand RAI off.

1 = on demand RAI on (send RAI).

1RSVDReserved. —

0FRM_TXAISTransmit AIS.

0 = on demand AIS off.

1 = on demand AIS on (send AIS).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

307Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.17 Line Decoder/Enco de r Pe r Link Reg is ters

Table 438. Line Decoder Per Link Register Addressing Map

* L and R represent hexadecimal digits used for absolute addressing in Table 423 through Table 427.

Table 439. Line Decoder Per Link Registers Address Indexing

Read: for link 1, the hexadecimal digit L is 0x0 and the hexadecimal digit T is 0x3.

Table 440. Line Encoder Per Link Register Addressing Map

* L and R represent hexadecimal digits used for absolute addressing in Table 416 on page 294 through Table 420.

Table 441. Line Encoder Per Link Registers Address Indexing

Read: for link 1, the hexadecimal digit L is 0x0 and the hexidecimal digit R is 0x2.

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 TXP = 1 1111 1 1 0 0

L* T* —

Link L T Link L T Link L T Link L T

1 0x00x3 8 0x10x1160x20x1240x30x1

2 0x00x5 9 0x10x3170x20x3250x30x3

3 0x00x7100x10x5180x20x5260x30x5

4 0x00x9110x10x7190x20x7270x30x7

5 0x00xB120x10x9200x20x9280x30x9

6 0x0 0xD 13 0x1 0xB 21 0x2 0xB — — —

7 0x0 0xF 14 0x1 0xD 22 0x2 0xD — — —

— — — 15 0x1 0xF 23 0x2 0xF — — —

Address Pins (ADDR15—ADDR0)

151413 12 11 10 9 8 7654 3 2 1 0

00LNK4LNK3LNK2LNK1LNK0 RXP = 0 1111 1 1 0 0

L* R* —

Link L R Link L R Link L R Link L R

1 0x00x2 8 0x10x0160x20x0240x30x0

2 0x00x4 9 0x10x2170x20x2250x30x2

3 0x00x6100x10x4180x20x4260x30x4

4 0x00x8110x10x6190x20x6270x30x6

5 0x00xA120x10x8200x20x8280x30x8

6 0x0 0xC 13 0x1 0xA 21 0x2 0xA — — —

7 0x0 0xE 14 0x1 0xC 22 0x2 0xC — — —

— — — 15 0x1 0xE 23 0x2 0xE — — —

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

308 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.18 Line Encoder/Deco de r Pe r Link Reg is ters

Table 442. FRM_LDLR1, Line Decoder Link Register 1 (R/W)

* See Table 439 on page 307 for values of L and T.

Table 443. FRM_LDLR2, Line Encoder Link Register 2 (R/W)

* See Table 441 on page 307 for values of L and R.

Address*Bit Name Function Reset

Default

0x8LTFC 15:6 RSVD Reserved. Must write to 0. 0x000

5FRM_EXCZEROLine Format Violation Option.

0 = excessive zeros are not included in bipolar violations.

1 = excessive zeros are included in bipolar violations.

4 FRM_RLCLK_EDGE Receive Line Clock Edge Select.

0 = data and bipolar violations are latched in on the posi-

tive edge of the receive line interface clock (rlclk).

1 = data and bipolar violations are latched in on the neg-

ative edge of the receive line interface clock

(RLCLK0).

3RSVDReserved. Must write to 0. 0

2:0 FRM_LD_MODE[2:0] Line Decoder Mode.

000 = single-rail (CMI use single-rail).

001 = HDB3.

010 = B8ZS.

011 = AMI.

100 = reserved.

101 = reserved.

110 = reserved.

111 = reserved.

000

Address*Bit Name Function Reset

Default

0x8LRFD 15:5 RSVD Reserved. Must write to 0. 0x000

4 FRM_TLCLK_EDGE Transmit Line Clock Edge Select.

0 = data and frame sync are latched out on the positive

edge of the transmit line interface clock (TL_CLK).

1 = data and frame sync are latched out on the negative

edge of the transmit line interface clock (TL_CLK).

3RSVDReserved. Must write to 0. 0

2:0 FRM_LE_MODE[2:0] Line Encoder Mode.

000 = single-rail (CMI use single-rail).

001 = HDB3.

010 = B8ZS.

011 = AMI.

100 = reserved.

101 = reserved.

110 = reserved.

111 = reserved.

000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

309Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.19 HDLC Per Channel Configura tion and Status Regis ters

Table 444. HDLC Per Channel Register Addressing Map

* H and P represent hexidecimal digits used for absolute addressing in Table 445 through Table 458.

Table 445. FRM_HCR1, Transmit HDLC Channel Register 1 (R/W)

* See Table 444 for mapping of H and P.

Table 446. FRM_HCR2, Transmit HDLC Channel Register 2 (R/W)

* See Table 444 for mapping of H and P.

Address Pins (ADDR15—ADDR0)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

01HDLC Channels 1—64 (000000—111111) RXP= 0/

TXP = 1 000 Per Channel Register

HDL9 HDL8 HDL7 HDL6 HDL5 HDL4 HDL3 HDL2 HDL1 HDL0

H* P* —

Address*Bit Name Function Reset

Default

0x8HP80 15:13 RSVD Reserved. Must write to 0. 000

12:8 FRM_TTIMESLOT[4:0] Transmit HDLC Time Slot.

These bits indicate (in binary) the time-slot number

assigned to this channel.

0x0

7:0 FRM_TBIT_IM[7:0] Transmit HDLC Bit Assignment.

These bits indicate which bits of a time slot are to be

assigned to this channel (1 = bit assigned).

In loopback mode, set as follows:

00000000 = slowest (~6 kbits/s at 52 MHz).

10000000 = faster (~2x above).

11000000 = faster still (~4x slowest rate).

. . . .

11111111 = fastest (~1.5 Mbits/s at 52 MHz).

Note: If running a mix of loopback and nonloopback

channels, the loopback speed should not be set

faster than 11100000.

0x00

Address*Bit Name Function Reset

Default

0x8HP81 15:14 FRM_TFRAME_SEL[1:0] Transmit HDLC Frame Select.

These bits are encoded to select odd and/or even num-

bered frames assigned to this channel.

00 = no data selected.

01 = data to even frames selected (FS, FAS).

10 = data to odd frames selected (FT, NOTFAS, ESF-DL).

11 = data to all (even and odd) frames selected.

13:5 RSVD Reserved. Must write to 0. 0x000

4:0 FRM_TLINK[4:0] Transmit HDLC Link Select.

These bits indicate (in binary) the link number assigned to

this channel.

00000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

310 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

* See Table 444 on page 309 for mapping of H and P.

Table 447. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W)

Address*Bit Name Function Reset

Default

0x8HP82 15 FRM_THC_RESET Transmit HDLC Reset. When this bit is 1, the channel is

held in reset.

This clears status for the channel, disables the channel,

and clears the FIFO for the channel.

14 FRM_TENABL Transmit HDLC Enable. When this bit is 0, and written

to 1, the channel is reinitialized and enabled. When this bit

is 1, and written to 0, no further data will be transmitted

and any partial data being serialized will be lost. The

channel is disabled.

The user should reset the FIFO to prevent partial packets

from being transmitted once re-enabled. Writing the same

value as currently programmed has no effect.

13:11 RSVD Reserved. Must write to 0. 000

Bits 10:0, 3, 1:0 can only be written as the channel is being enabled, (i.e., bit 14 held 0 and is now being

written to 1).

0x8HP82 10:9 FRM_CFLAGS[1:0] Closing Flags. Only valid in HDLC mode. These bits

select one of four values (00 = FRM_FCNT0[4:0],

01 = FRM_FCNT1[4:0], 10 = FRM_FCNT2[4:0],

11 = FRM_F CNT3[4:0] (Table 345—Table 348)). This

value indicates the number of additional closing flags

inserted after an HDLC packet (e.g., if FRM_FCNT2[4:0]

is selected and it is set to 00100, then five flags are

inserted).

8 FRM_PRMEN PRM Enable. When 1, this channel is enabled to send

PRM packets automatically. When 0, this feature is dis-

abled. (Bit only for channels 1—28, or else reserved.)

When enabled, PRMs will not be sent until all four sec-

onds of PRM information are valid.

7 FRM_TLOOP HDLC Controller Loopback. When this bit is set to 1, the

channel will operate in loopback mode. When 0, the chan-

nel operates normally.

Note: The corresponding Rx channel should be enabled

before enabling the Tx channel for loopback.

6 FRM_C_R PRM C/R Bit. This bit is inserted as the C/R bit when

sending a PRM packet on this channel. (Bit only for chan-

nels 0—27, or else reserved.)

5 FRM_HTTHRSEL Transmit Threshold Select. This bit selec ts which of the

two programmable FIFO threshold values to use for this

channel (0 selects FRM_HTTHRSH0, Table 339, 1

selects FRM_HTTHRSH1, Table 340).

4FRM_IFCSFCS In ser t. Only valid in HDLC mode. When 0, this bit

indicates the FCS at the end of an HDLC packet should

be inserted. A 1 indicates that the internally computed

FCS will not be inserted at the end of the packet.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

311Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 447. FRM_HCR3, Transmit HDLC Channel Register 3 (R/W) (continued)

* See Table 444 on page 309 for mapping of H and P.

Table 448. FRM_HCR4, Transmit HDLC Channel Register 4 (RO)

* See Table 444 on page 309 for mapping of H and P.

Table 449. FRM_HCR5, Transmit HDLC Channel Register 5 (R/W)

* See Table 444 on page 309 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP82 3 FRM_HTIDLE HDLC Idle Select. Only valid in HDLC mode. This bit indi-

cates the idle fill character when the Tx FIFO is empty. A 0

means fill with flags (01111110). A 1 means fill with idle

(11111111).

2FRM_HTMODETransmit Channel Mode Select. A 0 indicates the chan-

nel is in HDLC mode. A 1 indicates the channel is in trans-

parent mode .

1:0 FRM_HXPIDLE[1:0] Transparent Idle Mode Character Select. Only valid in

transparent mode. These bits indicate one of the four pos-

sible 8-bit patterns to be sent when the Tx FIFO is empty.

(00 selects TXICHAR0, Table 341, 01 selects TXICHAR1,

Table 342, etc.)

Address*Bit Name Function Reset

Default

0x8HP83 15:3 RSVD Reserved. Reads 0. 0x000

2 FRM_HTUND Transmit FIFO Underrun. A 1 indicates this channel has

run out of data in the middle of an HDLC packet. In trans-

parent mode, it simply means the channel has run out of

data.

1FRM_HTDONET ransmit Done. A 1 indicates a complete packet has been

sent on this channel. 0

0 FRM_HTTHRSH Transmit FIFO Threshold Interrupt. A 1 indicates this

channel’s FIFO level has dropped below the programmed

threshold value.

Address*Bit Name Function Reset

Default

0x8HP84 15:3 RSVD Reserved. Must write to 0. 0x0

2 FRM_MHTUND Transmit FIFO Underrun In terr upt Mask. A 1 ma s ks the

corresponding channel’s FRM_HTUND status from caus-

ing an interrupt.

1 FRM_MHTDONE Transmit Done Interrupt Mask. A 1 masks the corre-

sponding channel’s FRM_HTDONE status from causing

an interrupt.

0 FRM_MHTTHRSH T ransmit FIFO Threshold Interrupt M ask. A 1 masks the

corresponding channel’s FRM_HTTHRSH status from

causing an interrupt.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

312 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 450. FRM_HCR6, Transmit HDLC Channel Register 6 (WO)

* See Table 444 on page 309 for mapping of H and P.

Table 451. FRM_HCR7, Transmit HDLC Channel Register 7 (RO)

* See Table 444 on page 309 for mapping of H and P.

Table 452. FRM_HCR8, Receive HDLC Channel Register 8 (R/W)

* See Table 444 on page 309 for mapping of H and P.

Table 453. FRM_HCR9, Receive HDLC Channel Register 9 (R/W)

* See Table 444 on page 309 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP85 15:10 RSVD Reserved. Must write to 0. 0x00

9:8 FRM_HTFUNC[1:0] Transmit Data Function. These two bits indicate the

action to be taken by writing this register:

00 = add DATA to the Tx FIFO (non-EOP).

01 = add DATA to the Tx FIFO as EOP data (i.e., last byte of

packet).

10 = abort last incomplete data packet in FIFO. (If written after

an EOP byte, this may abort the previous packet.)

11 = reserved.

7:0 FRM_HTDATA[7:0] Transmit Data Register. When FRM_HTFUNC[1:0] = 00

or 01, then these bits contain a byte of data to be written to

the FIFO.

0x00

Address*Bit Name Function Reset Default

0x8HP86 15:10 RSVD Reserved. Must write to 0. 0x0

9:0 FRM_HTCOUNT[9:0] Transmit FIFO Byte Count. These bits indicate

the number of bytes available to be filled in the Tx

FIFO for the specific channel.

x80 (x200 in

large buffer

mode)

Address*Bit Name Function Reset

Default

0x8HP00 15:13 RSVD Reserved. Must write to 0. 000

12:8 FRM_RTIMESLOT[4:0] Received HDLC Time Slot. These bits indicate (in

binary) the time-slot number assigned to this channel. 00000

7:0 FRM_RBIT_IM[7:0] Received HDLC Bit Assignment. These bits indicate

which bits of a time slot are to be assigned to this channel

(1 = bit assigned).

0x00

Address*Bit Name Function Reset

Default

0x8HP01 15:14 FRM_RFRAME_

SEL[1:0] Receive HDLC Frame Select. These bits are encoded to

select odd and/or even numbered frames assigned to this

channel.

00 = no data selected. (Use for loopback mode.)

01 = data from even frames selected (Fs, FAS).

10 = data from odd frames selected (FT, NOTFAS, ESF-DL).

11 = data from all (even and odd) frames selected.

000

13:5 RSVD Reserved. Must write to 0. 0x0

4:0 FRM_RLINK[4:0] Receive HDLC Link Select. These bits indicate (in binary)

the link number assigned to this channel. 00000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

313Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 454. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)

* See Table 444 on page 309 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP02 15 FRM_RHC_RESET Receive HDLC Reset. When this bit is 1, the channel is

held in reset. 0

14 RSVD Reserved. Must write to 0. 0

13 FRM_RENABL Receive HDLC Enable. When this bit is 0 and written to 1,

the channel is reinitialized (i.e., HDLC searching for open-

ing flag, transparent searching for alignment character if so

programmed) and enabled. When this bit is 1 and written to

0, any current HDLC packet will be aborted and the chan-

nel disabled. Writing the same value as currently pro-

grammed has no effect.

12 RSVD Reserved. Must write to 0. 0

Bits 11:0 can only be written as the channel is being enabled (i.e., bit 13 held 0 and is now being

written to 1).

11 FRM_RTHRSEL Receive FIFO Threshold Select. This bit se lect s whi ch of

the two programmable FIFO threshold values to use for

this channe l. (0 selects FRM _HRTHRSH0[9:0 ]

(Table 353), 1 selects FRM_HRTHRSH1[9:0], Table 354).

10 FRM_RFCS Receive FCS Option. Only valid in HDLC mode. When 1,

this bit indicates the FCS at the end of an HDLC packet

should be removed. A 0 indicates it should be kept as part

of the packet.

9 FRM_HRMODE Receive Channel Mode Select. A 0 indicates the channel

is in HDLC mode. A 1 indicates the channel is in transpar-

ent mode.

8 FRM_BYTAL Byte Alignment. This bit is only used in transparent mode

(forced to 1 in HDLC mode). A 0 indicates no byte align-

ment is done by the receiver. A 1 indicates that byte align-

ment will be done by the receiver once the

FRM_MATCH[7:0] code is found.

7:0 FRM_MATCH[7:0] Transparent Mode Pattern Match. Only valid in transpar-

ent mode with byte alignment. These bits indicate the pat-

tern to match to begin receiving transparent data (forced to

ones in HDLC mode).

0x0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

314 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 455. FRM_HCR11, Receive HDLC Channel Register 11 (RO)

* See Table 444 on page 309 for mapping of H and P.

Table 456. FRM_HCR12, Receive HDLC Channel Register 12 (R/W)

* See Table 444 on page 309 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP03 15:4 RSVD Reserved. Reads 0. 0x00 0

3 FRM_RIDLE Receive Channel Idle. A 1 indicates this channel has been

detected as idle. 0

2FRM_OVRReceive FIFO Overflow. A 1 indicates this channel’s FIFO

has overflowed. 0

1FRM_EOPEnd of Packet. A 1 indicates an end of packet has been

detected on this channel. 0

0 FRM_HRTHRSH Receive FIFO Threshold Interrupt. A 1 indicates this

channel’s FIFO has exceeded the programmed threshold

value.

Address*Bit Name Function Reset

Default

0x8HP04 15:4 RSVD Reserved. Must write to 0. 0x000

3 FRM_MIDLE Receive Channel Idle Interrupt Mask. A 1 masks this

channel’s idle detection interrupt. 1

2FRM_MOVRReceive FIFO Overflow Interrupt Mask. A 1 masks this

channel’s FIFO overflow interrupt. 1

1FRM_MEOPEnd of Packet Interrupt Mask. A 1 masks this channel’s

end of packet inte r ru pt. 1

0 FRM_MHRTHRSH Receive FIFO Thres hold Interr upt Mask. A 1 masks thi s

channel’s exceeded FIFO threshold interrupt. 1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

315Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 457. FRM_HCR13, Receive HDLC Channel Register 13 (RO)

* See Table 444 on page 309 for mapping of H and P.

Table 458. FRM_HGR14, Receive HDLC Channel Register 14 (COR)

* See Table 444 on page 309 for mapping of H and P.

Address*Bit Name Function Reset

Default

0x8HP05 15:11 RSVD Reserved. Reads 0. 00000

10 FRM_HMDA More Data Available. A 1 indicates that if the FIFO is

read again, valid data will be returned. A 0 indicates no

more data is available.

9FRM_HRVALIDReceive FIFO Valid Data. A 1 indicates the information

read from the FIFO is valid. A 0 indicates the FIFO was

empty and no information was available.

8FRM_HRTYPEReceive FIFO Data Type. A 0 indicates

FRM_HR_DATA[7:0] is data. A 1 indicates

FRM_HR_DATA[7:0] is status information.

7:0 FRM_HR_DATA[7:0] Receive FIFO Data. When FRM_HRTYPE = 0, these

bits contain a byte of data. When FRM_HRTYPE = 1, the

bits are defined below.

7FRM_HOVRFIFO Overflow. A 1 indicates the FIFO overflowed. 0

6FRM_HEOPEnd of Packet. A 1 indicates end of packet (normal

packet). 0

5 FRM_HCRCERR HDLC CRC Error. A 1 indicates a CRC error was

detected. 0

4FRM_HABRTHDLC Abort. A 1 indicates an abort was received. 0

3FRM_HIDLHDLC Idle. A 1 indicates idle (as defined by HDLC proto-

col) condition detected. 0

2:0 FRM_HBIT[2:0] Complete Byte Status. 111 indicates the last data

received was a complete byte.

These bits should be ignored if EOP is 0.

Address*Bit Name Function Reset

Default

0x8HP06 15:10 RSVD Reserved. Must write to 0. 0x00

9:0 FRM_HRCOUNT[9:0] Receive FIFO Byte Count. These bits indicate the

number of valid bytes contained in the Rx FIFO for the

specific channel.

0x000

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

316 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

12.20 28-Channe l Framer Block Register Map

Table 459. Framer Register M ap

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Superframer Global Registers—R/W

0x80000

Page 246 FRM_SFGR1 FRM_

SW_TRN FRM_LC_CNTRL[1:0] FRM_LOOP_

TIMING FRM_DS1_

CEPTN FRM_PLL_

BYPAS FRM_LG_BUF_MODE

0x80001

Page 247 FRM_SFGR2 FRM_TP_

SIG_PWDN FRM_RP_

SIG_PWDN FRM_TP_

RDL_PWDN FRM_RP_

TDL_PWDN FRM_TP_

RH_PWDN FRM_RP_

TH_PWDN FRM_TS_

PWDN FRM_RS_

PWDN FRM_TP_

PM_PWDN FRM_RP_

FF_PWDN FRM_TP_

RA_PWDN

0x80002

Page 248 FRM_SFGR3

(RO) FRM_RP_

SIG FRM_AR_IS FRM_TP_

RDL_IS FRM_TP_

TDL_IS FRM_RH_IS FRM_TH_IS FRM_TS_

IS FRM_RS_

IS FRM_TP_

PM_IS FRM_RP_

RDL_IS FRM_RP_

TDL_IS 000 0

0x80003

Page 248 FRM_SFGR4 FRM_VERSION[2:0]

0x80004

—

0x80009

RSVD

Arbiter (Framer) Global Registers—R/W

0x80010

Page 248 FRM_FGR1 FM_DIS_

LHSCD

0x80011

Page 249 FRM_FGR2 FRM_TC_

EN FRM_TC[7:0]

0x80012

Page 249 FRM_FGR3 FRM_

TPSSE_IM

0x80014

Page 249 FRM_FGR4

(COR) FRM_TPSSEI[16:1]

0x80015

Page 250 FRM_FGR5

(COR) FRM_TPSSEI[28:17]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

317Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Performance Monitor Global Registe rs—R/W

0x80P20

Page 250 FRM_PMGR1_

BFRM_

SEC_SEL FRM_GLB_

PL_CFG FRM_CT125[11:0]

0x80P30

Page 251 FRM_PMGR1

(COR) FRM_

DETECT FRM_

PTRNBER

0x80P31

Page 251 FRM_PMGR2 FRM_TPERR_CT[15:0]

0x80P32

Page 251 FRM_PMGR3 FRM_RAC[2:0] FRM_RDC[2:0] FRM_

FSFBEEN FRM_

CMFRFEN FRM_

CRCRFEN FRM_CEPTAISM[1:0] FRM_

DS1AISM FRM_

ESFRAIM FRM_

RAICLR

0x80P33

Page 252 FRM_PMGR4 FRM_SFSEST[15:0]

0x80P34

Page 252 FRM_PMGR5 FRM_DCT[15:0]

0x80P35

Page 253 FRM_PMGR6 FRM_ESFSEST[15:0]

0x80P36

Page 253 FRM_PMGR7 FRM_

DSEF FRM_DLFA FRM_DRFA FRM_

DSLIP FRM_

DLOS FRM_DAIS FRM_

DCRC FRM_DFS FRM_DFT

0x80P37

Page 253 FRM_PMGR8 FRM_CCT[15:0]

0x80P38

Page 253 FRM_PMGR9 FRM_CSEST[15:0]

0x80P39

Page 254 FRM_PMGR10 FRM_

CSA6_F FRM_

CSA6_E FRM_

CSA6_C FRM_

CSA6_8 FRM_

CSA6_1X FRM_

CSA6_X1 FRM_

CEBIT FRM_

CLMFA FRM_CLFA FRM_CRFA FRM_

CSLIP FRM_

CLOS FRM_CAIS FRM_

CCRC FRM_

CNOTFAS FRM_

CFAS

0x80P3A

Page 254 FRM_PMGR11 FRM_CRET[15:0]

0x80P3B

Page 255 FRM_PMGR12 FRM_

CRAI_

AIS

FRM_

CRAI_

OOF

FRM_

CRAI_

LOS

FRM_

CRAI_

SA6EQC

FRM_

CRAI_

SA6EQ8

FRM_

CRAI_

CRCTX

FRM_

CRAI_

LTS0MFA

FRM_

CRAI_

LTS16MFA

FRM_CRAI_

8MSEX SPLIT_

400MS_

100MS_EN

FRM_

DSRAI_

LOS

FRM_

DSRAI_

OOF

FRM_

DSRAI_AIS

0x80P3C

Page 256 FRM_PMGR13 FRM_

CFBE_

MODE

FRM_

CEBIT_

LTS0MFA

FRM_

CEBIT_

ESMF

FRM_

CEBIT_

CRCTX

0x80P3D

Page 256 FRM_PMGR14 FRM_

PTRN_EN FRM_

PTRN_INV FRM_

PTRN_

FRMT

FRM_PTRN_LNK[4:0] FRM_PTRN_SEL[3:0]

0x80P3E

Page 257 FRM_PMGR15 FRM_LN_IS[16:1]

0x80P3F

Page 257 FRM_PMGR16 FRM_LN_IS[28:17]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

318 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

HDLC Global Configuration and Status Registers—R/W

Transmit HDLC Global Registers

0x80140

Page 257 FRM_HGR1 FRM_HTTHRSH0[9:0]

0x80141

Page 257 FRM_HGR2 FRM_HTTHRSH1[9:0]

0x80142

Page 258 FRM_HGR3 FRM_TXICHAR0[7:0]

0x80143

Page 258 FRM_HGR4 FRM_TXICHAR1[7:0]

0x80144

Page 258 FRM_HGR5 FRM_TXICHAR2[7:0]

0x80145

Page 258 FRM_HGR6 FRM_TXICHAR3[7:0]

0x80146

Page 259 FRM_HGR7 FRM_FCNT0[4:0]

0x80147

Page 259 FRM_HGR8 FRM_FCNT1[4:0]

0x80148

Page 259 FRM_HGR9 FRM_FCNT2[4:0]

0x80149

Page 259 FRM_HGR10 FRM_FCNT3[4:0]

0x8014A

Page 259 FRM_HGR11 FRM_TH_IS[15:0]

0x8014B

Page 260 FRM_HGR12 FRM_TH_IS[31:16]

0x8014C

Page 260 FRM_HGR13 FRM_TH_IS[47:32]

0x8014D

Page 260 FRM_HGR14 FRM_TH_IS[63:48]

Receive HDLC Global Registers

0x80040

Page 260 FRM_HGR15 FRM_HRTHRSH0[9:0]

0x80041

Page 260 FRM_HGR16 FRM_HRTHRSH1[9:0]

0x80042

Page 260 FRM_HGR17 FRM_RH_IS[15:0]

0x80043

Page 261 FRM_HGR18 FRM_RH_IS[31:16]

0x80044

Page 261 FRM_HGR19 FRM_RH_IS[47:32]

0x80045

Page 261 FRM_HGR20 FRM_RH_IS[63:48]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

319Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 B it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

System Interface Global Registers—R/W

Receive System Interface Global Registers

0x80050

Page 261 FRM_SYSGR1 FRM_SYSMOD[3:0] FRM_ASM FRM_CMS FRM_

CHIDTS FRM_

STUFFL/FRM_

LNKSTART

FRM_

AISLFA FRM_

AISCRCT FRM_

DNOTFAS FRM_

TFSCKE FRM_

FSPOL

0x80051

Page 263 FRM_SYSGR2 FRM_HWYENA FRM_RSTDONE

(Read Only)

0x80052

Page 263 FRM_SYSGR3 FRM_STUFF[7:0] FRM_IDLE[7:0]

0x80053

Page 264 FRM_SYSGR4 FRM_

STSSLB FRM_

STSLLB FRM_TSLBA[4:0] FRM_TLSBL[4:0]

0x80054

Page 264 FRM_SYSGR5 FRM_TS_

DPAR FRM_TS_

SPAR

0x80055

Page 264 FRM_SYSGR6

0x80056

Page 265 FRM_SYSGR7 FRM_TPSB_FS_IS

0x80057

Page 265 FRMSYSGR8 FRM_PSB_FS_IM

Transmit System Interface Global Registers

0x80150

Page 265 FRM_SYSGR9 FRM_RS_

DPAR FRM_RS_

SPAR FRM_

RFSCKE

0x80151

Page 266 FRM_SYSGR10

0x80152

Page 266 FRM_SYSGR11

0x80153

Page 266 FRM_SYSGR12

0x80154

Page 266 FRM_SYSGR13

0x80155

Page 266 FRM_SYSGR14

0x80156

Page 266 FRM_SYSGR15 FRM_

DPAR_IS FRM_

SPAR_IS FRM_PSB_FS_IS

0x80157

Page 266 FRM_SYSGR16 FRM_

DPAR_IM FRM_

SPAR_IM FRM_PSB_FS_IM

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

320 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Signaling Global Registers—R/W

0x80060

Page 267 FRM_SGR1 FRM_R_

TSAISHG FRM_R_LINKCNT[4:0] FRM_TEST_BIT[2:0] FRM_R_

AFZFBE

0x80061

Page 267 FRM_SGR2 FRM_R_

SCOSEN FRM_R_SCOSDTH[9:0]

0x80062

Page 268 FRM_SGR3 FRM_R_SCOSTTH[15:0]

0x80063

Page 268 FRM_SGR4

(Read Only) FRM_R_COSFIFOS[1:0] FRM_R_COSFIFOL[4:0] FRM_R_COSFIFOTS[4:0] FRM_R_COSFIFOSIG[3:0]

0x80064

Page 268 FRM_SGR5

(Read Only) FRM_R_

COSDTHS

0x80065

Page 269 FRM_SGR6

(COR) 00 00000000000FRM_R_

COSDTHI FRM_R_

COSTTHI FRM_R_

COSOFI

0x80066

Page 269 FRM_SGR7 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_R_

COSDTHM FRM_R_

COSTTHM FRM_R_

COSOFM

0x80160

Page 270 FRM_SGR8 FRM_T_LINKCNT[4:0] FRM_T_

SUBZERO FRM_T_

FAS_NOTFAS FRM_T_

AFZFBE

Frame Formatter Global Register—R/W

0x80170

Page 271 FRM_FFGR1 FRM_

TXSOOF FRM_

PTRN_EN FRM_

PTRN_INV FRM_PTRN_

FRMT FRM_PTRN_LNK[4:0] FRM_PTRN_SEL[3:0]

Facility Data Link Global Registers—R/W

0x80090

Page 272 FRM_FDLGR1

0x801A1

Page 272 FRM_FDLGR2

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

321Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive Signaling Link Registers—R/W

See Table 382 for values of L and R in the register address field.

Reference Table 384 on Page 273 for the following addresses.

0x8LR00 FRM_RSLR0 FRM_RPSR0[6:0]

0x8LR01 FRM_RSLR1 FRM_RPSR1[6:0]

0x8LR02 FRM_RSLR2 FRM_RPSR2[6:0]

0x8LR03 FRM_RSLR3 FRM_RPSR3[6:0]

0x8LR04 FRM_RSLR4 FRM_RPSR4[6:0]

0x8LR05 FRM_RSLR5 FRM_RPSR5[6:0]

0x8LR06 FRM_RSLR6 FRM_RPSR6[6:0]

0x8LR07 FRM_RSLR7 FRM_RPSR7[6:0]

0x8LR08 FRM_RSLR8 FRM_RPSR8[6:0]

0x8LR09 FRM_RSLR9 FRM_RPSR9[6:0]

0x8LR0A FRM_RSLR10 FRM_RPSR10[6:0]

0x8LR0B FRM_RSLR11 FRM_RPSR11[6:0]

0x8LR0C FRM_RSLR12 FRM_RPSR12[6:0]

0x8LR0D FRM_RSLR13 FRM_RPSR13[6:0]

0x8LR0E FRM_RSLR14 FRM_RPSR14[6:0]

0x8LR0F FRM_RSLR15 FRM_RPSR15[6:0]

0x8LR10 FRM_RSLR16 FRM_RPSR16[6:0]

0x8LR11 FRM_RSLR17 FRM_RPSR17[6:0]

0x8LR12 FRM_RSLR18 FRM_RPSR18[6:0]

0x8LR13 FRM_RSLR19 FRM_RPSR19[6:0]

0x8LR14 FRM_RSLR20 FRM_RPSR20[6:0]

0x8LR15 FRM_RSLR21 FRM_RPSR21[6:0]

0x8LR16 FRM_RSLR22 FRM_RPSR22[6:0]

0x8LR17 FRM_RSLR23 FRM_RPSR23[6:0]

0x8LR18 FRM_RSLR24 FRM_RPSR24[6:0]

0x8LR19 FRM_RSLR25 FRM_RPSR25[6:0]

0x8LR1A FRM_RSLR26 FRM_RPSR26[6:0]

0x8LR1B FRM_RSLR27 FRM_RPSR27[6:0]

0x8LR1C FRM_RSLR28 FRM_RPSR28[6:0]

0x8LR1D FRM_RSLR29 FRM_RPSR29[6:0]

0x8LR1E FRM_RSLR30 FRM_RPSR30[6:0]

0x8LR1F FRM_RSLR31 FRM_RPSR31[6:0]

0x8LR20

Page 274 FRM_RSLR32 FRM_R_HGAIS[3:0] FRM_R_HGA[3:0] FRM_R_HGRDI[3:0] FRM_R_

TS16A FRM_R_

TS16AIS

0x8LR21

Page 274 FRM_RSLR33 FRM_R_

FZCON FRM_R_

SIGI FRM_R_

RXSTOMP FRM_R_

SIGDEB FRM_R_

HGEN FRM_R_

MSIGFZ FRM_R_

FGSRC FRM_R_SI

GSRC[1:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

322 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Transmit Signaling Link Registers—R/W

See Table 387 for values of L and T in the register address field.

Reference Table 389 on Page 276 for the following addresses.

0x8LT00 FRM_TSLR0 FRM_TPSR0[6:0]

0x8LT01 FRM_TSLR1 FRM_TPSR1[6:0]

0x8LT02 FRM_TSLR2 FRM_TPSR2[6:0]

0x8LT03 FRM_TSLR3 FRM_TPSR3[6:0]

0x8LT04 FRM_TSLR4 FRM_TPSR4[6:0]

0x8LT05 FRM_TSLR5 FRM_TPSR5[6:0]

0x8LT06 FRM_TSLR6 FRM_TPSR6[6:0]

0x8LT07 FRM_TSLR7 FRM_TPSR7[6:0]

0x8LT08 FRM_TSLR8 FRM_TPSR8[6:0]

0x8LT09 FRM_TSLR9 FRM_TPSR9[6:0]

0x8LT0A FRM_TSLR10 FRM_TPSR10[6:0]

0x8LT0B FRM_TSLR11 FRM_TPSR11[6:0]

0x8LT0C FRM_TSLR12 FRM_TPSR12[6:0]

0x8LT0D FRM_TSLR13 FRM_TPSR13[6:0]

0x8LT0E FRM_TSLR14 FRM_TPSR14[6:0]

0x8LT0F FRM_TSLR15 FRM_TPSR15[6:0]

0x8LT10 FRM_TSLR16 FRM_TPSR16[6:0]

0x8LT11 FRM_TSLR17 FRM_TPSR17[6:0]

0x8LT12 FRM_TSLR18 FRM_TPSR18[6:0]

0x8LT13 FRM_TSLR19 FRM_TPSR19[6:0]

0x8LT14 FRM_TSLR20 FRM_TPSR20[6:0]

0x8LT15 FRM_TSLR21 FRM_TPSR21[6:0]

0x8LT16 FRM_TSLR22 FRM_TPSR22[6:0]

0x8LT17 FRM_TSLR23 FRM_TPSR23[6:0]

0x8LT18 FRM_TSLR24 FRM_TPSR24[6:0]

0x8LT19 FRM_TSLR25 FRM_TPSR25[6:0]

0x8LT1A FRM_TSLR26 FRM_TPSR26[6:0]

0x8LT1B FRM_TSLR27 FRM_TPSR27[6:0]

0x8LT1C FRM_TSLR28 FRM_TPSR28[6:0]

0x8LT1D FRM_TSLR29 FRM_TPSR29[6:0]

0x8LT1E FRM_TSLR30 FRM_TPSR30[6:0]

0x8LT1F FRM_TSLR31 FRM_TPSR31[6:0]

0x8LT21

Page 277 FRM_TSLR32 FRM_T_

ATS16RFA FRM_T_

ASPLB FRM_T_MSP FRM_T_

ZCSM FRM_T_

VTSIGE FRM_T_

SIGI FRM_T_

TXSTOMP FRM_T_

HGEN FRM_T_

MSIGFZ FRM_T_

FGSRC FRM_T_SIGSRC[1:0]

0x8LT20

Page 277 FRM_TSLR33 FRM_T_

TS16A FRM_T_

TS16AIS

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

323Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Performance Monitor Link Registers—COR

See Table 393 for values of L and P in the register address field.

0x8LP80

Page 279 FRM_PMLR1

(R/W) FRM_PM_IM4[15:0]

0x8LP81

Page 279 FRM_PMLR2

(R/W) FRM_PM_IM5[15:0]

0x8LP82

Page 280 FRM_PMLR3

(R/W) FRM_MHGALIGN[3:0] FRM_

MSEFS FRM_MFE FRM_PM_IM6[4:0]

0x8LP83

Page 280 FRM_PMLR4 FRM_SLIPO FRM_SLIPU FRM_OOF FRM_LSFA FRM_OAIS FRM_AIS FRM_ORAI FRM_RAI FRM_

SA600X1E FRM_

SA6001XE FRM_

CRCTX FRM_

LTS0MFA FRM_

TS0MFABE FRM_SES FRM_BES FRM_ES

0x8LP84

Page 287 FRM_PMLR5 FRM_LFV FRM_FBE FRM_CRCE FRM_ECRCE FRM_

REBIT FRM_

CREBIT FRM_LTFA FRM_NFA FRM_

SA7LID FRM_

LLBON FRM_

LLBOFF FRM_

AUXP FRM_LOS FRM_

BOMR

0x8LP85

Page 289 FRM_PMLR6 FRM_

FDL_RAI FRM_FDL_

PLBON FRM_FDL_

PLBOFF FRM_FDL_

LLBON FRM_FDL_

LLBOFF

0x8LP86

Page 289 FRM_PMLR7 FRM_BPV[15:0]

0x8LP87

Page 290 FRM_PMLR8 FRM_FBEC[15:0]

0x8LP88

Page 290 FRM_PMLR9 FRM_CEC[15:0]

0x8LP89

Page 290 FRM_PMLR10 FRM_REC[15:0]

0x8LP8A

Page 290 FRM_PMLR11 FRM_CETE[15:0]

0x8LP8B

Page 290 FRM_PMLR12 FRM_CENT[15:0]

0x8LP8C

Page 291 FRM_PMLR13 FRM_FE_OP FRM_FE_N FRM_FE_M FRM_FE_L FRM_FE_K FRM_FE_I FRM_FE_H FRM_FE_G FRM_FE_F FRM_FE_E FRM_FE_D FRM_FE_C FRM_FE_B FRM_FE_A

0x8LP8D

Page 292 FRM_PMLR14 FRM_FE_Y FRM_FE_X FRM_FE_W FRM_FE_V FRM_FE_U FRM_FE_T FRM_FE_S FRM_FE_R FRM_FE_Q

0x8LP8E

Page 292 FRM_PMLR15 FRM_ESC[15:0]

0x8LP8F

Page 292 FRM_PMLR16 FRM_BESC[15:0]

0x8LP90

Page 292 FRM_PMLR17 FRM_SESC[15:0]

0x8LP91

Page 292 FRM_PMLR18 FRM_RBOM[7:0]

0x8LP92

Page 293 FRM_PMLR19 FRM_HGALIGN[3:0] FRM_SEFS

0x8LP93

Page 293 FRM_PMLR20 FRM_G6 FRM_G5 FRM_G4 FRM_G3 FRM_G2 FRM_G1 FRM_SE FRM_FE FRM_LV FRM_SL FRM_LB FRM_N1 FRM_N0

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

324 Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Receive FDL Link Registers—R/W

See Table 415 for values of L and R in the register address field. For the following five addresses, please reference Table 416 on Page 294.

0x8LRC0 FM_RFDLLR1 FRM_RXS0[15:0]

0x8LRC1 FM_RFDLLR2 FRM_RXS1[15:0]

0x8LRC2 FM_RFDLLR3 FRM_RXS2[15:0]

0x8LRC3 FM_RFDLLR4 FRM_RXS3[15:0]

0x8LRC4 FM_RFDLLR5 FRM_RXS4[15:0]

0x8LRC5

Page 294 FM_RFDLLR6 FRM_RXCRCSM

0x8LRC6

Page 294 FM_RFDLLR7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_RXSA

0x8LRC7

Page 295 FM_RFDLLR8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FRM_RXSR_IS

0x8LRC8

Page 295 FM_RFDLLR9 FRM_MRXSR

Transmit FDL Link Register s—R/W

See Table 422 for values of L and T in the register address field.

For the following five addresses, please reference Table 423 on Page 295.

0x8LTD0 FM_TFDLLR1 FRM_TXS0[15:0]

0x8LTD1 FM_TFDLLR2 FRM_TXS1[15:0]

0x8LTD2 FM_TFDLLR3 FRM_TXS2[15:0]

0x8LTD3 FM_TFDLLR4 FRM_TXS3[15:0]

0x8LTD4 FM_TFDLLR5 FRM_TXS4[15:0]

0x8LTD5

Page 296 FM_TFDLLR6 FRM_

SA8SC FRM_

SA7SC FRM_

SA6SC FRM_

SA5SC FRM_

SA4SC FRM_

TXCRCSM FRM_

ASRC FRM_DS1I

0x8LTD6

Page 297 FM_TFDLLR7 FRM_BOME FRM_TBOM[5:0]

0x8LTD7

Page 297 FM_TFDLLR8

(RO/COW) FRM_

BOMC_IS FRM_TXSE_IS

0x8LTD8

Page 297 FM_TFDLLR9 FRM_

BOMC_IM FRM_TXSE_IM

Syste m Interface Link Registers—R/W

See Table 429 for values of L and P in the register address field.

0x8LPE0

Page 299 FRM_SYSLR1 FRM_BYOFF[6:0] FRM_OFF[2:0] FRM_

HALFOFF FRM_QUAROFF

0x8LPE1

Page 299 FRM_SYSLR2 FRM_

CEPTMAIS FRM_

CEPTAAIS FRM_

MANAIS FRM_

CEPTSTMP

For the following four addresses, please reference Table 432 on Page 299.

0x8LPE2 FRM_SYSLR3

0x8LPE3 FRM_SYSLR4

0x8LPE4 FRM_SYSLR5

0x8LPE5 FRM_SYSLR6

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

325Agere Systems Inc.

12 28-Channel Framer Registers (continued)

Table 459. Framer Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Arbi ter L ink Re gisters—R/W; See Table 429 for values of L and T in the register address field.

0x8LPF0

page 300 FRM_ARLR1 FRM_

LNK_ENA FRM_LNK_

TRANSP FRM_LNK_

RESTARTN FRM_LNK_

REFRAME FRM_

ICKEDGE

0x8LPF1

page 301 FRM_ARLR2 FRM_ESF_

CRC_EN FRM_FAST FRM_OPT[1:0] FRM_FBE_

MODE FRM_LF_CRT[2:0] FRM_

AUTO_AIS FRM_RAIL3_DEC[1:0] FRM_MODE[3:0]

0x8LPF2

page 304 FRM_ARLR3 FRM_TP_CK

_SRC_EN FRM_TP_

CK_SRC FRM_TP_

DD_SRC FRM_

SYSFSM

Frame Formatter Link Re gisters—R/W; See Table 429 for values of L and T in the register address field.

0x8LPF4

page 305 FRM_FFLR1 FRM_

ESFRAMD FRM_ZCSMD[2:0] FRM_

OCKEDGE FRM_

AUTOPLB FRM_

AUTOLLB FRM_

AUTOEBIT FRM_

AUTORAI

0x8LPF5

page 306 FRM_FFLR2 FRM_TXLBMD[1:0] FRM_

TXLLBOFF FRM_

TXLLBON FRM_TXIID FRM_

TXAUXP FRM_

TXRAI FRM_

TXAIS

Line Decoder/Encoder Link Registers—R/W; see Table 439 and Table 441 for values of L and T in the register address field.

0x8LTFC

page 308 FRM_LDLR1 FRM_

EXCZERO FRM_RLCLK_

EDGE FRM_LD_MODE[2:0]

0x8LRFD

page 308 FRM_LDLR2 FRM_TLCLK_

EDGE FRM_LE_MODE[2:0]

HDLC Channel Registers—R/W; See Table 444 for mapping of H and P in the register address field.

Transmit HDLC Channel Registers

0x8HP80

page 309 FRM_HCR1 FRM_TTIMESLOT[4:0] FRM_TBIT_IM[7:0]

0x8HP81

page 309 FRM_HCR2 FRM_TFRAME_SEL[1:0] FRM_TLINK[4:0]

0x8HP82

page 310 FRM_HCR3 FRM_THC_

RESET FRM_

TENABL FRM_CFLAGS[1:0] FRM_

PRMEN FRM_

TLOOP FRM_C_R FRM_

HTTHRSEL FRM_IFCS FRM_

HTIDLE FRM_

HTMODE FRM_HXPIDLE[1:0]

0x8HP83

page 311 FRM_HCR4 (RO) 0 0000 00000000FRM_

HTUND FRM_

HTDONE FRM_

HTTHRSH

0x8HP84

page 311 FRM_HCR5 FRM_

MHTUND FRM_

MHTDONE FRM_

MHTTHRSH

0x8HP85

page 309 FRM_HCR6(WO) FRM_HTFUNC[1:0] FRM_HTDATA[7:0]

0x8HP86

page 312 FRM_HCR7 FRM_HTCOUNT[9:0]

Receive HDLC Channel Registers

0x8HP00

page 312 FRM_HCR8 FRM_RTIMESLOT[4:0] FRM_RBIT_IM[7:0]

0x8HP01

page 312 FRM_HCR9 FRM_RFRAME_SEL[1:0] FRM_RLINK[4:0]

0x8HP02

page 313 FRM_HCR10 FRM_RHC_

RESET FRM_

RENABL FRM_

RTHRSEL FRM_RFCS FRM_

HRMODE FRM_

BYTAL FRM_MATCH[7:0]

0x8HP03

page 314 FRM_HCR11 (RO) 0 0000 0000000FRM_

RIDLE FRM_

OVR FRM_EOP FRM_

HRTHRSH

0x8HP04

page 314 FRM_HCR12 FRM_

MIDLE FRM_

MOVR FRM_

MEOP FRM_

MHRTHRSH

0x8HP05

page 315 FRM_HCR13 (RO) 0 0 0 0 0 FRM_HMDA FRM_

HRVALID FRM_

HRTYPE FRM_HR_DATA[7:0]

FRM_HOVR FRM_HEOP FRM_

HCRCERR FRM_HABRT FRM_HIDL FRM_HBIT[2:0]

0x8HP06

page 315 FRM_HCR14

(COR) FRM_HRCOUNT[9:0]

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

326 Agere Systems Inc.

13 Cross Connect (XC) Registers

Table of Con t ents

Contents Page

13 Cross Connect (XC) Registers ........................................................................................................................326

13.1 Cross Connect Register Descriptions ......................................................................................................327

13.2 Cross Connect Register Map...................................................................................................................333

Tables Page

Table 460. XC_ID_R, XC Global Register 1 (RO).................................................................................................327

Table 461. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W) ..................................................327

Table 462. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W) ..................................................327

Table 463. XC_PIND_SRC[1—15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W)............328

Table 464. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W)........................328

Table 465. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W)...................................................328

Table 466. XC_VT_SRC[1—14], XC1 VT Mapper Source Configuration (R/W)...................................................329

Table 467. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configuration (R/W) ..............................329

Table 468. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configuration (R/W) .......................329

Table 469. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W).............329

Table 470. XC_TPM_SRC[1—4], XC1 Test-Pattern Monitor Source Configuration (R/W)....................................330

Table 471. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)..........................330

Table 472. XC2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W)...........................................330

Table 473. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W)...........................................330

Table 474. XC_MISC, XC Global Register 2 (R/W)...............................................................................................330

Table 475. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W)...........................................331

Table 476. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W) ..................................................................332

Table 477. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)...............................332

Table 478. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)...............332

Table 479. Register Address Map .........................................................................................................................333

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

327Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

13.1 Cross Connect Regis ter Descriptions

Table 460. XC_ID_R, XC Global Register 1 (RO)

Table 461. XC_CHI_MODE1_R, XC System Interface Global Register 1 (R/W)

Table 462. XC_CHI_MODE2_R, XC System Interface Global Register 2 (R/W)

Address Bit Name Function Reset

Default

0x50000 15:11 RSVD Reserved. 0x0005

10:8 XC_VERSION[2:0] Version. These bits identify the version number of the XC.

7:0 XC_ID[7:0] XC_ID. XC_ID register returns a fixed value (0x05) when

read.

Address Bit Name Function Reset

Default

0x5000E 15:3 RSVD Reserved. 0x0000

2RSVDReserved. Must write to 0.

1 XC_SYNC_FOR_DATA Sync for Data. This bit should set to 1 if the transmit sys-

tem interface is in use (CHI, PSB, and NSMI). Setting this

bit allows the external I/O pins LINETXSYNC[29—1] to

output transmit system data. Otherwise, set to 0.

0 XC_SI_CHI PSB/CHI. This bit should be set to 1 if the transmit system

interface is in PSB mode; otherwise, 0 in CHI mode.

Address Bit Name Function Reset

Default

0x5000F 15:14 RSVD Reserved. 0x0000

13:0 XC_CHI_MODE[1—7][1:0] CHI Mode. The 28 transmit system links are broken

down into seven groups of four. Each group is con-

trolled by 2 bits, XC_CHI_MODE[1—7][1:0].

XC_CHI_MODE[1—7][1:0] controls the group of links

4i – 3, 4i – 2, 4i – 1, and 4i, where i = 1 to 7. The defini-

tion of CHI_MODE[1—7][1:0] is as follows:

00 = all four links within the group are normal outputs at

2 Mbits/s or 4 Mbits/s.

01 = links 4i – 3 and 4i – 2 are normal outputs; links

4i – 1 and 4i are combined into a single output on 4i;

and output 4i – 1 is used as T1/E1 line output.

10 = links 4i – 1 and 4i are combined into a single output

on 4i; links 4i – 3 and 4i – 2 are combined into a

single output on 4i – 2; and outputs 4i – 1 and

4i – 3 are used as T1/E1 line outputs.

11 = all four links are combined into a single output on 4i;

the other three outputs are used as T1/E1 line

outputs.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

328 Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

DS1/E1 crosspoint connectivity is determined by a set of source identifiers (SOURCE_IDs), one for each channel

leaving the crosspoint switch. A DS1/E1 SOURCE_ID is therefore defined as follows:

The SOURCE_BLOCK is defined as:

The CHANNEL_ID typically ranges from 1 to 28 (29 for external). Values 0, 30, and 31 (and usually 29 as well) are

unused. The above definition is valid for XC_PDATA[1—29], XC_RP_RDATA[1—28], XC_MDS1DATA[1—29]

(Table 465 on page 328), XC_VDATA[1—28] (Table 466 on page 329), XC_SYNC[1—29] (Table 477 on

page 332), and XC_ALCO[1—29] (Table 478 on page 332).

Table 464. XC_FRP_SRC[1—14], XC1 Framer Receive Path Data Source Configuration (R/W)

Table 465. XC_M13_SRC[1—14], XC1 M13 Data Source Configuration (R/W)

Bit 76543210

SOURCE_ID SOURCE_BLOCK[2:0] CHANNEL_ID[4:0]

Index Block Identifier Index Block Identifier

000 TPG (Test-Pattern Generator)/Special 100 VTMPR (VT Mapper)

001 PIN (External I/O) 101 DJA (Jitter Attenuator)

010 FRM TP (Superframer) 110 FRM RP (Framer Line Interface)

011 M13 (M13 MUX) 111 FRM TS (Framer System Interface)

Table 463. XC_PIND_SRC[1—15], XC1 External I/O TXDATA and TXCLK Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x50010—

0x5001D 15:8 XC_PDATA[2, 4, . . . 28][7:0]

(SOURCE_ID) Source Identifier for External I/O Pin LINETX-

DATA and LINETXCLK Connection. External I/O

DS1/E1 data and clock (even channels).

0x1E

(invalid)

0x5001E 15:8 RSVD Reserved.0x00

0x50010—

0x5001E 7:0 XC_PDATA[1, 3, . . . 29][7:0]

(SOURCE_ID) Source Identifier for External I/O Pin LINETX-

DATA and LINETXCLK Connection. External I/O

DS1/E1 data and clock (odd channels).

Note: External I/O has 29 channels.

0x1E

(invalid)

Address Bit Name Function Reset

Default

0x50020—

0x5002D 15:8 XC_RP_RDATA

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for Framer Receive Path Connection.

Framer receive path DS1/E1 input signals RP_RDATA,

RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (even channels).

0xFF

(invalid)

7:0 XC_RP_RDATA

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for Framer Receive Path Connection.

Framer receive path DS1/E1 input signals RP_RDATA,

RP_RCLK, RP_RFS, RP_AIS, and RP_RAI (odd channels).

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50030—

0x5003D 15:8 XC_MDS1DATA

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for M13 MUX Connection. M13 DS1/E1

data and clock inputs (even channels). Also for stuff request

inputs if operating in LOW_CLOCK_OUT mode.

0xFF

(invalid)

7:0 XC_MDS1DATA

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for M13 MUX Connection. M13 DS1/E1

data and clock inputs (odd channels). Also for stuff request

inputs if operating in LOW_CLOCK_OUT mode.

0xFF

(invalid)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

329Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 466. XC_VT_SRC[1—14], XC1 VT Mapper Source Configuration (R/W)

Table 467. XC_DJA_SRC[1—14], XC1 Digital Jitter Attenuator Source Configuration (R/W)

Table 468. XC_FTP_SRC[1—14], XC1 Framer Transmit Path Data Source Configuration (R/W)

Table 469. XC_FRS_SRC[1—14], XC1 Framer Receive System Interface Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x50040

—

0x5004D

15:8 XC_VDATA

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for VT Mapper Connection. VT mapper

DS1/E1 data, clock, sync, and RAI inputs (even channels). 0xFF

(invalid)

7:0 XC_VDATA

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for VT Mapper Connection. VT mapper

DS1/E1 data, clock, sync, and RAI inputs (odd channels). 0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50050

—

0x5005D

15:8 XC_JDATA

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for Jitter Attenuator Connection. DJA

DS1/E1 data, clock, pointer adjustment, and AUTO AIS inputs

(even ch ann els ).

0xFF

(invalid)

7:0 XC_JDATA

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for Jitter Attenuator Connection. DJA

DS1/E1 data, clock, pointer adjustment, and AUTO AIS inputs

(odd channels).

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50060

—

0x5006D

15:8 XC_TP_RDATA

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for Framer Transmit Path Connection.

Framer transmit path DS1/E1 input signals (even channels). 0xFF

(invalid)

7:0 XC_TP_RDATA

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for Framer Transmit Path Connection.

Framer transmit path DS1/E1 input signals (odd channels). 0xFF

(invalid)

Address Bit Name Function Reset

Default

0x50070

—

0x5007D

15:8 XC_RS_D

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for Framer Receive System Interface

Connection. Framer receive system (RS) data input (even

channels).

0x00

(invalid)

7:0 XC_RS_D

[1, 3, . . . 27][7:0]

(SOURCE_ID)

Source Identifier for Framer Receive System Interface

Connection. Framer receive system (RS) data input (odd

channels).

0x00

(invalid)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

330 Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 470. XC_TPM_SRC[1—4], XC1 Test-Pattern Monitor Source Configuration (R/W)

The DS2 crosspoint’s connectivity is determined by a smaller set of source2 identifiers (SOURCE2_IDs), one for

each channel leaving the DS2 crosspoint switch XC2. A DS2 SOURCE2_ID is therefore defined as follows:

The SOURCE2_BLOCK is defined as follows:

The CHANNEL2_ID typically ranges from 1 to 7. For test data (SOURCE2_BLOCK = 0), value 4 represents the

DS2 test pattern. For DS2 signals routed from external pins to the input of M23 MUX or TPM, the CHANNEL2_ID

can range from 1 to 29.

Table 471. XC2_M12_SRC[1—7], XC2 M12 DS2 Clock and Data Source Configuration (R/W)

Table 472. XC2_M23_SRC[1—7], XC2 M23 DS2 Data Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x50080 15:8 RSVD Reserved. 0x00

7:0 XC_TPM_DS1_DATA[7:0]

(SOURCE_ID) Source Identifier for TPM DS1 Data Pattern. Source

identifier for test-pattern monitor (TPM) DS1 test channel

inputs.

0xFF

(invalid)

0x50081 15:8 RSVD Reserved. 0x00

7:0 XC_TPM_DS1_IDLE[7:0]

(SOURCE_ID) Source Identifier for TPM DS1 Idle Pattern. Source

identifier for TPM DS1 idle channel inputs. 0xFF

(invalid)

0x50082 15:8 RSVD Reserved. 0x00

7:0 XC_TPM_E1_DATA[7:0]

(SOURCE_ID) Source Identifier for TPM E1 Data Pattern. Source

identifier for TPM E1 test channel inputs. 0xFF

(invalid)

0x50083 15:0 RSVD Reserved. 0x0000

Bit 7 6 5 43210

SOURCE2_ID 0 SOURCE2_BLOCK[1:0] CHANNEL2_ID[4:0]

Index Block2 Identifier

00 TPG (DS 2 Tes t- Pa tter n Ge nerator)

01 M13:M12 MUX

10 M13:M23 DeMUX

11 External I/O

Address Bit Name Function Reset

Default

0x50090

—

0x50096

15:8 XC2_DS2M12CLK

[1—7][7:0]

(SOURCE_ID)

Source Identifier for High-Speed DS2 Clock Input to M12

Multiplexers Connection. DS2 clock input to M12 multiplex-

ers, see Section 20.5.1 M12 Multiplexers, on page 467.

0x0040

(invalid)

7:0 XC2_M21[1—7][7:0]

(SOURCE_ID) S ource Id ent ifier for Hig h-S pee d DS2 Data and Clock

Connection. DS2 data and clock inputs to M12 demultiplex-

ers, see Section 22.7.3 on page 567.

Address Bit Name Function Reset

Default

0x500A0

—

0x500A6

15:8 RSVD Reserved. 0x0040

(invalid)

7:0 XC2_MDS2M23DATA

[1—7][7:0]

(SOURCE2_ID)

Source Identifier for M23 Input DS2 Signals Connec-

tion. When SOURCE2_BLOCK = 11, CHANNEL2_ID

can range from 1 to 29.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

331Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 473. XC2_TPM_SRC, XC2 Test-Pattern Monitor Source Configuration (R/W)

Table 474. XC_MISC, XC Global Register 2 (R/W)

Table 475. XC3_TPM_SRC, XC3 Test-Pattern Monitor Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x500A8 15:8 RSVD Reserved. 0x0000

(invalid)

7:0 XC2_TSOURCE_ID[7:0] XC2 TPM So urce Connectio n. Sour ce2 i dent ifie r for T PM

DS2 test data. When external I/O is selected

(SOURCE2_BLOCK = 1 1), CHANNEL2_ID can range from

1 to 29.

Address Bit Name Function Reset

Default

0x500C0 15:6 RSVD Reserved. 0

5XC_DS2ALCOENM23 DS2 Clock Out. Setting this bit to 1 enables DS2 low

clock-out mode from M23. Setting this bit to 0 selects the nor-

mal DS2 clock and data in put mod e.

4XC_DS1ALCOENM12/M 13 DS1 Clo ck Out . Setting this bit to 1 enables DS1

low clock-out mode from M12/M13. Setting this bit to 0 selects

the normal DS1 clock and data input mode.

3 XC_RPOAC_EN Receive POAC Enable. Setting this bit to 1 enables RPOAC

channel output and 0 to disable. 0

2XC_TPOAC_ENTransmit POAC Enable. Setting this bit to 1 enables TPOAC

channel output and 0 to disable. 0

1 XC_RSTS1_TUG3 Receive POAC Channel Select. Selector for TMUX (logic 1)/

SPEMPR (logic 0) receive POAC channel. 0

0 XC_TSTS1_TUG3 Transmit POAC Channel Select. Selector for TMUX

(logic 1)/SPEMPR (logic 0) transmit POAC channel. 0

Address Bit Name Function Reset

Default

0x500D3 15:8 RSVD Reserved.0x0000

7RSVDReserved. Must write to 0.

6:5 XC3_TSOURCE_ID[1:0] TPG/TPM DS3 Sourc e. Source identifier for TPM DS3 test

data.

00 = TPM receives DS3 from external pins.

01 = TPG and TPM are connected to M13 through NSMI

interface.

10 = TPM receives DS3 from SPE.

11 = Reserved.

4:0 RSVD Reserved. Must write to 0.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

332 Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 476. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)

Table 477. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)

Table 478. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)

Address Bit Name Function Reset

Default

0x500D4 15:2 RSVD Reserved. 0x0000

1:0 XC3_SOURCE_ID[1:0] DS3 Level Connections. This register defines the connec-

tivity at DS3 level among external I/O, M13, and SPE.

00 = M13 inputs/outputs DS3 through external pins.

01 = M13 and SPE pass data to each other.

10 = SPE inputs/outputs DS3 through external pins and M13

is used as a monitor for the transmit DS3.

11 = SPE inputs/outputs DS3 through external pins and M13

is used as a monitor for the receive DS3.

Address Bit Name Function Reset

Default

0x500E0

—

0x500ED

15:8 XC_SYNC

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for External I/O Pin LINETXSYNC. (Even

channels.) In the LIU mode, these registers must be pro-

grammed the same as XC_PIND_SRC[1—15] (Table 463 on

page 328) registers; in the system interface mode (CHI, PSB,

and framer only), these registers will be programmed sepa-

rately to ensure the system data output properly.

0xFF

(invalid)

0x500EE 15:8 RSVD Reserved. 0x00

0x500E0

—

0x500EE

7:0 XC_SYNC

[1, 3, . . . 29][7:0]

(SOURCE_ID)

Source Identifier for External I/O Pin LINETXSYNC. (Odd

channels.)

Note: External I/O has 29 channels.

0xFF

(invalid)

Address Bit Name Function Reset

Default

0x500F0

—

0x500FD

15:8 XC_ALCO

[2, 4, . . . 28][7:0]

(SOURCE_ID)

Source Identifier for External I/O Pin LINERXCLK when

Operating in Low Clock Output Mode. (Either DS1/E1 or

DS2.) For DS1/E1 channels, the programmed value of these

registers should be consistent with those of registers

XC_PIND_SRC[1—15] (Table 463 on page 328) to ensure

that clock and data for the same channel will always be routed

together; while for DS2 channels, the value of these registers

should match thos e of regis ters XC2 _M2 3_S RC[1 — 7]

(Table 472 on page 330) (even channels).

0xFF

(invalid)

0x500FE 15:8 RSVD Reserved. 0x00

0x500F0

—

0x500FE

7:0 XC_ALCO

[1, 3, . . . 29][7:0]

(SOURCE_ID)

Source Identifier for External I/O Pin LINERXCLK when

Operating in Low Clock Output Mode. (Either DS1/E1 or

DS2.) For DS1/E1 channels, the programmed value of these

registers should be consistent with those of registers

XC_PIND_SRC[1—15] (Table 463 on page 328) to ensure

that clock and data for the same channel will always be routed

together; while for DS2 channels, the value of these registers

should match thos e of regist ers XC2 _M2 3_S RC[1 —7] (o dd

channels).

Note: External I/O has 29 channels.

0xFF

(invalid)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

333Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

13.2 Cross Connect Regis ter Map

Table 479. Register Address Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Cross Connect Glob a l—RO

0x50000

Page 327 XC_ID_R XC_VERSION[2:0] XC_ID[7:0]

0x50001

—

0x5000D

RSVD

Framer System Interface Control—R/W

0x5000E

Page 327 XC_CHI_MODE1_R 0 XC_SYNC_FOR_DATA XC_SI_CHI

0x5000F

Page 327 XC_CHI_MODE2_R XC_CHI_MODE7[1:0] XC_CHI_MODE6[1:0] XC_CHI_MODE5[1:0] XC_CHI_MODE4[1:0] XC_CHI_MODE3[1:0] XC_CHI_MODE2[1:0] XC_CHI_MODE1[1:0]

DS1/ E1 Cr os spoint Config ur a tio n— R /W

External I/O (LINETXDATA[1—29] and LINETXCLK[1—29] Pins) Data and Clock Output Selects

0x50010

—

0x5001D

Page 328

XC_PIND_SRC[1—14] XC_PDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_PDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5001E

Page 328 XC_PIND_SRC15 XC_PDA TA29[7:0] Source_ID

0x5001F RSVD

DS1/ E1 Cr os spoint Config ur a tio n— R /W

Framer Receive Path Selects

0x50020

—

0x5002D

Page 328

XC_FRP_SRC[1—14] XC_RP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_RP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5002E RSVD

0x5002F RSVD

DS1/ E1 Cr os spoint Config ur a tio n— R /W

M13 MUX Selects

0x50030

—

0x5003D

Page 328

XC_M13_SRC[1—14] XC_MDS1DATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_MDS1DATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5003E RSVD

0x5003F RSVD

DS1/ E1 Cr os spoint Config ur a tio n— R /W

VT Mapper Selects

0x50040

—

0x5004D

Page 329

XC_VT_SRC[1—14] XC_VDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_VDATA[1, 3, 5, 7, 9, 11, 13, 15, 1 7, 19, 21, 23, 25, 27][7:0] Source_ID

0x5004E RSVD

0x5004F RSVD

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

334 Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 479. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 B it 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DS1/E1 Crosspoint Configuration—R/W

Jitter Attenuation Selects

0x50050

—

0x5005D

Page 329

XC_DJA_SRC[1—14] XC_JDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_JDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5005E RSVD

0x5005F RSVD

DS1/E1 Crosspoint Configuration—R/W

Framer Transmit Path Selects

0x50060

—

0x5006D

Page 329

XC_FTP_SRC[1—14] XC_TP_RDATA[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_TP_RDATA[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5006E

—

0x5006F

RSVD

DS1/E1 Crosspoint Configuration—R/W

Framer RS (System Interface) Selects

0x50070

—

0x5007D

Page 329

XC_FRS_SRC[1—14] XC_RS_D[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0] Source_ID XC_RS_D[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x5007E

—

0x5007F

RSVD

Test-Pattern Monitor (TPM) Inputs

0x50080

Page 330 XC_TPM_SRC1 XC_TPM_DS1_DATA[7:0] Source_ID

0x50081

Page 330 XC_TPM_SRC2 XC_TPM_DS1_IDLE [7:0] Source_ID

0x50082

Page 330 XC_TPM_SRC3 XC_TPM_E1_DATA[7:0] Source_ID

0x50083

Page 330 XC_TPM_SRC4

0x50084

—

0x5008F

RSVD

DS2 Crosspoint Configuration—R/W

M12 MUX/DeMUX Selects

0x50090

—

0x50096

Page 330

XC2_M12_SRC[1—7] XC2_DS2M12CLK[1—7][7:0] Source_ID XC2_M21_[1—7][7:0] Source_ID

0x50097

—

0x5009F

RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

335Agere Systems Inc.

13 Cross Connect (XC) Registers (continued)

Table 479. Register Address Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DS2 Crosspoint Configuration—R/W

M23 MUX Selects

0x500A0

—

0x500A6

Page 330

XC2_M23_SRC[1—7] XC2_MDS2M23DATA[1—7][7:0] Source2_ID

0x500A7 RSVD

DS2 Crosspoint Configuration—R/W

Test-Pattern Monitor (TPM) Inputs

0x500A8

Page 331 XC2_TPM_SRC XC2_TSOURCE_ID[7:0] Data Source2_ID

0x500A9

—

0x500BF

RSVD

Miscellaneous

0x500C0

Page 331 XC_MISC XC_DS2 ALCOEN XC_DS1 ALCOEN XC_RPOAC_EN XC_TPOAC_EN XC_RSTS1_TUG3 XC_TSTS1_ TUG3

0x500C1

—

0x500D2

RSVD

DS3 Crosspoint Configuration—R/W

0x500D3

Page 331 XC3_TPM_SRC 0 XC3_TSOURCE_ID[1:0] 0 0 0 0 0

0x500D4

Page 332 XC3_MDS3_SRC XC3_SOURCE_ID[1:0]

0x500D5

—

0x500DF

RSVD

DS1/ E1 Cr os spoint Config ur a tio n— R /W

External I/O (LINETXSYNC Pins) Sync Selects

0x500E0

—

0x500ED

Page 332

XC_PINS_SRC[1—14] XC_SYNC[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0]

SOURCE ID XC_SYNC[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21 , 23, 25, 27][7:0] SOURCE_ID

0x500EE

Page 332 XC_PINS_SRC15 XC_SYNC29[7 :0] SOURCE_ID

0x500EF RSVD

DS1/ E1 Cr os spoint Config ur a tio n— R /W

Low Clock Out Selects

0x500F0

—

0x500FD

Page 332

XC_ALCO_SRC[1—14] XC_ALCO[2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28][7:0]

Source_ID XC_ALCO[1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27][7:0] Source_ID

0x500FE

Page 332 XC_ALCO_SRC15 XC_ALCO29 Source_ID

0x500FF RSVD

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

336 Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers

Table of Con t ents

Contents Page

14 Digital Jitter Attenuation Controller Registers ..................................................................................................336

14.1 Digital Jitter Attenuation Controller Register Descriptions........................................................................337

14.2 Digital Jitter Attenuation Controller Register Map ....................................................................................340

Tables Page

Table 480. DJA_VERSION, DJA Version and Identification (RO).........................................................................337

Table 481. DJA_EVENT1—DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta (COR/COW) ..............337

Table 482. DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W)...........................337

Table 483. DJA_STATE1—DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators (R/W)...............338

Table 484. DJA_E1GAINH—DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W) .........................................338

Table 485. DJA_DS1GAINH—DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W)..................................338

Table 486. DJA_E1SCALE, E1 Scale Factor (R/W)..............................................................................................338

Table 487. DJA_DS1SCALE, DS1 Scale Factor (R/W).........................................................................................338

Table 488. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W) .................................................339

Table 489. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W) ..........................................339

Table 490. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W) .........................................................339

Table 491. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W) .................339

Table 492. DJA Register Map................................................................................................................................340

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

337Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

14.1 Digital Jitter Attenuation Controller Regis ter Descriptions

This section gives a brief description of each register bit and its functionality. The abbreviations after each register

indicate if the register is read only (RO), clear-on-read/clear-on-write (COR/COW), or read/write (R/W).

Table 480. DJA_VERSION, DJA Version and Identification (RO)

Table 481. DJA_EVENT1—DJA_EVENT2, Loss of Clock and Overflow/Underflow Delta

(COR/COW)

Table 482. DJA_MASK1—DJA_MASK2, Loss of Clock and Overflow/Underflow Masks (R/W)

Address Bit Name Function Re set

Default

0x70000 15:11 RSVD Reserved. 00000

10:8 DJA_VERSION[2:0] Block Version Number. Block version register

will change each time the device is changed. 0x0

7:0 DJA_ID[7:0] Block ID Number. 0x7

Address Bit Name Function Reset

Default

0x70003 15 DJA_G_DS1_DLT G_PIN_DS1XCLK Loss of Clock Delta. 0

14 DJA_DS1_DLT PIN_DS1XCLK Loss of Clock Delta. 0

13 DJA_G_E1_DLT G_PIN_E1XCLK Loss of Clock Delta. 0

12 DJA_E1_DLT PIN_E1XCLK Loss of Clock Delta. 0

0x70003

0x70004 11:0

15:0 DJA_ESOVFL[28:17]

DJA_ESOVFL[16:1] Elastic Store Overflow/Underflow Event. 0x0

Address Bit Name Function Reset

Default

0x70006 15 DJA_G_DS1_MSK G_PIN_DS1XCLK Loss of Clock Indication

Mask. 1

14 DJA_DS1_MSK PIN_DS1XCLK Loss of Clock Indication

Mask. 1

13 DJA_G_E1_MSK G_PIN_E1XCLK Loss of Clock Indication

Mask. 1

12 DJA_E1_MSK PIN_E1XCLK Loss of Clock Indication Mask. 1

0x70006

0x70007 11:0

15:0 DJA_ESOVFL_MSK[28:17]

DJA_ESOVFL_MSK[16:1] Elastic Store Over/Underflow Indication

Mask. 0xFFFFFFF

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

338 Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

Table 483. DJA_STATE1—DJA_STATE2, Loss of Clock and VT Pointer Adjustment Indicators (R/W)

Table 484. DJA_E1GAINH—DJA_E1GAINL, E1 Accumulator Gain Threshold (R/W)

Table 485. DJA_DS1GAINH—DJA_DS1GAINL, DS1 Accumulator Gain Threshold (R/W)

Table 486. DJA_E1SCALE, E1 Scale Factor (R/W)

Table 487. DJA_DS1SCALE, DS1 Scale Factor (R/W)

Address Bit Name Function Reset

Default

0x70009 15 DJA_G_DS1LOC G_PIN_DS1XCLK Loss of Clock Indication. (1 = LOC.) 0

14 DJA_DS1LOC PIN_DS1XCLK Loss of Clock Indication. (1 = LOC.) 0

13 DJA_G_E1LOC G_PIN_E1XCLK Loss of Clock Indication. (1 = LOC.) 0

12 DJA_E1LOC PIN_E1XCLK Loss of Clock Indication. (1 = LOC.) 0

11:0 RSVD Reserved.

0x7000A 15:0 DJA_PTRADJS[16:1] VT Pointer Adjustment Indicator State. When this state

is high, the associated PLL has experienced a VT pointer

adjustment within the last PTRADJCNT register specified

time interval.

Address Bit Name Function Reset

Default

0x7000B

0x7000C

15:11

10:0

15:0

RSVD

DJA_E1GAIN[26:16]

DJA_E1GAIN[15:0]

Reserved.

E1 Gain. Accumulator gain threshold at which a

clock adjustment takes place for E1 signals (see

Table 634 on page 580).

0x7FFFFFF

Address Bit Name Function Reset

Default

0x7000D

0x7000E

15:11

10:0

15:0

RSVD

DJA_DS1GAINTHR[26:16]

DJA_DS1GAINTHR[15:0]

Reserved.

DS1 Gain. Accumulator gain threshold at which

a clock adjustment takes place for DS1 signals

(see Table 634).

0x7FFFFFF

Address Bit Name Function Reset

Default

0x7000F 15:0 DJA_E1SCALE[15:0] E1 Scale. Scale factor that controls clock adjust-

ment rates for E1 signals (see Table 634). 0xFFFF

Address Bit Name Function Reset

Default

0x70010 15:2 DJA_DS1SCALE[15:2] DS1 Scale. Scale factor that controls clock

adjustment rates for DS1 signals (see

Table 634).

1 DJA_BLUECLKSWITCH DJA Blue Clock Switch Fix. If this bit is a 1,

then the fix is disabled. If this bit is a 0, then the

DJA does not respond to AIS and the clock does

not switch from the DJA generated.

—

0 DJA_DS1SCALE[0] DS1 Scale. —

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

339Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

Table 488. DJA_E1PTRH—DJA_E1PTRL, E1 First-Order Loop Counter (R/W)

Table 489. DJA_DS1PTRH—DJA_DS1PTRL, DS1 First-Order Loop Counter (R/W)

Table 490. DJA_DS1SELH—DJA_DS1SELL, DS1 E1 Mode Select (R/W)

Table 491. DJA_CLK_CTL1—DJA_CLK_CTL4, Reference Clock Rate and Edge Transitions (R/W)

Address Bit Name Function Reset

Default

0x70011

0x70012

15:5

4:0

15:0

RSVD

DJA_E1PTRADJCNT[20:16]

DJA_E1PTRADJCNT[15:0]

Reserved.

E1 First-Order Loop Count. Count value that

determines the amount of time spent as a first-

order loop following a VT pointer adjustment in

E1 mode (see Table 635 on page 580).

0x177000

Address Bit Name Function Reset

Default

0x70013

0x70014

15:5

4:0

15:0

RSVD

DJA_DS1PTRADJCNT[20:16]

DJA_DS1PTRADJCNT[15:0]

Reserved.

DS1 First-Order Loop Count. Count value that

determines the amount of time spent as a first-

order loop following a VT pointer adjustment in

DS1 mode (see Table 635).

0x11AB70

Address Bit Name Function Reset

Default

0x70015

0x70016

15:12

11:0

15:0

RSVD

DJA_DS1SEL[28:17]

DJA_DS1SEL[16:1]

Reserved.

DS1 E1 Mode Select. Control signal that deter-

mines the operating mode of each jitter attenua-

tion block (1 = DS1, 0 = E1).

0xFFFFFFF

Address B it Name Func tion Reset

Default

0x70017 15:14 RSVD Reserved.

13:12 DJA_BLUECLKD1[1:0] Reference Clock Rate. Control signal that indi-

cates that the input XCLK runs at 32 X (11) or

16 X (01) the line rate or exactly the line rate

(00).

111

0x70017

0x70018 11:0

15:0 DJA_TXEDGE[28:17]

DJA_TXEDGE[16:1] Tr ansmit Edge Select. Control signal that deter-

mines on which edge of the clock the output

DS1/ E1 data transit ions (1 = rising edge).

0xFFFFFFF

0x70019

0x7001A

15:12

11:0

15:0

RSVD

DJA_RXEDGE[28:17]

DJA_RXEDGE[16:1]

Reserved.

Receive Edge Select. Control signal that deter-

mines on which edge of the clock the input

DS1/E1 data is retimed (1 = rising edge).

0xFFFFFFF

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

340 Agere Systems Inc.

14 Digital Jitter Attenuation Controller Registers (continued)

14.2 Digital Jitter Attenuation Controller Register Map

The register bank architecture of the microprocessor interface is shown in Table 86 on page 75.

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Table 492. DJA Register Map

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

ID and Interrupt Registers (RO)

0x70000

Page 337 DJA_VERSION DJA_VERSION[2:0] DJA_ID[7:0]

0x70001

0x70002 RSVD

Delta and Event Parameters (COR/COW)

0x70003

Page 337 DJA_EVENT1 DJA_G_DS1_

DLT DJA_DS1_DLT DJA_G_E1_

DLT DJA_E1_DLT DJA_ESOVFL[28:17]

0x70004

Page 337 DJA_EVENT2 DJA_ESOVFL[16:1]

0x70005 RSVD Interrupt Mask Parameters for INT Pins (R/W)

0x70006

Page 337 DJA_MASK1 DJA_G_DS1_

MSK DJA_DS1_MSK DJA_G_E1_

MSK DJA_E1_MSK DJA_ESOVFL[28:17]

0x70007

Page 337 DJA_MASK2 DJA_ESOVFL[16:1]

0x70008 RSVD State and Value Parameters (RO)

0x70009

Page 338 DJA_STATE1 DJA_G_DS1L

OC DJA_DS1LOC DJA_G_

E1LOC DJA_E1LOC

0x7000A

Page 338 DJA_STATE2 DJA_PTRADJS[16:1]

Control Parameters for PLL Bandwidth and Mode (R/W)

0x7000B

Page 338 DJA_E1GAINH DJA_E1GAIN[26:16]

0x7000C

Page 338 DJA_E1GAINL DJA_E1GAIN[15:0]

0x7000D

Page 338 DJA_DS1GAINH DJA_DS1GAINTHR[26:16]

0x7000E

Page 338 DJA_DS1GAINH DJA_DS1GAINTHR[15:0]

0x7000F

Page 338 DJA_E1SCALE DJA_E1SCALE[15:0]

0x70010

Page 338 DJA_DS1SCALE DJA_DS1SCALE[15:0] DJA_BLUECLK

SWITCH DJA_DS1SCALE[0]

0x70011

Page 339 DJA_E1PTRH DJA_E1PTRADJCNT[20:16]

0x70012

Page 339 DJA_E1PTRL DJA_E1PTRADJCNT[15:0]

0x70013

Page 339 DJA_DS1PTRH DJA_DS1PTRADJCNT[20:16]

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

14 Digital Jitter Attenuation Controller Register Map (continued)

341Agere Systems Inc.

0x70014

Page 339 DJA_DS1PTRL DJA_DS1PTRADJCNT[15:0]

0x70015

Page 339 DJA_DS1SELH DJA_DS1SEL[28:17]

0x70016

Page 339 DJA_DS1SELL DJA_DS1SEL[16:1]

0x70017

Page 339 DJA_TXEDGEH DJA_BLUECLKD1[1:0] DJA_TXEDGE[28:17]

0x70018

Page 339 DJA_TXEDGEL DJA_TXEDGE[16:1]

0x70019

Page 339 DJA_RXEDGEH DJA_RXEDGE[28:17]

0x7001A

Page 339 DJA_RXEDGEL DJA_RXEDGE[16:1]

0x7001B

—

0x700FF

RSVD

Table 492. DJA Register Map (continued)

Addr Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

342 Agere Systems Inc.

15 Test-P attern Genera tion/Detection Registers

Table of Con t ents

Contents Page

15 Test-Pattern Generation/Detection Registers .................................................................................................342

15.1 Test-Pattern Generation/Detection Register Descriptions .......................................................................343

15.2 Test-Pattern Generation/Detection Register Map....................................................................................356

Tables Page

Table 493. TPG_ID, Status Register (RO).............................................................................................................343

Table 494. TPG_ISRC_OOFD, Delta Register (RO).............................................................................................343

Table 495. TPG_ISRC_OOSD, Delta Register (RO).............................................................................................343

Table 496. TPG_ISRC_BERE, Event Register (RO).............................................................................................344

Table 497. TPG_ISRC_FERE, Event Register (RO).............................................................................................344

Table 498. TPG_ISRC_BPVE, Event Register (RO).............................................................................................344

Table 499. TPG_ISRC_AISD, Delta Register (RO)...............................................................................................345

Table 500. TPG_ISRC_CRCE, Event Register (RO) ............................................................................................345

Table 501. TPG_IMSK_OOFD, Register (R/W).....................................................................................................345

Table 502. TPG_IMSK_OOSD, Register (R/W) ....................................................................................................345

Table 503. TPG_IMSK_BERE, Register (R/W).....................................................................................................346

Table 504. TPG_IMSK_FERE, Register (R/W) .....................................................................................................346

Table 505. TPG_IMSK_BPV, Register (R/W)........................................................................................................346

Table 506. TPG_IMSK_AISD, Register (R/W).......................................................................................................347

Table 507. TPG_IMSK_CRCE, Register (R/W).....................................................................................................347

Table 508. TPG_VAL_OOF, Register (RO) ...........................................................................................................347

Table 509. TPG_VAL_OOS, Register (RO)...........................................................................................................348

Table 510. TPG_VAL_AIS, Register (RO).............................................................................................................348

Table 511. TPG_VAL_FER, Register (RO)............................................................................................................348

Table 512. TPG_VAL_CRCE, Register (RO).........................................................................................................349

Table 513. TPG_BER_INSRT, Register (R/W)......................................................................................................349

Table 514. TPG_FER_INSRT, Register (R/W) ......................................................................................................349

Table 515. TPG_CRCE_INSRT, Register (R/W) ...................................................................................................349

Table 516. TPG_ESFDL_TX, Register (R/W)........................................................................................................350

Table 517. TPG_E1SA_TX12, Register (R/W)......................................................................................................350

Table 518. TPG_E1SA_TX34, Register (R/W)......................................................................................................350

Table 519. TPG_CONFIG0, Register (R/W)..........................................................................................................351

Table 520. TPG_CONFIG2, Register (R/W)..........................................................................................................352

Table 521. TPG_CONFIG4, Register (R/W)..........................................................................................................353

Table 522. TPG_CONFIG5, Register (R/W)..........................................................................................................354

Table 523. TPG_USER, Register (R/W)................................................................................................................354

Table 524. TPM_USER, Register (R/W)................................................................................................................354

Table 525. TPG_BERCNT0, Register (RO)...........................................................................................................354

Table 526. TPG_BERCNT2, Register (RO)...........................................................................................................355

Table 527. TPG_BERCNT4, Register (RO)...........................................................................................................355

Table 528. TPG_BERCNT5, Register (RO)...........................................................................................................355

Table 529. TPM_ESFDL_RX, Register (RO).........................................................................................................355

Table 530. TPM_E1SA_RX12, Register (RO).......................................................................................................355

Table 531. TPM_E1SA_RX34, Register (RO).......................................................................................................355

Table 532. Test-Pattern Generation/Detection Register Map................................................................................356

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

343Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

15.1 Test-Pattern Generation/Detection Register Descriptions

The following tables describe the functions of all bits in the microprocessor register map. For each address, the

Table 493. TPG_ID, Status Register (RO)

Table 494. TPG_ISRC_OOFD, Delta Register (RO)

Table 495. TPG_ISRC_OOSD, Delta Register (RO)

Address Bit Name Function Reset

Default

0x60000 15 TPG_READY This bit signifies that TPG reset/initialization is complete. 1

14:11 RSVD Reserved. 0x0

10:8 TPG_VERSION[2:0] These bits identify the version number of the TPG. 0x0

7:0 TPG_ID[7:0] TPG_ID returns a fixed value (0x06) when read. 0x06

Address Bit Name Function Reset

Default

0x60004 15:3 RSVD Reserved. 0x0000

2 TPM_OOF2D This bit is set when the TPM monitor E1 test signal out of

frame detector changes state (transitions). 0

1RSVDReserved. 0

0 TPM_OOF0D This bit is set when the TPM monitor DS1 test signal out of

frame detector changes state (transitions). 0

Address Bit Name Function Reset

Default

0x60005 15:6 RSVD Reserved. 0x000

5 TPM_OOS5D This bit is set when the TPM monitor DS3 test signal out-of-

sync detector changes state (transitions). 0

4 TPM_OOS4D This bit is set when the TPM monitor DS3 test signal out-of-

sync detector changes state (transitions). 0

3RSVDReserved. 0

2 TPM_OOS2D This bit is set when the TPM monitor E1 test signal out of sync

detector changes state (transitions). 0

1RSVDReserved. 0

0 TPM_OOS0D This bit is set when the TPM monitor DS1 test signal out of

sync detector changes state (transitions). 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

344 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 496. TPG_ISRC_BERE, Event Register (RO)

Table 497. TPG_ISRC_FERE, Event Register (RO)

Table 498. TPG_ISRC_BPVE, Event Register (RO)

Address Bit Name Function Reset

Default

0x60006 15:6 RSVD Reserved. 0x000

5 TPM_BERE5 This bit is set when the TPM monitor determines that the incom-

ing DS3 test signal has a single bit error. 0

4 TPM_BERE4 This bit is set when the TPM monitor determines that the incom-

ing DS2 test signal has a single bit error. 0

3RSVDReserved. 0

2 TPM_BERE2 This bit is set when the TPM monitor determines that the incom-

ing E1 test signal has a single bit error. 0

1RSVDReserved. 0

0 TPM_BERE0 This bit is set when the TPM monitor determines that the incom-

ing DS1 test signal has a single bit error. 0

Address Bit Name Function Reset

Default

0x60007 15:3 RSVD Reserved. 0x000

2 TPM_FERE2 This bit is set when the TPM monitor determines that the incom-

ing E1 test signal has a framing error. 0

1RSVDReserved. 0

0 TPM_FERE0 This bit is set when the TPM monitor determines that the incom-

ing DS1 test signal has a framing error. 0

Address Bit Name Function Reset

Default

0x60008 15:3 RSVD Reserved. 0x0000

2 TPM_BPVE2 This bit is set when the TPM monitor determines that the incom-

ing E1 test signal has a bipolar violation error. 0

1RSVDReserved. 0

0 TPM_BPVE0 This bit is set when the TPM monitor determines that the incom-

ing DS1 test signal has a bipolar violation error. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

345Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 499. TPG_ISRC_AISD, Delta Register (RO)

Table 500. TPG_ISRC_CRCE, Event Register (RO)

Tab le 501. TPG_IM SK_ OOF D, Regist er (R/W)

Table 502. TPG_IMSK_OOSD, Register (R/W)

Address Bit Name Function Reset

Default

0x60009 15:6 RSVD Reserved. 0x000

5 TPM_AIS5D This bit is set when the TPM monitor DS3 test signal AIS detector

changes state (transitions). 0

4 TPM_AIS4D This bit is set when the TPM monitor DS2 test signal AIS detector

changes state (transitions). 0

3RSVDReserved. 0

2 TPM_AIS2D This bit is set when the TPM monitor E1 test signal AIS detector

changes state (transitions). 0

1RSVDReserved. 0

0 TPM_AIS0D This bit is set when the TPM monitor DS1 test signal AIS detector

changes state (transitions). 0

Address Bit Name Function Reset

Default

0x6000A 15:3 RSVD Reserved. 0x000

2 TPM_CRCE2 This bit is set when the TPM monitors E1 CRC errors. 0

1RSVDReserved. 0

0 TPM_CRCE0 This bit is set when the TPM monitors DS1 CRC errors. 0

Address Bit Name Function Reset

Default

0x60010 15:3 RSVD Reserved. 0x000

2 TPM_OOF2DM This mask bit is set to suppress an interrupt when the TPM moni-

tors E1 test signal out of frame indicator changes. 1

1RSVDReserved. 0

0 TPM_OOF0DM This mask bit is set to suppress an interrupt when the TPM moni-

tors DS1 test signal out of frame indicator changes. 1

Address Bit Name Function Reset

Default

0x60011 15:6 RSVD Reserved. 0x000

5 TPM_OOS5DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS3 test signal out of sync indicator changes. 1

4 TPM_OOS4DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS2 test signal out of sync indicator changes. 1

3RSVDReserved. 0

2 TPM_OOS2DM This mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test signal out of sync indicator changes. 1

1RSVDReserved. 0

0 TPM_OOS0DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test signal out of sync indicator changes. 1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

346 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 503. TPG_IMSK_BERE, Register (R/W)

Table 504. TPG_IMSK_FERE, Register (R/W)

Table 505. TPG_IMSK_BPV, Register (R/W)

Address Bit Name Function Reset

Default

0x60012 15:6 RSVD Reserved. 0x000

5 TPM_BERE5M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS3 test signal has a bit error. 1

4 TPM_BERE4M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS2 test signal has a bit error. 1

3RSVDReserved. 0

2 TPM_BERE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming E1 test signal has a bit error. 1

1RSVDReserved. 0

0 TPM_BERE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the incoming DS1 test signal has a bit error. 1

Address Bit Name Function Reset

Default

0x60013 15:3 RSVD Reserved. 0x0000

2 TPM_FERE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the E1 test signal has a framing error. 1

1RSVDReserved. 0

0 TPM_FERE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS1 test signal has a framing error. 1

Address Bit Name Function Reset

Default

0x60014 15:3 RSVD Reserved. 0x0000

2 TPM_BPV2M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the E1 test signal ha s a bipolar violation error. 1

1RSVDReserved. 0

0 TPM_BPV0M This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS1 test signal has a bipolar violation

error.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

347Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 506. TPG_IMSK_AISD, Register (R/W)

Table 507. TPG_IMSK_CRCE, Register (R/W)

Table 508. TPG_VAL_OOF, Register (RO)

Address Bit Name Function Reset

Default

0x60015 15:6 RSVD Reserved. 0x000

5 TPM_AIS5DM This mask bit is set to suppress an interrupt when the TPM moni-

tor determines that the DS3 test signal AIS indicator changes. 1

4 TPM_AIS4DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS2 test signal AIS indicator changes. 1

3RSVDReserved. 0

2 TPM_AIS2DM This mask bit is set to suppress an interrupt when the TPM moni-

tor E1 test signal AIS indicator changes. 1

1RSVDReserved. 0

0 TPM_AIS0DM This mask bit is set to suppress an interrupt when the TPM moni-

tor DS1 test signal AIS indicator changes. 1

Address Bit Name Function Reset

Default

0x60016 15:3 RSVD Reserved. 0x0000

2 TPM_CRCE2M This mask bit is set to suppress an interrupt when the TPM moni-

tor detects an E1 test signal CRC-4 error. 1

1RSVDReserved. 0

0 TPM_CRCE0M This mask bit is set to suppress an interrupt when the TPM moni-

tor detects a DS1 test signal CRC-6 error. 1

Address Bit Name Function Reset

Default

0x60020 15:3 RSVD Reserved. 0x0000

2 TPM_OOF2 This status bit is set whenever the TPM E1 test monitor has

encountered an out of frame condition. 1

1RSVDReserved. 0

0 TPM_OOF0 This status bit is set whenever the TPM DS1 test monitor has

encountered an out of frame condition. 1

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

348 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 509. TPG_VAL_OOS, Register (RO)

Table 510. TPG_VAL_AIS, Register (RO)

Table 511. TPG_VAL_FER, Register (RO)

Address Bit Name Function Reset

Default

0x60021 15:6 RSVD Reserved. 0x000

5 TPM_OOS5 This status bit is set whenever the TPM DS3 test monitor has

encountered an out of sync condition. 1

4 TPM_OOS4 This status bit is set whenever the TPM DS2 test monitor has

encountered an out of sync condition. 1

3RSVDReserved. 0

2 TPM_OOS2 This status bit is set whenever the TPM E1 test monitor has

encountered an out of sync condition. 1

1RSVDReserved. 0

0 TPM_OOS0 This status bit is set whenever the TPM DS1 test monitor has

encountered an out of sync condition. 1

Address Bit Name Function Reset

Default

0x60022 15:6 RSVD Reserved. 0x000

5 TPM_AIS5 This status bit is set whenever the TPM DS3 test monitor has

encountered an AIS condition. 0

4 TPM_AIS4 This status bit is set whenever the TPM DS2 test monitor has

encountered an AIS condition. 0

3RSVDReserved. 0

2 TPM_AIS2 This status bit is set whenever the TPM E1 test monitor has

encountered an AIS condition. 0

1RSVDReserved. 0

0 TPM_AIS0 This status bit is set whenever the TPM DS1 test monitor has

encountered an AIS condition. 0

Address Bit Name Function Reset

Default

0x60023 15:3 RSVD Reserved. 0x0000

2 TPM_FER2 This status bit is set whenever the TPM E1 test monitor has

encountered an FER condition. 0

1RSVDReserved. 0

0 TPM_FER0 This status bit is set whenever the TPM DS1 test monitor has

encountered an FER condition. 0

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

349Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 512. TPG_VAL_CRCE, Register (RO)

Table 513. TPG_BER_INSRT, Register (R/W)

Table 514. TPG_FER_INSRT, Register (R/W)

Table 515. TPG_CRCE_INSRT, Register (R/W)

Address Bit Name Function Reset

Default

0x60024 15:3 RSVD Reserved. 0x0000

2 TPG_CRCEINS2 This bit is set when the user desires to inject a single CRC error

into the E1 test signal (via 0 to 1 transition). 0

1RSVDReserved. 0

0 TPG_CRCEINS0 This bit is set when the user desires to inject a single CRC error

Into the DS1 test signal (via 0 to 1 transition). 0

Address Bit Name Function Reset

Default

0x60028 15 TPG_BER_EN This bit, when set, allows automatic bit error insertion by the

microprocessor. 0

14:6 RSVD Reserved. 0x000

5 TPG_BERINS5 This bit is set when the user desires to inject a single bit error into

the DS3 test signal via S MPR_BER_INSRT (Table 75 on

page 68).

4 TPG_BERINS4 This bit is set when the user desires to inject a single bit error into

the DS2 test signal via SMPR_BER_INSRT. 0

3RSVDReserved. 0

2 TPG_BERINS2 This bit is set when the user desires to inject a single bit error into

the E1 test signal via SMPR_BER_INSRT. 0

1RSVDReserved. 0

0 TPG_BERINS0 This bit is set when the user desires to inject a single bit error into

the DS1 test signal via SMPR_BER_INSRT. 0

Address Bit Name Function Reset

Default

0x60029 15:3 RSVD Reserved. 0x0000

2 TPG_FERINS2 This bit injects a single framing error into the E1 test signal (via 0

to 1 transition). 0

1RSVDReserved. 0

0 TPG_FERINS0 This bit injects a single framing error into the DS1 test signal (via

0 to 1 transition). 0

Address Bit Name Function Reset

Default

0x6002A 15:3 RSVD Reserved. 0x0000

2 TPG_CRC4EINS2 This bit is set when the user desires to inject a single

CRC-4 error into the E1 test signal (via 0 to 1 transition). 0

1 RSVD Reserved. 0

0 TPG_CRC6EINS0 This bit is set when the user desires to inject a single

CRC-6 error into the DS1 test signal (via 0 to 1 transition). 0

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

350 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 516. TPG_ESFDL_TX, Register (R/W)

Table 517. TPG_E1SA_TX12, Register (R/W)

Table 518. TPG_E1SA_TX34, Register (R/W)

Address Bit Name Function Reset

Default

0x6002C 15:0 TPG_ESFDL[15:0] Data-Link Field to Be Sent with Each DS1 Idle Frame. 0x7E7E

Address Bit Name Function Reset

Default

0x6002E 15:13 RSVD Reserved. 0x0

12:8 TPG_E1SA2[4:0] Sa (spare bits [8:4]) to Be Sent with E1 Idle Frame. 0x00

7:5 RSVD Reserved. 0x0

4:0 TPG_E1SA1[4:0] Sa (spare bits [8:4]) to Be Sent with E1 Idle Frame. 0x00

Address Bit Name Function Reset

Default

0x6002F 15:13 RSVD Reserved. 0x0

12:8 TPG_E1SA4[4:0] Sa (spare bits [8:4]) to Be Sent with E1 Test Frame. 0x00

7:5 RSVD Reserved. 0x0

4:0 TPG_E1SA3[4:0] Sa (spare bits [8:4]) to Be Sent with E1 Test Frame. 0x00

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

351Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 519. TPG _CONF IG0, Reg iste r (R/W)

Address Bit Name Function Reset

Default

0x60030 15:13 TPM_SEQ0[2:0] These bits select the test pattern to be monitored by the

TPG on the DS1 test input. 000

12 TPM_TPINV0 This bit, if set, inverts the received data for DS1 test sig-

nals. 0

11 TPG_TPINV0 This bit, if set, inverts the transmitted data for DS1 test

signals. 0

10 TPM_EDGE0 This bit, if set, selects the rising edge of XC_TCLK[0] for

use as the retiming clock edge, or else selects the falling

edge.

9 TPG_EDGE0 This bit, if set, selects the rising edge of TPG_CLK[0] for

use as the transmit clock edge, or else selects the falling

edge.

8 TPG_TPM_ESF_0 This bit selects extended superframe mode for DS1 test

signals. 0

7:6 TPG_TPM_CODE0[1:0] Do not use line coding/decoding when 00.

Use HDB3 coding/decoding when 01.

Use B8ZS coding/decoding when 10.

Use AMI coding/decoding when 11.

This code is common to the generator and monitor sides.

5 TPM_FRAME0 This bit is set to select a framed DS1 test pattern in the

monitor. 0

4 TPG_FINV0 If this bit is set, the frame bit in the twelfth frame of each

superframe is inverted in the DS1 test pattern. 0

3 TPG_FRAME0 This bit is set to select a framed DS1 test pattern in the

generator. 0

2:0 TPG_SEQ0[2:0] These bits select the test pattern to be generated and

transmitted by the TPG on the DS1 test output.

000 = PRBS15

001 = PRBS20

010 = QRSS

011 = PRBS23

100 = alternating 01

101 = all ones

110 = unused

111 = user defined

000

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

352 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Tabl e 520. TPG_CO NFIG2, Reg ister (R/W)

Address Bit Name Function Reset

Default

0x60032 15:13 TPM_SEQ2[2:0] These bits select the test pattern to be monitored by the

tpg on the E1 test input. 000

12 TPM_TPINV2 This bit, if set, inverts the received data for E1 test sig-

nals. 0

11 TPG_TPINV2 This bit, if set, inverts the transmitted data for E1 test sig-

nals. 0

10 TPM_EDGE2 This bit, if set, selects the rising edge of XC_TCLK[2] for

use as the retiming clock edge, or else selects falling

edge.

9 TPG_EDGE2 This bit, if set, selects the rising edge of TPG_CLK[2] for

use as the transmit clock edge, or else selects falling

edge.

8 TPG_TPM_CRC4_EN2 This bit, if set, enables CRC-4 insertion if E1 framing is

selected.

This bit is common to the generator and monitor sides.

7:6 TPG_TPM_CODE2[1:0] Do not use line coding/decoding when 00.

Use HDB3 coding/decoding when 01.

Use B8ZS coding/decoding when 10.

Use AMI coding/decoding when 11.

This code is common to the generator and monitor sides.

5 TPM_FRAME2 This bit is set to select a framed E1 test pattern. 0

4 TPG_FINV2 If this bit is set, the frame alignment sequence (normally

0011011) is transmitted with the last bit inverted

(0011010).

3 TPG_FRAME2 This bit is set to select a framed E1 test pattern. 0

2:0 TPG_SEQ2[2:0] These bits select the test pattern to be generated and

transmitted by the TPG on the E1 test output

(TPG_DATA[2]).

000 = PRBS15.

001 = PRBS20.

010 = QRSS.

011 = PRBS23.

100 = alternating 01.

101 = all ones.

110 = unused.

111 = user defined.

000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

353Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 521. TPG _CONF IG4, Reg iste r (R/W)

Address Bit Name Function Reset

Default

0x6 003 4 15:13 TPM_ SEQ 4[ 2 : 0] These bi ts sel ec t th e te st pat t er n t o be mo n it o re d by th e TPG on

the DS2 test input. 000

12 TPM_TPINV4 This bit, if set, inverts the received data for DS2 test signals. 0

11 TPG_TPINV4 This bit, if set, inverts the transmitted data for DS2 test signals. 0

10 TPM_EDGE4 This bit, if set, selects the rising edge of XC_TCLK[4] for use as

the retiming clock edge, or else selects falling edge. 1

9 TPG_EDGE4 This bit, if set, selects the rising edge of TPG_CLK[4] for use as

the transmit clock edge, or else selects falling edge. 1

8:3 RSVD Reserved. —

2:0 TPG_SEQ4[2:0] These bits select the test pattern to be generated and transmit-

ted by the TPG on the DS2 output (TPG_DATA[4]).

000 = PRBS1 5.

001 = PRBS2 0.

010 = QRSS.

011 = PRBS23.

100 = alternating 01.

101 = all ones.

110 = unused.

111 = user defined.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

354 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Tabl e 522. TPG_CO NFIG5, Reg ister (R/W)

Table 523. TPG_USER, Register (R/W)

Table 524. TPM_USER, Register (R/W)

Table 525. TPG_BERCNT0, Register (RO)

Address Bit Name Function Reset

Default

0x60035 15:13 TPM_SEQ5[2:0] These bits select the test pattern to be monitored by the TPG on

the DS3 test input. 000

12 TPM_TPINV5 This bit, if set, inverts the received data for DS3 test signals. 0

11 TPG_TPINV5 This bit, if set, inverts the transmitted data for DS3 test signals. 0

10 TPM_EDGE5 This bit, if set, selects the rising edge of XC_TCLK[5] for use as

the retiming clock edge, or else selects falling edge. 1

9 TPG_EDGE5 This bit, if set, selects the rising edge of TPG_CLK[5] for use as

the transmit clock edge, or else selects falling edge. 1

8:3 RSVD Reserved. —

2:0 TPG_SEQ5[2:0] These bits select the test pattern to be generated and transmitted

by the TPG on the DS3 output (TPG_DATA[5]).

000 = PRBS1 5.

001 = PRBS2 0.

010 = QRSS.

011 = PRBS23.

100 = alternating 01.

101 = all ones.

110 = unused.

111 = user defined.

Address Bit Name Function Reset

Default

0x60036 15:0 TPG_USER[15:0] User-Programmed Test Pattern Generator Da ta. 0xDEAD

Address Bit Name Function Reset

Default

0x60037 15:0 TPM_USER[15:0] User-Programmed Test Pattern Monitor Data. 0xBEEF

Address Bit Name Function Reset

Default

0x60040 15:0 TPM_CNT0[15:0] This field holds the current counter value for DS1 test pattern bit

errors as detected by the TPM. 0x0000

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

355Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 526. TPG_BERCNT2, Register (RO)

Table 527. TPG_BERCNT4, Register (RO)

Table 528. TPG_BERCNT5, Register (RO)

Table 529. TPM_ESFDL_RX, Register (RO)

Table 530. TPM_E1SA_RX12, Register (RO)

Table 531. TPM_E1SA_RX34, Register (RO)

Address Bit Name Function Reset

Default

0x60042 15:0 TPM_CNT2[15:0] This field holds the current counter value for E1 test pattern bit

errors as detected by the TPM. 0x0000

Address Bit Name Function Reset

Default

0x60044 15:0 TPM_CNT4[15:0] This field holds the current counter value for DS2 test pattern bit

errors as detected by the TPM. 0x0000

Address Bit Name Function Reset

Default

0x60045 15:0 TPM_CNT5[15:0] This field holds the current counter value for DS3 test pattern bit

errors as detected by the TPM. 0x0000

Address Bit Name Function Reset

Default

0x6004C 15:0 TPM_ESFDL[15:0] Data-Link Field Received from Last DS1 Idle Frame. 0x0000

Address Bit Name Function Reset

Default

0x6004E 15:13 RSVD Reserved. 0x0

12:8 TPM_E1SA2[4:0] Sa (spare bits [4:8]) Received from E1 Frame. 0x00

7:5 RSVD Reserved. 0x0

4:0 TPM_E1SA1[4:0] Sa (spare bits [4:8]) Received from E1 Frame. 0x00

Address Bit Name Function Reset

Default

0x6004F 15:13 RSVD Reserved. 0x0

12:8 TPM_E1SA4[4:0] Sa (spare bits [4:8]) Received from E1 Frame. 0x00

7:5 RSVD Reserved. 0x0

4:0 TPM_E1SA3[4:0] Sa (spare bits [4:8]) Received from E1 Frame. 0x00

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

356 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

15.2 Test-Pattern Generation /De tection Reg ister M ap

Table 532. Test-Pattern Generation/Detection Register Map

Note: The reset default of all reserved bits is 0. Shading denotes reserved bits.

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Block-Level Status—RO

0x60000

Page 343 TPG_ID TPG_READY TPG_VERSION[2:0] TPG_ID[7:0]

0x60001

—

0x60003

RSVD

TPM Interrupt Sources (Deltas and Events)—RO

0x60004

Page 343 TPG_ISRC_OOFD TPM_OOF2D TPM_OOF0D

0x60005

Page 343 TPG_ISRC_OOSD TPM_OOS5D TPM_OOS4D TPM_OOS2D TPM_OOS0D

0x60006

Page 344 TPG_ISRC_BERE TPM_BERE5 TPM_BERE4 TPM_BERE2 TPM_BERE0

0x60007

Page 344 TPG_ISRC_FERE TPM_FERE2 TPM_FERE0

0x60008

Page 344 TPG_ISRC_BPVE TPM_BPEV2 TPM_BPEV0

0x60009

Page 345 TPG_ISRC_AISD TPM_AIS5D TPM_AIS4D TPM_AIS2D TPM_AIS0D

0x6000A

Page 345 TPG_ISRC_CRCE TPM_CRCE2 TPM_CRCE0

0x6000B

—

0x6000F

RSVD

TPM Interrupt Masks—R/W and Edge Controls

0x60010

Page 345 TPG_IMSK_OOFD TPM_OOF2DM TPM_OOF0DM

0x60011

Page 345 TPG_IMSK_OOSD TPM_OOS5DM TPM_OOS4DM TPM_OOS2DM TPM_OOS0DM

0x60012

Page 346 TPG_IMSK_BERE TPM_BERE5M TPM_BERE4M TPM_BERE2M TPM_BERE0M

0x60013

Page 346 TPG_IMSK_FERE TPM_FERE2M TPM_FERE0M

0x60014

Page 346 TPG_IMSK_BPV TPM_BPV2M TPM_BPV0M

0x60015

Page 347 TPG_IMSK_AISD TPM_AIS5DM TPM_AIS4DM TPM_AIS2DM TPM_AIS0DM

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

357Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 532. Test-Pattern Generation/Detection Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0x60016

Page 347 TPG_IMSK_CRCE TPM_CRCE2M TPM_CRCE0M

0x60017

—

0x6001F

RSVD

TPM State and Value Parameters—RO

0x60020

Page 347 TPG_VAL_OOF TPM_OOF2 TPM_OOF0

0x60021

Page 348 TPG_VAL_OOS TPM_OOS5 TPM_OOS4 TPM_OOS2 TPM_OOS0

0x60022

Page 348 TPG_VAL_AIS TPM_AIS5 TPM_AIS4 TPM_AIS2 TPM_AIS0

0x60023

Page 348 TPG_VAL_FER TPM_FER2 TPM_FER0

0x60024

Page 349 TPG_VAL_CRCE TPG_CRCEINS2 TPG_CRCEINS0

0x60025

—

0x60027

RSVD

TPG Error Insert Enables—R/W

(Error Injection Triggered by SMPR_BER_INSRT (Table 75 on Page 68))

0x60028

Page 349 TPG_BER_INSRT TPG_BER_EN TPG_BERINS5 TPG_BERINS4 TPG_BERINS2 TPG_BERINS0

TPG Error Insert Triggers (rising edge)—R/W

0x60029

Page 349 TPG_FER_INSRT TPG_FERINS2 TPG_FERINS0

0x6002A

Page 349 TPG_CRCE_INSRT TPG_CRC4EINS2 TPG_CRC6EINS0

0x6002B RSVD

TPG (Transmit) ESF Data Link and E1 SA-Bits Contents—R/W

0x6002C

Page 350 TPG_ESFDL_TX TPG_ESFDL[15:0]

0x6002D RSVD

0x6002E

Page 350 TPG_E1SA_TX12 TPG_E1SA2[4:0]TPG_E1SA1[4:0]

0x6002F

Page 350 TPG_E1SA_TX34 TPG_E1SA4[4:0]TPG_E1SA3[4:0]

TMXF28155 Supermapper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

358 Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 532. Test-Pattern Generation/Detection Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TPG/TPM Configuration—R/W

(Test Channels Only)

0x60030

Page 351 TPG_CONFIG0 TPM_SEQ0[2:0] TPM_TPINV0 TPG_TPINV0 TPM_EDGE0 TPG_EDGE0 TPG_TPM_

ESF_0 TPG_TPM_CODE0[1:0] TPM_

FRAME0 TPG_

FINV0 TPG_

FRAME0 TPG_SEQ0[2:0]

0x60031 RSVD

0x60032

Page 352 TPG_CONFIG2 TPM_SEQ2[2:0] TPM_TPINV2 TPG_TPINV2 TPM_EDGE2 TPG_EDGE2 TPG_TPM_

CRC4_EN2 TPG_TPM_CODE2[1:0] TPM_

FRAME2 TPG_

FINV2 TPG_

FRAME2 TPG_SEQ2[2:0]

0x60033 RSVD

0x60034

Page 353 TPG_CONFIG4 TPM_SEQ4[2:0] TPM_TPINV4 TPG_TPINV4 TPM_EDGE4 TPG_EDGE4 TPG_SEQ4[2:0]

0x60035

Page 354 TPG_CONFIG5 TPM_SEQ5[2:0] TPM_TPINV5 TPG_TPINV5 TPM_EDGE5 TPG_EDGE5 TPG_SEQ5[2:0]

0x60036

Page 354 TPG_USER TPG_USER[15:0]

0x60037

Page 354 TPM_USER TPM_USER[15:0]

0x60038

—

0x6003F

RSVD

TPM Bit Error Counters—RO

(See Also PMRST (Table 3 on Page 17), SMPR_SAT_ROLLOVER and SMPR_COR_COW (Table 77 on Page 70))

0x60040

Page 354 TPG_BERCNT0 TPM_CNT0[15:0]

0x60041 RSVD

0x60042

Page 355 TPG_BERCNT2 TPM_CNT2[15:0]

0x60043 RSVD

0x60044

Page 355 TPG_BERCNT4 TPM_CNT4[15:0]

0x60045

Page 355 TPG_BERCNT5 TPM_CNT5[15:0]

0x60046

—

0x6004B

RSVD

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SDH x28/x21 DS1/E1

359Agere Systems Inc.

15 Test-Pattern Generation/Detection Registers (continued)

Table 532. Test-Pattern Generation/Detection Register Map (continued)

Address Symbol Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

TPM Received DS1-ESF Data Link and E1 Sa-Bits Contents—RO

0x6004C

Page 355 TPM_ESFDL TPM_ESFDL[15:0]

0x6004D RSVD

0x6004E

Page 355 TPM_E1SA_RX12 TPM_E1SA2[4:0] TPM_E1SA1[4:0]

0x6004F

Page 355 TPM_E1SA_RX34 TPM_E1SA4[4:0] TPM_E1SA3[4:0]

0x60050

—

0x600FF

RSVD

360 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

Functional Descriptions

16 Microprocessor Interface Functional Description

Table of Con t ents

Contents Page

16 Microprocessor Interface Functional Description ............................................................................................360

16.1 Introduction...............................................................................................................................................361

16.2 Features...................................................................................................................................................361

16.3 Microprocessor Interface..........................................................................................................................361

16.4 MPU Block Diagram.................................................................................................................................362

16.5 Supermapper Register Address Mapping................................................................................................362

16.6 Performance Monitoring (PM) Counters Operation..................................................................................362

16.7 Supermapper Global Interrupt Status and Control...................................................................................364

16.8 Global Control ..........................................................................................................................................364

Figures Page

Figure 19. Microprocessor Interface......................................................................................................................362

Figure 20. PM Reset Counter................................................................................................................................363

Figure 21. PM Reset Signal Generation................................................................................................................363

Tables Page

Table 533. Supermapper Register Address Mapping............................................................................................362

361Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

16 Microprocessor Interface Functional Description (continued)

16.1 Introducti on

The Supermapper microprocessor interface consists of a 20-bit address and a 16-bit data bus. In addition, this

block contains global control and status registers. These registers include the summary of interrupt status of major

functional blocks and the control to enable them or power them down.

16.2 Features

■20-bit address/16-bit data bus microprocessor interface.

■Synchronous (16 MHz to 60 MHz)/asynchronous microprocessor interface modes.

■Microprocessor data bus parity monitoring.

■Summary of interrupts from major functional blocks/maskable.

■Separate device interrupt outputs for automatic protection switch and the Supermapper global interrupt.

■Global configuration of network performance monitoring counters operation.

■Global software resets.

■Global enabling and powering down of major functional blocks.

■Miscellaneous global configuration and control.

16.3 Microprocessor Interface

This device is equipped with a generic 20-bit address/16-bit data microprocessor interface that allows operation

with most commercially available microprocessors. Device input pin MPMODE (pin AD17) is used to configure this

interface into one of two possible modes (synchronous or asynchronous). In synchronous mode (MPMODE = 1),

the microprocessor interface can operate at speeds from 16 MHz up to 60 MHz. In asynchronous mode

(MPMODE = 0), a 16 MHz to 60 MHz clock is required on the MPCLK (pin AE17) pin for proper operation.

Two parity detectors are provided for the microprocessor data bus, one for the higher-order byte and one for the

lower-order byte. The parity sense is programmed as even or odd with register bit SMPR_PARITY_EVEN_ODD

(Table 77 on page 70). The composite status of both parity detectors is indicated in register bit SMPR_PARITY_IS

(Table 73 on page 66). The interrupt from this status indicator may be masked with register bit SMPR_PARITY_IM

(Table 74 on page 67 ). A bad parity event does not inhibit a data transfer. The microprocessor interface is fully

functional without parity supplied by the host processor.

The interrupt status from each of the major blocks, the automatic protection switch, and the microprocessor data

bus parity are summarized in Table 73 on page 66. Each interrupt is maskable with the complementary bit set in

the interrupt mask register; see Table 74 on page 67.

362 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

16 Microprocessor Interface Functional Description (continued)

16.4 MPU Block Diagram

5-9039(F)r.2

Figure 19. Micr op roce sso r Inte rface

16.5 Supermapper Register Ad dress Mapp ing

Each of the Supermapper’s major functional blocks is selected with an address mapping of the highest-order nib-

ble, device pins ADDR[19:16], and allocated a 16-bit address range, pins ADDR[15:0], as defined in Table 533.

Table 533. Supermapper Register Address Mapping

16.6 Performance Mo ni tori ng (PM ) Cou nters Operation

PM counters are error counters or other statistics counters. In general, two internal registers are needed to imple-

ment a PM counter: a running count register (1), maintained by the core logic, which is incremented by 1 every time

an error (or statistics event) happens. At a defined interval, 1 s for example, the content of the running counter is

transferred to a holding register (2), while the running count register is reset to 0 and starts to count anew. The

count holding register holds the data that the microprocessor actually reads.

ADDR[19:16] Block ID Block Name ADDR

0000 0 TOP [15:0]

0001 1 M13 [15:0]

0010 2 VTMPR [15:0]

0011 3 SPEMPR [15:0]

0100 4 TMUX [15:0]

0101 5 XC [15:0]

0110 6 TPG [15:0]

0111 7 DJA [15:0]

1000 8 FRAMER [15:0]

MPCLK

ADDR[19:0]

CSN

ADSN

DSN

RWN

DATA[15:0]

DTN

MPMODE

INTN

APS_INTN

INTERNAL

ADDRESS

INTERNAL

DATA

INTERNAL

CONTROL

PAR[1:0]

363Agere Systems Inc.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

16 Microprocessor Interface Functional Description (continued)

5-9040(F)r.3

Figure 20. PM Reset Count er

The PM counter control signal controls the transfer and reset of all performance monitoring registers (collecting

events/statistics). The source of this signal is configurable and can come from external pin (PMRST pin T25), an

internal timer , or be controlled by software, depending on the SMPR_PMMODE[1:0] bits (Table 77 on page 70, bits

9:8), described as follows:

SMPR_PMMODE[1:0] = 00, 10: PM counter control is sourced from external pin PMRST.

SMPR_PMMODE[1:0] = 01: PM counter control is sourced from internal 1 s timer. Writing a logic 1 to the

SMPR_PMRESET bit (Table 75 on page 68, bit 8) will reset the timer so that a transition occurs on the internal PM

counter control signal within 10 MPCLK clock cycles. The timer is based on the period of the MPCLK and the pro-

grammed value of the registers in Table 82 on page 73 and Table 83. Once initially reset and synchronized, the

PM counter reset interval is determined by the combined delay of the programmed registers. The device pin,

PMRST, is enabled as an output.

SMPR_PMMODE[1:0] = 11: The PM counter control signal is software controlled. Writing a logic 1 to the

SMPR_PMRESET bit will cause a PM reset within 10 MPCLK cycle times after writing. This pulse will be

100 cycles high and 100 cycles low at the MPCLK frequency. During this 200 cycle time, writing to PM bit will have

no effect. The device pin, PMRST, is enabled as an output.

5-9931(F)

Figure 21. PM Reset Signal Generation

PM COUNT EVENT HOLDING

MPU READABLE MPUCLK

MPU READ HOLDING

(ONE PER BLOCK)

COUNTER

PM COUNT EVENT CLOCK

RESET

PM COUNTER CONTROL

PM COUNTER

BUFFERED

ENABLE

RUNNING

COUNTER

MPUCLK DELAY

1/2 SECOND

COUNTERS

SMPR_PMRESET_HIGH_COUNT

SMPR_PMRESET_LOW_COUNT

SMPR_PMMODE

(REGIST E R SM P R_ GC R bits[9:8])

SMPR_PMRESET

(REGISTER SMPR_GTR bit 8)

FREE RUNNING

(SMPR_PMMODE[1:0] = 01)

SOFTWARE CONTROLLED

(SMPR_PMMODE[1:0] = 11)

EXTERNAL

(SMPR_ PM M O DE [1:0] = 00, 10)

MPUCLK

OUTPUT ENABLED

SMPR_PMMODE[1:0] = 01, 11

OUTPUT DISABLED

SMPR_PMMODE[1:0] = 00, 10

PMRST (TO BLOCKS)

PMRSTO

PMRSTI

MPU BLOCK

364 Agere Systems Inc.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

16 Microprocessor Interface Functional Description (continued)

16.7 Supermapper Global Interrupt Status and Control

The Supermapper provides two hardware interrupt output pins: one global (INTN pin AB24) and one for the

SONET automatic protection switching (APS_INTN pin AC25). Both interrupt pins are active-low and are open-

drain outputs to allow a wired OR with complementary devices.

Interrupt status for major functional blocks are summarized in Table 73 on page 66 and maskable in Table 74.

16.8 Global Control

Several registers in this block provide global control of Supermapper features. The register descriptions are selfex-

planatory, but some highlights follow:

■Global enabling and powering down of major functional blocks is shown in Table 81 on page 73.

■Software resets for major functional blocks are shown in Table 76 on page 68.

■Global reset of the Supermapper is controlled with SMPR_SWRS, bit 8, in Table 75 on page 68.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

365Agere Systems Inc.

17 TMUX Functional Description

Table of Con t en ts

Contents Page

17 TMUX Functional Description ..........................................................................................................................365

17.1 TMUX Introduction ...................................................................................................................................367

17.2 TMUX Features........................................................................................................................................367

17.3 TMUX Receive Path Overview.................................................................................................................368

17.3.1 Receive Line Framer and Transport Overhead Termination ........................................................ 368

17.3.2 Receive Transport Overhead Monitor and RTOAC Drop ............................................................. 368

17.3.3 Receive MSP 1 + 1 Payload Switch ............................................................................................. 369

17.3.4 R eceiv e Pointe r Interpreter ............................. ...... ...... ....... ...... ....... ................... ....... .................... 369

17.3.5 Receive High-Order Path Overhead Termination and RPOAC Drop ........................................... 369

17.3.6 Receive Byte Interleave Demultiplexer ......................................................................................... 369

17.3.7 Receive Telecom Bus ................................................................................................................... 369

17.4 TMUX Transmit Path Overview................................................................................................................370

17.4.1 Transm it Tele co m Bus ................ .................... ...... ...... ....... ...... ....... ................... ....... .................... 370

17.5 Receive Direction (Receive Path from SONET Global/SDH)...................................................................374

17.5.1 Input Clock and Loss-of-Signal Monitoring ................................................................................... 375

17.5.2 High-Speed Loopback Select Logic .............................................................................................. 375

17.5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or STS-1 Framing .......................................... 375

17.5.4 B1 BIP -8 Check ............. .................... ...... ....... ...... ...... ....... ................... ....... ...... ....... .................... 375

17.5.5 J0 Mon itor ... ...... ....... ...... ....... ...... .................... ...... ...... ....... ...... .................... ...... ........................... 376

17.5.6 D escram bler ...... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ........................... 376

17.5.7 F1 Monito r ......... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... ................................. 377

17.5.8 B2 BIP -8 Check ............. .................... ...... ....... ...... ...... ....... ................... ....... ...... ....... .................... 377

17.5.9 Automatic Protection Switch (APS) Monitor .................................................................................. 377

17.5.10 K2 Monitor, AIS-L, and RDI-L Detect .......................................................................................... 377

17.5.11 M1 REI-L Detect ......................................................................................................................... 378

17.5.12 Sync Status Monitor .................................................................................................................... 378

17.5.13 Receive Transport Overhead Access Channel (RTOAC) ........................................................... 378

17.5.14 MSP 1 + 1 Payload Switch ......................................................................................................... 380

17.5.15 Pointer Interpreter ....................................................................................................................... 380

17.5.16 Path Monitoring Functions .......................................................................................................... 383

17.6 Transmit Direction (Transmit Path to SONET/SDH Line).........................................................................392

17.6.1 Transm it Si de Telecom Bus Interface ......................... ....... ...... ....... ...... .................... ...... ....... ....... 392

17.6.2 Transmit Path and Transport Overhead Insertion Diagram .......................................................... 392

17.6.3 PO AC Insert ............. ...... ....... ...... ....... ...... ....... ...... ...... ....... ................... ....... ...... ........................... 394

17.6.4 AIS Path Generation ..................................................................................................................... 395

17.6.5 J1 Insert Control ............. ....... ...... ....... ...... ....... ...... ...... ....... ...... .................... ...... ........................... 395

17.6.6 B3 BIP-8 Calculation and Insert .................................................................................................... 395

17.6.7 C2 Signal Label Byte Insert .......................................................................................................... 395

17.6.8 Pat h RDI (RDI-P) Insert . ....... ................... ....... ...... ...... ....... ...... ....... ...... .................... .................... 396

17.6.9 REI-P: G1(7:4) Insert .................................................................................................................... 397

17.6.10 F2 Byte Insert .............................................................................................................................. 397

17.6.11 H4 Insert Control ......................................................................................................................... 397

17.6.12 F3 Byte Insert .............................................................................................................................. 397

17.6.13 K3 Byte Insert ............................................................................................................................. 397

17.6.14 N1 Byte Insert ............................................................................................................................. 397

17.6.15 MSP 1 + 1 Payload Switch ......................................................................................................... 397

17.6.16 Transmit Transport Overhead Access Channel (TTOAC) .......................................................... 397

17.6.17 Sync Status Byte (S1) Insert ....................................................................................................... 399

17.6.18 REI-L: M1 Insert .......................................................................................................................... 399

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

366 Agere Systems Inc.

17 TMUX Functional Description (continued)

Table of Conten ts (continued)

Contents Page

17.6.19 APS Value and K2 Insert Control Parameters ............................................................................ 400

17.6.20 Criteria for Insert Line RDI .......................................................................................................... 400

17.6.21 Line AIS Generation ................................................................................................................... 400

17.6.22 B2 BIP-8 Calculation and Insert .................................................................................................. 400

17.6.23 F1 Byte Insert ............................................................................................................................. 401

17.6.24 B1 Generate and Error Insert ..................................................................................................... 401

17.6.25 Scrambler ................................................................................................................................... 401

17.6.26 J0 Insert Control ......................................................................................................................... 401

17.6.27 Z0-2, Z0-3 Insert Control ............................................................................................................. 401

17.6.28 A2 Error Insert ............................................................................................................................ 401

Figures Page

Figure 22. TMUX RTOAC Timing Diagram ...........................................................................................................368

Figure 23. TMUX TTOAC and RTOAC Timing Diagram.......................................................................................371

Figure 24. High-Level TMUX Interconnect............................................................................................................371

Figure 25. Detailed Block Diagram of the TMUX...................................................................................................372

Figure 26. Receive Direction Functional Block Diagram .......................................................................................373

Figure 27. Pointer Interpretation State Diagram....................................................................................................380

Figure 28. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals.................................................391

Figure 29. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals................................................392

Figure 30. Transmit Direction POH and TOH Insertion Diagram ..........................................................................393

Tables Page

Table 534. Receive TOAC Modes .........................................................................................................................379

Table 535. Transport Overhead Byte Access—Receive Direction ........................................................................379

Table 536. STS Signal Label Defect Conditions....................................................................................................385

Table 537. STS-1 P-REI Interpretation..................................................................................................................386

Table 538. Signal Degrade (SD) Parameters........................................................................................................388

Table 539. Signal Fail Parameters.........................................................................................................................389

Table 540. Signal Fail or Signal Degrade Recommended Programming Values ..................................................390

Table 541. Path Overhead Byte Access................................................................................................................390

Table 542. Path Overhead Byte Access—Transmit Direction ...............................................................................394

Table 543. TPOAC Control Bits.............................................................................................................................395

Table 544. RDI-P Defects for Enhanced RDI-P Mode...........................................................................................396

Table 545. Transmit TOAC Modes ........................................................................................................................398

Table 546. Transmit Transport Overhead Byte Full Access Mode ........................................................................398

Table 547. TTOAC Control Bits in Full Access Mode............................................................................................399

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

367Agere Systems Inc.

17 TMUX Functional Description (continued)

17.1 TMUX Introduction

The TMUX multiplexer block implements SDH/SONET-compliant, byte-interleave multiplexing/demultiplexing,

overhead insertion and termination, multiplex section protection (MSP) 1 + 1 switch capability, and serializer/dese-

rializer for 155.52 Mbits/s and 51.84 Mbits/s traffic.

As shown in Figure 24 on page 371, the TMUX provides three modes of operation: STS-3 mode, STM-1 mode,

and STS-1 mode. In STS-3 mode, the TMUX implements the functions necessary to multiplex and demultiplex up

to three STS-1 signals to/from a SONET STS-3 signal. In STM-1 (VC-4) mode, the TMUX provides the functionality

to multiplex and demultiplex up to three TUG-3 signals to/from an STM-1 (VC-4) signal. The device can also build/

extract up to three AU-3 signals to/from an STM-1 (VC-3) stream. In STS-1 mode, the TMUX implements the func-

tions necessary to interface a single STS-1 to/from an external serial link.

On the high-speed side or line side, the block can be configured for either a 155.52 Mbits/s (STS-3/STM-1) or

51.84 Mbits/s (STS-1) serial data interface. On the low-speed side or tributary side, the TMUX provides a byte-

wide bus that can communicate with up to three STS-1/TUG-3/AU-3 devices at a 19.44 MHz rate. If single STS-1

mode is employed, th e bus rate will be 6.48 MHz. The TMUX therefore provides complete multiplexing/demulti-

plexing to/from an STS-3/STM-1 signal for up to 84 DS1, 84 JT1, or 63 E1 signals. In STS-1 mode, the TMUX pro-

vides multiplexing/demultiplexing for up to 28 DS1, 28 JT1, or 21 E1 streams. In STS-3/STM-1 mode, the TMUX

from only one device is required. The TMUX in other connected devices may be powered down to reduce con-

sumed power. This architecture allows flexible and modular growth in equipment capacity for both 51.84 Mbits/s

and 155.52 Mbits/s links.

17.2 TMUX Features

■Multiplexes three STS-1 signals into a SONET STS-3 signal.

■Multiplexes three VC-3 signals into an SDH STM-1 (AU-4) signal via a TUG-3 construction.

■Multiplexes three VC-3 signals into an SDH STM-1 (AU-3) signal.

■Demultiplexes three STS-1 signals from a SONET STS-3 signal.

■Demultiplexes three VC-3 signals from an SDH STM-1 (AU-4) signal via a TUG-3 deconstruction.

■Demultiplexes three VC-3 signals from an SDH STM-1 (AU-3) signal.

■Provides STS-1-only mode for receive and transmit directions.

■Provides complete functionality for SDH MSP 1 + 1 protection switching.

■Detects STS-3/STM-1 loss-of-signal (LOS) conditions.

■Detects STS-3/STM-1 out of frame and loss-of-frame (OOF/LOF) conditions.

■Provides an 8-bit parallel bus interface that can accommodate up to three STS-1/AU-3s.

■Provides STS-3/STM-1/STS-1 selectable scrambler/descrambler functions and B1/B2/B3 generation/detection.

■Provides STS-3/STM-1/STS-1 pointer interpretation. Detects AIS-P and LOP.

■Complies with GR-253-CORE, T1.105, G.707, G.783, G.806, G.821, and ETSI 417-1-1.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

368 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.3 TMUX Receive Path Overview

A detailed drawing of the TMUX receive path is provided in the bottom half of Figure 25 on page 372. For the

receive path, the TMUX implements two serial inputs for both the work and protect streams of an MSP 1 + 1 net-

work interface. Synchronous data (SDH/SONET) framers are implemented to frame on the incoming receive data

streams. One or both may be employed depending on system architecture. The incoming traffic is converted from

serial to byte-wide parallel. The transport overhead bytes of the incoming traffic are monitored and dropped via the

receive path TOAC drop interface. A multiplexer implements the receive MSP 1 + 1 payload switch and only one of

the incoming streams is passed to the downstream processing blocks. The pointer interpreter passes pointer infor-

mation to the 1:3 demultiplexer logic, and bus control circuitry provides functions necessary to manage traffic on

the telecom bus drop interface which drops traffic from up to three STS-1/TUG-3 paths on the TMUX receive path.

The path overhead bytes are monitored by the path overhead monitor and are dropped via the receive path POAC

drop inter fac e.

17.3.1 Receive Line Framer and Transport Overhead Termination

Input receive data is received at the TMUX synchronous data framer from the high-speed line interface block. The

framer performs a multitude of functions including frame alignment (STS-3/STM-1 or STS-1), B1 BIP-8 check,

J0 byte monitoring, descrambling, F1 byte monitoring, B2 BIP-8 check, automatic protection switch (APS) and K2

byte monitoring, AIS-L and RDI-L detection, M1 byte REI-L detection, S1 byte sync status monitoring, and receive

transport overhead access channel (RTOAC) drop. The states of the framer as well as all state changes are

reported, and, if not masked, cause an interrupt. The B1 and B2 byte parity check supports bit and block modes.

The TMUX implements internal performance monitor counters. These counters can count up to one second worth

of BIP errors. The counters operate in either a saturation mode, so that the maximum value is retained once

reached, or in a rollover mode. These counters should be optimally read (and cleared) at least once per second.

The J0 monitor supports nonframed, SONET-framed, and SDH-framed 16-byte sequences as well as single

J0 byte monitoring mode. APS monitoring is performed on bytes K1[7:0] and K2[7:3]. The value of each is stored

and changes are reported. Bits [2:0] of the K2 byte are monitored independently. Line AIS (AIS-L/MS-AIS) and

RDI-L/MS-RDI are monitored separately and changes are reported. This AIS-L/MS-AIS and RDI-L/MS-RDI infor-

mation is also sent to the protection device for add/drop multiplex (ADM) applications. The M1 byte monitor oper-

ates either in bit or block mode and allows access to the REI-L/MS-REI errored bit count. The S1 byte can be

monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits 7 to 4). Continuous N-times detection

counters are implemented for these monitoring functions. All automatic receive monitoring functions can be config-

ured to provide an interrupt to the control system, or the device can be operated in a polled mode.

17.3.2 Receive Transport Overhead Monitor and RTOAC Drop

The receive RTOAC provides access to all of the line section overhead bytes. Even or odd parity is calculated over

all bytes. It has a data rate of 5.184 Mbits/s and consists of a clock, data, and an 8 kHz sync pulse. In an alternate

operating mode, the data communication channel bytes D1—D3 or D4—D12 may transmit a serial 192 kbits/s or a

576 kbits/s data stream onto the RTOAC drop channel.

0783(F)

Figure 22. TMUX RTOAC Timing Diagram

rtoac clk

rtoac sync

rtoac data

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

369Agere Systems Inc.

17 TMUX Functional Description (continued)

17.3.3 Receive MSP 1 + 1 Payload Switch

Output from both receive framer blocks provides the input to the MSP 1 + 1 payload switch. This portion of the

TMUX implements a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpreta-

tion. If the protection switch is activated, then the data is selected from the receive protection interface rather than

from the high-speed input path. Only the selected input traffic is provided downstream to the pointer interpreter.

The interface consists of a 155.52 MHz or 51.84 MHz clock, data, and sync pulse.

17.3.4 Receive Pointer Interpreter

The pointer interpreter is implemented via a state machine which implements the pointer interpretation algorithm

described in ETS 300 417-1-1: January 1996-Annex B. The pointer interpreter evaluates the current pointer state

for the normal state, path AIS state, or LOP conditions, as well as pointer increments and decrements. The current

pointer state and any changes in pointer condition are reported to the control system. The number of consecutive

frames for invalid pointer and invalid concatenation indication is fixed at 9.

17.3.5 Receive High-Order Path Overhead Termination and RPOAC Drop

Path overhead (POH) termination is performed in the receive path on either all three STS-1s or on the VC-4 POH

only. The receive POH circuitry includes J1 byte monitoring, B3 byte BIP-8 checking, C2 byte signal label monitor-

ing, REI-P and RDI-P detection, H4 byte multiframe monitoring; F2, F3, and K3 byte APS monitoring, N1 byte tan-

dem connection monitoring (TCM), signal degrade BER and signal fail BER detection; receive path overhead

access channel (RPOAC) drop, and AIS-P/HO-AIS insertion and automatic AIS generation (with individual inhibit).

The J1 monitor provides five modes of operation for a programmable length (1 byte to 64 bytes) of the trace identi-

fier. These five modes are comprised of cyclic checking against the last received sequence, compare against a

programmed sequence, SONET framing mode, SDH framing mode, and consecutive consistent occurrences of a

new pattern. B3 is monitored either in bit or block mode. Provisionable N-times detection counters are imple-

mented for the C2, F2, F3, N1, and K3 bytes. The K3 APS byte and N1 TCM byte can be monitored as an entire

8-bit word or two 4-bit nibbles.

The receive RPOAC provides access to all the path overhead bytes. Even or odd parity is calculated over all bytes.

The RPOAC has a data rate of 9 bytes per 8 kHz frame and consists of clock, data, and an 8 kHz sync pulse.

17.3.6 Receive Byte Interleave Demultiplexer

The byte interleave demultiplexer accepts serial traffic and demultiplexes that information into one (STS-1 mode)

or three (STS-3/STM-1 mode) traffic streams for input via the telecom bus to the VT/VC mapper . The demultiplexer

takes the bytes in the order they are presented and places that traffic onto the telecom bus.

17.3.7 Receive Telecom Bus

The TMUX can communicate with up to three SPE mappers via the telecom bus interface. In typical applications,

since one SPE mapper is included in the Supermapper device, two external SPE mappers reside on the telecom

bus. The bus operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode. In the receive

direction, the Supermapper outputs one parallel clock at 19.44 MHz, three sync signals (SPE, J0J1V1, and V1), an

8-bit data bus, and an odd/even parity bit. The data bus carries either three STS-1/TUG-3 signals, each in their

own time slot, or it carries one STS-1 signal. A 51.84 MHz low-speed clock and sync signal is also output from this

circuit.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

370 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.4 TMUX Tr ans mit Path O verv iew

The TMUX transmit path is depicted in the top half of Figure 25 on page 372. The transmit path of the TMUX imple-

ments the inverse function to the receive path. Transmit input traffic at the telecom bus interface from up to three

STS-1/TUG-3 paths is managed via the transmit path bus control circuitry. Transmit traffic, alarms, or unequipped

indication information is inserted as needed depending on the status and provisioning of the device. The 3:1 multi-

plexer provides byte interleave multiplexing of the incoming traffic and insertion of the path overhead bytes. A serial

path provides input for the transmit protection traffic and the framer and serial-to-parallel converter formats this traf-

fic for input to the transmit MSP 1 + 1 payload switch. The selected output from the transmit MSP 1 + 1 switch is

input to the transport overhead insert block and the parallel-to-serial converter sends a serial stream to the device

output. The TMUX transmit path provides path overhead byte insertion and transport overhead byte insertion via

the respective POAC insert and TOAC insert interfaces.

Local clock and frame generation control circuitry is implemented in the TMUX for controlling the STS-1, STS-3,

and STM-1 termination and generation functions. Internal loopbacks in the TMUX provide near-end line loopback

and far-end line loopback capability.

17.4.1 Transmit Telecom Bus

The transmit side of Supermapper drives a clock and three sync signals (SPE, J0J1V1, and V1) onto the telecom

bus. These signals control when the internal SPE mapper or one of the mate devices talks on the data bus.

Because it is on the receive side, the transmit telecom bus operates at 19.44 MHz for STS-3/STM-1 modes and at

6.48 MHz for STS-1 mode. The TMUX communicates with up to three VT/VC mappers, via an 8-bit data word and

an odd/even parity bit from the telecom bus. The data consists of the STS-1/TUG-3 from up to three mappers,

each in its own time slot, or it carries one single STS-1 signal. A 51.84 MHz low-speed clock and sync are also out-

put.

Transmit High-Order Path Overhead Generation and TPOAC Insert. In the transmit direction, J1 path trace

byte insertion, B3 byte calculation and insertion, C2 signal label byte insertion, REI-P and RDI-P insertion; F2 byte

insertion, H4 multiframe byte insertion, F3 path user byte insertion, K3 byte insertion, N1 byte insertion, and AIS-P

insertion via POAC or software control is supported. The transmit TPOAC allows insertion of all overhead bytes

other than the B3 byte, which is automatically calculated. Even or odd parity is checked over all bytes. Bytes which

are not enabled for insertion are set to an all-ones or all-zeros stuff value. Transport path overhead bytes are

added to the payload stream during multiplexing in the byte interleave multiplexer.

Transmit Byte Interleave Multiplexer. In STS-3/STM-1 mode, the transmit byte interleave multiplexer block multi-

plexes up to three STS-1/TUG3 signals to form a SONET/SDH STS-3/STM-1 structured signal. The STS-3/STM-1

multiplexer function processes the input bytes in the order in which they are presented on the transmit telecom bus

and multiplexes these bytes into a single high-speed stream. Grooming of the VTs/VCs is performed in the SPE

mapper of each of the three devices. High-order path overhead bytes are interleaved with the data traffic during the

byte interleave multiplexing.

Transmit Payload Framer and MSP 1 + 1 Payload Switch. In the transmit direction, the MSP 1 + 1 switch func-

tion incorporates dual MSP 1 + 1 payload switch structures. In operation, the traffic from the transmit byte inter-

leave multiplexer is presented to both MSP 1 + 1 payload switches. The output of the signal from the 3:1 multiplex

is broadcast to both switch paths, and the output of the receive payload framers is also input respectively to one of

the two switch paths. For normal operation, one of the two outputs from the two MSP 1 + 1 blocks is selected. The

path from the receive framer to the MSP switch structures provides a means to perform far-end loopback.

Transmit Transport Overhead Generation and TTOAC Insert. The transmit transport overhead generator per-

forms TTOAC byte insertion, sync status byte (S1) insertion, M0/M1—REI-L insertion, K1 and K2 byte insertion,

AIS-L insertion, B2 byte calculation and insertion, F1 byte insertion, B1 byte generation and error insertion, scram-

bling, J0 byte insertion control, and A2 byte error insertion. All insert control functions that are inhibited will option-

ally insert either an all-zeros or an all-ones word.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

371Agere Systems Inc.

17 TMUX Functional Description (continued)

The transmit TTOAC allows the users to insert the following overhead bytes: E1, F1, D1—D3, D4—D12, S1, and

E2. Even or odd parity is checked over all bytes. Bytes which are not enabled for insertion are set to an all-ones or

all-zeros st u ff value.

The data communication channels D1—D3 or D4—D12 may also be received via the TTOAC interface. In this

mode, the TTOAC channel will comprise a serial 192 kbits/s or a 576 kbits/s data stream.

The insertion (overwrite by TOAC) of programmed S1, F1, J0, Z0-2, and Z0-3 bytes can be enabled via registers.

Automatic insertion of M0/M1 may also be inhibited via registers. A protection switch selects the REI-L value for

insertion to be taken from the protection board rather than from the receive side. The entire APS value or K2[2:0]

can be inserted via writable registers. Automatic RDI insertion is supported with individual inhibit for each contribu-

tor. A protection switch selects the RDI-L value for insertion to be taken from the protection board rather than from

the receive side. B1 and B2 BIP-8 values are calculated and inserted. Both values can be optionally inverted.

0784(F)

Figure 23. TMUX TTOAC and RTOAC Timing Diagram

5-9004(F)

Figure 24. High-Level TMUX Interconnect

ttoac clk

ttoac sync

ttoac data

TMUX

SPE

TELECOM BUS

VT/TU

MAPPER

M13

TUG-2DS3

MAPPER

STS-1/TUG-3

(TIME SLOT #1)

STS-1/TUG-3

(TIME SLOT #2)

STS-1/TUG-3

(TIM E SLOT #3)

STS-3/STM-1

OR STS-1

DEVICE #1

DEVICE #2

DEVICE #3

HIGH-SPEED

SONET/SDH INTERFACE

VT MPR RDI_P, REI_P

VT MPR RDI_L, REI_L

TMUX RDI_L, REI_L

TMUX RDI_P, REI_P

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

372 Agere Systems Inc.

17 TMUX Functional Description (continued)

5-9005(F)r.1

Figure 25. Detailed Block Diagram of the TMUX

PATH RDI

POAC

DROP

1:3

DEMUX

LOGIC

MSP 1 + 1

STS#1

STS#2

STS#3

TOAC

INSERT

TRANSMIT DIRECTION

RECEIVE DIRECTION

STS#3

TLSCLK

PAIS, UEQ

INSERT

BUS

CONTROL

TLSPAR

TLSDATA[7:0]

RLSCLK

BUS

CONTROL

RLSPAR

RLSDATA[7:0]

TTOACCLKO,

POINTER

INTERPRETER

TTOACSYNCO,

TTOACDATI

TLSV1

(19.44 MHz)

RTPOACSYNC,

RTPOACDATA

THSD

RLSJ0J1V1

RLSV1

RLSSPE

TLSJ0J1V1

TLSSPE

TLSSYNC52

TLSCLK52

RLSSYNC52

RLSCLK52

TOH

MONITOR

TOAC

DROP

RTOACCLK,

RTOACSYNC,

RTOACDATA

POAC

INSERT

TPOACCLK,

TPOACSYNC,

TPOACDATA

POH

MONITOR

STM-1

TOH

STS#2

PAIS, UEQ

INSERT

STS#1

PAIS, UEQ

INSERT

FRAMER

PAYLOAD

SWITCH 1

AND S/P

3:1

AND

POH

INSERT

MUX

LOGIC

PATH REI

INSERT

MSP 1 + 1

PAYLOAD

SWIT CH 2

LINE RDI

LINE REI

P/S

VTMPR RDI_L, REI_L

VTMPR RDI_P,

AUTO_AISO[1—3] RHSC

RPSD155

FRAMER,

S/P, AND

RPSC155

TPSC155

RHSD

B2 ERR

INSERT,

MSP 1 + 1

PAYLOAD

SWITCH 3

TPSD155

P/S

L-REI INS

B2 MON,

LOC, OOF,

LOF, B2E

LOC, OOF,

LOF, B2E

L-REI MON

LOCAL CLOCK

GENERATION

THSC THSSYNC

AND FRAME

RPSC155

RPSSYNC155 (FROM RECEIVE SI DE)

TPSMUXSEL2

RPSSYNC155

TIMING SIGNALS TO TX SI D E

RTPOACCLK,

REI_P

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

373Agere Systems Inc.

17 TMUX Functional Description (continued)

The following block diagram describes the receive side transport overhead functions. Data is received from the

high-speed interface at 155 Mbits/s (51.84 Mbits/s for STS-1 mode) and the output is driven onto the low-speed

telecom bus in a parallel format. The TOH receive side functional blocks are shown in Figure 26.

5-9006(F)r.2

Figure 26. Receive Direction Functional Block Diagram

INSERT

MONITOR

BIP N K3

CHECK

RDI-P G1

REI-L

DETECT

APS

MONITOR

B3 K3

DETECT

G1 G1N1C2

POAC

DROP

RECEIVE DATA

REI

COUNTER

AIS-P

BER

ALGORITHM

FRAME DESCR-

AMBLER

BIP-8

MONITOR

LOS

CHECK

MONITOR

BIP N K1/K2

CHECK

AIS-L

RDI-L M1

REI-L SYNC

MONITOR

DETECT

APS

MONITOR

B2 K1

DETECT

K2 M1 S1

STATUS

DETECTOR

J0 F1

TOAC

DROP

LOF

MONITOR

OOF

ALIGN

MONITOR

INPUT

REI

COUNTER

BER

ALGORITHM

MONITOR

H1, H2, H3

INTERPRETER

POINTER

TELECOM BUS

MONITOR

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

374 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.5 Receive Direction (Receive Path from SONET Global/SD H)

All functi ons supp orted by the TM UX in the rece iv e dir ect io n are summarize d here:

■Input clock monitoring and loss-of-signal monitoring

■High-sp eed loo pba ck

■Frame alignment

■Receive si de frame sy nc output

■B1 BIP-8 check

■J0 monitor

■Descrambler

■F1 monitor

■B2 BIP-8 check

■APS (automatic protection switch) monitor

■K2 monitor, AIS-L and RDI- L detect

■M1 REI-L detect

■Sync status monitor

■Receive transport overhead access channel (RTOAC)

■MSP 1 + 1 payload switch

■Pointer int erpreter

■J1 monitor

■B3 BIP-8 check

■Signal label C2 byte monitor

■RDI-P detect

■REI-P detect

■Path user byte F2 monitor

■H4 multiframe indicator

■Path user byte F3 monitor

■K3 byte monitor

■N1 tandem connection byte monitor

■Signal degrade BER algorithm

■Signal fail BER algorithm

■Path overhead access channel (POAC) drop

■AIS-P insertion and AUTO_AISO[1—3] generation

■Receive si de tele co m bus int erf ace

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

375Agere Systems Inc.

17 TMUX Functional Description (continued)

17.5.1 Input Clock and Loss-o f-Signal Monitoring

The TMUX detects and reports the loss of the 155 MHz input clock for the STS-3 mode and the loss of the

51.84 MHz clock for the STS-1 mode with register bits TMUX_RHSILOC—state (Table 101, starting on page 94),

TMUX_RHSILOCD—delta state (Table 101, starting on page 94), and TMUX_RHSILOCM—interrupt mask

(Table 101, starting on page 94). LOC is determined by a stuck high or stuck low for a time greater than 10 µs and

uses the microprocessor clock as its reference.

The TMUX will detect and report a loss-of-signal condition with register bits TMUX_RHSLOS—state (Table 101 on

page 94), TMUX_RHSLOSD—delta state (Table 101, starting on page 94), TMUX_RHSLOSM—interrupt mask

(Table 96 on page 90 ), by monitoring the external input signal pin, LOSEXT (pin AE5), or detecting a continuous

all-zeros/ones pattern for 51.44 ns to 105 µs in 51.44 ns steps before data is descrambled. The detection time is

determined by the value programmed in register bits, TMUX_LOSDETCNT[10:0] (Table 107 on page 99). The

LOS state will clear after reception of two consecutive receive frames with the correct framing pattern spaced 125

µs apart without an incoming LOS all-zeros/ones pattern. This recovery applies to both internal and external LOS

failure cau ses.

17.5.2 High-Speed Loopback Select Logic

The device can be configured to loop back the transmit STS-3/STM-1 (AU-4) TMUX_THS2RHSLB = 1 (Table 103

on page 96) or accept the local STS-3/STM-1 (AU-4) signal TMUX_THS2RHSLB = 0.

17.5.3 Frame Alignment—STS-3/STM-1 (AU-4) Framing or STS-1 Framing

The device will frame on the incoming signal. The state of the framer, out of frame (OOF) (register bit

TMUX_RHSOOF; see Table 101 on page 94) as well as any changes to this state (register bits

TMUX_RHSO OFD —del ta sta te; see Table 101, starting on page 94 and TMUX_RHSOO FM —interrupt mas k; see

Table 96 on page 90) will be reported.

The 32-bit (A1-2, A1-3, A2-1, and A2-2) framing pattern will be used in the frame detection for the

STS-3/STM-1 case and a 16-bit pattern will be used for the STS-1 case. The device will be considered out of frame

until two successive framing patterns separated in time by 125 µs occur without framing byte errors.

The device will be considered in frame until five successi ve fram es, se parat ed in t ime by 125 µs, occur w ith er rore d

framing patterns. If the framer transitions to the out of frame state, the framer will remain synchronized to the last

known frame boundary or the latest detected unerrored framing pattern.

A loss of frame (LOF) (register bit TMUX_RHSLOF; see Table 101 on page 94) state bit as well as any changes to

this state (register bits TMUX_RHSLOFD—delta state; see Table 101, starting on page 94, TMUX_RHSLOFM—

interrupt mask; see Table 96 on page 90) will be reported. These state and mask and delta bits are the same for

both types of input data, STS-3/STM-1 or STS-1.

The device will be considered in the LOF state when an OOF condition persists for 24 consecutiv e frames (3 ms).

The device will transition out of the LOF state after receiving 24 consecutive frames with the correct framing pat-

terns spaced 125 µs apart and the OOF condition is clear.

17.5.4 B1 BIP-8 Check

A BIP-8 even parity will be computed over all the incoming bits of the STS-3/STM-1 frame (STS-1 frame in STS-1

mode), which are scrambled (except for the bits in the A1, A2, and J0/Z0 bytes) and compared to the B1 byte

receiv ed in the next frame.

The total number of B1 BIP-8 bit errors (raw count), or block errors (as determined by register bit

TMUX_BITBLKB1; see Table 105 on page 97), are counted. Upon the assertion of the performance monitor con-

trol signal as configured in the microprocessor interface block, the raw count will be reset to zero and the value

transferred to a 16-bit counter for B1 error counts B1ECNT[15:0] (Table 134 on page 120).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

376 Agere Systems Inc.

17 TMUX Functional Description (continued)

In case of overflow, depending on the value programmed in the microprocessor interface register bit

SMPR_SAT_ROLLO V ER (Table 77 on page 70), the B1 error counter will either roll over or saturate at the maxi-

mum value until cleared.

17.5.5 J0 Monitor

J0 (section trace overhead) monitoring is done via register bits TMUX_J0MONMODE[2:0]; see Table 105 on

page 97. This J0 monitoring has six different monitoring modes, as follows:

■TMUX_J0MONMODE[2:0] = 000: the TMUX latches the value of the J0 byte every frame for a total of

16 bytes into registers TMUX_J0DMON[16—1][7:0]; see Table 142 on page 123. The TMUX compares the

incoming J0 byte with the next expected value (the expected value is obtained by cycling through the previously

stored 16 received bytes in round-robin fashion). The TMUX will perform a byte-by-byte comparison and, if differ-

ent, set the section trace identifier mismatch state register bit, TMUX_RTIMS; see Table 101 on page 94. Any

change to TMUX_RTIMS will be reported via delta and interrupt register bits TMUX_RTIMSD; see Table 92,

starting on page 81 and TMUX_RTIMSM; see Table 96 on page 90.

■TMUX_J0MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for a 0x0A character to

indicate that the next byte is the first byte of the path trace message. The J0 byte message is continuously writ-

ten into TMUX_J0DMON[1—16][7:0] registers with the first byte residing at the first address. If any received byte

does not match the previously received byte for its location, then the state register bit, TMUX_RTIMS, is set. Any

change to RTIMS will be reported via delta and interrupt mask register bits TMUX_RTIMSD and

TMUX_RTIMSM.

■TMUX_J0MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most

significant bit (MSB) set to one, which indicates that the next byte is the second byte of the message. The rest of

operation is the same as in SONET framing mode.

■TMUX_J0MONMODE[2:0] = 011: a new J0 byte (TMUX_J0DMON[1][7:0]) will be detected after the number of

consecutive consistent occurrences of a new pattern in the J0 overhead byte as determined by the values in reg-

isters TMUX_CNTDJ0[3:0]; see Table 108 on page 100. Any changes to this byte are reported via delta and

interrupt mask registers TMUX_RTIMSD and TMUX_RTIMSM. The TMUX_RTIMSD delta bit in this mode indi-

cates a change in state for the TMUX_J0DMON[1][7:0] byte and the state register bit, TMUX_RTIMS, is not

used.

■TMUX_J0MONMODE[2:0] = 100: the user will program the 16 expected values of J0 in the SONET frame into

registers TMUX_ EXPJ0DMON[1— 16][7:0]; see Table 141 on page 123. The first expected byte (the byte follow-

ing the 0x0A character) is written into the first location, TMUX_J0DMON[1][7:0]. The TMUX performs a byte-by-

byte comparison of the incoming J0 sequence with the stored expected value. If different, the TMUX will set the

section trace identifier mismatch state register bit, TMUX_RTIMS (Table 101 on page 94). Any change to

TMUX_RTIMS is reported via register bits TMUX_RTIMSD (delta state) and TMUX_RTIMSM (interrupt mask).

■TMUX_J0MONMODE[1:0] = 101: the user will program the 16 expected values of J0 in the SDH frame in regis-

ters TMUX_EXPJ0DMON[1—16][7:0]. The first byte of the message has the MSB set to 1. The TMUX performs

a byte-by-byte comparison of the incoming J0 sequence with the stored expected value. If different, the TMUX

will set the section trace identifier mismatch state register bit, TMUX_RTIMS (Table 101 on page 94). Any

change to TMUX_RTIMS will be reported via register bits TMUX_RTIMSD (delta state) and TMUX_RTIMSM

(interrupt mask).

■TMUX_J0MONMODE[1:0] = 110 and 111 are currently undefined.

17.5.6 Descrambler

A frame synchronous descrambler of length 127 and generating polynomial x7 + x6 + 1 will descramble the entire

STS-3/STM-1 (or STS-1) signal except for the first row of overhead. The scrambler will be set to 1111111 on the

first byte following the last section overhead byte in the first row (i.e., after byte J0 for STS-1). The descrambler

operates in a byte-wide mode.

The frame descrambler can be enabled or disabled using register bit TMUX_RHSDSCR (Table 103 on page 96).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

377Agere Systems Inc.

17 TMUX Functional Description (continued)

17.5.7 F1 Monitor

The TMUX monitors the fault location byte TMUX_RF1MON0[7:0] (Table 111 on page 102). A new fault location

state will be detected after the number of consecutive consistent occurrences of a new pattern in the F1 overhead

byte as determined by the value programmed in TMUX_CNTDF1[3:0] (Table 108 on page 100).

The TMUX maintains a history of the previous valid F1 byte in TMUX_RF1MON1[7:0] (Table 111 on page 102),

and any changes will be reported via TMUX_RF1MOND (delta state) (Table 92, starting on page 81) and

TMUX_RF1MONM— (interrupt mask) (Tab le 96 on page 90).

This continuous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame

state.

17.5.8 B2 BIP-8 Check

A B2 BIP-8 even parity is computed over all the incoming bits (except for the 9 section overhead bytes) of the STS-

1 frame after descrambling, and compared to the B2 byte received in the next frame. The total number of B2 BIP-8

bit errors (raw count), or block errors (as determined by TMUX_BITBLKB2; Table 104 on page 96), is counted.

Upon the assertion of the performance monitor control signal as configured in the microprocessor interface, the

raw count will be reset to zero and the value transferred to an 18-bit holding register for B2 error counts

(TMUX_B2ECNT[17:0]; see Table 135 on page 121). In case of overflow, depending on the value programmed in

the microprocessor interface register bit SMPR_SAT_ROLLOVER (Table 77 on page 70), the B2 error counter will

either roll over or saturate at the maximum value until cleared.

17.5.9 Automatic Protection Switch (APS) Monitor

The TMUX monitors the receive APS value (the K1 byte, and the five most significant bits of the K2 byte) and

stores this value in TMUX_RAPSMON[12:0] (Table 112 on page 102). This register is updated after the reception

of a programmed number of identical consecutive frames as determined by the value in TMUX_CNTDK1K2[3:0]

(Table 108 on page 100). Whenever the contents of TMUX_RAPSMON[12:0] changes, a delta bit,

TMUX_RAPSMOND will be set (Table 92, starting on page 81) and the interrupt can be masked using

TMUX_RAPSMONM (Table 96 on page 90). This indication also contributes to a separate device interrupt indica-

tion specifically intended for automatic protection switching.

The TMUX monitors this same 13-bit APS value (K1[7:0], K2[7:3]) in the receive direction and reports when the

APS value is inconsistent, using TMUX_RAPSBABE—Receive APS Babble Event (Table 92 on page 81) and

TMUX_RAPSBABM—Receive APS Babble Mask (Table 96 on page 90). Inconsistent APS bytes are defined as

the number of successive frames of ASP data where no frames satisfy the criteria for updating the

TMUX_RAPSMON register (Table 112 on page 102). The number of inconsistent frames allowed before reporting

is programmed in TMUX_CNTDK1K2FRAME[3:0] (default = 12; see Table 108 on page 100). This continuous N-

times detection counter will be reset to 0 upon the transition of the framer into the out of frame state or upon the

detection of a B1 error.

17.5.10 K2 Monitor, AIS-L, and RDI-L Detect

The three least significant bits of K2 are independently monitored and the current value is stored in

TMUX_K2MON[2:0] (Table 112 on page 102). The register will be updated after the programmed number of con-

secutive identical K2[2:0] bits. This number is programmed by the value in TMUX_CNTDK2[3:0] (Table 108 on

page 100). Whenever the contents of TMUX_K2MON[2:0] changes, a delta bit, TMUX_RK2MOND, will be set

(Table 92, starting on page 81), and the interrupt can be masked using TMUX_RK2MONM (Table 96 on page 90).

The TMUX monitors for line AIS (AIS-L/MS-AIS) in the K2[2:0] bits (K2[2:0] = 111). When line AIS is detected,

TMUX_RLAISMON (Table 101 on page 94) will be set to 1 after a number of consecutive occurrences of line AIS

as determined by the value programmed in TMUX_CNTDK2[3:0]. Once set, AIS-L will be cleared after a number of

consecutive frames of no line AIS as determined by this same value in TMUX_CNTDK2[3:0].

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

378 Agere Systems Inc.

17 TMUX Functional Description (continued)

Any change to TMUX_RLAISMON will be reported in TMUX_RLAISMOND (Table 92 , st art ing on pa ge 81 ) and the

interrupt can be masked using TMUX_RLAISMONM (Table 96 on page 90).

The TMUX monitors for a remote defect indication (RDI-L/MS-RDI) condition in the K2[2:0] bits (K2[2:0] = 110). A

line RDI condition will be detected and TMUX_RLRDIMON (Table 1 01 on page 94) will be set to 1 after a number

of consecutive occurrences of RDI as determined by the value in TMUX_CNTDK2[3:0]. Once set, RDI-L will be

cleared after a number of consecutive frames of no RDI as determined by this same value programmed in

TMUX_CNTDK2[3:0]. Any change to TMUX_RLRDIMON will be reported in TMUX_RLRDIMOND (Table 92, start-

ing on page 81), and the interrupt can be masked using TMUX_RLRDIMONM (Table 96 on page 90). This contin-

uous N-times detection counter will be reset to 0 upon the transition of the framer into the out of frame state.

17.5.11 M1 REI-L Detect

One byte (M1) is allocated for use as a line remote error indication function (REI-L). For STS-3/STM-1 signals, all

eight bits of the M1 byte are allocated for REI-L information. The REI-L value reflects the error count detected by

the line terminating equipment (LTE) (using the line BIP-8 code) back to its peer LTE. For STS-3/STM-1 signals,

the value of the error count can be up to 24. A value of 25 and above will be interpreted as no errors. If

TMUX_R_M1_B IT 7 (Tab le 106 on page 98) is 1, then the most significant bit of the byte is ignored.

The TMUX allows access to the accumulated M1-REI errored bit count from the M1 byte via TMUX_M1ECNT[17:0]

(Table 136 on page 121). The counter will count in bit or block mode, depending upon the value of

TMUX_BITBLKM1 (Table 104 on page 96). At the selected performance monitor (PM) interval, the value of the

internal running raw counter is placed into a holding register, TMUX_M1ECNT[17:0], and then cleared. Depending

on the value of SMPR_SAT_ROLLOVER (Table 77 on page 70) in the microproces s or inter fac e, the inte rnal

counter will either roll over or saturate at its maximum value until cleared.

17.5.12 Sync Status Monitor

The S1 byte is allocated for synchronization status. S1 bits [7:4] are used t o convey a 4-bit code of which only six

patterns are defined, with the remaining codes reserved for quality levels defined by individual administrations.

The S1 byte can be monitored in two modes: as an entire 8-bit word or as one 4-bit nibble (bits [7:4]), as pro-

grammed by TMUX_S1MODE4 (Table 105 on page 97).

■TMUX_S1MODE4 = 0. The associated state, delta, and mask registers are TMUX_RS1MON[7:0] (Table 113 on

page 102), TMUX_RS1MOND (Table 92, starting on page 81), and TMUX_RS1MONM (Table 96 on page 90),

respectively.

■TMUX_S1MODE4 = 1. The associated state, delta, and mask registers are TMUX_RS1MON[7:4],

TMUX_RS1MOND, and TMUX_RS1MONM.

A new value will be detected after a programmed number of consecutive occurrences of a consistent new value in

the incoming S1 byte as determine by the value in TMUX_CNTDS1[3:0] (Table 108 on page 100). A maskable

event, TMUX_RS1BABE (Table 92, starting on page 81), is set if a programmed number of consecutive frames

pass without a validated message occurring as determined by the value in TMUX_CNTDS1FRAME[3:0]

(Table 108 on page 100).

In 8-bit mode, the entire value is monitored for an inconsistent value, while in 4-bit mode, only the most significant

nibble is monitored for an inconsistent value. This continuous N-times detection counter will be reset to 0 upon the

transition of the framer into the out of frame state.

17.5.13 Receive Transport Overhead Access Channel (RTOAC)

A transport overhead access channel (TOAC) is provided on-chip to drop the transport overhead (TOH) portion of

the incoming SDH or SONET frame. The TOAC channel supports three modes of operation based on the configu-

ration of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE (Table 127 on page 115).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

379Agere Systems Inc.

17 TMUX Functional Description (continued)

The TOAC channel consists of the following signals:

■A clock signal sourced by the device pin, RTOACCLK (external output pin AD1). The clock frequency depends

on the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 534.

■A data signal out of RTOACDAT A (external output pin AD3). The data rate and the values transmitted depend on

the values of TMUX_RTOAC_D13MODE and TMUX_RTOAC_D412MODE. See Table 534.

■An 8 kHz synchronization signal, out to output pin, RTOACSYNC (external output pin AA5). The sync signal is

normally low. During the last clock period of each frame coincident with the least significant bit of the last byte

(the eighty-first byte for all TOH modes), the sync signal is driven high.

Receive TOAC DCC1—DCC3 Mode. In this mode, DCC bytes 1 to 3 are transmitted serially on the data pin. The

clock rate is 192 kHz. The data bytes are transmitted MSB first, and the data bytes are driven out in sequential

order: DCC1, DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes with a repetition rate of 8 kHz.

Receive TOAC DCC4—DCC12 Mode. In this mode, DCC bytes 4—12 are transmitted serially on the data output.

The clock rate is 576 kHz. The data bytes are transmitted MSB first, and the data bytes are driven out in sequential

order: DCC4, DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into

frames of 9 bytes. The frame repetition rate is 8 kHz.

Receive TOAC Full TOH Access Mode. In this mode, the data signal is partitioned into frames of 81 bytes. The

frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received most significant bit first.

The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of the previous frame. The

remaining 7 bits of this byte are not specified.

Bytes shown in Table 535 summarize the access capabilities of the receive TAOC in full access mode. The trans-

port overhead bytes shown in this table are always dropped by the receive side. There is programmability on the

transmit side regarding the insertion of these bytes. Bytes indicated in bold type are not specified in the standard,

but are available on the receive TOAC data signal.

Tab le 534. Receive TOAC Modes

TOAC Mode TMUX_RTOAC_D13MODE

Value TMUX_RTOAC_D412MODE

Value Number of Data

Bytes per Frame Clock Rate

DCC1—DC C3 1 X 3 192 kHz

DCC4—DCC 12 0 1 9 576 kHz

Full TOH Mode 0 0 81 5.184 MHz

Table 535. Transport Overhead Byte Access—Receive Direction

OH Parity A1-2 A1-3 A2-1 A2-2 A2-3 J0 Z0-2 Z0-3

B1 B1-2 B1-3 E1 E1-2 E1-3 F1 F1-2 F1-3

D1 D1-2 D1-3 D2 D2-2 D2-3 D3 D3-2 D3-3

H1-1 H1-2 H1-3 H2 H2-2 H2-3 H3 H3-2 H3-3

B2-1 B2-2 B2-3 K1 K1-2 K1-3 K2 K2-2 K2-3

D4 D4-2 D4-3 D5 D5-2 D5-3 D6 D6-2 D6-3

D7 D7-2 D7-3 D8 D8-2 D8-3 D9 D9-2 D9-3

D10 D10-2 D10-3 D11 D11-2 D11-3 D12 D12-2 D12-3

S1 Z1-2 Z1-3 Z2-1 Z2-2 M1 E2 E2-2 E2-3

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

380 Agere Systems Inc.

17 TMUX Functional Description (continued)

Receive TOAC—OH Parity. Even or odd parity can be inserted into the first bit of the MSB byte of the TOAC out-

going frame by programmi ng TMUX _RTOAC_OEP INS (Tab le 127 on page 115 ).

17.5.14 MSP 1 + 1 Payload Switch

The TMUX supports a payload 1 + 1 protection switch. In the receive direction, this occurs prior to pointer interpre-

tation. If TMUX_RPSMUXSEL1 = 1 (Table 103 on page 96), then the input receive data and clock are selected

from the protection path: device pins RPSD155P/N (pins AD10/AE10) and RPSC155P/N (pins AC10/AD11), rather

than from the normal (working) path device pins, RHSDP/N (pins AF7/AE7) and RHSCP/N (pins AC7/AD8).

17.5.15 Pointer Interpreter

The STS-3/STM-1 pointer interpreter logic block performs all necessary functions to support STS-3/STM-1, as well

as STS-1, pointer interpretation. The pointer interpreter operates as one machine in STM-1 mode and as three

independent machines in STS-3 mode. The following features are implemented:

■The pointer interpreter consists of the following states:

— LOP: loss of pointer

— AIS: alarm indiction signal (all ones in H1 and H2)

— NDF: new data flag enabled (1001,0001,1101,1011, and 1000)

— NORM: normal (disabled NDF, normal pointer)

— INC: increment (inverted I bits)

— DEC: decrement (inverted D bits)

* This state diagram is based on the ETS-417-1-1 pointer interpretation state diagram (Figure B.1). T ransitions of eight invalid pointers fro m t he

INC, DEC, and NDF states into the LOP state have been added. 5-9007(F)

Figure 27. Pointer Interpretation State Diagram

NORM

DEC

INC

NDF

AISLOP

FROM ALL STATES

8 INVALID POINTERS

FROM AL L STATES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENABLE

NDF ENAB L E

NDF

3 ANY 3 AN Y

3 NEW POINTERS

3 ANY PO INTERS

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

381Agere Systems Inc.

17 TMUX Functional Description (continued)

■The pointer interpreter transitions into the LOP state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received in 8, 9, or 10 consecutive frames, as

determined by the value in TMUX_CTDLOPCNT[1:0] (Tab le 108 on page 100), then LOP will be declared.

— Invalid pointer values. If 8, 9, or 10 consecutive frames (determined by TMUX_CTDLOPCNT[1:0]) are received

with a pointer that is not a normal value, NDF, AIS, increment, or decrement, then LOP will be declared.

■The pointer interpreter will transition out of the LOP state based on the following conditions:

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition

from the LOP state into the AIS state.

— Following three new , consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

LOP state into the NORM state.

— The pointer interpreter will not transition from the LOP state into the NDF state.

■The pointer interpreter will transition into the AIS state based on the following conditions:

— Following three consecutive frames with all ones in the H1 and H2 bytes, AIS will be declared.

■The pointer interpreter will transition out of the AIS state based on the following conditions:

— Following three new , consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

AIS state into the NORM state.

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the AIS state into the

LOP state.

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the AIS state

into the NDF state.

■The pointer interpreter will transition into the NDF state based on the following condition:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM,

NDF, AIS, INC, and DEC states into the NDF state.

■The pointer interpreter will transition out of the NDF state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, and 1000) is received for eight consecutive frames, the

pointer interpreter will transition from the NDF state into the LOP state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

NDF state into the NORM state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition

from the NDF state into the AIS state.

— Following three new , consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

NDF state into the NORM state.

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the NDF state into the

LOP state.

■The pointer interpreter will transition into the NORM state based on the following conditions:

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state, i.e., transitioning from the INC, DEC, and NDF states.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

382 Agere Systems Inc.

17 TMUX Functional Description (continued)

■The pointer interpreter will transition out of the NORM state based on the following conditions:

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the NORM state into

the LOP state.

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM

state into the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition

from the NORM state into the AIS state.

— When operating in the 8 of 10 mode, controlled by TMUX_8ORMAJORITY = 1 (Table 105 on page 97), if 8 of

the 10 I and D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer inter-

preter will transition from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D

bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition

from the NORM state into the DEC state.

— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM

state into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment

on the incoming H1 and H2 bytes, the pointer interpreter will transition from the NORM state into the INC

state.The pointer interpreter will transition into the INC state based on the following conditions.

— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for

a pointer increment on the incoming H1 and H2 bytes, the pointer interpreter will transition into the INC

state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming

H1 and H2 bytes, the pointer interpreter will transition into the INC state.

■The pointer interpreter will transition out of the INC state based on the following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the INC state

into the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition

from the INC state into the AIS state.

— Following three new , consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

INC state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

INC state into the NORM state.

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the INC state into the

LOP state.

■The pointer interpreter will transition into the DEC state based on the following conditions:

— When operating in the 8 of 10 mode (TMUX_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter will transition into the DEC state.

Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on the incoming H1 and

H2 bytes, the pointer interpreter will transition into the DEC state.

■ The pointer interpreter will transition out of the DEC state based on the following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter will transition from the DEC state

into the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter will transition

from the DEC state into the AIS state.

— Following three new , consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

DEC state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

DEC state into the NORM state.

— Following eight consecutive invalid pointers, the pointer interpreter will transition from the DEC state into the

LOP state.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

383Agere Systems Inc.

17 TMUX Functional Description (continued)

■Pointer increments and decrements will be counted and presented to the microprocessor as follows:

— Pointer increments and decrements will be monitored and counted internally.

— The internal and latched counts will be forced to clear (0x00) if TMUX_RLOP[3—1] = 1 (Table 102 on

page 94) or TMUX_RPAIS[3—1] = 1 (Table 102), where [3—1] designates the tributary number.

— Upon the configured performance monitoring interval, raw counts are transferred to holding registers for

pointer increments (TMUX_RPTR_INC[1—3][10:0] (Table 139 on page 123)) and decreme nts

TMUX_RPTR_DEC[1—3][10:0] (Table 140 on page 123), allowing access by the microprocessor. The raw

counters will reset (to 0x00).

— Depending on the value of SMPR_SAT_ROLLOVER (Table 77 on page 70) in the microprocessor interface

block, the internal running counts saturate at their maximum value or rollover.

— However, increment and decrement event indications should be ignored during LOP station.

■The current pointer state is read from TMUX_RLOP[3—1] and TMUX_RPAIS[3—1]. Any changes in pointer con-

dition are read from the delta state bits TMUX_RLOPD[3—1] and TMUX_RPAISD[3—1] (Table 93 on page 83).

The associat ed interrupt mask bits are TMUX_RLOPM[3—1] (Table 97 on page 91) and TMUX_RPAISM[3—1]

(Table 97 on page 91). When the device is receiving a concatenated signal (STM-1(AU-3)), the receive concate-

nation mode register bit, TMUX_RCONCATMODE (Table 105 on page 97), must be set for the concatenation

state machi nes (registe r bit s TM UX_CO NCAT_STATE[3—2 ][1:0 ] (Table 102 on page 94)) on ports 2 and 3 to

contribute to pointer evaluation. This state machine implements the pointer interpretation algorithm described in

ETS 300 417-1-1: January 1996 - Annex B.

17.5.16 Path Monitoring Functions

The following sections describe the path monitoring functions. For STM-1 signals, the values corresponding to

STS-1 #1 are the relevant signals. For STS-3 input data, there are three versions of each path monitor, one corre-

sponding to each STS-1. The mode bits are applied to the monitors of all three STS-1s.

J1 Monitor . J1 (path trace) monitoring has six different monitoring modes controlled by TMUX_J1MONMODE[2:0]

(Table 105 on page 97). The J1 monitoring mode for all three STS-1s within an STS-3 signal is the same.

■TMUX_J1MONMODE[2:0] = 000: The TMUX latches the value of the J1 byte every frame for a total of 64 bytes

in TMUX_J1DMON[1—3][1—64][7:0] (Table 147 on page 124, Table 148, and Table 149). The TMUX compares

the incoming J1 byte with the next expected value (the expected value is obtained by cycling through the previ-

ously stored 16 received bytes in round-robin fashion). The TMUX will perform a byte-by-byte comparison and, if

different, set the path trace identifier state register bit(s), TMUX_RTIMP[1—3] (Table 102 on page 94). The state

bit is cleared at a single byte match. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3]

(Table 93 on page 83) with interrupt mask bits, TMUX_RTIMPM[1—3] (Table 97 on page 91).

■TMUX_J1MONMODE[2:0] = 001: This is the SONET framing mode. The hardware looks for the 0x0A character

to indicate that the next byte is the first byte of the path trace message. The J1 byte message is continuously

written into registers, TMUX_J1DMON[1—3][1—64][7:0], with the first byte residing at the first address. If any

received byte does not match the previously received byte for its location, then the state bit(s),

TMUX_RTIMP[1—3], is set. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3], with

interrupt masks bits, TMUX_RTIMPM[1—3].

■TMUX_J1MONMODE[2:0] = 010: This is the SDH framing mode. The hardware looks for the byte with the MSB

set to one, which indicates that the next byte is the second byte of the message. The rest of operation is the

same as in SONET framing mode, except that there are 16 bytes instead of 64.

■TMUX_J1MONMODE[2:0] = 011: A new J1 byte (TMUX_J1DMON[1][7:0]) will be detected after a number of

consecutive consistent occurrences of a new pattern (determined by the value in TMUX_CNTDJ1[3:0]

(Table 109 on page 101)) in the J1 overhead byte. Any changes to this byte must be reported in

TMUX_RTIMPD[1—3] with the interrupt mask bits, TMUX_RTIMPM[1—3]. The delta bit(s) in this mode indicate

a change in state for the TMUX_J1DMON[1][7:0] byte and the state bits, TMUX_RTIMP[1—3], are not used.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

384 Agere Systems Inc.

17 TMUX Functional Description (continued)

■TMUX_J1MONMODE[1:0] = 100: The user will program the 64 expected values of J1 in

TMUX_EXPJ1DMON[1—3][1—64][7:0] (Table 144 on page 124, Table 145, and Table 146), in SONET framing

mode, where the first expected byte (the byte following the 0x0A character) is written into the first location of

TMUX_EXPJ1DMON[1][7:0]. The TMUX performs a byte-by-byte comparison of the incoming J1 sequence with

the stored expected value. If different, the TMUX will set the path trace identifier state bit(s),

TMUX_RTIMP[1—3]. Any change to the path trace identifier is reported in TMUX_RTIMPD[1—3] with interrupt

mask bits, TMUX_RTIMPM[1—3].

■TMUX_J1MONMODE[1:0] = 101: The user will program the 16 expected values of J1 in

EXPJ1DMON[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1. The

TMUX performs a byte-by-byte comparison of the incoming J1 sequence with the stored expected value. If differ-

ent, the TMUX will set the path trace identifier state bit(s), TMUX_RTIMP[1—3]. Any change to path trace identi-

fier is reported in register bits, TMUX_RTIMPD[1—3] with interrupt mask bits, TMUX_RTIMPM[1—3].

■TMUX_J1MONMODE[1:0] = 110 and 111 are currently undefined.

B3 BIP-8 Check. A B3 BIP-8 even parity is computed over all the incoming synchronous payload envelope bits of

the STS-3/STM-1/STS-1 signal after descrambling, and compared to the B3 byte received in the next frame. The

total number of B3 BIP-8 bit errors (raw count), or block errors (as determined by TMUX_BITBLKB3 (Table 105 on

page 97), is counted. Upon the configured performance monitor (PM) interval, the value of the internal running

counter is placed into holding registers TMUX_B3ECNT[1—3][15:0] (Table 136 on page 121) and then cleared.

Depending on the value of SMPR_SAT_ROLLOVER (Table 77 on page 70) in the microprocessor interface block,

the internal counter will either roll over or stay at its maximum value until cleared.

Signal Label C2 Byte Monitor. The C2 byte per STS-1/STM-1 is stored in TMUX_C2MON[1—3][7:0] (Table 114

on page 10 3 ). Each register will be updated after a number, determined by the value in TMUX_CNTDC2[3:0]

(Table 109 on page 101), of consecutive frames of identical C2 bytes for a given STS-1/STM-1, i.e., the 8-bit pat-

tern must be identical for a programmed number frames prior to updating the C2 register. Any change to C2 byte

monitor is reported via the corresponding delta and mask register bits, TMUX_RC2MOND[1—3] (Table 93) and

TMUX_RC2MONM[1—3] (Table 97 on page 91).

In addition, there are programmable expected value(s) for the C2 bytes of each STS-1/STM-1 in

TMUX_C2EX P[1—3][7:0] (Table 110 on page 102). If the current value of a C2 byte in TMUX_C2MON[1—3][7:0]

does not equal the expected C2 value in TMUX_C2EXP[1—3][7:0]), then a payload label mismatch defect may be

declared for that STS-1/STM-1 in TMUX_RPLMP[1—3] (Table 102 on page 94). Also, if the current value of a

C2 byte is all zeros, then the corresponding unequipped defect is declared in TMUX_RUNEQP[1—3] (Table 102).

Note: The payload label mismatch and unequipped defects are mutually exclusive and unequipped takes priority.

The Table 536 describes the conditions for generating payload label mismatch (TMUX_RPLMP[1—3]) and

unequipped defects (TMUX_RUNEQP).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

385Agere Systems Inc.

17 TMUX Functional Description (continued)

Table 536. STS Signal Label Defect Conditions

TMUX_FORCEC2DEF[2:0] will force path payload label mismatch defects on those conditions that are shown in

Table 536.

The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame

state.

RDI-P Detection. A remote defect indication-path (RDI-P) signal indicates to STS path terminating equipment

(PTE) that its peer STS PTE has detected a defect on the signal that it originated. The TMUX supports a 1-bit

RDI-P code as well as a 3-bit enhanced RDI-P code; the mode is selectable using the TMUX_REPRDI_MODE

(Table 105 on page 97). If TMUX_REPRDI_MODE = 0, then the 1-bit code is supported, and if

TMUX_REPRDI_MODE = 1, then the 3-bit enhanced path RDI code is supported.

The TMUX monitors for a 1-bit RDI-P code in G1[3] or a 3-bit enhanced remote defect indication (RDI-P) condition

in G1[3:1]. The current value of the path RDI state will be detected after a number of consecutive occurrences

determined by the value in TMUX_CNTDRDIP[3:0] (Table 109 on page 101). The current value(s) will be stored in

TMUX_RDIPMON[1—3][2:0]] (Table 114 on page 103), for nonenhanced RDI-P mode, and the current value(s)

will be stored in TMUX_RDIPMON[1—3][2:0], for enhanced RDI-P mode. Any change to

TMUX_RDIPMON[1—3][2:0] will be reported in TMUX_RRDIPD[1—3] with interrupt mask

bits,TMUX_RRDIPM[1—3] (Table 97 on page 91).

The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame

state.

Provisioned STS PTE

Functionality, Expected C2 Received Payload Label

(C2 in hex) Defect TMUX_FORCEC2DEF = 1

(Table 107 on page 99)

Any Equipped Functionality Unequipped (00) TMUX_RUNEQP No Change

Any Equipped Functionality Equipped—Nonspecific (01) None No Change

Equipped—Nonspecific Any Value (02 to E0, FD to FE) None No Change

Any Payload Specific Code The Same Payload Specific

Code (02 to E0, FD to FE) None No Change

Any Payload Specific Code A Different Payload Specific

Code (02 to E0, FD to FE) TMUX_ RPL MP No Change

Equipped—Nonspecific (01) or

VT-Structured STS-1 (02) PDI, 1 to 27 VTx Defects

(E1 to FB) None TMUX_RPLMP

Any Payload Specific Code

Except VT-Structured

STS-1 (02)

PDI, 1 to 27 VTx Defects

(E1 to FB) TMUX_ RPL MP No Change

Any Equipped Functionality PDI, 28 VT1.5 Defects or 1

Non-VT Payload Defect (FC) None TMUX_RPLMP

Any Equipped Functionality Reserved (FF) None TMUX_RPLMP

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

386 Agere Systems Inc.

17 TMUX Functional Description (continued)

REI-P Detection. Bits [7:4] of the G1 byte are allocated for use as a path remote error indication function (REI-P).

■For STS-1 and STM-1 signals, bits [7:4] of the G1 byte are allocated for REI-P, which conveys the error count

detected by the PTE (using the path BIP-8 code B3) back to its peer PTE as shown in Table 537.

Table 537. STS-1 P-REI Interpretation

The TMUX allows access to the G1-REI errored bit count for each STS-1/STM-1 in TMUX_G1ECNT[1—3][15:0]

(Table 138 on page 122), which is the accumulated error count from G1[3:0] byte of the STS-1/STM-1 signal. The

counter(s) will count in bit or block mode, depending on the value of TMUX_BITBLKG1 (Table 105 on page 97).

Upon the configured performance monitor (PM) interval, the value of the internal running counter is placed into the

holding registers TMUX_G1ECNT[1—3][15:0] and then cleared. Depending on the value of

SMPR_SAT_ROLLOVER (Table 77 on page 70) in the microprocessor interface block, the internal counter will

either roll over or stay at its maximum value until cleared.

Path User Byte F2 Monitor. The TMUX monitors the path user channel in the F2 byte of each STS-1/STM-1. The

F2 byte(s) will be stored in TMUX_F2MON0[1—3][7:0] (Tabl e 114, starting on page 103). Each register will be

updated after a number of consecutive frames of identical F2[7:0], as determined by the value in

TMUX_CNTDF2[3:0] (Table 109 on page 101). That is, the 8-bit pattern must be identical for the programmed

number of frames prior to updating the F2 register. Any change to F2 monitor registers will be reported in

TMUX_RF2MOND[1—3] (Table 93) with interrupt mask bits, TMUX_RF2MONM[1—3] (Table 97 on page 91). The

TMUX also maintains a history of the previous valid F2 byte in TMUX_F2MON1[1—3][7:0] (Table 114). The contin-

uous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the out of frame state.

H4 Multif rame Indicator. The H4 byte is allocated for use as a mapping specific indicator byte. For VT-structured

SPEs, this byte is used as a multiframe indicator.

The TMUX passes the H4 byte of each STS-1 onto the low-speed telecom bus so that it can be monitored by the

VT mapper block. The TMUX also indicates when the H4 byte(s) has a value of 0x01 by asserting the RLSV1 out-

put pin (pin number W4) on the telecom bus during that frame.

Note: The three H4 bytes of an STS-3 signal can occur at any time with respect to one another within a frame.

Path User Byte F3 Monitor. The TMUX monitors the second path user channel in the F3 byte for each

STS-1/STM-1 . The F3 b yte(s) for each STS-1/STM-1 is stored in TMUX_F3MON0[1—3][7:0] (Table 114 on

page 103). Each register will be updated after a number determined by the value in TMUX_CNTDF3[3:0]

(Table 109 on page 101) of consecutive frames of identical F3[7:0] monitor bytes on that particular STS-1. That is,

the 8-bit pattern must be identical for the programmed number of frames prior to updating the F3 register.

G1[7:4] Code Code Interpretation

0000 0 (no errors )

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 0 (no errors )

. . . . . .

1111 0 (no errors)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

387Agere Systems Inc.

17 TMUX Functional Description (continued)

Any change to F3 byte monitor registers is reported in TMUX_RF3MOND[1—3] (Table 93 on page 83) with inter-

rupt mask bits, TMUX_RF3MONM[1—3] (Table 97 on page 91).

The TMUX also maintains a history of the previous valid F3 byte in TMUX_F3MON1[1—3][7:0] (Table 114 on

page 103). The continuous N-times detection counter(s) will be reset to 0 upon the transition of the framer into the

out of frame state.

K3 Byte Monitor. The TMUX monitors the K3 byte for each STS-1/STM-1. The K3 byte(s) is stored in

TMUX_K3MON[1—3][7:0] (Tab le 114 on page 103). Each register will be updated after a number determined by

the value in TMUX_CNTDK3[3:0] (Table 109 on page 101) of consecutive frames of identical K3[7:0] for that par-

ticular

STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the K3 register.

Any change to K3 monitor registers is reported in TMUX_RK3MOND[1—3] (Table 93 on page 83) with interrupt

mask bits, TMUX_RK3MONM[1—3] (Table 97 on page 91). The continuous N-times detection counter(s) will be

reset to 0 upon the transition of the framer into the out of frame state.

N1 Byte Monitor. The TMUX monitors the N1 byte for each STS-1/STM-1. The N1 byte(s) is stored in

TMUX_N1MON[1—3][7:0] (Table 114 on page 103). Each register will be updated after a number determined by

the value in TMUX_CNTDN1[3:0] (Table 109 on page 101) of consecutive frames of identical N1[7:0] for that par-

ticular STS-1/STM-1. That is, the 8-bit pattern must be identical for a number of frames prior to updating the N1

with interrupt mask bits, TMUX_RN1MONM[1—3] (Table 97 on page 91). The continuous N-times detection

counter(s) will be reset to 0 upon the transition of the framer into the out of frame state.

Signal Degrade BER Algorithm. A signal degrade state in register bit TMUX_RHSSD (Table 101 on page 94)

and change of state indication is reported in register bit TMUX_RHSSDD (Table 92, starting on page 81), with the

interrupt mask bit, TMUX_RHSSDM (Table 97 on page 91). This bit error rate algorithm can operate on either B1

or B2 errors, determined by the value of TMUX_SDB1B2SEL (Table 105 on page 97). Each B3 mon ito r ha s an

independent signal degrade function as well in TMUX_RSDB3[1—3] (Table 102 on page 94).

Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block con-

sisting of a number of frames in TMUX_SDNSSET[18:0] (Table 130 on page 118), and a measurement interval

consisting of a number of monitoring blocks in TMUX_SDBSET[11:0] (Table 130). A block is determined bad when

the number of bit errors equals or exceeds a threshold set in TMUX_SDLSET[3:0] (Table 130). Signal degrade is

declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SDMSET[7:0]

(Table 538) for the measurement interval.

Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consist-

ing of a number of frames in TMUX_SDNSCLEAR[18:0] (Table 130), and a measurement interval consisting of a

number of monitoring blocks in TMUX_SDBCLEAR[11:0] (Table 130). A block is determined good when the num-

ber of bit err ors i s l ess th an a thr esh old s e t in TMUX _SD LCL EAR [3:0 ] ( Table 130). Signal degrade is cleared when

a number of good monitoring blocks equals or exceeds the threshold in TMUX_SDMCLEAR[7:0] (Table 130) for

the measur ement interval.

The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the

signal degrade state is declared.

The signal degrade state may be forced to the declared state with TMUX_SDSET (Table 88 on page 79) and

forced to the cleared state with TMUX_SDCLEAR (Table 88). One shot signal must be provided to force the BER

algorithm into the failed state or normal state, respectively.

The algorithm described above can detect bit error rates from 1 x 10–3 to 1 x 10–9.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

388 Agere Systems Inc.

17 TMUX Functional Description (continued)

Table 538. Signal Degrade (SD) Parameters

Note: The thresholds written by the control system will be one less than the desired number, except for the

TMUX_SDLSET[3:0] and TMUX_SDLCLEAR[3:0] parameters.

Signal Fail BER Algorithm. A signal degrade state in register bit TMUX_RHSSF (Table 101) and change of state

indication is reported in register bit TMUX_RHSSFD (Table 92, starting on page 81), with the interrupt mask bit,

TMUX_RHSSFM (Table 96 on page 90). This bit error rate algorithm can operate on either B1 or B2 errors

selected with register bit TMUX_SDB1B2SEL (Tab le 105 on page 97). Each B3 monitor has its own bit error rate

algorithm as well as the failure indicated in TMUX_RSFB3[1—3] (Table 102 on page 94).

Declaring the signal degrade state requires the definition of two measurement windows, a monitoring block con-

sisting of a number of frames in TMUX_SFNSSET[18:0] (Table 131 on page 119), and a measurement interval

consisting of a number of monitoring blocks in TMUX_SFBSET[11:0] (Table 131). A block is determined bad when

the number of bit errors equals or exceeds a threshold set in TMUX_SFLSET[3:0] (Table 131). Signal degrade is

declared when a number of bad monitoring blocks equals or exceeds the threshold in TMUX_SFMSET[7:0]

(Table 131) for the measurement interval.

Name Function

TMUX_SDNSSET[18:0] (Table 130 on page 118)Signal Degrade Ns Set. Number of frames in a monitoring

block for SD.

TMUX_SDLS ET[3:0] (Table 130)Signal Degrade L Set. Error threshold for determining if a

monitoring block is bad.

TMUX_SDMSET[7:0] (Table 130)Signal Degrade M Set. Threshold of the number of bad moni-

toring blocks in an observation interval. If the number of bad

blocks is below this threshold, then SD is cleared.

TMUX_SDBSET[15:0] (Table 130)Signal Degrade B Set. Number of monitoring blocks in a

measurement interval.

TMUX_SDNSCLEAR[18:0] (Table 130)Signal Degrade Ns Clear. Number of frames in a monitoring

block for SD.

TMUX_SDLCLEAR[3:0] (Table 130)Signal Degrade L Clear. Error threshold for determining if a

monitoring block is bad.

TMUX_SDMCLEAR[7:0] (Table 130)Signal Degrade M Clear. Threshold of the number of bad

monitoring blocks in an observation interval. If the number of

bad blocks is below this threshold, then SD is cleared.

TMUX_SDBCLEAR[15:0] (Table 130)Signal Degrade B Clear. Number of monitoring blocks in a

measurement interval.

TMUX_SDSET (Table 88 on page 79)Signal Degrade Set. Allows the signal degrade algorithm to

be forced into the failed state (active 0 to 1).

TMUX_SDCLEAR (Table 88)Signal Degrade Clear . Allows the signal degrade algorithm to

be forced into the normal state (active 0 to 1).

TMUX_SDB1B2SEL (Table 105 on page 97)Signal Degrade B1/B2 Error Count Select. Control bit, when

set to a logic 0, causes the signal fail bit error rate algorithm to

use B1 errors; otherwise, B2 errors are used to calculate the

error rate.

TMUX_RHSSD (Table 101 on page 94)Signal Degrade BER Algorithm State Bit.

TMUX_RHSSDD (Table 92 on page 81)Signal Degrade BER Algorithm Delta Bit.

TMUX_RHSSDM (Table 96 on page 90)Signal Degrade BER Algorithm Mask Bit.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

389Agere Systems Inc.

17 TMUX Functional Description (continued)

Clearing the signal degrade state requires the definition of two measurement windows, a monitoring block consist-

ing of a number of frames in TMUX_SFNSCLEAR[18:0] (Table 131 on page 119), and a measurement interval

consisting of a number of monitoring blocks in TMUX_SFBCLEAR[11:0] (Table 131). A block is determined good

when the number of bit errors is less than a threshold set in TMUX_SFLCLEAR[3:0] (Table 131).

Signal degrade is cleared when a number of good monitoring blocks equals or exceeds the threshold in

TMUX_SFMCLEAR[7:0] (Table 131) for the measurement interval.

The set parameters are used when the signal fail state is clear , and the clear parameters are used when the signal

fail state is declared.

The signal degrade state may be forced to the declared state with TMUX_SFSET (Table 88 on page 79) and

forced to the cleared state with TMUX_SFCLEAR (Table 88). One shot signal must be provided to force the BER

algorithm into the failed state or normal state, respectively.

The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.

Table 539. Signal Fail Parameters

Note: The thresholds written by the control system will be one less than the desired number, except for the

TMUX_SFLSET[3:0] and TMUX_SFLCLEAR[3:0] parameters.

Name Function

TMUX_SFNSSET[18:0] (Table 131 on page 119)Signal Fail Ns Set. Number of frames in a monitoring block

for SF.

TMUX_SFLSET[3:0] (Table 131)Signal Fail L Set. Error threshold for determining if a monitor-

ing block is bad.

TMUX_SFMSET[7:0] (Table 131)Signal Fail M Set. Threshold of the number of bad monitoring

blocks in an observation interval. If the number of bad blocks

is below this threshold, then SF is cleared.

TMUX_SFBSET[15:0] (Table 131)Signal Fail B Set. Number of monitoring blocks.

TMUX_SFNSCLEAR[18:0] (Table 131)Signal Fail Ns Clear . Number of frames in a monitoring block

for SF.

TMUX_SFLCLEAR[3:0] (Table 131)Signal Fail L Clear. Error threshold for determining if a moni-

toring block is bad.

TMUX_SFMCLEAR[7:0] (Table 131)Signal Fail M Clear. Threshold of the number of bad monitor-

ing blocks in an observation interval. If the number of bad

blocks is below this threshold, then SF is cleared.

TMUX_SFBCLEAR[15:0] (Table 131)Signal Fail B Clear. Number of monitoring blocks.

TMUX_SFB1B2SEL (Table 105 on page 97)Signal Fail B1/B2 Error Count Select. Control bit, when set

to a logic 0, causes the signal fail bit error rate algorithm to

use B1 errors; when set to a logic 1, causes the signal fail bit

error rate algorithm to use B2 errors.

TMUX_SFSET (Table 88 on page 79)Signal Fail Set. Allows the signal degrade algorithm to be

forced into the failed state (active 0 to 1).

TMUX_SFCLEAR (Table 88)Signal Fail Clear. Allows the signal degrade algorithm to be

forced into the normal state (active 0 to 1).

TMUX_RHSSF (Table 101 on page 94)Signal Fail BER Algorithm State Bit.

TMUX_RHSSFD (Table 92 on page 81)Signal Fail BER Algorithm Delta Bit.

TMUX_RHSSFM (Table 96 on page 90)Signal Fail BER Algorithm Mask Bit.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

390 Agere Systems Inc.

17 TMUX Functional Description (continued)

Path Overhead Access Channel (POAC) Drop. The TMUX provides one path overhead access channel (POAC

output channel). The TMUX can receive up to three STS-1 signals. There are two register bits,

TMUX_RPOAC_SEL[1:0] (Table 128 on page 117), to designate which STS-1s POH will be dropped onto the

POAC channel. TMUX_RPOAC_SEL[1:0] = 01 designates STS-1 #1, TMUX_RPOAC_SEL[1:0] = 10 designates

STS-1 #2, and TMUX_RPOAC_SEL[1:0] = 11 designates STS-1 #3. TMUX_RPOAC_SEL[1:0] = 00 designates

that the RPOAC channel is not driven by the TMUX.

The POAC channel consists of the following signals:

■A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).

■A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4).

■An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally

low. During the last clock period of each frame coincident with the least significant bit of the last byte, the sync

signal is high.

The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits

that are transmitted/received most significant bit first. The MSB of the second byte of each frame contains an

odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified.

Bytes shown in Table 541 summarize the access capabilities of the receive POAC.

Table 541. Path Overhead Byte Access

Even or odd parity can be inserted into the first bit of the MSB byte of the POAC outgoing frame. Parity is selected

with TMUX_RPOAC_OEPINS (Table 128 on page 117).

AIS-P Insertion and AUTO_AISO Generation. Upon detecting certain failure conditions, the TMUX asserts the

external output signals named AUTO_AIS[1—3] (pins AD6, AE6, and AC6). The AUTO_AIS[1—3] signals, one per

STS-1, also informs the other blocks within the Supermapper to insert AIS downstream due to detected failures.

The following conditions can cause AUTO_AISO[1—3] signals to be asserted: line AIS, LOC (STS-1 mode only),

LOS, LOF, OOF, LOP-P, SF (B1, B2, or B3), SD (B1, B2, or B3), payload label mismatch, or payload unequipped.

Each condition can be individually inhibited from contributing to the internal AUTO_AISO[1—3] signals. For concat-

enated signals (STS-3c or STM-1), all AUTO_AISO[1—3] signals should be driven coincidentally. In STS-3 mode,

each STS-1 signal has a corresponding AUTO_AISO signal.

Table 540. Signal Fail or Signal Degrade Recommended Programming Values

Set

Threshold NsSet LSet MSet BSet Clear

Threshold NsClear LClear MClear BClear

1x10–3 0x00001 0x5 0x3D 0x003D 1x10–4 0x00001 0x6 0x03 0x0007

1x10–4 0x00006 0x8 0x03 0x0007 1x10–5 0x00006 0x2 0x03 0x0007

1x10–5 0x00030 0x6 0x03 0x0007 1x10–6 0x00030 0x2 0x03 0x0007

1x10–6 0x001E0 0x6 0x03 0x0007 1x10–7 0x001E0 0x2 0x03 0x0007

1x10–7 0x01275 0x6 0x04 0x0009 1x10–8 0x01275 0x2 0x04 0x0009

1x10–8 0x0B5A4 0x6 0x04 0x0009 1x10–9 0x0B5A4 0x2 0x03 0x0009

1x10–9 0x3F7A0 0x4 0x05 0x0013 1x10–10 0x3F7A0 0x2 0x02 0x000F

POH Parity

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

391Agere Systems Inc.

17 TMUX Functional Description (continued)

The following boolean expression is the criteria for AUTO_AIS and send path AIS. The expressions represent com-

binations of signal status states register bits and inhibit state register bits that form the criteria.

Criteria for AUTO_AISO<n> =

((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX _RPSMUXSEL) OR

(TMUX_RILOC AND TMUX_RILOC_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSLOS AND TMUX_RHSLOS_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR

(TMUX_RHSOOF AND TMUX_RHSOOF_AISINH) OR

(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR

(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RSFB3<n> AND TMUX_RSFB3_AISINH) OR

(TMUX_RSDB3<n> AND TMUX_RSDB3_AISINH) OR

(TMUX_RPLMP<n> AND TMUX_RHPLMP_AISINH) OR

(TMUX_RUNEQP<n> AND TMUX_RUNEQP_AISINH) OR

(TMUX_RTIMP<n> AND TMUX_RTIMP_AISINH) OR

(TMUX_RPAIS_INS))

In addition to generating the external AUTO_AIS signal, the TMUX can insert path AIS into the received signal prior

to driving it onto the low-speed telecom bus. The conditions for sending path AIS include some of the above condi-

tions. The same inhibit bits are used as above. Note that the above AUTO_AISO[1—3] signal generation is on a

per STS-1 basis, while sending path AIS occurs on the complete STS-3/STM-1 signal (or STS-1 for STS-1 only

mode).

Criteria for Send Path AIS =

((TMUX_RLAISMON AND TMUX_RLAISMON_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSLOS AND TMUX_RHSLOS_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSLOF AND TMUX_RHSLOF_AISINH) OR

(TMUX_RHSOOF AND TMUX_RHSOOF_AISINH) OR

(TMUX_RLOP<n> AND TMUX_RLOP_AISINH) OR

(TMUX_RHSSF AND TMUX_RHSSF_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RHSSD AND TMUX_RHSSD_AISINH AND TMUX_RPSMUXSEL) OR

(TMUX_RPAIS_INS))

Receive Side Telecom Bus Interface. The TMUX outputs one parallel clock (RLSCLK, pin V4), three sync signals

(RLSSPE, RLSJ0J1V1, and RLSV1; pin numbers V1, V3, and W4), an 8-bit data bus (RLSDATA[7:0], pins R1, R3,

T4, T2, T3, U4, U2, and U3), and an odd/even (RLSPAR, pin V2) parity signal. The data bus carries either three

STS-1/TUG-3 signals, each in their own time slot, or it carries one STS-1 signal where the parallel clock operates

at 6.48 MHz instead of 19.44 MHz.

5-9008(F)

Figure 28. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals

A1-1 A1-2 A1-3 A2-1 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3A2-2

A1 A2 J0 J1 V1

3 BYTES 3 BYTES 3 BYTES 3 BYTES 3 BY TES

RLSSPE

RLSJ0J1V1

RLSV1

RLSDATA[7:0]

RLSCLK

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

392 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.6 Transmit Direction (Transmit Path to SONET/SDH Line)

All functions supported by TMUX in the transmit direction are summarized below:

■Tran sm it si de tele co m b us inter fac e

■Path overhead access channel (POAC) insert

■Path overhead insertion functions

■MSP 1 + 1 payload switch

■Transport overhead access channel (TOAC) insert

■Section and line overhead insertion functions

17.6.1 Transmit Side Telecom Bus Interface

The TMUX transmit side drives a parallel clock (TLSCLK, pin AA2) and three sync signals (TLSSPE, TLSJ0J1V1,

and TLSV1; pins AB2, AB4, and AB3) onto the telecom bus. From these sync signals, the SPE mappers can deter-

mine when to drive data onto the bus. The TMUX receives an 8-bit data bus (TLSDAT A[7:0], pins W2, W1, W3, Y4,

Y2, Y1, Y3, and AA4), and an odd/even (TLSPAR, pin AA3) parity signal from the telecom bus. The data consists

of the SPE for up to 3 STS-1s.

The parallel clock operates at 19.44 MHz for STS-3/STM-1 modes and at 6.48 MHz for STS-1 mode.

5-9009(F)

Figure 29. Transmit Low- Speed Bus Interface Signals for STS-3/STM-1 Signals

17.6.2 Transmit Path and Transport Overhead Insertion Diagram

The transmit block consists of two overhead insertion sections. The first section inserts the path overhead (POH)

bytes into the payload data to create an STS-3/STM-1/STS-1 SPE. After POH insertion, there is an MSP 1 + 1 pro-

tection switch on the payload. After the switch selection is made, the transport overhead bytes are added to the

SPE to generat e a compl ete SONE T /SDH frame .

A1-1 A1-2 A1-3 A2-1 A2-3 J0-1 J0-2 J0-3 J1-1 J1-2 J1-3 V1-1 V1-2 V1-3A2-2

A1 A2 J0 J1 V1

3 BYTES 3 BYTES 3 BYTES 3 BYTES 3 BYTES

TLSSPE

TLSJ0J1V1

TLSV1

TLSDATA[7:0]

TLSCLK

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

393Agere Systems Inc.

17 TMUX Functional Description (continued)

5-9010(F)r.2

Figure 30. Transmit Direction POH and TOH Insertion Diagram

The first section, which is the path overhead section, is broken down into the following functional parts:

■J1 path trace insert

■B3 calculation and insert

■C2 signal label insert

■REI-P and RDI-P insert

■Path user byte F2 insert

■H4 multiframe insert

■Path user byte F3 insert

■ K3 insert

■Tandem connection byte N1 insert

■ AIS-P insert

SCRAM. INSERT INSERT

AIS

MSOH

INSERT LINE/MSOH

F1 B2

GENERATE K1/K2 RDI-L M0

REI-L SYNC

APS

B2 K1

INSERT

K2 M0 S1

STATUS

B1 F1

SECTION/RSOH

INSERT J0

A1/A2

TRANSMIT PATH TO SONET/SDH LINE (TRANSMIT DIRECTION)

TRANSMIT DATA

TOAC INSERT

D4—D12 AND E2

B1, E1, F1, D1—3 INSERT

INSERT

J1 INSERT

N1 INSERT

C2 INSERT

REI-P

INSERT

RDI-P

INSERT

APS

INSERT

N1 C2 F3 F2K3 G1 G1J1

INSERT

AIS-P

POAC IN SERT

F2, F3, C2, N1, AND J1

INSERT PATH OVERHEAD BYTES

INSERT

TELECOM BUS

TRANSMIT PROTECTION

MSP 1 + 1

SWITCH

SWITC H BU S DATA

[2:0]

GENERATE

INSERT

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

394 Agere Systems Inc.

17 TMUX Functional Description (continued)

The second section after the switch, the transport overhead section, is broken down into the following functional

parts:

■ TOAC insert

■ Sync status byte (S1) insert

■ M0/M1—REI-L insert

■ K1 and K2 insert

■ AIS-L insert

■ B2 calculation and insert

■ F1 byte insert

■ B1 generate and error insert

■ Scrambler

■ J0 inse rt control

■ A2 error insert

All insert control functions that are inhibited will insert all zeros or all ones, depending on the value of microproces-

sor register bit, SMPR_OH_DEFLT (Table 77 on page 70).

17.6.3 POAC Insert

One path overhead access channel (POAC) is provided on-chip to provision the path overhead (POH) portion of

the outgoing frame. The TMUX transmits up to three STS-1s. The register bits TMUX_TPOAC_SEL[1:0]

(Table 128 on page 117) designate which STS-1s POH is inserted from the transmit POAC channel.

TMUX_TPOAC_SEL[1:0] = 00 designates no TMUX_TPOAC insertion, TMUX_TPOAC_SEL[1:0] = 01 designates

STS-1 #1, TMUX_TPOAC_SEL[1:0] = 10 designates STS-1 #2, and TMUX_TPOAC_SEL[1:0] = 11 designates

STS-1 #3.

A POAC channel consists of the following signals:

■A 576 kHz inverted clock signal sourced by the TMUX (TPOACCLK, pin AE4).

■A 576 kbits/s serial data signal received by the TMUX in the transmit direction (TPOACDATA, pin AD5).

An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the TMUX. The sync signal is normally low.

During the last clock period of each frame, coincident with the least significant bit of the eighth byte, the sync signal

is high.

The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits

that are transmitted/received most significant bit first. The MSB of the first byte of each frame contains an odd/even

parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. The B3, G1, and

H4 transmit path overhead bytes are not provisionable via the POAC channel.

Bytes shown in Table 542 summarize the access capabilities of the transmit POAC channel. X indicates a don’t

care.

Table 542. Path Overhead Byte Access—Transmit Direction

J1 X F3

POH Parity F2 K3

C2 X N1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

395Agere Systems Inc.

17 TMUX Functional Description (continued)

An event indication TMUX_TPOAC_PE (Table 90 on page 80), interrupt mask bit TMUX_TPOAC_PM (Table 94

on page 89), is provided to indicate parity errors for the POAC channel. Odd (logic 0)/even (logic 1) parity is

checked and is configured with TMUX_TPOAC_OEPMON (Table 127 on page 115).

Table 543 summarizes the insertion options for the specified overhead bytes for POAC. The TMUX allows a fixed

default value (all zeros or all ones) to be inserted on the corresponding POAC value. All control signals are active-

high.

Table 543. TPOAC Control Bits

17.6.4 AIS Path Generation

Path AIS is specified as all ones in the entire STS-1 signal before scrambling, excluding the transport overhead

(section and li ne ove rhead ).

Path AIS can be inserted for each STS-1 in the STS-3 using register bits TMUX_TLS_PAISINS[3:1] (Table 115 on

page 104).

17.6.5 J1 Insert Control

A 64-byte sequence stored in TMUX_TJ1DINS[1—3][1—64][7:0] (Table 150 on page 125, Table 151, and

Table 152), will be inserted into the outgoing J1 byte if TMUX_THSJ1INS (Table 118 on page 107) is set to 1. Oth-

erwise, the associated POAC value is inserted when TMUX_TPOAC_J1 (Table 128 on page 117) is a logic 1, or

the default value is inserted when TMUX_TPOAC_J1 is logic 0.

17.6.6 B3 BIP-8 Calculation and Insert

The B3 bytes are allocated for a path overhead error monitoring function. This function will be a bit interleaved par-

ity 8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous STS-1

frame except for the first three columns consisting of the section and line overhead and is placed in byte B3 of the

current frame, also before scrambling.

A bit error rate can be inserted on any B3 byte with TMUX_THSB3ERRINS[1—3] (Table 125 on page 114) and

microprocessor interface block SMPR_BER_INSRT (Table 75 on page 68) bit. When TMUX_THSB3ERRINS[1—

3] is asserted, the corresponding B3 byte is inverted each time the SMPR_BER_INSRT bit is asserted.

17.6.7 C2 Signal Label Byte Insert

When TMUX_THSC2INS[1—3] = 1 (Table 118 on page 107), the value in TMUX_TC2INS[1—3][7:0] (Table 134

on page 120) is inserted into the C2 byte of the outgoing signal. Otherwise, the associated POAC value is inserted

when TMUX_TPOAC_C2 = 1 (Table 128 on page 117). If both TMUX_THSC2INS and TMUX_TPOAC_C2 = 0,

then the value inserted depends on the microprocessor interface block, SMPR_OH_DEFL T (Table 77 on page 70),

bit value. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are

inserted.

Overhead Bytes Register Control Bits Values

0 (Default Value) 1

J1 TMUX_TPOAC_J1 (Table 128 on page 117)SMPR_OH_DEFLT

(00000000/11111111) TPOAC

Data

C2 TMUX_TPOAC_C2 (Table 128)

F2 TMUX_TPOAC_F 2 (Table 128)

F3 TMUX_TPOAC_F 3 (Table 128)

K3 TMUX_TPOAC_K3 (Table 128)

N1 TMUX_TPOAC_N1 (Table 128)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

396 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.6.8 Path RDI (RDI-P) Insert

When TMUX_THSRDIPINS = 1 (Table 118 on page 107), then data from TMUX_TRDIPINS[1—3][2:0] (Table 124

on page 112) is written into the corresponding three STS-1 G1 byte output bits (G1[3:1]). For STS-3 mode, each

STS-1 signal carries its own G1 value. For STM-1 mode, only TMUX_TRDIPINS1[2:0] is written into the first

STS-1 location. When TMUX_THSRDIPINS = 0, hardware insert is enabled for RDI-P insertion. Each defect contri-

bution to the RDI-P outgoing code can be inhibited. There are two modes supported for path RDI insertion. One

mode conforms to the earlier 1-bit version of the standard. The other mode, enhanced RDI-P mode, uses a 3-bit

RDI-P code and conforms to the current version of the standard. When TMUX_TEPRDI_MODE = 0 (Tabl e 12 0 on

page 111), the TMUX sends a 3-bit code that conforms to the earlier 1-bit version of the standards. If

TMUX_TEPRDI_MODE = 1, the TMUX will send a 3-bit code conforming to the current enhanced path RDI encod-

ing. Note that for nonenhanced RDI-P mode, the relevant defects are AIS-P and LOP-P. For enhanced RDI-P

mode, the relevant defects are AIS-P, LOP-P, PLM-P, and UNEQ-P.

When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must

last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.

Table 544 describes the encoding of the path RDI defects.

Table 544. RDI-P Defects for Enhanced RDI-P Mode

The TMUX provides a protection switch MUX for RDI-P insertion. The MUX is controlled by TMUX_TPREIRDISEL

(Table 117 on page 105). If TMUX_TPREIRDISEL = 1, then the RDI-P value for insertion is taken from the value

on the protection board rather than from the receive side of the same TMUX.

17.6.9 REI-P: G1(7:4) Insert

Four bits of the G1 byte G1(7:4) are allocated for use as path remote error indication (REI). For STS-1 signals and

for STM-1 signals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been

detected in error by the BIP-8 (B3) detector on the received signal.

The automatic insertion of path REI can be inhibited on an STS-1 basis by programming the corresponding register

bits TMUX_TPREIINS[1:3] (Table 125 on page 114) to 1. For STM-1 mode, only TMUX_TPREIINS[1] is relevant. If

the register bit(s) TMUX_TPREIINS[1:3] are programmed to 1, then one error is inserted into the G1 byte for that

particular STS-1(s) each time the microprocessor interface block SMPR_BER_INSRT (Table 75 on page 68) bit is

asserted.

The TMU X pro v id es a p ro t ec t io n s w it ch MU X fo r R E I- P i nsertio n. T h e M UX i s con tr ol l e d by TMUX_TP R EI RD I SE L

(Table 117 on page 105). If TMUX_TPREIRDISEL = 1, then the REI-P value for insertion is taken from the value

on the protection board rather than from the receive side of the same TMUX.

G1 Triggers

Bit 3 Bit 2 Bit 1

0 0 0 No defects (nonenhanced RDI-P mode).

0 0 1 No defects (enhanced RDI-P mode).

0 1 0 LCD-P, PLM-P (LCD-P not supported in Supermapper).

0 1 1 No defects (nonenhanced RDI-P mode).

1 0 0 AIS-P, LOP-P (nonenhanced RDI-P mode).

1 0 1 AIS-P, LOP-P (enhanced RDI-P mode).

1 1 0 TIM-P, UNEQ-P (enhanced RDI-P mode).

1 1 1 AIS-P, LOP-P (nonenhanced RDI-P mode).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

397Agere Systems Inc.

17 TMUX Functional Description (continued)

17.6.10 F2 Byte Insert

When TMUX_THSF2INS = 1 (Table 118 on page 107), the value in TMUX_TF2INS[1—3][7:0] (Table 124 on

page 112) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when

TMUX_TPOAC_F2 = 1 (Table 128 on page 117). If both TMUX_THSF2INS and TMUX_TPOAC_F2 = 0, then the

value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77 on page 70)

bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.11 H4 Insert Control

A 4-byte sequence (0, 1, 2, and 3) will be inserted into the outgoing H4 bytes. Note that the assertion of pin TLSV1

(pin AB3) occurs after the J1 byte(s) during the frame where the H4 count equals one.

17.6.12 F3 Byte Insert

When TMUX_THSF3INS = 1 (Table 118), the value in TMUX_TF3INS[1—3][7:0] (Table 124 on page 112) is

inse rte d into the outg oin g signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_F3 = 1

(Table 128 on page 117). If both TMUX_THSF3INS and TMUX_TPOAC_F3 = 0, then the value inserted depends

on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77 on page 70) bit. If

SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.13 K3 Byte Insert

When TMUX_THSK3INS = 1 (Table 118 on page 107), the value in TMUX_TK3INS[1—3][7:0] (Table 124) is

inse rte d into the outg oin g signal. Otherwise, the associated POAC value is inserted when TMUX_TPOAC_K3 = 1

(Table 128 on page 117). If both TMUX_THSK3INS and TMUX_TPOAC_K3 = 0, then the value inserted depends

on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77 on page 70) bit. If

SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.14 N1 Byte Insert

When TMUX_THSN1INS = 1 (Table 118 on page 107), the value in TMUX_TN1INS[1—3][7:0] (Table 124 on

page 112) is inserted into the outgoing signal. Otherwise, the associated POAC value is inserted when

TMUX_TPOAC_N1 = 1 (Table 128). If both TMUX_THSN1INS and TMUX_TPOAC_N1 = 0, then the value

inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77 on page 70) bit. If

SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.15 MSP 1 + 1 Payload Switch

For the working transmit high-speed data output (THSDP/N, pins AF9/AE9), it is possible to select the normal

transmit path low-speed data by setting TMUX_TPSMUXSEL2 = 0 (Table 116 on page 105), or the receive-side

protection input data by setting TMUX_TPSMUXSEL2 = 1. Note that if the receive-side protection input is selected,

then the local clock and frame sync are generated based on the receive-side protection inputs as well.

To create the transmit high-speed protection outputs (TPSD155P/N and TPSC155P/N; pins AF13/AE13 and

AC12/AD13), it is possible to select the normal transmit path low-speed input data with TMUX_TPSMUXSEL3 = 0

(Table 116 on page 105) or the receive-side working inputs with TMUX_TPSMUXSEL3 = 1.

Note: Clocks and timing signals are selected by TMUX_TPSMUXSEL3 as well as the parallel data.

17.6.16 Transmit Transport Overhead Access Channel (TTOAC)

The TMUX provides a transmit transport overhead access channel (TTOAC) to provision the TOH portion of the

outgoing frame. The TTOAC channel supports three modes of operation based on values in

TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE (Table 127 on page 115).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

398 Agere Systems Inc.

17 TMUX Functional Description (continued)

The TTOAC channel consists of the following signals:

■A data signal received by the TMUX in the transmit direction (TTOACDATA, pin AE2). The data bytes per frame

received depend on the values of TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 545.

■A clock signal sourced by the TMUX (TTOACCLK, pin AB6). The clock frequency depends on the values of

TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See Table 545.

■An 8 kHz synchronization signal (TTOACSYNC, pin AF3) is sourced by the TMUX. This sync signal is normally

low; during the last clock period of each frame, coincident with the least significant bit of the last byte, the sync

signal is high.

Table 545. Transmit TOAC Modes

Transmit TOAC—DCC1 Through DCC3 Mode. In this mode, DCC bytes 1 to 3 are received serially on the data

pin. The clock rate is 192 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC1,

DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes. The frame repetition rate is 8 kHz.

Transmit TOAC—DCC4 Through DCC12 Mode. In this mode, DCC bytes 4 to 12 are received serially on the

data output. The clock rate is 576 kHz. The data bytes are received MSB first, and the sequence of data bytes is

DCC4, DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into

frames of 9 bytes. The frame repetition rate is 8 kHz.

Transmit TOAC—Full TOH Access Mode. In this mode, where TMUX_TTOAC_D13MODE = 0 and

TMUX_TTOAC_D412MODE = 0 (Table 127 on page 115 ), the data signal (TTOACDATA, pin AE2) is partitioned

into frames of 81 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/

received most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the

648 bits of the previous frame. The remaining 7 bits of this byte are not specified.

Bytes shown in Table 546 summarize the access capabilities of the transmit TOAC. This table describes the possi-

ble bytes in the outgoing frame that can be provisioned from the values on the TOAC channel. There are additional

mode bits described in Table 547 that must be programmed to allow insertion from the TOAC channel. Bytes indi-

cated in bold type below are not specified in the standard, but are available for insertion into the outgoing frame via

the registe r bit TMUX_T TOAC_AVAIL (Table 127 on page 115). An X in Table 546 indicates bytes that are don’t

cares; the values of these bytes in the outgoing transmit frame are not related to the values on the TTOAC chan-

nel.

Table 546. Transmit Transport Overhead Byte Full Access Mode

TOAC Mode TMUX_TTOAC_D13MODE

Value TMUX_TTOAC_D412MODE

Value Data Bytes

per Frame Clock Rate

DCC1—DCC3 1 X 3 192 kHz

DCC4—DCC12 0 1 9 576 kHz

Full TOH mode 0 0 81 5.184 MHz

OH ParityXXXXXXXX

XB1-2 B1-3 E1 E1-2 E1-3 F1 F1-2 F1-3

D1 D1-2 D1-3 D2 D2-2 D2-3 D3 D3-2 D3-3

XXXXXXXXX

XXXXK1-2K1-3XK2-2K2-3

D4 D4-2 D4-3 D5 D5-2 D5-3 D6 D6-2 D6-3

D7 D7-2 D7-3 D8 D8-2 D8-3 D9 D9-2 D9-3

D10 D10-2 D10-3 D11 D11-2 D11-3 D12 D12-2 D12-3

S1 Z1-2 Z1-3 Z2 Z2-2 X E2 E2-2 E2-3

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

399Agere Systems Inc.

17 TMUX Functional Description (continued)

Table 547 summarizes the insertion options for the specified overhead bytes for TOAC in full TOH access mode.

The TMUX allows a default value (all zeros if microprocessor interface block SMPR_OH_DEFLT = 0 (Table 77 on

page 70), and all ones if SMPR_OH_DEFLT = 1) to be inserted on the corresponding TOAC value. All control sig-

nals are active-high.

Table 547. TTOAC Control Bits in Full Access Mode

An event indication must be provided to indicate parity errors for the TOAC channel. Odd or even parity is checked

depending on TMUX_TTOAC_OEPMON (Table 127 on page 115); 0 selects odd parity and 1 selects even parity.

A parity error is reported in status register bit TMUX_TTOAC_PE (Table 90 on page 80), and the interrupt is

maskable with TMUX_TTOAC_PM (Table 94 on page 89).

17.6.17 Sync Status Byte (S1) Insert

When TMUX_THSS1INS = 1 (Table 117 on page 105), the value in TMUX_TS1INS[7:0] (Table 122 on page 112)

is inserted into the S1 byte of the outgoing signal; otherwise, the associated TOAC value is inserted when

TMUX_TTOAC_S1 = 1 (Table 127 on page 115). If both TMUX_THSS1INS and TMUX_TTOAC_S1 are a logic 0,

then the value inserted depends on the value of the microprocessor interface block SMPR_OH_DEFLT (Table 77

on page 70) bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are

inserted.

17.6.18 REI-L: M1 Insert

For STS-3/STM-1 modes, the M1 byte is allocated for use as a line remote error indication (REI). For STS-1, bits 0

to 3 of the M0 byte are used. The M0 or M1 bytes convey the count of interleaved bit blocks that have been

detected in error by the line BIP-8 (B2) detector on the received signal.

This function can be inhibited by asserting TMUX_THSLREIINH (Table 117 on page 105). A bit error in the M0/M1

byte can be inserted under user control. When TMUX_TLREIINS (Tab le 125 on page 114 ) is asserted, the corre-

sponding M0 or M1 byte will indicate one error each time the microprocessor interface block SMPR_BER_INSRT

(Table 75 on page 68 ) bit is asserted.

The TMUX provides a protection switch MUX for REI-L insertion, controlled by TMUX_TLREIRDISEL (Table 117

on page 105). If TMUX_TLREIRDISEL = 1, then the REI-L value for insertion is taken from the value on the protec-

tion board rather than from the receive side of the same TMUX.

Overhead Bytes Register Control Bits Value of the Register Control Bits

0 (Default Value) 1

E1 TMU X_T TO AC_ E1 (Table 1 27 on page 115)SMPR_OH_DEFLT

(00000000 or 11111111) TOAC Data

F1 TMUX_TTOAC_F1 (Table 127)

D1—D3 TMUX_TTOAC_D1TO3 (Table 127)

D4—D12 TMUX_TTOAC_D4T O12 (Table 127)

S1 TMU X_T TO AC_ S1 (Table 127)

E2 TMU X_T TO AC_ E2 (Table 127)

All remai n ing b yte s in

Table 546 TMUX_TTOAC_AVAIL (Table 127)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

400 Agere Systems Inc.

17 TMUX Functional Description (continued)

17.6.19 APS Value and K2 Insert Control Parameters

When TMUX_THSAPSINS = 1 (Table 117 on page 105), the K1 byte and the five most significant bits of the K2

byte are written from TMUX_TAPSINS[12:0] (Table 123 on page 112). When TMUX_THSAPSINS = 0, either all

zeros or all ones will be written, depending on the value of microprocessor interface block SMPR_OH_DEFLT

(Table 77 on page 70) bit.

An APS babbling test is controlled with TMUX_TAPSBABINS (Table 126 on page 115). Setting

TMUX_TAPSBABINS = 1 forces the K1[7:0], K2[7:3) to an inconsistent state; no three consecutive values are con-

tinuou sl y the sam e.

When the transmit K2 software insert bit TMUX_THSK2INS = 1 (Table 117 on page 105), data from bits

TMUX_TK2INS[2:0] (Table 123 on page 112) is written into the K2[2:0] output bits. When TMUX_THSK2INS = 0,

hardware insertion of RDI-L is enabled.

17.6.20 Criteria for Insert Line RDI

Hardware insertion of line RDI is generated using the following equation. Each defect contribution to line RDI can

be individ ual ly inhi bit ed.

(TMUX_RHLOC AND TMUX_ TRILOC_L RDIINH ) OR

(TMUX_RHSLOS AND TMUX_TRLOS_LRDIINH) OR

(TMUX_RHSLOF AND TMUX_TRLOF_LRDIINH) OR

(TMUX_RHSOOF AND TMUX_TROOF_LRDIINH) OR

(TMUX_RLAISMON AND TMUX_TRLAISMON_LRDIINH) OR

(TMUX_RHSSF AND TMUX_TRSF_LRDIINH) OR

(TMUX_RHSSD AND TMUX_TRSD_LRDIINH)

When a failure condition exists that will cause RDI-L to be generated, the generation of RDI-L must last for at least

20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.

The TMUX provides a protection switch MUX for RDI-L insertion. The MUX is controlled by TMUX_TLREIRDISEL

(Table 117 on page 105). If TMUX_TLREIRDISEL = 1, then the RDI-L value for insertion is taken from the value on

the protection board rather than from the receive side of the same TMUX.

17.6.21 Line AIS Generation

Line AIS is specified as all ones in the entire STS/STM signal before scrambling, excluding the section overhead.

Line AIS can be generated by setting TMUX_THSLAISINS = 1 (Table 117 on page 105).

17.6.22 B2 BIP-8 Calculation and Insert

The B2 byte is allocated for a line overhead error monitoring function. This function will be a bit interleaved parity-8

code (BIP-8) using even parity. The BIP-8 is computed before scrambling, over all the bits of the previous STS-1

frame (except for the 9 bytes of section overhead) and is placed in byte B2 of the current frame also before scram-

bling.

A bit error rate can be inserted on any B2 byte. When bit(s) TMUX_THSB2ERRINS[1—3] (Table 125 on page 114)

is (are) asserted, the corresponding B2 byte is inverted each time the microprocessor interface block

SMPR_BER_INSRT (Tab le 75 on page 68) bit is asserted.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

401Agere Systems Inc.

17 TMUX Functional Description (continued)

17.6.23 F1 Byte Insert

When TMUX_THSF1INS = 1 (Table 117 on page 105), the value in TMUX_TF1INS[7:0] (Table 122 on page 112)

is inserted into the F1 byte of the outgoing signal. Otherwise, the associated TOAC value is inserted when

TMUX_TTOAC_F1 = 1 (Table 127 on page 115). If both TMUX_THSF1INS and TMUX_TTOAC_F1 = 0, then the

value inserted depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77 on page 70)

bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.24 B1 Generate and Error Insert

The section bit interleaved parity code (BIP-8) byte (even parity) is used to check for transmission errors over a

section. Its value is calculated over all bits in the previous frame after scrambling and placed in the B1 byte of time

slot 1 before scrambling.

A bit error rate can be inserted on the B1 byte. When TMUX_THSB1ERRINS = 1 (Table 125 on page 114), the B1

byte is inverted each time the microprocessor interface block SMPR_BER_INSRT (Table 75 on page 68) bit is

asserted.

17.6.25 Scrambler

The outgoing frame will be scrambled with the frame synchronous scrambler of length 127 and generating polyno-

mial x7 + x6 + 1. The entire STS/STM signal will be scrambled except for the first row of overhead. The scrambler

will be set to 1111111 on the first byte following the last overhead byte in the first row.

For test purposes, the scrambler will be disabled when TMUX_THSSCR = 0 (Table 116 on page 105).

17.6.26 J0 Inser t Control

A 16-byte sequence stored in TMUX_TJ0DINS[1—16][7:0] (Table 143 on page 123) will be inserted into the outgo-

ing J0 byte if TMUX_THSJ0INS = 1 (Table 117 on page 105). If TMUX_THSJ0INS = 0, then the value inserted

depends on the value of microprocessor interface block SMPR_OH_DEFLT (Table 77) bit. If SMPR_OH_DEFLT =

0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.

17.6.27 Z0-2, Z0-3 Insert Control

The two bytes, Z0-2 and Z0-3, that follow J0 are not scrambled. If TMUX_THSZ0INS = 1 (Table 117), then the val-

ue s s t ored in TM UX_TZ0 2I NS [ 7 :0] ( Table 121 on page 1 12) and TMUX_TZ03INS[7:0] (Table 121) will be inserted.

If TMUX_THSZ0INS = 0, then the value inserted depends on the value of microprocessor interface block

SMPR_OH_DEFLT bit. If SMPR_OH_DEFLT = 0, then all zeros are inserted. If SMPR_OH_DEFLT = 1, then all

ones are inse r ted.

17.6.28 A2 Error Insert

The TMUX allows, under software control, from 1 to 32 continuous frames to have an inverted A2-1 (0x28 to 0xD7)

pattern in the outgoing frame. The value in TMUX_TA2ERRINS[4:0] (Table 116) specifies the number of frames to

insert errors while assertion of microprocessor interface block, SMPR_BER_INSRT bit, starts the error insertion

process.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

402 Agere Systems Inc.

18 SPE Mapper Functional Description

Table of Con t ents

Contents Page

18 SPE Mapper Functional Description ...............................................................................................................402

18.1 Introduction...............................................................................................................................................404

18.2 Features...................................................................................................................................................404

18.3 SPE Mapper Functional Block Diagrams.................................................................................................405

18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)...............................................408

18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standard-Based Systems)...............................................408

18.6 DS3 to AU-3/STS-1 SPE Mapping (Used in Telcordia/ANSI Standards-Based Systems).......................409

18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standards-Based Systems).................................................409

18.8 SPE Mapper Basic Configuration.............................................................................................................409

18.9 DS3 Configuration....................................................................................................................................409

18.9.1 D S3 M13 .................. ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... .................... ...... ........................... 410

18.9.2 D S3 Loopbac k Channe l ........ ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... .................... 410

18.9.3 DS3 Clear Channel from External Pins ......................................................................................... 410

18.10 Phase Dete ctor for External DS3 PLL.............. ....... ...... ....... ...... ...... ....... ...... .................... ...... ...............410

18.11 Serial STS-1 SPE Channel (NSMI)........................................................................................................411

18.12 TMUX Interface to the SPE Mapper.......................................................................................................412

18.13 PATH Termination Block........................................................................................................................412

18.13.1 Pointer Interpretation Block ........................................................................................................ 413

18.14 SPE Mapper Receive Direction Requirements ......................................................................................416

18.14.1 Loss of Clock and Loss of Sync Monitors ................................................................................... 417

18.14.2 J1 Monitor ................................................................................................................................... 417

18.14.3 B3 BIP-8 Check .......................................................................................................................... 418

18.14.4 Signal Label C2 Byte Monitor ..................................................................................................... 418

18.14.5 Path User Byte F2 Monitor .......................................................................................................... 419

18.14.6 Path User Byte F3 Monitor .......................................................................................................... 420

18.14.7 N1 Monitor .................................................................................................................................. 420

18.14.8 K3 Byte Monitor .......................................................................................................................... 421

18.14.9 AIS-P and RDI-P Detect ............................................................................................................. 421

18.14.10 REI-P Detect ............................................................................................................................. 422

18.14.11 Signal Degrade BER Algorithm ................................................................................................. 422

18.14.12 Signal Fail BER Algorithm ......................................................................................................... 423

18.14.13 POAC Drop ............................................................................................................................... 424

18.14.14 Insertion of AIS-P ...................................................................................................................... 425

18.15 Transmit Direction (to SONET/SDH Line)..............................................................................................426

18.15.1 PATH Insertion Block .................................................................................................................. 426

18.15.2 Loss of Clock and Loss of Sync Detectors ................................................................................. 427

18.15.3 J1 Byte Insert .............................................................................................................................. 427

18.15.4 B3 BIP-8 Calculation and Insert .................................................................................................. 427

18.15.5 C2 Signal Label Byte Insert ........................................................................................................ 427

18.15.6 REI-P G1(7:4) Insert ................................................................................................................... 427

18.15.7 Path RDI (RDI-P) Insert .............................................................................................................. 428

18.15.8 F2 Byte Insert ............................................................................................................................. 428

18.15.9 H4 Insert Control ......................................................................................................................... 428

18.15.10 F3 Byte Insert ........................................................................................................................... 428

18.15.11 K3 Insert Control Parameters ................................................................................................... 429

18.15.12 N1 Insert Control Parameters ................................................................................................... 429

18.16 POAC Insert...........................................................................................................................................429

18.17 AIS Path Generation ..............................................................................................................................430

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

403Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table of Conten ts (continued)

Figures Page

Figure 31. SPE Mapper Block with Connections to External Pins and Other Blocks in the Device ......................405

Figure 32. Basic Functional Flow of the SPE Mapper Transmit Section...............................................................404

Figure 33. Basic Functional Flow of the SPE Mapper Receive Section................................................................407

Figure 34. STS-1 NSMI Receive Operation ..........................................................................................................411

Figure 35. STS-1 NSMI Transmit Operation .........................................................................................................412

Figure 36. Receive Direction Path Termination Block...........................................................................................413

Figure 37. Pointer Interpretation State Diagram....................................................................................................414

Figure 38. Transmit Direction Path Insertion Block...............................................................................................426

Tables Page

Table 548. J1 Monitor ............................................................................................................................................418

Table 549. STS Signal Label Defect Conditions....................................................................................................418

Table 550. C2MON Processing .............................................................................................................................419

Table 551. F2 Monitor............................................................................................................................................420

Table 552. F3 Monitor............................................................................................................................................420

Table 553. N1 Monitor ...........................................................................................................................................420

Table 554. K3 Monitor............................................................................................................................................421

Table 555. AIS-P and RDI-P Detect ......................................................................................................................421

Table 556. STS-1 P-REI Interpretation..................................................................................................................422

Table 557. Signal Degrade Parameters.................................................................................................................423

Table 558. Signal Fail Parameters.........................................................................................................................424

Table 559. Path Overhead Byte Access................................................................................................................425

Table 560. RDI-P Defects for Enhanced RDI-P Mode...........................................................................................428

Table 561. Path Overhead Byte Access—Transmit Direction ...............................................................................429

Table 562. TPOAC Control Bits ............................................................................................................................430

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

404 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.1 Introducti on

This section describes the functions of the SPE mapper block.

The SPE mapper is highly configurable; it can operate in two different modes: as an AU-3/STS-1 mapper or as a

TUG-3 mapper. In both modes, it can map/demap data from/to either the VT mapper block, the M13 MUX/deMUX

block, the DS3 clear channel, or the DS3 loopback channel.

The SPE mapper supports numerous automatic monitoring functions. It can provide interrupts to the control sys-

tem, or it can be operated in a polled mode.

Additionally, this block has a built-in auxiliary channel known as the path overhead access channel (POAC). This

channel is mainly used for path overhead insertion and drop functions.

18.2 Features

■The SPE mapper accepts/delivers TUG-2 data from/to the VT mapper. The TUG-2 data is mapped/demapped

either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the

European digital systems.

■Flexibility down to TUG-2 level is provided for choosing which TUG-2s (between 1 and 7) are mapped into which

TUG-3s (between 1 and 3) for generating STM-1 signals. Similarly, any TUG-2s (up to 7) may be dropped/termi-

nated from the 21 TUG-2s of an STM-1 signal.

■The SPE mapper accepts/delivers DS3 data from/to the M13 MUX/deMUX. The DS3 data is mapped/demapped

either to/from an AU-3/STS-1 signal for the North American digital systems or to/from a TUG-3 signal for the

European digital systems.

■The SPE mapper accepts/delivers a clear DS3 signal at 44.736 Mbits/s rate. The clear DS3 signal is mapped/

demapped essentially the same way as the M13 signal described above.

■The SPE mapper has a DS3 loopback circuit placed for the functions of demapping and remapping a DS3 signal.

It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to be remapped

as a TUG-3 signal, or vice versa.

■The SPE mapper supports a path overhead access channel more commonly known as the POAC channel.

Seven path overhead bytes, namely J1, C2, F2, H4, F3, K3, and N1 may be inserted/dropped through this chan-

nel. This channel works as the master, which means that this channel provides a clock in both transmit and

receive directions, and POH data may be inserted by the user on the transmit side or dropped by the block in the

receive side.

■Path overhead byte B3 (BIP error) generation/detection and programmable BIP-2 bit error rate insertion.

■Programmable clear on read/clear on write registers.

■Signal fail and signal degrade indicators available to report bit error rates above a certain programmable thresh-

old.

■Capable of detecting/inserting alarm indication signals (AIS), remote defect indication signals (RDI) and remote

error indication signals (REI).

■Numerous monitoring functions provided on all the TUG-3 path overhead bytes.

■Supports unidirectional path switch ring (UPSR) applications.

■N1 tandem connection support is provided.

■Complies with GR-253-CORE, T1.105, ITU-T G.707, ITU-T G.831, G.783, ETS 300 417-1-1.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

405Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.3 SPE Mapper Functional Block Diagrams

5-9065(F)

Figure 31. SPE Mapper Block with Connections to External Pins and Other Blocks in the Device

MICRO INTERFACE

SPE MAPPER

DS3DATAINCLK

DS3DATAOUTCLK

DS3NEGDATAIN

PHASEDETUP

PHASEDETDOWN

DS3NEGDATAOUT

AUTO_AIS,

TPOAC

DS3POSDATAOUT

DS3POSDATAIN

REI DS3

AUTO_AIS

DATA, CLK, SYNC

TRANSMIT

RECEIVE

TELECOM

BUS

CLK, DATA

RPOAC

TRANSMIT

RECEIVE

CLK, DATA

TRANSMIT RECEIVE

TRANSMIT

PATH OVERHEAD

INSERT

POAC CHANNEL

TELECOM

BUS

RDI, REI

MAPPER

TRANSMIT

SECTION

MAPPER

RECEIVE

SECTION

M13

MAPPER

TRANSMIT

SECTION

M13

MAPPER

RECEIVE

SECTION

DS3

CLEAR INPUT

TRANSMIT

PINS

DS3

CLEAR INPUT

RECEIVE

PINS

RECEIVE

PATH OVERHEAD

EXTRACT

POAC CHANNEL

TMUX

RECEIVE

SECTION

TMUX

TRANSMIT

SECTION

DATA, CLK, SYNC

DATA, CLK,

CONTROL

DATA, CLK,

CONTROL

LOOPBACKRDI

TRANSMIT

SECTION

SPE MAPPER

RECEIVE

SECTION

MISC SIGNALS

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

406 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9066(F)

Figure 32. Basic Functional Flow of the SP E Mapper Transmit Section

TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)

TO/FROM TMUX TRANSMIT SIDE

DS3 _EXT_CLK

DS3 POS_DATA

51.84 MHz CLOCK FROM TMUX

51.84 MHz CLOCK, CONTROL FROM TMUX

B3ZS

M13

DS3 DATA

DS3 CLK

DS3 CLK_EN

DS3 INPUT CONTROL &

VT/TU

FIFO

DS3

TUG-2

PATH

TUG-2_DATA

SYNC_V1

CLK_6MHz

MUX

TUG-3 MAPPER

AU-3 MAPPER

MUX

TUG-3 OR AU-3

MUX

MICRO-

C-3

TUG-2

MUX

LOOPBACK_CLK

LOOPBACK_DATA

TX_POACDATA

TX_POACSYNC

TX_POACINH

TX_POACCLKO

PATH OVERHEAD

LOOPBACK_CLK_EN

DS3 NEG_DATA

STS3_TIME SLOT

AU3_TUG3

VT_DS3

AU3_TUG3

VT_DS3

TDS3_BIPOLAR

DS3_SRC_TYPE

VT_DS3

84 x 9 bytes

84 x 9

85 x 9 bytes

87 x 9 bytes

87 x 9 bytes 87 x 9 bytes

TU11_TU12

TUG2_NO[2:0]

TUG3_NO[1:0]

AU3_TUG3

VT_DS3

MPUCLKDS3CLK

TELECOM BUS

OUTPUT (87 x 9 bytes)

CONTROL CIRCUITRY

ADD 1 COLUMN

OF FIXED STUFFING &

TU-3 PTR BYTES

ADD 2 COLUMNS

OF FIXED STUFFING

OVERHEAD

INSERTION

INSERT

POAC CHANNEL

MAPPERMAPPER

DECODE

SERIAL-TO-PARALLEL

CONVERSION INPUT

CONTROL

MAPPED AS

CONTAINER C-3

INTERFACE

CLOCK

bytes

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

407Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9067(F)r.1

Figure 33. Basic Functional Flow of the SP E Mapper Receive Section

TELECOM BUS DATA[7:0], CLOCK, PARITY, SYNC (19.44 MHz OR 6.48 MHz)

FROM TMUX RECEIVE SIDE

DS3 _EXT_CLK

DS3 POS_DATA

51.84 MHz CLOCK, CONTROL FROM TMUX

AUTO AIS SIGNAL FROM TMUX

B3ZS

M13

DS3 DATA

DS3 CLK

DS3 CLK_EN

DS3 OUTPUT CONTROL &

VT/TU

FIFO

C-3

TUG-2

PATH

TUG-2_DATA

SYNC_V1

CLK_6MHz

TUG-3 DEMAPPER

AU-3 DEMAPPER

TUG-3 OR AU-3

MICRO

C-3

TUG-2

RX_POACSYNCO

RX_POACCINH

RX_POACSINH

RX_POACDATAO

PATH OVERH EAD

DS3 NEG_DATA

STS3_TIME SLOT

VT_DS3

AU3_TUG3

VT_DS3

DS3CLK

VT_DS3

84 x 9 bytes

84 x 9

85 x 9 byte s

87 x 9 bytes 87 x 9 bytes

TU11_TU12

TUG2_NO[2:0]

TUG3_NO[1:0] AU3_TUG3

VT_DS3

TELECOM BUS

INPUT (87 x 9 BYTES)

CONTROL CIRCUITRY

REMOVE 1 COLUMN

OF FIXED STUFFING &

TU-3 PTR BYTES

REMOVE 2 COLUMNS

OF FIXED STUFFING

OVERHEAD

EXTRACTION/

EXTRACT

POAC CHANNEL

DEMAPPER

ENCODER

PARALLEL-TO-SERIAL

CONVERSION OUTPUT

CONTROL

DE MAPPED AS

AS DS3

INTERFACE

CLOCK

bytes

DS3

TERMINATION

POINTER

INTERPRETER

MUX

85 x 9 bytes

VT_DS3

RX_POACCLKO

RX_POACDINH

85 x 9 bytes

VC-3

DS3_OUT_TYPE

DS3_BIPOLAR

PHASE_DET_UP

PHASE_DET_DOWN

DS3 _LOOPBACK_DATA

DS3 _LOOPBACK_CLK

LOOPBACK_CLK_EN

TUG3MPR_DS3_AIS

MPUCLK

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

408 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

The SPE mapper basically interfaces to three other blocks within the Supermapper device:

■The VT mapper.

■ The M13 MUX/deMUX.

■ The TMUX.

The interface between the SPE mapper and the VT mapper consists of clock, parallel data, sync, and control type

interfaces and is completely internal to the Supermapper device.

The interface between the SPE mapper and the M13 MUX/deMUX consists of a serial clock, serial data, and clock

enable type interface and is also completely internal to the Supermapper device.

The interface between the SPE mapper and the TMUX consists of the telecom bus, and every signal that flows

between these two blocks is also brought in/out through external device pins connected to the telecom bus.

As outlined in the features, the SPE mapper can map/demap seven TUG-2 or a DS3 to/from AU3/STS-1 or TUG-3.

Each TUG-2 assembled/disassembled by the VT mapper consists of three TU-12 (E1) or four TU-11 (DS1) virtual

tributaries.

The following is a brief description of the supported standards based mappings. For greater details, please refer to

the appropriate standard.

18.4 TUG-2 to AU-3/STS-1 SPE Mapping (Used in North American Systems)

A TUG-2 payload capacity, which is 9 rows by 12 columns or 108 bytes, may contain four TU-11s or three TU-12s

byte interleavingly multiplexed.

The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STS-1 frame of 125 µs. Four TU-11s

are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure

of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly

distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete

STS-1 SPE frame of 9 rows by 87 columns.

The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STS-1 frame of 125 µs. Three TU-12s

are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a VC-3. The VC-3 has a structure

of 9 rows by 85 columns: one column is VC-3 path overhead and the other 84 columns are seven TUG-2s evenly

distributed within the payload. Two columns of fixed stuffing are then added to the payload to build the complete

STS-1 SPE frame of 9 rows by 87 columns.

18.5 TUG-2 to TUG-3 Mapping (Used in ITU/ETSI Standar d-Bas ed Systems)

A TUG-2 payload capacity, which is 9 rows by 12 columns or 108 bytes, may contain four TU-11s or three

TU-12s byte interleavingly multiplexed.

The 27-byte capacity of a TU-11 is equivalent to three-column capacity in an STM-1 frame of 125 µs. Four TU-11s

are byte interleavingly multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3. The TUG-3 has a struc-

ture of 9 rows by 86 columns: one column of NPI (null pointer indication) plus fixed stuffing bytes, one column of

fixed stuffing, and the other 84 columns are seven TUG-2s evenly distributed within the TUG-3 payload.

The 36-byte capacity of a TU-12 is equivalent to four-column capacity in an STM-1 frame of 125 µs. Three TU-12s

are byte interleaving multiplexed into a TUG-2 payload capacity which has a capacity of 12 columns. Seven

TUG-2s can then be byte interleavingly multiplexed into the payload capacity of a TUG-3.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

409Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

The TUG-3 has a structure of 9 rows by 86 columns: one column of null pointer indication (NPI) plus fixed stuffing

bytes, one column of fixed stuffing, and the other 84 columns are seven TUG-2s evenly distributed within the

TUG-3 payload.

18.6 DS3 to AU-3/STS- 1 SPE Mapping (Used in Telcordia/ANSI Standards-Based Systems)

DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total

3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s) which occupies 84 columns of an STS-1 frame.

One column of path overhead bytes is added to the C-3 container to make a VC-3. Finally, two columns of fixed

stuffing (column numbers 30 and 59) are added to VC-3 to form an STS-1 SPE (87 columns).

Stuffing (S bits) is used to rate adapt the DS3 payload to the SPE. Nine stuffing S bits are included in the C-3 con-

tainer. When no stuffing is used, the STS-1 SPE can accommodate a rate of 44.712 Mbits/s. When all 9 stuffing

S bits are used, the STS-1 SPE can accommodate 44.784 Mbits/s. Since the DS3 coming from the M13 has a

nominal rate of 44.736 Mbits/s, stuffing is used for every third row of an STS-1 frame; or, in other words, three S

bits per 125 µs are used for stuffing to achieve the DS3 rate.

18.7 DS3 to TUG-3 Mapping (Used in ITU/ETSI Standards-Based Systems)

DS3 is an asynchronous signal with a rate of 44.736 Mbits/s. This payload with other information bits (total

3.648 Mbits/s) is used to form the container C-3 (48.384 Mbits/s), which occupies 84 columns of an STM-1 frame.

One column of path overhead bytes are added to the C-3 container to make a VC-3 (85 columns). Now a TUG-3

signal consists of 86 columns by 9 rows; therefore, 3 bytes of TU-3 pointer (H1, H2, and H3 bytes) are placed on

rows 1 through 3 of the newly added column and fixed stuffing bits are placed on the remaining rows. Thus, a

TUG-3 frame of 9 rows by 86 columns is formed. Three TUG-3s are byte interleavingly multiplexed by the TMUX to

form an STM-1 signal.

Stuffing (S bits) is used to rate adapt the DS3 payload to the TUG-3. Nine stuffing S bits are included in the C-3

container. When no stuffing is used, the TUG-3 payload can accommodate a rate of 44.712 Mbits/s. When all 9

stuffing S bits are used, the TUG-3 payload can accommodate 44.784 Mbits/s. Since the DS3 coming from the

M13 has a nominal rate of 44.736 Mbits/s, stuffing is used for every third row of a TUG-3 frame; or, in other words,

three S bits per 125 µs are used for stuffing to achieve the DS3 rate.

18.8 SPE Mapper Basic Configuration

SPE mapper configuration programming is provided through registers SPE_MAP_CTL1—SPE_MAP_CTL3

(Table 163 on page 143).

When mapping to an STS-3/STM-1 rate, the SPE mapper requires configuration to select one of the three time

slots on the telecom bus that interfaces the TMUX. The register bits for selection are SPE_TSTS3TMSLOT[1:0]

and SPE_RSTS3TMSLOT[1:0] (Table 163).

Selection of AU-3/STS-1 or TUG-3 mapping is provided through bits SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3

(Table 163).

TUG-2 (virtual tributary) or DS3 data is selected with bits SPE_T_AU3_TUG3 and SPE_R_AU3_TUG3.

18.9 DS3 Configuration

The SPE mapper is configured to select the source and destination of the DS3 signals. The configuration is deter-

mined with register bits SPE_TDS3SRCTYP[1:0] and SPE_RDS3OUTTYP[1:0] (Table 163). DS3 source/destina-

tion may be selected as loopback, external device pins, or M13.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

410 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.9.1 DS3 M13

The SPE mapper is configured to/from the M13 MUX/deMUX as the source/destination of data by setting bits

SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 00 or 01.

18.9.2 DS3 Loopback Channel

The DS3 loopback circuit is placed in the SPE mapper to allow demapping and remapping of a DS3 signal.

When SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 10, the SPE mapper extracts the asynchronous DS3

data and clock from the received payload. The recovered DS3 is looped back to the transmit path and either

mapped as AU-3/STS-1 SPE signal for the North American digital systems or mapped as TUG-3 for the European

digital systems. It is particularly useful in cases where a DS3 signal mapped as an AU-3/STS-1 signal is needed to

be remapped as a TUG-3 signal or vice versa.

18.9.3 DS3 Clear Channel from External Pins

The SPE mapper is configured for a DS3 signal at 44.736 MHz rate from external device pins by setting

SPE_TDS3SRCTYP[1:0] = SPE_RDS3OUTTYP[1:0] = 11.

The DS3 data can either be unipolar or bipolar. Unipolar data and clock is selected (device pins DS3POSDATAIN,

DS3DATAINCLK, DS3POSDATAOUT, and DS3DATAOUTCLK (pins M22, J22, R22, and N22, respectively)) when

bits SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 0 (Table 163 on page 143). Bipolar data and clock are

selected (device pins DS3POSDATAIN, DS3NEGDATAIN, DS3DATAINCLK, DS3POSDATAOUT,

DS3NEGDATAOUT, and DS3DATAOUTCLK (pins M22, K22, J22, R22, P22, and N22, respectively)) when bits

SPE_TDS3_BIPOLAR and SPE_RDS3_BIPOLAR = 1.

When bipolar data is selected for the transmit path (SPE_TDS3_BIPOLAR = 1), the data received from the exter-

nal pins is expected to be B3ZS encoded. A B3ZS decoder is used to recover the DS3 data prior to being mapped

into a container.

The B3ZS decoder also checks for bipolar coding violations. The SPE mapper contains a counter that increments

on each occurrence of a received bipolar coding violation (BPV). It also monitors the occurrence of excessive

zeros (EXZ), which is defined as any zero string length equal to or greater than three. These are part of the perfor-

mance monitoring counters that can be sampled and simultaneously reset. Their last sampled values are available

through SPE_BIPOL_CNT[23:0] and SPE_EXZ_CNT[23:0] (Table 170 on page 150).

When bipolar data is selected for the receive path (SPE_RDS3_BIPOLAR = 1), the data out from the external pins

will be B3ZS encoded. A single bipolar violation may be inserted in the data when SPE_BIPOL_ERR is asserted

(Table 155 on page 136).

The clock edge for sampling the transmit path data (device pin DS3DATAINCLK (pin J22)) is selected with

SPE_TDS3CLK_EDGE (Table 163 on page 143).

18.10 Phase Detector for Extern al DS3 PLL

The receive section of the SPE mapper has a phase detector circuit built inside the device. This phase detector cir-

cuit generates the necessary up and down signals (device pins PHASEDETUP and PHASEDETDOWN (pins V22

and U22, respectively)) for an external phase-lock loop (PLL) circuit to generate a smooth DS3 clock at

44.736 MHz rate.

The logic sense of the phase detector up and down outputs may be inverted with bits SPE_PHDETUP_INV

(Table 163 on page 143) and SPE_PHDETDN_INV, respectively.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

411Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.11 Serial STS-1 SPE Channel (NSMI)

The SPE mapper has the capability of accepting a clear serial STS-1 SPE signal at 51.84 MHz rate. The intent is to

map/demap the network serial multiplexed interface (NSMI) interface data.

The receive section of the SPE mapper outputs a serial data at 51.84 MHz rate, a clock enable signal inhibited dur-

ing overhead insertion times, and a sync signal whose position within the STS-1 frame is programmable to a cer-

tain extent (is programmable to occupy any STS-1 column position (numbers 0—89) within a fixed row (# 8)),

through bits SPE_R_NSMI_BIT[2:0] (Table 163 on page 143) and SPE_R_NSMI_COL[6:0] (Table 163).

The transmit section of the SPE mapper inputs serial data at 51.84 MHz rate, outputs a clock enable signal inhib-

ited during overhead insertion times and a sync signal whose position within the STS-1 frame is programmable to

a certain extent (is programmable to occupy any STS-1 column position (numbers 0—89) within a fixed row (#8)),

through bits SPE_T_NSMI_BIT[2:0] and SPE_T_NSMI_COL[6:0] (Table 163).

The STS-1 SPE data is then mapped as AU-3 signal for the North American digital systems.

0786(F)(F)

Figure 34. STS-1 NSMI Receive Operat ion

UNUSED

VARIABLE

LINE_RXCLK29

RXDATAEN

RXSYNC (OPTIONAL)

LINE_RXDATA29

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

412 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

0785(F)(F)

Figure 35. STS-1 NSMI Transmit Operation

18.12 TMUX Interface to the SPE Mapper

The SPE mapper sends/receives data mapped as an AU-3/STS-1 SPE signal or as a TUG-3 signal to/from the

TMUX. The interface required for this exchange of data, clock, and control signals is called the high-speed telecom

bus. The high-speed telecom bus is accessible from external pins so that the TMUX can send/receive data to/from

other external Supermapper devices in the system. The TMUX can byte interleavingly multiplex three STS-1s or

three TUG-3 signals, receiving through the telecom bus, to form one STS-3 or STM-1 signal, respectively.

The high-speed telecom bus consists of a byte-wide data bus running at 19.44 Mbits/s for STS-3/STM-1 mode, or

6.48 Mbits/s for STS-1 stand-alone mode. It also consists of a parity bit line, a clock line which is 19.44 MHz or

6.48 MHz depending on STS-3/STM-1 or STS-1 mode, respectively; one sync line and two sync control lines. The

sync line outputs the J0, J1, and V1 time-slot signals of the STS-3/STM-1 frame and the two sync control signals

distinguish between the three sync bytes. The sync signals are used to synchronize the byte counters in the SPE

mapper, and the information is also passed along to the VT mapper for synchronizing the V1 counters.

The TMUX also provides through the external pins one 51.84 MHz serial clock and 1 clock control signal which

synchronizes the 51.84 MHz to the J0 byte of the STS-3/STM-1 frame. This serial clock is required for the M13

MUX/deMUX because of its serial mode of working.

In the case where the SPE mapper has to drive the telecom bus in the transmit side, there is a 3-state control sig-

nal (active-high) which is an output from the SPE mapper . This signal enables the 3-state drivers on the high-speed

telecom bus at the time period when the clock is low.

18.13 PATH Termination Block

The path termination block of the SPE mapper is shown Figure 36. The block consists of a pointer interpreter which

monitors the TU-3 pointer bytes H1, H2, and H3, and interprets the beginning of the path overhead bytes for the

TUG-3 frames. After monitoring and terminating the path overhead bytes, the TUG-3 payload is passed on to the

output blocks.

UNUSED

VARIABLE

LINE_TXCLK29

TXDATAEN

TXSYNC (OPTIONAL)

LINE_TXDATA29

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

413Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9068(F)

Figure 36. Receive Direction Path Termination Block

18.13.1 Pointer Interpretation Block

The TUG-3 pointer interpreter logic block performs all necessary functions to support TU-3 pointer interpretation.

The following features are implemented:

■ The pointer interpreter consists of the following states:

— LOP-TU3—loss of pointer

— AIS-TU3—TUG-3-AIS (all ones in H1 and H2)

— NDF—NDF enabled (1001, 0001, 1101, 1011, 1000)

— NORM—normal (disabled NDF, normal pointer)

— INC—increment (inverted I bits)

— DEC—decrement (inverted D bits)

The SPE mapper includes event or change of state indicators for pointer interpreter states except the NORM state.

States NDF, DEC, and INC are reported with event status bits SPE_RNDFE (Table 156 on page 136),

SPE_RDECE (Table 156), and SPE_RINCE (Table 156), respectively. States AIS and LOP are reported with

change of state (delta) status bits SPE_RAISD (Table 156) and SPE_RLOPD (Table 156), respectively. Interrupts

for each event or delta state may be masked with bits SPE_RNDFM, SPE_RDECM, SPE_RINCM, SPE_RAISM,

and SPE_RLOPM (all in Table 157 on page 138).

INSERT

B3 K3 AIS-P G1

B3 K3 G1 G1N1C2

POAC G1

J1F3

H1, H2, H3 POINTER

PATH

POAC DAT A

TUG-3 DATA VC-3 DATA

TUG-2 DATA

PAYLOAD DATA TO OUTPU T BLOCKS

MUX

MONITOR INTERPRETER

MONITOR F3

MONITOR C2

MONITOR J1

MONITOR N1

MONITOR BIP N

CHECK APS

MONITOR RDI-P

DETECT REI-L

DETECT

AIS-P

TERMINATE

REI

COUNTER

DROP

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

414 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

5-9007(F)

* This state diagram is based on the ETS 417-1-1 pointer interpretation state diagram (Figure B.1). Transiti ons of eight invalid pointers from the

INC, DEC, and NDF states into the LOP state have been added.

Figure 37. Pointer Interpretation State Diagram

■The pointer interpreter transitions into the LOP-TU3 state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames

(determined by the value programmed in bits SPE_CNTDLOPCNT[1:0] (Table 159 on page 141)), then LOP-

TU3 is declared.

— Invalid pointer values. If the number of consecutive frames (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]) are received with a pointer that is not a normal value, NDF, AIS-TU3, increment, or

decrement, then LOP-TU3 is declared.

■ The pointer interpreter transitions out of the LOP-TU3 state based on the following conditions:

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the LOP-TU3 state into the AIS-TU3 state.

— Following three new, consecutive, consistent, valid pointers, the pointer interpreter transitions from the

LOP-TU3 state into the NORM state.

— The pointer interpreter will not transition from the LOP-TU3 state into the NDF state.

■ The pointer interpreter transitions into the AIS-TU3 state based on the following conditions:

— Following three consecutive frames with all ones in the H1 and H2 bytes, AIS-TU3 is declared.

■ The pointer interpreter transitions out of the AIS-TU3 state based on the following conditions:

— Following three new, consecutive, consistent, valid pointers, the pointer interpreter transitions from the AIS-

TU3 state into the NORM state.

— Following the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the AIS-TU3 state into the LOP-TU3 state.

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the AIS-TU3 state

into the NDF state.

NORM

DECINC

NDF

AISLOP

FROM ALL STATES

8 INVALID POINTERS

FROM ALL STAT ES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENAB L E

NDF ENABLE

NDF

3 ANY 3 ANY

3 NEW POINTERS

3 ANY POINTERS

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

415Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

■The pointer interpreter transitions into the NDF state based on the following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM, NDF,

AIS, INC, and DEC states into the NDF state.

■ The pointer interpreter transitions out of the NDF state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive frames

(determined by the value programmed in SPE_CNTDLOPCNT[1:0] (Table 159 on page 141)), the pointer in-

terpreter transitions from the NDF state into the LOP-TU3 state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the NDF

state into the NORM state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the NDF state into the AIS-TU3 state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the

NDF state into the NORM state.

— Following the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NDF state into the LOP-TU3 state.

■ The pointer interpreter transitions into the NORM state based on the following conditions:

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions into the

NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions into the

NORM state, i.e., transitioning from the INC, DEC, and NDF states.

■ The pointer interpreter transitions out of the NORM state based on the following conditions:

— Following the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the NORM state into the LOP-TU3 state.

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state

into the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the NORM state into the AIS-TU3 state.

— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 159 on page 141)), if 8 of the 10 I and

D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions

from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a

pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state

into the DEC state.

— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state

into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the

incoming H1 and H2 bytes, the pointer interpreter transitions from the NORM state into the INC state.

■ The pointer interpreter transitions into the INC state based on the following conditions:

— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a

pointer increment on the incoming H1 and H2 bytes, the pointer interpreter transitions into the INC state. Oth-

erwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming H1 and H2

bytes, the pointer interpreter transitions into the INC state.

■The pointer interpreter transitions out of the INC state based on the following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the INC state into

the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the INC state into the AIS-TU3 state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC

state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the INC

state into the NORM state.

— Following the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0] (Table 159 on page 141)), the pointer interpreter transitions from the INC state into

the LOP-TU3 state.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

416 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

■The pointer interpreter transitions into the DEC state based on the following conditions:

— When operating in the 8 of 10 mode (SPE_8ORMAJORITY = 1 (Table 159 on page 141)), if 8 of the 10 I and

D bits are correct for a pointer decrement on the incoming H1 and H2 bytes, the pointer interpreter transitions

into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement on

the incoming H1 and H2 bytes, the pointer interpreter transitions into the DEC state.

■The pointer interpreter transitions out of the DEC state based on the following conditions:

— If NDF is enabled on the incoming H1 and H2 bytes, the pointer interpreter transitions from the DEC state into

the NDF state.

— Following three consecutive frames with all ones in the H1 and H2 bytes, the pointer interpreter transitions from

the DEC state into the AIS-TU3 state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter transitions from the

DEC state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter transitions from the DEC

state into the NORM state.

— Following the number of consecutive invalid pointers (determined by the value programmed in

SPE_CNTDLOPCNT[1:0]), the pointer interpreter transitions from the DEC state into the LOP-TU3 state.

■Pointer increments and decrements will be counted and presented to the microprocessor as follows:

— Pointer increments and decrements will be monitored and counted internally.

— The internal and latched counts will be forced to 0x00 if device pin AUTO_AIS (AC6, AE6, and AD6) = 1 (from

TMUX), bit SPE_RLOP = 1 (Table 158 on page 140), or bit SPE_RAIS = 1 (Table 158).

— Latched counts, SPE_RPTR_INC[10:0] (Table 171 on page 151) and SPE_RPTR_DEC[10:0] (Table 171), will

be updated coincident with the end of a performance monitor interval.

— The internal counters will reset to 0x00 coincident with the end of a performance monitor interval.

— If SMPR_SAT_ROLLOVER = 1 (Table 77 on page 70), the internal running counts will hold at their maximum

value. Otherwise, the counts will roll over.

— However, increment and decrement event indications should be ignored during LOP state.

■LOP-TU3 (TU-3 path LOP) and AIS-TU3 (TU-3 path AIS) will be detected and reported to the microprocessor.

Both the LOP-TU3 and AIS-TU3 conditions will contribute to the AUTO AIS control signal from the SPE mapper

to the VT mapper. Any change in state of SPE_RLOP (Table 158 on page 140) or SPE_ RAI S (Table 158) will be

rep or te d t o t he micropro ce ss or via SPE _R L OP D (Table 156 on page 136) and SPE_RAISD (Table 156). Unless

the appropriate mask bit is set (SPE_RLOPM/SPE_RAISM (Table 157 on page 138)), SPE_RLO PD = 1 or

SPE_RAISD = 1 will generate an interrupt.

■The current TU-3 pointer value is stored in SPE_STORED_PTR[9:0] (Table 171 on page 151).

18.14 SPE Mapper Receive Dire ction Req uire m ents

All monitoring functions supported by the SPE mapper in the receive direction are summarized here:

■Loss o f CLOCK and loss of sync monitors

■J2 monitor

■B3 BIP-8 check

■C2 signal label monitor

■F2 monitor

■F3 monitor

■N1 monitor

■K3 monitor

■AIS-P and RDI-P detect

■REI-P detect

■Signal degrade BER algorithm

■Signal fail BER algorithm

■Path overhead access channel (POAC) drop

■Insertion of AIS-P

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

417Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Whenever the continuous N-times detect signals are defined, they require not only that the monitored signal be

consistent for N consecutive frames, but also that the frame bytes be error free for all N frames before the status

can be updated. If there are any errors in the framing pattern, then the consecutive N-times detection counters

must be reset to 0. N can range from 1 to 15. Programming a CNTD block with any value less than 1 will set the

CNTD to 1 time detect.

18.14.1 Loss of Clock and Loss of Sync Monitors

The SPE mapper detects and reports loss of the input clocks state for RLSCLK (pin V4) (19 MHz clock) in bit

SPE_RLSLOC (Table 158 on page 140), RLSC52 (pin AC2) (52 MHz clock) in bit SPE_RC52LOC (Table 158),

and DS3DATAINCLK (pin J22) (DS3 external clock) in bit SPE_RDS3LOC (Table 158), as determined by stuck

high or stuck low for time T. The detection time T will be greater than 10 µs but less than 125 µs. The function uses

the microprocessor clock as its reference. The device will report changes in the states using bits, SPE_RLSLOCD

(Table 156 on page 136), SPE_RC52LOCD (Table 156), and SPE_RDS3LOCD (Table 156); interrupt mask bits

SPE_RLSLOCM, SPE_RC52LOCM, and SP E_ RDS3 LO CM (Tabl e 157 on page 138), resp ec t iv e l y.

The SPE mapper will detect loss-of-sync conditions for the telecom bus sync signals. The states are reported in the

bits, SPE_RSY52LOS, SPE_RJ0J1V1LOS, SPE_RSPELOS, and SPE_RV1LOS (Table 158 on page 140). The

device will report changes in the states in bits SPE_RSY52LOSD (Table 156 on page 136), SPE_RJ0J1V1LOSD

(Table 156), SPE_RSPELOSD (Table 156), SPE_RV1LOSD (Table 156); interrupt mask bits SPE_RSY52LOSM,

SPE_RJ0J1V1LOSM, SPE_RSPELOSM, and SPE_RV1LOSM (Table 157 on page 138), respectively.

18.14.2 J1 Monitor

J1 (path trace) monitoring has six different monitoring modes controlled by bits SPE_J1MONMODE[2:0]

(Table 159 on page 141):

■SPE_J1MONMODE[2:0] = 000: the SPE mapper will latch the value of the J1 byte every frame for a total

64 bytes in SPE_RJ1 DMO N[1 —64] [7:0 ] (Table 172 on page 151). The SPE mapper compares the incoming J1

byte with the next expected value (the expected value is obtained by cycling through the previous stored 64

received bytes in round-robin fashion). The SPE mapper will perform a byte-by-byte comparison and, if different,

set the path trace identifier state bit SPE_RTIM (Table 158 on page 140). Any change in state is reported in bit

SPE_RTIMD (Table 156 on page 136), using interrupt mask bit SPE_RTIMM (Table 157 on page 138). CRC is

not checked by the hardware.

■SPE_J1MONMODE[2:0] = 001: this is the SONET framing mode. The hardware looks for 0x0D and then the

0x0DA characters to indicate that the next byte is the first byte of the path trace message. The J1 byte message

is continuously written into SPE_RJ1DMON[1—64][7:0] with the first byte residing at the first address. If any

received byte does not match the previously received byte for its location, then the state bit SPE_RTIM is set.

Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM.

■SPE_J1MONMODE[2:0] = 010: this is the SDH framing mode. The hardware looks for the byte with the most sig-

nificant bit (MSB) set to 1, which indicates that the next byte is the second byte of the message. The rest of oper-

ation is the same as in SONET framing mode.

■SPE_J1MONMODE[2:0] = 011: a new J1 byte (SPE_RJ1DMON[1][7:0]) will be detected after a number of con-

secutive consistent occurrences (SPE_CNTDJ1[3:0] (Table 160 on page 142)) of a new pattern in the J1 over-

head byte. Any changes to this byte is reported in bit SPE_RTIMD, using interrupt mask bit SPE_RTIMM. The

delta bit in this mode indicates a change in state for the J1 byte, and the bit SPE_RTIM is not used.

■SPE_J1MONMODE[2:0] = 100: the user will program the 64 expected values of J1 in registers,

SPE_RJ1DEXP[1—64][7:0] (Table 174 on page 151), in SONET framing mode, where the first expected byte,

the byte following the 0x0A character, is written into the first register location, SPE_RJ1DEXP[1][7:0]. The SPE

mapper performs a byte-by-byte comparison of the incoming J1 sequence with the stored expected value. If dif-

ferent, the SPE will set the SPE_RTIM state bit. Any changes in the state are reported in bit SPE_RTIMD, using

interrupt mask bit SPE_RTIMM.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

418 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

■SPE_J1MONMODE[2:0] = 101: the user will program the 16 expected values of J1 in

SPE_RJ1DEXP[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1.

The SPE mapper performs a byte-by-byte comparison of the incoming J1 sequence with the stored expected

value. If different, the SPE will set the SPE_RTIM state bit. Any change in state is reported in bit SPE_RTIMD,

using interrupt mask bit SPE_RTIMM.

■SPE_J1MONMODE[1:0] = 110 and 111 are currently undefined.

■Unless bit PAIS_TIMINH (Table 159 on page 141) is set, bit SPE_RTIMD contributes to the AUTO AIS control

signal from the SPE mapper to the VT mapper.

■Unless mask bit SPE_RTIMM is set, bit SPE_RTIMD can generate an interrupt.

Table 548. J1 Monitor

18.14.3 B3 BIP-8 Check

A B3 BIP-8 even parity is computed over all the incoming bits of the TUG-3 frame, after descrambling, and com-

pared to the B3 byte received in the next frame. The total number of B3 BIP-8 bit errors (raw count) or block errors

is counted (selected through SPE_B3BITBLKCNT (Table 159 on page 141)). Upon a performance monitor (PM)

interval, the internal running counter is placed into SPE_B3ECNT[15:0] (Table 170 on page 150) and then cleared.

Depending on the value of microprocessor bit SMPR_SAT_ROLLOVER (Table 77 on page 70), the internal

counter will roll over or stay at its maximum value until cleared.

18.14.4 Signal Label C2 Byte Monitor

Table 549. STS Signal Label Defect Conditions

Name Function

SPE_J1MONMODE[2:0] (Table 159 on page 141)J1 Monitoring Type.

SPE_RJ1DEXP[1—64][7 :0] (Table 174 on page 151)J1 Expected Data Storage (64/1 Byte).

SPE_RJ1DMON[1—64][7:0] (Table 172 on page 151)J1 Received Data Storage (64/1 Byte).

SPE_CNTDJ1[3:0] (Table 160 on page 142)Continuous Times Detect Value.

SPE_RTIM (Table 158 on page 140)J1 Mismatch State Bit.

SPE_RTIMD (Table 156 on page 136)J1 Mismatch Delta Bit, Active-High.

SPE_RTIMM (Table 157 on page 138)J1 Mismatch Mask Bit, Active-High.

Provisioned STS PTE

Functionality, Expected C2 Received Payload Label

(C2 in hex) Defect TMUX_FORCEC2DEF = 1

(Table 107 on page 99)

Any Equipped Functionality Unequipped (00) TMUX_RUNEQP No Change

Any Equipped Functionality Equipped—Nonspecific (01) None No Change

Equipped—Nonspecific Any Value (02 to E0, FD to FE) None No Change

Any Payload Specific Code The Same Payload Specific

Code (02 to E0, FD to FE) No ne No Chan ge

Any Payload Specific Code A Different Payload Specific

Code (02 to E0, FD to FE) TMUX_ RPL MP No Change

Equipped—Nonspecific (01) or

VT-Str uctur ed STS -1 (02) PDI, 1 to 27 VTx Defects

(E1 to FB) None TMUX_RPLMP

Any Payload Specific Code

Except VT-Structured

STS-1 (02)

PDI, 1 to 27 VTx Defects

(E1 to FB) TMUX_ RPL MP No Change

Any Equipped Functionality PDI, 28 VT1.5 Defects or 1

Non-VT Payload Defect (FC) None TMUX_RPLMP

Any Equipped Functionality Reserved (FF) None TMUX_RPLMP

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

419Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

The C2 byte is stored in SPE_C2DMON[7:0] (Table 162 on page 143). This is updated after a number of consecu-

tive frames (determined by the value programmed in SPE_CNTDC2[3:0] (Table 160 on page 142)) of identical C2

bytes, i.e., the 8-bit pattern must be identical for the number of frames in the programmed SPE_CNTDC2[3:0] prior

to updating SPE_C2DMON[7:0].

Whenever the contents of the C2 byte monitor SPE_C2DMON[7:0] change, a delta bit SPE_C2DMOND

(Table 156 on page 136) is set and bit SPE_C2DMONM (Table 157 on page 138) is the interrupt mask bit.

The SPE mapper maintains a programmable expected value of the C2 byte in SPE_C2DEXP[7:0] (Table 161 on

page 143). If the current value of the C2 byte (SPE_C2DMON[7:0]) does not equal the expected C2 value

(C2DEXP[7:0]), then a payload label mismatch (PLM-P) defect is declared and reported in SPE_RPLM

(Table 158). The change in PLM-P state is reported in SPE_RPLMD (Table 156) with an interrupt mask bit

SPE_RPLMM (Table 157 on page 138).

Also, if the current value of the C2 byte (SPE_C2DMON[7:0]) is all zeros, then an unequipped (UNEQ-P) defect is

declared and reported in SPE_RUNEQ (Tab le 158 on page 140). The change in UNEQ-P state is reported in

SPE_RUNEQD (Table 156 on page 136) with an interrupt mask SPE_RUNEQM (Table 157 on page 138).

Table 550. C2MON Processing

18.14.5 Path User Byte F2 Monitor

The SPE mapper monitors the path user channel in the F2 byte. The current value of the F2 byte is stored in

SPE_F2DMON0[7:0] (Table 162 on page 143) after a number of consecutive frames (determined by the value pro-

grammed in SPE_CNTDF2[3:0] (Table 160 on page 142)) of identical F2 byte has been received, i.e., the 8-bit pat-

tern must be identical for a number of frames equal to the value of SPE_CNTDF2[3:0] prior to updating

SPE_F2DMON0[7:0].

Whenever the contents of the F2 byte monitor (SPE_F2DMON0[7:0]) change, a delta bit SPE_F2DMOND

(Table 156 on page 136) is set. The interrupt mask is SPE_F2DMONM (Table 157 on page 138).

The SPE mapper maintains a history of the previous valid F2 byte in SPE_F2DMON1[7:0] (Table 162 on

page 143).

Name Function

SPE_C2DMON[7:0] (Table 162 on page 143)C2 Current Data Monitor.

SPE_C2DEXP[7:0] (Table 161 on page 143)Expected Value of C2 Byte.

SPE_CNTDC2[3:0] (Table 160 on page 142)Continuous Times Detect Count Value for C2.

SPE_C2DMOND (Table 156 on page 136)C2 Data Monitor Event Bit.

SPE_C2 DMONM (Table 157 on page 138)C2 Data Monitor Mask Bit.

SPE_RPLM (Table 158 on page 140)Payload Label Mismatch State.

SPE_RPLMD (Table 156 on page 136)Payload Label Mismatch Delta Bit.

SPE_RPLMM (Table 157 on page 138)Payload Label Mismatch Mask Bit.

SPE_RUNEQ (Table 158 on page 140)Unequipped Path State.

SPE_RUNEQD (Table 156 on page 136)Unequipped Path Delta Bit.

SPE_RUNEQD (Table 157 on page 138)Unequipped Path Mask Bit.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

420 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table 551. F2 Monitor

18.14.6 Path User Byte F3 Monitor

The SPE mapper monitors the second path user channel in the F3 byte. The current value of the F3 byte is stored

in SPE_F3DMON0[7:0] (Table 162 on page 143) after a number of consecutive frames (determined by the value

programmed in SPE_CNTDF3[3:0] (Table 160 on page 142)) of identical F3 bytes has been received, i.e., the 8-bit

pattern must be identical for a number of frames, determined by SPE_CNTDF3[3:0], prior to updating

SPE_F3DMON0[7:0].

Whenever the contents of the F3 byte monitor (SPE_F3DMON0[7:0]) change, a delta bit SPE_F3DMOND

(Table 156 on page 136) is set. The interrupt mask is in register bit SPE_F3DMONM (Table 157 on page 138).

The SPE mapper maintains a history of the previous valid F3 byte in SPE_F3DMON1[7:0] (Table 162 on

page 143).

Table 552. F3 Monitor

18.14.7 N1 Monitor

The SPE mapper stores the current value of the N1 byte in SPE_N1DMON[7:0] (Table 162 on page 143). This is

updated after a number of consecutive frames (determined by the value programmed in bits SPE_CNTDN1[3:0]

(Table 160 on page 142)) of identical N1 bytes, i.e., the 8-bit pattern must be identical for a number frames deter-

mined by the value in register bits SPE_CNTDN1[3:0] prior to updating the N1 register.

Whenever the contents of the N1 byte monitor (SPE_N1DMON[7:0]) change, a delta bit SPE_N1DMOND

(Table 156 on page 136) is set. The interrupt generated by SPE_N1DMOND can be masked off by

SPE_N1DMONM (Table 157 on page 138).

Table 553. N1 Monitor

Name Function

SPE_F2DMON0[7:0] (Table 162 on page 143)Fault Location Current Consistent Value.

SPE_F2DMON1[7:0] (Table 162 on page 143)Fault Location Previous Consistent Value.

SPE_CNTDF2[3:0] (Table 160 on page 142)Continuous N-Time s Detect (3—15).

SPE_F2DMOND (Table 156 on page 136)F2 Data Monitor Delta Bit.

SPE_F2DMONM (Table 157 on page 138)F2 Data Monitor Mask Bit.

Name Function

SPE_F3DMON0[7:0] (Table 162 on page 143)User Channel Current Consistent Value.

SPE_F3DMON1[7:0] (Table 162 on page 143)User Channel Previous Consistent Value.

SPE_CNTDF3[3:0] (Table 160 on page 142)Continuous N-Times Detect (3—15).

SPE_F3DMOND (Table 156 on page 136)F3 Data Monitor Delta Bit.

SPE_F3DMONM (Table 157 on page 138)F3 Data Monitor Mask Bit.

Name Function

SPE_N1DMON[7:0] (Table 162 on page 143)Fault Location Current Consistent Value.

SPE_CNTDN1[3:0] (Table 160 on page 142)Continuous N-Times Detect (3—15).

SPE_N1DMOND (Table 156 on page 136)N1 Data Monitor Delta Bit.

SPE_N1 DMONM (Table 157 on page 138)N1 Data Monitor Mask Bit.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

421Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.14.8 K3 Byte Monitor

The SPE mapper stores the current value of the K3 byte in SPE_K3DMON[7:0] (Table 162 on page 143). This is

updated after a number of consecutive frames (determined by the value programmed in bits SPE_CNTDK3[3:0]

(Table 160 on page 142)) of identical K3 bytes, i.e., the 8-bit pattern must be identical for a number of frames

determined by the value of SPE_CNTDK3[3:0] prior to updating the K3 register.

Whenever the contents of the K3 byte monitor (SPE_K3DMON[7:0]) change, a delta bit SPE_K3DMOND

(Table 156 on page 136) is set. The interrupt generated by SPE_K3DMOND can be masked off by the

SPE_K3DMONM (Table 157).

Table 554. K3 Monitor

18.14.9 AIS-P and RDI-P Detect

The SPE mapper monitors for path AIS in the H1 and H2 bytes (all H1 and H2 bits = 1) of the TUG-3 pointer . When

path AIS is detected, SPE_RAIS (Table 158 on page 140) will be set to 1 after three consecutive occurrences. Any

changes to SPE_RAIS will be reported in SPE_RAISD (Table 156 on page 136) and the interrupt can be masked,

using SPE_RAISM (Table 157 on page 138).

A remote defect indication-path (RDI-P) signal indicates to STS PTE that its peer STS PTE has detected a defect

on the signal that it originated. The SPE mapper supports both the single bit RDI-P and the 3-bit enhanced RDI-P;

the mode is selectable using bit SPE_RPRDI_MODE (Table 159 on page 141). When SPE_RPRDI_MODE = 0,

1-bit code is supported and when SPE_RPRDI_MODE = 1, 3-bit enhanced RDI-P code is supported. Three bits of

the G1 byte (G1[3:1]) are reserved for the RDI-P signal.

The SPE mapper monitors for a 1-bit RDI-P code in G1[3] bit or a 3-bit enhanced remote defect indication (RDI-P)

condition in the G1[3:1] bits and stores the current value in bits SPE_PRDIDMON[2:0] (Table 162 on page 143).

The current value is updated after a number of consecutive frames (determined by the value of bits

SPE_CNTDPRDI[3:0] (Table 160 on page 142)) of identical G1[3:1], i.e., the 3-bit pattern must be identical for a

number of frames, determined by the value of SPE_CNTDPRDI[3:0] prior to updating SPE_PRDIDMON[2:0].

Whenever the contents of SPE_PRDIDMON[2:0] change, a delta bit SPE_PRDIDMOND (Table 156 on page 136)

is set. The interrupt generated by SPE_PRDIDMOND can be masked off by SPE_PRDIDMONM (Table 157 on

page 138).

Table 555. AIS-P and RDI-P Detect

Name Function

SPE_K3DMON[7:0] (Table 162 on page 143)Fault Location Current Consistent Value.

SPE_CNTDK3[3:0] (Table 160 on page 142)Continuous N-Times Detect (3—15).

SPE_K3DMOND (Table 156 on page 136)K3 Data Monitor Delta Bit.

SPE_K3DMONM (Table 157 on page 138)K3 Data Monitor Mask Bit.

Name Function

SPE_CNTDPRDI[ 3:0] (Tab le 160 on page 142)Continuous Times Dete ct Count Value for

G1[3:1] Bits (3—15 ).

SPE_PRDIDMOND (Table 156 on page 136)Path RDI Delta Bit.

SPE_PRDIDMONM (Table 157 on page 138)Path RDI Mask Bit.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

422 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.14.10 REI-P Detect

Bits 7 through 4 of the G1 byte are allocated for use as a path remote error indication function (REI-P).

■For STS-1 signals, bits 7 through 4 of the G1 byte are allocated for REI-P, which conveys the error count

detected by the PTE (using the path BIP-8 code B3) back to its peer PTE as follows.

Table 556. STS-1 P-REI Interpretation

The SPE mapper provides a counter to accumulate G1-REI errored bit count in SPE_G1ECNT[15:0] (Table 170 on

page 150) from G1[7:4]. This counter will hold at its maximum value or roll over (depending on the value of micro-

processor bit SMPR_SAT_ROLLOVER (Table 77 on page 70)) and update upon the performance monitoring inter-

val.

18.14.11 Signal Degrade BER Algorithm

A signal degrade state bit is SPE_SDB3 (Table 158 on page 140) with a change of state indication reported in

delta bit SPE_SDB3D (Table 156 on page 136) and the interrupt mask bit is SPE_SDB3M (Table 157). This bit

error rate algorithm operates on B3 errors.

Declaring the signal degrade state requires the definition of two measurement windows: a monitoring block con-

sisting of a number of frames, Ns (SPE_SDNSSET[18:0] (Table 168 on page 149)), and a measureme nt inte rval

consisting of a number of monitoring blocks, B (SPE_SDBSET[11:0] (Table 168)). A block is determined bad when

the number of bit errors equals or exceeds a threshold, L (SPE_SDLSET[3:0] (Table 168)). Signal degrade is

declared when a number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SDMSET[7:0]

(Table 168)), for the measurement interval.

Clearing the signal degrade state requires the definition of two measurement windows: a monitoring block consist-

ing of a number of frames, Ns (SPE_SDNSCLEAR[18:0] (Table 168)), and a measurement interval consisting of a

number of monitoring blocks, B (SPE_SDBCLEAR[11:0] (Table 168)). A block is determined good when the num-

ber of bit errors is less than a threshold, L (SPE_SDLCLEAR[3:0] (Table 168)). Signal degrade is cleared when a

number of good monitoring blocks equals or exceeds the threshold, M (SPE_SDMCLEAR[7:0] (Table 168)) , for th e

measurement interval.

The set parameters are used when the signal degrade state is clear, and the clear parameters are used when the

signal degrade state is declared.

The signal degrade state may be forced to the declared state with bit SPE_SDSET (Tab le 155 on page 136) and

forced to the cleared state with bit SPE_SDCLEAR (Table 155). The controls are provided to force the BER algo-

rithm into the failed state or normal state, respectively.

The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.

G1[7:4] Code Code Interpretation

0000 0 (no errors )

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001—1111 0 (no errors )

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

423Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table 557. Signal Degrade Paramete rs

Note: The threshold written by the c ontrol system is one less than the desired number, except for the SPE_SDLSET[3:0]/SDLCLEA R[3:0]

parameter.

18.14.12 Signal Fail BER Algorithm

A signal fail state is reported by bit SPE_SFB3 (Table 158 on page 140) and change of state in bit SPE_SFB3D

(Table 156) with the interrupt mask bit SPE_SFB3M (Table 157). This bit error rate algorithm operates on B3

errors.

Declaring the signal fail state requires the definition of two measurement windows: a monitoring block consisting of

a number of frames, Ns (SPE_SFNSSET[18:0] (Tab le 169 on page 150)), and a measurement interval consisting

of a number of monitoring blocks, B (SPE_SFBSET[15:0] (Table 169)). A block is determined to be bad when the

number of bit errors equals or exceeds a threshold, L (SPE_SFLSET[3:0] (v)). Signal fail is declared when the

number of bad monitoring blocks equals or exceeds the threshold, M (SPE_SFMSET[7:0] (Table 169)), for the

measurement interval.

Clearing the signal fail state requires the definition of two measurement windows: a monitoring block consisting of

a number of frames, Ns (SPE_SFNSCLEAR[18:0] (Table 169)), and a measurement interval consisting of a num-

ber of monitoring blocks, B (SPE_SFBCLEAR[11:0] (v)). A block is determined to be good when the number of bit

errors is less than a threshold, L (SPE_SFLCLEAR[3:0] (Table 169)). Signal fail is cleared when a number of good

monitoring blocks equals or exceeds the threshold, M (SPE_SFMCLEAR[7:0] (v)), for the measurement interval.

The set parameters are used when the signal fail state is clear , and the clear parameters are used when the signal

fail state is declared.

The signal fail state may be forced to the declared state with bit SPE_SFSET (Table 155 on page 136), and forced

to the cleared state with bit SPE_SFCLEAR (Table 155).

The above algorithm can detect bit error rates from 1 x 10–3 to 1 x 10–9.

Name Function

SPE_SDNSSET[18:0] (Table 168 on page 149)Signal Degrade Ns Set. Number of frames in a monitoring

block for SD.

SPE_SDLSET[3:0] (Table 168)Signal Degrade L Set. Error threshold for determining if a mon-

itoring block is bad.

SPE_SDMSET[7:0] (Table 168)Signal Degrade M Set. Threshold of the number of bad moni-

toring blocks in an observation interval. If the number of bad

blocks is below this threshold, then SD is cleared.

SPE_SDBSET[15:0] (Table 168)Signal Degrade B Set. Number of monitoring blocks in a mea-

surement interval.

SPE_SDNSCLEAR[18:0] (Table 168)Signal Degrade Ns Clear. Number of frames in a monitoring

block for SD.

SPE_SDLCLEAR[3:0] (Table 168)Signal Degrade L Clear. Error threshold for determining if a

monitoring block is bad.

SPE_SDMCLEAR[ 7:0] (Table 168)Signal Degrade M Clear. Threshold of the number of bad mon-

itoring blocks in an observation interval. If the number of bad

blocks is below this threshold, then SD is cleared.

SPE_SDBCLEAR[15:0] (Table 168)Signal Degrade B Clear. Number of monitoring blocks in a

measurement interval.

SPE_SD SET (Table 155 on page 136)Signal Degrade Set. Allows the signal degrade algorithm to be

forced into the failed state (active 0 to 1).

SPE_SDCLEAR (Table 155)Signal Degrade Clear. Allows the signal degrade algorithm to

be forced into the normal state (active 0 to 1).

SPE_SDB3 (Table 158 on page 140)Signal Degrade BER Algorithm State Bit.

SPE_SDB3D (Table 156 on page 136)Signal Degrade BER Algorithm Delta Bit.

SPE_SDB3M (Table 157 on page 138)Signal Degrade BER Algorithm Mask Bit.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

424 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table 558. Signal Fail Parameters

Note: The threshold written by the c ontrol sys tem is one less than the desired number, except for the SPE_SFLSET[3:0]/SFLCLE AR[ 3:0]

parameter.

18.14.13 POAC Drop

The SPE mapper accommodates one path overhead access channel (POAC output channel).

The POAC channel consists of the following signals:

■A 576 kHz inverted clock signal sourced by the TMUX (RPOACCLK, pin AE3).

■A 576 kbits/s data signal sourced by the TMUX (RPOACDATA, pin AD4).

■An 8 kHz synchronization signal, sourced by the TMUX (RPOACSYNC, pin AF4). The sync signal is normally

low; during the last clock period of each frame coincident with the least significant bit of the last byte, the sync

signal is high.

The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits

that are transmitted/received most significant bit first (MSB). The MSB of the second byte of each frame contains

an odd/even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified.

Name Function

SPE_SFNSSET[18:0] (Table 169 on page 150)Signal Fail Ns Set. Number of frames in a monitoring block for

SF.

SPE_SFLSET[3:0] (Table 169)Signal Fail L Set. Error threshold for determining if a monitoring

block is bad.

SPE_SFMSET[7:0] (Table 169)Signal Fail M Set. Threshold of the number of bad monitoring

blocks in an observation interval. If the number of bad blocks is

below this threshold, then SF is cleared.

SPE_SFBSET[15:0] (Table 169)Signal Fail B Set. N umber of monitoring blocks.

SPE_SFNSCLEAR[18:0] (Table 169)Signal Fail Ns Clear. Number of frames in a monitoring block

for SF.

SPE_SFLCLEAR[3:0] (Table 169)Signal Fail L Clear. Error threshold for determining if a monitor-

ing block is bad.

SPE_SFMCLEAR[7:0] (Table 169)Signal Fail M Clear. Threshold of the number of bad monitoring

blocks in an observation interval. If the number of bad blocks is

below this threshold, then SF is cleared.

SPE_SFBCLEAR[15:0] (Table 169)Signal Fail B Clear. Number of monitoring blocks.

SPE_SFSET (Table 155 on page 136)Signal Fail Set. Allows the signal degrade algorithm to be

forced into the failed state (active 0 to 1).

SPE_SFCLEAR (Table 155)Signal Fail Clear. Allows the signal degrade algorithm to be

forced into the normal state (active 0 to 1).

SPE_SFB3 (Table 1 58 on page 140 )Signal Fail BER Algorithm State Bit.

SPE_SFB3D (Table 156 on page 136)Signal Fail BER Algorithm Delta Bit.

SPE_SFB3M (Table 157 on page 138)Signal Fail BER Algorithm Mask Bit.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

425Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Bytes shown in Table 559 summarize the access capabilities of the receive POAC.

Table 559. Path Overhead Byte Access

Even or odd parity can be inserted into the first bit of the second byte of the POAC outgoing frame. Parity is

selected with register bit SPE_RPOAC_OEPINS (Table 159 on page 141).

18.14.14 Insertion of AIS-P

The SPE mapper automatically generates AIS path (AIS-P) when:

■The pointer interpreter declares the receive AIS state (SPE_RAIS in Table 158 on page 140) or rece ive loss-of-

pointer state (SPE_RLOP (Table 158)) and the appropriate inhibit signals are inactive.

■AIS is requested by signals from the TMUX interface.

■AIS is forced by setting bit SPE_PAISINS (Table 159).

■Any one of the loss-of-clock or loss-of-sync bits are active and their corresponding inhibit bits are inactive.

■Any of bits SPE_RUNEQ, SPE_RPLM, and SPE_RTIM (all are in Table 158) are active, and the appropriate

inhibit signals are inactive.

Criteria for PATH_AIS_GE NE RATE =

((SP E_RLOP AND (SPE_PAIS_LOPINH)) OR

(SPE_RAIS AND (SPE_PAIS_AISIN H)) OR

(SPE_RUNEQ AND (SPE_PAIS_UNEQINH)) OR

(SPE_RPLM AND (SPE_PAIS_PLMINH)) OR

(SPE_RTIM AND (SPE_PAI S_TIMINH)) OR

(SPE_SFB3 AND (SPE_PAIS_SFB3INH)) OR

(SPE_SDB3 AND (SPE_PAIS_SDB3INH)) OR

(SPE_RSY52LOS AND (SPE_AIS_LOSSY52INH)) OR

(SPE_RV1LOS AND (SPE_AIS_LOSV1INH)) OR

(SPE_RSPELOS AND (SPE_AIS_LOSSPEINH)) OR

(SPE_RJ0J1V1LOS AND (SPE_AIS_LOSJ0J1V1INH)) OR

(SPE_RDS3LOC AND (SPE_AIS_LOCDS3INH)) OR

(SPE_RC52LOC AND (SPE_AIS_LOC52INH)) OR

(SPE_RLSLOC AND (SPE_AIS_LOCINH)) OR

SPE_PAISINS OR

RAUTO_AIS (signal from TMUX))

The SPE mapper starts/stops generating AIS-P within 125 µs of the detection/absence of a failure condition.

AIS-P consists of writing all ones into the H1, H2, and H3 bytes and into the entire payload.

POH Parity

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

426 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.15 Tran smit Direction (to SONET /SDH Line)

The transmit block inserts the path overhead (POH) bytes to the payload data and outputs an STS-1 SPE or a

TUG-3 payload as required.

The transmit section is broken down into the following functional parts:

■Loss of clock and loss of sync detectors

■N1 insert

■K3 insert

■Path user byte F3 insert

■Path user byte F2 insert

■AIS-P insert

■REI-P insert

■RDI-P insert

■C2 signal label insert

■B3 calculation and insert

■J1 path trace insert

All insert control functions that are inhibited will insert all zeros or all ones into the outgoing bytes, depending on the

value of microprocessor register bit SMPR_OH_DEFLT (Ta ble 77 on page 70).

18.15.1 PATH Insertion Block

The path overhead insertion block of the SPE mapper is shown below. The block computes and inserts the B3 BIP

error bytes and the rest of the path overhead bytes to form a TUG-3 frame.

5-9069(F)

Figure 38. Transmit Direction Path Insertion Block

INSERT K3

N1 C2 F3 F2K3 G1 G1J1

INSERT

AIS-P

POAC INSERT

INSERT PATH OVERHEAD BYTES

MUX

TO TMUX INTERFACE

BLOCK

VC-3 DATA

TUG-3 DATA

J1 APS

INSERT

RDI-P

INSERT

REI-P

INSERT INSERT

N1 INSERT

C2 INSERT

F3 INSERT

F2 INSERT H4

FIXED VAL

GENERATEINSERT

F2, F3, C2, N1, AND J1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

427Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.15.2 Loss of Clock and Loss of Sync Detectors

The SPE mapper detects and reports the loss of the input clocks for the transmit telecom bus clock, device pin

TLSCLK (A A2), i n bit SPE_ TLS LOC (Table 158 on page 140), the 51.84 MHz transmit low-speed clock, device pin

TLSC52 (AC3), in bit SPE_TC52LOC (Table 158), and the external DS3 clock, device pin DS3DATAINCLK (J22),

in bit SPE_TDS3LOC (Table 158). Loss of clock is determined by stuck high or stuck low for time T. The detection

time T will be greater than 10 µs but less than 125 µs. The function uses the microprocessor clock as its reference.

The device will report a change in the loss of clock state for the monitored clocks using bits SPE_TLSLOCD

(Table 156 on page 136), SPE_TC52LOCD (Table 156), and SPE_TDS3LOCD (Table 156), respectively. The

microprocessor interrupt may be masked using bits SPE_TLSLOCM, SPE_TC52LOCM, and SPE_TDS3LOCM

(Table 157 on page 138), respectively.

The SPE mapper detects loss-of-sync conditions for the telecom bus sync signals, device pins TLSSYNC52 (AD2),

TLSJ0 J1V1 (AB4), TLSSPE (AB2), and TLSV1 ( AB3). The loss of syn c states are repo rted in bits SPE_ TSY52LOS

(Table 158), SPE_TJ0J1V1LOS (Table 158), SPE_TSPELOS (Table 158), and SPE_TV1LOS (Table 158),

respectively. The device will report a change in the loss of sync state for the monitored sync signals in bits

SPE_TSY52LOSD (Table 156), SPE_TJ0J1V1LOSD (Table 156), SPE_TSPELOSD (Table 156), and

SPE_TV1LOSD (Table 156), respectively. The microprocessor interrupt may be masked using bits

SPE_TSY52LOSM, SPE_TJ0J1V1LOSM, SPE_TSPELOSM, and SPE_TV1LOSM (Table 157), respec ti v el y.

18.15.3 J1 Byte Insert

A 64-byte sequence stored in SPE_TJ1DINS[1—64][7:0] (Table 173 on page 151) will be inserted into the outgo-

ing J1 byte when bit SPE_TJ1INS = 1 (Table 164 on page 146); otherwise, the associated POAC value is inserted

when bit SPE_TPOAC_J1 = 1 (Table 164) or the default value, determined by the value of microprocessor bit

SMPR_OH_DEFLT (Table 77 on page 70), is inserted when SPE_TPOA C_J1 = 0.

The CRC for the J1 trace has to be programmed into the J1 bytes by the user.

18.15.4 B3 BIP-8 Calculation and Insert

The B3 bytes are allocated for path overhead error monitoring function. This function is a bit interleaved parity

8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous AU-3/TUG-

3 frame, and is placed in byte B3 of the current frame also before scrambling. When enabled with control bit,

SPE_TB3ERRINS (Table 166 on page 148), a single B3 byte can be inverted each time bit SPE_BERR_INS

(Table 166) is asse rted.

18.15.5 C2 Signal Label Byte Insert

When bit SPE_TC2INS = 1 (Table 164 on page 146), the value in SPE_TC2DINS[7:0] (Table 167 on page 149) is

inserted into the outgoing C2 byte; otherwise, insert the associated POAC value when SPE_TPOAC_C2 = 1

(Table 164) or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT when bit

SPE_T PO A C_C2 = 0.

18.15.6 REI-P G1(7:4) Insert

Four bits of the G1 byte G1(7:4) are allocated for use as a path remote error indication (REI). For AU-3/TUG-3 sig-

nals, these bits convey the count (in the range of 0 to 8) of interleaved bit blocks that have been detected in error

by the BIP-8 (B3) detector on the received signal.

This function can be inhibited with bit SPE_TREIP_INH (Table 165 on page 148) and the value in

SPE_TG1DINS[7:4] (Table 167 on page 149) is inserted in G1(7:4) bits. A continuous error in the G1 byte can be

transmitted using control bit SPE_TREIERRINS (Table 166 on page 148). A value of 0x03 will be inserted when

SPE_TREIERRINS = 1, subject to SPE_BERR_INS and SMPR_BER_INSRT being enabled.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

428 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.15.7 Path RDI (RDI-P) Insert

When transmit RDI software insert control bit SPE_TPRDIINS = 1 (Table 165 on page 148), data from

SPE_TG1DINS[3:1] (Table 167 on page 149) is written into the G1[3:1] output bits. When SPE_TPRDIINS = 0,

hardware insert is enabled for RDI-P insertion. Each defect contribution to the RDI-P outgoing code can be inhib-

ited. There are two modes supported for path RDI Insertion. One mode conforms to the earlier 1-bit version of the

standard. The other mode, enhanced RDI-P mode, uses a 3-bit RDI-P code and conforms to the current version of

the standard. When the mode selection bit SPE_TPRDI_MODE = 0 (Table 165 on page 148), the SPE mapper

sends a 3-bit code that conforms to the earlier 1-bit version of the standards. When SPE_TPRDI_MODE = 1, the

SPE mapper sends a 3-bit code conforming to the current enhanced path RDI encoding. Note that for nonen-

hanced RDI-P mode, the relevant defects are AIS-P and LOP-P. For enhanced RDI-P mode, the relevant defects

are AIS-P, LOP-P, TIM-P, PLM-P, UNEQ-P, and TIM-P.

When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must

last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.

The following table describes the encoding of the path-RDI defects.

Table 560. RDI-P Defects for Enhanced RDI-P Mode

18.15.8 F2 Byte Insert

When control bit SPE_TF2INS = 1 (Table 164 on page 146), insert the value in SPE_TF2DINS[7:0] (Table 167 on

page 149) in the outgoing F2 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F2 = 1

(Table 164), or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 77 on

page 70) when SPE_TPOAC_F2 = 0.

18.15.9 H4 Insert Control

When control bit SPE_TH4INS = 1 (v), insert the value in SPE_TH4DINS[7:0] (Table 167 on page 149) in the out-

going H4 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_H4 = 1 (Table 164 on

page 146), or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT when

SPE_T PO A C_H4 = 0.

18.15.10 F3 Byte Insert

When control bit SPE_TF3INS = 1 (Table 164 on page 146), insert the value in SPE_TF3DINS[7:0] (Table 167 on

page 149) in the outgoing F3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F3 = 1

(Table 164), or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT (Table 77 on

page 70) when SPE_TPOAC_F3 = 0.

G1 Triggers

Bit 3 Bit 2 Bit 1

0 0 0 No defects (nonenhanced RDI-P mode)

0 0 1 No defects (enhanced RDI-P mode)

0 1 0 LCD-P, PLM-P (LCD-P not supported in Supermapper)

0 1 1 No defects (nonenhanced RDI-P mode)

1 0 0 AIS-P, LOP-P (nonenhanced RDI-P mode)

1 0 1 AIS-P, LOP-P (enhanced RDI-P mode)

1 1 0 TIM-P, UNEQ-P (enhanced RDI-P mode)

1 1 1 AIS-P, LOP-P (nonenhanced RDI-P mode)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

429Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

18.15.11 K3 Insert Control Parameters

When control bit SPE_TK3INS = 1 (Table 164 on page 146), insert the value in SPE_TK3DINS[7:0] (Table 167 on

page 149) in the outgoing K3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_K3 = 1

(Table 164), or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT when

SPE_TPOAC_K3 = 0.

18.15.12 N1 Insert Control Parameters

When control bit SPE_TN1INS = 1 (Table 164 on page 146), insert the value in SPE_TN1DINS[7:0] (Table 167 on

page 149) in the outgoing N1 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_N1 = 1

(Table 164), or insert the default value determined by the microprocessor bit SMPR_OH_DEFLT when

SPE_T PO A C_N1 = 0.

18.16 POAC Insert

One overhead access channel (POAC) is provided on-chip to provision the path overhead portion of the outgoing

frame. A POAC channel consists of the following signals:

■A 576 kHz inverted clock signal sourced by the SPE mapper (TPOACCLK, pin AE4).

■A 576 kbits/s data signal received by the SPE mapper in the transmit direction (TPOACDATA, pin AD5).

■An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the SPE mapper. The sync signal is nor-

mally low; during the first clock period of each frame coincident with the most significant bit of the first byte, the

sync signal is high.

The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits

that are transmitted/received most significant bit first. The MSB of the second byte of each frame contains an odd/

even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. The POAC

input has full access to all the path overhead bytes of the STS-1 frame. Bytes shown in the table below summarize

the access capabilities of the transmit POAC channel.

Table 561. Path Overhead Byte Access—Transmit Direction

An event indication is provided to indicate parity errors for the POAC channel. Monitoring of odd or even parity is

sel ected with bit SPE_TPOAC_OEPMON (Table 164 on page 146). Parity errors are reported with bit

SPE_TPOAC_PE (Table 156 on page 136). The interrupt can be masked with bit SPE_TPOAC_PM (Table 157 on

page 138).

Table 562 on page 430 summarizes the insertion options for the specified overhead bytes for POAC. The SPE

mapper allows a predefined default value determined by the value of the microprocessor bit SMPR_OH_DEFLT

(Table 77 on page 70 ) to be inserted on the corresponding POAC value.

POH Parity

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

430 Agere Systems Inc.

18 SPE Mapper Functional Description (continued)

Table 562. TPOAC Control Bits

18.17 AIS Path Generation

Path AIS is specified as all ones in the entire STS-1 SPE/TUG-3 frame. Path AIS can be forced by setting bit

SPE_TAISPINS = 1 (Table 164 on page 146).

Overhead Bytes Control Bits

(Table 164 on page 146)Values

0 (Default Value) 1

J1 SPE_TPOAC_ J1 SMPR_OH_DE FLT TPOAC Data

H4 SPE_TPOAC_H4

F2 SPE_TPOAC_F2

F3 SPE_TPOAC_F3

C2 SPE_TPOAC_C2

K3 SPE_TPOAC_K3

N1 SPE_TPOAC_N1

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

431Agere Systems Inc.

19 VT/TU Mapper Functional Description

Table of Con t en ts

Contents Page

19 VT/TU Mapper Functional Description ............................................................................................................431

19.1 VT/TU Mapper Introduction......................................................................................................................433

19.2 VT/TU Mapper Features...........................................................................................................................433

19.3 VT/TU Mapper Functional Block Diagram................................................................................................434

19.4 VT/TU Mappings ......................................................................................................................................436

19.5 VT/TU Locations.......................................................................................................................................437

19.6 VT/TU Mapper Receive Path Description ................................................................................................438

19.7 VT Demultiplexer (VTDEMUX).................................................................................................................438

19.8 VT Pointer Interpre ter (VTPI) .......... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... .........................................438

19.9 VT Termination (VTTERM).......................................................................................................................441

19.9.1 V5 Term in ation ......... ................... ....... ...... ....... ................... ...... ....... ...... ....... ................................. 441

19.9.2 Z6/N2 Term in ation ................ ...... ....... ...... ....... ...... ...... .................... ...... ....... ...... ....... .................... 442

19.9.3 Z7/K4 Termination ............................. ...... ....... ...... ...... ....... ...... .................... ...... ....... .................... 443

19.9.4 Pay load Te rmin ation ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... .................... ...... ....... .................... 443

19.10 Output Signal Selection (OUTSEL)........................................................................................................444

19.11 J2 Byte Monitor and Termination (J2MON)............................................................................................444

19.12 Receive Signaling (RX_VTSIG) .............................................................................................................445

19.13 Receive Lower-Order Path Overhead (RX_LOPOH).............................................................................446

19.14 VT/TU Mapper Transmit Path Requirements.........................................................................................447

19.14.1 Input Selector (INSEL) ................................................................................................................ 447

19.14.2 Transmit Elastic Store (TES) ...................................................................................................... 448

19.14.3 Virtual Tributary Generator (VTGEN) .......................................................................................... 449

19.14.4 Pointer Generation ...................................................................................................................... 449

19.14.5 VT Multiplexer (VTMUX) ............................................................................................................. 457

19.14.6 Transmit Signaling (TX_VTSIG) ................................................................................................. 457

19.14.7 Transmit Lower Path Overhead (TX_LOPOH) ........................................................................... 457

19.15 VT Mapper System Interface Timing......................................................................................................458

19.15.1 VT Mapper DS1/E1 Receive Interface (to System Interface) ..................................................... 458

19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface) ................................................ 459

19.16 VT Mapper Lower-Order Path Overhead Interface Timing ....................................................................459

19.16.1 VT Mapper Receive Path Overhead Interface Description ......................................................... 459

19.16.2 VT Mapper Transmit Path Overhead Interface Description ........................................................ 460

Figures Page

Figure 39. VT Mapper Interface Diagram..............................................................................................................434

Figure 40. VT Mapper Functional Block Diagram..................................................................................................435

Figure 41. Pointer Interpretation State Diagram....................................................................................................439

Figure 42. DS1 Mode Gapped Clocking Scheme..................................................................................................458

Figure 43. E1 Mode Gapped Clocking Scheme ....................................................................................................458

Figure 44. DS1 Interface .......................................................................................................................................458

Figure 45. E1 Interface..........................................................................................................................................459

Figure 46. VT Mapper Receive Path Overhead Serial Access Channel...............................................................459

Figure 47. VT Mapper Transmit Path Overhead Serial Access Channel..............................................................460

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

432 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table of Conten ts (continued)

Tables Page

Table 563. VT2/TU-12 Payload Mapping...............................................................................................................436

Table 564. VT1.5/TU-11 Payload Mapping............................................................................................................436

Table 565. VT2/TU-12 Locations...........................................................................................................................437

Table 566. VT1.5/TU-11 Locations ........................................................................................................................437

Table 567. Receive VT/TU Demapping Selection .................................................................................................443

Table 568. Rx Signaling Behavior Per Channel.....................................................................................................446

Table 569. Data Type Header Definitions..............................................................................................................447

Table 570. Transmit VT/TU Mapping Selection per Channel, VT_TX_MAPTYPE[1—28][3:0]..............................448

Table 571. V5 Overhead Byte Format...................................................................................................................450

Table 572. BIP-2 Error Insertion Modes ................................................................................................................450

Table 573. RDI-V, RFI-V, and REI-V Automatic Generation..................................................................................451

Table 574. VT Signal Label Definition....................................................................................................................451

Table 575. J2 Overhead Byte Insertion Modes Per Channel.................................................................................452

Table 576. Z6/N2 Overhead Byte Insertion Modes Per Channel...........................................................................452

Table 577. Z7/K4 Overhead Byte Insertion Modes Per Channel...........................................................................452

Table 578. O-Bit Insertion Modes Per Channel.....................................................................................................453

Table 579. Asynchronous VT1.5............................................................................................................................454

Table 580. Bit-Synchronous VT1.5........................................................................................................................454

Table 581. Byte-Synchronous VT1.5.....................................................................................................................454

Table 582. Asynchronous VT2...............................................................................................................................455

Table 583. Bit-Synchronous VT2...........................................................................................................................455

Table 584. Byte-Synchronous VT2........................................................................................................................455

Table 585. VC-11 to TU-12 Conversion.................................................................................................................456

Table 586. Framing Byte Generation Per Channel................................................................................................457

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

433Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.1 VT/TU Mapper Introd uction

This section describes the requirements of the SONET/SDH virtual tributary payload mapping block. This block

supports the following mappings:

■28 asynchronous, byte-synchronous, or bit-synchronous DS1 signals into seven virtual tributary groups (VTGs).

■28 asynchronous, byte-synchronous, or bit-synchronous DS1 signals into seven tributary unit groups (TUG-2s).

■28 asynchronous, byte-synchronous, or bit-synchronous J1 signals into seven virtual tributary groups (VTGs).

■28 asynchronous, byte-synchronous, or bit-synchronous J1 signals into seven tributary unit groups (TUG-2s).

■21 asynchronous, byte-synchronous, or bit-synchronous E1 signals into seven tributary unit groups (TUG-2s).

■Any valid DS1/E1 combination resulting in mixed VTGs and TUG-2s.

Additionally, this block has two auxiliary channels: one for DS1/E1 signaling insertion and drop, and another for

low-order path overhead (LOPOH) insertion and drop. Control inputs and outputs for each internal block are speci-

fied, along with appropriate control register bit definitions.

19.2 VT/TU Mapper Fea t ure s

■Maps T1/E1/J1 into VT/TU structures:

— T1 into VT1.5/TU-1 1/TU-12.

— J1 into VT1.5/TU-11/TU-12.

— E1 into VT2/TU-12.

■Supports async hr ono us, byte- synchro nou s, and bit -sy nc hr ono us map p in gs.

■Supports automatic generation or microprocessor overwrite of one bit RDI and one bit RFI.

■Supports automatic generation or microprocessor overwrite of enhanced RDI.

■Supports ADM applications via tributary loopback and tributary pointer processing.

■Supports unidirectional path switch ring (UPSR) applications via low-order path overhead access channel.

■Supports five J2 trace identifier modes.

■Programmable BIP-2 error insertion.

■Monitors BIP-2 bit error rate.

■Programmable clear-on-read/clear-on-write registers.

■Supports automatic AIS generation for downstream devices.

■VC-BIP-2, VC -REI 1 s error counters.

■Programmable saturation or rollover of internal counters.

■Complies with GR-253-CORE, G.707, T1.105, G.704, G.783, JT-G707, GR-499, ETS 300 417-1-1.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

434 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.3 VT/TU Mapper Fu nction al Blo ck Diagr am

The following block diagram shows a high-level view of the VT/TU mapper block and the interface to the T1/E1

framer, cross connect, SPE mapper (SPEMPR), digital jitter attenuator (DJA), and control (microprocessor inter-

face).

5-9011(F)r.2

Figure 39. VT Mapper Interface Diagram

DATA

RECEIVE

TRANSMIT

RECEI VE VT / TU MAPPER

TRANS MI T VT / TU MA PPER

FRAMER

[28:1]

LOPOHDATAOUT

LOPOHDATAIN

TRIBUTARY

LOPOHCLKIN

CROSS

CONNECT

DJA

CONTROL INTERFACE

DS1XCLK

E1XCLK

LOPOHVALIDOUT

LOPOHVALIDIN

RDI-V

REI-V

RX PATH SIGNALING

TX PATH SIGNALING

SPEM PR R D I , R EI

TUG3 RDI, REI

TRANSMIT

RECEIVE

LOOPBACK

TMUX

DATA CLOCK

FSYNC ALARM

[28:1]

DATA CLOCK

FSYNC ALARM

RDI, REI PATH, AND LINE ALARMS

RDI, REI PATH, A ND LINE ALARMS

DATA CLOCK

CLOCK CONTROL

ALARM CONTROL SPE

SPEMPR

SPE

SPEMPR

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

435Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

5-9012(F)

Figure 40. VT Mapper Functional Block Diagram

TES

SOFTWARE REGISTERS

LOPOHDATAIN

LOPOHDATAOUT

LOPOHCLKIN

VTRXDATA[7:0]

RX_EN

V1TIME

VTTXDATA[7:0]

DATA[28:1]

CLK[28:1]

FSYNC[28:1]

DATA[28:1]

CLK[28:1]

FSYNC[28:1]

CLK7M_RX

CLK7M_TX

J1TIME

DS1XCLK

E1XCLK

LOPOHVALIDIN

LOPOHVALIDOUT

INSEL

AUTO_AIS[28:1]

VTPI

RX_LOPOH

J2MON

VTTERM

OUTSEL VTDEMUX

RX_VTSIG

VT LOOPBACK (VTLBSEL = 1)

VTGEN

TX_VTSIG TX_LOPOH

VTMUX

TUG3_REI[3:0]

TUG3_RDI[2:0]

RDI_L

RDI[2:0]

REI_L[4:0]

REI[3:0]

RDI[2:0]

REI[3:0]

RDI_L

RDI_P[2:0]

REI_L[4:0]

REI_P[3:0]

J0TIME

RAI[28:1]

16-BIT MICROPROCESSOR

TX_EN

DEVICE I/O

TRANSMIT PATH

DS1/E1 TO

RECEIVE PATH

DEVICE I/O

SPE MAPPER TMUX

SPE MAPPER

TMUX

DS1/E1 FROM

SIGNALING TO

FRAMERS

x28

SPE MAPPER

CROSS CONNECT

X28

X28X28X28

INTERFACE SIGNALING FROM

FRAMERS

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

436 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.4 VT/TU Mappings

Table 563. VT2/TU-12 Payload Mapping

Table 564. VT1.5/TU-11 Payload Mapping

Column X 1 2 • • • 2

2• • • 2

8X2

9• • • 4

3• • • 5

6X5

7• • • 6

4• • • 8

J1 V

• • • V

Column X 1 2 • • • 2

8X2

0• • • 5

6X5

8• • • 8

J1 V

• • • v

• • • V

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

437Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.5 VT/TU Locations

Table 565. VT2/TU-12 Locations

* This column is for the I/O of the VTMPR. The cross connect can be

provisioned to map any external E1 to any VT2.

†See Table 563 on page 436.

Table 566. VT1.5/TU-11 Locations

* This column is for the I/O of the VTMPR. The cross connect can be

provisioned to map any external DS1 to any VT1.5.

†See Table 564 on page 436.

VTG VT E1* Columns†

1 1 1 1, 22, 43, 64

2 1 2 2, 23, 44, 65

3 1 3 3, 24, 45, 66

4 1 4 4, 25, 46, 67

5 1 5 5, 26, 47, 68

6 1 6 6, 27, 48, 69

7 1 7 7, 28, 49, 70

1 2 8 8, 29, 50, 71

2 2 9 9, 30, 51, 72

3 2 10 10, 31, 52, 73

4 2 11 11, 32, 53, 74

5 2 12 12, 33, 54, 75

6 2 13 13, 34, 55, 76

7 2 14 14, 35, 56, 77

1 3 15 15, 36, 57, 78

2 3 16 16, 37, 58, 79

3 3 17 17, 38, 59, 80

4 3 18 18, 39, 60, 81

5 3 19 19, 40, 61, 82

6 3 20 20, 41, 62, 83

7 3 21 21, 42, 63, 84

VTG VT DS1* Columns†

1 1 1 1, 29, 57

2 1 2 2, 30, 58

3 1 3 3, 31, 59

4 1 4 4, 32, 60

5 1 5 5, 33, 61

6 1 6 6, 34, 62

7 1 7 7, 35, 63

1 2 8 8, 36, 64

2 2 9 9, 37, 65

3 2 10 10, 38, 66

4 2 11 11, 39, 67

5 2 12 12, 40, 68

6 2 13 13, 41, 69

7 2 14 14, 42, 70

1 3 15 15, 43, 71

2 3 16 16, 44, 72

3 3 17 17, 45, 73

4 3 18 18, 46, 74

5 3 19 19, 47, 75

6 3 20 20, 48, 76

7 3 21 21, 49, 77

1 4 22 22, 50, 78

2 4 23 23, 51, 79

3 4 24 24, 52, 80

4 4 25 25, 53, 81

5 4 26 26, 54, 82

6 4 27 27, 55, 83

7 4 28 28, 56, 84

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

438 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.6 VT/TU Mapper Rece ive Path Descrip tion

This section describes all necessary functions of the receive logic (see Figure 40, right to left):

■Virtual tributary demultiplexor (VTDEMUX)

■Virtual tributary pointer interpreter (VTPI)

■Virtual tributary terminator (VTTERM)

■Output selector (OUTSEL)

■J2 16-byte sequence monitor (J2MON)

■Receive VT/TU signaling (RX_VTSIG)

■Receive low-order path overhead (RX_LOPOH)

19.7 VT Demultiplexer (VTDEMUX)

The VTDEMUX logic block (in Figure 40 on page 435) will perform all necessary functions to decode which virtual

tributary (VT) is active on the data bus.

This block monitors the H4 byte and frames on the H4 multiframe indication. In frame (VT_H4LOMF = 0 (Table 189

on page 16 2 )) will be declared following two consecutive, nonerrored multiframe indications. A multiframe indica-

tion consists of four consecutive frames containing a (00, 01, 10, 11) pattern in the two LSBs of the H4 byte. Once

fram ed, H4 los s of m ult ifra me (V T_H4 LOM F = 1) will be de cla red fo llow ing the n umb er of cons ecut ive mism atc hes

in the H4 multiframe indication programmed into bits VT_H4_NTIME[3:0] (Table 195 on page 165). Loss of H4

multiframe alignment will generate AIS downstream. A change in H4 multiframe alignment is indicated by bit

VT_H 4 L OM F _D ( Table 181 on page 158) and will generate an interrupt unless the mask is set (VT_H4LOMF_M =

1 (Table 193 on page 164)).

Bits VT_RX_GRP_TYPE[6:0] (Table 193) are programmed to determine whether the incoming tributary is a

VT1.5/TU-11 or a VT2/TU-12.

See Table 563 on page 436, through Table 566 on page 436 through page 437, for VT/TU mapping formats.

19.8 VT Pointer Interpreter (VTPI)

The VTPI logic block (in Figu re 40 on pag e 435) will perform all necessary functions to support VT/TU pointer inter-

pretation. The following features are implemented:

The pointer interpreter consists of the following states:

■Loss-of-pointer (LOP-V)

■VT-AIS (AIS-V) (all ones in V1 and V2)

■NDF enabled (NDF) (1001, 0001, 1101, 1011, 1000)

■Normal (NORM) (disabled NDF, normal pointer)

■Increment (INC) (inverted I bits)

■Decrement (DEC) (inverted D bits)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

439Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

5-9007(F)

* This state diagram is based on the ETS 417-1-1 pointer interpretation state diagram (Figure B.1). Transiti ons of eight invalid pointers from the

INC, DEC, and NDF states into the LOP state have been added.

Figure 41. Pointer Interpretation State Diagram

■The pointer interpreter will transition into the LOP-V state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive super-

frames programmed in bits VT_NDF_NTIME[3:0] (Table 196 on page 165), then LOP-V will be declared.

— Invalid pointer values. If the number of consecutive superframes programmed in register bits

VT_INV_NTIME[3:0] (Table 196) are received with a pointer that is not a normal value, NDF, AIS-V, increment,

or decrement, then LOP-V will be declared. The SS bits contribute to an invalid pointer indication.

■The pointer interpreter will transition out of the LOP-V state based on the following conditions:

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, the pointer interpreter will

transition from the LOP-V state into the AIS-V state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

LOP-V state into the NORM state.

— The pointer interpreter does not transition from the LOP-V state into the NDF state.

■The pointer interpreter will transition into the AIS-V state based on the following conditions:

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, AIS-V will be declared.

■The pointer interpreter will transition out of the AIS-V state based on the following conditions:

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

AIS-V state into the NORM state.

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer in-

terpreter will transition from the AIS-V state into the LOP-V state.

— If NDF is enabled on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the AIS-V

state into the NDF state.

NORM

DECINC

NDF

AISLOP

FROM ALL STATES

8 INVALID POINTERS

FROM ALL STAT ES

3 NEW POINTERS

INCREMENT DECREMENT

8 NDF ENABLE

NDF ENAB L E

NDF ENABLE

NDF

3 ANY 3 ANY

3 NEW POINTERS

3 ANY POINTERS

3 NEW POINTERS

8 INVALID

8 INVALID POINTERS*

INDICATION INDICATION

3 AIS INDICATIONS ENABLE

ENABLE

POINTERS POINTERS

POINTERS ENABLE

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

440 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■The pointer interpreter will transition into the NDF state based on the following conditions:

— If NDF is enabled on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the NORM,

NDF, AIS, INC, and DEC states into the NDF state.

■The pointer interpreter will transition out of the NDF state based on the following conditions:

— Continuous NDF. If NDF (1001, 0001, 1101, 1011, 1000) is received for the number of consecutive super-

frames programmed in bits VT_NDF_NTIME[3:0] (Table 196 on page 165), the pointer interpreter will transi-

tion from the NDF state into the LOP-V state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

NDF state into the NORM state.

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, the pointer interpreter will

transition from the NDF state into the AIS-V state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

NDF state into the NORM state.

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 196), the

pointer interpreter will transition from the NDF state into the LOP-V state.

■The pointer interpreter will transition into the NORM state based on the following conditions:

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition into the

NORM state, i.e., transitioning from the INC, DEC, and NDF states.

■The pointer interpreter will transition out of the NORM state based on the following conditions:

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer in-

terpreter will transition from the NORM state into the LOP-V state.

— If NDF is enabled on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the NORM

state into the NDF state.

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, the pointer interpreter will

transition from the NORM state into the AIS-V state.

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 194 on page 164)), if 8 of the 10 I and D

bits are correct for a pointer decrement on the incoming V1 bytes and V2 bytes, the pointer interpreter will tran-

sition from the NORM state into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct

for a pointer decrement on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the

NORM state into the DEC state.

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer

increment on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the NORM state

into the INC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the

incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the NORM state into the INC state.

■The pointer interpreter will transition into the INC state based on the following conditions:

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1), if 8 of the 10 I and D bits are correct for a pointer

increment on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition into the INC state. Oth-

erwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer increment on the incoming V1 bytes and

V2 bytes, the pointer interpreter will transition into the INC state.

■The pointer interpreter will transition out of the INC state based on the following conditions:

— If NDF is enabled on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the INC

state into the NDF state.

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, the pointer interpreter will

transition from the INC state into the AIS-V state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

INC state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

INC state into the NORM state.

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0], the pointer in-

terpreter will transition from the INC state into the LOP-V state.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

441Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■The pointer interpreter will transition into the DEC state based on the following conditions:

— When operating in the 8 of 10 mode (VT_8ORMAJORITY = 1 (Table 194 on page 164)), if 8 of the 10 I and D

bits are correct for a pointer decrement on the incoming V1 bytes and V2 bytes, the pointer interpreter will tran-

sition into the DEC state. Otherwise, if 3 of the 5 I bits and 3 of the 5 D bits are correct for a pointer decrement

on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition into the DEC state.

■ The pointer interpreter will transition out of the DEC state based on the following conditions:

— If NDF is enabled on the incoming V1 bytes and V2 bytes, the pointer interpreter will transition from the DEC

state into the NDF state.

— Following three consecutive superframes with all ones in the V1 bytes and V2 bytes, the pointer interpreter will

transition from the DEC state into the AIS-V state.

— Following three new, consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

DEC state into the NORM state.

— Following any three consecutive, consistent, and valid pointers, the pointer interpreter will transition from the

DEC state into the NORM state.

— Following the number of consecutive invalid pointers programmed in bits VT_INV_NTIME[3:0] (Table 196 on

page 165), the pointer interpreter will transition from the DEC state into the LOP-V state.

Pointer increments and decrements are monitored and counted internally. The performance monitoring reset signal

transfers the count to the holding registers for pointer increment (VT_PTR_INC[1—28][3:0] (Table 221 on

page 174)), and pointer decrement (VT_PTR_DEC[1—28][3:0] (Table 221)) for microprocessor read, and rese ts

the running count registers to 0. When SMPR_SAT_ROLLOVER = 1 (Table 77 on page 70), the inte rnal running

counts will hold at their maximum value. Otherwise, the counts will roll over. The running count and holding register

counts will be forced to 0, if the SPE mapper is requesting AUTO AIS or VT_LOP[1—28] = 1 (loss-of-pointer)

(Table 190 on page 163) or VT_AIS[1—28] = 1 (VT AIS) (Table 190 on page 163), or VT_H4LOMF = 1 (loss of H4

multiframe alignment), see Table 189 on page 162.

LOP-V (VT_LOP) and AIS-V (VT_AIS) will be detected and reported to the microprocessor. Both the LOP-V and

AIS-V conditions will contribute to the VT/TU mapper automatic AIS generation that is driven over a 28-bit internal

output bus to the cross connect (XC). Any change in state of VT_LOP or VT_AIS will be reported to the micropro-

cessor via VT_LOP_D[1—28] and VT_AIS_D[1—28] (Tab le 182 on page 159). Unless the appropriate mask bit is

set (VT_LOP_M[1—28] or VT_AIS_M[1—28]) (Table 186 on page 161), VT_LOP_D[1—28] = 1 or

VT_AIS_D[1—28] = 1 will generate an interrupt.

A check for VT/TU size mismatches is performed by comparing the expected VT/TU size bits (VT1.5 = 11,

VT2 = 10) with the actual received SS bits in the V1 byte. After three consecutive mismatches, size errors will be

reported with bit VT_SIZERR[1—28] (Table 190 on page 163). Any change in state of VT_SIZERR[1—28] will be

reported with bit VT_SIZERR_D[1—28] (Table 182 on page 159). Unless the VT_SIZ ER R_M[ 1—2 8] (Table 186

on page 16 1 ) mask bit is set, VT_SIZERR_D[1—28] = 1 will generate an interrupt.

The accepted pointer is stored and accessible by the microprocessor.

This block supports tributary loopback.

19.9 VT Termination (VTTERM)

The VTTERM logic block (in Figure 40) will perform all necessary functions to support complete VT/TU termination.

The following features are implemented.

19.9.1 V5 Termination

The V5 byte is checked for BIP-2 errors. If BIP-2 errors are detected, REI-V is transmitted in the V5 byte of the cor-

responding transmit VT, if enabled by bit VT_REI_EN[1—28] = 1 (Table 211 on page 170). BIP-2 errors and recep-

tion of REI-V in the V5 byte are counted on a per-superframe basis. BIP-2 errors can counted on either a bit or

block basis selected by bit VT_BIT_BLOCK_CNT (1 = bit, 0 = block) (Table 194 on page 164).

TMXF28155 Superma pper Data Sheet

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442 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

BIP-2 errors and REI-V reception are monitored and counted internally. The performance monitoring reset signal

transfers the count to the holding registers for BIP-2 error count (VT_BIP2ERR_CNT[1—28][11:0]; Table 219 on

page 173), and REI-V count (VT_REI_CNT[1—28][10:0] (Table 220 on page 173)) for microprocessor read, and

resets the running count registers to 0. When SMPR_SAT_ROLLOVER = 1 (Table 77 on page 70), the inte r nal

running counts will hold at their maximum value. Otherwise, the counts will roll over . The running count and holding

pointer), VT_AIS[1—28] = 1 (VT AIS) (Table 190 on page 163), or VT_H4LOMF = 1 (loss of H4 multiframe align-

ment) (Table 189 on page 162).

The V5 byte will be checked for received RFI-V via VT_RFI[1—28] bits (Table 190 on page 163). New values will

be latched into the register after the number of consecutive values programmed in bits VT_RDI_NTIME[3:0]

(Table 197 on page 166) have been received. A VT_RFI[1—28] change of state is reported by bit VT_RFI_D[1—

28] (Table 182). When operating in the DS1 byte-synchronous mode, RFI-V = 1 will force DS1 RAI downstream to

the framer . Unless the VT_RFI_M mask bit (Table 186 on page 161) is set, VT_RFI_D[1—28] = 1 will generate and

cause an interrupt.

When operating in normal RDI-V mode (VT_RX_ERDI_EN[1—28] = 1 (Table 217, starting on page 172)), the V5

byte will be checked for received RDI-V and reported via VT_RDI[1—28] bits (Table 190 on page 163). New values

will be latched to this register after VT_RDI_NTIME[3:0] consecutive values have been received. A VT_RDI[1—28]

change of state is reported via VT_RDI_D[1—28] (Table 182 on page 159). Unless the VT_RDI_M[1—28]

(Table 186) mask bit is set, VT_RDI_D[1—28] = 1 will generate and cause an interrupt.

When operating in enhanced RDI-V mode (VT_RX_ERDI_EN[1—28] = 0 (Table 217, starting on page 172)), the

V5 byte will be checked for received RDI-V and reported via VT_RDI[1—28] bit (Table 190 on page 163). New val-

ues will be latched to this register after VT_ERDI_NTIME[3:0] (Table 197 on page 166) consecutive ERDI-V values

(V5 bit 8 and Z7 bits 5—7) have been received. A VT_ERDI[1—28][2:0] change of state is reported via

VT_ERDI_D[1—28] (Table 182). Unless the VT_ERDI_M[1—28] mask bit (Tab le 186 on page 161) is set,

VT_ERDI_ D[1— 28] = 1 will gen er ate and ca us e an interr upt.

The V5 byte VT/TU signal label will be monitored and reported to the microprocessor using bits

VT_LAB[1—28][2:0] (Table 190 on page 163). New values will be latched to the microprocessor after the number

of consecutive values programmed in bits VT_LAB_NTIME[3:0] (Table 197 on page 166) has been received. An

all- zeros signal label will set bit VT_UNEQ[1—28] (Table 190). Any change in state of VT_UNEQ[1—28] will be

reported to the microprocessor via bit VT_UNEQ_D[1—28] (Table 182 on page 159). Unless the VT_UNEQ_M[1—

28] (Table 186 on page 161) mask bit is set, VT_UNEQ_D[1—28] = 1 will generate an interrupt. VT_UNEQ[1—28]

will contribute to automatic AIS generation. The latched signal label will be compared to the expected signal label.

If the expected signal label is 001 or if VT_UNEQ[1—28] is detected, the detection of PLM-V is disabled. Other-

wise, any mismatch is reported to the microprocessor via bit VT_PLM[1—28] (Table 190). Any change in state of

VT_PLM[1—28] will be reported to the microprocessor via bit VT_PLM_D[1—28] (Table 182). Unless the

VT_PLM_M[1—28] mask bit is set (Table 186), VT_PLM_D[1—28] = 1 will generate an interrupt.

19.9.2 Z6 /N2 Termination

For SONET applications, the Z6 byte is monitored and presented to the microprocessor using bits

VT_Z6_BYTE[1—28][7:0] (Table 218 on page 173) for growth and monitoring purposes only. The Z6 byte is

updated when three consecutive consistent bytes are received. N2 is defined for tandem connection applications

per ETS 300 417-1-1 and ITU-T G.707/G.783. Low-order tandem connection is not supported.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

443Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.9.3 Z7 /K4 Termination

This termination will support enhanced RDI when bit VT_RX_ERDI_EN[1—28] = 1 (Table 217, starting on

page 172). The Z7/K4[3:1] byte will be monitored and reported to the microprocessor with bits

VT_ERDI[1—28][2:0] (Table 190 on page 163). New values will be latched to the microprocessor after the number

of consecutive values programmed in register bits VT_ERDI_NTIME[3:0] (Table 197 on page 166) has been

received. A change of state is reported using bit VT_ERDI_D[1—28] (Table 182 on page 159). Unless the

VT_ERDI_M[1—28] (Table 186 on page 161) mask bit is set, VT_ERDI_D[1—28] = 1 will generate an interrupt.

The Z7/K4[7:4] byte will be monitored and reported to the microprocessor via bits VT_APS[1—28][3:0] (Table 191

on page 16 3 ). New values will be latched to the microprocessor after the number of consecutive values pro-

grammed in bits VT_APS_NTIME[3:0] (Tabl e 197 on page 166) has been received. A change of state is reported

using bit VT_APS_D[1—28] (Table 182). Unless the VT_APS_M[1—28] (Table 186) mask bit is set,

VT_APS_D[1—28] = 1 will generate an interrupt.

19.9.4 Pay lo ad Terminatio n

Payload termination will support asynchronous, byte-synchronous, and bit-synchronous demappings for SONET

VT1.5s and VT2s per Bellcore GR-253 and ANSI T1.105.

Payload termination will support asynchronous, byte-synchronous, and bit-synchronous demappings for

SDH TU11s and TU12s per ITU-T G.707 and ETS 300 417-4-1.

Demapping modes are selected with bits VT_RX_MAPTYPE[1—28][3:0] (Table 217, starting on page 172), as

defined in Table 567.

Table 567. Receive VT/TU Demapping Selection

The payload termination provides an elastic store for rate adoption. An elastic store overflow is indicated in bit

VT_RX_ESOVFL_D[1—28] (Table 182 on page 159). Unless the VT_RX_ESOVFL_M[1—28] mask bit is set

(Table 186 on page 161), VT_RX_ESOVFL_D[1—28] = 1 will generate an interrupt.

When an overflow condition exists, the read/write count will be forced to the center of the FIFO. The FIFO is 64 bits

deep.

The payload termination circuitry will generate a gapped DS1/E1 clock (VT_TERM_CLK). Figure 42 and Figure 43

on page 45 8 describe the DS1 and E1 gapped clocking schemes, respectively. A frame sync is generated and

transmitted from the device coincident with the frame bit for DS1 and the MSB of time slot 0 for E1 when demap-

ping a byte-synchronous payload.

VT_RX_MAPTYPE[1—28][3:0] (See Tab le 217 on page 172.)Description

0 0 0 0 Asynchronous VT1.5/TU-11 (DS1 output)

0 0 0 1 Asynchronous VT2/TU-12 (E1 output)

0 0 1 0 Byte-Synchronous VT1.5/TU-11 (DS1 output)

0 0 1 1 Byte-Synchronous VT2/TU-12 (E1 output)

0 1 0 0 Bit-Sy nc hrono us VT1. 5/TU- 11 (DS1 output)

0 1 0 1 Bit-Synchronous VT2/TU-12 (E1 output)

0110—0111 Undefined, Generates AIS

1 0 0 0 Asynchronous VT2/TU-12 (DS1 output)

1 0 0 1 Byte-Synchronous VT2/TU-12 (DS1 output)

1 0 1 0 Bit-Synchronous VT2/TU-12 (DS1 output)

1011—1111 Undefined, Generates AIS

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

444 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.10 Output Signal Selection (OUTSEL)

The OUTSEL logic block (in Figure 40 on page 435) will perform all necessary functions to overwrite the outgoing

DS1/E1 signals with the appropriate AIS clock, data, and frame synchronization.

VT/TU mapper automatic AIS, which is driven over a 28-bit internal output bus to the cross connect (XC), is gener-

ated according to the following equation:

SPEMPR_AUTO_AIS

VT_LOP[1—28]

VT_AIS[1—28]

(VT_H4LOMF and (VT_LOMF_AIS_INH))

(VT_UNEQ [1— 28] and (V T _UNEQ _A IS_ INH))

(VT_PLM[1—28] and (VT_PLM_AIS_INH))

(VT_J2TIM[1—28] and (VT_J2TIM_AIS_INH))

(VT_LOPS[1—28] and VT_LOPS_AIS_INH))

The output of the VT/TU mapper receive path will be as shown in Figure 44 on page 458 and Figure 45 on

page 459.

19.11 J2 Byte Monitor and Termination (J2M ON)

The J2MON logic block (in Figure 40 on page 435) will perform all necessary functions to monitor the incoming J2

trace identifier. The following features are implemented:

■J2 monitoring will support five different monitoring modes defined by VT_J2MON_MODE[1—28][2:0]; see

Table 217 on page 172:

— VT_J2MON_MODE[1—28][2:0] = 000: this mode captures an incoming 16-byte sequence and stores it in

VT_J2BYTE_DET[1—28][1—16][7:0] (Table 222 on page 174). TIM-V is disabled for this mode.

— VT_J2MON_MODE[1—28][2:0] = 001: this mode captures an incoming 16-byte sequence with SDH framing

and stores it in VT_J2BYTE_DET[1—28][1—16][7:0]. TIM-V is disabled for this mode.

— VT_J2MON_MODE[1—28][2:0] = 010: this mode captures a constant 1-byte sequence and stores it in

VT_J2BYTE_DET[1—28][1][7:0]. TIM-V is disabled for this mode.

— VT_J2MON_MODE[1—28][2:0] = 011: this mode monitors a 16-byte sequence with SDH framing and com-

pares it to a programmable expected value. The expected value is programmed by the user using register bits

VT_J2BYTE_EXP[1—28][1—16][7:0] (Table 222). The hardware frames by looking for the byte with the MSB

set to one, which indicates that the next byte is the second byte of the message. CRC is verified based on the

value programmed in VT_J2BYTE_EXP[1—28][1—16][7:0]. TIM-V is enabled for this mode.

— VT_J2MON_MODE[1—28][2:0] = 100: this mode monitors a constant 1-byte sequence and compares it to a

programmable expected value. The expected value is programmed by the user using register bits

VT_J2BYTE_EXP[1—28][1][7:0]. TIM-V is enabled for this mode.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

445Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■Trace identifier mismatch (TIM-V) will be detected following the number of consecutively errored sequences

(1-byte or 16-byte sequences) programmed in bits VT_J2_NTIME[3:0] (Table 196 on page 165), and reported to

the microprocessor via bit VT_J2TIM[1—28] (Tab le 190 on page 163). If TIM-V is detected, the J2 byte monitor

will transition into the capture mode and start searching for two consecutive consistent 1-byte or 16-byte

sequences. Once two consecutive consistent sequences are detected, the J2 byte monitor will transition into the

monitor mode and start searching for the number of consecutive mismatches programmed in register bits

VT_J2_NTIME[3:0] on a per 1-byte or 16-byte sequence basis. Once the hardware finds synchronization

(VT_J2TIM[1—28] = 0), the new sequence is latched into VT_J2BYTE_DET[1—28][1—16][7:0] (Table 222 on

page 174). The synchronization algorithm used will not allow single bit errors to pass through to

VT_J2BYTE_DET[1—28][1—16][7:0].

■Unless bit VT_J2TIM_AIS_INH (Table 194 on page 164) is set to a 1, VT_J2TIM[1—28] will contribute to auto-

matic AIS generation.

■Any change in sta te of VT_J2TIM[1—28][1—16][7:0] will be reported in bit VT_J2TIM_D[1—28] (Table 182 on

page 159). Unless the VT_J2TIM_M[1—28] (Table 186 on page 161) mask bi t is set, VT_J2TIM_D[1—28] = 1

will generate an interrupt.

19.12 Receive Signaling (RX_VTSIG)

The RX_VTSIG logic block (in Figure 40 on page 435) will perform all necessary function s to extract and transmit

the received signaling bits when operating in DS1 byte-synchronous mode. The following features are imple-

mented:

■The signaling is sent to the appropriate framer link selected by bits VT_RXSIG_CH_SEL[1—28][4:0] (Table 217

on page 172). VT_RXSIG_CH_SEL[1—28][4:0] is a necessary duplication of the routing information pro-

grammed with in the cros s co nne ct (X C) bloc k.

■When VT_SYNC_PBIT[1—28] = 1 (Table 217 on page 172), the RX_VTSIG block will synchronize to the incom-

ing VT/TU phase indication (P1, P0). Otherwise, VT_LOPS[1—28] (Table 190 on page 163) and

VT_LOPS_D[1—28] (Table 182 on page 159) will be forced to 0.

■P-bit phase synchronization (VT_LOPS[1—28] = 0) is declared following two consecutive nonerrored multi-

frames (48 frames). Loss of phase synchronization (VT_LOPS[1—28] = 1) is declared following the number of

consecutive errored multiframes programmed in bits VT_LOPS_NTIME[3:0] (Table 195 on page 165). Any

change in VT_LOPS[1—28] state will be detected and reported to the microprocessor with bit VT_LOPS_D[1—

28].

■If the loss of phase synchronization (VT_LOPS[1—28] = 1) condition exists and VT_LOPS_AIS_INH = 0, DS1

AIS is transmitted downstream and the signaling bits will be forced to the value in SMPR_OH_DEFLT (Table 77

on page 70) in the MPU block. Otherwise (VT_LOPS[1—28] = 0), the VT_RX_VTSIG logic block will behave as

described in Table 568.

■Unless VT_LOPS_M[1—28] (Table 186 on page 161) mask bit is set, VT_LOPS_D[1—28] will generate an inter-

rupt.

■See Table 568 for signaling behavior based on the receive status and control.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

446 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 568. Rx Signaling Behavior Per Channel

* If the P1 bits and P 0 bits are not used for phase indication and the F bit is not passed transparently, the F bit is overwritten with the appropri-

ate SF or ESF framing pattern based on a random starting position. Robbed-bit signaling will not be accessible under such a condition.

† When operating in the ESF mode, the Ft bits will be overwritten with the ESF frame and the C bits and M bits passed transparently.

19.13 Receive Lower-Order Path Overhead (RX_LOPOH)

The RX_LOPOH logic block (in Figure 40 on page 435) will perform all necessary functions to store and transmit

the overhead associated with each VT/TU, specifically, V5, J2, Z6/N2, Z7/K4, and the O bits. The following fea-

tures will be implemented:

■V5, J2, Z6/N2, Z7/K4, and the 0 bits, on a per-VT basis, are stored for one complete superframe and transmitted

during the next superframe. REI and RDI values received from the SPEMPR and TMUX are stored on a per-

frame basis and transmitted during the next frame. REI and RDI values are latched during the A1 time of the

receiv ed SO NET fra me.

■When operating in UPSR mode (bit VT_UPSR = 1 (Table 186 on page 161)), REI, RDI, and ERDI values in the

V5 and Z7 bytes will be modified based on the receive status. See Table 573 on page 451 for automatic genera-

tion requirements.

■The REI and RDI received from the SPEMPR and TMUX blocks is the first data type transmitted in each frame

as a burst of 34 bits on the rising edge of the SPE mapper Rx clock (6.48 MHz). All other data types are transmit-

ted as a burst of 224 bits on the rising edge of the SPE mapper Rx clock.

Note: The number of valid bits transmitted is dependent upon the VT/TU group types, i.e., full VT2 equals 168 bits.

■The first frame of the four frame multiframe contains data types 001, 010, 01 1, and 100, respectively. The second

frame of the multiframe contains data types 001, 101, and 110, respectively. The remaining frames contain only

data type 001. Data type headers will be defined as shown in Table 569 on page 447.

All data types must be transmitted within 500 µs.

VT_SYNC_PBIT

[1—28] VT_WR_FBIT

[1—28] VT_SF_ESF

[1—28] VT_LOPS

[1—28] Action

See Table 217 on page 172. See Table 190 on

page 163.—

0 0 X X Pass F-bit transparently.

0 1 0* X Overwrite outgoing F bit with ESF pattern.

0 1 1 X Overwrite outgoing F bit with SF pattern.

0†0 Overwrite outgoing F bit with ESF pattern.

1 1 1 0 Overwrite outgoing F bit with SF pattern.

1 X X 1 Transmit DS1 AIS downstream.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

447Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 569. Data Type Header Definitions

* All overhead bytes will be transmitted from MSB to LSB.

† O bits are received in the byte following J2 and the byte following Z6/N2 in asynchronous mode. The O bits will be transmitted in the order in

which they are received within a VT, starting with the MSB of the nibble following the J2 byte.

Figure 46 on page 459 contains the RX_LOPOH block serial channel format and timing.

19.14 VT/TU Mapper Transmit Path Requireme nts

This section describes all necessary functions of the transmit logic (see Figure 40 on page 435, left to right).

■ Input selector (INSEL)

■ Transmit elastic store (TES)

■ Virtual tributary generator (VTGEN)

■ Virtual tributary multiplexer (VTMUX)

■ Transmit DS1/E1 signaling (TX_VTSIG)

■ Transmit low-order path overhead (TX_LOPOH)

19.14.1 Input Selector (INSEL)

The INSEL logic block (in Figure 40 on page 435) will perform loss of clock (LOC), AIS, and loss of frame sync

detection. The following features will be implemented:

■The incoming DS1/E1 signal will be retimed immediately using the selected DS1/E1 clock edge

(VT_TX _CLK ED GE [1— 28] (Table 211 on page 170)). If VT_TX_CLKEDGE[1—28] = 1, the rising edge of the

incoming DS1/E1 CLOCK is used to retime the signal; otherwise, the falling edge is used.

■The incoming DS1/E1 signals will be checked for a digital loss of clock (LOC) condition and reported with bit

VT_TX_LOC[1—28] (Table 192 on page 163). Any change in state of VT_TX_LOC[1—28] will be reported to the

microprocessor via bit VT_TX_LOC_D[1—28] (Tab le 184 on page 160). Unless the VT_TX_LOC_M[1—28]

(Table 188 on page 162) mask bit is set, VT_TX_LOC_D = 1 will generate an interrupt.

■If LOC is detected (VT_TX_LOC[1—28] = 1), DS1/E1 AIS will be inserted in the appropriate transmit path VT.

DS1/E1 AIS consists of a valid VT/TU pointer, valid VT/TU overhead, and an all-ones payload.

■In the byte-synchronous mode, the incoming DS1/E1 frame sync is monitored for the loss of frame sync condi-

tion (LOFS) and reported in bit VT_LOFS[1—28] (Table 192 on page 163). In frame sync, (VT_LOFS[1—28] = 0)

is declared following three consecutive valid frame sync pulses (375 µs). Loss of frame sync (VT_LOFS[1—28] =

1) is declared following six consecutive frame sync mismatches (750 µs). Any change in state of VT_LOFS[1—

28] will be reported in bit VT_LOFS_D[1—28] (Table 184 on page 160). Unless the VT_LOFS_M[1—28]

(Table 188 on page 162) mask bit is set, VT_LOFS_D[1—28] = 1 will generate an interrupt.

■If LOFS is detected (VT_LOFS[1—28] = 1), AIS-V is inserted in the appropriate VT location. AIS-V consists of

writing an all-ones pattern into the entire VT, including V1~4.

Header Description

0 0 0 Reserved.

0 0 1 TMUX and SPE mapper RDI/REI.

0 1 0 V5 byte, 28/21 bytes starting with VT 1*.

0 1 1 J2 byte, 28/21 bytes starting with VT 1.

1 0 0 Z6/N2 byte, 28/21 bytes starting with VT 1.

1 0 1 Z7/K4 byte, 28/21 bytes starting with VT 1.

110

O bits, 28/21 bytes starting with VT 1†.

1 1 1 Reserved. Data will be ignored.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

448 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■The incoming DS1/E1 signal will be checked for the AIS condition and reported in bit VT_TX_AIS[1—28]

(Table 192 on page 163). Any change in state of VT_TX_AIS[1—28] is reported in bit VT_TX_AIS_D[1—28]

(Table 184). Unless the VT_TX_AIS_M[1—28] (Table 188 on page 162) mas k b it i s s et , V T_T X_ AI S_ D[ 1— 2 8] =

1 will generate an interrupt.

■If the incoming data is DS1, AIS will be declared if there are less than 9 zeros out of 8192 clock periods. If the

incoming data is E1, AIS will be declared if there are less than three zeros in each of two consecutive 512-bit

periods, and cleared when each of two consecutive 512-bit periods contains more than two zeros.

Transmit mapping modes are shown in Table 570.

Table 570. Transmit VT/TU Mapping Selection Per Channel, VT_TX_MAPTYPE[1—28][3:0]

19.14.2 Transmit Elastic Store (TES)

The TES logic block (in Figure 40 on page 435) will perform all functions necessary to synchronize the incoming

DS1/E1 or VT1.5/VT2 signals to the local STS-1/STS-3 clock.

■This logic block will support the following modes of operation:

— Asynchronous, bit-synchronous, and byte-synchronous mapping from DS1/E1 input.

— Asynchronous, bit-synchronous, and byte-synchronous mapping from loopback VT1.5/VT2 input.

The TES logic block has programmable stuffing thresholds. The value programmed in the VT_HIGH_THRES[6:0]

(Table 223 on page 174) controls positive justification. The value programmed in the VT_LOW_THRES[6:0]

(Table 223) controls negative justification. The recommended values for nontributary loopback (VT_LB_SEL[1—

28] = 0 (Table 211 on page 170)) are VT_HIGH_THRES[6:0] = 0x28 and VT_LOW_THRES[6:0] = 0x27. Otherwise

(VT_LB_SEL[1—28] = 1), the recommended values are VT_HIGH_THRES[6:0] = 0x05 and VT_LOW_THRES[6:0]

= 0x04.

The TES logic block monitors for elastic store overflow conditions and reports with bit VT_TX_ESOVFL_E[1—28]

(Table 184 on page 160). Unless the VT_TX_E SO VFL _M[ 1—2 8] (Table 188 on page 162) mask bit is set,

VT_TX_ESOVFL_E[1—28] = 1 will generate an interrupt.

VT_TX_MAPTYPE[1—28][3:0]

(See Table 211 on page 170.) Description

0 0 0 0 Asynchronous VT1.5/TU-11 (DS1 input).

0 0 0 1 Asynchronous VT2/TU-12 (E1 input).

0 0 1 0 Byte-Synchronous VT1.5/TU-11 (DS1 input).

0 0 1 1 Byte-Synchronous VT2/TU-12 (E1 input).

0 1 0 0 Bit-Synchr ono us VT1.5/T U- 11 (DS1 input) .

0 1 0 1 Bit-Synchronous VT2/TU-12 (E1 input).

0110—0111 Undefined, Generates VT1.5/TU-11 UNEQ-V.

1 0 0 0 Asynchronous VT2/TU-12 (DS1 input).

1 0 0 1 Byte-Synchronous VT2/TU-12 (DS1 input).

1 0 1 0 Bit-Synchronous VT2/TU-12 (DS1 input).

1011—1111 Undefined, Generates VT2/TU-12 UNEQ-V.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

449Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.14.3 Virtual Tributary Generator (VTGEN)

The VTGEN logic block (in Figure 40 on page 435) performs all functions necessary to map all possible DS1/E1

inputs to the appropriate VT/TU structure. This includes VT/TU pointer generation, positive/negative stuffing,

VT/TU overhead generation/insertion, and DS1/E1 data insertion. The following features will be implemented:

■This logic block will support the following modes of operation:

— Asynchronous

— Byte-synchronous

— Bit-synchronous

19.14.4 Pointer Generation

■The pointer generator will support the following features when operating in asynchronous or bit-synchronous

mode:

— If transmit AIS-V is not requested, the following requirements apply:

1. A fixed pointer value of decimal 78 is generated for VT1.5/TU-11 mappings.

2. A fixed pointer value of decimal 105 is generated for VT2/TU-12 mappings.

3. The VT size field will be set to binary 11 for VT1.5/TU-11 mappings.

4. The VT size field will be set to binary 10 for VT2/TU-12 mappings.

5. The new data flag (NDF) is set to binary 0110 for VT1.5/VT2 mappings.

6. V3 and V4 are set to the selected overhead default (SMPR_OH_DEFLT (Table 77 on page 70) in the

microprocessor interface block) for all mappings:

— If transmit AIS-V is requested, V1~V4 will be forced to 0xFF.

— Bit stuffing, using the C and S bits, will be performed based on the fullness of the elastic store.

■The pointer generation will support the following features when operating in byte-synchronous mode:

— If transmit AIS-V is not requested, the following requirements apply:

1. The pointer value is generated based on the location of the incoming frame sync for VT1.5/VT2 mappings.

2. The VT size field is set to 11 for VT1.5/TU-11 mappings.

3. The VT size field is set to 10 for VT2/TU-12 mappings.

4. The new data flag (NDF) is set to 0110 for normal VT1.5/VT2 mappings. If an NDF is requested, the NDF

will be set to 1001 (binary) .

5. If an increment is requested, the pointer bytes, V1 and V2, are programmed with the I bits inverted. The

pointer action byte, V3, will be programmed to the selected default (microprocessor bit

SMPR_FXD_STFF_DEFLT (Table 77 on page 70)), as well as the byte directly following V3. However,

when incrementing from 139 to 0 for VT2 mapping, the pointer generator sends out NDF-V indication with

the correct pointer (0) instead of the increment indication.

6. If a decrement is requested, the pointer bytes, V1 and V2, will be programmed with the D bits inverted. The

pointer action byte, V3, will be programmed to actual customer data. However, when decrementing from 0

to 139 for VT2 mapping, the pointer generator sends out NDF-V indication with the correct pointer (139)

instead of the decrement indication.

7. The V4 byte will be programmed to the selected overhead default (microprocessor bit SMPR_OH_DEFLT)

for all mappings.

— If transmit AIS-V is requested, V1~V4 will be forced to 0xFF.

Overhead Byte Generation (V5, J2, Z6/N2, Z7/K4, and O Bits). This portion of the VTGEN logic block will gener-

ate and insert the V5, J2, Z6/N2, and Z7/K4 overhead bytes into the appropriate virtual tributary. O bits are only

accessible in the asynchronous and bit-synchronous modes.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

450 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

V5 Overhead Byte Format/Generation. The V5 overhead byte will be mapped as defined in Table 571.

Tab le 571. V5 Ov erh e ad Byte For mat

The following features are supported:

■When operating in tributary loopback mode (bit VT_LB_SEL[1—28] = 1 (Tab le 211 on page 170)), all bits are

simply passed through transparently.

■When operating in UPSR mode VT_V5_INS[1—28] = 1 (Table 212 on page 171), only a new BIP-2 and signal

label is generated and inserted while all other bits are programmed from the received LOPOH serial access

channel storage. BIP-2 will be automatically calculated and inserted. The signal label is determined based on

bits VT_TX_MAPTYPE[1—28][3:0] (Table 211) and automatically inserted.

■AIS-V is forced by setting bit VT_AIS_INS[1—28] (Table 211) to a 1. AIS-V consists of overwriting the entire VT,

including V1~4, with all ones.

■Bits VT_TX_MAPTYPE[1—28][3:0] may be programmed to insert an UNEQ-V signal label. See Table 574 on

page 451.

■User-controlled bits VT_BIP2ERR_INS[1—28][1:0] (Table 212) will force BIP-2 errors for troubleshooting pur-

poses. See Table 572 for er ror insertion modes.

Table 572. BIP-2 Error Insertion Modes

■When operating in UPSR mode VT_V5_INS[1—28] = 1, REI-V is set to the value in the received LOPOH serial

access channel storage when enabled by bit VT_REI_EN[1—28] =1 (Table 211 on page 170). When operating

in normal mode VT_V5_INS[1—28] = 0, REI-V is set to 1 for any detected BIP-2 errors in the corresponding

received VT when enabled by bit VT_REI_EN = 1. Otherwise, the REI-V bit is set to 0.

■RFI-V is supported. Manual control of the RFI-V bit is enabled with bit VT_RFI_EN[1—28] = 1 (Table 211). The

RFI-V bit is programmed with the value of bit VT_RFI_INS[1—28] (Table 213 on page 171). When

VT_RFI_EN[1—28] = 0 and operating in UPSR mode VT_V5_INS[1—28] = 1, RFI-V is set to the value in the

received LOPOH serial access channel storage. Otherwise, RFI-V is automatically generated and inserted as

defined in Table 573 on page 451. When operating in byte-synchronous mode, RFI-V is also based on the

incoming DS1 RAI from the framer.

■One bit RDI-V is supported when bit VT_TX_ERDI_EN[1—28] = 0 (Table 211). Manual control of the RDI-V bit is

enabled with bit VT_RDI_EN[1—28] = 1 (Table 211). The RDI_V bit is programmed with the value of bit

VT_RDI_INS [1— 28] ( Table 213). When VT_RDI_EN[1—28] = 0 and is operating in UPSR mode

VT_V5_INS[1—28] = 1 (Table 212), RDI-V is set to the value in the received LOPOH serial access channel stor-

age. Otherwise, RDI-V is automatically generated and inserted as defined in Table 573.

Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8

BIP-2 REI-V RFI-V SIGNAL LABEL RDI-V

VT_BIP2ERR_INS[1—28][1:0]

(See Table 212 on page 171.) Action

00 No BIP-2 errors inserted.

01 Insert continuous BIP-2 errors.

10 Insert BIP-2 errors based on microprocessor register bit

SMPR_BER_INSRT (Table 75 on page 68).

11 No BIP-2 errors inserted.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

451Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■Enhanced RDI will be supported when bit VT_TX_ERDI_EN[1—28] = 1. Manual control of the ERDI bits 5, 6,

and 7 of the Z7 byte is enabled with bit VT_ERDI_EN[1—28] = 1 (Table 211 on page 170). The ERDI bits, in bit

positions 5, 6, and 7 of the Z7 byte are programmed with the value of bits VT_ERDI_INS[1—28][2:0] (Table 213

on page 171), respectively. When VT_ERDI_EN[1—28] = 0 and is operating in UPSR mode VT_V5_INS[1—28]

= 1 (Table 212 on page 171), ERDI-V is set to the value in the received LOPOH serial access channel storage.

Otherwise, bits 5, 6, and 7 of the Z7 byte are automatically generated and inserted as defined in Table 573.

Table 573. RDI-V, RFI-V, and REI-V Automatic Generation

■The signal label will be automatically generated based on bits VT_TX_MAPTYPE[1—28][3:0] (Table 211 on

page 170) . The va lue s sup porte d are defi ned in Table 574.

Remote Er ro r Indic at io n

REI-V Anomaly/defect

0 No BIP-2 errors detected.

1 BIP-2 errors detected.One-Bit Remote Failure Indication

RFI-V Anomaly/defect

0 No alarms.

1 AIS-V, LOP-V, UNEQ-V, PLM-V or automatic AIS detected from SPEMPR.

One-Bit Remote Defect Indication

RDI-V Anomaly/defect

0 No alarms.

1 AIS-V, LOP-V, UNEQ-V, or TIM-V.

Enhanced Remote Defect Indication (Bellcore GR-253)

RDI-V

(V5 bit 8) RDI-V

(Z7 bit 5) RDI-V

(Z7 bit 6) RDI-V

(Z7 bit 7) Anomaly/Defect

0 001No defects.

0 0 1 0 PLM-V (VT payload mismatch).

1 1 0 1 AIS-V or LOP-V.

1 1 1 0 UNEQUIP-V or TIM-V.

Table 574. VT Signal Label Definition

V5(5) V5(6) V5(7) Description

0 0 0 Unequipped

0 0 1 Equipped Nonspecific

0 1 0 Asynchronous DS1

0 1 0 Asynchronous E1

0 1 1 Bit-Sy nchr ono us DS1

0 1 1 Bit-Sy nc hrono us E1

1 0 0 Byte-Synchronous DS1

1 0 0 Byte-Synchronous E1

Others Undefined

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

452 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

J2 Overhe ad Byte Inser ti on. Three modes of programming the J2 byte, as defined in Table 575, will be sup-

ported.

Table 575. J2 Overhead Byte Insertion Modes Per Channel

Z6/N2 Overhead Byte Insertion. The modes of programming the Z6/N2 byte, defined in Table 576, are sup-

ported.

Table 576. Z6/N2 Overhead Byte Insertion Modes Per Channel

Z7/K4 Overhead Byte Insertion. Three modes of programming the Z7/K4 APS bits are supported and controlled

by register bits VT_Z7_INS[1—28][1:0], as defined in Table 577.

Table 577. Z7/K4 Overhead Byte Insertion Modes Per Channel

Note: When bits Z7_INS[1—28][1:0] = 01, the APS bits in the Z7/K4 byte (bits 1:4) are based on

VT_APS_INS [1—28][3:0] (Table 213 on page 171), while Z7/K4 bits 5:7 are either automatically inserted

(when VT_ERDI_EN[1—28] = 0 (Table 211 on page 170) and VT_TX_ERDI_EN[1—28] = 1 (Table 211 on

page 170), or inserted based on VT_ERDI_INS[1—28][2:0] (Table 213 on page 171) (when

VT_ERDI_EN[1—28] = 1). In all other modes, all bits are overwritten.

VT_J2_INS[1—28][1:0]

(See Table 212 on page 171.) Insertion Mode

00 Default based on SMPR_OH_DEFLT (Table 77 on page 70).

01 Microprocessor insert (VT_J2BYTE_INS[1—28][1—16][7:0]; see Table 216 on

page 172).

10 LOPOH serial access channel insert.

11 Default based on SMPR_OH_DEFLT.

VT_Z6_INS[1—28][1:0]

(See Table 212 on page 171.) Insertion Mode

00 Default based on SMPR_OH_DEFLT.

01 Insert from bits VT_Z6BYTE_INS[1—28][7:0] (Tab le 214 on page 171).

10 LOPOH seri al access channel insert.

11 Reserved.

VT_Z7_IN S[1—28][1:0]

(See Table 212 on page 171.) Insertion Mode

00 Default based on microprocessor bits SMPR_OH_DEFLT (Table 77 on page 70).

01 Insert from bits VT_APS_INS[1—28][3:0] (Table 213 on page 171) and

VT_ERDI_INS[1—28][2:0] (Table 213).

10 LOPOH serial access channel insert.

11 Default based on microprocessor bits SMPR_OH_DEFLT.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

453Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

O-Bit Insertion (Asynchronous/Bit-Synchronous Modes Only). Three modes of programming the O bits,

defined in Table 578 will be supported.

Table 578. O-Bit Insertion Modes Per Channel

VT Mappings. Detailed mapping formats are shown in Table 579 through Table 585, where:

I = information bit.

O = overhead bit.

R = fixed stuff bit.

P = phase bit.

S = signaling bit.

F = frame bit.

S1, S2 = stuff bits.

C1, C2 = stuff indication bits.

V5 = VT overhead byte.

J2 = VT path trace byte.

Z6/N2 = growth/t and em byte.

Z7/K4 = ERDI/APS byte.

V1, V2 = pointer bytes.

V3 = pointer action byte.

V4 = reserved.

VT_O_INS[1—28][1:0]

(See Table 212 on page 171.) Insertion Mode

00 Default based on microprocessor bits SMPR_OH_DEFLT.

01 Insert from bits VT_OBIT_INS[1—28][7:0] (Table 214 on page 171).

10 LOPOH serial access channel insert.

11 Default based on microprocessor bits SMPR_OH_DEFLT.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

454 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 579. Asynchronous VT1.5

* R—value based on

SMPR_FXD_STFF_ DEFLT (Table 77 on

page 70).

Table 580. Bit-Synchronous VT1.5

* R—value based on

SMPR_FX D_ST FF_DE F LT (Table 77 on

page 70).

Table 581. Byte-Synchronous VT1.5

* R—value based on

SMPR_FX D_ST FF_DE F LT (Table 77 on

page 70).

RRRRRRIR*

Byte 1

Byte 24

C1C2OOOOIR

Byte 1

Byte 24

Z6/N2

C1C2OOOOIR

Byte 1

Byte 24

Z7/K4

C1C2RRRS1S2R

Byte 1

Byte 24

10RRRRIR*

Byte 1

Byte 24

10OOOOIR

Byte 1

Byte 24

Z6/N2

10OOOOIR

Byte 1

Byte 24

Z7/K4

10RRRRIR

Byte 1

Byte 24

P1P0S1S2S3S4FR*

Byte 1

Byte 24

P1P0S1S2S3S4FR

Byte 1

Byte 24

Z6/N2

P1P0S1S2S3S4FR

Byte 1

Byte 24

Z7/K4

P1P0S1S2S3S4FR

Byte 1

Byte 24

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

455Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 582. Asynchronous VT2

* R—value based on

SMPR_FXD_STFF_DE F LT (Table 77 on

page 70).

Table 583. Bit-Synchronous VT2

* R—value based on

SMPR_FX D_ST FF_DE F LT (Table 77 on

page 70).

Table 584. Byte-Synchronous VT2

* R—value based on

SMPR_FX D_ST FF_DE F LT (Table 77 on

page 70).

RRRRRRRR*

Byte 1

Byte 32

RRRRRRRR

C1C2OOOORR

Byte 1

Byte 32

RRRRRRRR

Z6/N2

C1C2OOOORR

Byte 1

Byte 32

RRRRRRRR

Z7/K4

C1C2RRRRRS1

S2 Byte 1[6:0]

Byte 32

RRRRRRRR

10RRRRRR*

Byte 1

Byte 32

RRRRRRRR

10OOOORR

Byte 1

Byte 32

RRRRRRRR

Z6/N2

10OOOORR

Byte 1

Byte 32

RRRRRRRR

Z7/K4

10RRRRRR

Byte 1

Byte 32

RRRRRRRR

P1P0RRRRRR*

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

Z6/N2

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

Z7/K4

P1P0RRRRRR

Channels 1—15

Superframer

Alignment/Signal

Channels 16—30

RRRRRRRR

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

456 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

Table 585. VC-11 to TU-12 Conversion

* R—value based on SMPR_FXD_STFF_DEFLT (Table 77 on page 70).

V1/V2/V3/V4

V5/J2/Z6/Z7

RRRRRRIR/P1P0S1S2S3S4FR*

Fixed Stuff/Even Parity

Byte 1

Byte 2

Byte 3

Fixed Stuff/Even Parity

Byte 4

Byte 5

Byte 6

Fixed Stuff/Even Parity

Byte 7

Byte 8

Byte 9

Fixed Stuff/Even Parity

Byte 16

Byte 17

Byte 18

Fixed Stuff/Even Parity

Byte 19

Byte 20

Byte 21

Fixed Stuff/Even Parity

Byte 22

Byte 23

Byte 24

Fixed Stuff/Even Parity

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

457Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

19.14.5 VT Multiplexer (VTMUX)

The VTMUX logic block (in Figure 40 on page 435) performs all functions necessary to place the appropriate VT

data onto the outgoing mapper transmit path data bus.

Bits VT_TX_GRP_TYPE[6:0] (Table 193 on page 164) are programmed to determine whether the outgoing tribu-

tary is a VT1.5/TU-11 or a VT2/TU-12.

See Table 563 on page 436 through Table 566 on page 436 for VT/TU mapping formats.

19.14.6 Transmit Signaling (TX_VTSIG)

The TX_V TSI G lo gi c bl oc k ( in Figure 40 on page 435) will perform all necessary functions to retrieve the signaling

phase and data from the framer and insert it into the outgoing VT/TU.

Note: This block is only enabled when operating in the byte-synchronous mode.

■The signaling is received from the appropriate framer link selected with the value programmed in bits

VT_TXSIG_ CH_SEL [1— 28][4 :0] (Table 215 on page 172). VT_TXSIG_CH_SEL[1—28][4:0] is a necessary

duplication of the routing information programmed within the cross connect (XC) block.

■The TX_VTSIG block determines whether the phase and signaling bits are to be used in the VT/TU mapping. If

the phase or signaling bits are not being used (VT_USE_PBIT[1—28] = 0, VT_USE_SBIT[1—28] = 0

(Table 215)), they will be set to SMPR_FXD_STFF_DEFLT (Table 77 on page 70) in the microprocessor inter-

face block. Stomping of the F bit is controlled by VT_USE_FBIT[1—28] = 0 (Table 215). Refer to Table 586 for

programming signaling inserting.

Table 586. Framing Byte Generation Per Channel

* X—value based on SMPR_OH_DEFLT (Table 77 on page 70), R—value based on SMPR_FXD_STFF_DEFLT (Table 77).

19.14.7 Transmit Lower Path Overhead (TX_LOPOH)

The TX_LOPOH logic block (in Figure 40 on page 435) performs all necessary functions to receive and store the

low-order path overhead, as well as the REI and RDI values from the external LOPOH serial access channel. The

following functions are supported:

■The TX_LOPOH logic block retimes all incoming signals on the falling edge of the external input pin

LOPOHCLKIN (AC13).

■The source of the external inputs LOPOHDATAIN (AC14), LOPOHVALIDIN, and LOPOHCLKIN is required to

hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The TX_LOPOH logic block moni-

tors the incoming LOPOHVALIDIN and detects failure conditions. A failure exists if there are less than eight

LOPOHCLKIN cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the internal bit

counter reaches its maximum count, for the active data type, and LOPOHVALIDIN does not transition to 0.

VT_USE_FBIT[1—28] VT_USE_PBIT[1—28] VT_USE_SBIT[1—28] Action

See Table 215 on page 172.

0 0 0 VT/TU frame byte* = XXXXXXXR

0 0 1 VT/TU frame byte* = XXS1S2S3S4XR

0 1 0 VT/TU frame byte* = P1P0XXXXXR

0 1 1 VT/TU fr ame byt e* = P1 P0S1S2 S3S 4XR

1 0 0 VT/TU frame byte* = XXXXXXFR

1 0 1 VT/TU frame byte* = XXS1S2S3S4FR

1 1 0 VT/TU frame byte* = P1P0XXXXFR

1 1 1 VT/TU frame byte* = P1P0S1S2S3S4FR

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

458 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

■The first three bits received, following a rising edge of external input pin LOPOHVALIDIN (AB14), define the data

type on the incoming stream. Data types are defined in Tabl e 569 on page 447.

■LOPOH failure is reported in bit VT_LOPOH_FAIL_E (Table 183 on page 159). If an LOPOH failure exists (indi-

cated by VT_LOPOH_FAIL_E = 1), the incoming data will be ignored. Unless the mask bit VT_LOPOH_FAIL_M

(Table 187 on page 162) is set, VT_LOPOH_FAIL_E = 1 will generate an interrupt.

Figure 47 on page 460 contains the TX_LOPOH block serial channel format and timing.

19.15 VT Mapper System Interfa ce Timing

19.15.1 VT Mapper DS1/E1 Receive Interface (to System Interface)

Figure 42 and Figure 43 show the minimum, typical, and maximum gaps of the clock and data out of the VT map-

per for DS1 and E1. An asymmetric VT/TU mapper clock (VTMPR_RCLK) is derived from an internal 6.48 MHz

clock. The rising edge of this VT mapper clock is delayed by one 6.48 MHz clock cycle with respect to the data

(VTMPR_RDATA) and is one cycle in widt h.

5-8986(F)r.2

Figure 42. DS1 Mode Gapped Clocking Scheme

5-8987(F)r.2

Figure 43. E1 Mode Gapped Clocking Scheme

Figure 44 and Figure 45 show a typical frame of VT mapper output. The VT mapper 8 kHz frame sync output

(VTMPR_RFSYNC) is coincident with the DS1 frame-bit position and with the MSB of E1 time slot 0.

Note: The VT mapper 8 kHz frame sync is only transmitted for byte-synchronous mappings.

5-8988(F)r.1

* Maximum gap between rising clock edges = 1848 ns.

Figure 44. DS1 Interface

VTMPR_RCLK

VTMPR_RDATA

1232 ns 1848 ns

616 ns

154 ns154 ns

VTMPR_RCLK

VTMPR_RDATA

462 ns 924 ns 1386 ns

154 ns 154 ns

VTMPR_RCLK

VTMPR_RDATA

VTMPR_RFSYNC

DS0 #1 DS0 #2

125 µs

154 ns 616 ns 1232 ns*

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

459Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

5-8989(F)r.1

* Maximum gap between rising clock edges = 1386 ns.

Figure 45. E1 Interface

19.15.2 VT Mapper DS1/E1 Transmit Interface (from System Interface)

The VT mapper input clock and data will meet the timing requirements of G.703, 1.544 MHz ± 50 ppm and

2.048 MHz ± 50 ppm. The VT mapper will accommodate up to ±200 ppm to allow operation under maintenance or

trouble conditions. The clock edge to retime the data is programmable with VT_TX_CLKEDGE[1—28] bit

(Table 211 on page 170). The receive data is clocked on the rising edge when VT_TX_CLKEDGE[1—28] = 1 and

the falling edge when VT_TX_CLKEDGE[1—28] = 0.

See VT Mapper Timing on page 47 for VT mapper interface and clock timing numbers.

19.16 VT Mapper Lower-Ord er Path O verh ead Interface Timing

19.16.1 VT Mapper Receive Path Overhead Interface Description

Figure 46 contains the VT mapper receive path overhead serial channel format and timing.

5-8327(F)r.2

Figure 46. VT Mapper Receive Path Overhead Serial Access Channel

VTMPR_RCLK

VTMPR_RDATA

VTMPR_RFSYNC

TS #0 TS #1 TS #1 TS #1

125 µs

154 ns 462 ns 924 ns*

TMUX/SPEM PR RDI/REI VTMPR VT#1—28 V5(MSB–>LSB) VTMPR VT#1—28 J2(MSB–>LS B ) VTMPR VT#1—28 Z6(MSB–>LSB)

FRAME #1 OF MULTIFRAME

125 µs

MINIMUM OF 8 CYCLES 154 ns

LOPOHCLKOUT

LOPOHVALIDOUT

LOPOHDATAOUT 001 010 011 100

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

460 Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

The Supermapper provides access to all necessary functions associated with the receive path overhead for each

VT/TU, specifically V5, J2, Z6/N2, Z7/K4, and the O bits. The following features are supported:

■V5, J2, Z6/N2, Z7/K4, and the O bits, on a per-VT basis, will be stored for one complete superframe and transmit-

ted out on external output pin LOPOHDATAOUT (AB17) during the next superframe. REI and RDI values

received from the SPE mapper and TMUX will be stored on a per-frame basis and transmitted during the next

frame. REI and RDI values will be latched during the A1 time of the received SONET frame.

■When operating in unidirectional path switch ring (UPSR) mode (VT_UPSR = 1 (Table 194 on page 164)), REI,

RDI, and ERDI values in the V5 and Z7 bytes will be modified based on the receive status. See Table 569 on

page 447 for automatic generation requirements.

■Each data type out of LOPOHDATAOUT will be transmitted serially as a burst of 227 bits (VT1.5 mode) or

171 bits (VT2 mode) on the rising edge of the clock, LOPOHCLKOUT, which is driven out on external pin AB15.

The REI and RDI received from the SPE mapper and TMUX will be transmitted serially as a burst of 37 bits on

the rising edged of the clock, LOPOHCLKOUT.

■The LOPOHVALIDOUT signal (driving external output pin AB18) is set to 1 when valid data is being transmitted.

■Following transmission of any complete data type, LOPOHVALIDOUT is held at 0 for at least eight

LOPOHCLKOUT cycles.

■The first 3 bits transmitted, following a rising edge of LOPOHVALIDOUT, make up the data type header. Data

type 001 will be the first data type transmitted in each frame. V5, J2, and Z6 are transmitted respectively in the

first frame of the superframe. Z7 and the O bits are transmitted respectively in the second frame of the super-

frame. Note that the LOPOHDATAOUT data types are only transmitted in the first and second frames of the four

frame multif ra me.

■All data types must be transmitted within 500 µs.

19.16.2 VT Mapper Transmit Path Overhead Interface Description

Figure 47 contains the VT mapper transmit path overhead serial channel format and timing.

5-8329(F)r.2

Figure 47. VT Mapper Transmit Path Overhead Serial Access Channel

TMUX/SPEMPR RDI/REI VTMPR VT # 1— 2 8 V5 (M S B –> L SB ) VTMPR VT#1—28 J2(MSB–>LSB) VTMPR VT#1—28 Z6(MSB– >LSB)

FRAME #1 OF MULTIFRA ME

125 µs

MINIMUM OF 8 CYCLES 154 ns

LOPOHCLKIN

LOPOHVALIDIN

LOPOHDATAIN

LOPOH BITCNT 0 1 2

012

226

012

226

012

226

001 010 011 100

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

461Agere Systems Inc.

19 VT/TU Mapper Functional Description (continued)

The VT mapper transmit path overhead will perform all necessary functions for the low-order path overhead, as

well as the REI and RDI values from the internal SPE mapper and TMUX blocks. The following are supported:

■The interface clocks all incoming signals on the falling edge of external input LOPOHCLKIN (pin AC13).

■The first 3 bits received, following a rising edge of external input pin LOPOHVALIDIN (AB14), will define the data

type on the incoming stream. Data types are defined in Table 569 on page 447.

■The source of the external input LOPOHDATAIN (AC14), LOPOHVALIDIN, and LOPOHCLKIN signals is

required to hold the LOPOHVALIDIN at 0 for a minimum of eight LOPOHCLKIN cycles. The VT mapper will mon-

itor the incoming LOPOHV ALIDIN and detect failure conditions. A failure exists if there are less than eight LOPO-

HCLKIN cycles between a falling edge of LOPOHVALIDIN and the next rising edge, or if the LOPOH bit count

(LOPOH BITCNT) reaches its maximum count for the active data type and LOPOHVALIDIN does not transition

to 0.

■LOPOH failure is reported in bit VT_LOPOH_FAIL_E (Table 183 on page 159). If a failure exists

(VT_LOPOH_FAIL_E = 1), the incoming data will be ignored and unless the mask bit, VT_LOPOH_FAIL_M

(Table 187 on page 162), is set, the LOPOH failure will generate an interrupt.

■The VT mapper logic block will latch new REI and RDI values for the TMUX and SPE mapper during the A1 time

of the SONET/SDH frame.

The timing figures in this section are functional timing diagrams. See VT Mapper T iming on page 47 for VT mapper

interface and clock timing numbers.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

462 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Descripti on

Table of Con t ents

Contents Page

20 M13/M23 MUX/DeMUX Block Functional Description ....................................................................................462

20.1 M13 Introduction.......................................................................................................................................463

20.2 Features...................................................................................................................................................463

20.2.1 M13 App li catio ns ........... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... .................... 463

20.3 Block Diagrams........................................................................................................................................464

20.4 M13 Functional Description......................................................................................................................467

20.5 M13 Multiplexing Path..............................................................................................................................467

20.5.1 M12 Mul tip le xe rs ...... ...... .................... ...... ....... ...... ................... ....... ...... ....... ................................. 467

20.5.2 D S1/E1 Inte rfa ce ........... ....... ...... ....... ................... ....... ...... ...... ....... ...... .................... .................... 467

20.5.3 Loop bac k Select ................... ...... ....... ................... ....... ...... ...... ....... ................... ....... .................... 468

20.5.4 D S1/E1 FIFOs ......... ...... .................... ...... ....... ...... ....... ...... ................... ....... ...... ....... .................... 468

20.6 DS2 Frame Generation............................................................................................................................468

20.6.1 D S1 Mode ................ ...... ....... ...... ....... ................... ....... ...... ...... ....... ...... ........................................ 468

20.6.2 E1 Mode ........... ....... ...... ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ................................. 469

20.7 M23 Multiplexer........................................................................................................................................470

20.7.1 D S2 Interfa ce ................. ....... ...... ....... ...... ....... ................... ...... ....... ...... ....... ................................. 470

20.7.2 D S2 Select Logi c ..... ................... ....... ...... ....... ................... ...... ....... ...... ....... ................................. 470

20.7.3 Overhead Bit Generation (GR-499) .............................................................................................. 471

20.7.4 M23 Mod e .. ...... ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... .................... ...... ........................... 471

20.7.5 C-Bit Parity Mode .......................................................................................................................... 471

20.7.6 FEAC .... ...... ...... ....... ...... ....... ...... .................... ...... ....... ...... ...... ....... ...... ........................................ 472

20.7.7 FEBE .......... ...... ....... ...... ....... ...... ....... ...... ....... ...... ................... ....... ...... ....... ...... ........................... 473

20.7.8 Terminal-to-Terminal Path Maintenance Data Link ...................................................................... 473

20.8 AIS/Idle Insertion......................................................................................................................................474

20.9 B3ZS Encoder (GR-499)..........................................................................................................................474

20.10 DS3 R-to-T Loopback.............................................................................................................................475

20.10.1 DS3 Transmit Path Interface ....................................................................................................... 475

20.11 M13/M23 Demultiplexer .........................................................................................................................475

20.11.1 DS3 LOC and LOS ..................................................................................................................... 475

20.11.2 DS3 T-to-R Loopback ................................................................................................................. 476

20.11.3 M23 Demultiplexer ...................................................................................................................... 476

20.11.4 M12 Demultiplexers .................................................................................................................... 479

20.11.5 DS1 Mode ................................................................................................................................... 480

20.11.6 E1 Mode ..................................................................................................................................... 480

20.11.7 Output Select Logic .................................................................................................................... 481

Figures Page

Figure 48. M13 Block Diagram..............................................................................................................................464

Figure 49. M12 Functional Block Diagram ............................................................................................................465

Figure 50. M23 Functional Block Diagram ............................................................................................................466

Figure 51. DS3 NSMI Transmit Operation.............................................................................................................469

Figure 52. DS3 NSMI Receive Operation..............................................................................................................469

Tables Page

Table 587. C-Bit Parity Description and Transmit Value........................................................................................472

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

463Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.1 M13 Introduction

The M13 block is a highly configurable multiplexer/demultiplexer . It can operate as an M13 in either the C-bit parity

or M23 mode, a mixed M13/M23, or an M23.

In the C-bit parity mode, the M13 provides a far-end alarm and control (FEAC) code generator and receiver, an

HDLC transmitter and receiver, and automatic far-end block error (FEBE) generation and detection.

Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent MUX/

deMUX.

The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system, or it

can be operated in a polled mode.

20.2 Features

■Configurable multiplexer/demultiplexer for up to 28 DS1 signals, 21 E1 signals, or 7 DS2 signals to/from a DS3

signal.

■M23 or C-bit parity mode operation.

■Seven configurable independent M12 multiplexer/demultiplexers for up to 28 DS1 signals or 21 E1 signals

to/from 7 DS2 signals.

■Provisionable time-slot selection for DS1, E1, and DS2 insertion or drop.

■DS3 multiplexer capable of generating alarm indication signal (AIS), remote alarm indicator (RAI), idle, far-end

alarm and control (FEAC), and far-end block error (FEBE) signals.

■Automatic DS3 receive monitor that detects loss of signal (LOS), bipolar violation (BPV), excessive zeros (EXZ),

out of frame (OOF), severely errored frame (SEF), AIS, RAI, FEAC codes, P-bit parity errors, C-bit parity errors,

and FEBE indications.

■HDLC transmitter with 128-byte data buffer and HDLC receiver with 128-byte data FIFO for the C-bit parity path

maintenanc e data link.

■DS3, DS2, DS1, and E1 loopback and loopback request generation.

■Complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, and G.775.

20.2.1 M13 Applications

■M13 and M23 multiplexers.

■M13 multiplexers supporting G.747 format.

■Independent M12 multiplexers.

■Digita l acc es s cr os s co nne ct s (DA CS) .

■DS1/E1/DS2 broadcast.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

464 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.3 Block Diagrams

The following diagram illustrates the high-level interface between M13 block and other functional blocks.

5-9013(F)r.1

Figure 48. M13 Block Diagram

M13 MULTIPLEXER

M13 DEMULTIPLEX ER

CROSS

CONNECT

CONTROL INTERFACE

DS1XCLK

DS2AISCLK

DS1/E1/DS2

LOOPBACK DS3

LOOPBACK

E1XCLK

M13 AUTO AIS

SMPR_TDS3CLK

SMPR_TDS3CLK_EN

M13_DS3CLK

M13_DS3NEG

SMPR_RDS3CLK

SMPR_RDS3CLK_EN

SMPR_DS3NEG_BPV

SPEMPR_AUTOAIS

RCBSYNC

RCBCLK

RCBDATA

RDLCLK

RDLDATA TCBSYNC

TCBCLK

TCBDATA

TDLCLK

TDLDATA

SMPR_DS3POS_DAT

M13_DS3POS_DATA

NSMI_RELATED

DNSMI_RELATED

DEVICE I/O

SPE

CROSS

CONNECT

DS3

DS1/E1

DS2

MAPPER

DEVICE I/O

M12 DS1 DATA/

M23 DS2 DATA/

M12 DS2 DATA /CLOCK

CLOCK/STFREQ

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

465Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

5-9014(F)r.1

Figure 49. M12 Functional Block Diagram

XC_DS1DATA[1—4] M12 MUX

DS1AISCLK

M12 MUX

DS1/E1

LOC & AIS

MONITOR

#[1—4]

M13_DS1DATA[1—4]

M13_DS1DATA[25—28]

XC_DS1CLK[25—28]

XC_DS1CLK[1—4]

M13_DS1CLK[1—4]

M13_DS1CLK[25—28]

E1AISCLK

XC_DS1STFREQ[25—28]

M13_AUTOAIS[1—4]

M13_AUTOAIS[25—28]

XC_DS1STFREQ[1—4]

M13_DS1M12CLK[1—4]

DS1/E1

LOC & AIS

MONITOR

#[25—28]

DS1/E1

SELECT

#[1—4]

M13_DS1M12CLK[25—28]

XC_DS1DATA[25—28]

OUTPUT

SELECT

#[1—4]

DS1/E1

OUTPUT

SELECT

#[25—28]

DS1/E1

SELECT

#[25—28]

M12 DEMUX

XC_DS2DMXCLK[1—7]

XC_DS2M12CLK[1—7]

XC_DS2DMXDATA[1—7]

M13_DS2M12DATA[1—7]

M13_M12DS2DATA[1—7]

DEVICE I/O

DS1/E1 FROM

CROSS CONNECT

DS1/E1 TO

CROSS CONNECT

M12 DEMUX

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

466 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

5-9015(F)

Figure 50. M23 Functional Block Diagram

M13_DS3NEG

SMPR_RDS3NEG_BPV

DS2

SELECT

TCBDATA

TDLDATA

RDLDATA

RCBDATA

DS3

LOOP-

BACK

SELECT

DS3

LOOP-

BACK

SELECT

AIS/

IDLE

INSERT

TCBCLK

TCBSYNC

TDLCLK

RDLCLK

RCBSYNC

RCBCLK

SMPR_RDS3CLK

SMPR_RDS3CLK_EN

SMPR_TDS3CLK

M23

MUX B3ZS

ENCODE

SPEMPR_AUTOAIS

M23

DEMUX B3ZS

DECODE

LOC &

DETECT

LOS

MICROPROCESSOR

INTER FACE AND

M13_M12DS2

DNSMI_RELATED

DS3

LOOP-

BACK

SELECT

M23

DEMUX B3ZS

DECODE

DS2 LOC

& AIS

MONITOR

#[1—7]

XC_DS2M23

XC_DS2ST

DS2AISCLK

M13_DS2

OUTPUT

SELECT

#[1—7]

DS2

M13_DS2M12

M13_DS2M23

SMPR_TDS3CLK_EN

M13_DS3POS_DATA

SMPR_RDS3POS_DATA

DEVICE I/O

DS2

SELECT

DEVICE I/O

NSMI_RELATED

DATA[1—7]

CLK[1—7]

FREQ[1—7]

CLK[1—7]

DATA[1—7]

CLK[1—7]

DS3 FROM/TO

CROSSCONNECT

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

467Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.4 M13 Functional Description

In the descriptions below, some of the register bits exist for each of the DS1, E1, or DS2 signals. The names of

these register bits have a lower case x or a y suffix to show that there are actually 28 or 7 of them, respectively.

20.5 M13 Multiplexing Path

There are seven M12 multiplexers and one M23 multiplexer on the transmit side of this M13 block, and all of them

can operate independently. Twenty-eight DS1 inputs in groups of four , or twenty-one E1 input signals in groups of

three can feed into individual M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or

direct DS2 inputs, or loopback deMUXed DS2s.

20.5.1 M12 Multiplexers

M12 multiplexers have four operation modes provisionable through M13_M12_MODEy[1:0] (Table 275 on

page 220):

■M13_M12_MODEy[1:0] = 00: the M12 operates as the first stage of M13 multiplexing. It takes 4 DS1s

(M13_DS1_E1Ny = 1(Table 275)) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be fed

into the M23 MUX. In this mode, the DS1/E1 clocks are independent inputs to the block. There should be no

valid DS2 input (XC_DS2M23DATAy). This is the default mode.

■M13_M12_MODEy[1:0] = 01: the M12 operates as an independent multiplexer. It takes 4 DS1s

(M13_DS1_E1Ny = 1) or 3 E1s (M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent directly to

the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this mode, the

DS1/E1 clocks are independent inputs to the block and a DS2 input clock (XC_DS2M12CLKy) is required.

■M13_M12_MODEy[1:0] = 10: the M12 operates as an independent multiplexer. It takes 4 DS1s (register bit

M13_DS1_E1Ny = 1) or 3 E1s (register bit M13_DS1_E1Ny = 0) and MUXes into a DS2 signal which will be sent

directly to the DS2 output (M13_DS2M12DATAy) of the block and not be passed to M23 MUX input. In this

mode, the associated DS1/E1 clocks are outputs from the block and derived from the DS2 input clock

(XC_DS2M12CLKy).

■M13_M12_MODEy[1:0] = 11: the M12 is idle. The output from this M12 multiplexer will be held low.

20.5.2 DS1/E1 Interface

The incoming DS1/E1 clock signals (XC_DS1CLK[28—1]) are first checked for activity or loss of clock (LOC). This

is reported to the microprocessor via bits M13_DS1_LOC[28:1] (Table 259 on page 214). Once LOC is detected,

AIS will be inserted into the associated DS1/E1 channel using DS1AISCLK and E1AISCLK, generated by the DJA

using the DS1CXCLK/W1XCLK.

The incoming DS1/E1 data signals are retimed immediately by the associated clocks. The edge of the clocks that

is used to retime the data is user provisionable to either the rising edge (M13_RDS1_EDGEx = 1 (Table 276 on

page 220)) or falling edge (M13_RDS1_EDGEx = 0).

After being retimed, the incoming data stream is checked for AIS. When the input is DS1, the M13 will declare AIS

if the input data is logic 0 for fewer than 9 out of 8192 clock periods (T1.231). When the input is E1, AIS is declared

if there are less than 3 zeros in each of two consecutive 512-bit periods and cleared when each of two consecutive

512-bit periods contains more than 2 zeros (G.775). If AIS is detected on any of the DS1/E1 inputs

(XC_DS1DATA[28—1]), the associated M13_DS1_AIS_DET[28:1] (Table 260 on page 215) bit is set.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

468 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.5.3 Loopback Select

DS1/E1 loopback selectors allow DS1 or E1 received within the DS2 or DS3 inputs from the deMUX path to be

looped back. This loopback can be performed automatically if M13_AUTO_FLB (Table 271 on page 218) or

M13_AUTO_LB (Table 271) bits are set. Regardless of the state of M13_AUTO_FLB and M13_AUTO_LB, the

user can force a DS1 or E1 loopback by setting M13_SEL_DS1_LBx (Table 276 on page 220) to 1.

When M13_AUTO_LB = 1, loopback of channel x is activated if M13_DS1_LB_DETx = 1 (Table 261 on page 215)

(see Section 20.11.4 on page 479). In the C-bit parity mode, automatic loopback can also be activated as a result

of receiving a loopback request through the far-end alarm and control (FEAC) channel. Such a request is indicated

by status bit M13_DS1_FEAC_LB_DETx (Table 263 on page 216) (see Section 20.7.6 on page 472). If status bit

M13_DS1_FEAC_LB_DETx = 1 and M13_AUTO_FLB = 1, loopback of channel x is activated.

20.5.4 DS1/E1 FIFOs

When M13_M12_MODEy[1] = 0 (Table 275 on page 220), the 4 selected DS1 or 3 selected E1 signals for each

M12 MUX are fed into single bit 16-word-deep FIFOs that are used to synchronize the selected signals to the DS2

frame generation clock. The DS2/DS3 transmit clock (XC_DS2M12CLKy) is used to derive the clock source for

DS2 frame generation blocks. In the C-bit parity mode, all DS2 stuff opportunities are used, which produces a nom-

inal 6.306 MHz DS2 clock. In the M23 mode, the DS2 stuffing ratio is fixed so that the DS2 clock is nominally 6.312

MHz.

The fill level of each FIFO determines the need for bit stuffing its DS1/E1 input. This block allows the M13 to accept

DS1/E1 signals with nominal frequency offsets of ±130 ppm and up to 5 unit intervals peak jitter.

When operating in M13_M12_MODEy[1:0] = 10 mode, the FIFOs are not used.

20.6 DS2 Frame Generation

Each M12 MUX generates a DS2 frame either from 4 DS1 signals multiplexed as specified in T1.107 and GR-499-

CORE when M13_DS1_E1Ny = 1 (Table 275 on page 220), or from 3 E1 signals multiplexed using the format

specifi ed in ITU-T reco mme ndation G.747 when M13_DS1_E1 Ny = 0.

When M13_M12_MODEy[1:0] = 01/10 (Table 275), each M12 MUX is operating independently. In this case, the

output DS2 signals are retimed by the associated clocks. The edge of the clocks that is used to retime the data is

user provisionable to either the rising edge (M13_DS2M12_EDGEy = 1; see Table 287 on page 223) or falling

edge (M13_DS2M12_EDGEy = 0). The AIS signal can be inserted into any DS2 output by setting

M13_DS2_FORCE_AISy to 1; see Table 283.

20.6.1 DS1 Mode

In the DS1 mode, the 4 signals interleaved to generate the yth DS2 signal are the outputs from DS1/E1 loopback

selectors 4y – 3, 4y – 2, 4y – 1, and 4y. Bits multiplexed into the second and fourth channels (from selectors 4y – 2

and 4y) are inverted before being interleaved (T1.107) when bit M13_MUXCH2_4_INVy = 1 (Table 275 on

page 220).

Loopback requests for a DS1 channel are indicated by inverting the third C bit for that channel (T1.107). This is

done when bit M13_DS1_LB_REQx is set to 1 (Table 275). The 4 M13_DS1_LB_REQx bits that affect the yth DS2

are 4y – 3, 4y – 2, 4y – 1, and 4y.

The X bit is set to the inverse of the remote alarm indication (RAI) bit (T1.107) M13_DS2_RAI_SENDy (Table 277

on page 22 0 ).

For testing purposes, the M-frame alignment signal (normally 011) is generated with the last bit inverted (010) if

M13_DS2_MPINVy is set (Table 279 on page 221), and the M-subframe alignment signal (01) is generated as (00)

if M13_DS2_FINVy is set (Table 280 on page 221).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

469Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.6.2 E1 Mode

In the E1 mode, the 3 signals interleaved to generate the yth DS2 signal are the outputs from DS1/E1 loopback

selectors 4y – 3, 4y – 2, and 4y – 1.

Although it is not part of the G.747 standard, loopback requests for an E1 channel can be indicated as in the DS1

mode by inverting the third C bit for that channel. This is done if the M13_DS1_LB_REQx bit is set. The

three M13_DS1_LB_REQx bits that affect the yth DS2 are 4y – 3, 4y – 2, and 4y – 1.

The remote alarm indication (RAI) bit and the reserved bit are set to the value of M13_DS2_RAI_SENDy and

M13_DS2_RSV_SENDy register bits, (Table 278 on page 220) respectively (G.747).

For testing purposes, the frame alignment signal (normally 11 1010000, as specified in G.747) is generated with the

last bit inverted (111010001) if M13_DS2_FINVy is set, and the parity bit is inverted if M13_DS2_MPINVy is set.

The first parity bit after a 0 to 1 transition of SMPR_BER_INSRT (Table 75 on page 68) is also inverted if

M13_DS2_P_BERy is set to 1 (Table 281 on page 221).

0781(F)

Figure 51. DS3 NSMI Transmit Operation

0782(F)

Figure 52. DS3 NSMI Receive Operation

UNUSED

FRAM E BI T

VARIABLE

LINE_TXCLK29

TXDATAEN

TXSYNC (OPTIONAL)

LINE_TXDATA29

DS3POSDATAOUT

UNUSED

FRAME B I T

VARIABLE

LINE_RXCLK29

RXDATAEN

RXSYNC (OPTIONAL)

LINE_RXDATA29

DS3POSDATAOUT

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

470 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.7 M23 Multiplexer

The M23 multiplexer generates a transmit DS3 frame and fills the information bits in the frame with data either from

the 7 DS2 select blocks when M13_NSMI_MODE = 0 (Table 289 on page 224), or from the serial payload input

XC_NSMI_DATA (when M13_NSMI_MODE = 1). It generates the frame using either the SMPR_TDS3CLK or the

SMPR_RDS3CLK input clocks. In the receive loop-timing mode (M13_LOOP_TIME = 1 (Table 271 on page 218)),

the received clock, SMPR_RDS3CLK, is selected. Otherwise, SMPR_TDS3CLK is used for DS3 frame generation.

SMPR_TDS3CLK is monitored for loss of clock, which is reported through bit M13_TDS3_LOC (Table 237 on

page 209).

The serial data interface, when enabled (M13_NSMI_MODE = 1), generates a clock M13_NSMI_CLK and an

enable M13_NSMI_EN for accepting DS3 payload data XC_NSMI_DATA. A sync pulse, in reference to and ahead

of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to the first M bit is program-

mable through bits M13_NSMI_SP_OFFSET[7:0] (Table 273 on page 219).

The M23 MUX can be provisioned to operate in either the M23 mode (M13_M23_CBP = 1 (Table 272 on

page 219)) or the C-bit parity mode (M13_M23_CBP = 0).

An unframed all ones data stream is generated if M13_TDS3_FORCE_ALL1 is set to 1 (Table 288 on page 223).

20.7.1 DS2 Interface

The clocks associated with input DS2 signals can be either inputs to the M23 MUX (M13_M23CLK_MODE = 0

(Table 288 on page 223)) or outputs from the M23 MUX (M13_M23CLK_MODE = 1).The incoming DS2 clock sig-

nals are checked for activity or loss of clock (LOC). This is reported to the microprocessor via bits

M13_XC_DS2_LOC[7:1] (Table 250 on page 212). In case LOC is detected, AIS will be inserted into the associ-

ated DS2 channel using DS2AISCLK

(pin E10).

The incoming DS2 data signals (XC_DS2M23DATA[7—1]) are retimed immediately by the associated clocks. The

edge of the clocks that is used to retime the data is user provisionable to either the rising edge

(M13_RDS2_EDGEy = 1 (Table 295 on page 226)) or falling edge (M13_RDS2_EDGEy = 0).

After being retimed, the incoming data stream is checked for AIS. The M13 will declare AIS if the input data is 0 for

fewer than five clock cycles in each of two consecutive 840 clock periods. The AIS is not cleared until there are

more than four zeros in each of two consecutive 840-bit periods (G.775). If AIS is detected on any of DS2 inputs,

the associated M13_XC_DS2_AIS_DET[7:1] bit is set (Table 251 on page 212).

20.7.2 DS2 Select Logic

The selection of DS2 signal source for each DS2 time slot is controlled by M13_AUTO_LB (Table 271 on

page 218), M13_DS2_LB_DETy (Table 256 on page 214), M13_SEL_DS2_LBy (Table 294 on page 226), and

M13_M12_MODEy (Table 275 on page 220) bits.

When M13_AUTO_LB = 1 and M13_DS2_LB_DET y = 1, the DS2 signal from time slot y in the received DS3 signal

is looped back into time slot y of the transmitted DS3 signal (see C Bit Processing Section on page 477). The user

can also force a loopback by setting M13_SEL_DS2_LBy to 1. DS2 loopback should not be done in the C-bit parity

mode.

If a loopback is not active, the DS2 signal selector is controlled by bits M13_M12_MODEy[1:0]. If register bits

M13_M12_MODEy[1:0] = 00, the output of M12 multiplexer y is chosen for the yth DS2 time slot in the transmitted

DS3 signal; otherwise, the input DS2 signal XC_DS2M23DAT A y is selected for the yth DS2 time slot in the transmit-

ted DS3 signal.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

471Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.7.3 Overhead Bit Generation (GR-499)

For testing purposes the F bits, M bits, and P bits can be generated with errors. The frame alignment signal (F-bit

pattern that is normally 1001) is generated with the last bit inverted (1000) if M13_DS3_FINV (Table 288 on

page 223) is set. The multiframe alignment signal (M-bit pattern that is normally 010) is generated as (011) if

M13_DS3_MINV (Table 288) is set.

The parity bits (P bits) are generated as odd rather than the normal even parity if M13_DS3_PINV (Table 288) is

set. Both P bits within the first DS3 frame after a 0 to 1 transition of SMPR_BER_INSRT (Table 75 on page 68) are

also inverted if M13_DS3_P_BERy (Table 289 on page 224) is set to 1.

The X bits are set to the inverse of the remote alarm indication (RAI) bit (GR-499) M13_DS3_RAI_SEND

(Table 289).

C-bit transmission is a function of whether the M13 MUX/deMUX is in the M23 mode or the C-bit parity mode.

20.7.4 M23 Mode

Please refer to M13_M2 3_CB P = 1 in Table 272 on page 219. The information bits in the DS3 frame are drawn

from the 7 DS2 select blocks. If M13_M23CLK_MODE = 0 (Table 288 on page 223) and a select block is in the

loopback or direct DS2 input state, the selected DS2 must be synchronized to the DS3 frame generation clock. To

do this, the M13 contains seven DS2 FIFOs each with a depth of 8. The fill level of each FIFO determines the need

for bit stuffing its DS2 input.

When M13_M23CLK_MODE = 0 and DS2 select blocks are not in the loopback or direct DS2 input state, the

selected DS2s are generated using the DS3 frame generation clock. In this case, a fixed stuffing ratio is used for

the DS2s in order to produce a nominal 6.312 MHz DS2 clock rate.

When M13_M23CLK_MODE = 1, the FIFOs are not used and DS2 stuff request inputs (XC_DS2STFREQ[7—1])

will determine when stuff bits are needed.

The three C bits in each M-subframe of the DS3 frame are stuff indication bits. If the stuff opportunity bit in an M

subframe is filled by a DS2 bit, the first and second C bits in that M-subframe are transmitted as zeros. If the stuff

opportunity bit in an M-subframe is filled with a stuff bit, the first and second C bits in that M-subframe are transmit-

ted as ones.

The third C bit in each M-subframe is normally transmitted with the same value as the first and second C bits. How-

ever, if M13_DS2_LB_REQy = 1 (Table 293 on page 225), the third C bit is transmitted as the inverse of the first

two C bits (which indicates a loopback request for DS2 channel y).

20.7.5 C-Bit Parity Mode

Please refer to M13_M23_CBP = 0 in Table 272 on page 219. The M23 MUX can operate in the C-bit parity mode

under the following two circumstances:

■When M13_M23CLK_MODE = 0 and 28 DS1 or 21 E1 signals are being MUXed into the DS3.

■When M13_M23CLK_MODE = 1 and 7 DS2 signals are being MUXed into the DS3.

In the C-bit parity mode, every DS2 stuffing opportunity is filled with a stuff bit. Because stuffing is not used for syn-

chronization, the selected DS2s cannot come directly from the M13 inputs, and the selected DS2s cannot be

looped back from the M23 demultiplexer. The 21 C bits in each DS3 frame are not required as stuffing indicators.

Their use is described in Table 587 on page 472.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

472 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

Table 587. C-Bit Parity Description and Transmit Value

20.7.6 FEAC

The third C bit of each DS3 frame provides a far-end alarm and control (FEAC) signal. The use of this signal and

FEAC code words are defined in T1.107 and GR-499-CORE.

When the FEAC signal is not active, it is transmitted continuously as a 1. The user can provision the M13 to trans-

mit continuous ones by setting M13_TFEAC_CTL[1:0] to 00 (Table 290 on page 224).

Active FEAC signals consist of repeating 16-bit code words of the form 0 x5x4x3x2x1x0 0 11111111, where xi can

be a 1 or a 0. The code words are transmitted right to left one bit each DS3 frame for 16 consecutive frames.

Alarm and Status Signals. EAC alarm and status signals should be transmitted continuously for the duration of

the condition being reported, or for a minimum of 10 repetitions of the code word. FEAC signals are transmitted

continuously by setting M13_TFEAC_CTL[1:0] to 01, and M13_TFEAC_CODE[5:0] to x5x4x3x2x1x0 (Table 290),

where x5x4x3x2x1x0 is the appropriate value for the alarm or status code word.

Control Signals. EAC control signals are defined for activating or deactivating a loopback. Code words for loop-

back activation, deactivation, and specifying the type of loopback can be transmitted using the same method as

described above for alarm and status signals. Alternatively, the user may provision the M13 to automatically send

the activate or deactivate commands.

In order to activate a loopback, the user may set M13_TFEAC_CTL[1:0] to 11, and M13_TFEAC_CODE[5:0] to

x5x4x3x2x1x0, where x5x4x3x2x1x0 is the appropriate value for the loopback code word. The M13 will then trans-

mit 10 repetitions of the activate code word, 0 000111 0 11111111 followed by 10 repetitions of

0x5x4x3x2x1x0 0 11111111. After transmitting this 40 octet sequence, it will set M13_TFEAC_DONE to 1

(Table 229 on page 204).

In order to deactivate a loopback, the user may set M13_TFEAC_CTL[1:0] to 10, and M13_TFEAC_CODE[5:0] to

x5x4x3x2x1x0, where x5x4x3x2x1x0 is the appropriate value for the loopback code word. The M13 will then trans-

mit 10 repetitions of the deactivate code word, 0 011100 0 11111111, followed by 10 repetitions of

0x5x4x3x2x1x0 0 11111111. After transmitting this 40 octet sequence, it will set M13_TFEAC_DONE to 1.

C Bit Number Description Transmit Value

C1 C-Bit Parity Identification 1.

C2 Network Requirements Bit If M13_CBIT2_ACT = 0 (Table 289 on page 224), the C2 bit

is set to 1.

If M13_CBIT2_ACT = 1, the transmit value of C2 is input

through pin TCBDATA (E12).

C3 Far-End Alarm and Control (FEAC) See FEAC below.

C4—C6,

C16—C21 Unused If M13_UNUSED_ACT = 0 (Table 289), all are transmitted

as 1.

If M13_UNUSED_ACT = 1, the transmit values are input

through pin TCBDATA (E12).

C7—C9 CP Bits (path DS3 parity) Set to the same value as the P bits.

C10—C12 Far-End Block Error (FEBE) Bits See Section 20.7.7 on page 473.

C13—C15 Terminal-to-Terminal Data Link See Section 20.7.8 on page 473.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

473Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

20.7.7 FEBE

C bits 10, 11, and 12 provide a far-end block error (FEBE) indication. Each frame of the received DS3 signal is

checked for errors in the F-bit or M-bit framing sequences and for errors in the CP-bit path parity. If no errors are

found, the FEBE bits are set to 1 11 in the next transmitted DS3 frame. If one or more errors are detected, the FEBE

bits are transmitted as 000. The user can force the transmission of FEBE error indications by setting

M13_FEBE_ERR to 1 (Table 289 on page 224). This causes all DS3 frames to be transmitted with the FEBE bits

set to 000, regardless of whether or not errors were detected in the received DS3 signal.

20.7.8 Terminal-to-Terminal Path Maintenance Data Link

C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link. If the data link is not used, the user should set

M13_TDL_ACT to 0 (Table 291 on page 225), which causes all ones to be transmitted. When M13_TDL_ACT = 1

and M13_TDL_NTRNL = 0 (Table 291), the data transmitted on this link comes directly from the M13 input pin, pin

TDLDATA (E8). Otherwise (M13_TDL_ACT = 1 and M13_TDL_NTRNL = 1), the data link is controlled by the inter-

nal HDLC transmitter.

HDLC Transmitter. The internal HDLC transmitter circuitry is composed of two 64-byte data buffers (registers

M13_TDL_0DA T A_R[0—63] (Table 310 on page 230) and M13_TDL_1DA TA_R[0—63] (Table 31 1 on page 230)),

a CRC-16 frame check sequence (FCS) generator, and control circuits. The HDLC transmitter continually outputs

flag bytes (01 1 1 1 110) with MSB first until the user sets M13_TDL_NTRNL_ACT to 1 (Table 291 on page 225). Fol-

lowing the completion of the next flag byte, the HDLC transmitter begins transmitting the first byte of the first data

buffer (register M13_TDL_0DA TA_R[0]), which should be filled by the user with the first byte of the address field.

(For LAPD messages, this byte contains the service access point identifier , the command/response bit, and a zero

extended address bit.)

Bytes from the data buffer are transmitted least significant bit (LSB) first (GR-499). The HDLC controller inserts a 0

after any sequence of five consecutive ones in the data buffer to prevent the occurrence of a flag pattern prior to

the closing flag.

Buffer Usage. The number of bytes transmitted from the data buffers before completing the frame is controlled as

follows. M13_TDL_BUF0_END (Table 291 on page 225) and M13_TDL_BUF1_END (Table 291) are two bits

which indicate whether or not the final buffer byte to be transmitted is currently in buffer 0 or buffer 1. While bytes

from buffer 0 are being transmitted, the HDLC controller checks the value of M13_TDL_BUF0_END bit. If it is 0, all

bytes from buffer 0 and at least one byte from buffer 1 are transmitted. If it is 1, bytes from buffer 0 are transmitted

sequentially up to and including byte K, where M13_TDL_BYTE_END[5:0] = K (Table 292 on page 225).

Similarly, the number of bytes transmitted from buffer 1 is controlled by the value of M13_TDL_BUF1_END and

M13_TDL_BYTE_END[5:0] bits. Bytes are transmitted alternately from buffer 0 and buffer 1 until bit

M13_TDL_BUF[0, 1]_END = 1 for the active transmission buffer and the value of bits M13_TDL_BYTE_END[5:0]

is equal to the byte number being transmitted.

When the HDLC controller completes transmission of register M13_TDL_0DATA_R[63] (the last byte of buf fer 0),

the interrupt bit M13_TDL_BUF0_INT is set to 1 (Table 229 on page 204). Similarly, the interrupt bit

M13_TDL_BUF1_INT (Table 229) is set after the last byte of buffer 1 is transmitted. These bits indicate that the

corresponding buffer has been emptied and is available for refilling.

The user may abort the transmission of an HDLC frame by clearing M13_TDL_NTRNL_ACT to 0 prior to complet-

ing transmission of the last byte from the data buffers. If so, the HDLC controller will stop transmission from the

buffers and send an abort byte (01111111) transmitted MSB first. The abort byte will then be followed by flag bytes

until M13_TDL_NTRNL_ACT is again set to 1, starting transmission of a new frame.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

474 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

FCS Generation. Once the last buffer byte is transmitted, the HDLC controller either transmits a closing flag byte

(when M13_TDL_FCS = 0 (Table 291 on page 225)), or it first appends the 2-byte ITU-T FCS with the necessary

zero stuffing before sending the closing flag (when M13_TDL_FCS = 1). In either case, the HDLC controller sets

M13_TDL_DONE (Table 2 29 on page 204 ) to 1 after the transmission of the frame is complete. For testing pur-

poses, the user can send corrupted FCS bytes by clearing M13_TDL_FCS to 0 and filling the last 2 bytes in the

buffer with an incorrect CRC value.

LAPD Exam ple. T1.107 defines three standard LAPD messages that may be transmitted on the path maintenance

data link. After the opening flag, each of these messages contains 79 bytes of address, control, and information.

These are followed by the 2-byte FCS and the closing flag.

To transmit one of these messages using the internal HDLC transmitter, the microprocessor should first set

M13_TDL_ACT (Table 291) to 1, M13_TDL_NTRNL (Table 291) to 1, and M13_TDL_NTRNL_ACT (Table 291) to

0. This causes the continuous generation of flag bytes.

The microprocessor may then fill buffer 0 with the first 64 bytes of the message and fill bytes 0 through 14 of buffer

1 with the last 15 bytes prior to the FCS of the message. By setting M13_TDL_BUF0_END (Table 291) to 0,

M13_TDL_BUF1_END (Table 291) to 1, and M13_TDL_BYTE_END[5:0] (Table 292 on page 225) to 001110, the

microprocessor can indicate that 79 buffer bytes are to be transmitted.

The microprocessor can then set M13_TDL_FCS to 1 and M13_TDL_NTRNL_ACT to 1. This will cause the inter-

nal HDLC transmitter to send the 79 buffer bytes, append the FCS and closing flag, set M13_TDL_DONE to 1, and

resume co nti nuou s fla g trans m is sion.

If the same LAPD message is to be transmitted later without first having transmitted a different message, the

microprocessor only needs to toggle M13_TDL_NTRNL_ACT to 0 and back to 1, since the values of the other con-

trol parameters and the buffer bytes are not modified by the internal HDLC transmitter.

20.8 AIS/Idle Insertion

The AIS/idle insertion block can be provisioned to operate in the normal mode (M13_DS3_FORCE_AIS = 0

(Table 288 on page 223) and M13_DS3_FORCE_IDLE = 0 (Table 288) ), gener ate DS3 AIS

(M13_DS3_FORCE_AIS = 1), or generate DS3 idle (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE =

1).

In the normal mode, data from the M23 multiplexer is passed unchanged to the B3ZS encoder block.

During AIS insertion (M13_DS3_FORCE_AIS = 1), the generated DS3 frame is altered by overwriting the informa-

tion bits with an alternating 1010 . . . pattern, starting with a 1 after each overhead bit. In addition, the X bits are

overwritten with ones, and the C bits are overwritten with all zeros (T1.107 and T1.404).

During idle signal generation (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE = 1), the information bits

are overwritten with 11001100 . . ., starting with 11 after each overhead bit. The X bits are overwritten with ones. In

the M23 mode (M13_M23_CBP = 1 (Table 272 on page 219)), the C bits are overwritten with all zeros. In the C-bit

parity mode, the C bits are passed unchanged (T1.107 and T1.404).

20.9 B3ZS Encoder (GR-499 )

The transmit DS3 device output can either be in the form of unipolar data (M13_DS3POS_DATA when

M13_BIPOLAR = 0 (Table 272 on page 219)) or positive data and negative data (M13_DS3POS_DATA, and

M13_DS3NEG when M13_BIPOLAR = 1). If M13_BIPOLAR = 1, the DS3 data is B3ZS encoded with

M13_DS3POS_DATA = 1 indicating a positive pulse and M13_DS3NEG = 1 indicating a negative pulse.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

475Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

The B3ZS encoder block accepts data output from the M23 multiplexer and when M13_BIPOLAR = 1, performs

coding as follows: for each input data bit that is a 1, the encoder outputs a 1 (or pulse) on either its positive or neg-

ative output. The positive or negative output is chosen so that the resulting pulse is opposite in polarity to the last

nonzero output.

For each input data bit that is a 0, the encoder outputs zeros on both its positive and negative outputs, unless doing

so would cause three consecutive output periods of positive and negative zeros. In the latter case, the three con-

secutive input zeros are output as either [00V] or [B0V], where B is a pulse on either the positive or negative output

that is opposite in polarity to the last nonzero output, and V is a pulse that is the same polarity as the last nonzero

output. The choice of [00V] or [B0V] is made so that the polarity of consecutive V-pulses alternates (which is equiv-

alent to forcing the number of B-pulses between successive V-pulses to be odd).

When M13_BIPOLAR = 1, the user can force errors in the bipolar coding by setting M13_BIPOL_ERR (Table 270

on page 21 8 ) to 1. When this is done, the M13 transmits the next 1 as a bipolar violation.

20.10 DS3 R-to-T Loopba ck

The received DS3 signal can be looped directly back to the transmit DS3 output. If either M13_LOOP_R_TO_T = 1

(Table 272 on page 219), or both M13_AUTO_FLB = 1 (Table 271 on page 218) and M13_DS3_FLB_DET = 1

(Table 263 on page 216) (see Section 20.7.6 FEAC on page 472), the loopback is activated. (During loopback, the

SMPR_RDS3POS_DATA and SMPR_RDS3NEG_BPV input signals are looped to the M13_DS3POS_DATA and

M13_DS3NEG outputs, respectively.)

20.10.1 DS3 Transmit Path Interface

When cross connected to the DS3 device pins, the DS3 data out DS3POSDATAOUT (pin R22) and

DS3NEGDATAOUT (pin P22) are clocked out on the falling edge of DS3DATAOUTCLK (pin N22).

If the M13 DS3 interface is optioned for loop timing (M13_LOOP_TIME = 1), the DS3 data is clocked out on the ris-

ing edge of DS3DATAINCLK (pin J22).

20.11 M13/M23 Demultiplexer

20.11.1 DS3 LOC and LOS

SMPR_RDS3CLK is monitored for loss of clock, which is reported through bit M13_RDS3_LOC (Tab le 237 on

page 209). The user can configure which edge of SMPR_RDS3CLK retimes the data (M13_RDS3_EDGE = 1

(Table 299 on page 227) selects the rising edge; M13_RDS3_EDGE = 0 selects the falling edge).

The receive DS3 signal is also checked for loss of signal (LOS), which is reported through bit M13_RDS3_LOS

(Table 237 on page 209). An LOS defect, according to T1.231, is the occurrence of 175 ± 75 contiguous pulse

positions with no pulses of either positive or negative polarity at the DS3 input. An LOS defect is terminated upon

detecting an average pulse density of at least 33% over a period of 175 ± 75 contiguous pulse positions starting

with the receipt of a pulse. An LOS defect will not be terminated if, at the end of the pulse-position interval, any sub-

intervals of

100 pulse positions containing no pulses of either polarity were observed (T1.231).

B3ZS Decoder. The receive DS3 device input can either be in the form of unipolar clock and data

(SMPR_RDS3CLK and SMPR_RDS3POS_DATA when M13_BIPOLAR = 0 (Table 272 on page 219)) or unipolar

clock, positive data, and negative data (SMPR_RDS3CLK, SMPR_RDS3POS_DATA, and

SMPR_RDS3NEG_BPV when M13_BIPOLAR = 1 and M13_BPV_IN = 0 (Table 271 on page 218)) or unipolar

clock, data, and bipolar violation indication (external input) (SMPR_RDS3CLK, SMPR_RDS3POS_DATA, and

SMPR_RDS3NEG_BPV when M13_BIPOLAR = 0 and M13_BPV_IN = 1).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

476 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

When M13_BIPOLAR = 0, the received DS3 data and clock are passed directly to the M23 demultiplexer. When

M13_BIPOLAR = 0 and M13_BPV_IN = 1, the received DS3 data and clock are passed to the M23 demultiplexer

while the bipolar violation indication is forwarded to the internal BPV counter for performance monitoring (B3ZS

decoder is not used). When M13_BIPOLAR = 1 and M13_BPV_IN = 0, the received SMPR_RDS3POS_DATA and

SMPR_RDS3NEG_BPV data inputs are first B3ZS decoded.

The B3ZS decoder block performs decoding as follows. For each clock period that both SMPR_RDS3POS_DATA

and SMPR_RDS3NEG_BPV are 0 (no pulse), the decoder outputs a 0. For each clock period that either

SMPR_RDS3POS_DATA or SMPR_RDS3NEG_BPV is 1 (pulse), the decoder determines whether or not the

pulse is part of a zero substitution (ZS) sequence. A ZS sequence is [00V] or [B0V], where B is a pulse on either

the positive or negative input that is opposite in polarity to the last nonzero input, and V is a pulse that is the same

polarity as the last nonzero input.

If the received pulse is not part of a ZS sequence, the decoder outputs a 1. Otherwise, the decoder outputs three

consecutive zeros in place of the received ZS sequence.

The B3ZS decoder also checks for bipolar coding violations. Bipolar coding violations are defined as received

V-pulses that are not opposite in polarity to the last V-pulse or are not immediately preceded by a 0, or received

zeros that are immediately preceded by two other zeros.

The M13 contains a counter that increments on each occurrence of a received bipolar coding violation (BPV). It

also monitors the occurrence of excessive zeros (EXZ), which is defined as any zero string length equal to or

greater than 3 (T1.231). These are part of the performance monitoring counters that can be sampled and simulta-

neously reset (see DS3 Performance Monitors Section on page 479). Their last sampled values are available in

registers M13_BPV_CNT_R[1—3] (Table 3 07 on page 229) and M13 _EXZ _CN T_ R[1— 3] (Table 308 on

page 230).

20.11.2 DS3 T-to-R Loopback

The M13 can be configured to loopback the internal transmit DS3 from the output of the M23 MUX

(M13_LOOP_T_TO_R = 1 (Table 271 on page 218)), or accept the received DS3 signal after B3ZS decoding

(M13_LOOP_T_TO_R = 0) and send it into the M23 deMUX block.

20.11.3 M23 Demultiplexer

The M23 demultiplexer will take the received DS3 signal and either deMUX it into 7 DS2 data streams or strip off the

overhead bits and send payload out through the NSMI serial interface when M13_NSMI_MODE = 1; see Table 289

on page 22 4 .

The serial data interface, when enabled (M13_NSMI_MODE = 1), generates a clock M13_DNSMI_CLK and an

enable M13_DNSMI_EN for outputting DS3 payload data M13_DNSMI_DATA. A sync pulse M13_DNSMI_SYNC,

in reference to and ahead of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to

the first M bit is programmable through bits M13_D_SP_OFFSET[7:0] (Table 274 on page 219).

In the case of the received DS3 signal being deMUXed into 7 DS2s, those DS2s can be sent out of the device, or

looped back to the transmit side, or passed to M12 demultiplexers for further breakdown into DS1s/E1s.

DS3 Framer. After being B3ZS decoded, the incoming DS3 data stream is checked for the presence of unframed

all ones. If the input data is 0 for fewer than 9 out of 8192 clock periods, bit M13_RDS3_ALL1_DET (Table 237 on

page 209) will be set.

The M23 demultiplexer determines if the input signal contains valid DS3 framing. This is done in two stages by first

finding a bit position that matches the frame alignment pattern (F bits), and then locating the multiframe alignment

signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS3_OOF = 0 (Table 236 on

page 208)) when correct M bits are received for three consecutive M frames (T1.231). The maximum average

reframe time is 0.5 ms in the presence of a bit error rate of 10–3.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

477Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

Once the deMUX is in-frame, the received frame bits are monitored for out of frame. Out-of-frame is declared

(M13_DS3_OOF = 1) when too many errors are received in either the F bits (three errors in 16 bits when

M13_DS3_MODE = 0 (Table 299 on page 227), or at least 1 F-bit error in each of four consecutive M-subframes

when M13_DS3_MODE = 1) or the M bits (at least 1 error in each of three consecutive M frames) (T1.231). For

testing purposes, the user may also force the framer out of frame by setting M13_DS3_FORCE_OOF (Table 270

on page 21 8 ) to 1.

The traditional algorithm for declaring out of frame (three errors in 16 F bits) results in false out of frame approxi-

mately every 30 s when the received bit error rate is 10–3. By waiting for four consecutive M-subframes with F bit

errors before declaring out of frame (M13_DS3_MODE = 1), the M13 normally stays in frame for over an hour

when the bit error rate is 10–3.

The M13_DS3_LOF (Table 236 on page 208) bit is set if bit M13_DS3_OOF is high continuously for 28 frame peri-

ods (approximately 3 ms). Once set, M13_DS3_LOF is not cleared until M13_DS3_OOF is continuously low for 28

frame periods.

The user can provision the M13 to automatically output AIS if either bit M13_DS3_OOF = 1 (by setting

M13_AUTO_AIS_OOF (Table 271 on page 218) to 1), or M13_DS3_L OF = 1 (by setting M13_AUTO_AIS_LOF to

1).

The received DS3 frames are also checked for severely errored frames (SEF). An SEF defect is the occurrence of

three or more F-bit errors in 16 consecutive F bits and is reported through bit M13_RDS3_SEF (Table 237). An

SEF defect is terminated when the signal is in-frame and there are less than three F-bit errors in 16 consecutive

F bits.

AIS, Idle, and RAI Detection. In each M frame, the 4704 information bits are checked for the presence of the AIS

(1010) or idle (1100) pattern. In order to detect these patterns in the presence of a high error rate, AIS

(M13_DS3_AISPAT_DET = 1 (Table 236 on page 208)) or idle (M13_DS3_IDLEPAT_DET = 1 (Table 236)) pat-

tern detection is declared if fewer than five pattern errors are received in each of two consecutive frames. Once

AIS or idle is declared, these bits are not cleared until at least 16 pattern errors are received in each of 2 consecu-

tive frames (T1.2 31) .

In addition to the fixed information bit patterns, AIS and idle signals are transmitted with all C bits set to 0 and both

X bits set to 1. These conditions are monitored by the M13 and reported in bits M13_DS3_CBZ_DET (Table 236)

and M13_DS3_RAI_DET (Table 236).

If every C bit in three consecutive DS3 frames is 0, the M13 sets M13_DS3_CBZ_DET to 1. If the three C bits in a

single M-subframe are all 1, M13_DS3_CBZ_DET is cleared. If both X bits in two consecutive frames are received

as 0, the device sets M13_DS3_RAI_DET to 1. Once M13_DS3_RAI_DET is set, it is not cleared until both X bits

in two consecutive frames are received as 1.

The user may wish to declare AIS or idle based on a combination of some or all of the following bits:

M13_DS3_CBZ_DET, M13_DS3_RAI_DET, and M13_DS3_AISPAT_DET or M13_DS3_IDLEPAT_DET.

C-Bit Processing. The M13 can be provisioned to operate in either the M23 mode (M13_M23_CBP = 1

(Table 272 on page 219)) or the C-bit parity mode (M13_M23_CBP = 0). In the M23 mode, the C bits in each M-

subframe are interpreted as stuff indicator bits, and they are checked for loopback requests. If the third C bit differs

from the first and second C bits in the yth M-subframe for five successive DS3 frames, M13_DS2_LB_DETy is set

to 1; see Table 256 on page 214. The M13_DS2_LB_DETy bit is cleared when the third C bit does not differ from

the first two C bits in subframe y for five successive DS3 frames.

The first C bit of each frame, C1, provides C-bit parity identification. If for eight consecutive frames it is received as

a 1, the M13 sets M13_DS3_C1_DET to 1; see Table 236 on page 208. Once M13_DS3_C1_DET bit is set, three

consecutive frames with C1 = 0 must be received before it is cleared.

The RCBDAT A (pin E15) output provides access to the received C2, C4, C5, C6, and C16 through C21 C bits. The

received data link bits, C13 through C15, are output as a serial stream on RDLDATA pin (H22).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

478 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

FEAC. In the C-bit parity mode, the third C bit of each DS3 frame, C3, is monitored for FEAC signals. Active FEAC

signals consist of repeating 16-bit code words of the form 0 x5x4x3x2x1x0 0 11111111, where xi can be a 1 or a 0,

and the bits are received right-to-left. The same code word must be received four consecutive times before it is

accepted.

When a code word is accepted, the action taken by the M13 depends on the value of x5x4x3x2x1x0, which may be

an alarm indication, a loopback activation, or a loopback deactivation.

The values of M13_DS1_FEAC_LB_DETx and M13_DS3_FLB_DET bits are not changed if an activate or deacti-

vate control signal is accepted, but the next code word to be accepted is not a channel indication control signal

(010011, 011011, or 100001 throug h 111100).

Alarm, Status, or Unassigned Signals. If an FEAC signal is accepted that is not a loopback activate (000111),

deactivate (011 100), or channel indication (01001 1, 011011, or 100001 through 111100) signal, the M13 will set bits

M13_RFEAC_CODE [5:0] = x5x4x3x2x1x0 and M13_RFEAC_ALM_INT to 1; see Table 229 on page 204.

Control Signals. EAC control signals are defined for activating or deactivating a loopback. If a loopback activate

(000111), deactivate (011100), or channel indication (010011, 011011, or 100001 through 111100) is accepted, the

M13 will s et bi ts M1 3_ RFEA C _COD E [5: 0 ] = x5 x4 x3x2 x1 x0 ( Table 264 on page 216) and M13_RFEAC_LB_INT to

1; see Table 229 on page 204.

If a loopback activate (000111), followed by the all-DS1 channels indication (010011) is accepted, the device sets

all M13_DS1_FEAC_LB_DETx bits (Tab le 263 on page 216). All M13_DS1_FEAC_LB_DETx bits are cleared if a

loopback deactivate (011100), followed by the all-DS1 channels indication, is accepted.

If a loopback activate (000111), followed by the DS3 indication (011011) is accepted, the device sets the

M13_DS3_FLB_DET bit (Table 263). The M13_DS3_FLB_DET bit is cleared if a loopback deactivate (011100),

followed by the DS3 indication, is accepted.

Similarly, if the M13 accepts an activate or deactivate control signal followed by a DS1 channel indication (100001

through 111100), it sets or clears the M13_DS1_FEAC_LB_DETx bit, where x is equal to the binary value of

x5x4x3x2x1x0.

Terminal-to-Terminal Path Maintenance Data Link. C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link.

These bits are available directly at device output pin RDLDATA (H22). The M13 also contains an internal HDLC

receiver for processing the received data link bits.

HDLC Receiver. The internal HDLC receiver circuitry is composed of a 128-byte FIFO, a CRC-16 frame check

sequence (FCS) error detector, and control circuits.

The HDLC receiver searches for flag bytes (01111110) and processes the bits received between flag bytes as fol-

lows. The receiver removes zeros that immediately follow any sequence of five consecutive ones. Sequences of

8 bits after zero destuffing are grouped into bytes and written into the FIFO.

As bytes are received, the CRC-16 value, based on the ITU-T polynomial, is calculated. When the closing flag is

received, the receiver checks that the received FCS in the final 2 bytes matches the calculated CRC-16. If

M13_RDL_FCS = 1 (Table 299 on page 227) and the FCS does not match, M13_RDL_FCS_ERR (Tab le 265 on

page 216) is set. If M13_RDL_FCS = 0, M13_RDL_FCS_ERR is held reset at 0. M13_RDL_FCS bit also deter-

mines whether or not the final 2 bytes of the frame are written into the FIFO. They are written into the FIFO only

when M13_RDL_FCS = 0.

The receiver allows frames to be sent back-to-back with the closing flag of one frame shared as the opening flag of

the next frame. If fewer than three complete destuffed bytes are received between flag bytes, the receiver ignores

the data and writes nothing into the FIFO.

FIFO Usage. The FIFO is large enough to hold one full and two partial standard DS3 LAPD frames of 79 bytes. In

case shorter frames are being transmitted, the M13 can keep track of up to four frames in the FIFO that have not

been read.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

479Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

The receive data-link frame interrupt bit, M13_RDL_FRM_INT (Table 229 on page 204), is set when a frame clos-

ing flag or an abort byte is received. The M13_RDL_FIFO_UF bit is set (Table 237 on page 209) if the buffer

underflows, and the M13_RDL_FIFO_AF bit is set (Table 237 on page 209) if the buffer reaches a provisionable fill

level. The fill level can be set to 16 bytes (M13_RDL_FILL[1:0] = 00 (Table 299)), 32 bytes (M13_RDL_FILL[1:0] =

01), 64 bytes (M13_RDL_FILL[1:0] = 10), or 96 bytes (M13_RDL_FILL[1:0] = 11).

The user may read bytes from the FIFO through register M13_RDL_DATA_R (Table 266 on page 217). The por-

tion of the earliest frame still in the FIFO can be deleted by setting M13_RDL_FRM_CLR to 1 (Tab le 270 on

page 218). (This is normally done to purge a corrupted or aborted frame.) The user must reset

M13_RDL_FRM_CLR before another frame can be deleted. If M13_RDL_FRM_CLR is set before the closing flag

of the frame currently being read from the FIFO has been received, all subsequent bytes of the frame will be dis-

carded without being written into the FIFO.

Frame Status and Error Reporting. The M13 provides information on the earliest frame still in the FIFO through

status register M13_RHDLC_STATUS_R (Table 268 on page 217).

The status register has 1 bit to indicate whether or not the closing flag (or an abort byte) for the current frame has

been received, 1 bit to indicate if the current frame is corrupted, 5 bits to indicate the size of the current frame mod-

ulo-32, and 1 bit to indicate whether or not there are less than 32 bytes of the earliest frame left in the FIFO.

There are four ways in which the M13 can identify that the current frame has been corrupted. The frame may have

been aborted (M13_RDL_ABORT = 1 (Table 265 on page 216)), it may have failed the CRC check

(M13_RDL_FCS_ERR = 1 (Table 265 on page 216)), the number of bits between opening and closing flags may

not have been a multiple of 8 (M13_RDL_NOT_BYTE = 1 (Table 265 on page 216)), or it may have been overwrit-

ten before being read from the FIFO (M13_RDL_OVFL = 1 (Table 265)). Also, there is a separate bit

M13_RDL_FLAG (Table 265) to indicate whether or not the closing flag (or an abort byte) for the current frame has

been received.

The size of the current frame modulo-128 (including FCS bytes only if M13_RDL_FCS = 0 (Table 299 on

page 227)) is indicated by register M13_RDL_FRAME_SIZE_R (Table 267 on page 217).

DS3 Performance Monitors. For performance monitoring purposes, there are a number of error counters in the

M13. All of these internal counters are comprised of a running error counter and a hold register that presents stable

results to the microprocessor. The counts in all of the running counters are latched to the hold registers, and the

running counters cleared with the configured internal performance monitor reset signal.

The latched results are then held to be read by the microprocessor. All of the internal counters have the ability to

store more than the maximum possible count in a one second interval for a bit error rate of 10–3. As long as the per-

formance monitor reset occurs at least once every second, no counts will be lost. In case this doesn’t happen, all of

the running counters will either hold their maximum value or roll over to zero, depending on the control signal input

SMPR_SAT_ROLLO V ER (Table 77 on page 70).

Within the M23 demultiplexer, there are four performance monitoring counters. M13_DS3_FERR_CNT[11:0]

(Table 301 on page 227) increments each time an error is detected in either an F bit or M bit, and

M13_DS3_PERR_CNT[13:0] (Table 304 on page 228) increments if at least one of the P bits disagrees with the

parity of the previous frame. In the C-bit parity mode only, M13_DS3_CPERR_CNT[13:0] (Table 303 on page 228)

counts frames with at least two of the three C-bit parity bits indicating an error, and M13_DS3_FEBE_CNT[13:0]

(Table 302 on page 228) accumulates FEBE error indications (1 error indication for each DS3 frame with at least

one FEBE bit equal to zero).

20.11.4 M12 Demultiplexers

Each M12 demultiplexer outputs either 4 DS1 signals from the DS2 frame as specified in GR-499-CORE (when

M13_DS1_E1Ny = 1 (Table 275 on page 220)), or three E1 signals from the DS2 format specified in ITU-T Recom-

mendation G.747 (when M13_DS1_E1Ny = 0). In the DS1 mode, the demultiplexed second and fourth channels

are inverted before being sent to the output selectors when M13_DEMUXCH2_4_INVy = 1 (Table 284 on

page 222).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

480 Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

Each M12 deMUX can be programmed independently to receive DS2 signal either from M23 deMUX (when

M13_M12DMX_MODEy[1:0] = 00 (Table 284 on page 222)) or direct DS2 input XC_DS2DMXDATAy (when

M13_M12DMX_MODEy[1:0] = 01). In the latter case, an input DS2 clock XC_DS2DMXCLKy is also required.

When M13_M12DMX_MODEy[1:0] = 10/11, the M12 demultiplexer is idle and the outputs are held low.

The DS2 signal is monitored for AIS, which is declared (M13_DS2_AIS_DETy = 1 (Table 254 on page 213)) if the

demultiplexer input is 0 for fewer than five clock cycles in each of two consecutive 840 clock periods, and cleared if

there are more than 4 zeros in each of two consecutive 840-bit periods (G.775).

20.11.5 DS1 Mode

Framer. The M12 demultiplexers determine if the input signal contains valid DS2 framing. This is done in two stages

by first finding a bit position that matches the M-subframe alignment pattern (F bits), and then locating the M frame

alignment signal (M bits). After a matching F-bit sequence is found, in-frame is declared (M13_DS2_OOFy = 0

(Table 252 on page 213)) whe n correct M bits ar e rece ived fo r three consec utiv e M frames . The m aximum averag e

reframe time is 2.5 ms in the presence of a bit error rate of 10–3.

Once the deMUX is in-frame, the received frame bits are monitored for out of frame. Out-of-frame is declared

(M13_DS2_OOFy = 1) if too many errors are received in either the F bits (two errors in 4 bits when

M13_DS2_MODE = 0 (Table 286 on page 222), or at least one F-bit error in four consecutive M-subframe pairs

when M13_DS2_MODE = 1) or the M-bits (at least one error in three consecutive M frames). For testing purposes,

the user may also force the framer out of frame by setting M13_DS2_FORCE_OOFy to 1 (Table 269 on pa ge 217 ).

The traditional algorithm for declaring out of frame (two errors in 4 F bits) results in false out of frame approximately

every 5 s when the bit error rate is 10–3. By waiting for four consecutive errored M-subframe pairs (containing 4-F

bits) before declaring out of frame (M13_DS2_MODE = 1), the M13 normally stays in frame for over four days

when the bit error rate is 10–3.

Overhead Processing. The C bits for each DS1 channel are checked for loopback requests. If the third C bit dif-

fers from the first and second C bits in the zth M-subframe for five successive DS2 frames, M13_DS1_LB_DETx is

set to 1 (Table 261 on page 215), where x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third C bit does

not differ from the first two C bits in the zth M-subframe for five successive DS2 frames.

If the X bit in four consecutive frames is received as 0, the M13 sets M13_DS2_RAI_DETy to 1 (Table 255 on

page 213). Once M13_DS2_RAI_DETy is set, it is not cleared until the X bit is received as 1 in four consecutive

frames.

20.11.6 E1 Mode

Framer. The M12 demultiplexers determine if the input signal contains a valid frame format as specified in ITU-T

Recommendation G.747. Frame alignment is declared (M13_DS2_OOFy = 0 (Tab le 252 on page 213)) when a

correct frame alignment signal is received for three consecutive frames. The maximum average reframe time is

0.5 ms in the presence of a bit error rate of 10–3. Out-of-frame is declared (M13_DS2_OOFy = 1) if the frame align-

ment signal contains at least 1-bit error for four consecutive frames. For testing purposes, the user may also force

the framer out of frame by setting M13_DS2_FORCE_OOFy to 1 (Table 269 on page 217).

Overhead Processing. The C bits for each E1 channel are checked for loopback requests. If the third Cz bit differs

from the first and second Cz bits for five successive frames, M13_DS1_LB_DETx is set to 1 (Table 261 on

page 215), where x = (4y – 4 + z). M13_DS1_LB_DETx is cleared when the third Cz bit does not differ from the first

two Cz bits for five successive frames.

If the RAI bit in four consecutive frames is received as 1, the M13 sets M13_DS2_RAI_DETy to 1 (Table 255 on

page 213). Once M13_DS2_RAI_DETy is set, it is not cleared until the RAI bit is received as 0 in four consecutive

frames. The received reserved bit is reported through the M13_DS2_RSV_RCVy (Table 257 on page 214), which

is updated only when a new value is received in four consecutive frames.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

481Agere Systems Inc.

20 M13/M23 MUX/DeMUX Block Functional Description (continued)

Loss of Frame and Automatic AIS Inse rtion. The M13_DS2_LOFy bit is set (Table 253 on page 213) when

M13_DS2_OOFy is high continuously for 28 DS3 frame periods (approximately 3 ms). Once set, M13_DS2_LOFy

is not cleared until M13_DS2_OOFy is continuously low for 28 DS3 frame periods.

The user can provision the M13 to automatically output AIS if either bit M13_DS2_OOFy = 1 (by setting

M13_AUTO_AIS_OOF to 1), or M13_DS2_LOFy = 1 (by setting M13_AUTO_AIS_LOF to 1).

DS2 Performance Monitors. Within each M12 demultiplexer, there are two performance monitoring counters.

These counters are cleared and read as described above (see DS3 Performance Monitors Section on page 479).

Registers M13_DS2_FERR_CNT[7—1]_R (Table 306 on page 229) count errors in the frame alignment signal. In

the DS1 mode, M13_DS2_FERR_CNTy (Table 306) increments each time an error is detected in either an F bit or

M bit. In the E1 mode, this counter increments either for each frame alignment signal bit error (when

M13_DS2_FERR_MODE = 0 (Table 286 on page 222)), or once for each frame alignment signal that contains at

least one bit error (when M13_DS2_FERR_MODE = 1).

In the E1 mode only, registers M13_DS2_PERR_CNT[7—1]_R[1—2] (Table 305 on page 228) count errors in P

bits.

20.11.7 Output Select Logic

DS2 Output Selection. The M23 demultiplexer outputs are fed into seven DS2 output selection logic blocks. This

allows the M13 to output the demultiplexed DS2 signals or insert AIS.

Each selector is identified by a number y that ranges from one to seven and corresponds directly to M13 outputs

M13_DS2DATA[7—1]. The outgoing DS2 signals are retimed by an associated clock, M13_DS2CLK[7—1]. The

edge of the clocks that is used to retime the data is provisionable to either the rising edge (M13_TDS2_EDGE = 1

(Table 306)) or falling edge (M13_TDS2_EDGE = 0).

The output from each selection block is controlled by the values of bits M13_DS2_OUT_IDLEy (Table 2 96 on

page 226) and M13_DS2_OUT_AISy (Table 297 on page 226).

■Output is held low when M13_DS2_OUT_IDLEy = 1; otherwise, the deMUXed DS2 signal is output when

M13_DS2_OUT_AISy = 0 and DS2 AIS is output when M13_DS2_OUT_AISy = 1.

The all-ones DS2 AIS signal is also output under all failure conditions at DS3 level which require automatic AIS

insertion at DS2 level.

DS1/E1 Output Selection. The M12 demultiplexer outputs are fed into 28 DS1/E1 output selection logic blocks.

This allows the M13 to output the demultiplexed DS1/E1 (M13_DS1_OUT_AISx = 0 (Table 285 on page 222)), or

insert AIS (M13_DS1_OUT_AISx = 1). The all-ones AIS signal is also output under all failure conditions at DS3 or

DS2 level which require automatic AIS insertion at DS1/E1 level.

Each selector is identified by a number x that ranges from 1 to 28 and corresponds directly to a block output

M13_DS1DATA[28—1]. The outgoing DS1 and/or E1 signals are retimed by an associated clock,

M13_DS1CLK[28—1]. The edge of the clock that is used to retime the data is provisionable to either the rising

edge (M13_TDS1_EDGEx = 1 (Table 284 on page 222)) or falling edge (M13_TDS1_EDGEx = 0).

Each output selector number, x can be expressed as either 4y – 3, 4y – 2, 4y – 1, or 4y, where y ranges from 1

to 7. For a given y, the four selectors in the group output DS1 signals when M13_OUT_TYPEy = 1 (Table 284), or

E1 signals when M13_OUT_TYPEy = 0. In either of these modes, the four selectors in the group are controlled by the

2-bit values OUTSELx, where x = 4y – 3, 4y – 2, 4y – 1, and 4y.

When M13_OUT_TYPEy = 0, the output of selector 4y is held low.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

482 Agere Systems Inc.

21 28-Channel Framer Block Functional Description

Table of Con t ents

Contents Page

21 28-Channel Framer Block Functional Description .........................................................................................4802

21.1 28-Channel Framer Introduction ..............................................................................................................486

21.1.1 D S0/E0 Swi tc hin g Applic ation s ............................. ....... ...... ................... ....... ...... ....... .................... 486

21.2 Transport Applications..............................................................................................................................489

21.3 Framer-to-Line Interface Unit Physical Interface......................................................................................492

21.3.1 Line Interface References/Standards ........................................................................................... 492

21.3.2 Frame Formats . ....... ...... ....... ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... .................... 492

21.3.3 Transm it Fram er Functions ......... ....... ...... ....... ...... ....... ...... ...... ....... ...... ....... ...... ....... .................... 493

21.3.4 Framin g Referenc es/S tand ards .. ....... ...... ....... ...... ................... ....... ...... ....... ...... ....... .................... 493

21.4 DS1 Transparent Framing Format ...........................................................................................................493

21.5 CEPT 2.048 Basic Frame Structure Transparent Framing Format..........................................................494

21.6 Receive Framer Nonalignment Mode (DS1/E1).......................................................................................495

21.6.1 Loss of Frame Alignment Criteria ................................................................................................. 495

21.7 Frame Alignment Criteria .........................................................................................................................496

21.8 Receive and Transmit Signaling Processor .............................................................................................496

21.8.1 Si gnalin g Intr oducti on and Featu re Description ........... ...... ...... ....... ...... ....... ................... ....... ....... 496

21.8.2 Si gnalin g Refer ences /S tan dards .................... ...... ....... ...... ................... ....... ...... ....... .................... 497

21.9 Receive Signaling Per-Link Feature Provisioning ....................................................................................497

21.9.1 Signaling State Mode Source Selection ........................................................................................ 498

21.9.2 Signaling State Mode Selection .................................................................................................... 498

21.9.3 Signaling Source Selection ........................................................................................................... 498

21.9.4 Signaling Destination Selection .................................................................................................... 499

21.10 Optional Receive Signaling Features Provisioned for Each Link ...........................................................501

21.10.1 Support of DS1 Robbed-Bit Stomping ........................................................................................ 501

21.10.2 Support of CEPT Time Slot 16 Stomping ................................................................................... 501

21.10.3 Support of Signaling Debounce .................................................................................................. 501

21.10.4 Support of Japanese Handling Groups ....................................................................................... 501

21.11 Receive Signaling Global Feature Provisioning .....................................................................................501

21.11.1 Link Count Selection ................................................................................................................... 502

21.12 Other Receive Signaling Global Features..............................................................................................502

21.12.1 Support of Automatic Signaling Freeze on Framing Bit Errors ................................................... 502

21.12.2 Support of Change of Signaling State FIFO ............................................................................... 502

21.13 Receive Signaling Interrupts ..................................................................................................................503

21.13.1 Maintenance of the Change of Signaling State FIFO Status Bits ............................................... 503

21.13.2 Maintenance of Handling Group-Related Status Bits ................................................................. 503

21.14 Transmit Signaling Per-Link Feature Provisioning.................................................................................504

21.14.1 Signa li ng Sta te Mode Sou rce Se lec ti on . ....... ...... ....... ...... ...... .................... ...... ....... .................... 504

21.14.2 Signaling State Mode Selection .................................................................................................. 505

21.14.3 Signa li ng Sou rce Selec tio n . ...... ....... ...... ....... ...... ....... ...... ...... ....... ...... .................... ...... .............. 505

21.14.4 Signaling Destination Selection .................................................................................................. 507

21.15 Optional Transmit Signaling Features Provisioned for Each Link..........................................................508

21.15.1 Support of Automatic Maintenance of the Time Slot 16 Remote Frame Alarm .......................... 508

21.15.2 Support of DS1 Robbed-Bit Stomping ........................................................................................ 508

21.15.3 Support of CEPT Time Slot 16 Stomping ................................................................................... 508

21.15.4 Support of Signaling Debounce .................................................................................................. 508

21.15.5 Support of Japanese Handling Groups ....................................................................................... 508

21.15.6 Support of Zero-Code Suppression ............................................................................................ 508

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

483Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table of Conten ts (continued)

Contents Page

21.16 Transmit Signaling Global Feature Provisioning ....................................................................................509

21.16.1 Link-Count Selection ................................................................................................................... 509

21.17 Other Transmit Signaling Global Features.............................................................................................509

21.17.1 Support of Automatic Signaling Freeze on Framing Bit Errors ................................................... 509

21.17.2 Support of Byte-Sync SONET Mapping ...................................................................................... 509

21.18 Transmit Signaling Status Registers ......................................................................................................509

21.18.1 Maintenance of CEPT Related Status Bits ................................................................................. 509

21.19 Performance-Monitoring Functional Integration into Superframer .........................................................510

21.20 Performance Report Message ...............................................................................................................514

21.21 Performance-Monitoring References/Standards....................................................................................515

21.22 Facility Data Link....................................................................................................................................516

21.22.1 Facility Data Link References/Standards .................................................................................... 516

21.22.2 Receive Data Link Functional Description .................................................................................. 516

21.22.3 SLC-96 Superfra me Receiv e Data Lin k ........ ...... ...... ....... ...... ....... ...... .................... ...... ....... ...... . 516

21.22.4 DDS Receive Data Link Stack .................................................................................................... 516

21.22.5 CEPT; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms) Multiframe Sa Bits Receive Stack ....... 517

21.22.6 Receive Data Link Stack Idle Modes .......................................................................................... 518

21.22.7 Receive Data Link Stack Pointer ................................................................................................ 518

21.22.8 Transmit Facility Data Link Functional Description ..................................................................... 520

21.22.9 SLC-96 Superframe Transmit Data Link ..................................................................................... 520

21.22.10 DDS Transmit Data Link Stack ................................................................................................. 521

21.22.11 Transmit ESF Data Link Bit-Oriented Messages ...................................................................... 522

21.22.12 CEPT, CEPT Multiframe Transmit Data Link Sa Bits Stack ..................................................... 522

21.22.13 Transmit Data Link Stack Idle Modes ....................................................................................... 523

21.22.14 SLC-96, DDS, or CEPT ESF Frame Alignment ........................................................................ 523

21.23 HDLC Functional Description.................................................................................................................524

21.24 HDLC Operation.....................................................................................................................................524

21.24.1 Zero-Bit Insertion/Deletion (Bit Stuffing/Destuffing) .................................................................... 524

21.24.2 Flags ........................................................................................................................................... 524

21.24.3 Aborts .......................................................................................................................................... 525

21.24.4 Receive IDLES ............................................................................................................................ 525

21.24.5 CRC ............................................................................................................................................ 525

21.24.6 HDLC Mode ................................................................................................................................ 526

21.24.7 Receive HDLC Transparent Mode .............................................................................................. 526

21.24.8 Receive HDLC ............................................................................................................................ 526

21.24.9 Receive HDLC Features ............................................................................................................. 526

21.24.10 Transmit HDLC FIFO Features ................................................................................................. 527

21.25 Framer Phase-Lock Loop (PLL).............................................................................................................529

21.25.1 Framer Timing Selection ............................................................................................................. 530

21.26 System Interface ....................................................................................................................................530

21.26.1 System Interface Introduction ..................................................................................................... 530

21.26.2 System Interface References/Standards .................................................................................... 531

21.26.3 Transmit/Receive System Interface Features ............................................................................. 531

21.26.4 Double NOTFAS System Time Slot (FRM_DNOTFAS) Mode ................................................... 532

21.26.5 Transparent Mode ....................................................................................................................... 532

21.26.6 Loopbacks ................................................................................................................................... 532

21.26.7 System AIS ................................................................................................................................. 532

21.26.8 Slip Detection .............................................................................................................................. 533

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

484 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table of Conten ts (continued)

Contents Page

21.26.9 The Concentration Highway (CHI) Mode .................................................................................... 533

21.26.10 Nominal CHI Timing .................................................................................................................. 533

21.26.11 CHI Timing with CHI Double Time-Slot Timing (CHIDTS) Mode Enabled ................................ 535

21.26.12 CHI Timing with Associated Signaling Mode Enabled .............................................................. 535

21.26.13 ASM 2-Byte Time-Slot Format .................................................................................................. 536

21.26.14 CEPT: Time Slot 16 Signaling ASM 2-Byte Time-Slot Format ................................................. 537

21.26.15 CHI Offset Programming ........................................................................................................... 537

21.26.16 The Parallel Bus System Interface Mode .................................................................................. 539

21.26.17 Distributed Stuffing: DS1 .......................................................................................................... 540

21.26.18 Distributed Stuffing: E1 ............................................................................................................. 542

21.26.19 Drive to 3-State and 3-State to Drive Timing ............................................................................ 543

21.27 Serial Multiplex Interface........................................................................................................................543

21.27.1 Signals (6-Pin Mode) .................................................................................................................. 544

21.27.2 Signals (8-Pin Mode) .................................................................................................................. 544

21.27.3 Timing Diagrams ......................................................................................................................... 545

21.27.4 Time-Slot Sequencing ................................................................................................................ 546

21.27.5 Timing Between Transmit and Receive ...................................................................................... 546

21.28 Superframer Host Interface....................................................................................................................547

21.28.1 Superframer Register Addressing ............................................................................................... 547

21.29 Superframer Register Addressing..........................................................................................................548

21.29.1 Per Link Register Sections in the Above Table ........................................................................... 548

Figures Page

Figure 53. Switching Application of the Supermapper...........................................................................................486

Figure 54. Supermapper Switching Configuration.................................................................................................487

Figure 55. Supermapper Switching Mode for Framer in DS0 Interface (Parallel or Serial) Configuration ............488

Figure 56. Transport Application of the Supermapper...........................................................................................489

Figure 57. Supermapper Transport Configuration.................................................................................................480

Figure 58. Supermapper Transport (with Intrusive Performance Monitoring) Mode .............................................491

Figure 59. DS1 Transparent Frame Structure.......................................................................................................493

Figure 60. CEPT Transparent Frame Structure ....................................................................................................494

Figure 61. HG Alignment Algorithm.......................................................................................................................504

Figure 62. Rx Data Link Block Diagram ................................................................................................................518

Figure 63. Stack Available and Stack Ready Bit Formatting.................................................................................519

Figure 64. Tx Data Link Block Diagram.............. ....... ...... ....... ...... ................... ....... ...... ....... ...... ............................523

Figure 65. Receive HDLC Block Diagram.............................................................................................................526

Figure 66. Transmit HDLC FIFO Block Diagram...................................................................................................527

Figure 67. Framer PLL ..........................................................................................................................................529

Figure 68. Framer Block Transmit Path Timing Selection.....................................................................................530

Figure 69. System Loopbacks...............................................................................................................................532

Figure 70. CHI Mode of the Transmit System Interface........................................................................................533

Figure 71. Nominal Concentration Highway Interface Timing...............................................................................534

Figure 72. CHIDTS Mode Concentration Highway Interface Timing.....................................................................535

Figure 73. Associated Signaling Mode Concentration Highway Interface Timing.................................................536

Figure 74. TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 0............................................538

Figure 75. CHI TCHIDATA and RCHIDATA to CHICK Relationship with FRM_CMS = 1.....................................539

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

485Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table of Conten ts (continued)

Figures (continued) Page

Figure 76. Parallel Bus System Interface Mode of the Transmit System Interface ...............................................539

Figure 77. Parallel Bus System Interface Turnaround Timing...............................................................................543

Figure 78. Signals (6-Pin Mode)............................................................................................................................544

Figure 79. Signals (8-Pin Mode)............................................................................................................................544

Figure 80. Network Serial Multiplexed Interface (Single Octet).............................................................................545

Figure 81. Network Serial Multiplexed Interface (Multiple Octets).........................................................................546

Tables Page

Table 588. Frame Alignment Criteria.....................................................................................................................496

Table 589. Receive Signaling Link Registers 0—31 Bit Description......................................................................498

Table 590. Receive Signaling Link Registers 0—31 G-Bit and F-Bit Description..................................................498

Table 591. Receive Signaling Link Registers 0—31 DS1/CEPT/CMI Data...........................................................500

Table 592. Receive Signaling Link Registers 0—31 Expected Data.....................................................................501

Table 593. Signaling Receive Global Register 3, Bit Definition .............................................................................502

Table 594. Transmit Signaling Link Registers 0—31 Bit Description.....................................................................505

Table 595. Transmit Signaling Link Registers 0—31 G-Bit and F-Bit Description.................................................505

Table 596. Transmit Signaling Link Registers 0—31 DS1/CEPT/CMI Data..........................................................506

Table 597. Transmit Signaling Link Registers 0—31 Expected Data ....................................................................507

Table 598. Performance Monitor Functional Descriptions.....................................................................................510

Table 599. Performance Report Message Format.................................................................................................514

Table 600. Performance Report Message Field Definition....................................................................................514

Table 601. Shared Rx Stack Format for SLC-96 Frames......................................................................................516

Table 602. Shared Rx FDL Stack Format for DDS Frames...................................................................................517

Table 603. Shared Rx Stack Format for CEPT Frames.........................................................................................517

Table 604. Shared Tx FDL Stack Format for SLC-96 Frames...............................................................................520

Table 605. Shared Tx FDL Stack Format for DDS Frames ...................................................................................521

Table 606. Shared Tx Stack Format for CEPT Frame...........................................................................................522

Table 607. HDLC Frame Format ...........................................................................................................................524

Table 608. Performance Report Message Structure .............................................................................................528

Table 609. Clock Mode Programming for PLL Mode Device Pins.........................................................................529

Table 610. Associated Signaling Mode CHI 2-Byte Time-Slot Format for DS1 Frames........................................536

Table 611. Associated Signaling Mode CHI 2-Byte Time-Slot Format for Stuffed Channels.................................537

Table 612. Associated Signaling Mode CHI 2-Byte Time-Slot Format for CEPT...................................................537

Table 613. Programming Values for FRM_TOFF[2:0] and FRM_ROFF[2:0] when FRM_CMS = 0 ......................537

Table 614. Programming Values for FRM_TOFF[2:0] when FRM_CMS = 1.........................................................537

Table 615. Programming Values for FRM_ROFF[2:0] when FRM_CMS = 1 ........................................................537

Table 616. Parallel System Bus Interface Time-Slot Arrangement for DS1...........................................................541

Table 617. Parallel System Bus Interface Ti me-Slot Arrangement for E1 .............................................................542

Table 618. PSB System I/O Definition...................................................................................................................542

Table 619. Serial ID ...............................................................................................................................................545

Table 620. Current Number of Global and Per-Link/Channel Registers for Each Block........................................547

Table 621. Framer Addressing Map for the Global and Per-Link/Channel Registers of the Superframer.............548

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

486 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.1 28-Channel Framer Introd uction

The next two sections describe the switching and transport mode of the superframer . The framer can be configured

into two basic modes: DS0/E0 switching mode and DS1/E1 transport/monitoring mode.

21.1.1 D S0/ E0 Swit chin g Applic at ion s

The switching application of the Supermapper/superframer is shown in Figure 53 and Figure 54. The system inter-

face is either a parallel interface (e.g., system telecom bus interface) or a serial system interface (e.g., CHI) that

transmits or receives framed (channelized) or unframed (unchannelized) DS0/E0 time slots.

In the transmit line direction (Tx, to the mapper), the framer receives data from the DS0/E0 switch through the sys-

tem interface and sends this data (framed or unframed) to the mapper Section via the internal DS1 cross connect

block. The data consists of data, clock, and frame sync.

In the receive line direction (Rx), the mapper sends the line data and clock (through the internal DS1 cross con-

nect) to the framer block. The framer then takes this data and transmits it to a DS0/E0 switch through the system

interface. Links provisioned for extended superframe format (ESF) can automatically generate and send perfor-

mance message reports (PRMs) from the Rx path performance monitor through a Tx path HDLC channel assigned

to the facility data link in the transmit line path.

5-8924(F)r.1

Figure 53. Switching Application of the Supermapper

FRAMER MAPPER

FRAMERMAPPER

SUPERMAPPER #1 SUPERMAPPER #1

SUPERMAPPER #2 SUPERMAPPER #2

SUPERMAPPER #3SUPERMAPPER #3

MAPPER

TELECOM

BUS

STS-3

SYSTEM

INTERFACE SYSTEM

INTERFACE

DS0/E0

SWITCH DS0/E0

SWITCH

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

487Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9017(F)r.1

Figure 54. Supermapper Switching Configuration

FRAMER

RECEIVE LINE TO TRANSMIT

SYSTEM PATH

(Rx PATH)

FRAM ER R EC E IVE SYST EM

TO TRANSMIT LINE PATH

(Tx PATH )

SUPERMAPPER: FRAMER

FDL PRMs

LOOPBACKS

RFS1,

RCLK1,

RDATA28

TFS1,

TCLK1,

TDATA28

SYSTEM INTERFACE

DS0 I/O

DS2 I/O DS3 I/O SONET/SDH DS3

MAPPED I/O

DS3 OR T1/E1 TO STS-1

MAPPED O UT PU T

(HIGH-SPEED TELECOM BUS)

M12

MULTIPLEXER DS3 MAPPER

8-bit DATA + 1-bit PARITY

VT/VC

MAPPER VC-4

MULTIPLEXER STM-1

MULTPLEXER

MAPPER

FRAMER

DS1 CROSS

CONNECT

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

488 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Figure 55 shows the framer block in a switching application. The framer system interface for the transmit path is

labeled receive and the receive path is labeled transmit. This may seem an error but is chosen based on estab-

lished, his to ri ca l naming conventi on.

5-9018(F)

Note: The Optional Byte-Synchronous VT Mapping Path Is Shown

Figure 55. Supermapper Switching Mode for Framer in DS0 Interface (Parallel or Serial) Configuration

VT MAPP ER :

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING RECEIVE DATA

RECEIVE SIGNALING DATA

(TO SIGNALING REGISTERS)

VT MAPP ER :

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING TRANSMIT DATA

RECEIVE

HDLC RECEIVE

FACILITY

DATA LINK

SUPERMAPPER

VT MAPPER

INTERFACE

RECEIVE

FRAME

ALIGNER

SIGNALING

PROCESSOR

(EXTRACTION)

TRANSMIT

SYSTEM

INTERFACE

TFS1, TCLK1, TDATA 28

SIGNALING

PROCESSOR

(INSERTION)

RECEIVE

SYSTEM

INTERFACE

TRANSMIT

FACILITY DATA

LINK

TRANSMIT

FRAME

FORMATTER

SUPERMAPPER

M12

MULTIPLEXER

INTERFACE

Rx PATH

Tx P ATH

ESF PRM PATH

TFS1, TCLK1, TDATA8,

TDATA_PARITYA1

TSIGNALING8,

TSIGNALING_PARITYA1

RFS1, RCLK1, RDATA28

RFS1, RCLK1, RDATA8,

RDATA_PARITYA1

RSIGNALING8,

RSIGNALING_PARITYA1

SYSTEM INTERFACE

PARALLEL DS0 BUS

SYSTEM INTERFACE

SERIAL DS0 BUS

SUPERMAPPER: FRAMER

TRANSMIT SIGNALI NG DATA (EXTRACTED

FROM SYSTEM INTERFACES OR

SIGNALING REGISTERS)

PERFORMANCE

MONITOR

TRANSMIT

HDLC

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

489Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.2 Transport Applications

The transport application of the Supermapper is depicted in Figure 56, Figure 57, and Figure 58. The Superm ap-

per interfaces with LIUs at the DS1/E1 rate in this mode. The data is either framed or unframed DS1s. In the trans-

mit path direction (Tx, to the mapper), the framer receives framed or unframed DS1/E1 data from its line interface

and sends this line data and clock (via the DS1 cross connect) to the mapper block. The framer can be provisioned

to frame align the data prior to sending it to the mapper Section. The framer can be provisioned for performance

monitoring on the data and in ESF mode, transmit PRMs back to its line interface.

In the receive path direction (Rx), the mapper sends the line data and clock (through the DS1 cross connect) to the

framer block. This data may be framed or unframed DS1/E1 data. The framer can be provisioned to frame align the

data and transmit a frame sync signal in addition to the data and clock. The framer can be provisioned for perfor-

mance monitoring on the data. In ESF mode, it can automatically generate and send PRMs back to the mapper

interface.

5-8925(F)r.1

Figure 56. Transport Application of the S upermapper

FRAMER MAPPER

FRAMERMAPPER

SUPERMAPPER #1 SUPERMAPPER #1

SUPERMAPPER #2 SUPERMAPPER #2

SUPERMAPPER #3SUPERMAPPER #3

MAPPER

TELECOM

BUS

STS-3

LINE

INTERFACE LINE

INTERFACE

PM PM

PMPM

T1/E1

LINE INTERFACE

UNIT

(T7690 OR T7698)

T1/E1

LINE INTERFACE

UNIT

(T7690 OR T7698)

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

490 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9020(F)r.1

Figure 57. Supermapper Transport Configuration

FRAMER

DS1 RECEIVE LINE PATH

PERFORMANCE MONITORING

(Rx PATH)

DS1 TRANSMIT LINE PATH

PERFORMANCE MONITORING

(Tx PATH )

SUPER M APPER : FRAMER

FDL PRM s

LOOPBACKS

MAPPER-

TO-

FRAMER I/O

CROSS

CONNECT

VT/VC

MAPPER VC-4

MULTIPLEXER STM-1

MULTIPLEXER

8-bit DATA + 1-bit PARITY

DS3

MAPPER

M12

MULTIPLEXER

DS2 I/O DS3 I/O SONET/SDH DS3

MAPPED I/O

RLCK28,

RPD28,TLCK28,

LINE INTERFACE

DS1 I/O

TPD28,

TND28

RND28 DS3 OR T1/E1 TO ST S- 1

MAPPED OUTPUT

(HIGH- SPE ED T ELE C O M BU S )

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

491Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9021(F)r.2

Note: The Optional Byte-Synchronous VT Mapping Path is Shown

Figure 58. Supermapper Transport (with Intrusive Performance Monitoring) Mode

RECEIVE

SIGNALING

PROCESSOR

RX SIGNALING DA TA

(TO SIGNALING REGISTERS)

RECEIVE

HDLC RECEIVE

FACILITY

DATA

LINK

RECEIVE

FRAME

ALIGNER

VT MAPPER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING RECEIVE DATA

VT MAPPER:

BYTE-SYNCHRONOUS ROBBED-BIT

SIGNALING TRANSMIT DATA

SUPERMAPPER

VT MAPPER

INTERFACE

SUPERMAPPER

M12

MULTIPLEXER

INTERFACE

ESF PRM PATH

PERFORMANCE

MONITOR

TRANSMIT

FRAME

FORMATTER

TRANSMIT

HDLC

TRANSMIT

FRAME

FORMATTER

RECEIVE

FRAME

ALIGNER

TRANSMIT

HDLC

PERFORMANCE

MONITOR

ESF PRM PA TH

TX PATH

SIGNALING

PROCESSOR

TRANSMIT

FACILITY

DATA

LINK

TRANSMIT SIGNALIN G DATA

SUPERMAPPER: FRAMER

RX PATH

TX PATH

TX LINE

ENCODER

RX LINE

DECODER

RLCK28, RPD28, RND28

TLCK28, TPD28, TND28

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

492 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.3 Framer-to-Line Interface Unit Physical Interface

The framer-LIU interface of the Supermapper framer consists of 28 groups of six connections. The internal DS1

cross connect must be configured to connect the framer-LIU interface through the multifunction system interface to

external T1/E1 line interface devices. The six connections for each framer are TND, TPD, and TLCK driven from

the transmit framer (receive path) and RPD, RND, and RCLK (transmit path) sourced from the external line inter-

face device. The connections can optionally be from/to the protected switch. See Table 3 on page 17 for the exter-

nal pin names that correspond to the desired six connections.

The line interface may operate in single-rail or dual-rail mode. The default mode of the line encoder is single-rail

(FRM_LD_MODE[2:0] = 000 (Table 442 on page 308), FRM_LE_MODE[2:0] = 000 (Table 443 on page 308)). In

this mode, the input signals are passed transparently through the line encoder.

In single-rail mode, the link’s framer internal bipolar line encoder/decoder is disabled, and monitoring of received

line format violation is accomplished with the use of the RND input. When RND = 1 on the rising edge of RLCK, the

line format violation FRM_BPV[15:0] (Table 400 on page 289) counter increments by one. The link’s transmit

framer transmits data via the TPD output pin while TND is forced to a 0 state.

In dual-rail mode, the internal line encoder/decoder and monitoring are enabled. The line code may be selected by

provisioning FRM_LD_MODE[2:0] and FRM_LE_MODE[2:0]:

1. Alternate Mark Inversion (AMI).

2. High-Density Bipolar of Order 3—G.703, A.1 (HDB3).

3.Binary 8 Zero Code Suppression—G.703, A.2 (B8ZS).

Line format violations due to excessive zeros will be optionally monitored as follows:

1. B8ZS—8 consecutive zeros cause a violation.

2. HDB3—4 consecutive zeros cause a violation.

21.3.1 Line Interface References/Standards

1. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces;1991.

2. ANSI T1.403-1995, Network-to-Customer Installation - DS1 Metallic Interface; March 21, 1995.

21.3.2 Fr ame Form ats

The 28 superframers support the following frame formats:

1. DS1 super fr ame D4.

2. DS1 superframe J-D4 with Japanese remote alarm.

3. DS1 super frame DDS.

4. DS1 sup erfr ame SLC-96.

5. DS1 ext end ed super fr ame (ESF).

6. Japanese extended superframe J-ESF (J1 standard with different CRC-6 algorithm).

7. Nonalig n DS1 (tran sp ar ent 193 bit s).

8. CEPT basic frame {ITU G.706}.

9. CEPT CRC-4 multiframe with 100 ms timer {ITU G.706}.

10. CEPT CRC-4 multiframe with 400 ms timer (automatic CRC-4/nonCRC-4 equipment interworking) {ITU G.706

Annex B}.

11. Nona li gn E1 (tran spar ent 256 bit s).

12. 2.048 coded mark inversion (CMI) coded interface (TTC Standards JJ-20.11).

13. 6.312 Mbits/s interface (ITU G.704/NTT J2).

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

493Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.3.3 Transmit Framer Functions

1. Transmits alarm indication signal (AIS) to the line automatically and on demand.

2. Transmits AIS-CI to the line automatically and on demand.

3. Transmits remote alarm indication (RAI) to the line automatically and on demand. Conditions for transmitting

RAI include: loss of received frame alignment, CEPT loss of received time slot 0 multiframe alignment, CEPT

CRC-4 timer expiration, CEPT loss of received time slot 16 signaling multiframe alignment, CEPT received Sa6

equals 8, and received Sa6 equals C.

4. Transmits RAI-CI to the line automatically and on demand.

5. Transmits auxiliary test pattern (AUXP) to the line automatically and on demand.

6. Transmits CEPT E bits based received CRC-4 errors.

7. Support the CEPT double NOTFAS system mode.

8. Transmits a PRBS test pattern to the line on demand.

9. Transmits line loopback on and off codes to the line on demand (T1.403 Section 9.3.1).

10. In transport mode, when not in frame alignment, to optionally send AIS or transparently pass data.

21.3.4 Fr aming Referen c es/St and ards

1. ANSI T1.403, 1997.

2. ITU-T Recommendation G.703, Physical/Electrical Characteristics of Hierarchical Digital Interfaces; 1991.

3. ITU-T Recommendation G.704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488, and

44736 kbits/s Hierarchical Levels; July 1995.

4. ITU-T Recommendation G.706, Frame Alignment and Cyclic Redundancy Check (CRC) Procedures Relating to

Basic Frame Structures defined in Recommendation G.704; 1991.

5. TTC Standard JT-G704, Synchronous Frame Structures used at 1554, 6312, 2048, 8488, and 44736 kbits/s

Hierarc hic al Lev el s; Ju ly 1995.

21.4 DS1 Transparent Framing Format

The transmit framer can be programmed to transparently transmit 193 bits of CHI system data to the line.

When configured for transparent framing, the transmit framer extracts from the receive CHI system data bit 8 of

time slot 1 and inserts this bit into the framing bit position of the transmit line data. The other 7 bits of the receive

system time slot 1 are ignored by the transmit framer. The receive framer will extract the framing bit (or 193rd bit) of

the receive line data and insert it into bit 8 of time slot 1 of the CHI system data. The other bits of time slot 1 are set

to 0.

Frame integrity is maintained in both the transmit and receive framer sections.

5-5989(F).ar.1

Figure 59. DS1 Transparent Frame Structure

TIME SLOT 1

(STUFF TIME SLOT)

32 TIME SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

0000000F BIT

TRAMSMIT FRAMER’S

193-bit FRAME

DS 1 = 125 µs

TIME SLOT 1 TIME SLOT 2 TIME SLOT 24F BIT

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

494 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipo-

lar violations and unframed AIS monitoring, there is no processing of the receive line data. The receive framer will

insert the 193rd bit of the receive line data into bit 8 of time slot 1 of the transmit system data.

Bit 8 of time slot 1 of the receive system interface is inserted as the 193rd data bit into the transmit line data.

Transparent framing mode 1 is selected by setting FRM_LNK_TRANSP to 1 (Table 433 on page 300) and

FRM_MO DE[ 3:0] to 1000 (Tab le 434 on page 301) (nonalign 193rd bit).

In transparent framing mode 2, the receive framer functions normally on receive line data. All normal monitoring of

receive line data is performed and data is passed to the transmit CHI as programmed. The receive framer will

insert the extracted framing bit of the receive line data into bit 8 of time slot 1 of the transmit system data. The

remaining bits in time slot 1 are set to 0.

Bit 8 of time slot 1 of the receive system interface is inserted in the transmit line framing bit position.

Transparent framing mode 2 is selected by setting FRM_LNK_TRANSP to 1 (Table 433 on page 300) and select-

ing the appropriate framing mode with FRM_MODE[3:0] (Table 434 on page 301).

21.5 CEPT 2.048 Basic Frame Structu re Transparent Framing Fo rma t

The transmit framer can be programmed to transparently transmit 256 bits of CHI system data to the line. The

transmit framer must be programmed to transparent framing mode 1.

In transparent mode, the transmit framer transmits all 256 bits of the system payload unmodified to the line. time

slot 1 of the CHI system interface, determined by the system frame sync signal, is inserted into the FAS/NOTFAS

time slot of the transmit line interface.

Frame integrity is maintained in both the transmit and receive framer sections.

5-5988(F)

Figure 60. CEPT Transparent Frame Structure

In transparent framing mode 1, the receive framer is forced not to reframe on the receive line data. Other than bipo-

lar violations and unframed AIS monitoring, there is no processing of the receive line data. The entire receive line

payload is transmitted unmodified to the CHI.

Transparent framing mode 1 is selected by setting FRM_LNK_TRANSP to 1 (Table 433 on page 300) and

FRM_MO DE[ 3:0] to 0000 (Tab le 434 on page 301) (nonalign 256th bit).

In transparent framing mode 2, the receive framer functions normally on the receive line data. All normal monitor-

ing of receive line data is performed and data is transmitted to the CHI as programmed.

Transparent framing mode 2 is selected by setting FRM_LNK_TRANSP to 1 (Table 433) and selecting the appro-

priate framing mode with FRM_MODE[3:0] (Table 434).

TIME SL OT 1 32 TIME SLOT CHI FRAMETIME SLOT 2 TIME SLOT 3 TIME SLOT 31 TIME SLOT 32

TIME SL OT 1 32 TIME SLOT LINE FRAMETIME SLOT 2 TIM E SLO T 3 T IM E SLO T 31 TIME SLOT 32

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

495Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.6 Receive Framer Nonalignment Mode (DS1/E1)

In the nonalign framing modes, the receive frame aligner does not frame to the receive line data. Other than bipolar

violations, AIS, and AUXP monitoring, there is no processing of the receive line data. The entire receive line frame

is given unmodified to the system interface.

21.6.1 Loss of Frame Alignment Criteria

There are two criteria for declaring loss of frame: frame bit errors and CRC errors.

Frame Bit Errors.

1. T1: two frame bit errors out of 4 frame bits (FT and FS bits checked).

2. T1: two frame bit errors out of 5 frame bits (FT and FS bits checked).

3. T1: two frame bit errors out of 6 frame bits (FT and FS bits checked).

4. T1: three frame bit errors out of 12 frame bits—DDS only (FT, FS, and time slot 24 F bits).

5. T1: two frame bit errors out of 4 frame bits (only FT bits checked).

6. T1: two frame bit errors out of 5 frame bits (only FT bits checked).

7. T1: two frame bit errors out of 6 frame bits (only FT bits checked).

8. T1: four frame bit errors out of 12 frame bits—DDS only (FT, FS, and time slot 24 FAS pattern).

9. E1: three consecutive incorrect frame alignment signals.

10. E1: three consecutive incorrect frame alignment signals or three consecutive incorrect non-F AS frames as indi-

cated by bit 2 in time slot 0 in frames not containing the frame alignment signal.

11. E1: 3 consecutive incorrect FAS or non-FAS frames.

12. 2.048 Mbits/s CMI: 2 consecutive missing code rule violations (CRVs).

CRC Errors.

The use of CRC errors to declare loss of frame is optional. CRC errors are monitored in the performance monitor

block.

In DS1 mode, ESF, and J-ESF formats only, N or more CRC-6 errors in a 1 s interval results in loss of frame align-

ment. N is provisionable. N defaults to 320 in DS1 mode.

In CEPT mode, N or more CRC-4 errors in a 1 s interval results in loss of frame alignment. N is provisionable. N

defaults to 915 in CEPT modes.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

496 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.7 Frame Alignment Criteria

Table 588 describes the frame alignment criteria for the formats supported by the superframer.

Table 588. Frame Alignment Criteria

21.8 Receive and Transmit Signaling Processor

21.8.1 Signaling Intr oduction and Feat ure Description

The signaling processor, which is duplicated in the receive and transmit paths, moves signaling data to and from

the following interfaces:

■T1/E1/J1/CMI line interface

■System interface

■VT mapper interface

■Host interface

The following frame types are supported when processing signaling to and from the line interface (no special provi-

sioning is needed for the signaling processor to distinguish between these frame types):

■DS1: ESF; J-ESF; D4; J-D4 (2-, 4-, or 16-state mode)

■CEPT Basic Frame; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms)

■CMI

Frame Format Alignment Procedure

SF Frame alignment is established when six consecutive error-free superframes are

received. Only the FT framing bits are checked (36 bits checked).

D4 and J-D4 Frame alignment is established when six consecutive error-free superframes are

received (72 bits checked in D4, 66 bits checked in J-D4).

DDS Frame alignment is established when six consecutive error-free frames are

received (42 bits checked: FT, FS, and time slot 24).

SLC-96 The FT frame position is established when four consecutive error-free superframes

are received (24 FT bits checked). After establishing the FT frame position, SLC-96

superframe alignment is established on the first valid FS sequence of

000111000111. All the while, the FT frame position must remain error free.

ESF and J-ESF Frame alignment is established when three consecutive error-free superframes

are received (18 bits checked).

CEPT Basic Frame Uses the strategy outlined in G.706 paragraph 4.1.2.

CEPT CRC-4 100 ms Timer Uses the strategy outlined in G.706 paragraphs 4.1.2 and 4.2.

CEPT CRC-4 400 ms Timer Uses the strategy outlined in G.706 paragraph 4.1.2 and ANNEX B.

2.048 Mbits/s CMI Coded

Interface Frame alignment is established on the first detection of the CRV violation. Multi-

frame alignment is achieved the first time the 01111111 multiframe alignment pat-

tern is detected.

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

497Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

The following system bus modes are supported (no special provisioning is needed for the signaling processor to

distinguish between these system bus modes):

■Parallel syste m bus

■CHI bus in ASM mode

The VT mapper interface in the signaling processor supports VT1.5, VT 2 byte sync mapping, as well as VC-11

byte sync mapping using handling groups.

The host can read the signaling data extracted from the line, system, or VT mapper interface at any time. The

transmit signaling processor can be configured so that the host provides the signaling data to be forwarded to the

line, system, or VT mapper interface.

Other signaling features include:

■Debounce on all signaling data extracted from the line interface or the VT mapper interface.

■Host interrupt upon change of signaling state in the receive path.

■Signaling extraction inhibit based on frame alignment and framing bit errors.

■Stomping of DS1 robbed-bit signaling positions.

■Support of zero-code suppression on the line interface in the transmit path.

■Superframe signaling integrity. No signaling data transmitted will be a mix of old and new due to a mid-super-

frame update of signaling information.

21.8.2 Sig nali ng Ref ere nces /St and ar ds

■ITU Rec. G.704 10/98 CEPT Multiframe Signaling Structure

■ITU Rec. G.775 10/98 CEPT TS16 AIS Detection, Remote Alarm Detection

■ITU Rec. G.732 1998 CEPT time slot 16 mfa, Time Slot 16 rfa

■ITU Rec. O.162 10/92 CEPT Ti me Slot 16 rfa Detection

■T1.403 1995 Robbed-Bit Signaling

■TTC JJ-20.11 CMI Coded Interface

■ANSI T1.105 SONET Payload Mapping

■Telcordia GF-25 3- CO RE SO NE T Transpor t System s

■ITU Rec G.707 10/98 Network Node Interface for SDH

■TTC JT G.704 Japanese Synchronous Frame Structures

21.9 Receive Signaling Per-Link Featu re Prov isioning

The receive signaling processor requires the provisioning of four items for each link in order to enable signaling

extraction and delivery:

1. Signaling state mode source (host or Rx CHI interface).

2. Signaling state mode (2-, 4-, and 16-state mode or no-signaling).

3. Signaling source (receive line, VT mapper, or host interface).

4. Signaling destination (transmit system or transmit line interface).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

498 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.9.1 Signaling State Mode Source Selection

The signaling state mode source is selected by programming FRM_R_FGSRC, bit 2; see Table 386, sta rting on

page 274. The typical application will select the host for programming the state mode. If so, the host will have to

program the state mode for all of the time slots on each of the links. The default state mode selected is 16-state

signaling.

It is possible for the state mode to be set by the values received on the CHI bus by the receive system interface. In

this mode, the signaling processor will constantly monitor those values and update the state mode for each of the

time slots on each link.

21.9.2 Sig naling State Mo de Selec tion

The signaling state mode for each time slot is selected by programming bits 5 and 6 of FRM_RSLR0—

FRM_RSLR31, receive signaling link registers 0—31 (R/W) in Table 384 on page 273 for each link. The bit defini-

tion for each of those 32 registers is shown below.

Tab le 589. Rece ive Sign ali ng Lin k Registers 0—31 Bit Description

The signaling state mode definitions are shown in the table below.

Tab le 590. Rece ive Sign ali ng Lin k Registers 0—31 G-Bit and F-Bit Description

The signaling state mode for DS1 type links should be set to match the function of each time slot. The signaling

state mode does not apply to CEPT type links and the value must be kept in the reset state, which is 00. The sig-

naling state mode for CMI type links must be set to 11.

The 16-state mode, which is the state mode selected out of reset, can be used on SF type DS1 links in order to

detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code.

When programming the state mode for each time slot, the host can also program the D, C, B, and A bits in the

same register. Doing this will determine the default code forwarded to the transmit system or the transmit line inter-

face before the first valid signaling code has been extracted from the receive line or VT mapper interface.

Each of the links and time slots is completely independent from one another with respect to the signaling state

mode selection. Any combination is acceptable.

21.9.3 Sig nali ng So urc e Selec tion

The signaling source is selected by programming FRM_R_SIGSRC, bits [1:0]; see Table 386 on page 274. If the

source selected is the receive line interface, the receive signaling processor will start extracting data from the

receive line and store valid signaling codes into the D, C, B, and A locations of FRM_RSLR0—FRM_RSLR31,

receive signaling link registers 0—31 (R/W), Table 384 on page 273 for each of the links.

The receive signaling processor will automatically determine the link type and extract the correct signaling bit posi-

tions from each link. The receive signaling processor can simultaneously service any combination of CEPT, DS1,

and CMI type links. The receive signaling processor will extract robbed-bit signaling from DS1 links, common chan-

nel signaling from CEPT links, and time slot 0 signaling from CMI links compliant with the following standards.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GF—DCBA

G and F Signaling State Mode Selected

00 16 state (reset state)

01 4 state

10 no signaling

11 2 state

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

499Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

■ITU Rec G.704 10/98 CEPT multiframe signaling structure

■T1.403 1995 robbed-bit signaling

■TTC JJ-20.11 CMI coded interface

If the VT mapper is transporting byte sync mapped DS1 links into SONET frames, then the signaling source should

be set to VT mapper interface. In that case, the receive signaling processor will start collecting valid signaling

codes from the VT mapper and store them into the D, C, B, and A locations of FRM_RSLR0—FRM_RSLR31,

receive signaling link registers 0—31 (R/W), (Table 384 on page 273) for each of the links.

If the VT mapper is the source of signaling, data will be extracted based on the standards listed below.

■ANSI T1.105SONET payload mapping

■Bellcore GF-253-CORE SO NET transport syste ms

■ITU Rec G.707 10/98 network node interface for SDH

If the VT mapper is transporting byte sync mapped CEPT links into SONET frames, then the signaling source

should be set to the receive line interface. In that case, the receive signaling processor will extract the entire time

slot 16 multiframe and store that information into FRM_RSLR0—FRM_RSLR31, receive signaling link registers

0—31 (R/W) for each of the links.

If the signaling source is set to be the host, the host may write to FRM_RSLR0—FRM_RSLR31, receive signaling

link registers 0—31 (R/W), and those values will be forwarded to the selected destination. The host mode can also

be used to manually freeze signaling. When the source is switched from receive line to host, for example, the exist-

ing signaling codes will be held until modified by the host or until the signaling source is switched back to the

receive line interface. If the host mode is used to manually freeze signaling, then the signaling debounce feature

must be enabled. To enable signaling debounce set FRM_R_SIGDEB in bits 5 to 1; see Table 386 on page 274.

Each of the links is completely independent from one another with respect to the signaling source selection. Any

combination of receive line, VT mapper, and host is acceptable.

21.9.4 Sig nali ng Destin atio n Sele ctio n

There are three destinations for the signaling extracted from the receive line or VT mapper interface:

1. Transmit system interface.

2. Transmit line interface.

3. FRM_RSLR0—FRM_RSLR31, receive signaling link registers 0—31 (R/W), Table 384 on page 273.

The signaling extracted from the receive line or VT mapper interface will automatically be delivered to the transmit

system interface when the framer Section of the Supermapper is programmed for switch mode. This is done by

setting FRM_SW_TRN in FRM_SFGR1, superframer global register 1 (R/W), Table 313 on page 246, bits 15 to 1.

The system interface will need to be configured for ASM mode in order for the signaling to be transmitted on the

PSB or CHI buses. ASM mode is controlled by bit 11 of the FRM_SYSGR1 register; see Table 359 on page 261.

The signaling extracted from the VT mapper interface can be inserted into the transmit line interface when the

framer Section of the Supermapper is programmed for transport mode. This is done by setting FRM_SW_TRN in

FRM_SFGR1, superframer global register 1 (R/W), Table 313 on page 246, bits 15 to 0, and by setting

FRM_R_SIGI in Table 386 on page 274, bits 8 to 1. The signaling will be inserted based on the programming of

state modes of each time slot.

The receive signaling processor cannot provide data to the transmit system and the transmit line interface on differ-

ent links simultaneously.

Signaling extracted from the VT mapper or receive line interface will always be available in

FRM_RSLR0—FRM_RSLR31, receive signaling link registers 0—31 (R/W), Table 384 on page 273, for each link.

The host can read these registers regardless of whether or not the signaling is forwarded to the transmit system or

transmit line interface. Receive signaling link registers 0—31 DS1/CEPT/CMI data, Table 589 on page 498, shows

the position of the data in those 32 registers for each of the receive line formats.

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

500 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Tab le 591. Rece ive Sign ali ng Lin k Registers 0—31 DS1/CEPT/CMI Data

For CEPT links, the entire time slot 16 multiframe is stored in FRM_RSLR0—FRM_RSLR31, receive signaling link

registers 0—31 (R/W), Table 384 on page 273. The spare bits X[2:0] and the time slot 16 remote frame alarm Y bit

are stored in RSLR0. When time slot 16 multiframe alignment is lost, X[2:0] will automatically be set to 111 and the

Y bit will be set to 0.

The format of the data stored in FRM_RSLR0—FRM_RSLR31, receive signaling link registers 0—31 (R/W),

Table 384 on page 273, also depends on the signaling state mode selected for each time slot as shown in

Table 592 on page 501.

RSLR Address RSLR Bit[6:0] (DS1) RSLR Bit[6:0] (CEPT) RSLR Bit[6:0] (CMI)

0 — 000 X0 Y X1 X2 —

1 GF0 DCBA (Channel 1) 000 DCBA (Channel 1) 110 DCBA (Channel 1)

2 GF0 DCBA (Channel 2) 000 DCBA (Channel 2) 110 DCBA (Channel 2)

3 GF0 DCBA (Channel 3) 000 DCBA (Channel 3) 110 DCBA (Channel 3)

4 GF0 DCBA (Channel 4) 000 DCBA (Channel 4) 110 DCBA (Channel 4)

5 GF0 DCBA (Channel 5) 000 DCBA (Channel 5) 110 DCBA (Channel 5)

6 GF0 DCBA (Channel 6) 000 DCBA (Channel 6) 110 DCBA (Channel 6)

7 GF0 DCBA (Channel 7) 000 DCBA (Channel 7) 110 DCBA (Channel 7)

8 GF0 DCBA (Channel 8) 000 DCBA (Channel 8) 110 DCBA (Channel 8)

9 GF0 DCBA (Channel 9) 000 DCBA (Channel 9) 110 DCBA (Channel 9)

10 GF0 DCBA (Channel 10) 000 DCBA (Channel 10) 110 DCBA (Channel 10)

11 GF0 DCBA (Channel 11) 000 DCBA (Channel 11) 110 DCBA (Channel 11)

12 GF0 DCBA (Channel 12) 000 DCBA (Channel 12) 110 DCBA (Channel 12)

13 GF0 DCBA (Channel 13) 000 DCBA (Channel 13) 110 DCBA (Channel 13)

14 GF0 DCBA (Channel 14) 000 DCBA (Channel 14) 110 DCBA (Channel 14)

15 GF0 DCBA (Channel 15) 000 DCBA (Channel 15) 110 DCBA (Channel 15)

16 GF0 DCBA (Channel 16) — —

17 GF0 DCBA (Channel 17) 000 DCBA (Channel 17) 110 DCBA (Channel 17)

18 GF0 DCBA (Channel 18) 000 DCBA (Channel 18) 110 DCBA (Channel 18)

19 GF0 DCBA (Channel 19) 000 DCBA (Channel 19) 110 DCBA (Channel 19)

20 GF0 DCBA (Channel 20) 000 DCBA (Channel 20) 110 DCBA (Channel 20)

21 GF0 DCBA (Channel 21) 000 DCBA (Channel 21) 110 DCBA (Channel 21)

22 GF0 DCBA (Channel 22) 000 DCBA (Channel 22) 110 DCBA (Channel 22)

23 GF0 DCBA (Channel 23) 000 DCBA (Channel 23) 110 DCBA (Channel 23)

24 GF0 DCBA (Channel 24) 000 DCBA (Channel 24) 110 DCBA (Channel 24)

25 — 000 DCBA (Channel 25) 110 DCBA (Channel 25)

26 — 000 DCBA (Channel 26) 110 DCBA (Channel 26)

27 — 000 DCBA (Channel 27) 110 DCBA (Channel 27)

28 — 000 DCBA (Channel 28) 110 DCBA (Channel 28)

29 — 000 DCBA (Channel 29) 110 DCBA (Channel 29)

30 — 000 DCBA (Channel 30) 110 DCBA (Channel 30)

31 — 000 DCBA (Channel 31) 110 DCBA (Channel 31)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

501Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table 592. Receive Signaling Link Registers 0—31 Expected Data

If the state mode is 4 state or 2 state, then the unused bits will be set to 0.

21.10 Optional Receive Signaling Feat ure s Provision ed for Each Lin k

21.10.1 Suppor t of DS1 Robbed-Bit Stomping

The DS1 robbed-bit positions of voice time slots will be set to 1 in the payload when FRM_R_RXSTOMP in

FRM_RSLR 33, (Table 386 on page 274), bit 7 is set to 1. The robbed-bit positions in the payload will be stomped;

however, the signaling will be transmitted untouched by the system interface.

21.10.2 Support of CEPT Time Slot 16 Stomping

Stomping of time slot 16 for CEPT links is enabled in the system interface block.The Supermapper can also be

configured to transmit AIS on the system bus in time slot 16 when the signaling block loses time slot 16 alignment.

The configuration bits related to these two features are located in the FRM_SYSLR2, Table 431 on page 299.

When using these features, the signaling codes forwarded to the transmit system bus will continue to reflect the

contents of FRM_RSLR0—FRM_RSLR31, Table 384 on page 273.

21.10.3 Support of Signaling Debounce

If programmed to do so, the signaling extracted from the selected source will be debounced. This implies that a

valid signaling code would have to be detected twice before it is updated in FRM_RSLR0—FRM_RSLR31,

Table 384 on page 273. This feature is enabled by setting FRM_R_SIGDEB in FRM_RSLR33, (Table 386 on

page 274), bit 5.

21.10.4 Support of Japanese Handling Groups

If the signaling is transported by the VT mapper within four handling groups compliant to the Japanese standard,

TTC JT G.704, then FRM_R_HGEN in FRM_RSLR33, (Table 386 on page 274), bit 4 must be set to 1. The signal-

ing state mode must be set to either 2 state or no-signaling when using handling groups.

If the signaling transported by the VT mapper uses handling groups, then the status of the handling group alignment

can be transmitted across the system interface. The transmission of this status is enabled by setting

FRM_R_TSAISHG in FRM_SGR1 , (Table 3 71 on page 267) , bits 15 to 1. This mode forces the signaling data for

the channels contained in each handling group to 1 if HG alignment has not been achieved by the receive signaling

processor . For example, if HG2 is unaligned then the A bit for time slots 2, 6, 10, 14, 18, and 22 forwarded to the sys-

tem would be forced to 1.

21.11 Receive Signaling Global Feature Provision i ng

The receive signaling processor requires the provisioning of one global item in order to enable signaling extraction

and delivery.

■Link count (number of active receive links).

Signaling State Mode Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

16 state 0 0 0 D C B A

4 state 01 000BA

2 state 11 000 0A

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

502 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.11.1 Link Count Selection

The link count is specified by programming FRM_R_LINKCNT[4:0] in FRM_SGR1, receive signaling global register

1 (R/W), Table 371 on page 267, bits [14:10]. The reset value is 28, which is appropriate for a 28-link DS1 applica-

tion. A value of 21 is appropriate for a 21-link CEPT application. If the application mixes DS1 and CEPT links or the

TDM clock supplied to the framer section is less than 51.84 MHz, this value should match the terminal count set in

FRM_FGR2, framer global register 2 (R/W), Table 318 on page 249, bits [7:0].

21.12 Other Receive Signaling Glob al Featu res

21.12.1 Support of Automatic Signaling Freeze on Framing Bit Errors

By default, signaling extraction from a particular link will halt when the appropriate alignment has been lost. In order

to guarantee that signaling freeze takes place as soon as possible, FRM_R_AFZFBE in FRM_SGR1, (Table 371

on page 26 7 ), bit 1 must set to 1. When enabled, FRM_R_AFZFBE halts signaling extraction for 32 frames upon

detection of a frame bit error. This configuration bit is applicable to DS1, CEPT, and CMI type frames and for sig-

naling extracted from the receive line or the VT mapper interface. When FRM_R_AFZFBE is enabled, the receive

signaling debounce feature must also be enabled. The FRM_R_SIGDEB feature is enabled in FRM_RSLR33, bit 5

(Table 386 on page 274).

21.12.2 Support of Change of Signaling State FIFO

Signaling can be terminated in the framer section of the Supermapper by polling FRM_RSLR0—FRM_RSLR31, for

each link (Table 384 on page 273). An alternative method is to enable the operation of a signaling change of state

FIFO. In doing so, the host will be interrupted when there have been signaling state changes which need to be pro-

cessed. In order to enable the operation of the signaling change of state FIFO, set FRM_R_SCOSEN in

FRM_SGR2, bit 15 to 1 (Table 372 on page 267 ).

The FIFO is located at signaling receive global register 3. The word read by the host has the following format.

Table 593. Signaling Receive Global Register 3, Bit Definition

The data read by the host indicates the link number (L[4:0]), time-slot number (TS[4:0]), and the signaling informa-

tion for a time slot whose value has changed. The word read by the host will also indicate whether or not the entry

is valid (V = 1) and whether or not there are more entries yet to be read (M = 1). A word with V set to 0 indicates

that the FIFO is empty. The signaling code presented will reflect the associated GF value programmed by the host.

The unused signaling bits will be set to 0. For example, if the time slot is programmed for 4-state signaling, the D

and C bits will be set to 0. The A and B bit will identify the valid signaling code.

This feature can be used in combination with any other feature (i.e., debounce).

When the change of state FIFO is enabled, the host will be interrupted when one of two conditions is satisfied. If

the number of entries in the FIFO exceed the threshold programmed by the host or if there are valid entries to be

processed and the signaling interrupt timer has expired, then the host will be interrupted.

The host sets the FIFO depth threshold by programming FRM_R_SCOSDTH[9:0] in FRM_SGR2, receive signal-

ing global register 2 (R/W), bits [9:0]. The depth of the FIFO is 672, which is sufficient to store an entry for every

time slot processed by the 28-link framer. The timer interval is selected by programming FRM_R_SCOSTTH[15:0]

in FRM_SGR3, bits [15:0] (Table 373 on page 268). The timer increments are 125 µs and the maximum interval

possible is 8 s. The default setting for the depth and timer threshold is 0, which results in the host being interrupted

whenever an entry is made into the FIFO.

If the FIFO overflows, the processor will immediately be interrupted. The current contents of the FIFO will be lost,

however, subsequent entries will be stored normally.

The host can poll the change of state FIFO without the use of interrupts.

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

M V L4 L3 L2 L1 L0 TS4 TS3 TS2 TS1 TS0 D C B A

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

503Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.13 Receive Signaling Interrup ts

There are three interrupts that are maintained in the receive signaling processor, which are located in FRM_SGR7

(Table 377 on page 269). The three interrupts reflect the status of the change of signaling state FIFO. These inter-

rupt bits can be reset based on a clear-on-read protocol, which is provisioned in the Supermapper global registers.

■Threshold overflow interrupt. This bit is set to 1 when the programmed threshold for the FIFO capacity has been

exceeded.

■Interrupt timer interrupt. This bit is set to 1 when the programmed interrupt timer has expired, and there are valid

entries in the FIFO to be processed.

■FIFO overflow interrupt. This bit is set to 1 when the FIFO overflows.

There are mask bits associated with each of the three interrupt status bits, which are located in FRM_SGR7,

receive signaling global register 7 (R/W).

21.13.1 Maintenance of the Change of Signaling State FIFO Status Bits

There is 1 bit that reflects the status of the change of signaling state FIFO. The location of this status bit is in

FRM_SGR5 (Table 375 on page 268).

■FIFO depth threshold overflow status. This bit is set to 1 when the programmed threshold for the FIFO capacity

has been exceeded.

21.13.2 Maintenance of Handling Group-Related Status Bits

There are 3 bits that reflect the status of the handling groups extracted from the VT mapper interface. There are

four handling groups on each link; therefore, there will be three copies of the following bits for each link. The loca-

tion of these status bits are in FRM_RSLR33; see Table 386 on page 274.

■Loss of HG alignment. Alignment uses the 0101010 . . . framing pattern and follows the alignment algorithm

shown in Figu re 61 on page 504.

■AIS detection within each handling group (AIS detection 48 consecutive ones, AIS loss any two zeros).

■RDI detection within each handling group (RDI detection is the presence of three consecutive zeros in the Sp bit

position).

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

504 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

5-9024(F)r.1

Figure 61. HG Alignment Algorithm

21.14 Transmit Signaling Per-Link Feature Provisioning

The transmit signaling processor requires the provisioning of four items for each link to enable signaling extraction

and delivery.

■Signaling state mode source (host or Rx CHI interface)

■Signaling state mode (2-, 4-, and 16-state mode or no-signaling)

■Signaling source (receive line, receive system, or host interface)

■Signaling destination (VT mapper or transmit line interface)

21.14.1 Signaling State Mode Source Selection

The signaling state mode source is selected by programming FRM_T_FGSRC in FRM_TSLR32, transmit signaling

link register 32 (R/W), bit 2; see Table 386 on page 274. The typical application will select the host for program-

ming the state mode. If so, the host will have to program the state mode for all of the time slots on each link.

It is possible for the state mode to be implied by the values received on the CHI or PSB bus by the receive system

interface. In this mode, the signaling processor will constantly monitor those values and update the state mode for

each of the time slots on each link.

RESET

n = 1

(n) = 0 AND

(n + 8) = 1 AND

(n + 16 ) = 0 AND

(n + 24) = 1 NO

YES

LOF FOR HG

n = n + 1

n = n + 32

(n) = 0 AND

(n + 8) = 1 AND

(n + 16 ) = 0 AND

(n + 24) = 1

n = n + 25

YES n = n + 16

YES n = n + 32

MFA FOR HG

—INDICATES S bits FROM VT MAPPER (S1, 2, 3, 4)

n—INDICATES THE SEQUENCE OF EACH S

bit RECEIVED

—INDICATES THE HG (HG1, 2, 3, 4) ASSOCIATED

LOF FOR HG

WITH THE CORRESPONDING S BIT (S1, S2, S3, AND S4)

Data Sheet TMXF28155 Supermapper

June 2002 155/51 Mbits/s SONET/SD H x28/x21 DS1/E1

505Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

21.14.2 Signaling State Mode Selection

The signaling state mode is selected by programming bits 5 and 6 in FRM_TSLR0—FRM_TSLR31 (Table 384 on

page 273) for each link. The bit definition for each of those 32 registers is illustrated below.

Table 594. Transmit Signaling Link Registers 0—31 Bit Description

The signaling state mode definitions are illustrated in the table below.

Table 595. Transmit Signaling Link Registers 0—31 G-Bit and F-Bit Description

The signaling state mode for DS1 type links should be set to match the function of each time slot. The signaling

state mode does not apply to CEPT type links, and the value must be kept in the reset state which is 00. The sig-

naling state mode for CMI type links must be set to 11.

The sixteen state mode, which is the state mode selected out of reset, can be used on SF-type DS1 links in order

to detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code.

When programming the state mode for each time slot, the host can also program the DCBA bits in the same regis-

ter. Doing this will determine the default code forwarded to the transmit line or the transmit VT mapper interface

before the first valid signaling code has been extracted from the receive line or receive system interface.

Each of the links and time slots is completely independent from one another with respect to the signaling state

mode selection. Any combination is acceptable.

21.14.3 Signaling Source Selection

There are three sources for signaling in the transmit path.

■Transmit signaling link registers 0—31 (host programmed)

■Receive sys tem int er fac e

■Receive line inte rf ace

The signaling source is selected by programming FRM_T_SIGSRC[1:0] in FRM_TSLR32 (Table 385 on

page 274), bits [1:0]. If the source of signaling is the host, then the Transmit Signaling Link Registers 0—31 must

be programmed with valid signaling. Table 596 on page 506 shows the organization of signaling data in those reg-

isters for the different types of links.

Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

GF—DCBA

G and F Signaling State Mode Selected

00 16 state (reset state)

01 4 state

10 No signali ng

11 2 state

TMXF28155 Superma pper Data Sheet

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1 June 2002

506 Agere Systems Inc.

21 28-Channel Framer Block Functional Description (continued)

Table 596. Transmit Signaling Link Registers 0—31 DS1/CEPT/CMI Data

For CEPT links, the entire time slot 16 multiframe is sourced from the transmit signaling link registers

(TSLR) 0—31.

The time slot 16 multiframe alignment pattern is transmitted from TSLR 16. That location must be written to 0 if the

correct time slot 16 multiframe alignment pattern is to be transmitted. The reset value of all TSLR locations is 0.

The spare bits (X2, X1, and X0) and the time slot 16 remote frame alarm (Y bit) to be transmitted must be written

by the host into TSLR0. If the source of signaling is the receive system interface and the X or Y bits must be

changed, then switch the signaling source back to host temporarily, write the new values, and then switch the sig-

naling source back to the receive system interface.

If the source of signaling is the host, only the relevant bits need to be written in each transmit signaling link register.

The format of the data written in each transmit signaling link register depends on the signaling state mode selected

for each time slot as shown in Table 597.

TSLR Address TSLR Bit[6:0] (DS1) TSLR Bit[6:0] (CEPT) TSLR Bit[6:0] (CMI)

0 — 000 X2 X1 Y X0 —