SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DOperating Range 2-V to 5.5-V VCC
DDesigned Specifically for High-Speed
Memory Decoders and Data-Transmission
Systems
DIncorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
DLatch-Up Performance Exceeds 250 mA Per
JESD 17
DESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
Y1
Y2
NC
Y3
Y4
C
G2A
NC
G2B
G1
B
A
NC
Y6
Y5
V
Y0
Y7
GND
NC
SN54AHC138 ...FK PACKAGE
(TOP VIEW)
CC
NC − No internal connection
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
B
C
G2A
G2B
G1
Y7
GND
VCC
Y0
Y1
Y2
Y3
Y4
Y5
Y6
SN54AHC138 ...J OR W PACKAGE
SN74AHC138 ...D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN74AHC138 . . . RGY PACKAGE
(TOP VIEW)
116
89
2
3
4
5
6
7
15
14
13
12
11
10
Y0
Y1
Y2
Y3
Y4
Y5
B
C
G2A
G2B
G1
Y7
A
Y6 V
GND
CC
description/ordering information
The ’AHC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing
applications that require very short propagation-delay times. In high-performance memory systems, these
decoders can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are
less than the typical access time of the memory. This means that the effective system delay introduced by the
decoders is negligible.
ORDERING INFORMATION
TAPACKAGEORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY Tape and reel SN74AHC138RGYR HA138
PDIP − N Tube SN74AHC138N SN74AHC138N
SOIC D
Tube SN74AHC138D
AHC138
SOIC − D Tape and reel SN74AHC138DR AHC138
−40°C to 85°CSOP − NS Tape and reel SN74AHC138NSR AHC138
SSOP − DB Tape and reel SN74AHC138DBR HA138
TSSOP PW
Tube SN74AHC138PW
HA138
TSSOP − PW Tape and reel SN74AHC138PWR HA138
TVSOP − DGV Tape and reel SN74AHC138DGVR HA138
CDIP − J Tube SNJ54AHC138J SNJ54AHC138J
−55°C to 125°CCFP − W Tube SNJ54AHC138W SNJ54AHC138W
55 C
to
125 C
LCCC − FK Tube SNJ54AHC138FK SNJ54AHC138FK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
Copyright © 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding.
A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one
inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
ENABLE INPUTS SELECT INPUTS OUTPUTS
G1 G2A G2B C B A Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
X H X X X X H H H H H H H H
XXHXXXHHHHHHHH
LXXXXXHHHHHHHH
HLLLLLLHHHHHHH
HLLLLHHLHHHHHH
HLLLHLHHLHHHHH
HLLLHHHHHLHHHH
HLLHLLHHHHLHHH
HLLHLHHHHHHLHH
HLLHHLHHHHHHLH
H L L H H H H H H H H H H L
logic diagram (positive logic)
G1
G2B
G2A
C
B
A
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
Data
Outputs
Select
Inputs
Enable
Inputs
1
2
3
4
5
6
15
14
13
12
11
10
9
7
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) −20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0 or VO > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±25 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±75 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 2): D package 73°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DB package 82°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): DGV package 120°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): NS package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 2): PW package 108°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 3): RGY package 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-5.
recommended operating conditions (see Note 4)
SN54AHC138 SN74AHC138
UNIT
MIN MAX MIN MAX UNIT
VCC Supply voltage 2 5.5 2 5.5 V
VCC = 2 V 1.5 1.5
VIH High-level input voltage VCC = 3 V 2.1 2.1 V
VIH
High level
input
voltage
VCC = 5.5 V 3.85 3.85
V
VCC = 2 V 0.5 0.5
VIL Low-level input voltage VCC = 3 V 0.9 0.9 V
VIL
Low level
input
voltage
VCC = 5.5 V 1.65 1.65
V
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 2 V −50 −50 mA
IOH High-level output current VCC = 3.3 V ± 0.3 V −4 −4
mA
IOH
High level
output
current
VCC = 5 V ±0.5 V −8 −8 mA
VCC = 2 V 50 50 mA
IOL Low-level output current VCC = 3.3 V ±0.3 V 4 4
mA
IOL
Low level
output
current
VCC = 5 V ±0.5 V 8 8 mA
Δt/Δv
Input transition rise or fall rate
VCC = 3.3 V ± 0.3 V 100 100
ns/V
Δt/ΔvInput transition rise or fall rate VCC = 5 V ±0.5 V 20 20 ns/V
TAOperating free-air temperature −55 125 −40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER TEST CONDITIONS VCC MIN TYP MAX MIN MAX MIN MAX UNIT
2 V 1.9 2 1.9 1.9
IOH = −50 mA3 V 2.9 3 2.9 2.9
V
OH
IOH
50
mA
4.5 V 4.4 4.5 4.4 4.4 V
VOH
IOH = −4 mA 3 V 2.58 2.48 2.48
V
IOH = −8 mA 4.5 V 3.94 3.8 3.8
2 V 0.1 0.1 0.1
IOL = 50 mA3 V 0.1 0.1 0.1
V
OL
IOL
50
mA
4.5 V 0.1 0.1 0.1 V
VOL
IOL = 4 mA 3 V 0.36 0.5 0.44
V
IOL = 8 mA 4.5 V 0.36 0.5 0.44
IIVI = 5.5 V or GND 0 V to 5.5 V ±0.1 ±1* ±1mA
ICC VI = VCC or GND, IO = 0 5.5 V 4 40 40 mA
CiVI = VCC or GND 5 V 2 10 10 pF
* On products compliant to MIL-PRF-38535, this parameter is not production tested at VCC = 0 V.
switching characteristics over recommended operating free-air temperature range,
VCC = 3.3 V ±0.3 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
ABC
Any Y
C15 pF
8.2** 11.4** 1** 13** 1 13
ns
tPHL
A, B, C Any Y CL = 15 pF 8.2** 11.4** 1** 13** 1 13 ns
tPLH
G1
Any Y
C15 pF
8.1** 12.8** 1** 15** 1 15
ns
tPHL
G1 Any Y CL = 15 pF 8.1** 12.8** 1** 15** 1 15 ns
tPLH
G2A G2B
Any Y
C15 pF
8.2** 11.4** 1** 13.5** 1 13.5
ns
tPHL
G2A, G2B Any Y CL = 15 pF 8.2** 11.4** 1** 13.5** 1 13.5 ns
tPLH
ABC
Any Y
C50 pF
10 15.8 1 18 1 18
ns
tPHL
A, B, C Any Y CL = 50 pF 10 15.8 1 18 1 18 ns
tPLH
G1
Any Y
C50 pF
10.6 16.3 1 18.5 1 18.5
ns
tPHL
G1 Any Y CL = 50 pF 10.6 16.3 1 18.5 1 18.5 ns
tPLH
G2A G2B
Any Y
C=50pF
10.7 14.9 1 17 1 17
ns
tPHL
G2A, G2B Any Y CL = 50 pF 10.7 14.9 1 17 1 17 ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V ±0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
FROM TO LOAD TA = 25°C SN54AHC138 SN74AHC138
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE MIN TYP MAX MIN MAX MIN MAX UNIT
tPLH
ABC
Any Y
C15 pF
5.7* 8.1* 1* 9.5* 1 9.5
ns
tPHL
A, B, C Any Y CL = 15 pF 5.7* 8.1* 1* 9.5* 1 9.5 ns
tPLH
G1
Any Y
C15 pF
5.6* 8.1* 1* 9.5* 1 9.5
ns
tPHL
G1 Any Y CL = 15 pF 5.6* 8.1* 1* 9.5* 1 9.5 ns
tPLH
G2A G2B
Any Y
C15 pF
5.8* 8.1* 1* 9.5* 1 9.5
ns
tPHL
G2A, G2B Any Y CL = 15 pF 5.8* 8.1* 1* 9.5* 1 9.5 ns
tPLH
ABC
Any Y
C50 pF
7.2 10.1 1 11.5 1 11.5
ns
tPHL
A, B, C Any Y CL = 50 pF 7.2 10.1 1 11.5 1 11.5 ns
tPLH
G1
Any Y
C50 pF
7.1 10.1 1 11.5 1 11.5
ns
tPHL
G1 Any Y CL = 50 pF 7.1 10.1 1 11.5 1 11.5 ns
tPLH
G2A G2B
Any Y
C=50pF
7.3 10.1 1 11.5 1 11.5
ns
tPHL
G2A, G2B Any Y CL = 50 pF 7.3 10.1 1 11.5 1 11.5 ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, VCC = 5 V, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
Cpd Power dissipation capacitance No load, f = 1 MHz 13 pF
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
50% VCC
VCC
VCC
0 V
0 V
th
tsu
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
tPLH
tPHL
tPHL
tPLH
VOH
VOH
VOL
VOL
VCC
0 V
50% VCC
50% VCC
Input
Out-of-Phase
Output
In-Phase
Output
Timing Input
50% VCC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
Output
Control
Output
Waveform 1
S1 at VCC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOL
VOH
tPZL
tPZH
tPLZ
tPHZ
VCC
0 V
50% VCC VOL + 0.3 V
50% VCC
0 V
VCC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
Open Drain
Open
VCC
GND
VCC
TEST S1
VCC
0 V
50% VCC
tw
VOLTAGE WAVEFORMS
PULSE DURATION
Input
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO = 50 Ω, tr 3 ns, tf 3 ns.
D. The outputs are measured one at a time with one input transition per measurement.
E. All parameters and waveforms are not applicable to all devices.
From Output
Under Test
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE AND OPEN-DRAIN OUTPUTS
S1
VCC
RL = 1 kΩ
GND
From Output
Under Test
CL
(see Note A)
Test
Point
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
Open
50% VCC
50% VCC 50% VCC
50% VCC
50% VCC 50% VCC
50% VCC 50% VCC
VOH 0.3 V
Figure 1. Load Circuit and Voltage Waveforms
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
BIN/OCT
1
1
A0
2
2
A1
4
3
A3
4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHC138
VCC
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHC138
A2
A4
Figure 2. 24-Bit Decoding Scheme
SN54AHC138, SN74AHC138
3-LINE TO 8-LINE DECODERS/DEMULTIPLEXERS
SCLS258L − DECEMBER 1995 − REVISED JULY 2003
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
APPLICATION INFORMATION
VCC
BIN/OCT
1
1
A0
2
2
A1
4
3
A3 4
5
6
0
15
0
&
EN
1
14
1
2
13
2
3
12
3
4
11
4
5
10
5
6
9
6
7
7
7
SN74AHC138
A2
A4
BIN/OCT
1
1
2
2
4
3
4
5
6
8
15
0
&
EN
9
14
1
10
13
2
11
12
3
12
11
4
13
10
5
14
9
6
15
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
16
15
0
&
EN
17
14
1
18
13
2
19
12
3
20
11
4
21
10
5
22
9
6
23
7
7
SN74AHC138
BIN/OCT
1
1
2
2
4
3
4
5
6
24
15
0
&
EN
25
14
1
26
13
2
27
12
3
28
11
4
29
10
5
30
9
6
31
7
7
SN74AHC138
Figure 3. 32-Bit Decoding Scheme
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN74AHC138DBR SSOP DB 16 2000 330.0 16.4 8.2 6.6 2.5 12.0 16.0 Q1
SN74AHC138DGVR TVSOP DGV 16 2000 330.0 12.4 6.8 4.0 1.6 8.0 12.0 Q1
SN74AHC138DR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
SN74AHC138PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
SN74AHC138RGYR VQFN RGY 16 3000 330.0 12.4 3.8 4.3 1.5 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN74AHC138DBR SSOP DB 16 2000 367.0 367.0 38.0
SN74AHC138DGVR TVSOP DGV 16 2000 367.0 367.0 35.0
SN74AHC138DR SOIC D 16 2500 333.2 345.9 28.6
SN74AHC138PWR TSSOP PW 16 2000 367.0 367.0 35.0
SN74AHC138RGYR VQFN RGY 16 3000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 8-Apr-2013
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUAR Y 1996 – REVISED AUGUST 2000
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE
24 PINS SHOWN
14
3,70
3,50 4,90
5,10
20
DIM
PINS **
4073251/E 08/00
1,20 MAX
Seating Plane
0,05
0,15
0,25
0,50
0,75
0,23
0,13
112
24 13
4,30
4,50
0,16 NOM
Gage Plane
A
7,90
7,70
382416
4,90
5,103,70
3,50
A MAX
A MIN
6,60
6,20
11,20
11,40
56
9,60
9,80
48
0,08
M
0,07
0,40
0°8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE
4040065 /E 12/01
28 PINS SHOWN
Gage Plane
8,20
7,40
0,55
0,95
0,25
38
12,90
12,30
28
10,50
24
8,50
Seating Plane
9,907,90
30
10,50
9,90
0,38
5,60
5,00
15
0,22
14
A
28
1
2016
6,50
6,50
14
0,05 MIN
5,905,90
DIM
A MAX
A MIN
PINS **
2,00 MAX
6,90
7,50
0,65 M
0,15
0°ā8°
0,10
0,09
0,25
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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