TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
1
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
DHigh-Performance Floating-Point Digital
Signal Processor (DSP):
-- TMS320C31-80 (5 V)
25-ns Instruction Cycle Time
440 MOPS, 80 MFLOPS, 40 MIPS
-- TMS320C31-60 (5 V)
33-ns Instruction Cycle Time
330 MOPS, 60 MFLOPS, 30 MIPS
-- TMS320C31-50 (5 V)
40-ns Instruction Cycle Time
275 MOPS, 50 MFLOPS, 25 MIPS
-- TMS320C31-40 (5 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
-- TMS320LC31-40 (3.3 V)
50-ns Instruction Cycle Time
220 MOPS, 40 MFLOPS, 20 MIPS
-- TMS320LC31-33 (3.3 V)
60-ns Instruction Cycle Time
183.7 MOPS, 33.3 MFLOPS, 16.7 MIPS
D32-Bit High-Performance CPU
D16-/32-Bit Integer and 32-/40-Bit
Floating-Point Operations
D32-Bit Instruction Word, 24-Bit Addresses
DTwo 1K ×32-Bit Single-Cycle Dual-Access
On-Chip RAM Blocks
DBoot-Program Loader
DOn-Chip Memory-Mapped Peripherals:
-- O n e S e r i a l P o r t
-- T w o 3 2 - B i t T i m e r s
-- One-Channel Direct Memory Access
(DMA) Coprocessor for Concurrent I/O
and CPU Operation
DFabricated Using 0.6 μm Enhanced
Performance Implanted CMOS (EPIC™)
Technology by Texas Instruments (TI™)
D132-Pin Plastic Quad Flat Package
(PQ Suffix)
DEight Extended-Precision Registers
DTwo Address Generators With Eight
Auxiliary Registers and Two Auxiliary
Register Arithmetic Units (ARAUs)
DTwo Low-Power Modes
DTwo- and Three-Operand Instructions
DParallel Arithmetic/Logic Unit (ALU) and
Multiplier Execution in a Single Cycle
DBlock-Repeat Capability
DZero-Overhead Loops With Single-Cycle
Branches
DConditional Calls and Returns
DInterlocked Instructions for
Multiprocessing Support
DBus-Control Registers Configure
Strobe-Control Wait-State Generation
description
The TMS320C31 and TMS320LC31 DSPs are 32-bit, floating-point processors manufactured in 0.6 μm
triple-level-metal CMOS technology. The TMS320C31 and TMS320LC31 are part of the TMS320C3x
generation of DSPs from Texas Instruments.
The TMS320C3x’s internal busing and special digital-signal-processing instruction set have the speed and
flexibility to execute up to 80 million floating-point operations per second (MFLOPS). The TMS320C3x
optimizes speed by implementing functions in hardware that other processors implement through software or
microcode. This hardware-intensive approach provides performance previously unavailable on a single chip.
The TMS320C3x can perform parallel multiply and ALU operations on integer or floating-point data in a single
cycle. Each processor also possesses a general-purpose register file, a program cache, dedicated ARAUs,
internal dual-access memories, one DMA channel supporting concurrent I/O, and a short machine-cycle time.
High performance and ease of use are results of these features.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and TI are trademarks of Texas Instruments Incorporated.
All trademarks are the property of their respective owners.
Copyright ©1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
2POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
description (continued)
General-purpose applications are greatly enhanced by the large address space, multiprocessor interface,
internally and externally generated wait states, one external interface port, two timers, one serial port, and
multiple-interrupt structure. The TMS320C3x supports a wide variety of system applications from host
processor to dedicated coprocessor.
High-level-language support is easily implemented through a register-based architecture, large address space,
powerful addressing modes, flexible instruction set, and well-supported floating-point arithmetic.
TMS320C31 and TMS320LC31 pinout (top view)
The TMS320C31 and TMS320LC31 devices are packaged in 132-pin plastic quad flatpacks (PQ Suffix).
D0
H1
A8
A7
A5
VDD
A4
A3
A2
A1
A0
VSS
D31
VDD
VDD
D30
VSS
VSS
D29
D28
VDD
D27
VSS
D26
D25
D24
D23
D22
D21 VSS
X2/CLKIN
HOLDA
HOLD
VDD
RDY
STRB
R/W
RESET
XF0
VDD
XF1
IACK
INT0
VSS
VSS
VDD
VDD
INT2
INT3
DR0
VSS
FSR0
CLKR0
CLKX0
VSS
FSX0
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
36
50
49
48
47
46
45
44
43
42
41
40
39
38
37
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
DD
V
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
SS
V
SS
V
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 80 81 82 83
DD
V
DD
V
A22
A23
MCBL/MP
EMU2
EMU1
EMU0
EMU3
TCLK1
SHZ
DD
V
D18
D16
D15
D14
D13
D12
D11
D9
D10
D7
D6
D5
D4
D3
DD
V
DD
V
D8
SS
V
H3
79
A9
VSS
A6
VSS
VDD
D20
A10D19
D2
D1
VDD
DX0
INT1
X1
SS
V
A11
DD
V
SS
V
TCLK0
SS
V
SS
V
VSS
VSS
SS
V
D17
SS
V
DD
V
SS
V
SS
V
SS
V
DD
V
DD
V
PQ PACKAGE
(TOP VIEW)
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
3
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
TMS320C31 and TMS320LC31 Terminal Assignments (Alphabetical)†
TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL
NAME NO. NAME NO. NAME NO. NAME NO. NAME NO.
A0 29 D4 76 EMU0 124 VDD 40 VSS 84
A1 28 D5 75 EMU1 125 VDD 49 VSS 85
A2 27 D6 73 EMU2 126 VDD 59 VSS 86
A3 26 D7 72 EMU3 123 VDD 65 VSS 101
A4 25 D8 68 FSR0 110 VDD 66 VSS 102
A5 23 D9 67 FSX0 114 VDD 74 VSS 109
A6 22 D10 64 H1 81 VDD 83 VSS 113
A7 21 D11 63 H3 82 VDD 91 VSS 117
A8 20 D12 62 HOLD 90 VDD 97 VSS 119
A9 18 D13 60 HOLDA 89 VDD 104 VSS 128
A10 16 D14 58 IACK 99 VDD 105 X1 88
A11 14 D15 56 INT0 100 VDD 115 X2/CLKIN 87
A12 13 D16 55 INT1 103 VDD 121 XF0 96
A13 12 D17 54 INT2 106 VDD 131 XF1 98
A14 11 D18 53 INT3 107 VDD 132
A15 10 D19 52 MCBL/MP 127 VSS 3
A16 9D20 50 RDY 92 VSS 4
A17 8D21 48 RESET 95 VSS 17
A18 7D22 47 R/W94 VSS 19
A19 5D23 46 SHZ 118 VSS 30
A20 2D24 45 STRB 93 VSS 35
A21 1D25 44 TCLK0 120 VSS 36
A22 130 D26 43 TCLK1 122 VSS 37
A23 129 D27 41 VSS 42
CLKR0 111 D28 39 VSS 51
CLKX0 112 D29 38 VDD 6 VSS 57
D0 80 D30 34 VDD 15 VSS 61
D1 79 D31 31 VDD 24 VSS 69
D2 78 DR0 108 VDD 32 VSS 70
D3 77 DX0 116 VDD 33 VSS 71
†VDD and VSS pins are on a common plane internal to the device.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
4POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
TMS320C31 and TMS320LC31 Terminal Assignments (Numerical)†
TERMINAL TERMINAL TERMINAL TERMINAL TERMINAL
NO. NAME NO. NAME NO. NAME NO. NAME NO. NAME
1A21 31 D31 61 VSS 91 VDD 121 VDD
2A20 32 VDD 62 D12 92 RDY 122 TCLK1
3 VSS 33 VDD 63 D11 93 STRB 123 EMU3
4 VSS 34 D30 64 D10 94 R/W 124 EMU0
5A19 35 VSS 65 VDD 95 RESET 125 EMU1
6 VDD 36 VSS 66 VDD 96 XF0 126 EMU2
7A18 37 VSS 67 D9 97 VDD 127 MCBL/MP
8A17 38 D29 68 D8 98 XF1 128 VSS
9A16 39 D28 69 VSS 99 IACK 129 A23
10 A15 40 VDD 70 VSS 100 INT0 130 A22
11 A14 41 D27 71 VSS 101 VSS 131 VDD
12 A13 42 VSS 72 D7 102 VSS 132 VDD
13 A12 43 D26 73 D6 103 INT1
14 A11 44 D25 74 VDD 104 VDD
15 VDD 45 D24 75 D5 105 VDD
16 A10 46 D23 76 D4 106 INT2
17 VSS 47 D22 77 D3 107 INT3
18 A9 48 D21 78 D2 108 DR0
19 VSS 49 VDD 79 D1 109 VSS
20 A8 50 D20 80 D0 110 FSR0
21 A7 51 VSS 81 H1 111 CLKR0
22 A6 52 D19 82 H3 112 CLKX0
23 A5 53 D18 83 VDD 113 VSS
24 VDD 54 D17 84 VSS 114 FSX0
25 A4 55 D16 85 VSS 115 VDD
26 A3 56 D15 86 VSS 116 DX0
27 A2 57 VSS 87 X2/CLKIN 117 VSS
28 A1 58 D14 88 X1 118 SHZ
29 A0 59 VDD 89 HOLDA 119 VSS
30 VSS 60 D13 90 HOLD 120 TCLK0
†VDD and VSS pins are on a common plane internal to the device.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
5
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
TMS320C31 and TMS320LC31 Terminal Functions
TERMINAL
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
CONDITIONS
W
H
E
N
NAME QTY T
Y
PE
†
D
E
S
C
R
I
P
T
I
O
N
WHEN
SIGNAL IS Z TYPE‡
PRIMARY-BUS INTERFACE
D31--D0 32 I/O/Z 32-bit data port S H R
A23--A0 24 O/Z 24-bit address port S H R
R/W 1 O/Z Read/write. R/W is high when a read is performed and low when a write is performed
over the parallel interface. S H R
STRB 1O/Z External-access strobe S H
RDY 1 I Ready. RDY indicates that the external device is prepared for a transaction
completion.
HOLD 1 I
Hold. When HOLD is a logic low, any ongoing transaction is completed. A23--A0,
D31--D0, STRB, and R/W are placed in the high-impedance state and all
transactions over the primary-bus interface are held until HOLD becomes a logic high
or until the NOHOLD bit of the primary-bus-control register is set.
HOLDA 1O/Z
Hold acknowledge. HOLDA is generated in response to a logic low on HOLD.HOLDA
indicates that A23--A0, D31--D0, STRB, and R/W are in the high-impedance state
and that all transactions over the bus are held. HOLDA is high in response to a logic
high of HOLD or the NOHOLD bit of the primary-bus-control register is set.
S
CONTROL SIGNALS
RESET 1 I Reset. When RESET is a logic low, the device is in the reset condition. When RESET
becomes a logic high, execution begins from the location specified by the reset vector.
INT3-- INT0 4 I External interrupts
IACK 1O/Z Interrupt acknowledge. IACK is generated by the IACK instruction. IACK can be used
to indicate the beginning or the end of an interrupt-service routine. S
MCBL/MP 1 I Microcomputer boot-loader/microprocessor mode-select
SHZ 1 I
Shutdown high impedance. When active, SHZ shuts down the device and places all
pins in the high-impedance state. SHZ is used for board-level testing to ensure that
no dual-drive conditions occur. CAUTION: A low on SHZ corrupts the device memory
and register contents. Reset the device with SHZ high to restore it to a known
operating condition.
XF1, XF0 2I/O/Z External flags. XF1 and XF0 are used as general-purpose I/Os or to support
interlocked processor instruction. S R
SERIAL PORT 0 SIGNALS
CLKR0 1I/O/Z Serial port 0 receive clock. CLKR0 is the serial shift clock for the serial port 0 receiver. S R
CLKX0 1I/O/Z Serial port 0 transmit clock. CLKX0 is the serial shift clock for the serial port 0
transmitter. S R
DR0 1I/O/Z Data-receive. Serial port 0 receives serial data on DR0. S R
DX0 1I/O/Z Data-transmit output. Serial port 0 transmits serial data on DX0. S R
FSR0 1I/O/Z Frame-synchronization pulse for receive. The FSR0 pulse initiates the data-receive
process using DR0. S R
FSX0 1I/O/Z Frame-synchronization pulse for transmit. The FSX0 pulse initiates the data-transmit
process using DX0. S R
TIMER SIGNALS
TCLK0 1I/O/Z Timer clock 0. As an input, TCLK0 is used by timer 0 to count external pulses. As an
output, TCLK0 outputs pulses generated by timer 0. S R
TCLK1 1I/O/Z Timer clock 1. As an input, TCLK0 is used by timer 1 to count external pulses. As an
output, TCLK1 outputs pulses generated by timer 1. S R
†I = input, O = output, Z = high-impedance state
‡S=SHZactive, H = HOLD active, R = RESET active
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
6POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
TMS320C31 and TMS320LC31 Terminal Functions (Continued)
TERMINAL
T
Y
P
E
†
D
E
S
C
R
I
P
T
I
O
N
CONDITIONS
W
H
E
N
NAME QTY T
Y
PE
†
D
E
S
C
R
I
P
T
I
O
N
WHEN
SIGNAL IS Z TYPE‡
SUPPLY AND OSCILLATOR SIGNALS
H1 1O/Z External H1 clock. H1 has a period equal to twice CLKIN. S
H3 1O/Z External H3 clock. H3 has a period equal to twice CLKIN. S
VDD 20 I5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be
connected to a common supply plane.§
VSS 25 IGround. All grounds must be connected to a common ground plane.
X1 1 O Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left
unconnected.
X2/CLKIN 1 I Internal-oscillator input from a crystal or a clock
RESERVED¶
EMU2--EMU0 3 I Reserved for emulation. Use pullup resistors to VDD
EMU3 1O/Z Reserved for emulation S
†I = input, O = output, Z = high-impedance state
‡S=SHZactive, H = HOLD active, R = RESET active
§Recommended decoupling capacitor value is 0.1 μF.
¶Follow the connections specified for the reserved pins. Use 18-kΩ-- 2 2 - k Ωpullup resistors for best results. All VDD supply pins must be connected
to a common supply plane, and all ground pins must be connected to a common ground plane.
NOTES: 1. A test mode for measuring leakage currents in the TMS320C31 is implemented. This test mode powers down the clock oscillator
circuit resulting in currents below 10 μA. The test mode is entered by asserting SHZ low, which tri--states all output pins and then
holds both H1 and H3 at logic high. The test mode is not intended for application use because it does not preserve the processor
state.
2. Since SHZ is a synchronized input and the clock is disabled, exiting the test mode occurs only when at least one of the H1/H3 pins
is pulled low. Reset cannot be used to wake up in test mode since the SHZ pin is sampled and the clocks are not running.
3. On power up, the processor can be in an indeterminate state. If the state is SHZ mode and H1 and H3 are both held logic high by
pull--ups, then shutdown will occur. Normally, if H1 and H3 do not have pull--ups, the rise time lag due to capacitive loading on a
tri--state pin is enough to ensure a clean start. However, a slowly rising supply and board leakages to VCC may be enough to cause
a bad start. Therefore, a pulldown resistor on either H1 or H3 is recommended for proper wakeup.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
7
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
functional block diagram
24
Boot
Loader
Cache
(64 ×32)
RAM
Block 0
(1K ×32)
RAM
Block 1
(1K ×32)
RDY
HOLD
HOLDA
STRB
R/W
D31--D0
A23--A0
RESET
IR
PC CPU1
REG1
REG2
MUX
40
32
32
32
32
32
32
32
24
24
24
24
BK
ARAU0 ARAU1
DISP0, IR0, IR1
Extended-
Precision
Registers
(R7--R0)
Auxiliary
Registers
(AR0-- AR7)
Other
Registers
(12)
40
40
40
40
Multiplier
32-Bit
Barrel
Shifter
ALU
DMA Controller
Global-Control
Register
Source-Address
Register
Destination-
Address
Register
Serial Port 0
Serial-Port-Control
Register
Receive/Transmit
(R/X) Timer Register
Data-Transmit
Register
Data-Receive
Register
FSX0
DX0
CLKX0
FSR0
DR0
CLKR0
Timer 0
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK0
Timer 1
Global-Control
Register
Timer-Period
Register
Timer-Counter
Register
TCLK1
Port Control
STRB-Control
Register
Transfer-
Counter
Register
PDATA Bus
PADDR Bus
DDATA Bus
DADDR1 Bus
DADDR2 Bus
DMADATA Bus
DMAADDR Bus
24
40
32 32 24 24 32
INT(3--0)
IACK
MCBL/MP
XF(1,0)
VDD(19--0)
VSS(24--0)
X1
X2/CLKIN
H1
H3
EMU(3--0)
32 24 24 24 2432 32 32
CPU2
32 32 40 40
MUX
Controller
Peripheral Data Bus
Peripheral Address Bus
CPU1
REG1
REG2
MUX
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
8POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
memory map
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
Reset, Interrupt, Trap Vector, and
Reserved Locations (64)
(External STRB Active)
0h
03Fh
040h
External
STRB Active
(8M Words -- 64 Words)
7FFFFFh
Reserved
(32K Words)
800000h
807FFFh
808000h
8097FFh
RAM Block 0
(1K Words Internal)
809800h
809BFFh
809C00h
809FFFh
80A000h External
STRB Active
(8M Words -- 40K Words)
FFFFFFh
0h
FFFh
1000h
7FFFFFh
Reserved
(32K Words)
800000h
807FFFh
Peripheral Bus
Memory-Mapped Registers
(6K Words Internal)
808000h
8097FFh
RAM Block 0
(1K Words Internal)
809800h
809BFFh
809C00h
809FFFh
80A000h External
STRB Active
(8M Words --
40K Words)
FFFFFFh
Boot 1
Boot 2
400000h
RAM Block 1
(1K Words -- 63 Words Internal)
809FC0h
809FC1h User-Program Interrupt
and Trap Branches
(63 Words Internal)
Boot 3
FFF000h
External
STRB
Active
(8M Words --
4K Words)
Reserved for Boot-Loader
Operations
(a) Microprocessor Mode (b) Microcomputer/Boot-Loader Mode
RAM Block 1
(1K Words Internal)
Figure 1. TMS320C31 Memory Maps
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
9
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
memory map (continued)
Reset
00h INT0
809FC1h
INT1
01h INT1
809FC2h
INT2
02h INT2
809FC3h
INT3
03h
INT3
809FC4h
XINT0
04h
XINT0
809FC5h
RINT0
06h RINT0
809FC6h
Reserved
07h Reserved
809FC7h
809FC8h
08h
TINT0
09h TINT0809FC9h
TINT1
0Ah TINT1
809FCAh
DINT
0Bh DINT
809FCBh
Reserved
0Ch Reserved
809FDFh
1Fh
809FCCh
TRAP 020h TRAP 0
809FE0h
TRAP 273Bh TRAP 27809FFBh
Reserved
3Ch Reserved
809FFFh
3Fh
809FFCh
(a) Microprocessor Mode (b) Microcomputer/Boot-Loader Mode
INT0
05h
Figure 2. Reset, Interrupt, and Trap Vector/Branches Memory-Map Locations
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
10 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
memory map (continued)
FSX/DX/CLKX Serial Port Control
FSR/DR/CLKR Serial Port Control
Serial R/X Timer Control
Serial R/X Timer Counter
Serial R/X Timer Period Register
Data-Transmit
Data-Receive
Primary-Bus Control
DMA Global Control
DMA Source Address
DMA Destination Address
DMA Transfer Counter
Timer 0 Global Control
Timer 0 Counter
Timer 0 Period Register
Timer 1 Global Control
Timer 1 Counter
Timer 1 Period Register
Serial Global Control
808000h
808004h
808006h
808008h
808020h
808024h
808028h
808030h
808034h
808038h
808040h
808042h
808043h
808044h
808045h
808046h
808048h
80804Ch
808064h
†Shading denotes reserved address locations
Figure 3. Peripheral Bus Memory-Mapped Registers†
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
11
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
absolute maximum ratings over specified temperature range (unless otherwise noted)†
’C31 ’LC31
Supply voltage range, VDD (see Note 1) --0.3 V to 7 V......................... --0.3Vto5V..........
Input voltage range, VI--0.3Vto7V........................................ --0.3Vto5V..........
Output voltage range, VO--0.3Vto7V..................................... --0.3Vto5V..........
Continuous power dissipation (worst case) (see Note 5) 2.6 W..................
(for TMS320C31-80)
850 mW
..............
(for TMS320LC31-33)
Operating case temperature range, TCPQL (commercial) 0°Cto85°C......... 0°Cto85°C...........
PQA (industrial) -- 40°C to 125°C.......
Storage temperature range, Tstg -- 5 5 °C to 150°C............................. -- 5 5 °C to 150°C.......
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 4. All voltage values are with respect to VSS.
5. Actual operating power is less. This value was obtained under specially produced worst-case test conditions for the TMS320C31,
which are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard
pattern to both primary and extension buses at the maximum rate possible. See normal (ICC) current specification in the electrical
characteristics table and also read Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note 6)
’C31 ’LC31
U
N
I
T
MIN NOM MAX MIN NOM MAX UNIT
VDD Supply voltage (DVDD, etc.) 4.75 55.25 3.13 3.3 3.47 V
VSS Supply voltage (CVSS, etc.) 0 0 V
VIH High-level input voltage 2 VDD +0.3
‡1.8 VDD +0.3
‡V
VIL Low-level input voltage -- 0 . 3 ‡0.8 -- 0 . 3 ‡0.6 V
IOH High-level output current -- 300 -- 300 μA
IOL Low-level output current 2 2 mA
TCOperating case temperature (commercial) 085 085 °C
Operating case temperature (industrial) -- 4 0 125 °C
VTH High-level input voltage for CLKIN 2.6 VDD +0.3
‡2.5 VDD +0.3
‡V
‡These values are derived from characterization and not tested.
NOTE 6: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
12 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
(see Note 3)†
P
A
R
A
M
E
T
E
R
T
E
S
T
C
O
N
D
I
T
I
O
N
S
’C31 ’LC31
U
N
I
T
P
A
R
A
METER TEST CONDITIONS MIN TYP‡MAX MIN TYP‡MAX UNIT
VOH High-level output voltage VDD =MIN, I
OH =MAX 2.4 3 2 V
VOL Low-level output voltage VDD =MIN, I
OH =MAX 0.3 0.6 0.4 V
IZHigh-impedance current VDD =MAX -- 2 0 +20 -- 2 0 +20 μA
IIInput current VI=V
SS to VDD -- 1 0 +10 -- 1 0 +10 μA
IIP Input current (with internal
pullup) Inputs with internal pullups§-- 600 20 -- 600 10 μA
f
3
3
M
H
z
’
L
C
3
1
3
3
1
5
0
3
2
5
1
2
0
2
5
0
f
x=33MHz ’LC31-33 150 325 120 250
fx=33MHz ’C31-33
(ext. temp) 150 325
I
C
C
Su
p
p
l
y
current¶# TA=25°C,
V
M
A
X
fx=40MHz ’C31-40 160 390 150 300 m
A
I
C
C
S
u
p
p
l
y
c
u
r
r
e
n
t
V
DD =M
A
Xfx=50MHz ’C31-50 200 425
m
A
fx=60MHz ’C31-60 225 475
fx=80MHz ’C31-80 275 550
IDD Supply current Standby, IDLE2 Clocks shut off 50 20 μA
C
In
p
ut All inputs except CLKIN 15|| 15||
p
F
Ci
I
n
p
u
t
capacitance CLKIN 25 25 pF
CoOutput capacitance 20|| 20|| pF
†All input and output voltage levels are TTL compatible.
‡For ’C31, all typical values are at VDD =5V,T
A(air temperature) = 25°C. For ’LC31, all typical values are at VDD =3.3V,
TA(air temperature) = 25°C.
§Pins with internal pullup devices: INT3-- I N T 0 ,MCBL/MP.
¶Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the
maximum rate possible. See Calculation of TMS320C30 Power Dissipation Application Report (literature number SPRA020).
#fxis the input clock frequency.
|| Specified by design but not tested
NOTE 6: All voltage values are with respect to VSS. All input and output voltage levels are TTL-compatible. CLKIN can be driven by a CMOS
clock.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
13
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLoad
IOL
CT
IOH
Output
Under
Test
Where: IOL = 2 mA (all outputs)
IOH = 300 μA (all outputs)
VLOAD =2.15V
CT= 80-pF typical load-circuit capacitance
Figure 4. TMS320C31 Test Load Circuit
signal transition levels for ’C31 (see Figure 5 and Figure 6)
TTL-level outputs are driven to a minimum logic-high level of 2.4 V and to a maximum logic-low level of 0.6 V.
Output transition times are specified as follows:
DFor a high-to-low transition on a TTL-compatible output signal, the level at which the output is said to be
no longer high is 2 V and the level at which the output is said to be low is 1 V.
DFor a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
0.6 V
1V
2V
2.4 V
Figure 5. TTL-Level Outputs
Transition times for TTL-compatible inputs are specified as follows:
DFor a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
2 V and the level at which the input is said to be low is 0.8 V.
DFor a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.8 V and the level at which the input is said to be high is 2 V.
2V
0.8 V
Figure 6. TTL-Level Inputs
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
14 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
VLoad
IOL
CT
IOH
Output
Under
Test
Where: IOL = 2 mA (all outputs)
IOH = 300 μA (all outputs)
VLOAD =2.15V
CT= 80-pF typical load-circuit capacitance
Figure 7. TMS320LC31 Test Load Circuit
signal transition levels for ’LC31 (see Figure 8 and Figure 9)
Outputs are driven to a minimum logic-high level of 2 V and to a maximum logic-low level of 0.4 V. Output
transition times are specified as follows:
DFor a high-to-low transition on an output signal, the level at which the output is said to be no longer high
is 2 V and the level at which the output is said to be low is 1 V.
DFor a low-to-high transition, the level at which the output is said to be no longer low is 1 V and the level at
which the output is said to be high is 2 V.
0.4 V
0.6 V
2V
1.8 V
Figure 8. ’LC31 Output Levels
Transition times for inputs are specified as follows:
DFor a high-to-low transition on an input signal, the level at which the input is said to be no longer high is
1.8 V and the level at which the input is said to be low is 0.6 V.
DFor a low-to-high transition on an input signal, the level at which the input is said to be no longer low is
0.6 V and the level at which the input is said to be high is 1.8 V.
1.8 V
0.6 V
Figure 9. ’LC31 Input Levels
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
15
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
PARAMETER MEASUREMENT INFORMATION
timing parameter symbology
Timing parameter symbols used herein were created in accordance with JEDEC Standard 100-A. In order to
shorten the symbols, some of the pin names and other related terminology have been abbreviated as follows,
unless otherwise noted:
A A23--A0 H H1 and H3
ASYNCH Asynchronous reset signals HOLD HOLD
C CLKX0 HOLDA HOLDA
CI CLKIN IACK IACK
CLKR CLKR0 INT INT3-- INT0
CONTROL Control signals RDY RDY
DD31--D0 RWR/
W
DR DR RESET RESET
DX DX S STRB
FS FSX/R SCK CLKX/R
FSX FSX0 SHZ SHZ
FSR FSR0 TCLK TCLK0, TCLK1, or TCLKx
GPI General-purpose input XF XF0, XF1, or XFx
GPIO General-purpose input/output; peripheral pin XFIO XFx switching from input to output
GPO General-purpose output
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
16 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
timing
Timing specifications apply to the TMS320C31 and TMS320LC31.
X2/CLKIN, H1, and H3 timing
The following table defines the timing parameters for the X2/CLKIN, H1, and H3 interface signals. The numbers
shown in Figure 10 and Figure 11 correspond with those in the NO. column of the table below.
timing parameters for X2/CLKIN, H1, H3 (see Figure 10 and Figure 11)
NO. ’LC31 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
1 tf(CI) Fall time, CLKIN 5†5†5†4†4†ns
2 tw(CIL) Pulse duration, CLKIN
low tc(CI) =min 10 9 7 6 5 ns
3 tw(CIH) Pulse duration, CLKIN
high tc(CI) =min 10 9 7 6 5 ns
4 tr(CI) Rise time, CLKIN 5†5†5†4†4†ns
5 tc(CI) Cycle time, CLKIN 30 303 25 303 20 303 16.67 303 12.5 303 ns
6 tf(H) Fall time, H1 and H3 33333ns
7 tw(HL) Pulse duration, H1
and H3 low P--6‡P--5‡P--5‡P--4‡P--3‡ns
8 tw(HH) Pulse duration, H1
and H3 high P--7‡P--6‡P--6‡P--5‡P--4‡ns
9 tr(H) Rise time, H1 and H3 43333ns
10 td(HL-HH)
Delay time. from H1
lowtoH3highorfrom
H3lowtoH1high
0504040403ns
11 tc(H) Cycle time, H1 and H3 60 606 50 606 40 606 33.3 606 25 606 ns
†Specified by design but not tested
‡P=t
c(CI)
1
4
X2/CLKIN
3
5
2
Figure 10. Timing for X2/CLKIN
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
17
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
X2/CLKIN, H1, and H3 timing (continued)
H3
H1
6
9
10
10
6
9
11
78
7
8
11
Figure 11. Timing for H1 and H3
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
18 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
•
memory read/write timing
The following table defines memory read/write timing parameters for STRB. The numbers shown in Figure 12 and Figure 13 correspond with
those in the NO. column of the table below.
timing parameters for memory (STRB = 0) read/write (see Figure 12 and Figure 13)†
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
12 td(H1L-SL) Delay time, H1 low to STRB low 0‡10 0‡6 0‡5 0‡5 0‡5ns
13 td(H1L-SH) Delay time, H1 low to STRB high 0‡10 0‡6 0‡5 0‡5 0‡5ns
14 td(H1H-RWL)R Delay time, H1 high to R/W low (read) 0‡10 0‡9 0‡7 0‡6 0‡4ns
15 td(H1L-A) Delay time, H1 low to A valid 0‡14 0‡11 0‡9 0‡8 0‡7ns
16 tsu(D-H1L)R Setup time, D before H1 low (read) 16 14 10 9 8 ns
17 th(H1L-D)R Hold time, D after H1 low (read) 0 0 0 0 0 ns
18 tsu(RDY-H1H) Setup time, RDY before H1 high 8 8 6 5 4 ns
19 th(H1H-RDY) Hold time, RDY after H1 high 0 0 0 0 0 ns
20 td(H1H-RWH)W Delay time, H1 high to R/W high (write) 10 9 7 6 4 ns
21 tv(H1L-D)W Valid time, D after H1 low (write) 20 17 14 12 8ns
22 th(H1H-D)W Hold time, D after H1 high (write) 0 0 0 0 0 ns
23 td(H1H-A)W Delay time, H1 high to A valid on back-to-back write
cycles (write) 18 15 12 10 8ns
24 td(A-RDY) Delay time, RDY from A valid 8‡7‡6‡6‡P-8
§ns
24A Taa Address valid to data valid (read) 30 25 21 16 10 ns
†See Figure 14 for address bus timing variation with load capacitance greater than typical load-circuit capacitance (CT=80pF).
‡This value is characterized but not tested
§In earlier data sheets, this parameter was shown as an “at speed” value. It is in fact a synchronized signal and therefore relative to Tc(H) where P = tc(C1) =t
c(H)/2.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
19
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
memory read/write timing (continued)
12
14
15
13
16
17
19
18
H3
H1
R/W
A
D
RDY
STRB
24
NOTE A: STRB remains low during back-to-back read operations.
Figure 12. Timing for Memory (STRB = 0) Read
14
12
RDY
D
A
R/W
STRB
H1
H3
20
22
23
18 19
21
15
13
Figure 13. Timing for Memory (STRB =0)Write
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
20 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
memory read/write timing (continued)
4.00
3.50
3.00
2.50
2.00
1.50
1.00
0.50
10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 100
Change in Load Capacitance, pF
Change in Address-Bus Timing, ns
Address-Bus Timing Variation Load Capacitance
NOTE A: 30 pF/ns slope
Figure 14. Address-Bus Timing Variation With Load Capacitance (see Note A)
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
21
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII. The
numbers shown in Figure 15 correspond with those in the NO. column of the tables below.
timing parameters for XF0 and XF1 when executing LDFI or LDII for TMS320C31 (see Figure 15)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
25 td(H3H-XF0L) Delay time, H3 high to XF0 low 15 13 12 11 8ns
26 tsu(XF1-H1L) Setup time, XF1 before H1 low 10 9 9 8 6 ns
27 th(H1L-XF1) Hold time, XF1 after H1 low 00000ns
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
XF1 Pin
Fetch
LDFI or LDII Decode Read Execute
25
26
27
Figure 15. Timing for XF0 and XF1 When Executing LDFI or LDII
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
22 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
XF0 timing when executing STFI and STII†
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII. The number
shown in Figure 16 corresponds with the number in the NO. column of the table below.
timing parameters for XF0 when executing STFI or STII (see Figure 16)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
28 td(H3H-XF0H) Delay time, H3 high to XF0
high 15 13 12 11 8ns
†XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
H3
H1
STRB
R/W
A
D
RDY
XF0 Pin
Fetch
STFI or STII Read Execute
28
Decode
Figure 16. Timing for XF0 When Executing an STFI or STII
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
23
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
XF0 and XF1 timing when executing SIGI
The following tables define the timing parameters for the XF0 and XF1 pins during execution of SIGI. The
numbers shown in Figure 17 correspond with those in the NO. column of the tables below.
timing parameters for XF0 and XF1 when executing SIGI for TMS320C31 (see Figure 17)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
29 td(H3H-XF0L) Delay time, H3 high to XF0
low 15 13 12 11 8ns
30 td(H3H-XF0H) Delay time, H3 high to XF0
high 15 13 12 11 8ns
31 tsu(XF1-H1L) Setup time, XF1 before H1
low 10 9 9 8 6 ns
32 th(H1L-XF1) Hold time, XF1 after H1 low 0 0 0 0 0 ns
H3
H1
Fetch
SIGI Decode Read Execute
XF0
XF1
31
32
29 30
Figure 17. Timing for XF0 and XF1 When Executing SIGI
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
24 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
loading when XF is configured as an output
The following table defines the timing parameter for loading the XF register when the XFx pin is configured as
an output. The number shown in Figure 18 corresponds with the number in the NO. column of the table below.
timing parameters for loading the XF register when configured as an output pin (see Figure 18)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
33 tv(H3H-XF) Validtime,H3hightoXFx 15 13 12 11 8ns
Fetch Load
Decode Read Execute
H3
H1
OUTXFx Bit
(see Note A)
XFx Pin
1or0
33
Instruction
NOTE A: OUTXFx represents either bit 2 or 6 of the IOF register.
Figure 18. Timing for Loading XF Register When Configured as an Output Pin
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
25
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
changing XFx from an output to an input
The following table defines the timing parameters for changing the XFx pin from an output pin to an input pin.
The numbers shown in Figure 19 correspond with those in the NO. column of the table below.
timing parameters of XFx changing from output to input mode for TMS320C31 (see Figure 19)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
34 th(H3H-XF) Hold time, XFx after
H3 high 15†13†12†11†9†ns
35 tsu(XF-H1L) Setup time, XFx
before H1 low 10 9 9 8 6 ns
36 th(H1L-XF) Hold time, XFx after
H1 low 00000ns
†This value is characterized but not tested.
Execute
Load of IOF
Buffers Go
From Output
to Output
Synchronizer
Delay
Value on Pin
Seen in IOF
H3
H1
XFx Pin
INXFx Bit
(see Note A)
I/OxFx Bit
(see Note A)
34
35
36
Data
Sampled
Data
Seen
Output
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register, and INXFx represents either bit 3 or bit 7 of the IOF register.
Figure 19. Timing for Change of XFx From Output to Input Mode
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
26 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
changing XFx from an input to an output
The following table defines the timing parameter for changing the XFx pin from an input pin to an output pin.
The number shown in Figure 20 corresponds with the number in the NO. column of the table below.
timing parameters of XFx changing from input to output mode (see Figure 20)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
37 td(H3H-XFIO) Delay time, H3 high to XFx
switching from input to output 20 17 17 16 9ns
Execution of
Load of IOF
37
H3
H1
I/OxFx
Bit
(see Note A)
XFx Pin
NOTE A: I/OxFx represents either bit 1 or bit 5 of the IOF register.
Figure 20. Timing for Change of XFx From Input to Output Mode
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 21 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 21
correspond with those in the NO. column of the following table.
Resetting the device initializes the bus control register to seven software wait states and therefore results in slow
external accesses until these registers are initialized.
HOLD is an asynchronous input and can be asserted during reset.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 - REVISED JANUARY 1999
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
•27
timing parameters for RESET for the TMS320C31 and TMS320LC31 (see Figure 21)
NO. ’LC31-33 ’C31-40
’LC31-40 ’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
38 tsu(RESET-CIL) Setup time, RESET before
CLKIN low 10 P†‡ 10 P†‡ 10 P†‡ 10 P†‡ 7 P†‡ 4 P†‡ ns
39 td(CLKINH-H1H) Delay time, CLKIN high to H1
high§212 212¶214 210 210 2 8 ns
40 td(CLKINH-H1L) Delay time, CLKIN high to H1
low§212 212¶214 210 210 2 8 ns
41 tsu(RESETH-H1L)
Setup time, RESET high before
H1 low and after ten H1 clock
cycles
10 99765ns
42 td(CLKINH-H3L) Delay time, CLKIN high to H3
low§212¶212 214 210 210 2 8 ns
43 td(CLKINH-H3H) Delay time, CLKIN high to H3
high§212¶212 214 210 210 2 8 ns
44 tdis(H1H-DZ) Disable time, H1 high to D (high
impedance) 15#13#13#12#11#9#ns
45 tdis(H3H-AZ) Disable time, H3 high to A (high
impedance) 10#9#9#8#7#6#ns
46 td(H3H-CONTROLH) Delay time, H3 high to control
signals high 10#9#9#8#7#6#ns
47 td(H1H-RWH) Delay time, H1 high to R/W high 10#9#9#8#7#6#ns
48 td(H1H-IACKH) Delay time, H1 high to IACK
high 10#9#9#8#7#6#ns
49 tdis(RESETL-ASYNCH)
Disable time, RESET low to
asynchronous reset signals
disabled (high impedance)
25#21#21#17#14#12#ns
†P=t
c(CI)
‡Specified by design but not tested
§See Figure 22 for temperature dependence .
¶14 ns for the extended temperature ’C31-40
#This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
28 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
timing parameters for RESET for the TMS320C31 and TMS320LC31 (continued)
CLKIN
H1
H3
38
39
42
45
46
49
48
41
40
43
RESET
(see Notes A and B)
IACK
Ten H1 Clock Cycles
D
(see Note C)
A
(see Note C)
Control Signals
(see Note D)
Asynchronous
Reset Signals
(see Note A)
44
47
TMS320C31 R/W
(see Note E)
NOTES: A. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
B. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
C. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
D. Control signals include STRB.
E. The R/W outputs are placed in a high-impedance state during reset and can be provided with a resistive pullup, nominally
18--22 kΩ, if undesirable spurious writes are caused when these outputs go low.
Figure 21. Timing for RESET
510 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 95 1000
0
2
4
6
8
10
12
14
16
18
20
22
Case Temperature (°C)
CLKIN to H1 and H3 (ns)
TMS320C31-40 (Extended Temperature)
TMS320C31-40
4.75 V ≤VDD ≤5.25 V
105 110 115 120 125
Extended
Temperature
Range
Figure 22. CLKIN to H1 and H3 as a Function of Temperature
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
29
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
interrupt response timing
The following table defines the timing parameters for the INT signals. The numbers shown in Figure 23
correspond with those in the NO. column of the table below.
timing parameters for INT3-- I N T 0 response (see Figure 23)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
50 tsu(INT-H1L) Setup time, INT3--
INT0 before H1 low 15 13 10 8 5 ns
51 tw(INT)
Pulse duration,
interrupt to ensure
only one interrupt
P2P†‡ P2P†‡ P2P†‡ P2P†‡ P2P†‡ ns
†This value is characterized but not tested.
‡P=t
c(H)
The interrupt (INT) pins are asynchronous inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts are level-sensitive, not edge-sensitive. Interrupts are detected on the falling edge of H1.
Therefore, interrupts must be set up and held to the falling edge of H1 for proper detection. The CPU and DMA
respond to detected interrupts on instruction-fetch boundaries only.
For the processor to recognize only one interrupt on a given input, an interrupt pulse must be set up and held
to:
DA minimum of one H1 falling edge
DNo more than two H1 falling edges
The TMS320C3x can accept an interrupt from the same source every two H1 clock cycles.
If the specified timings are met, the exact sequence shown in Figure 23 occurs; otherwise, an additional delay
of one clock cycle is possible.
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
30 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
timing parameters for INT3-- I N T 0 response (continued)
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
INT3 -- I N T 0
Pin
INT3 --INT0
Flag
ADDR
Data
Vector Address First Instruction Address
50
51
Figure 23. Timing for INT3-- I N T 0 Response
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
31
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 24
correspond with those in the NO. column of the table below.
timing parameters for IACK (see Note 7 and Figure 24)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
52 td(H1H-IACKL) Delay time, H1 high to IACK
low 10 9 7 6 5 ns
53 td(H1H-IACKH) Delay time, H1 high to IACK
high 10 9 7 6 5 ns
NOTE 7: IACK goes active on the first half-cycle (H1 rising) of the decode phase of the IACK instruction and goes inactive at the first half-cycle
(H1 rising) of the read phase of the IACK instruction. Because of pipeline conflicts, IACK remains low for one cycle even if the decode
phase of the IACK instruction is extended.
H3
H1
IACK
ADDR
Data
52
53
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
Figure 24. Timing for IACK
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
32 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
serial-port timing parameters for TMS320C31-33 and TMS320LC31-33 (see Figure 25 and Figure 26)
N
O
’LC31-33
U
N
I
T
NO. MIN MAX UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 15 ns
5
5
t
C
y
c
l
e
t
i
m
e
C
L
K
X
/
R
CLKX/R ext tc(H)x2.6
n
s
55 tc(SCK) Cycle time, CLKX
/
RCLKX/R int tc(H)x2 tc(H)x232 ns
5
6
t
P
u
l
s
e
d
u
r
a
t
i
o
n
C
L
K
X
/
R
h
i
g
h
/
l
o
w
CLKX/R ext tc(H)+12
n
s
56 tw(SCK) Pulse duration, CLKX
/
Rhigh
/
low CLKX/R int [tc(SCK)/2]--15 [tc(SCK)/2]+5 ns
57 tr(SCK) Rise time, CLKX/R 8ns
58 tf(SCK) Fall time, CLKX/R 8ns
5
9
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
D
X
a
l
i
d
CLKX ext 35
n
s
59 td(C-DX) Delay time, CLKX to DX valid CLKX int 20 ns
6
0
t
S
e
t
p
t
i
m
e
D
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 10
n
s
60 tsu(DR-CLKRL) Setup time, DR be
f
ore CLKR low CLKR int 25 ns
6
1
t
H
o
l
d
t
i
m
e
D
R
f
r
o
m
C
L
K
R
l
o
CLKR ext 10
n
s
61 th(CLKRL-DR) Hold time, DR
f
rom CLKR low CLKR int 0ns
6
2
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
i
n
t
e
r
n
a
l
F
S
X
h
i
g
h
/
l
o
CLKX ext 32
n
s
62 td(C-FSX) Delay time, CLKX to internal FS
X
high
/
low CLKX int 17 ns
6
3
t
S
e
t
p
t
i
m
e
F
S
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 10
n
s
63 tsu(FSR-CLKRL) Setup time, FSR be
f
ore CLKR low CLKR int 10 ns
6
4
t
H
o
l
d
t
i
m
e
F
S
X
/
R
i
n
p
t
f
r
o
m
C
L
K
X
/
R
l
o
CLKX/R ext 10
n
s
64 th(SCKL-FS) Hold time, FSX
/
R input
f
rom CLK
X
/
Rlow CLKX/R int 0ns
6
5
t
S
e
t
p
t
i
m
e
e
t
e
r
n
a
l
F
S
X
b
e
f
o
r
e
C
L
K
X
CLKX ext -- [ t c(H)-- 8 ] †[tc(SCK)/2]--10†
n
s
65 tsu(FSX-C) Setup time, external FSX be
f
ore CLK
X
CLKX int [tc(H)--21]†tc(SCK)/2†ns
6
6
t
Dela
y
time, CLKX to
f
irst DX bit, FS
X
CLKX ext 36†
n
s
66 td(CH-DX)V
D
e
l
a
y
t
i
m
e
,
C
L
K
X
t
o
f
i
r
s
t
D
X
b
i
t
,
F
S
X
precedes CLKX high CLKX int 21†ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 36†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 20†ns
†This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
33
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
serial-port timing parameters for TMS320C31-40 and TMS320LC31-40 (see Figure 25 and Figure 26)
NO.
’C31-40
’LC31-40 UNIT
N
O
.
MIN MAX
U
N
I
T
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 13 ns
5
5
t
C
y
c
l
e
t
i
m
e
C
L
K
X
/
R
CLKX/R ext tc(H)x2.6
n
s
55 tc(SCK) Cycle time, CLKX
/
RCLKX/R int tc(H)x2 tc(H)x232 ns
5
6
t
P
u
l
s
e
d
u
r
a
t
i
o
n
C
L
K
X
/
R
h
i
g
h
/
l
o
w
CLKX/R ext tc(H)+10
n
s
56 tw(SCK) Pulse duration, CLKX
/
Rhigh
/
low CLKX/R int [tc(SCK)/2]--5 [tc(SCK)/2]+5 ns
57 tr(SCK) Rise time, CLKX/R 7ns
58 tf(SCK) Fall time, CLKX/R 7ns
5
9
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
D
X
a
l
i
d
CLKX ext 30
n
s
59 td(C-DX) Delay time, CLKX to D
X
valid CLKX int 17 ns
6
0
t
S
e
t
p
t
i
m
e
D
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 9
n
s
60 tsu(DR-CLKRL) Setup time, DR be
f
ore CLKR low CLKR int 21 ns
6
1
t
H
o
l
d
t
i
m
e
D
R
f
r
o
m
C
L
K
R
l
o
CLKR ext 9
n
s
61 th(CLKRL-DR) Hold time, DR
f
rom CLKR low CLKR int 0ns
6
2
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
i
n
t
e
r
n
a
l
F
S
X
h
i
g
h
/
l
o
CLKX ext 27
n
s
62 td(C-FSX) Delay time, CLKX to internal FS
X
high
/
low CLKX int 15 ns
6
3
t
S
e
t
p
t
i
m
e
F
S
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 9
n
s
63 tsu(FSR-CLKRL) Setup time, FSR be
f
ore CLKR low CLKR int 9ns
6
4
t
H
o
l
d
t
i
m
e
F
S
X
/
R
i
n
p
t
f
r
o
m
C
L
K
X
/
R
l
o
CLKX/R ext 9
n
s
64 th(SCKL-FS) Hold time, FSX
/
R input
f
rom CLK
X
/
Rlow CLKX/R int 0ns
6
5
t
S
e
t
p
t
i
m
e
e
t
e
r
n
a
l
F
S
X
b
e
f
o
r
e
C
L
K
X
CLKX ext -- [ t c(H)-- 8 ] †[tc(SCK)/2]--10†
n
s
65 tsu(FSX-C) Setup time, external FS
X
be
f
ore CLK
X
CLKX int [tc(H)--21]†tc(SCK)/2†ns
6
6
t
Dela
y
time, CLKX to
f
irst D
X
bit, FS
X
CLKX ext 30†
n
s
66 td(CH-DX)V
D
e
l
a
y
t
i
m
e
,
C
L
K
X
t
o
f
i
r
s
t
D
X
b
i
t
,
F
S
X
precedes CLKX high CLKX int 18†ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 30†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 17† ns
†This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
34 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
serial-port timing parameters for TMS320C31-50 (see Figure 25 and Figure 26)
N
O
’C31-50
U
N
I
T
NO. MIN MAX UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 10 ns
5
5
t
C
y
c
l
e
t
i
m
e
C
L
K
X
/
R
CLKX/R ext tc(H)x2.6
n
s
55 tc(SCK) Cycle time, CLKX
/
RCLKX/R int tc(H)x2 tc(H)x232 ns
5
6
t
P
u
l
s
e
d
u
r
a
t
i
o
n
C
L
K
X
/
R
h
i
g
h
/
l
o
w
CLKX/R ext tc(H)+10
n
s
56 tw(SCK) Pulse duration, CLKX
/
Rhigh
/
low CLKX/R int [tc(SCK)/2]--5 [tc(SCK)/2]+5 ns
57 tr(SCK) Rise time, CLKX/R 6ns
58 tf(SCK) Fall time, CLKX/R 6ns
5
9
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
D
X
a
l
i
d
CLKX ext 24
n
s
59 td(C-DX) Delay time, CLKX to DX valid CLKX int 16 ns
6
0
t
S
e
t
p
t
i
m
e
D
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 9
n
s
60 tsu(DR-CLKRL) Setup time, DR be
f
ore CLKR low CLKR int 17 ns
6
1
t
H
o
l
d
t
i
m
e
D
R
f
r
o
m
C
L
K
R
l
o
CLKR ext 7
n
s
61 th(CLKRL-DR) Hold time, DR
f
rom CLKR low CLKR int 0ns
6
2
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
i
n
t
e
r
n
a
l
F
S
X
h
i
g
h
/
l
o
CLKX ext 22
n
s
62 td(C-FSX) Delay time, CLKX to internal FS
X
high
/
low CLKX int 15 ns
6
3
t
S
e
t
p
t
i
m
e
F
S
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 7
n
s
63 tsu(FSR-CLKRL) Setup time, FSR be
f
ore CLKR low CLKR int 7ns
6
4
t
H
o
l
d
t
i
m
e
F
S
X
/
R
i
n
p
t
f
r
o
m
C
L
K
X
/
R
l
o
CLKX/R ext 7
n
s
64 th(SCKL-FS) Hold time, FSX
/
R input
f
rom CLK
X
/
Rlow CLKX/R int 0ns
6
5
t
S
e
t
p
t
i
m
e
e
t
e
r
n
a
l
F
S
X
b
e
f
o
r
e
C
L
K
X
CLKX ext -- [ t c(H)-- 8 ] †[tc(SCK)/2]--10†
n
s
65 tsu(FSX-C) Setup time, external FSX be
f
ore CLK
X
CLKX int -- [ t c(H)--21]†tc(SCK)/2†ns
6
6
t
Dela
y
time, CLKX to
f
irst DX bit, FS
X
CLKX ext 24†
n
s
66 td(CH-DX)V
D
e
l
a
y
t
i
m
e
,
C
L
K
X
t
o
f
i
r
s
t
D
X
b
i
t
,
F
S
X
precedes CLKX high CLKX int 14†ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 24†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last
data bit 14†ns
†This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
35
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
serial-port timing parameters for TMS320C31-60 (see Figure 25 and Figure 26)
N
O
’C31-60
U
N
I
T
NO. MIN MAX UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 8ns
5
5
t
C
y
c
l
e
t
i
m
e
C
L
K
X
/
R
CLKX/R ext tc(H)x2.6
n
s
55 tc(SCK) Cycle time, CLKX
/
RCLKX/R int tc(H)x2 tc(H)x232 ns
5
6
t
P
u
l
s
e
d
u
r
a
t
i
o
n
C
L
K
X
/
R
h
i
g
h
/
l
o
w
CLKX/R ext tc(H)+10
n
s
56 tw(SCK) Pulse duration, CLKX
/
Rhigh
/
low CLKX/R int [tc(SCK)/2]--5 [tc(SCK)/2]+5 ns
57 tr(SCK) Rise time, CLKX/R 5ns
58 tf(SCK) Fall time, CLKX/R 5ns
5
9
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
D
X
a
l
i
d
CLKX ext 20
n
s
59 td(C-DX) Delay time, CLKX to D
X
valid CLKX int 15 ns
6
0
t
S
e
t
p
t
i
m
e
D
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 8
n
s
60 tsu(DR-CLKRL) Setup time, DR be
f
ore CLKR low CLKR int 15 ns
6
1
t
H
o
l
d
t
i
m
e
D
R
f
r
o
m
C
L
K
R
l
o
CLKR ext 6
n
s
61 th(CLKRL-DR) Hold time, DR
f
rom CLKR low CLKR int 0ns
6
2
t
D
e
l
a
y
t
i
m
e
C
L
K
X
t
o
i
n
t
e
r
n
a
l
F
S
X
h
i
g
h
/
l
o
w
CLKX ext 20
n
s
62 td(C-FSX) Delay time, CLKX to internal FS
X
high
/
low CLKX int 14 ns
6
3
t
S
e
t
p
t
i
m
e
F
S
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 6
n
s
63 tsu(FSR-CLKRL) Setup time, FSR be
f
ore CLKR low CLKR int 6ns
6
4
t
H
o
l
d
t
i
m
e
F
S
X
/
R
i
n
p
t
f
r
o
m
C
L
K
X
/
R
l
o
CLKX/R ext 6
n
s
64 th(SCKL-FS) Hold time, FSX
/
R input
f
rom CLK
X
/
Rlow CLKX/R int 0ns
6
5
t
S
e
t
p
t
i
m
e
e
t
e
r
n
a
l
F
S
X
b
e
f
o
r
e
C
L
K
X
CLKX ext -- [ t c(H)-- 8 ] †[tc(SCK)/2]--10†
n
s
65 tsu(FSX-C) Setup time, external FS
X
be
f
ore CLK
X
CLKX int -- [ t c(H)--21]†tc(SCK)/2†ns
6
6
t
Dela
y
time
,
CLKX to
f
irst D
X
bit
,
FS
X
CLKX ext 20†
n
s
66 td(CH-DX)V
D
e
l
a
y
t
i
m
e
,
C
L
K
X
t
o
f
i
r
s
t
D
X
b
i
t
,
F
S
X
precedes CLKX high CLKX int 12†ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 20†ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last
data bit 12†ns
†This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
36 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
serial-port timing parameters for TMS320C31-80 (see Figure 25 and Figure 26)
N
O
’C31-80
U
N
I
T
NO. MIN MAX UNIT
54 td(H1H-SCK) Delay time, H1 high to internal CLKX/R 7ns
5
5
t
C
y
c
l
e
t
i
m
e
C
L
K
X
/
R
CLKX/R ext tc(H)x2.6
n
s
55 tc(SCK) Cycle time, CLKX
/
RCLKX/R int tc(H)x2 tc(H)x232 ns
5
6
t
P
u
l
s
e
d
u
r
a
t
i
o
n
C
L
K
X
/
R
h
i
g
h
/
l
o
w
CLKX/R ext tc(H)+6
n
s
56 tw(SCK) Pulse duration, CLKX
/
Rhigh
/
low CLKX/R int [tc(SCK)/2]--5 [tc(SCK)/2]+5 ns
57 tr(SCK) Rise time, CLKX/R 3ns
58 tf(SCK) Fall time, CLKX/R 3ns
5
9
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
D
X
a
l
i
d
CLKX ext 16
n
s
59 td(C-DX) Delay time, CLKX to DX valid CLKX int 11 ns
6
0
t
S
e
t
p
t
i
m
e
D
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 6
n
s
60 tsu(DR-CLKRL) Setup time, DR be
f
ore CLKR low CLKR int 13 ns
6
1
t
H
o
l
d
t
i
m
e
D
R
f
r
o
m
C
L
K
R
l
o
CLKR ext 5
n
s
61 th(CLKRL-DR) Hold time, DR
f
rom CLKR low CLKR int 0ns
6
2
t
D
e
l
a
t
i
m
e
C
L
K
X
t
o
i
n
t
e
r
n
a
l
F
S
X
h
i
g
h
/
l
o
CLKX ext 16
n
s
62 td(C-FSX) Delay time, CLKX to internal FS
X
high
/
low CLKX int 12 ns
6
3
t
S
e
t
p
t
i
m
e
F
S
R
b
e
f
o
r
e
C
L
K
R
l
o
CLKR ext 5
n
s
63 tsu(FSR-CLKRL) Setup time, FSR be
f
ore CLKR low CLKR int 5ns
6
4
t
H
o
l
d
t
i
m
e
F
S
X
/
R
i
n
p
t
f
r
o
m
C
L
K
X
/
R
l
o
CLKX/R ext 5
n
s
64 th(SCKL-FS) Hold time, FSX
/
R input
f
rom CLK
X
/
Rlow CLKX/R int 0ns
6
5
t
S
e
t
p
t
i
m
e
e
t
e
r
n
a
l
F
S
X
b
e
f
o
r
e
C
L
K
X
CLKX ext -- [ t c(H)-- 8 ] †[tc(SCK)/2]--10†
n
s
65 tsu(FSX-C) Setup time, external FSX be
f
ore CLK
X
CLKX int -- [ t c(H)--21]†tc(SCK)/2†ns
6
6
t
Dela
y
time, CLKX to
f
irst DX bit, FS
X
CLKX ext 16
n
s
66 td(CH-DX)V
D
e
l
a
y
t
i
m
e
,
C
L
K
X
t
o
f
i
r
s
t
D
X
b
i
t
,
F
S
X
precedes CLKX high CLKX int 10 ns
67 td(FSX-DX)V Delay time, FSX to first DX bit, CLKX precedes FSX 16 ns
68 td(CH-DXZ) Delay time, CLKX high to DX high impedance following last data
bit 10 ns
†This value is characterized but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
37
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
data-rate timing modes
Unless otherwise indicated, the data-rate timings shown in Figure 25 and Figure 26 are valid for all serial-port
modes, including handshake. For a functional description of serial-port operation refer to subsection 8.2.12 of
the TMS320C3x User’s Guide (literature number SPRU031).
The serial-port timing parameters for seven ’C3x devices are defined in the preceding “serial-port timing
parameters” tables (such as “serial-port timing parameters for TMS320C31-60”). The numbers shown in
Figure 25 and Figure 26 correspond with those in the NO. column of each table.
FSX(EXT)
FSX(INT)
FSR
DR
DX
CLKX/R
H1
61
57 58
55
56
56
60
65
64
62
64
63
62
66
54
54
68
Bit 0
Bit n-1 Bit n-2
Bit n-1 Bit n-2
59
NOTES: A. Timing diagrams show operations with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
Figure 25. Timing for Fixed Data-Rate Mode
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
38 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
data-rate timing modes (continued)
CLKX/R
FSX(INT)
FSX(EXT)
DX
FSR
DR
62
65
64
63
60 61
59
68
67
66
Bit 0
Bit n-2 Bit n-3
Bit n-2 Bit n-3Bit n-1
Bit n-1
NOTES: A. Timing diagrams show operation with CLKXP = CLKRP = FSXP = FSRP = 0.
B. Timing diagrams depend on the length of the serial-port word, where n = 8, 16, 24, or 32 bits, respectively.
C. The timings that are not specified expressly for the variable data-rate mode are the same as those that are specified for the fixed
data-rate mode.
Figure 26. Timing for Variable Data-Rate Mode
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B - MARCH 1996 - REVISED JANUARY 1999
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
•39
HOLD timing
HOLD is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings are met, the exact sequence
shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA signals. The numbers shown in
Figure 27 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device comes out of hold and prevents
future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a read from or a write to the
primary bus is requested. In certain circumstances, the first write is pending, thus allowing the processor to continue until a second write is
encountered.
timing parameters for HOLD/HOLDA (see Figure 27)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
69 tsu(HOLD-H1L) Setup time, HOLD before H1 low 15 13 10 8 5 ns
70 tv(H1L-HOLDA) Valid time, HOLDA after H1 low 0†10 0†9 0†7 0†6 0†5ns
71 tw(HOLD)‡Pulse duration, HOLD low 2tc(H) 2tc(H) 2tc(H) 2tc(H) 2tc(H) ns
72 tw(HOLDA) Pulse duration, HOLDA low tcH-- 5 †tcH-- 5 †tcH-- 5 †tcH-- 5 †tcH-- 5 †ns
73 td(H1L-SH)H Delay time, H1 low to STRB high for a HOLD 0§10 0§9 0§7 0§6 0§4ns
74 tdis(H1L-S) Disable time, H1 low to STRB to the
high-impedance state 0§10†0§9†0§8†0§7†0§7†ns
75 ten(H1L-S) Enable time, H1 low to STRB enabled (active) 0§10 0§9 0§7 0§6 0§6ns
76 tdis(H1L-RW) Disable time, H1 low to R/W to the
high-impedance state 0†10†0†9†0†8†0†7†0†6†ns
77 ten(H1L-RW) Enable time, H1 low to R/W enabled (active) 0†10 0†9 0†7 0†6 0†6ns
78 tdis(H1L-A) Disable time, H1 low to address to the
high-impedance state 0§10†0§10†0§8†0§7†0§7†ns
79 ten(H1L-A) Enable time, H1 low to address enabled (valid) 0§15 0§13 0§12 0§11 0§10 ns
80 tdis(H1H-D) Disable time, H1 high to data to the
high-impedance state 0§10†0§9†0§8†0§7†0§6†ns
†This value is characterized but not tested
‡HOLD is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown in Figure 27 occurs; otherwise,
an additional delay of one clock cycle is possible.
§Not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
40 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
HOLD timing (continued)
H3
H1
HOLD
HOLDA
STRB
R/W
A
D
69 69
70
71
70
72
74
76
75
77
79
78
80
73
Write Data
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 27. Timing for HOLD/HOLDA
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
41
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The table, timing parameters for peripheral pin general-purpose I/O, defines peripheral pin general-purpose I/O
timing parameters. The numbers shown in Figure 28 correspond with those in the NO. column of the table
below.
timing parameters for peripheral pin general-purpose I/O (see Note 8 and Figure 28)
NO. LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
81 tsu(GPIO-H1L)
Setup time,
general-purpose input
before H1 low
12 10 9 8 7 ns
82 th(H1L-GPIO)
Hold time,
general-purpose input
after H1 low
0 0 0 0 0 ns
83 td(H1H-GPIO)
Delay time,
general-purpose output
after H1 high
15 13 10 8 6 ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Peripheral
Pin
(see Note A)
H1
H3
83 83
81
82
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 28. Timing for Peripheral Pin General-Purpose I/O
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
42 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
changing the peripheral pin I/O modes
The following tables show the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa. The numbers shown in Figure 29 and Figure 30 correspond
to those shown in the NO. column of the tables below.
timing parameters for peripheral pin changing from general-purpose output to input mode
(see Note 8 and Figure 29)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
84 th(H1H) Hold time, peripheral pin after
H1 high 15 13 10 8 6 ns
85 tsu(GPIO-H1L) Setup time, peripheral pin
before H1 low 10 9 9 8 7 ns
86 th(H1L-GPIO) Hold time, peripheral pin after
H1 low 00000ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
86
85
84
Value on Pin
Seen in
Peripheral-
Control
Register
Synchronizer Delay
Buffers Go
From
Output to
Input
Execution
of Store of
Peripheral-
Control
Register
Data Bit
Peripheral
Pin
(see Note A)
I/O
Control Bit
H1
H3
Output
Data
Seen
Data
Sampled
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 29. Timing for Change of Peripheral Pin From General-Purpose Output to Input Mode
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
43
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
timing parameters for peripheral pin changing from general-purpose input to output mode
(see Note 8 and Figure 30)
NO. ’LC31-33 ’C31-40
’LC31-40 ’C31-50 ’C31-60 ’C31-80 UNIT
N
O
.
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
U
N
I
T
87 td(H1H-GPIO)
Delay time, H1 high to
peripheral pin switching
from input to output
15 13 10 8 6 ns
NOTE 8: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Peripheral
Pin
(see Note A)
I/O
Control
Bit
H1
H3
Execution of Store
of Peripheral-
Control Register
87
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 30. Timing for Change of Peripheral Pin From General-Purpose Input to Output Mode
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B - MARCH 1996 - REVISED JANUARY 1999
44 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251--1443
•
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers.
The following tables define the timing parameters for the timer pin. The numbers shown in Figure 31 correspond with those in the NO. column
of the tables below.
timing parameters for timer pin for TMS320LC31-33 (see Figure 31) †
NO. DESCRIPTION‡’LC31-33 ’C31-40,
’LC31-40 UNIT
N
O
.
D
E
S
C
R
I
P
T
I
O
N
‡
MIN MAX MIN MAX
U
N
I
T
88 tsu(TCLK-H1L) Setup time, TCLK external before H1 low 12 10 ns
89 th(H1L-TCLK) Hold time, TCLK external after H1 low 0 0 ns
90 td(H1H-TCLK) Delay time, H1 high to TCLK internal valid 10 9ns
9
1
t
C
y
c
l
e
t
i
m
e
T
C
L
K
TCLK ext tc(H)×2.6 tc(H)×2.6
n
s
91 tc(TCLK) Cycle time, TCLK TCLK int tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡ns
9
2
t
P
u
l
s
e
d
u
r
a
t
i
o
n
T
C
L
K
h
i
g
h
/
l
o
w
TCLK ext tc(H)+12 tc(H)+10
n
s
92 tw(TCLK) Pulse duration, TCLK high
/
low TCLK int [tc(TCLK)/2]--15 [tc(TCLK)/2]+5 [tc(TCLK)/2]--5 [tc(TCLK)/2]+5 ns
†Timing parameters 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous input clock.
‡Specified by design but not tested
timing parameters for timer pin for TMS320LC31-40, TMS320C31-50, and TMS320C31-60 (see Figure 31) †
N
O
D
E
S
C
R
I
P
T
I
O
N
‡
’C31-50 ’C31-60 ’C31-80
U
N
I
T
NO. DESCRIPTION
‡
MIN MAX MIN MAX MIN MAX UNIT
88 tsu(TCLK-H1L) Setup time, TCLK external
before H1 low 8 6 5 ns
89 th(H1L-TCLK) Hold time, TCLK external
after H1 low 0 0 0 ns
90 td(H1H-TCLK) Delay time, H1 high to TCLK
internal valid 9 8 6 ns
9
1
t
TCLK ext tc(H)×2.6 tc(H)×2.6 tc(H)×2.6
n
s
91 tc(TCLK) TCLK int tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡tc(H)×2 tc(H)×232‡ns
9
2
t
TCLK ext tc(H)+10 tc(H)+10 tc(H)+6
n
s
92 tw(TCLK) TCLK int [tc(TCLK)/2]--5 [tc(TCLK)/2]+5 [tc(TCLK)/2]--5 [tc(TCLK)/2]+5 [tc(TCLK)/2]--5 [tc(TCLK)/2]+5 ns
†Timing parameters 88 and 89 are applicable for a synchronous input clock. Timing parameters 91 and 92 are applicable for an asynchronous input clock.
‡Specified by design but not tested
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
45
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
timer pin timing (continued)
90
90
89
Peripheral
Pin
(see Note A)
H1
H3
88
91
92
NOTE A: HOLDA goes low in response to HOLD going low and continues to remain low until one H1 cycle
after HOLD goes back high.
Figure 31. Timing for Timer Pin
SHZ pin timing
The following table defines the timing parameter for the SHZ pin. The number shown in Figure 32 corresponds
with that in the NO. column of the table below.
timing parameters for SHZ (see Figure 32)
NO.
’C31
’LC31 UNIT
N
O
.
MIN MAX
U
N
I
T
93 tdis(SHZ) Disable time, SHZ low to all O, I/O pins disabled (high impedance) 0†2P†‡ ns
†This value is characterized but not tested
‡P=t
c(CI)
93
H3
H1
SHZ
All I/O Pins
NOTE A: Enabling SHZ destroys TMS320C3x register and memory contents.
Assert SHZ = 1 and reset the TMS320C3x to restore it to a known
condition.
Figure 32. Timing for SHZ
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
46 POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
SHZ pin timing (continued)
Table 1. Thermal Resistance Characteristics
PARAMETER °C/W AIR FLOW
LFPM
RθJC†11.0 N/A
RθJA‡49.0 0
RθJA‡35.5 200
RθJA‡28.0 400
RθJA‡23.5 600
RθJA‡21.6 800
RθJA‡20.0 1000
†RΘSC = junction-to-case
‡RΘJA = junction-to-free air
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B -- MARCH 1996 -- REVISED JANUARY 1999
47
POST OFFICE BOX 1443 •HOUSTON, TEXAS 77251--1443
MECHANICAL DATA
The following packaging information and addendum reflect the most current data available for the designated
device(s). This data is subject to change without notice and without revision of this document.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Sep-2011
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TMS320C31PQA40 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C31PQA50 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C31PQL40 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C31PQL50 NRND BQFP PQ 132 1 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C31PQL60 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320C31PQL80 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
TMS320LC31PQ40 NRND BQFP PQ 132 36 Green (RoHS
& no Sb/Br) CU NIPDAU Level-4-260C-72 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 17-Sep-2011
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TMS320C31, TMS320LC31 :
•Catalog: SM320C31
•Enhanced Product: SM320LC31-EP
•Military: SMJ320C31
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
•Enhanced Product - Supports Defense, Aerospace and Medical Applications
•Military - QML certified for Military and Defense Applications
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PQ (S-PQFP-G***) PLASTIC QUAD FLATPACK
100 LEAD SHOWN
88
0.012 (0,30)
0.008 (0,20)
64
0.025 (0,635)
Seating Plane
132
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
4040045/C 11/95
100113
6339
”D2” SQ
”D1” SQ
”D” SQ
14
”D3” SQ
38
DIM
”D”
”D2”
”D3”
”D1”
NOM
MIN
MAX
MIN
MAX
MIN
MAX
LEADS ***
0.180 (4,57) MAX
100
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
0.004 (0,10)
M
0.006 (0,15)
0.010 (0,25)
0.020 (0,51) MIN
0.130 (3,30)
0.150 (3,81)
0.006 (0,16) NOM
Gage Plane
0.036 (0,91)
0.046 (1,17)
0°–8°
89
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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