Ultralow Noise Amplifier at Lower Power ADA4075-2 PIN CONFIGURATIONS Ultralow noise: 2.8 nV/Hz at 1 kHz typical Ultralow distortion: 0.0002% typical Low supply current: 1.8 mA per amplifier typical Offset voltage: 1 mV maximum Bandwidth: 6.5 MHz typical Slew rate: 12 V/s typical Unity-gain stable Extended industrial temperature range 8-lead SOIC and 2 mm x 2 mm LFCSP packages OUTA 1 -INA 2 8 ADA4075-2 V+ OUTB TOP VIEW 6 -INB (Not to Scale) 5 +INB V- 4 7 +INA 3 07642-001 FEATURES Figure 1. 8-Lead SOIC APPLICATIONS Precision instrumentation Professional audio Active filters Low noise amplifier front end Integrators -INA 2 ADA4075-2 7 OUTB +INA 3 TOP VIEW (Not to Scale) 6 -INB V- 4 5 +INB 07642-002 8 V+ OUTA 1 Figure 2. 8-Lead, 2 mm x 2 mm LFCSP GENERAL DESCRIPTION Table 1. Low Noise Precision Op Amps The ADA4075-2 is a dual, high performance, low noise operational amplifier combining excellent dc and ac characteristics on the Analog Devices, Inc., iPolar(R) process. The iPolar process is an advanced bipolar technology implementing vertical junction isolation with lateral trench isolation. This allows for low noise performance amplifiers in smaller die size at faster speed and lower power. Its high slew rate, low distortion, and ultralow noise make the ADA4075-2 ideal for high fidelity audio and high performance instrumentation applications. It is also especially useful for lower power demands, small enclosures, and high density applications. The ADA4075-2 is specified for the -40C to +125C temperature range and is available in a standard SOIC package and a 2 mm x 2 mm LFCSP package. Supply Single 44 V OP27 Dual OP275 Quad 36 V AD8671 AD8675 AD8597 ADA4004-1 AD797 AD8672 AD8676 AD8599 ADA4004-2 AD8674 ADA4004-4 12 V to 16 V AD8665 OP162 5V AD8605 AD8655 AD8691 AD8666 OP262 AD8606 AD8656 AD8692 AD8668 OP462 AD8608 AD8694 Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008-2009 Analog Devices, Inc. All rights reserved. ADA4075-2 TABLE OF CONTENTS Features .............................................................................................. 1 Applications Information .............................................................. 16 Applications ....................................................................................... 1 Input Protection ......................................................................... 16 Pin Configurations ........................................................................... 1 Total Harmonic Distortion ....................................................... 16 General Description ......................................................................... 1 Phase Reversal ............................................................................ 16 Revision History ............................................................................... 2 DAC Output Filter...................................................................... 17 Specifications..................................................................................... 3 Balanced Line Driver ................................................................. 18 Absolute Maximum Ratings............................................................ 5 Balanced Line Receiver.............................................................. 19 Thermal Resistance ...................................................................... 5 Low Noise Parametric Equalizer .............................................. 20 Power Sequencing ........................................................................ 5 Schematic ......................................................................................... 21 ESD Caution .................................................................................. 5 Outline Dimensions ....................................................................... 22 Typical Performance Characteristics ............................................. 6 Ordering Guide .......................................................................... 22 REVISION HISTORY 8/09--Rev. 0 to Rev. A Added 8-Lead LFCSP_WD ............................................... Universal Changes to Table 1 ............................................................................ 1 Changes to Table 2 ............................................................................ 3 Changes to Table 3 ............................................................................ 4 Changes to Table 4 and Table 5 ....................................................... 5 Changes to Figure 3, Figure 5, Figure 6, and Figure 8 ................. 6 Added Figure 4 and Figure 7; Renumbered Sequentially ........... 6 Added Figure 9 and Figure 12 ......................................................... 7 Changes to Figure 10, Figure 11, Figure 13, and Figure 14 ......... 7 Changes to Figure 16, Figure 17, Figure 19, and Figure 20 ......... 8 Changes to Figure 22 and Figure 25 ............................................... 9 Changes to Figure 36 ...................................................................... 11 Changes to Figure 54 ...................................................................... 14 Changes to and Moved Figure 57 and Figure 60 to ................... 15 Changes to Figure 59 and Figure 62 ............................................. 15 Changes to Input Protection Section and Phase Reversal Section .............................................................................. 16 Changes to DAC Output Filter Section ....................................... 17 Changes to Figure 67 ...................................................................... 18 Updated Outline Dimensions ....................................................... 22 Changes to Ordering Guide .......................................................... 22 10/08--Revision 0: Initial Version Rev. A | Page 2 of 24 ADA4075-2 SPECIFICATIONS VSY = 15 V, VCM = 0 V, TA = 25C, SOIC package, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 0.2 1 1.2 100 150 50 75 +12.5 mV mV nA nA nA nA V dB dB dB dB dB dB V/C M M pF pF -40C TA +125C Input Bias Current IB 30 -40C TA +125C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Input Resistance, Differential Mode Input Resistance, Common Mode Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin THD + NOISE Total Harmonic Distortion and Noise NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density VOS/T RINDM RINCM CINDM CINCM VOH VOL ISC ZOUT PSRR ISY 5 -40C TA +125C -40C TA +125C VCM = -12.5 V to +12.5 V -40C TA +125C RL = 2 k, VO = -11 V to +11 V -40C TA +125C RL = 600 , VO = -10 V to +10 V -40C TA +125C -40C TA +125C RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C -12.5 110 106 114 108 112 106 117 117 0.3 1.5 500 2.4 2.1 12.8 12.5 12.4 12 15 14 13 12.8 15.8 -14 -13.6 -16.6 -13.6 -13 -13 -12.5 -16 -15 40 0.1 f = 1 kHz, AV = 1 VSY = 4.5 V to 18 V -40C TA +125C VSY = 4.5 V to 18 V, IO = 0 mA -40C TA +125C 118 106 100 110 1.8 2.25 3.35 V V V V V V V V V V V V mA dB dB mA mA SR tS GBP M RL = 2 k, AV = 1 To 0.01%, VIN = 10 V step, RL = 1 k RL = 1 M, CL = 35 pF, AV = 1 RL = 1 M, CL = 35 pF, AV = 1 12 3 6.5 60 V/s s MHz Degrees THD + N RL = 2 k, AV = 1, VIN = 3 V rms, f = 1 kHz 0.0002 % en p-p en in f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 60 2.8 1.2 nV p-p nV/Hz pA/Hz Rev. A | Page 3 of 24 ADA4075-2 VSY = 15 V, VCM = 0 V, TA = 25C, LFCSP package, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Typ Max Unit 0.3 1 1.5 100 150 50 75 +12.5 mV mV nA nA nA nA V dB dB dB dB dB dB V/C M M pF pF -40C TA +125C Input Bias Current IB 30 -40C TA +125C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio CMRR Large Signal Voltage Gain AVO Offset Voltage Drift Input Resistance, Differential Mode Input Resistance, Common Mode Input Capacitance, Differential Mode Input Capacitance, Common Mode OUTPUT CHARACTERISTICS Output Voltage High Output Voltage Low Short-Circuit Current Closed-Loop Output Impedance POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier DYNAMIC PERFORMANCE Slew Rate Settling Time Gain Bandwidth Product Phase Margin THD + NOISE Total Harmonic Distortion and Noise NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density VOS/T RINDM RINCM CINDM CINCM VOH VOL ISC ZOUT PSRR ISY 5 -40C TA +125C -40C TA +125C VCM = -12.5 V to +12.5 V -40C TA +125C RL = 2 k, VO = -11 V to +11 V -40C TA +125C RL = 600 , VO = -10 V to +10 V -40C TA +125C -40C TA +125C RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C RL = 2 k to GND -40C TA +125C RL = 600 to GND -40C TA +125C VSY = 18 V, RL = 600 to GND -40C TA +125C -12.5 110 106 110 102 108 100 117 117 3 1.5 500 2.4 2.1 12.8 12.5 12.4 12 15 14 13 12.8 15.8 -14 -13.6 -16.6 -13.6 -13 -13 -12.5 -16 -15 40 0.1 f = 1 kHz, AV = 1 VSY = 4.5 V to 18 V -40C TA +125C VSY = 4.5 V to 18 V, IO = 0 mA -40C TA +125C 116 100 95 104 1.8 2.25 3.35 V V V V V V V V V V V V mA dB dB mA mA SR tS GBP M RL = 2 k, AV = 1 To 0.01%, VIN = 10 V step, RL = 1 k RL = 1 M, CL = 35 pF, AV = 1 RL = 1 M, CL = 35 pF, AV = 1 12 3 6.5 60 V/s s MHz Degrees THD + N RL = 2 k, AV = 1, VIN = 3 V rms, f = 1 kHz 0.0002 % en p-p en in f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 60 2.8 1.2 nV p-p nV/Hz pA/Hz Rev. A | Page 4 of 24 ADA4075-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Input Voltage Input Current1 Differential Input Voltage Output Short-Circuit Duration to GND Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature (Soldering, 60 sec) 1 JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. This was measured using a standard 4-layer board. Rating 20 V VSY 10 mA 1.2 V Indefinite -65C to +150C -40C to +125C -65C to +150C 300C Table 5. Thermal Resistance Package Type 8-Lead SOIC 8-Lead LFCSP JA 158 115 JC 43 40 Unit C/W C/W POWER SEQUENCING The input pins have clamp diodes to the power supply pins. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. The op amp supplies must be established simultaneously with, or before, any input signals are applied. If this is not possible, limit the input current to 10 mA. ESD CAUTION Rev. A | Page 5 of 24 ADA4075-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, unless otherwise noted. 200 150 100 VSY = 5V VCM = 0V BASED ON 600 OP AMPS SOIC PACKAGE 150 100 -0.5 0 0.5 1.0 VOS (mV) 0 -1.0 07642-003 0 -1.0 100 VSY = 15V VCM = 0V BASED ON 300 OP AMPS LFCSP PACKAGE 80 60 40 VSY = 5V VCM = 0V BASED ON 300 OP AMPS LFCSP PACKAGE 60 40 0 0.5 1.0 VOS (mV) 0 -1.0 -0.5 0 0.5 1.0 VOS (mV) Figure 4. Input Offset Voltage Distribution 07642-042 -0.5 07642-040 0 -1.0 Figure 7. Input Offset Voltage Distribution 80 70 VSY = 15V -40C TA +125C BASED ON 200 OP AMPS SOIC PACKAGE VSY = 5V -40C TA +125C BASED ON 200 OP AMPS SOIC PACKAGE 70 NUMBER OF AMPLIFIERS 60 50 40 30 20 10 60 50 40 30 20 10 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 TCVOS (V/C) 2.0 0 -2.0 07642-004 NUMBER OF AMPLIFIERS 1.0 20 20 0 -2.0 0.5 Figure 6. Input Offset Voltage Distribution NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 80 0 VOS (mV) Figure 3. Input Offset Voltage Distribution 100 -0.5 07642-006 50 50 -1.6 -1.2 -0.8 -0.4 0 0.4 0.8 1.2 1.6 TCVOS (V/C) Figure 8. Input Offset Voltage Drift Distribution Figure 5. Input Offset Voltage Drift Distribution Rev. A | Page 6 of 24 2.0 07642-007 NUMBER OF AMPLIFIERS 200 250 VSY = 15V VCM = 0V BASED ON 600 OP AMPS SOIC PACKAGE NUMBER OF AMPLIFIERS 250 ADA4075-2 40 40 VSY = 15V VCM = 0V BASED ON 300 OP AMPS LFCSP PACKAGE 30 25 20 15 10 5 30 25 20 15 10 2 3 4 5 TCVOS (V/C) 6 7 8 0 0 Figure 9. Input Offset Voltage Drift Distribution 100 100 VOS (V) 200 0 -100 -200 -200 -5 0 5 10 15 VCM (V) -300 -5 6 7 8 VSY = 5V BASED ON 60 OP AMPS -4 -3 -2 -1 0 1 2 3 5 125 4 VCM (V) Figure 10. Input Offset Voltage vs. Common-Mode Voltage 80 4 5 TCVOS (V/C) 0 -100 -10 3 300 VSY = 15V BASED ON 60 OP AMPS 200 -300 -15 2 Figure 12. Input Offset Voltage Drift Distribution 07642-005 VOS (V) 300 1 07642-008 1 07642-012 0 07642-052 5 07642-043 0 VSY = 5V VCM = 0V BASED ON 300 OP AMPS LFCSP PACKAGE 35 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 35 Figure 13. Input Offset Voltage vs. Common-Mode Voltage 100 VSY = 15V VSY = 5V 80 60 IB (nA) 40 40 20 20 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 07642-009 IB (nA) 60 Figure 11. Input Bias Current vs. Temperature 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) Figure 14. Input Bias Current vs. Temperature Rev. A | Page 7 of 24 ADA4075-2 60 60 VSY = 5V 50 40 40 30 20 20 10 10 -5 0 5 10 15 VCM (V) 0 -4 OUTPUT VOLTAGE TO SUPPLY RAIL (V) V+ - VOH 1 VOL - V- 0.1 1 10 100 LOAD CURRENT (mA) OUTPUT VOLTAGE TO SUPPLY RAIL (V) 1.5 VOL - V- -25 0 25 50 75 100 TEMPERATURE (C) 125 07642-011 0.5 0 -50 3 4 V+ - VOH 1 VOL - V- 0.01 0.1 1 10 2.0 V+ - VOH 1.0 2 100 Figure 19. Output Voltage to Supply Rail vs. Load Current VSY = 15V RL = 2k 2.0 1 LOAD CURRENT (mA) Figure 16. Output Voltage to Supply Rail vs. Load Current 2.5 0 VSY = 5V 0.1 0.001 07642-010 OUTPUT VOLTAGE TO SUPPLY RAIL (V) 10 0.01 -1 Figure 18. Input Bias Current vs. Input Common-Mode Voltage VSY = 15V 0.1 0.001 -2 VCM (V) Figure 15. Input Bias Current vs. Input Common-Mode Voltage 10 -3 07642-013 -10 Figure 17. Output Voltage to Supply Rail vs. Temperature VSY = 5V RL = 2k V+ - VOH 1.5 1.0 VOL - V- 0.5 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) Figure 20. Output Voltage to Supply Rail vs. Temperature Rev. A | Page 8 of 24 125 07642-014 0 -15 OUTPUT VOLTAGE TO SUPPLY RAIL (V) 30 07642-049 IB (nA) 50 07642-047 IB (nA) VSY = 15V ADA4075-2 100 80 80 80 60 60 60 40 40 20 20 GAIN 0 0 -20 -20 -40 -40 -60 -80 10k 100k 1M 40 20 20 0 0 -20 -40 -40 -60 -60 -60 -80 -80 -80 FREQUENCY (Hz) -100 1k 40 40 GAIN (dB) GAIN (dB) 20 0 1k 10k 100k 1M 10M 100M -20 10 07642-117 100 AV = +1 AV = +10 ZOUT () AV = +1 0.01 0.01 FREQUENCY (Hz) 10M 0.001 10 07642-017 1M 10M 100M AV = +10 AV = +100 AV = +1 0.1 100k 1M 1 0.1 10k 100k VSY = 5V 10 1 1k 10k 100 AV = +100 100 1k Figure 25. Closed-Loop Gain vs. Frequency 1k 10 100 FREQUENCY (Hz) VSY = 15V 100 ZOUT () AV = +10 -10 Figure 22. Closed-Loop Gain vs. Frequency 0.001 10 VSY = 5V AV = +100 10 AV = +1 FREQUENCY (Hz) 1k -100 100M 10M 30 AV = +10 -10 -20 10 1M 50 VSY = 15V AV = +100 10 0 100k Figure 24. Open-Loop Gain and Phase vs. Frequency 30 20 10k FREQUENCY (Hz) Figure 21. Open-Loop Gain and Phase vs. Frequency 50 60 GAIN 40 -20 -100 100M 10M 80 07642-120 -100 1k 100 PHASE 100 1k 10k 100k 1M FREQUENCY (Hz) Figure 26. Output Impedance vs. Frequency Figure 23. Output Impedance vs. Frequency Rev. A | Page 9 of 24 10M 07642-020 GAIN (dB) PHASE 120 PHASE (Degrees) 100 100 140 VSY = 5V 07642-018 120 GAIN (dB) 140 120 PHASE (Degrees) 140 VSY = 15V 120 07642-015 140 ADA4075-2 140 120 100 100 CMRR (dB) 120 80 60 80 60 40 40 20 20 10k 100k 1M 10M FREQUENCY (Hz) 0 100 1k 80 PSRR (dB) 80 PSRR- 40 60 40 20 0 0 100 1k 10k 100k 1M 10M 100M FREQUENCY (Hz) -20 10 100 40 100k 1M 10M 100M 1000 VSY = 5V AV = +1 RL = 2k 35 30 OVERSHOOT (%) 30 25 20 15 25 20 15 10 10 5 5 0 10 100 CAPACITANCE (pF) 1000 07642-023 OVERSHOOT (%) 10k Figure 31. PSRR vs. Frequency VSY = 15V AV = +1 RL = 2k 35 1k FREQUENCY (Hz) Figure 28. PSRR vs. Frequency 40 PSRR- PSRR+ 20 07642-022 PSRR (dB) 100 -20 10 10M VSY = 5V 100 PSRR+ 1M 120 VSY = 15V 60 100k Figure 30. CMRR vs. Frequency Figure 27. CMRR vs. Frequency 120 10k FREQUENCY (Hz) 07642-025 1k 07642-026 0 100 VSY = 5V 07642-024 VSY = 15V 07642-021 CMRR (dB) 140 0 10 100 CAPACITANCE (pF) Figure 32. Small Signal Overshoot vs. Load Capacitance Figure 29. Small Signal Overshoot vs. Load Capacitance Rev. A | Page 10 of 24 ADA4075-2 VSY = 5V VIN = 7V p-p AV = +1 RL = 2k CL = 100pF VOLTAGE (2V/DIV) TIME (4s/DIV) Figure 33. Large Signal Transient Response Figure 36. Large Signal Transient Response VOLTAGE (20mV/DIV) VSY = 15V VIN = 100mV p-p AV = +1 RL = 2k CL = 100pF VSY = 5V VIN = 100mV p-p AV = +1 RL = 2k CL = 100pF 07642-028 0V TIME (10s/DIV) Figure 37. Small Signal Transient Response 4 4 VSY = 15V VSY = 5V 2 2 TIME (1s/DIV) INPUT OUTPUT 0 -2 -10 -4 -15 -6 -20 Figure 35. Negative Overload Recovery TIME (1s/DIV) Figure 38. Negative Overload Recovery Rev. A | Page 11 of 24 -8 OUTPUT VOLTAGE (V) -5 INPUT VOLTAGE (V) 0 OUTPUT VOLTAGE (V) OUTPUT 0 07642-032 INPUT 07642-029 INPUT VOLTAGE (V) 0V TIME (10s/DIV) Figure 34. Small Signal Transient Response 0 07642-030 TIME (4s/DIV) VOLTAGE (20mV/DIV) 0V 07642-027 0V 07642-031 VOLTAGE (5V/DIV) VSY = 15V VIN = 20V p-p AV = +1 RL = 2k CL = 100pF ADA4075-2 4 4 VSY = 5V VSY = 15V 2 INPUT INPUT -2 15 10 5 -2 4 2 OUTPUT 0 0 -2 07642-033 -5 -10 TIME (1s/DIV) Figure 42. Positive Overload Recovery VSY = 5V VSY = 15V INPUT VOLTAGE (5V/DIV) VOLTAGE (5V/DIV) -4 TIME (1s/DIV) Figure 39. Positive Overload Recovery INPUT 07642-034 OUTPUT INPUT VOLTAGE (V) 0 OUTPUT VOLTAGE (V) INPUT VOLTAGE (V) 0 OUTPUT VOLTAGE (V) 2 +10mV OUTPUT +6mV OUTPUT 0V 0V ERROR BAND ERROR BAND -10mV TIME (2s/DIV) 07642-062 07642-061 -6mV TIME (2s/DIV) Figure 43. Positive Settling Time to 0.01% Figure 40. Positive Settling Time to 0.01% VSY = 5V VSY = 15V INPUT VOLTAGE (5V/DIV) VOLTAGE (5V/DIV) INPUT +10mV OUTPUT +6mV ERROR BAND OUTPUT 0V 0V ERROR BAND -10mV TIME (2s/DIV) Figure 44. Negative Settling Time to 0.01% Figure 41. Negative Settling Time to 0.01% Rev. A | Page 12 of 24 07642-063 07642-064 TIME (2s/DIV) -6mV ADA4075-2 10 10 VSY = 5V 100 1k 10k 100k FREQUENCY (Hz) 1 1 10 CURRENT NOISE DENSITY (pA/ Hz) CURRENT NOISE DENSITY (pA/ Hz) 10 RS2 UNCORRELATED RS1 = 0 1 1 10 100 1k 10k 100k FREQUENCY (Hz) 07642-045 CORRELATED RS1 = RS2 0.1 10k 100k 100k Figure 48. Voltage Noise Density RS1 VSY = 15V 1k FREQUENCY (Hz) Figure 45. Voltage Noise Density 10 100 07642-038 10 07642-046 1 VSY = 5V RS1 RS2 UNCORRELATED RS1 = 0 1 CORRELATED RS1 = RS2 0.1 1 10 100 1k 10k FREQUENCY (Hz) Figure 49. Current Noise Density Figure 46. Current Noise Density VSY = 5V TIME (1s/DIV) 07642-036 INPUT NOISE VOLTAGE (10nV/DIV) INPUT NOISE VOLTAGE (10nV/DIV) VSY = 15V TIME (1s/DIV) Figure 47. 0.1 Hz to 10 Hz Noise Figure 50. 0.1 Hz to 10 Hz Noise Rev. A | Page 13 of 24 07642-039 1 07642-035 VOLTAGE NOISE DENSITY (nV/Hz) VOLTAGE NOISE DENSITY (nV/Hz) VSY = 15V ADA4075-2 6 8 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) 5 6 +125C +85C 4 +25C -40C 2 VSY = 15V 4 VSY = 5V 3 2 4 6 8 10 12 14 16 18 SUPPLY VOLTAGE (V) 0 -50 07642-048 0 -25 50 75 100 125 Figure 54. Supply Current vs. Temperature 10 VSY = 15V f = 1kHz 1 1 0.1 0.1 THD + NOISE (%) THD + NOISE (%) 25 TEMPERATURE (C) Figure 51. Supply Current vs. Supply Voltage 10 0 07642-057 1 0.01 0.001 VSY = 5V f = 1kHz 0.01 0.001 600 600 0.001 0.01 0.1 1 2k 10 AMPLITUDE (V rms) 07642-058 0.00001 0.0001 0.0001 2k 0.00001 0.0001 0.1 1 10 Figure 55. THD + Noise vs. Amplitude 1 VSY = 15V VIN = 3V rms 0.1 VSY = 5V VIN = 1.5V rms THD + NOISE (%) 0.1 0.01 0.001 0.01 600 0.001 600 2k 0.0001 10 100 1k 10k FREQUENCY (Hz) 100k 0.0001 10 100 1k 10k FREQUENCY (Hz) Figure 56. THD + Noise vs. Frequency Figure 53. THD + Noise vs. Frequency Rev. A | Page 14 of 24 100k 07642-067 2k 07642-060 THD + NOISE (%) 0.01 AMPLITUDE (V rms) Figure 52. THD + Noise vs. Amplitude 1 0.001 07642-065 0.0001 ADA4075-2 0 1k -40 RL -60 -80 -100 -120 1k -40 RL -60 -80 -100 10k 100k FREQUENCY (Hz) -140 100 07642-041 1k 10k 100k FREQUENCY (Hz) Figure 57. Channel Separation vs. Frequency 10 1k 07642-044 -120 -140 100 Figure 60. Channel Separation vs. Frequency 1 VSY = 18V f = 1kHz 1 VSY = 18V VIN = 8V rms 0.1 THD + NOISE (%) 0.1 THD + NOISE (%) VSY = 5V VIN = 5V p-p RL = 2k 100k -20 CHANNEL SEPARATION (dB) CHANNEL SEPARATION (dB) -20 0 VSY = 15V VIN = 10V p-p RL = 2k 100k 0.01 0.001 0.01 0.001 600 600 2k 0.0001 0.0001 0.01 0.1 1 10 100 AMPLITUDE (V rms) 0.00001 10 10 OUTPUT VOLTAGE TO SUPPLY RAIL (V) 1.5 VOL - V- 0.5 0 -50 -25 0 25 50 75 100 TEMPERATURE (C) 125 07642-066 OUTPUT VOLTAGE TO SUPPLY RAIL (V) V+ - VOH 1.0 10k 100k Figure 61. THD + Noise vs. Frequency VSY = 18V RL = 2k 2.0 1k FREQUENCY (Hz) Figure 58. THD + Noise vs. Amplitude 2.5 100 07642-059 0.001 Figure 59. Output Voltage to Supply Rail vs. Temperature VSY = 18V V+ - VOH 1 VOL - V- 0.1 0.001 0.01 0.1 1 10 LOAD CURRENT (mA) Figure 62. Output Voltage to Supply Rail vs. Load Current Rev. A | Page 15 of 24 100 07642-068 0.00001 0.0001 07642-056 2k ADA4075-2 APPLICATIONS INFORMATION 1 INPUT PROTECTION ADA4075-2 R1 2 1 07642-050 R2 3 Figure 63. Input Protection TOTAL HARMONIC DISTORTION VSY = 4V RL = 2k VIN = 1.5V rms 0.01 0.0001 10 100 1k 10k 100k FREQUENCY (Hz) 07642-069 VSY = 15V RL = 2k VIN = 3V rms 0.001 Figure 64. THD + Noise vs. Frequency PHASE REVERSAL An undesired phenomenon, phase reversal (also known as phase inversion) occurs in many op amps when one or both of the inputs are driven beyond the specified input common-mode voltage (VICM) range, in effect reversing the polarity of the output. In some cases, phase reversal can induce lockups and cause equipment damage as well as self destruction. The ADA4075-2 incorporates phase reversal prevention circuitry that clamps the output to 2 V typical from the supply rails when one or both inputs exceed the VICM range. Figure 65 shows the input/output waveforms of the ADA4075-2 configured as a unitygain buffer for a supply voltage of 15 V. VIN VSY = 15V VOUT 07642-053 The total harmonic distortion + noise (THD + N) of the ADA4075-2 is 0.0002% typical with a load resistance of 2 k. Figure 64 shows the performance of the ADA4075-2 driving a 2 k load with supply voltages of 4 V and 15 V. Notice that there is more distortion for the supply voltage of 4 V than for a supply voltage of 15 V. Therefore, it is important to operate the ADA4075-2 at a supply voltage greater than 5 V for optimum distortion. The THD + noise graphs for supply voltages of 5 V and 18 V are available in Figure 56 and Figure 61. THD + NOISE (%) In small signal applications, current limiting is not required; however, in applications where the differential voltage of the ADA4075-2 exceeds 1.2 V, large currents may flow through these diodes. Employ external current-limiting resistors as shown in Figure 63 to reduce the input currents to less than 10 mA. Note that depending on the value of these resistors, the total voltage noise will most likely be degraded. For example, a 1 k resistor at room temperature has a thermal noise of 4 nV/Hz, whereas the ADA4075-2 has an ultralow voltage noise of only 2.8 nV/Hz typical. 0.1 VOLTAGE (5V/DIV) To prevent base-emitter junction breakdown from occurring in the input stage of the ADA4075-2 when a very large differential voltage is applied, the inputs are clamped by the internal diodes to 1.2 V. To preserve the ultralow voltage noise feature of the ADA4075-2, the commonly used internal current-limiting resistors in series with the inputs are not used. TIME (40s/DIV) Figure 65. No Phase Reversal Rev. A | Page 16 of 24 ADA4075-2 DAC OUTPUT FILTER For a DAC output filter, an op amp with reasonable slew rate and bandwidth is required. The ADA4075-2 has a high slew rate of the 12 V/s and a relatively wide bandwidth of 6.5 MHz. The cutoff frequency of the low-pass filter is approximately 167 kHz. In addition, the 100 k - 47 F RC network provides ac coupling to block out the dc components at the output. The ultralow voltage noise, low distortion, and high slew rate of the ADA4075-2 make it an ideal choice for professional audio signal processing. Figure 66 shows the ADA4075-2 used in a typical audio DAC output filter configuration. The differential outputs of the DAC are fed into the ADA4075-2. The ADA4075-2 is configured as a differential Sallen-Key filter. It operates as an external low-pass filter to remove high frequency noise present on the output pins of the DAC. It also provides differential-tosingle-ended conversion from the differential outputs of the DAC. 11k 68pF 5.62k 1.5k 1/2 100 ADA4075-2 560pF 5.62k 270pF 47F 2.2nF 150pF Figure 66. Typical DAC Output Filter Circuit (Differential) Rev. A | Page 17 of 24 OUTPUT 100k 07642-054 DAC OUTP 3.01k + DAC OUTN 11k ADA4075-2 Finally, even with these precautions, it is vital that the positive feedback be accurately controlled. This is partly achieved by using 1% resistors. In addition, the following setup procedure ensures that the positive feedback does not become excessive: BALANCED LINE DRIVER The circuit of Figure 67 shows a balanced line driver designed for audio use. Such drivers are intended to mimic an output transformer in operation, whereby the common-mode voltage can be impressed by the load. Furthermore, either output can be shorted to ground in single-ended applications without affecting the overall operation. 1. Set R11 to its midposition (or short the ends together, whichever is easier) and temporarily short the negative output to ground. Apply a 10 V p-p sine wave at approximately 1 kHz to the input and adjust R7 to provide 930 mV p-p at TEST (see Figure 67). Remove the short from the negative output (and across R11, if used) and adjust R11 until the output waveforms are symmetric. 2. Circuits of this type use positive and negative feedback to obtain a high common-mode output impedance, and they are somewhat notorious for component sensitivity and susceptibility to latch-up. This circuit uses several techniques to avoid spurious behavior. 3. First, the 4-op-amp arrangement ensures that the input impedance is load independent (the input impedance can become negative with some configurations). Note that the output op amps are packaged with the input op amps to maximize drive capability. The overall gain of the driver is equal to 2, which provides an extra 6 dB of headroom in balanced differential mode. The output noise is about -109 dBV in a 20 kHz bandwidth. Second, the positive feedback is ac-coupled by C2 and C3, which eliminates the need for offset trim. Because the circuit is ac-coupled at the input, these capacitors do not have significant dc voltage across them, thus tantalum types of capacitors can be used. C5 IN 50pF A1 R4 R5 4.7k 4.7k A2 1/2 R1 10k ADA4075-2 R6 C4 50pF R3 4.7k A3 R7 250 R8 4.7k FEEDBACK TRIM R10 4.7k 1/2 ADA4075-2 OUT+ 100 ADA4075-2 R18 4.7k R2 4.7k R13 1/2 SYMMETRY TRIM R12 R11 250 TEST 4.7k C2 10F C3 10F 4.7k C6 50pF A4 R15 R9 100 4.7k 1/2 R14 100 OUT- ADA4075-2 R16 R17 100 4.7k NOTES 1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE. 2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE. Figure 67. Balanced Line Driver Rev. A | Page 18 of 24 07642-073 C1 10F ADA4075-2 BALANCED LINE RECEIVER Figure 68 depicts a unity-gain balanced line receiver capable of a high degree of hum rejection. The CMRR is approximately given by Note that A3 is not in the signal path, and almost any op amp works well here. Although it may seem as though the inverting output should be noisier than the noninverting one, they are in fact symmetric at about -111 dBV (20 kHz bandwidth). R1 x R4 20 log 10 R2 x R3 Sometimes an overall gain of 1/2 is desired to provide an extra 6 dB of differential input headroom. This can be attained by reducing R3 and R4 to 5 k and increasing R9 to 22 k. Therefore, R1 to R4 should be close tolerance components to obtain the best possible CMRR without adjustment. The presence of A2 ensures that the impedances are symmetric at the two inputs (unlike many other designs), and, as a bonus, A2 also provides a complementary output. A3 raises the common-mode input impedance from approximately 7.5 k to approximately 70 k, reducing the degradation of CMRR due to mismatches in source impedance. C2 50pF R3 OUT+ C3 10k 50pF R6 R1 IN- IN+ R7 5.6k R2 5k A1 5k 1/2 R5 A2 5k ADA4075-2 R8 5.6k 5k 1/2 OUT- ADA4075-2 R4 10k A3* R9 R10 11k 11k *A3 REDUCES THE DEGRADATION OF CMRR (SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS). Figure 68. Balanced Line Receiver Rev. A | Page 19 of 24 07642-071 C1 22F (NON-POLAR) ADA4075-2 LOW NOISE PARAMETRIC EQUALIZER The circuit in Figure 69 is a reciprocal parametric equalizer yielding 20 dB of cut or boost with variable bandwidth and frequency. The frequency control range is 6.9:1, with the geometric mean center frequency conveniently occurring at the midpoint of the potentiometer setting. The center frequency is equal to 48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads. 47F 6.2k IN 6.2k The bandwidth control adjusts the Q from 0.9 to about 11. The overall noise is setting dependent, but with all controls centered, it is about -104 dBV in a 20 kHz bandwidth. Such a low noise level can obviate the need for a bypass switch in many applications. OUT 620 ADA4075-2 1/2 100 BOOST CUT BANDWIDTH 5k 1k 2.7k 1.5k ADA4075-2 1.5k C1* C2* 1/2 2.5k 2.5k 1.3k 2.5k 1.3k 1/2 2.5k 620 ADA4075-2 1/2 620 ADA4075-2 *THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2 (SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS). Figure 69. Low Noise Parametric Equalizer Rev. A | Page 20 of 24 07642-074 FREQUENCY (GANGED POTENTIOMETER) ADA4075-2 SCHEMATIC V+ +INA/ +INB OUTA/ OUTB V- Figure 70. Simplified Schematic Rev. A | Page 21 of 24 07642-072 -INA/ -INB ADA4075-2 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 4.00 (0.1574) 3.80 (0.1497) 8 1 5 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) 0.50 (0.0196) 0.25 (0.0099) 45 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-A A CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 71. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 0.30 0.25 0.18 2.00 BSC SQ 0.65 0.60 0.55 PIN 1 INDEX AREA 0.50 BSC 5 8 4 1 TOP VIEW 0.60 0.55 0.50 BOTTOM VIEW PIN 1 INDICATOR SEATING PLANE 0.20 REF 051608-A 0.05 MAX 0.02 NOM Figure 72. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD] 2 mm x 2 mm Body, Very Very Thin, Dual Lead (CP-8-6) Dimensions shown in millimeters ORDERING GUIDE Model ADA4075-2ARZ 1 ADA4075-2ARZ-R71 ADA4075-2ARZ-RL1 ADA4075-2ACPZ-R21 ADA4075-2ACPZ-R71 ADA4075-2ACPZ-RL1 1 Temperature Range -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C -40C to +125C Package Description 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead SOIC_N 8-Lead LFCSP_WD 8-Lead LFCSP_WD 8-Lead LFCSP_WD Z = RoHS Compliant Part. Rev. A | Page 22 of 24 Package Option R-8 R-8 R-8 CP-8-6 CP-8-6 CP-8-6 Branding A0 A0 A0 ADA4075-2 NOTES Rev. A | Page 23 of 24 ADA4075-2 NOTES (c)2008-2009 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07642-0-8/09(A) Rev. A | Page 24 of 24