Ultralow Noise Amplifier at Lower Power
ADA4075-2
Rev. A
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2008–2009 Analog Devices, Inc. All rights reserved.
FEATURES
Ultralow noise: 2.8 nV/√Hz at 1 kHz typical
Ultralow distortion: 0.0002% typical
Low supply current: 1.8 mA per amplifier typical
Offset voltage: 1 mV maximum
Bandwidth: 6.5 MHz typical
Slew rate: 12 V/μs typical
Unity-gain stable
Extended industrial temperature range
8-lead SOIC and 2 mm × 2 mm LFCSP packages
APPLICATIONS
Precision instrumentation
Professional audio
Active filters
Low noise amplifier front end
Integrators
PIN CONFIGURATIONS
OUTA 1
–INA 2
+INA 3
V– 4
V+8
OUTB7
–INB6
+INB
5
ADA4075-2
TOP VIEW
(Not to Scale)
0
7642-001
Figure 1. 8-Lead SOIC
07642-002
TOP VIEW
(Not to Scale)
ADA4075-2
3+INA
4V–
1OUTA
2–INA
6–INB
5+INB
8V+
7OUTB
Figure 2. 8-Lead, 2 mm × 2 mm LFCSP
GENERAL DESCRIPTION
The ADA4075-2 is a dual, high performance, low noise operational
amplifier combining excellent dc and ac characteristics on the
Analog Devices, Inc., iPolar® process. The iPolar process is an
advanced bipolar technology implementing vertical junction
isolation with lateral trench isolation. This allows for low noise
performance amplifiers in smaller die size at faster speed and
lower power. Its high slew rate, low distortion, and ultralow
noise make the ADA4075-2 ideal for high fidelity audio and
high performance instrumentation applications. It is also
especially useful for lower power demands, small enclosures,
and high density applications. The ADA4075-2 is specified for
the −40°C to +125°C temperature range and is available in a
standard SOIC package and a 2 mm × 2 mm LFCSP package.
Table 1. Low Noise Precision Op Amps
Supply 44 V 36 V 12 V to 16 V 5 V
Single OP27 AD8671 AD8665 AD8605
AD8675 OP162 AD8655
AD8597 AD8691
ADA4004-1
AD797
Dual OP275 AD8672 AD8666 AD8606
AD8676 OP262 AD8656
AD8599 AD8692
ADA4004-2
Quad AD8674 AD8668 AD8608
ADA4004-4 OP462 AD8694
ADA4075-2
Rev. A | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Pin Configurations ........................................................................... 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 5
Thermal Resistance ...................................................................... 5
Power Sequencing ........................................................................ 5
ESD Caution .................................................................................. 5
Typical Performance Characteristics ............................................. 6
Applications Information .............................................................. 16
Input Protection ......................................................................... 16
Total Harmonic Distortion ....................................................... 16
Phase Reversal ............................................................................ 16
DAC Output Filter...................................................................... 17
Balanced Line Driver ................................................................. 18
Balanced Line Receiver .............................................................. 19
Low Noise Parametric Equalizer .............................................. 20
Schematic ......................................................................................... 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 22
REVISION HISTORY
8/09—Rev. 0 to Rev. A
Added 8-Lead LFCSP_WD ............................................... Universal
Changes to Table 1 ............................................................................ 1
Changes to Table 2 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 and Table 5 ....................................................... 5
Changes to Figure 3, Figure 5, Figure 6, and Figure 8 ................. 6
Added Figure 4 and Figure 7; Renumbered Sequentially ........... 6
Added Figure 9 and Figure 12 ......................................................... 7
Changes to Figure 10, Figure 11, Figure 13, and Figure 14 ......... 7
Changes to Figure 16, Figure 17, Figure 19, and Figure 20 ......... 8
Changes to Figure 22 and Figure 25 ............................................... 9
Changes to Figure 36 ...................................................................... 11
Changes to Figure 54 ...................................................................... 14
Changes to and Moved Figure 57 and Figure 60 to ................... 15
Changes to Figure 59 and Figure 62 ............................................. 15
Changes to Input Protection Section and Phase
Reversal Section .............................................................................. 16
Changes to DAC Output Filter Section ....................................... 17
Changes to Figure 67 ...................................................................... 18
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
10/08—Revision 0: Initial Version
ADA4075-2
Rev. A | Page 3 of 24
SPECIFICATIONS
VSY = ±15 V, VCM = 0 V, TA = 25°C, SOIC package, unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.2 1 mV
−40°C ≤ TA ≤ +125°C 1.2 mV
Input Bias Current IB 30 100 nA
−40°C ≤ TA ≤ +125°C 150 nA
Input Offset Current IOS 5 50 nA
−40°C ≤ TA ≤ +125°C 75 nA
Input Voltage Range −40°C ≤ TA ≤ +125°C −12.5 +12.5 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 110 118 dB
−40°C ≤ TA ≤ +125°C 106 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = −11 V to +11 V 114 117 dB
−40°C ≤ TA ≤ +125°C 108 dB
R
L = 600 Ω, VO = −10 V to +10 V 112 117 dB
−40°C ≤ TA ≤ +125°C 106 dB
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 0.3 μV/°C
Input Resistance, Differential Mode RINDM 1.5 MΩ
Input Resistance, Common Mode RINCM 500 MΩ
Input Capacitance, Differential Mode CINDM 2.4 pF
Input Capacitance, Common Mode CINCM 2.1 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 2 kΩ to GND 12.8 13 V
−40°C ≤ TA ≤ +125°C 12.5 V
R
L = 600 Ω to GND 12.4 12.8 V
−40°C ≤ TA ≤ +125°C 12 V
V
SY = ±18 V, RL = 600 Ω to GND 15 15.8 V
−40°C ≤ TA ≤ +125°C 14 V
Output Voltage Low VOL R
L = 2 kΩ to GND −14 −13.6 V
−40°C ≤ TA ≤ +125°C −13 V
R
L = 600 Ω to GND −13.6 −13 V
−40°C ≤ TA ≤ +125°C −12.5 V
V
SY = ±18 V, RL = 600 Ω to GND −16.6 −16 V
−40°C ≤ TA ≤ +125°C −15 V
Short-Circuit Current ISC 40 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V 106 110 dB
−40°C ≤ TA ≤ +125°C 100 dB
Supply Current per Amplifier ISY V
SY = ±4.5 V to ±18 V, IO = 0 mA 1.8 2.25 mA
−40°C ≤ TA ≤ +125°C 3.35 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ, AV = 1 12 V/μs
Settling Time tS To 0.01%, VIN = 10 V step, RL = 1 kΩ 3 μs
Gain Bandwidth Product GBP RL = 1 MΩ, CL = 35 pF, AV = 1 6.5 MHz
Phase Margin ΦM R
L = 1 MΩ, CL = 35 pF, AV = 1 60 Degrees
T
HD + NOISE
Total Harmonic Distortion and Noise THD + N RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 1 kHz 0.0002 %
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz 60 nV p-p
Voltage Noise Density en f = 1 kHz 2.8 nV/√Hz
Current Noise Density in f = 1 kHz 1.2 pA/√Hz
ADA4075-2
Rev. A | Page 4 of 24
VSY = ±15 V, VCM = 0 V, TA = 25°C, LFCSP package, unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ Max Unit
INPUT CHARACTERISTICS
Offset Voltage VOS 0.3 1 mV
−40°C ≤ TA ≤ +125°C 1.5 mV
Input Bias Current IB 30 100 nA
−40°C ≤ TA ≤ +125°C 150 nA
Input Offset Current IOS 5 50 nA
−40°C ≤ TA ≤ +125°C 75 nA
Input Voltage Range −40°C ≤ TA ≤ +125°C −12.5 +12.5 V
Common-Mode Rejection Ratio CMRR VCM = −12.5 V to +12.5 V 110 116 dB
−40°C ≤ TA ≤ +125°C 106 dB
Large Signal Voltage Gain AVO R
L = 2 kΩ, VO = −11 V to +11 V 110 117 dB
−40°C ≤ TA ≤ +125°C 102 dB
R
L = 600 Ω, VO = −10 V to +10 V 108 117 dB
−40°C ≤ TA ≤ +125°C 100 dB
Offset Voltage Drift ∆VOS/∆T −40°C ≤ TA ≤ +125°C 3 μV/°C
Input Resistance, Differential Mode RINDM 1.5 MΩ
Input Resistance, Common Mode RINCM 500 MΩ
Input Capacitance, Differential Mode CINDM 2.4 pF
Input Capacitance, Common Mode CINCM 2.1 pF
OUTPUT CHARACTERISTICS
Output Voltage High VOH R
L = 2 kΩ to GND 12.8 13 V
−40°C ≤ TA ≤ +125°C 12.5 V
R
L = 600 Ω to GND 12.4 12.8 V
−40°C ≤ TA ≤ +125°C 12 V
V
SY = ±18 V, RL = 600 Ω to GND 15 15.8 V
−40°C ≤ TA ≤ +125°C 14 V
Output Voltage Low VOL R
L = 2 kΩ to GND −14 −13.6 V
−40°C ≤ TA ≤ +125°C −13 V
R
L = 600 Ω to GND −13.6 −13 V
−40°C ≤ TA ≤ +125°C −12.5 V
V
SY = ±18 V, RL = 600 Ω to GND −16.6 −16 V
−40°C ≤ TA ≤ +125°C −15 V
Short-Circuit Current ISC 40 mA
Closed-Loop Output Impedance ZOUT f = 1 kHz, AV = 1 0.1 Ω
POWER SUPPLY
Power Supply Rejection Ratio PSRR VSY = ±4.5 V to ±18 V 100 104 dB
−40°C ≤ TA ≤ +125°C 95 dB
Supply Current per Amplifier ISY V
SY = ±4.5 V to ±18 V, IO = 0 mA 1.8 2.25 mA
−40°C ≤ TA ≤ +125°C 3.35 mA
DYNAMIC PERFORMANCE
Slew Rate SR RL = 2 kΩ, AV = 1 12 V/μs
Settling Time tS To 0.01%, VIN = 10 V step, RL = 1 kΩ 3 μs
Gain Bandwidth Product GBP RL = 1 MΩ, CL = 35 pF, AV = 1 6.5 MHz
Phase Margin ΦM R
L = 1 MΩ, CL = 35 pF, AV = 1 60 Degrees
THD + NOISE
Total Harmonic Distortion and Noise THD + N RL = 2 kΩ, AV = 1, VIN = 3 V rms, f = 1 kHz 0.0002 %
NOISE PERFORMANCE
Voltage Noise en p-p f = 0.1 Hz to 10 Hz 60 nV p-p
Voltage Noise Density en f = 1 kHz 2.8 nV/√Hz
Current Noise Density in f = 1 kHz 1.2 pA/√Hz
ADA4075-2
Rev. A | Page 5 of 24
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 4.
Parameter Rating
Supply Voltage ±20 V
Input Voltage ±VSY
Input Current1 ±10 mA
Differential Input Voltage ±1.2 V
Output Short-Circuit Duration to GND Indefinite
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +125°C
Junction Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 60 sec) 300°C
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages. This
was measured using a standard 4-layer board.
Table 5. Thermal Resistance
Package Type θJA θ
JC Unit
8-Lead SOIC 158 43 °C/W
8-Lead LFCSP 115 40 °C/W
POWER SEQUENCING
The op amp supplies must be established simultaneously with,
or before, any input signals are applied. If this is not possible,
limit the input current to 10 mA.
1 The input pins have clamp diodes to the power supply pins.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
ADA4075-2
Rev. A | Page 6 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, unless otherwise noted.
0
50
100
150
200
250
–1.0 –0.5 0 0.5 1.0
VSY = ±15V
VCM = 0V
BASED ON 600 OP AMPS
SOIC PACKAGE
07642-003
VOS (mV)
NUMBER OF AMPLIFIERS
Figure 3. Input Offset Voltage Distribution
0
20
40
60
80
100
–1.0 –0.5 0 0.5 1.0
V
SY
= ±15V
V
CM
= 0V
BASED ON 300 OP AMPS
LFCSP PACKAGE
07642-040
V
OS
(mV)
NUMBER OF AMPLIFIERS
Figure 4. Input Offset Voltage Distribution
0
10
20
30
40
50
60
70
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
V
SY
= ±15V
–40°C T
A
+125°C
BASED ON 200 OP AMPS
SOIC PACKAGE
07642-004
TCV
OS
(V/°C)
NUMBER OF AMPLIFIERS
Figure 5. Input Offset Voltage Drift Distribution
0
50
100
150
200
250
–1.0 –0.5 0 0.5 1.0
V
SY
= ±5V
V
CM
= 0V
BASED ON 600 OP AMPS
SOIC PACKAGE
07642-006
V
OS
(mV)
NUMBER OF AMPLIFIERS
Figure 6. Input Offset Voltage Distribution
0
20
40
60
80
100
–1.0 –0.5 0 0.5 1.0
V
SY
= ±5V
V
CM
= 0V
BASED ON 300 OP AMPS
LFCSP PACKAGE
07642-042
V
OS
(mV)
NUMBER OF AMPLIFIERS
Figure 7. Input Offset Voltage Distribution
0
10
20
30
40
50
60
80
70
–2.0 –1.6 –1.2 –0.8 –0.4 0 0.4 0.8 1.2 1.6 2.0
07642-007
TCV
OS
(V/°C)
V
SY
= ±5V
–40°C T
A
+125°C
BASED ON 200 OP AMPS
SOIC PACKAGE
NUMBER OF AMPLIFIERS
Figure 8. Input Offset Voltage Drift Distribution
ADA4075-2
Rev. A | Page 7 of 24
40
35
30
25
20
15
10
5
0
01 23456 78
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
07642-043
V
SY
= ±15V
V
CM
= 0V
BASED ON 300 OP AMPS
LFCSP PACKAGE
Figure 9. Input Offset Voltage Drift Distribution
–300
–200
–100
0
100
200
300
–15 –10 –5 0 5 10 15
V
SY
= ±15V
BASED ON 60 OP AMPS
07642-005
V
CM
(V)
V
OS
(V)
Figure 10. Input Offset Voltage vs. Common-Mode Voltage
07642-009
TEMPERATURE (°C)
I
B
(nA)
0
20
40
60
80
–50 –25 0 25 50 75 100 125
V
SY
= ±15V
Figure 11. Input Bias Current vs. Temperature
40
35
30
25
20
15
10
5
0
012345678
TCV
OS
(µV/°C)
NUMBER OF AMPLIFIERS
07642-052
V
SY
= ±5V
V
CM
= 0V
BASED ON 300 OP AMPS
LFCSP PACKAGE
Figure 12. Input Offset Voltage Drift Distribution
–5 –4 –3 –2 –1 0 1 2 3 4 5
–300
–200
–100
0
100
200
300
07642-008
V
CM
(V)
V
OS
(V)
V
SY
= ±5V
BASED ON 60 OP AMPS
Figure 13. Input Offset Voltage vs. Common-Mode Voltage
07642-012
TEMPERATURE (°C)
I
B
(nA)
0
20
40
60
100
80
–50 –25 0 25 50 75 100 125
V
SY
= ±5V
Figure 14. Input Bias Current vs. Temperature
ADA4075-2
Rev. A | Page 8 of 24
0
10
20
30
40
50
60
–15 –10 –5 0 5 10 15
07642-047
V
CM
(V)
I
B
(nA)
V
SY
= ±15V
Figure 15. Input Bias Current vs. Input Common-Mode Voltage
07642-010
LOAD CURRENT (mA)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0.1
1
10
0.001 0.01 0.1 1 10 100
V+ – VOH
VOL – V–
VSY = ±15V
Figure 16. Output Voltage to Supply Rail vs. Load Current
07642-011
TEMPERATURE (°C)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0
0.5
1.0
1.5
2.0
2.5
–50 –25 0 25 50 75 100 125
VOL – V–
V+ – VOH
VSY = ±15V
RL = 2k
Figure 17. Output Voltage to Supply Rail vs. Temperature
–4–3–2–101234
0
10
20
30
40
50
60
07642-049
V
CM
(V)
I
B
(nA)
V
SY
= ±5V
Figure 18. Input Bias Current vs. Input Common-Mode Voltage
07642-013
LOAD CURRENT (mA)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0.1
1
10
0.001 0.01 0.1 1 10 100
V+ – V
OH
V
SY
= ±5V
V
OL
– V–
Figure 19. Output Voltage to Supply Rail vs. Load Current
07642-014
TEMPERATURE (°C)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
0
0.5
1.0
1.5
2.0
–50 –25 0 25 50 75 100 125
V+ – V
OH
V
OL
– V–
V
SY
= ±5V
R
L
= 2k
Figure 20. Output Voltage to Supply Rail vs. Temperature
ADA4075-2
Rev. A | Page 9 of 24
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
PHASE (Degrees)
GAIN
PHASE
1k 10k 100k 1M 10M 100M
07642-015
FREQUENCY (Hz)
GAIN (dB)
V
SY
= ±15V
Figure 21. Open-Loop Gain and Phase vs. Frequency
07642-117
50
–20
–10
0
10
20
30
40
10 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
A
V
= +100
V
SY
= ±15V
A
V
= +10
A
V
= +1
Figure 22. Closed-Loop Gain vs. Frequency
A
V
= +1
A
V
= +10
A
V
= +100
10 100 1k 10k 100k 1M 10M
07642-017
FREQUENCY (Hz)
Z
OUT
()
V
SY
= ±15V
0.001
0.01
0.1
1
10
100
1k
Figure 23. Output Impedance vs. Frequency
0
20
40
60
80
100
120
140
–80
–60
–40
–20
–80
–100–100
–60
–40
–20
0
20
40
60
80
100
120
140
PHASE (Degrees)
GAIN
PHASE
1k 10k 100k 1M 10M 100M
07642-018
FREQUENCY (Hz)
GAIN (dB)
V
SY
= ±5V
Figure 24. Open-Loop Gain and Phase vs. Frequency
07642-120
50
–20
–10
0
10
20
30
40
10 100 1k 10k 100k 1M 10M 100M
GAIN (dB)
FREQUENCY (Hz)
A
V
= +100
V
SY
= ±5V
A
V
= +10
A
V
= +1
Figure 25. Closed-Loop Gain vs. Frequency
10 100 1k 10k 100k 1M 10M
07642-020
FREQUENCY (Hz)
ZOUT ()
A
V
= +1
A
V
= +10
A
V
= +100
V
SY
= ±5V
0.001
0.01
0.1
1
10
100
1k
Figure 26. Output Impedance vs. Frequency
ADA4075-2
Rev. A | Page 10 of 24
0
20
40
60
80
100
120
140
100 1k 10k 100k 1M 10M
V
SY
= ±15V
07642-021
FREQUENCY (Hz)
CMRR (dB)
Figure 27. CMRR vs. Frequency
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
PSRR+ PSRR–
0
7642-022
FREQUENCY (Hz)
PSRR (dB)
V
SY
= ±15V
Figure 28. PSRR vs. Frequency
0
5
10
15
20
25
30
35
40
10 100 1000
07642-023
CAPACITANCE (pF)
OVERSHOOT (%)
V
SY
= ±15V
A
V
= +1
R
L
= 2k
Figure 29. Small Signal Overshoot vs. Load Capacitance
0
20
40
60
80
100
120
140
100 1k 10k 100k 1M 10M
07642-024
FREQUENCY (Hz)
CMRR (dB)
V
SY
= ±5V
Figure 30. CMRR vs. Frequency
–20
0
20
40
60
80
100
120
10 100 1k 10k 100k 1M 10M 100M
07642-025
FREQUENCY (Hz)
PSRR (dB)
PSRR+ PSRR–
VSY = ±5V
Figure 31. PSRR vs. Frequency
0
5
10
15
20
25
30
35
40
10 100 1000
07642-026
CAPACITANCE (pF)
OVERSHOOT (%)
V
SY
= ±5V
A
V
= +1
R
L
= 2k
Figure 32. Small Signal Overshoot vs. Load Capacitance
ADA4075-2
Rev. A | Page 11 of 24
V
SY
= ±15V
V
IN
= 20V p-p
A
V
= +1
R
L
= 2k
C
L
= 100pF
07642-027
TIME (4µs/DIV)
VOLTAGE (5V/DIV)
0V
Figure 33. Large Signal Transient Response
V
SY
= ±15V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 2k
C
L
= 100pF
07642-028
TIME (10µs/DIV)
VOLTAGE (20mV/DIV)
0V
Figure 34. Small Signal Transient Response
0
2
4
–20
–15
–10
–5
0
VSY = ±15V
INPUT
OUTPUT
07642-029
TIME (1µs/DIV)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 35. Negative Overload Recovery
V
SY
= ±5V
V
IN
= 7V p-p
A
V
= +1
R
L
= 2k
C
L
= 100pF
07642-030
TIME (4µs/DIV)
VOLTAGE (2V/DIV)
0V
Figure 36. Large Signal Transient Response
V
SY
= ±5V
V
IN
= 100mV p-p
A
V
= +1
R
L
= 2k
C
L
= 100pF
07642-031
TIME (10µs/DIV)
VOLTAGE (20mV/DIV)
0V
Figure 37. Small Signal Transient Response
–8
–6
–4
–2
0
0
2
4
V
SY
= ±5V
INPUT
OUTPUT
07642-032
TIME (1µs/DIV)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
Figure 38. Negative Overload Recovery
ADA4075-2
Rev. A | Page 12 of 24
–2
0
2
4
V
SY
= ±15V
INPUT
OUTPUT
07642-033
TIME (1µs/DIV)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–10
–5
0
5
10
15
Figure 39. Positive Overload Recovery
07642-061
INPUT
VOLTAGE (5V/DIV)
TIME (2µs/DIV)
OUTPUT
V
SY
= ±15V
–10mV
+10mV
0V
ERROR BAND
Figure 40. Positive Settling Time to 0.01%
0
7642-064
INPUT
OUTPUT
V
SY
= ±15V
–10mV
+10mV
0V
VOLTAGE (5V/DIV)
TIME (2µs/DIV)
ERROR BAND
Figure 41. Negative Settling Time to 0.01%
–2
0
2
4
V
SY
= ±5V
INPUT
OUTPUT
07642-034
TIME (1µs/DIV)
INPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
–4
–2
0
2
4
Figure 42. Positive Overload Recovery
07642-062
INPUT
OUTPUT
V
SY
= ±5V
–6mV
+6mV
0V
VOLTAGE (5V/DIV)
TIME (2µs/DIV)
ERROR BAND
Figure 43. Positive Settling Time to 0.01%
07642-063
INPUT
OUTPUT
V
SY
= ±5V
–6mV
+6mV
0V
VOLTAGE (5V/DIV)
TIME (2µs/DIV)
ERROR BAND
Figure 44. Negative Settling Time to 0.01%
ADA4075-2
Rev. A | Page 13 of 24
1
10
1 10 100 1k 10k 100k
0
7642-035
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/Hz)
V
SY
= ±15V
Figure 45. Voltage Noise Density
1 10 100 1k 10k 100k
07642-045
FREQUENCY (Hz)
CURRENT NOISE DENSITY (pA/ Hz)
0.1
1
10
CORRELATED
R
S1
= R
S2
UNCORRELATED
R
S1
= 0
V
SY
= ±15V R
S1
R
S2
Figure 46. Current Noise Density
INPUT NOISE VOLTAGE (10nV/DIV)
07642-036
TIME (1s/DIV)
V
SY
= ±15V
Figure 47. 0.1 Hz to 10 Hz Noise
1
10
1 10 100 1k 10k 100k
07642-038
FREQUENCY (Hz)
VOLTAGE NOISE DENSITY (nV/Hz)
V
SY
= ±5V
Figure 48. Voltage Noise Density
1 10 100 1k 10k 100k
07642-046
FREQUENCY (Hz)
CURRENT NOISE DENSITY (pA/ Hz)
0.1
1
10
CORRELATED
R
S1
= R
S2
UNCORRELATED
R
S1
= 0
V
SY
= ±5V R
S1
R
S2
Figure 49. Current Noise Density
INPUT NOISE VOLTAGE (10nV/DIV)
07642-039
TIME (1s/DIV)
V
SY
= ±5V
Figure 50. 0.1 Hz to 10 Hz Noise
ADA4075-2
Rev. A | Page 14 of 24
2
4
6
8
4 6 8 1012141618
0
07642-048
SUPPLY VOLTAGE (±V)
SUPPLY CURRENT (mA)
+125°C
+85°C
+25°C
–40°C
Figure 51. Supply Current vs. Supply Voltage
V
SY
= ±15V
f = 1kHz
600
2k
0.00001
0.0001
0.001
0.01
0.1
1
10
0.0001 0.001 0.01 0.1 1 10
07642-058
AMPLITUDE (V rms)
THD + NOISE (%)
Figure 52. THD + Noise vs. Amplitude
100 1k 10k
V
SY
= ±15V
V
IN
= 3V rms
600
2k
0.0001
0.001
0.01
0.1
1
10 100k
07642-060
FREQUENCY (Hz)
THD + NOISE (%)
Figure 53. THD + Noise vs. Frequency
0
1
2
3
4
5
6
–50 –25 0 25 50 75 100 125
07642-057
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
V
SY
= ±15V
V
SY
= ±5V
Figure 54. Supply Current vs. Temperature
0.00001
0.0001
0.001
0.01
0.1
1
10
0.0001 0.001 0.01 0.1 1 10
07642-065
AMPLITUDE (V rms)
THD + NOISE (%)
VSY = ±5V
f = 1kHz
600
2k
Figure 55. THD + Noise vs. Amplitude
0.0001
0.001
0.01
0.1
1
10 100 1k 10k 100k
07642-067
FREQUENCY (Hz)
THD + NOISE (%)
V
SY
= ±5V
V
IN
= 1.5V rms
600
2k
Figure 56. THD + Noise vs. Frequency
ADA4075-2
Rev. A | Page 15 of 24
–140
–120
–100
–80
–60
–40
–20
0
100 1k 10k 100k
07642-041
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
V
SY
= ±15V
V
IN
= 10V p-p
R
L
= 2k
R
L
100k
1k
Figure 57. Channel Separation vs. Frequency
V
SY
= ±18V
f = 1kHz
600
2k
0.00001
0.0001
0.001
0.01
0.1
1
10
0.0001 0.001 0.01 0.1 1 10 100
07642-056
AMPLITUDE (V rms)
THD + NOISE (%)
Figure 58. THD + Noise vs. Amplitude
0
0.5
1.0
1.5
2.0
2.5
–50 –25 0 25 50 75 100 125
07642-066
TEMPERATURE (°C)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
V+ – V
OH
V
OL
– V–
V
SY
= ±18V
R
L
= 2k
Figure 59. Output Voltage to Supply Rail vs. Temperature
–140
–120
–100
–80
–60
–40
–20
0
100 1k 10k 100k
07642-044
FREQUENCY (Hz)
CHANNEL SEPARATION (dB)
V
SY
= ±5V
V
IN
= 5V p-p
R
L
= 2k
R
L
100k
1k
Figure 60. Channel Separation vs. Frequency
10 100 1k 10k 100k
V
SY
= ±18V
V
IN
= 8V rms
6002k
0.00001
0.0001
0.001
0.01
0.1
1
07642-059
FREQUENCY (Hz)
THD + NOISE (%)
Figure 61. THD + Noise vs. Frequency
0.1
1
10
0.001 0.01 0.1 1 10 100
07642-068
LOAD CURRENT (mA)
OUTPUT VOLTAGE TO SUPPLY RAIL (V)
V
SY
= ±18V
V+ – V
OH
V
OL
– V–
Figure 62. Output Voltage to Supply Rail vs. Load Current
ADA4075-2
Rev. A | Page 16 of 24
APPLICATIONS INFORMATION
INPUT PROTECTION
To prevent base-emitter junction breakdown from occurring in
the input stage of the ADA4075-2 when a very large differential
voltage is applied, the inputs are clamped by the internal diodes
to ±1.2 V. To preserve the ultralow voltage noise feature of the
ADA4075-2, the commonly used internal current-limiting
resistors in series with the inputs are not used.
In small signal applications, current limiting is not required;
however, in applications where the differential voltage of the
ADA4075-2 exceeds ±1.2 V, large currents may flow through
these diodes. Employ external current-limiting resistors as
shown in Figure 63 to reduce the input currents to less than
±10 mA. Note that depending on the value of these resistors,
the total voltage noise will most likely be degraded. For example,
a 1 k resistor at room temperature has a thermal noise of
4 nV/√Hz, whereas the ADA4075-2 has an ultralow voltage
noise of only 2.8 nV/√Hz typical.
R2
R1
3
2
1
ADA4075-2
07642-050
Figure 63. Input Protection
TOTAL HARMONIC DISTORTION
The total harmonic distortion + noise (THD + N) of the
ADA4075-2 is 0.0002% typical with a load resistance of 2 kΩ.
Figure 64 shows the performance of the ADA4075-2 driving a
2 kΩ load with supply voltages of ±4 V and ±15 V. Notice that
there is more distortion for the supply voltage of ±4 V than for a
supply voltage of ±15 V. Therefore, it is important to operate the
ADA4075-2 at a supply voltage greater than ±5 V for optimum
distortion. The THD + noise graphs for supply voltages of ±5 V
and ±18 V are available in Figure 56 and Figure 61.
0.0001
0.001
0.01
0.1
1
10 100 1k 10k 100k
07642-069
FREQUENCY (Hz)
THD + NOISE (%)
V
SY
= ±4V
R
L
= 2k
V
IN
= 1.5V rms
V
SY
= ±15V
R
L
= 2k
V
IN
= 3V rms
Figure 64. THD + Noise vs. Frequency
PHASE REVERSAL
An undesired phenomenon, phase reversal (also known as phase
inversion) occurs in many op amps when one or both of the
inputs are driven beyond the specified input common-mode
voltage (VICM) range, in effect reversing the polarity of the output.
In some cases, phase reversal can induce lockups and cause
equipment damage as well as self destruction.
The ADA4075-2 incorporates phase reversal prevention circuitry
that clamps the output to 2 V typical from the supply rails when
one or both inputs exceed the VICM range. Figure 65 shows the
input/output waveforms of the ADA4075-2 configured as a unity-
gain buffer for a supply voltage of ±15 V.
07642-053
V
IN
V
OUT
VOLTAGE (5V/DIV)
TIME (40µs/DIV)
V
SY
= ±15V
Figure 65. No Phase Reversal
ADA4075-2
Rev. A | Page 17 of 24
DAC OUTPUT FILTER
The ultralow voltage noise, low distortion, and high slew rate of
the ADA4075-2 make it an ideal choice for professional audio
signal processing. Figure 66 shows the ADA4075-2 used in a
typical audio DAC output filter configuration. The differential
outputs of the DAC are fed into the ADA4075-2. The ADA4075-2
is configured as a differential Sallen-Key filter. It operates as an
external low-pass filter to remove high frequency noise present
on the output pins of the DAC. It also provides differential-to-
single-ended conversion from the differential outputs of the DAC.
For a DAC output filter, an op amp with reasonable slew rate and
bandwidth is required. The ADA4075-2 has a high slew rate of the
12 V/µs and a relatively wide bandwidth of 6.5 MHz. The cutoff
frequency of the low-pass filter is approximately 167 kHz. In
addition, the 100 kΩ − 47 µF RC network provides ac coupling
to block out the dc components at the output.
07642-054
OUTPUT
DAC OUTN
DAC OUTP
11k
11k
5.62k1.5k
3.01k
100
5.62k
100k
2.2nF
150pF270pF560pF
68pF
47µF
ADA4075-2
1/2
+
Figure 66. Typical DAC Output Filter Circuit (Differential)
ADA4075-2
Rev. A | Page 18 of 24
BALANCED LINE DRIVER
The circuit of Figure 67 shows a balanced line driver designed
for audio use. Such drivers are intended to mimic an output
transformer in operation, whereby the common-mode voltage
can be impressed by the load. Furthermore, either output can be
shorted to ground in single-ended applications without affecting
the overall operation.
Circuits of this type use positive and negative feedback to obtain a
high common-mode output impedance, and they are somewhat
notorious for component sensitivity and susceptibility to latch-up.
This circuit uses several techniques to avoid spurious behavior.
First, the 4-op-amp arrangement ensures that the input impedance
is load independent (the input impedance can become negative
with some configurations). Note that the output op amps are
packaged with the input op amps to maximize drive capability.
Second, the positive feedback is ac-coupled by C2 and C3, which
eliminates the need for offset trim. Because the circuit is ac-coupled
at the input, these capacitors do not have significant dc voltage
across them, thus tantalum types of capacitors can be used.
Finally, even with these precautions, it is vital that the positive
feedback be accurately controlled. This is partly achieved by
using 1% resistors. In addition, the following setup procedure
ensures that the positive feedback does not become excessive:
1. Set R11 to its midposition (or short the ends together,
whichever is easier) and temporarily short the negative
output to ground.
2. Apply a 10 V p-p sine wave at approximately 1 kHz to the
input and adjust R7 to provide 930 mV p-p at TEST (see
Figure 67).
3. Remove the short from the negative output (and across
R11, if used) and adjust R11 until the output waveforms
are symmetric.
The overall gain of the driver is equal to 2, which provides an
extra 6 dB of headroom in balanced differential mode. The
output noise is about −109 dBV in a 20 kHz bandwidth.
07642-073
C3
10µF
R2
4.7k
OUT+
OUT–
1/2
ADA4075-2
R5
4.7k
R6
4.7k
R7
250R8
100
R9
4.7k
R13
100
R4
4.7k
A2
1/2
ADA4075-2
A1
IN
C5
50pF
C1
10µF
C2
10µF
TEST
SYMMETRY
TRIM
FEEDBACK
TRIM
1/2
ADA4075-2
R12
4.7k
R11
250
R17
4.7k
R16
100
R10
4.7k
R15
4.7k
A4
C6
50pF
1/2
ADA4075-2
A3
C4
50pF
R14
100
R1
10k
NOTES
1. ALL RESISTORS SHOULD HAVE 1% TOLERANCE.
2. A1/A2 IN SAME PACKAGE; A3/A4 IN SAME PACKAGE.
R3
4.7k
R18
4.7k
Figure 67. Balanced Line Driver
ADA4075-2
Rev. A | Page 19 of 24
BALANCED LINE RECEIVER
Figure 68 depicts a unity-gain balanced line receiver capable of
a high degree of hum rejection. The CMRR is approximately
given by
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
×
×
R3R2
R4R1
10
log20
Therefore, R1 to R4 should be close tolerance components to
obtain the best possible CMRR without adjustment. The presence
of A2 ensures that the impedances are symmetric at the two inputs
(unlike many other designs), and, as a bonus, A2 also provides
a complementary output. A3 raises the common-mode input
impedance from approximately 7.5 k to approximately 70 k,
reducing the degradation of CMRR due to mismatches in source
impedance.
Note that A3 is not in the signal path, and almost any op amp
works well here. Although it may seem as though the inverting
output should be noisier than the noninverting one, they are in
fact symmetric at about −111 dBV (20 kHz bandwidth).
Sometimes an overall gain of ½ is desired to provide an extra
6 dB of differential input headroom. This can be attained by
reducing R3 and R4 to 5 k and increasing R9 to 22 k.
R5
5kOUT–
OUT+
IN–
*A3 REDUCES THE DEGRADATION OF CMRR
(SEE THE BALANCED LINE RECEIVER SECTION FOR MORE DETAILS).
C1
22µF
(NON-POLAR)
IN+
07642-071
R4
10k
1/2
ADA4075-2
R3
10k
R6
5k
R1
5k
R2
5k
C2
50pF
R9
11k
A3*
R8
5.6k
R7
5.6k
1/2
A1
A2
ADA4075-2
C3
50pF
R10
11k
Figure 68. Balanced Line Receiver
ADA4075-2
Rev. A | Page 20 of 24
LOW NOISE PARAMETRIC EQUALIZER
The circuit in Figure 69 is a reciprocal parametric equalizer
yielding ±20 dB of cut or boost with variable bandwidth and
frequency. The frequency control range is 6.9:1, with the geometric
mean center frequency conveniently occurring at the midpoint
of the potentiometer setting. The center frequency is equal to
48 Hz/Ct, where Ct is the value of C1 and C2 in microfarads.
The bandwidth control adjusts the Q from 0.9 to about 11. The
overall noise is setting dependent, but with all controls centered,
it is about −104 dBV in a 20 kHz bandwidth. Such a low noise
level can obviate the need for a bypass switch in many applications.
07642-074
1/2
C2*
100
1k
BANDWIDTH
*THE CENTER FREQUENCY IS AFFECTED BY THE VALUE OF C1 AND C2
(SEE THE LOW NOISE PARAMETRIC EQUALIZER SECTION FOR MORE DETAILS).
1.3k
1/2
1/2
C1*
2.5k
620
2.5k
620
1.5k
1.3k
2.5k
1/2
ADA4075-2
ADA4075-2
ADA4075-2ADA4075-2
6.2k6.2k
47µF
5k
BOOST CUT
1.5k
IN OUT
2.5k
2.7k
620
FREQUENCY (GANGED POTENTIOMETER)
Figure 69. Low Noise Parametric Equalizer
ADA4075-2
Rev. A | Page 21 of 24
SCHEMATIC
07642-072
–INA/
–INB
+INA/
+INB
OUTA/
OUTB
V
+
V–
Figure 70. Simplified Schematic
ADA4075-2
Rev. A | Page 22 of 24
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-A A
012407-A
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099) 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
4
1
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2441)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
Figure 71. 8-Lead Standard Small Outline Package [SOIC_N]
Narrow Body (R-8)
Dimensions shown in millimeters and (inches)
051608-A
TOP VIEW
8
1
5
4
0.30
0.25
0.18
BOTTOM VIEW
PIN 1 INDEX
AREA
2.00
BSC SQ
SEATING
PLANE
0.60
0.55
0.50
0.20 REF
0.05 MAX
0.02 NOM
0.65
0.60
0.55
0.50 BSC
PIN 1
INDICATOR
Figure 72. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
2 mm × 2 mm Body, Very Very Thin, Dual Lead
(CP-8-6)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
ADA4075-2ARZ1 −40°C to +125°C 8-Lead SOIC_N R-8
ADA4075-2ARZ-R71 −40°C to +125°C 8-Lead SOIC_N R-8
ADA4075-2ARZ-RL1 −40°C to +125°C 8-Lead SOIC_N R-8
ADA4075-2ACPZ-R21 −40°C to +125°C 8-Lead LFCSP_WD CP-8-6 A0
ADA4075-2ACPZ-R71 −40°C to +125°C 8-Lead LFCSP_WD CP-8-6 A0
ADA4075-2ACPZ-RL1 −40°C to +125°C 8-Lead LFCSP_WD CP-8-6 A0
1 Z = RoHS Compliant Part.
ADA4075-2
Rev. A | Page 23 of 24
NOTES
ADA4075-2
Rev. A | Page 24 of 24
NOTES
©2008–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07642-0-8/09(A)
