A-Data ADBDB1916 Revision History Revision 1 ( Dec. 2001 ) 1.Fister release. Revision 2 ( Apr. 2002 ) 1. Changed module current specification. 2. Add Performance range. 3. Changed AC Characteristics. 4. Changed typo size on module PCB in package dimensions. Rev 2 Apr. 2002 1 A-Data ADBDB1916 DDR SDRAM 184pin DIMM 64Mx64bits DDR SDRAM 184pin DIMM based on 32Mx8 General Description Features The ADBDB1916 is 64Mx64 bits Double Data Rate SDRAM Modules, The modules are composed of sixteen 32Mx8 bits CMOS Double Data Rate SDRAMs in TSOP-II 400mil 66pin package and one 2Kbit EEPROM in 8pin TSSOP(TSOP) package on a 184pin glass-epoxy printed circuit board. The A-Data is a Dual In-line Memory Module and is intended for mounting onto 184-pins edge connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable latencies and burst lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. *DLL aligns DQ and DQS transition with CK transition *Double-data-rate architecture. *Bi-directional data strobe (DQS) *Differential clock inputs(CK and /CK) *Auto refresh and self refresh *8192 refresh cycles / 64ms *Power supply: Vdd,Vddq:2.5V0.2V *Programmable Burst length (2,4,8) *Serial Presence Detect with EEPROM *Module bank : two physical bank *PCB : BUDA84A,Height (29.21mm),double sided component, Six layers Performance range Part No. ADBDB1916 Max Freq. Interface 166MHz SSTL_2 Pin Assignment FRONT SIDE BACK SIDE PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME PIN NAME 1 2 3 4 5 6 VREF 24 DQ17 47 DQS8 70 DQ0 25 DQS2 48 A0 71 VSS DQ1 VDD /CS2 93 94 VSS DQ4 116 VSS 139 VSS 117 DQ21 140 DM8 A11 DM2 141 142 A10 CB6 162 DQ47 163 /CS3 26 27 VSS A9 49 50 CB2 VSS 72 73 DQ48 DQ49 95 DQ5 118 96 VDDQ 119 164 VDDQ 165 DQ52 DQS0 28 DQ2 29 DQ18 A7 51 52 CB3 BA1 74 75 VSS /CK2 97 98 DM0 DQ6 120 VDD 143 VDDQ 166 DQ53 121 DQ22 144 CB7 167 NC 30 VDDQ 53 DQ32 76 CK2 99 31 DQ19 54 VDDQ 77 VDDQ 100 DQ7 VSS 122 A8 145 VSS 168 VDD 123 DQ23 146 DQ36 169 DM6 NC NC 124 125 7 8 VDD DQ3 9 10 NC NC 32 33 A5 DQ24 55 DQ33 78 DQS6 101 56 DQS4 79 DQ50 102 11 12 VSS DQ8 34 35 VSS DQ25 57 58 DQ34 VSS 80 81 13 DQ9 36 DQS3 59 14 DQS1 37 A4 60 BA0 DQ35 82 VDDID 105 DQ12 128 VDDQ 151 DQ39 174 DQ60 83 DQ56 106 DQ13 129 DM3 152 VSS 175 DQ61 VSS A6 147 DQ37 170 DQ54 148 VDD 171 DQ55 DQ51 103 A13 126 DQ28 149 DM4 172 VDDQ VSS 104 VDDQ 127 DQ29 150 DQ38 173 NC 15 VDDQ 38 16 CK1 39 VDD DQ26 61 DQ40 84 62 VDDQ 85 17 18 /CK1 VSS 40 41 DQ27 A2 63 64 /WE DQ41 86 DQS7 109 DQ14 132 VSS 155 DQ45 178 DQ62 87 DQ58 110 DQ15 133 DQ31 156 VDDQ 179 DQ63 19 20 DQ10 DQ11 42 43 VSS A1 65 66 /CAS VSS 88 89 21 CKE0 44 22 VDDQ 45 CB0 CB1 67 DQS5 90 68 DQ42 91 NC SDA 113 BA2 136 VDDQ 159 DM5 114 DQ20 137 CK0 160 VSS 23 VDD 69 SCL 115 DQ16 46 Rev 2 Apr. 2002 DQ43 92 DQ57 107 DM1 130 A3 153 DQ44 176 VSS VDD 108 VDD 131 DQ30 154 /RAS 177 DM7 DQ59 111 CKE1 134 VSS 112 VDDQ 135 2 A12 CB4 CB5 157 /CS0 180 VDDQ 158 /CS1 181 SA0 182 183 SA1 SA2 138 /CK0 161 DQ46 184 VDDS A-Data ADBDB1916 Pin Description PIN NAME CK0~2,/CK0~2 System Clock CKE0~1 Clock Enable FUNCTION Active on the positive edge to sample all inputs. Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least on cycle prior new command. Disable input buffers for power down in standby /CS0~3 Chip Select Disables or Enables device operation by masking or enabling all input except CK, CKE and L(U)DQM A0~A12 BA0~BA1 Address Row / Column address are multiplexed on the same pins. Banks Select Selects bank to be activated during row address latch time. Selects bank for read / write during column address latch time. DQ0~DQ63 Data DQS0~DQS7 Data Strobe DQM0~7 Data inputs / outputs are multiplexed on the same pins. Bi-directional Data Strobe Data Mask Makes data output Hi-Z, /RAS Row Address Strobe Latches row addresses on the positive edge of the CLK with /RAS low /CAS Column Address Strobe Latches Column addresses on the positive edge of the CLK with /CAS low /WE Write Enable Enables write operation and row recharge. Power Supply/Ground Power and Ground for the input buffers and the core logic. VDDQ Power Supply Power Supply for DQS VREF Power Supply reference Power Supply for reference VDDS SPD Power Supply Serial EEPROM power Supply SDA Serial data I/O EEPROM serial data I/O SCL Serial clock EEPROM clock input SA0~2 Address in EEPROM EEPROM address input VDDID VDD identification VDD identification flag No Connection This pin is recommended to be left No Connection on the device. VDD/VSS NC Rev 2 Apr. 2002 3 A-Data ADBDB1916 Block Diagram CS1 CS0 DQS0 DM0 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS4 DM4 CS DQS D0 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D8 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 CS DQS D4 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D12 DQS5 DM5 DQS1 DM1 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CS DQS D1 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D9 CS DQS D5 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D13 DQS6 DM6 DQS2 DM2 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 CS DQS D2 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 DQS CS D10 CS DQS D6 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D14 DQS7 DM7 DQS3 DM3 DM I/O 7 I/O 6 I/O 1 I/O 0 I/O 5 I/O 4 I/O 3 I/O 2 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 CS D3 DQS DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CS DQS D11 BA0 - BA1 BA0-BA1: SDRAMs D0 - D15 A0 - A13 A0-A13: SDRAMs D0 - D15 RAS RAS: SDRAMs D0 - D15 CAS CAS: SDRAMs D0 - D15 VDDSPD VDD/VDDQ D0 - D15 D0 - D15 VDDID Rev 2 Apr. 2002 D7 DM I/O 0 I/O 1 I/O 6 I/O 7 I/O 2 I/O 3 I/O 4 I/O 5 CKE: SDRAMs D8 - D15 CKE: SDRAMs D0 - D7 WE WE: SDRAMs D0 - D15 Serial PD SCL SDA WP D0 - D15 VSS DQS CKE1 CKE0 SPD D0 - D15 VREF CS Strap: see Note 4 4 A0 A1 A2 SA0 SA1 SA2 CS DQS D15 A-Data ADBDB1916 Absolute Maximum Ratings Parameter Symbol Value Unit VIN, Vout -0.5~3.6 V Voltage on VDD supply relative to Vss VDD -1.0~3.6 V Voltage on VDDQ supply relative to Vss VDDQ -0.5~3.6 V Storage temperature TSTG -55~+150 Power dissipation PD 16 W Short circuit current IOS 50 mA Voltage on any pin relative to Vss Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC Operating Condition Voltage referenced to Vss = 0V, TA = 0 to 70 Parameter Symbol Min Max Unit VDD, VDDQ 2.3 2.7 V Reference voltage VREF VDDQ/2-50mV VDDQ/2+50mV V Termination voltage VTT VREF-0.04 VREF+0.04 Input logic high voltage VIH VREF+0.15 VDDQ+0.3 V 3 Input logic low voltage VIL -0.3 VREF-0.15 V 3 Output logic high voltage VOH VTT+0.84 - V IOH=-16.8mA Output logic low voltage VOL - VTT-0.84 V IOL=16.8mA Input voltage Level VIN -0.3 VDDQ+0.3 V Input Differential Voltage VID 0.3 VDDQ+0.6 V 4 Input crossing point voltage VIX 1.15 1.35 V 5 Input leakage current IIL -2 2 uA Output leakage current IOL -5 5 uA Supply voltage Note 1 2 Note : 1. Includes25mV margin for DC offset on VREF, and a combined total of 50mV margin for all AC noise and DC offset on VREF, bandwidth limited to 20MHz. The DRAM must accommodate DRAM current spikes on VREF and internal DRAM noise coupled TO VREF, both of which may result in VREF noise. VREF should be de-coupled with an inductance of 3nH. 2.VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF 3.These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation. The AC and DC input specifications are relative to a VREF envelop that has been bandwidth limited to 200MHz. 4.VID is the magnitude of the difference between the input level on CK and the input level on /CK. 5.The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. Rev 2 Apr. 2002 5 A-Data ADBDB1916 Capacitance TA=25, VDDQ=2.5V, VDD=2.5V Parameter Pin Symbol Min Max Unit Input capacitance CK,A0~A11,BA0,BA1,RAS,/CAS,/WE Cl1 49 57 pF Input capacitance CKE,CS CI2 42 50 pF Input capacitance CK0~CLK2 CI3 22 25 PF Data input / output capacitance DQM CI4 6 8 pF Input capacitance CI5 6 8 pF DM0~DM8 Output load circuit Vtt=0.5*VDDQ RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ Output Load Circuit (SSTL_2) DC Characteristics II TA=0 to 70 Symbol Condition Typical Unit IDD0 One bank Active-Precharge 760 mA IDD1 One bank operation 980 mA IDD2P Precharge power-down standby current 24 mA IDD2F Precharge floating standby current 220 mA IDD2Q Precharge quiet standby current 180 mA IDD3P Active power-down standby current 280 mA IDD3N Active standby current 460 mA IDD4R Operating current-burst read 1,360 mA IDD4W Operating current-burst write 1,480 mA IDD5 Auto refresh current 1,480 mA IDD6 Self refesh current 24 mA IDD7A Operating current-Four bank operation 2,600 mA Rev 2 Apr. 2002 6 Note A-Data ADBDB1916 AC Characteristics ADBDB1916 Parameter Symbol Unit Min Max 7.5 12 Note System clock /CAS Latency = 2.5 tCK2.5 Cycle time /CAS Latency = 2 tCK2 6 12 Clock high pulse width tCHW 0.45 0.55 tCK 1 Clock low pulse width tCLW 0.45 0.55 tCK 1 Access time form clock tAC -0.75 0.75 ns 2 /RAS cycle time tRC 60 ns /RAS to /CAS delay tRCD 20 ns /RAS active time tRAS 42 /RAS precharge time tRP 20 ns /RAS to /RAS bank active delay tRRD 15 ns /CAS to /CAS delay tCCD 1 tCK Write recovery time tWR 2 tCK Refresh row cycle time tRFC 72 ns Col. Address to Col. Address delay tCCD 1 tCK DQS out access time from CK /CK tDQSCK Data strobe edge to output data edge tDQSQ CK to valid DQS-in tDQSS DQS - input setup time tWPRES 0 ns DQS - input hold time tWPREH 0.25 tCK Address/Command setup time tIS 0.75 ns Address/Command hold time tIH 0.75 ns DQS falling edge to CK rising-setup time tDDS 0.2 tCK DQS falling edge from CK rising-hold time tDSH 0.2 tCK DQS in high level width tDQSH 0.35 tCK DQS in low level width tDQSL 0.35 tCK DQS in cycle time tDSC 0.9 MRS to new command tMRD 12 ns Power down exit time tPDEX 6 ns ns Rev 2 Apr. 2002 -0.75 0.75 7 70K ns +0.75 ns +0.5 ns 1.25 tCK 1.1 tCK A-Data ADBDB1916 Command Truth-Table Command CKEn-1 CKEn /CS /RAS /CAS /WE DQM ADDR A10/AP Mode Register Set H X L L L L X OP code No Operation H X L H H H X X Bank Active H X L L H H X H X L H L H X RA Read V L CA Read with Auto Precharge Write V H H X L H L L X CA Write with Auto Precharge L H X L L H L X Precharge select Bank H X L V X Burst Stop H X L H H L X X Auto Refresh H H L L L H X X Entry H L L L L H X H X X X Exit L H Self Refresh H H H H X X X Precharge L H H H Power down H X X X L H H H Exit H L X X L Entry V H Precharge All Bank L X H X X Entry H L X X X X X Exit L H X X X X X Clock Suspend Rev 2 Apr. 2002 BA X 8 A-Data ADBDB1916 Package Information Units : Inches (Millimeters) 5.25 0.006 (133.350 0.15) 0.118 (3.00) 5.077 (128.950) 0.7 (17.80) 0.393 0.100 Min (2.30 Min) B A (10.00) (2X) 0.157 (4.00) 1.25 0.006 (31.75 0.15) 2.500 0.10 M 2.55 0.145 Max (3.67 Max) 1.95 (64.77) C B A (49.53) 0.157 (4.00) 0.100 0.26 (6.62) 0.250 (6.350) (2.50 ) 0.050 0.0039 (1.270 0.10) 0.0787 R (2.00) 0.1496 (3.80) 2.175 0.0078 0.006 (0.20 0.15) 0.071 (1.80) 0.050 (1.270) Detail A Rev 2 Apr. 2002 0.118 (3.00) 0.039 0.002 (1.000 0.050) Detail B 9 0.1575 (4.00) 0.10 M C A M B