AFE1105E/1K - Texas Instruments High-Performance Analog

International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111

Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132

HDSL/MDSL ANALOG FRONT END

FEATURES

●COMPLETE ANALOG INTERFACE

●T1, E1, AND MDSL OPERATION

●CLOCK SCALEABLE SPEED

●SINGLE CHIP SOLUTION

●+5V ONLY (5V OR 3.3V DIGITAL)

●250mW POWER DISSIPATION

●48-PIN SSOP

●–40°C TO +85°C OPERATION

DESCRIPTION

Burr-Brown’s Analog Front End greatly reduces the

size and cost of an HDSL or MDSL system by provid-

ing all of the active analog circuitry needed to connect

the Metalink MtH1210B HDSL digital signal proces-

sor to an external compromise hybrid and a 1:2.3

HDSL line transformer. All internal filter responses as

well as the pulse former output scale with clock

frequency—allowing the AFE1105 to operate over a

range of bit rates from 196kbps to 1.168Mbps.

Functionally, this unit is separated into a transmit and

a receive section. The transmit section generates, fil-

ters, and buffers outgoing 2B1Q data. The receive

section filters and digitizes the symbol data received

on the telephone line and passes it to the MtH1210B.

The HDSL Analog Interface is a monolithic device

fabricated on 0.6µCMOS. It operates on a single +5V

supply. It is housed in a 48-pin SSOP package.

Pulse

Former

PLL

OUT

PLL

txDAT

txCLK

rxSYNC

rxLOOP

rxGAIN

rxD13 - rxD0

Line

Driver

Voltage

Reference

Delta-Sigma

Modulator

Transmit

Control

Receive

Control

Decimation

Filter

txLINE

REF

rxLINE

rxHYB

Patents Pending

AFE1105

SBWS003

AFE1105

SPECIFICATIONS

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, ftx = 584kHz (E1 rate), unless otherwise specified.

AFE1105E

PARAMETER COMMENTS MIN TYP MAX UNITS

RECEIVE CHANNEL

Number of Inputs Differential 2

Input Voltage Range Balanced Differential(1) ±3.0 V

Common-Mode Voltage 1.5V CMV Recommended +1.5 V

Input Impedance All Inputs See Typical Performance Curves

Input Capacitance 10 pF

Input Gain Matching Line Input vs Hybrid Input ±2%

Resolution 14 Bits

Programmable Gain Four Gains: 0dB, 3.25dB, 6dB, and 9dB 0 9 dB

Settling Time for Gain Change 6 Symbol

Periods

Gain + Offset Error Tested at Each Gain Range 5 %FSR(2)

Output Data Coding Two’s Complement

Output Data Rate, rxSYNC(3) 98 584(4) kHz

TRANSMIT CHANNEL

Transmit Symbol Rate, ftx 98 584(4) kHz

T1 Transmit –3dB Point Bellcore TA-NWT-3017 Compliant 196 kHz

T1 Rate Power Spectral Density(5) See Typical Performance Curves

E1 Transmit –3dB Point ETSI RTR/TM-03036 Compliant 292 kHz

E1 Rate Power Spectral Density(5) See Typical Performance Curves

Transmit Power(5) 13 14 dBm

Pulse Output See Typical Performance Curves

Common-Mode Voltage, VCM AVDD/2 V

Output Resistance(6) DC to 1MHz 1 Ω

TRANSCEIVER PERFORMANCE

Uncancelled Echo(7) rxGAIN = 0dB, Loopback Enabled –67 dB

rxGAIN = 0dB, Loopback Disabled –67 dB

rxGAIN = 3.25dB, Loopback Disabled –69 dB

rxGAIN = 6dB, Loopback Disabled –71 dB

rxGAIN = 9dB, Loopback Disabled –73 dB

DIGITAL INTERFACE(6)

Logic Levels

VIH |IIH| < 10µADV

DD –1 DVDD +0.3 V

VIL |IIL| < 10µA –0.3 +0.8 V

VOH IOH = –20µADV

DD –0.5 V

VOL IOL = 20µA +0.4 V

Transmit/Receive Channel Interface

ttx1 txCLK Period 1.7 10.2 µs

ttx2 txCLK Pulse Width ttx1/16 15ttx1/16 ns

POWER

Analog Power Supply Voltage Specification 5 V

Analog Power Supply Voltage Operating Range 4.75 5.25 V

Digital Power Supply Voltage Specification 3.3 V

Digital Power Supply Voltage Operating Range 3.15 5.25 V

Power Dissipation(4, 8) DVDD = 3.3V, 1:2 Line Transformer 250 mW

Power Dissipation(4, 8) DVDD = 5V, 1:2 Line Transformer 300 mW

PSRR 60 dB

TEMPERATURE RANGE

Operating(6) –40 +85 °C

NOTES: (1) With a balanced differential signal, the positive input is 180° out of phase with the negative input, therefore the actual voltage swing about the common

mode voltage on each pin is ±1.5V to achieve a differential input range of ±3.0V or 6Vp-p. (2) FSR is Full-Scale Range. (3) The output data is available at twice the

symbol rate with interpolated values. (4) This specification does not apply to the AFE1105EA. (5) With a pseudo-random equiprobable sequence of HDSL pulses;

13.5dBm applied to the transformer (27dBm output from txLINEP and txLINEN). (6) Guaranteed by design and characterization. (7) Uncancelled Echo is a measure

of the total analog errors in the transmitter and receiver sections including the effect of non-linearity and noise. See the Discussion of Specifications section of this

data sheet for more information. (8) Power dissipation includes only the power dissipated within the component and does not include power dissipated in the external

loads. The AFE1105 is tested with a 1:2 line transformer, but will typically be used with a 1:2.3 line transformer, this will slightly increase power dissipation.

AFE1105

The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN

assumes no responsibility for the use of this information, and all use of such information shall be entirely at the user’s own risk. Prices and specifications are subject

to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not

authorize or warrant any BURR-BROWN product for use in life support devices and/or systems.

PIN DESCRIPTIONS

PIN # TYPE NAME DESCRIPTION

1 Ground PGND Analog Ground for PLL

2 Power PVDD Analog Supply (+5V) for PLL

3 Input txCLK Symbol Clock (XMTLE from MtH1210B) (392kHz for T1, 584kHz for E1)

4 Ground DGND Digital Ground

5 Input txDAT XMTDA from MtH1210B

6 Output rxD0 ADC Output Bit-0

7 Output rxD1 ADC Output Bit-1

8 Output rxD2 ADC Output Bit-2 (RCVD0 from MtH1210B)

9 Output rxD3 ADC Output Bit-3 (RCVD1 from MtH1210B)

10 Output rxD4 ADC Output Bit-4 (RCVD2 from MtH1210B)

11 Output rxD5 ADC Output Bit-5 (RCVD3 from MtH1210B)

12 Ground DGND Digital Ground

13 Power DVDD Digital Supply (+3.3V to +5V)

14 Output rxD6 ADC Output Bit-6 (RCVD4 from MtH1210B)

15 Output rxD7 ADC Output Bit-7 (RCVD5 from MtH1210B)

16 Output rxD8 ADC Output Bit-8 (RCVD6 from MtH1210B)

17 Output rxD9 ADC Output Bit-9 (RCVD7 from MtH1210B)

18 Output rxD10 ADC Output Bit-10 (RCVD8 from MtH1210B)

19 Output rxD11 ADC Output Bit-11 (RCVD9 from MtH1210B)

20 Output rxD12 ADC Output Bit-12 (RCVD10 from MtH1210B)

21 Output rxD13 ADC Output Bit-13 (RCVD11 from MtH1210B)

22 Power DVDD Digital Supply (+3.3V to +5V)

23 Input rxSYNC ADC Sync Signal (RCVCK from MtH1210B) (392kHz for T1, 584kHz for E1)

24 Input rxGAIN0 Receive Gain Control Bit-0

25 Input rxGAIN1 Receive Gain Control Bit-1 (RCVG0 from MtH1210B)

26 Input rxLOOP Loopback Control Signal (loopback is enabled by positive signal)

27 Power AVDD Analog Supply (+5V)

28 Input rxHYBNNegative Input from Hybrid Network

29 Input rxHYBPPositive Input from Hybrid Network

30 Input rxLINENNegative Line Input

31 Input rxLINEPPositive Line Input

32 Ground AGND Analog Ground

33 Ground AGND Analog Ground

34 Output REFPPositive Reference Output, Nominally 3.5V

35 Output VCM Common-Mode Voltage (buffered), Nominally 2.5V

36 Output REFNNegative Reference Output, Nominally 1.5V

37 Power AVDD Analog Supply (+5V)

38 Ground AGND Analog Ground

39 Output txLINENTransmit Line Output Negative

40 Power AVDD Analog Supply (+5V)

41 Output txLINEPTransmit Line Output Positive

42 Ground AGND Analog Ground

43 NC NC Connection to Ground Recommended

44 NC NC Connection to Ground Recommended

45 NC NC Connection to Ground Recommended

46 NC NC Connection to Ground Recommended

47 Output PLLOUT PLL Filter Output

48 Input PLLIN PLL Filter Input

AFE1105

PIN CONFIGURATION

Top View SSOP Analog Inputs: Current .............................................. ±100mA, Momentary

±10mA, Continuous

Voltage.................................. AGND –0.3V to AVDD +0.3V

Analog Outputs Short Circuit to Ground (+25°C) ..................... Continuous

AVDD to AGND ........................................................................ –0.3V to 6V

PVDD to PGND ........................................................................ –0.3V to 6V

DVDD to DGND........................................................................ –0.3V to 6V

PLLIN or PLLOUT to PGND.........................................–0.3V to PVDD +0.3V

Digital Input Voltage to DGND ..................................–0.3V to DVDD +0.3V

Digital Output Voltage to DGND ...............................–0.3V to DVDD +0.3V

AGND, DGND, PGND Differential Voltage .........................................0.3V

Junction Temperature (TJ) ............................................................ +150°C

Storage Temperature Range .......................................... –40°C to +125°C

Lead Temperature (soldering, 3s)................................................. +260°C

Power Dissipation ......................................................................... 700mW

ABSOLUTE MAXIMUM RATINGS

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown

recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degradation

to complete device failure. Precision integrated circuits may

be more susceptible to damage because very small parametric

changes could cause the device not to meet its published

specifications.

PGND



txCLK

DGND

txDAT

rxD0

rxD1

rxD2

rxD3

rxD4

rxD5

DGND

DD

rxD6

rxD7

rxD8

rxD9

rxD10

rxD11

rxD12

rxD13



rxSYNC

rxGAIN0

PLL



PLL

OUT

NC

AGND

txLINE



txLINE



AGND



REF



REF

P

AGND

rxLINE



rxLINE



rxHYB



rxHYB



rxLOOP

rxGAIN1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25



AFE1105E

MAXIMUM PACKAGE

BIT DRAWING TEMPERATURE

PRODUCT RATE PACKAGE NUMBER(1) RANGE

AFE1105E 1.168Mbps 48-Pin Plastic SSOP 333 –40°C to +85°C

AFE1105EA 512kbps 48-Pin Plastic SSOP 333 –40°C to +85°C

NOTE: (1) For detailed drawing and dimension table, please see end of data sheet, or Appendix

C of Burr-Brown IC Data Book.

PACKAGE/ORDERING INFORMATION

AFE1105

TYPICAL PERFORMANCE CURVES

At Output of Pulse Transformer

Typical at 25°C, AVDD = +5V, DVDD = +3.3V, unless otherwise specified.

CURVE 2. Transmitted Pulse Template and Actual Performance as Measured at the Transformer Output.

CURVE 1. Upper Bound of Power Spectral Density Measured at the Transformer Output.

0.4T

B = 1.07

C = 1.00

D = 0.93

0.4T

–0.6T

–1.2T

A = 0.01 E = 0.03

G = –0.16

A

B

C

D

E

F

G

0.01

1.07

1.00

0.93

0.03

–0.01

–0.16

–0.05

0.0264

2.8248

2.6400

2.4552

0.0792

–0.0264

–0.4224

–0.1320

–0.0264

–2.8248

–2.6400

–2.4552

–0.0792

0.0264

0.4224

0.1320

0.0088

0.9416

0.8800

0.8184

0.0264

–0.0088

–0.1408

–0.0440

–0.0088

–0.9416

–0.8800

–0.8184

–0.0264

0.0088

0.1408

0.0440

NORMALIZED

LEVEL

QUATERNARY SYMBOLS

+3 –3+1 –1

14T

H = –0.05 50T

F = –0.01

A = 0.01

F = –0.01

0.5T

1.25T

CURVE 3. Input Impedance of rxLINE and rxHYB.

–20

–40

–60

–80

–100

–120 10K 100K

POWER SPECTRAL DENSITY LIMIT

Power Spectral Density (dBm/Hz)

Frequency (Hz)

1M 10M

–38dBm/Hz for T1

–40dBm/Hz for E1

196kHz 292kHz

–80dB/decade

–120dBm/Hz

for E1

–118dBm/Hz

100

200

150

100

50

0300 500

INPUT IMPEDANCE vs BIT RATE

Input Impedance (kΩ)

Bit Rate (kbps)

700 900 13001100

T1 = 784kbps, 45kΩ

E1 = 1168kbps, 30kΩ

AFE1105

ADC

Pulse Former

Programmable

Gain Amp Difference

Amplifier

Differential

Line Driver

txLINE

rxHYB

rxLINE

txDAT

rxD13 - rxD0 14

THEORY OF OPERATION

The transmit channel consists of a switched-capacitor pulse

forming network followed by a differential line driver. The

pulse forming network receives symbol data from the

XMTDA output of the MtH1210B and generates a 2B1Q

output waveform. The output meets the pulse mask and

power spectral density requirements defined in European

Telecommunications Standards Institute document RTR/

TM-03036 for E1 mode and in sections 6.2.1 and 6.2.2.1 of

Bellcore technical advisory TA-NWT-001210 for T1 mode.

The differential line driver uses a composite output stage

combining class B operation (for high efficiency driving

large signals) with class AB operation (to minimize cross-

over distortion).

The receive channel is designed around a fourth-order delta

sigma A/D converter. It includes a difference amplifier

designed to be used with an external compromise hybrid for

first order analog crosstalk reduction. A programmable gain

amplifier with gains of 0dB to +9dB is also included. The

delta sigma modulator operating at a 24X oversampling ratio

produces 14 bits of resolution at output rates up to 584kHz.

The basic functionality of the AFE1105 is illustrated in

Figure 1 shown below.

The receive channel operates by summing the two differen-

tial inputs, one from the line (rxLINE) and the other from the

compromise hybrid (rxHYB). The connection of these two

inputs so that the hybrid signal is subtracted from the line

signal is described in the paragraph titled “Echo Cancella-

tion in the AFE”. The equivalent gain for each input in the

difference amp is 1. The resulting signal then passes to a

programmable gain amplifier which can be set for gains of

0dB through 9dB. The ADC converts the signal to a

14-bit digital word, rxD13-rxD0.

rxLOOP INPUT

rxLOOP is the loopback control signal. When enabled, the

rxLINEP and rxLINEN inputs are disconnected from the

AFE. The rxHYBP and rxHYBN inputs remain connected.

Loopback is enabled by applying a positive signal (Logic 1)

to rxLOOP.

ECHO CANCELLATION IN THE AFE

The rxHYB input is designed to be subtracted from the

rxLINE input for first order echo cancellation. To accom-

plish this, note that the rxLINE input is connected to the

same polarity signal at the transformer (positive to positive

and negative to negative) while the rxHYB input is con-

nected to opposite polarity through the compromise hybrid

(negative to positive and positive to negative) as shown in

Figure 2.

RECEIVE DATA CODING

The data from the receive channel A/D converter is coded in

two’s complement code.

ANALOG INPUT OUTPUT CODE (rxD13 - rxD0)

Positive Full Scale 01111111111111

Mid Scale 00000000000000

Negative Full Scale 10000000000000

FIGURE 1. Functional Block Diagram of AFE1105.

RECEIVE CHANNEL PROGRAMMABLE

GAIN AMPLIFIER

The gain of the amplifier at the input of the Receive Channel

is set by two gain control pins, rxGAIN1 and rxGAIN0. The

resulting gain between 0dB and +9dB is shown below.

rxGAIN1 rxGAIN0 GAIN

0 0 0dB

0 1 3.25dB

1 0 6dB

1 1 9dB

AFE1105

rxHYB

AND rxLINE INPUT ANTI-ALIASING FILTERS

The –3dB frequency of the input anti-aliasing filter for the

rxLINE and rxHYB differential inputs should be about

1MHz. Suggested values for the filter are 750Ω for each of

the two input resistors and 100pF for the capacitor. Together

the two 750Ω resistors and the 100pF capacitor result in

–3dB frequency of just over 1MHz. The 750Ω input resis-

tors will result in a minimal voltage divider loss with the

input impedance of the AFE1105.

This circuit applies at both T1 and E1 rates. For slower rates,

the antialiasing filters will give best performance with their

–3dB frequency approximately equal to the bit rate. For

example, a –3dB frequency of 500kHz should be used for a

single pair bit rate of 500kbps.

rxHYB AND rxLINE INPUT BIAS VOLTAGE

The transmitter output on the txLINE pins is centered at

midscale, 2.5V. But, the rxLINE input signal is centered at

1.5V in the circuit shown in Figure 2 above.

Inside the AFE1105, the rxHYB and rxLINE signals are

subtracted as described in the paragraph on echo cancella-

tion above. This means that the rxHYB inputs need to be

centered at 1.5V just as the rxLINE signal is centered at

1.5V. REFN (Pin 36) is a 1.5V voltage source. The external

compromise hybrid must be designed so that the signal into

the rxHYB inputs is centered at 1.5V.

FIGURE 2. Basic Connection Diagram.

PLL

OUT

REF

AFE1105

PLL

txDAT

txCLK

rxSYNC

rxGAIN1

rxD13 - rxD2

PGND

DGND

AGND

AGND

rxLOOP

txLINE

rxHYB



rxHYB



rxLINE



rxLINE

rxGAIN0

1kΩ

200Ω

0.1µF

0.01µF

14.7Ω

Neg

Pos

750Ω

100pF

Compromise

Hybrid

0.01µF

Input anti-alias

filter f

≅ 1MHz

1:2.3 Transformer

Tip

Ring

0.1µF 0.1µF 0.1µF

2kΩ

REF

2kΩ

196Ω

2kΩ

REF

0.1µF

XMTDA

XMTLE

RCVCK

RCVG0

RCVD11 - RCVD0

VCXCK

VCXLE

VCXDA

MtH1210B

5V Analog

0.1µF 0.1µF

10µF 0.1µF 0.1µF 0.1µF 1 - 10µF

5V to 3.3V Digital

5 - 10Ω resistor for isolation

PCM56

LOG COM

ANA COM

CLK

DATA

OUT

4, 14, 15 NC

0.1µF and 2.2µF

caps on ±5V supplies

12.1kΩ

0.1µF

18.2kΩ

69.8kΩ

30.1kΩMC33201D

2.2µF0.1µF

VCXCN

AFE1105

TIMING DIAGRAM

FIGURE 3. Timing Diagram.

RECEIVE TIMING

The rxSYNC signal controls portions of the A/D converter’s

decimation filter and the data output timing of the A/D

converter. It is generated at the symbol rate by the user and

must be synchronized with txCLK. The rising edge of

rxSYNC can occur at the falling edge of txCLK or it can be

shifted by the user in increments of 1/48 of a symbol period

to one of 47 discrete delay times after the falling edge of

txCLK.

The bandwidth of the A/D converter decimation filter is

equal to one half of the symbol rate. The A/D converter data

output rate is 2X the symbol rate. The specifications of the

AFE1105 assume that one A/D converter output is used per

symbol period and the other interpolated output is ignored.

The Receive Timing Diagram above suggests using the

rxSYNC pulse to read the first data output in a symbol

period. Either data output may be used. Both data outputs

may be used for more flexible post-processing.

tx1

tx2

tx1

(n + 25.5) t

tx1

/48

(n + 1.5) t

tx1

/48

Data 1 Data 1a Data 2

tx1

txCLK

Transmit Timing

txDAT

(+3 Symbol)

txDAT (+1 Symbol)

txDAT (–1 Symbol)

txDAT (–3 Symbol)

rxSYNC

Receive Timing

rxD13 - rxD0

tx1

/24 min

tx1

/48± t

tx1

/96

20ns

NOTES: (1) Any transmit sequence not shown will result in a zero symbol. (2) All transitions are specified relative to the falling edge of

txCLK. (3) Maximum allowable error for any txDAT edge is ±t

tx1

/12 (±17.8ns at E1 rate; ±26.6ns at T1 rate). (4) Both txDAT inputs are

read by the AFE1103 at 1/8, 3/8, and 5/8 of a symbol period from the rising edge of txCLK. (5) rxSYNC can shift to one of 48 discrete

delay times from the falling edge of txCLK. (6) It is recommended that rxD13 - rxD0 be read on the rising edge of rxSYNC.

20ns

AFE1105

DISCUSSION OF

SPECIFICATIONS

UNCANCELLED ECHO

The key measure of transceiver performance is uncancelled

echo. This measurement is made as shown in the diagram of

Figure 4. The AFE is connected to an output circuit includ-

ing a typical 1:2 line transformer. The line is simulated by a

135Ω resistor. Symbol sequences are generated by the tester

and applied both to the AFE and to the input of an adaptive

filter. The output of the adaptive filter is subtracted from the

AFE output to form the uncancelled echo signal. Once the

filter taps have converged, the RMS value of the uncancelled

echo is calculated. Since there is no far-end signal source or

additive line noise, the uncancelled echo contains only noise

and linearity errors generated in the transmitter and receiver.

The data sheet value for uncancelled echo is the ratio of the

RMS uncancelled echo (referred to the receiver input through

the receiver gain) to the nominal transmitted signal (13.5dBm

into 135Ω, or 1.74Vrms). This echo value is measured under

a variety of conditions: with loopback enabled (line input

disconnected); with loopback disabled under all receiver

gain ranges; and with the line shorted (S1 closed in Figure 4).

LAYOUT

The analog front end of an HDSL system has a number of

conflicting requirements. It must accept and deliver digital

outputs at fairly high rates of speed, phase-lock to a high-

speed digital clock, and convert the line input to a high-

precision (14-bit) digital output. Thus, there are really three

sections of the AFE1105: the digital section, the phase-

locked loop, and the analog section.

The power supply for the digital section of the AFE1105 can

range from 3.3V to 5V. This supply should be decoupled to

digital ground with a ceramic 0.1µF capacitor placed as

close to DGND (pin 12) and DVDD (pin 13) as possible.

Ideally, both a digital power supply plane and a digital

ground plane should run up to and underneath the digital

pins of the AFE1105 (pins 3 through 26). However, DVDD

may be supplied by a wide printed circuit board (PCB) trace.

A digital ground plane underneath all digital pins is strongly

recommended.

The phase-locked loop is powered from PVDD (pin 2) and its

ground is referenced to PGND (pin 1). Note that PVDD must

be in the 4.75V to 5.25V range. This portion of the AFE1105

should be decoupled with both a 10µF Tantalum capacitor

FIGURE 4. Uncancelled Echo Test Diagram.

rxHYB

AFE1105

rxLINE

REF

rxD13 - rxD0

rxHYB

txLINE

txDAT

100pF

0.01µF

576Ω

1.54kΩ

13Ω

5.6Ω1:2

5.6Ω

0.047µF

150Ω

576Ω0.047µF

2kΩ

100pF

750Ω

Transmit

Data

Uncancelled

Echo

0.1µF

750Ω0.1µF

2kΩ

135ΩS

Adaptive

Filter

AFE1105

and a 0.1µF ceramic capacitor. The ceramic capacitor should

be placed as close to the AFE1105 as possible. The place-

ment of the Tantalum capacitor is not as critical, but should

be close. In each case, the capacitor should be connected

between PVDD and PGND.

In most systems, it will be natural to derive PVDD from the

AVDD supply. A 5Ω to 10Ω resistor should be used to

connect PVDD to the analog supply. This resistor in combi-

nation with the 10µF capacitor form a lowpass filter—

keeping glitches on AVDD from affecting PVDD. Ideally,

PVDD would originate from the analog supply (via the

resistor) near the power connector for the printed circuit

board. Likewise, PGND should connect to a large PCB trace

or small ground plane which returns to the power supply

connector underneath the PVDD supply path. The PGND

“ground plane” should also extend underneath PLLIN and

PLLOUT (pins 47 and 48).

The remaining portion of the AFE1105 should be considered

analog. All AGND pins should be connected directly to a

common analog ground plane and all AVDD pins should be

connected to an analog 5V power plane. Both of these planes

should have a low impedance path to the power supply.

Ideally, all ground planes and traces and all power planes

and traces should return to the power supply connector

before being connected together (if necessary). Each ground

and power pair should be routed over each other, should not

overlap any portion of another pair, and the pairs should be

separated by a distance of at least 0.25 inch (6mm). One

exception is that the digital and analog ground planes should

be connected together underneath the AFE1105 by a small

trace.

PACKAGING INFORMATION

Orderable Device Status (1) Package

Type Package

Drawing Pins Package

Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)

AFE1105E ACTIVE SSOP DL 48 30 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

AFE1105E/1K ACTIVE SSOP DL 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

AFE1105E/1KG4 ACTIVE SSOP DL 48 1000 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

AFE1105EG4 ACTIVE SSOP DL 48 30 Green (RoHS &

no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Dec-2006

Addendum-Page 1

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,

enhancements, improvements, and other changes to its products and services at any time and to discontinue

any product or service without notice. Customers should obtain the latest relevant information before placing

orders and should verify that such information is current and complete. All products are sold subject to TI’ s terms

and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in

accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI

deems necessary to support this warranty. Except where mandated by government requirements, testing of all

parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for

their products and applications using TI components. To minimize the risks associated with customer products

and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,

in which TI products or services are used. Information published by TI regarding third-party products or services

does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.

Use of such information may require a license from a third party under the patents or other intellectual property

of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without

alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction

of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for

such altered documentation.

Resale of T I products or services with statements different from or beyond the parameters stated by TI for that

product or service voids all express and any implied warranties for the associated TI product or service and

is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application

solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio

Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband

Interface interface.ti.com Digital Control www.ti.com/digitalcontrol

Logic logic.ti.com Military www.ti.com/military

Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork

Microcontrollers microcontroller.ti.com Security www.ti.com/security

Low Power Wireless www.ti.com/lpw Telephony www.ti.com/telephony

Video & Imaging www.ti.com/video

Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265