S29JL032H60TAI410 - Advanced Micro Devices

This docum ent c ontain s in forma tion on a p roduct unde r de velo pment at FASL L LC. T he info rmati on is inte nded to h elp yo u e valu ate this product. FASL LLC reserves the

right to change or discontinue work on this proposed product without notice.

Publication Number S29JL032H Revision A Amendment 0 Issue Date May 21, 2004

ADVANCE INFORMATION

S29JL032H

32 Megabit (4 M x 8-Bit/2 M x 16-Bit)

CMOS 3.0 Volt-only, Simultaneous Read/Write

Flash Memory

Distinctive Characteristics

Architectural Advantages

Simultaneous Read/Write operations

— Data can be continuously read from one bank while

executing erase/program functions in another bank.

— Zero latency be tw ee n re a d and write operatio ns

Multiple Bank architecture

— Four ba n k a rc hitectur e s avai la b l e (r efer to Table 2).

Boot Sectors

— Top and bottom boot sect ors in the same device

— Any combination of sectors can be erased

Manufactured on 0.13 µm process technology

SecSi™ (Secured Silicon) Sector: Extra 256 Byte

sector

—Factory locked and identifiable: 16 bytes av ailable for

secure, random f actory Electronic Serial Number;

verifiable as f a ctor y l ocked through autoselect

function.

—Customer lockable: On e-time programmable only.

Once locked, data cannot be changed

Zero Power Operation

— Sophisticated po wer m anagem e nt circuits reduce

power c on s um e d du r in g ina ct ive pe r iods to nearl y

zero.

Compatible with JEDEC standards

— Pinou t an d s of tware com p a tib le with s ing le -power-

supply flash standard

Package options

48-pin TSOP

Performance Characteristics

High performance

— Acce ss ti me as fast as 55 ns

— Program time: 4 µs/wor d typical using a cce le rated

programming function

Ultra low power consumption (typical values)

— 2 mA active read current at 1 MHz

— 10 mA active read current at 5 MHz

— 200 nA in standby or au to m a tic slee p m ode

Cycling Endurance: 1 million cycles per sector

typical

Data Retention: 20 years typical

Software Features

Supports Common Flash Memory Interface (CFI)

Erase Suspend/Erase Resume

— Suspends erase op erations to r ead d ata from, or

program data to, a sector that is not being erased,

then resumes the erase operation.

Data# Polling and Toggle Bits

— Pro vides a softw are method of d etecting th e status of

program or erase cycles

Unlock Bypass Program command

— Reduces overall programming time when issuing

mult iple program command sequences

Hardware Features

Ready/Busy# output (RY/BY#)

— Hardware method for detecting program or erase

cycle completion

Hardware reset pin (RESET#)

— Hardware method of resetting the internal state

machine to the read mode

WP#/ACC input pin

— Write protect (WP#) function protects the two

outerm os t boot sectors reg a rd le s s of sector protec t

status

— Accel e ration (ACC) functi on accelerates progra m

timing

Sector protection

— Hardware method to prevent any program or erase

operation within a sector

— Temporary Sector U nprotect allows changing data in

protected sectors in-system

2 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

General Description

The S29JL032H is a 32 megabit, 3.0 volt -only flash memory device, organized as

2,097,152 wor ds of 16 bits each or 4,194, 304 bytes of 8 bits each. Word mod e

data appears on DQ15–DQ0; byte mode data appears on D Q7–DQ 0. Th e dev ice

is designed to be pr ogrammed in-system with the s tandard 3.0 volt VCC supply,

and can also be programmed in standard EPROM programmers.

The device is av ailable with an access time of 55, 60, 70, or 90 ns and is offered

in a 48-pin TSOP package. Standard control pins—chip enable (CE#), write en-

able (WE#), and output enable (OE#)—control normal read and write operations,

and avoid bus contention issues.

The device requires only a single 3.0 volt power supply for both read and write

functions. Internally generated and regulated voltages are provided for the pro-

gram and erase operations.

Simultaneous Read/Write Operations with Zero Latency

The Simultaneous Read/Write architecture provides simultaneous operation

by dividing the memory space into separate banks (see Table 2). Sector ad-

dresses are fixed, system software can be used to form user-defined bank

groups.

During an Erase/Program operation, any of the non-busy banks may be read

from. Note t hat on ly two banks can o perate simultaneous ly. The device c an im-

prove overall system performance by allowing a host system to program or erase

in one bank, then immediately and simultaneously read from the other bank, with

zero latency . This releases the system from waiting for the completion of program

or erase o perati ons.

The S29JL032H can be organized as both a top and bottom boot sector

configuration.

S29JL032H Features

The SecSi™ (Secured Silicon) Sector is an extra 256 byte sector capable of

being permanently locked by FASL or customers. The SecSi Customer Indicator

Bit (DQ6) is perman ently set to 1 i f the part has bee n custom er locked, perma-

nently set to 0 if the part has been factory locked, and is 0 if customer lockable.

This way, customer lockable parts can never be used to replace a factory locked

part.

Factory locked parts provide several options. T he SecSi Sector may store a se-

cure, random 16 byte ESN (Electronic Serial Number), customer code

(programmed through Spansion programming services), or both. Customer Lock-

able parts may utilize the SecSi Sector as bonus space, rea ding and writing like

any other flash sector, or may permanently lock their own code there.

DMS (Data Management Software) allows systems to easily take advantage

of the advanced architecture of the simultaneous read/write p roduct line by al-

lowing removal of EEPROM devices. DMS will also allow the system software to

be simplified, as it will perform all functions necessary to modify data in file struc-

tures, as opposed to single-byte modifications. To write or update a particular

piece of data (a phone number or configuration data, for example), the user only

needs to state which piece of data is to be updated, and where the updated data

is located in the system. This is an advantage compared to systems where user-

written software must keep track of the old data location, status, logical to phys-

ical translation of the da ta onto the Flas h memory devic e (or me mory devices),

May 21, 2004 S29JL032HA0 S29JL032H 3

ADVANCE INFORMATION

and more. Using DMS, user-written software does not need to interface with the

Flash mem ory dir ectly. Instead, the us er's softwar e acce sses t he Fla sh me mory

by calling one of only six functions.

The device offers complete compatibility with the JEDEC 42.4 sin-

gle-power-supply Flash command set standard. Comma nds are written to

the command register using standard microprocessor write timings. Reading data

out of the device is similar to reading from other Flash or EPROM devices.

The host system can detect whether a program or erase oper ation is complete by

using the device status bits: RY/BY# pin, DQ7 (Data# Polling) and DQ6/DQ2

(toggle bits). After a program or erase cycle has been completed, the device au-

tomatically returns to the read mode.

The sector erase architecture allows memory sectors to be erased and repro-

grammed without affecting the data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low V CC detector that automat-

ically inhibits write operations during power transitions. The hardware sector

protection feature disables both program and er ase operations in any combina-

tion of the sectors of memory. This can be achieved in-system or via

programming equipment.

The device offers two power-saving features. When a ddr es s es have b een stable

for a specified amount of time, the device ent ers the automatic sleep mode.

The system can al so pl ace the device into the standby mode. Power consump-

tion is greatly reduced in both modes.

4 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Ta b l e O f C o n t e n t s

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .5

Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . .7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . .9

Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 10

Table 1. S29JL032H Device Bus Operations ....... .. .................10

Requirements for Reading Array Data ............................................ 11

Writing Commands/Command Sequences ....................................11

Accelerated Program Operation ......................................................12

Autoselect Functions ............................................................................12

Simultaneous Read/Write Operations with Zero Latency ....... 12

Automatic Sleep Mode ......................................................................... 13

RESET#: Hardware Reset Pin ............................................................ 13

Output Disable Mode ...........................................................................14

Table 2. S29JL032H Bank Architecture .................................14

Table 3. S29JL032H Sector Addresse s - Top Boot Dev ices ......15

Table 4. S29JL032H Se ctor Addresses - Bottom Boot Devices .17

Table 5. S29JL032H Autoselect Codes,

(High Voltage Method) ......................................................19

Sector/Sector Block Protection and Unprotection ...................20

Table 6. S29JL032H Boot Sector/Sector Block Addresses

for Protection/Unprotection ............................. ...................20

Table 7. S29JL032H Bottom Boot Sector/Sector Block Addresses

for Protection/Unprotection ............................. ...................21

Table 8. WP#/ACC Modes ..................................................22

Temporary Sector Unprotect .......................................................... 22

Figure 1. Temporary Sector Unprotect Operation................... 23

Figure 2. In-System Sector Protect/Unprotect Algorithms....... 24

SecSi™ (Secured Silicon) Sector

Flash Memory Region .......................................................................... 25

Figure 3. SecS i Sector Protect Verify ................................... 26

Hardware Data Protection ................................................................ 26

Low VCC Write Inhibit ...................................................................... 26

Write Pulse “Glitch” Protection ...................................................... 27

Logical Inhibit ......................................................................................... 27

Power-Up Write Inhibit ..................................................................... 27

Common Flash Memory Interface (CFI) . . . . . . .27

Table 9. CFI Query Identification String ...............................28

Table 10. System Interface String .......................................28

Table 11. Device Geometry Definition ..................................29

Table 12. Primary Vendor-Specific Extended Query ................29

Command Definitions . . . . . . . . . . . . . . . . . . . . . . 31

Reading Array Data .............................................................................. 31

Reset Command .................................................................................... 31

Autoselect Command Sequence ...................................................... 32

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence ............................................................................ 32

Byte/Word Program Command Sequence ................................... 32

Unlock Bypass Command Sequence ................................................33

Figure 4. Program Operation .............................................. 34

Chip Erase Command Sequence ...................................................... 34

Sector Erase Command Sequence ...................................................35

Figure 5. Erase Operation .................................................. 36

Erase Suspend/Erase Resume Commands .................................... 36

Table 13. S29JL032H Command Definitions ......................... 38

Write Operation Status . . . . . . . . . . . . . . . . . . . . . 39

DQ7: Data# Polling .............................................................................. 39

Figure 6. Data# Polling Algorithm ....................................... 40

DQ6: Toggle Bit I ................................................................................... 41

Figure 7. Toggle Bit Algorithm ............................................ 42

DQ2: Toggle Bit II ................................................................................ 42

Reading Toggle Bits DQ6/DQ2 ........................................................ 43

DQ5: Exceeded Timing Limits .......................................................... 43

DQ3: Sector Erase Timer .................................................................. 43

Table 14. Write Operation Stat us ...... ................................. 44

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 45

Figure 8. Maximum Negative Overshoot Waveform................ 45

Figure 9. Maximum P ositive Overshoot Waveform ...... ........... 45

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . .45

Industrial (I) Devices ............................................................................ 45

Supply Voltages ............................................................................ 45

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .46

CMOS Compatible ...............................................................................46

Figure 10. I

CC1

Current vs. Time (Showing Active and

Automatic Sleep Currents) ................................................. 47

Figure 11. Typical I

CC1

vs. Frequency .................................. 47

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Figure 12. Test Setup...................... ................................. 48

Key To Switching Waveforms . . . . . . . . . . . . . . . .48

Figu re 13. Inp ut Waveforms and M easurement Levels............ 48

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 49

Read-Only Operations ...................................................................... 49

Figure 14. Read Operation Timings...................................... 49

Hardware Reset (RESET#) ................................................................50

Figure 15. Reset Timings ..... ................................... ........... 50

Word/Byte Configuration (BYTE#) ................................................. 51

Figure 16. BYTE# Timings for Read Operations ..................... 52

Figure 17. BYTE# Timings for Write Operations..................... 52

Erase and Program Operations .........................................................53

Figure 18. Program Op eration Timings................................. 54

Figure 19. Accelerated Program Timing Diagram ................... 54

Figure 20. Chip/Sector Erase Operation Timings.................... 55

Figure 21. Back-to-back Read/Write Cycle Timings.. .............. 56

Figure 22. Data# Polling Timings

(During Embedded Algorithms)........................................... 56

Figure 23. Toggle Bit Timings (During Embedded Algorithms) . 57

Figure 24. DQ2 vs. DQ 6.................................. ................... 57

Temporary Sector Unprotect .......................................................... 58

Figure 25. Temporary Sector Unprotect Timing Diagram......... 58

Figure 26. Sector/S ector Block Protect and

Unprotect Timing Diagram ................................................. 59

Alternate CE# Controlled Erase and Program Operations ....60

Figure 27. Alternate CE# Controlled Write (Erase/Program)

Operation Timings.......... ................................................... 61

Erase And Programming Performance . . . . . . . . 62

TSOP Pin Capacitance . . . . . . . . . . . . . . . . . . . . . 62

Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . 63

TS 048—48-Pin Standard TSOP ...................................................... 63

Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . . 64

May 21, 2004 S29JL032HA0 S29JL032H 5

ADVANCE INFORMATION

Product Selector Guide

Block Diagram

4 Bank Device

Part Number

S29JL032H

Speed Option Standard Voltage Range: V

= 2.7–3.6 V

55 60 70 90

Max Access Time (ns), t

ACC

55 60 70 90

CE# Access (ns), t

55 60 70 90

OE# Access (ns), t

25 25 30 35

Bank 1 Address

Bank 2 Address

A20–A0

RESET#

WE#

CE#

BYTE#

DQ0–DQ15

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Bank 1

X-Decoder

OE# BYTE#

DQ15–DQ0

Status

Control

A20–A0

A20–A0A20–A0

DQ15–DQ0

Mux

Bank 2

X-Decoder

Y-gate

Bank 3

X-Decoder

Bank 4

X-Decoder

Y-gate

Bank 3 Address

Bank 4 Address

6 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Block Diagram

2 Bank Device

VCC

VSS

Upper Bank Address

A20–A0

RESET#

WE#

CE#

BYTE#

DQ15–DQ0

WP#/ACC

STATE

CONTROL

COMMAND

RY/BY#

Upper Bank

X-Decoder

Y-Decoder

Latches and Control Logic

OE# BYTE#

DQ15–DQ0

Lower Bank

Y-Decoder

X-Decoder

Latches and

Control Logic

Lower Bank Address

OE# BYTE#

Status

Control

A20–A0

A20–A0A20–A0

DQ15–DQ0 DQ15–DQ0

May 21, 2004 S29JL032HA0 S29JL032H 7

ADVANCE INFORMATION

Connection Diagrams

A15

A18

A14

A13

A12

A11

A10

A19

A20

WE#

RESET#

WP#/ACC

RY/BY#

A17

A16

DQ2

BYTE#

DQ15/A-1

DQ7

DQ14

DQ6

DQ13

DQ9

DQ1

DQ8

DQ0

OE#

CE#

DQ5

DQ12

DQ4

DQ11

DQ3

DQ10

48-Pin Standard TSOP

8 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Pin Description

A20–A0 = 21 Addresses

DQ14–DQ0 = 15 Data Inputs/Outputs (x16-only devices)

DQ15/A-1 = DQ15 (Data Input/Output, word mode), A-1 (LSB

Address Input, byte mode)

CE# = Chip Enable

OE# = Output Enable

WE# = Write Enable

WP#/ACC = Hardware Write Protect/

Acceleration Pin

RESET# = Hard ware Re set Pin, Active Low

BYTE# = Selects 8-bit or 16-bit mode

RY/BY# = Rea dy/Busy Output

VCC = 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and voltage supply tolerances)

VSS = Device Ground

NC = Pin Not Connected Internally

Logic Symbol

21 16 or 8

DQ15–DQ0

(A-1)

A20–A0

CE#

OE#

WE#

RESET#

BYTE#

RY/BY#

WP#/ACC

May 21, 2004 S29JL032HA0 S29JL032H 9

ADVANCE INFORMATION

Ordering Information

The order number (Valid Combination) is formed by the follow ing:

Note:

1. Type 0 is standard. Specify other options as required.

2. Consult your local Spansion representative for availability of 55ns speed option.

Valid Combinations

Valid Combinations list configura tions planned to be supported in volume for this

device. Co nsult your local Spansion sales office to confirm availability of specific

valid combinations and to check on newly released combinations.

S29JL032H 55 T A I 00 0

PACKING TYPE

0=Tray

2 = 7- inch Tape and Reel

3 = 13 -inch Ta pe and Reel

MODEL NUMBER

01 = Top Boot Device, 4 Banks: 4/12/12/4Mb

02 = Bottom Boot Device, 4 Banks: 4/12/12/4Mb

21 = Top Bo ot De v i ce, 2 Bank s : 4/28Mb

22 = Bottom Boot Device, 2 Banks: 4/28Mb

31 = Top Bo ot De v i ce, 2 Bank s : 8/24Mb

32 = Bottom Boot Device, 2 Banks: 8/24Mb

41 = Top Boot Device, 2 Banks: 16/16Mb

42 = Bottom Boot Device, 2 Banks: 16/16Mb

TEMPERATURE RANGE

I = Industrial (–40

C to +85

PACKAGE MATERIAL SET

A = Standard

F = Pb-free

PACKAGE TYPE

T = Thin Small Outline Package (T SO P) Standa rd Pinout

SPEED OPTION

55 = 55 ns

60 = 60 ns

70 = 70 ns

90 = 90 ns

DEVICE FAMILY

S29JL032H

3.0 V o lt -only, 32 Megabit (2 M x 16-Bit/4 M x 8-Bit) Simultaneous Read/Write Flash Memory

Manufactured on 130 nm process technology

S29JL032H Valid Combinations

Device Family Speed Option Package &

Temperature Model Number Packing Type Package Type

S29JL032H

(Note 2)

TAI

TFI

(Note 1 )

TS048 TSOP

10 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Device Bus Operations

This section describes the requirements and use of the device bus operations,

which are initiated through the internal command register. The command register

itself does not occupy any addressable memory locati on. The register is a latch

used to store the commands, along with the address and data information

needed to ex ecute the command. The contents of the register serve as inputs to

the internal state machine. The state machine outputs dictate the function of the

device. Table 1 lists the device bus operations, the inputs and control levels they

require, and the resulting output. The following subsections describe each of

these operations in further detail.

Table 1. S29JL032H Device Bus Operations

Legend: L = Logic Low = VIL, H = Logic High = VIH, VID = 11.5–12.5 V, VHH = 9.0 ± 0.5 V, X = Don’t Care, SA = Sector

Address, AIN = Address In, DIN = Data In, DOUT = Data Out

Notes:

1. Addresses are A20:A0 in word mode (BYTE# = VIH), A20:A-1 in byte mode (BYTE# = VIL).

2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See

the “Sector/Sector Block Protection and Unprotection” section.

3. If WP#/ACC = VIL, the two outermost boot sectors remain protected. If WP#/ACC = VIH, protection on the two out-

ermost boot sectors depends on whether they were last protected or unprotected using the method described in

“Sector/Sector Block Protection and Unprotection”. If WP#/ACC = VHH, all sectors will be unprotected.

Operation CE# OE# WE# RESET# WP#/ACC

Addresses

(Note 2)

DQ15–DQ8

DQ7–DQ0

BYTE# =

BYTE# = V

Read L L H H L/H A

OUT

DQ14–DQ8 = High-

Z, DQ15 = A-1 D

OUT

Write L H L H (N ote 3) A

Standby V

0.3 V X X V

0.3 V L/H XHigh-Z High-Z High-Z

Output Disable L H H H L/H XHigh-Z High-Z High-Z

Reset X X X L L/H XHigh-Z High-Z High-Z

Sector Protect

(Note 2) L H L V

L/H SA, A6 = L,

A1 = H, A0 = L X X D

Sector Unprotect

(Note 2) L H L V

(Note 3) SA, A6 = H,

A1 = H, A0 = L X X D

Temporary

Sector Unprotect X X X V

(Note 3) A

High-Z D

May 21, 2004 S29JL032HA0 S29JL032H 11

ADVANCE INFORMATION

Word/Byte Configuration

The BYTE# pin controls whether the device da ta I/O pins operate in the byte or

word configuration. If the BYTE# pin is set at logic ‘1’, the device is in word con-

figur ation, DQ15– DQ0 are active an d controlled by CE# and OE#.

If the BYTE# pin is set a t logic ‘0’, the de vice is in byte configuration, and only

data I/O pins DQ7– DQ0 are ac tive and contr olled by CE# a nd OE#. The d ata I/

O pins DQ14–DQ8 are tri-stated, and the DQ15 pin is used as an input for the

LSB (A-1 ) address function .

Requirements for Reading Array Data

To read array data from the outputs, the system must drive the CE# and OE#

pins to VIL. CE# is the power control and selec ts the device. OE# is the output

control and gates a r ray data to the outp ut pins. WE# should remain at VIH. The

BYTE# pin determines whether the device outputs array data in words or bytes.

The internal state m achine is set for reading array data up on device power-up,

or after a hardware reset. This ensures that no spurious alteration of the memory

content occurs during the power transition. No command is necessary in this

mode t o obtain a rra y data. Stan dard micr oprocessor read cy cles that a ssert v alid

addresses on the device address inputs produce valid data on the device data

outpu ts . Each bank remains enab l ed for read access u n t il the command reg i ster

contents are altered.

Refer to the AC R ead-Only Operations table for timing specifications and to 14 for

the timing diagram. ICC1 in the DC Characteristics table represents the active cur-

rent specification for reading arr a y data.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

For program operations, the BYTE# pin determines whether the device accepts

program data in bytes or words. Refer to “Word/Byte Configuration” for more

information.

The device features an Unlock Bypass mode to facilitate faster programming.

Once a bank enters the Unlock Bypass mode, only two write cycles are required

to program a wor d or byte, inste ad of four. Th e “Byte /Wor d Pro gram Comm an d

Sequence” section has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sec tor, mu ltiple sectors, or the entire d evice.

Tables 3 and 4 ind i cat e the address space that each sector occupies. Similarly, a

“sector address” is the address bits required to uniquely select a sector. The

“Command Definitions” section has details on erasing a sector or the entire chip,

or suspending/resuming the erase operation.

The device address space is divided into four banks. A “bank address” is the ad-

dress bits required t o uniquely select a bank.

ICC2 in the DC Characteristics table represents the active current specification for

the write mode . The AC Characteristics section c ontains timing specification ta-

bles and timing diagrams for write operations.

12 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Accelerated Program Operation

The device offers acceler ated program operations through the ACC function. This

is one of two functions provided by the WP#/ACC pin. This function is primar ily

intended to allow faster manufacturing throughput at the factory.

If the system a sserts VHH on this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sectors,

and uses the hig her voltage on the pin to reduce the time requir ed for prog ram

operations. The system would use a two-cycle program command sequence as

required by the Unlock Bypa ss mode. Removing VHH from the WP#/ACC pin re-

turns the device to normal operation. Note that VHH must not be asserted on

WP#/ACC for operations other than accelerated programming, or device damage

may result. In addition, the WP#/ACC pin must not be left floating or uncon-

nected; inconsistent behavior of the device may result. See “Write Protect

(WP#)” on page 22. for related information.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

read cycle timings apply in this mode. Refer to t h e Au t o se l ect Mode and Autose-

lect Command Sequence sections for more information.

Simultaneous Read/Write Operations with Zero Latency

This device is capable of reading data f rom one bank of memory while program-

ming or erasing in the other bank of memory. An erase operation may also be

suspended to read from or program to another location within the same bank (ex-

cept the sector being er ased). Fi gure 21 shows how read and wr ite cycles may be

initiated for simultaneous operation with zero latency. ICC6 and ICC7 in the DC

Characteristics table represent the current specifications for read-while-program

and read-while-erase, respectively.

May 21, 2004 S29JL032HA0 S29JL032H 13

ADVANCE INFORMATION

Standby Mode

When the system is not readi ng or writing to the devic e, it can place the devic e

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CM OS s ta ndby mode when the CE# and RESET# pins are

both held at VCC ± 0. 3 V. (Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not within VCC ± 0.3 V, the device

will be in the standby mode, but the standby cur rent will be grea ter. The device

requires standard access time (tCE) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

ICC3 in the DC Characteri stics table represents the standby current specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. St andard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. ICC5 in t he DC Characteristics table r epresents the automatic slee p

mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a ha rdware method of res etting the device to reading

array data. When the RESET# pin is driven low for at least a period o f tRP, the

device immediately terminates any operation in progress, tristates all output

pins, and ig nores a ll read /wri te com mands for th e dur ation of t he RES ET# pul se.

The device also resets the inter n al st at e machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accep t an o t h er command seque n ce , to ensure data integrity.

Current is reduced for the duration of the RESET# puls e. When RESET# is hel d

at V SS±0.3 V, the device draws CMOS stan dby c urr ent (ICC4). If RESET# is held

at VIL but not within VSS±0.3 V, the standby current will be greater.

The RESET# pin ma y be tied to the system re set circu itry. A system reset would

thus also reset the Flash memory, enabling the system to read the boot-up firm-

ware from the Flash mem ory.

If RESET# is asserted during a program or erase operation, the RY/BY# pin re-

mains a “0” (busy) until the inte rnal r es et operation is complete , which requir es

a time of tREADY (during Embedded Algorithms). The system can thus monitor RY/

BY# to determine whether the reset operation is complete. If RESET# is asserted

when a program or erase operation is not executing (RY/BY# pin is “1”), the reset

operation is completed within a time of tREADY (not during Embedded Algorithms).

The syst em can read data tRH after the RESET# pin returns to VIH.

Refer to the AC Characteristics tab les for RESET# parameters and to 15 for the

timin g diagram.

14 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Output Disable Mode

When the OE# input is at VIH, output from the device is disabled. The output pins

are placed in the high impedance state.

Ta bl e 2 . S29JL032H Bank Architecture

Device

Model

Numbers

Bank 1 Bank 2 Bank 3 Bank 4

Megabits Sector Size Megabits Sector Size Megabits Sector Size Megabits Sector Size

01, 02 4 Mbit

Eight

8 Kbyte/

4 Kw ord,

seven

64 Kbyte/

32 Kword

12 Mbit Twenty-four

64 Kbyte/

32 Kword 12 Mbit Twenty-four

64 Kbyte/

32 Kword 4 Mbit Eight 64 Kbyte/

32 Kword

Device

Model

Numbers

Bank 1 Bank 2

Megabits Sector Sizes Megabits Sector Sizes

21, 22 4 Mbit Eight 8 Kbyte/4 Kw ord,

seven 64 Kbyte/32 Kword 28 Mbit Fifty-six

64 Kbyte/32 Kw ord

31, 32 8 Mbit Eight 8 Kbyte/4 Kw ord,

fifteen 64 Kbyte/32 Kword 24 Mbit Forty-eight

64 Kbyte/32 Kw ord

41, 42 16 Mbit Eight 8 Kbyte/4 Kword,

thirty-one 64 K byte/32 Kword 16 Mbit Thirty-two

64 Kbyte/32 Kw ord

May 21, 2004 S29JL032HA0 S29JL032H 15

ADVANCE INFORMATION

Ta b l e 3 . S29JL032H Sector Addresses - Top Boot Devices

S29JL032H (Model 41)

S29JL032H (Model 31)

S29JL032H (Model 21)

S29JL032H (Model 01)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

Bank 2

Bank 4

SA0 000000xxx 64/32 000000h-00FFFFh 000000h-07FFFh

SA1 000001xxx 64/32 010000h-01FFFFh 008000h-0FFFFh

SA2 000010xxx 64/32 020000h-02FFFFh 010000h-17FFFh

SA3 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh

SA4 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh

SA5 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh

SA6 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh

SA7 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh

Bank 3

SA8 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh

SA9 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh

SA10 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh

SA11 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

SA12 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh

SA13 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

SA14 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh

SA15 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

SA16 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh

SA17 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh

SA18 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh

SA19 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh

SA20 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

SA21 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

SA22 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

SA23 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

SA24 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

SA25 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

SA26 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

SA27 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

SA28 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

SA29 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

SA30 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

SA31 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh

16 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Bank 1

Bank 2 (cont’d)

Bank 2

SA32 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh

SA33 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh

SA34 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh

SA35 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh

SA36 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh

SA37 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh

SA38 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh

SA39 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh

SA40 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh

SA41 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh

SA42 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh

SA43 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

SA44 101100xxx 64/32 2C0000h-2CFFFFh 160000h-167FFFh

SA45 101101xxx 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

SA46 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh

SA47 101111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

Bank 1

SA48 110000xxx 64/32 300000h-30FFFFh 180000h-187FFFh

SA49 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh

SA50 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh

SA51 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh

SA52 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

SA53 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

SA54 110110xxx 64/32 360000h-36FFFFh 1B0000h-1BFFFFh

SA55 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

Bank 1

SA56 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh

SA57 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

SA58 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1DFFFFh

SA59 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

SA60 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

SA61 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

SA62 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

SA63 111111000 8/4 3F0000h-3F1FFFh 1F8000h-1F8FFFh

SA64 111111001 8/4 3F2000h-3F3FFFh 1F9000h-1F9FFFh

SA65 111111010 8/4 3F4000h-3F5FFFh 1FA000h-1FAFFFh

SA66 111111011 8/4 3F6000h-3F7FFFh 1FB000h-1FBFFFh

SA67 111111100 8/4 3F8000h-3F9FFFh 1FC000h-1FCFFFh

SA68 111111101 8/4 3FA000h-3FBFFFh 1FD000h-1FDFFFh

SA69 111111110 8/4 3FC000h-3FDFFFh 1FE000h-1FEFFFh

SA70 111111111 8/4 3FE000h-3FFFFFh 1FF000h-1FFFFFh

Table 3. S29JL032H Sector Addresses - Top Boot Devices (Continued)

S29JL032H (Model 41)

S29JL032H (Model 31)

S29JL032H (Model 21)

S29JL032H (Model 01)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

May 21, 2004 S29JL032HA0 S29JL032H 17

ADVANCE INFORMATION

Ta bl e 4 . S29JL032H Sector Addresses - Bottom Boot Devices

S29JL032H (Model 42)

S29JL032H (Model 32)

S29JL032H (Model 22)

S29JL032H (Model 02)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

Bank 1

SA0 000000000 8/4 000000h-001FFFh 000000h-000FFFh

SA1 000000001 8/4 002000h-003FFFh 001000h-001FFFh

SA2 000000010 8/4 004000h-005FFFh 002000h-002FFFh

SA3 000000011 8/4 006000h-007FFFh 003000h-003FFFh

SA4 000000100 8/4 008000h-009FFFh 004000h-004FFFh

SA5 000000101 8/4 00A000h-00BFFFh 005000h-005FFFh

SA6 000000110 8/4 00C000h-00DFFFh 006000h-006FFFh

SA7 000000111 8/4 00E000h-00FFFFh 007000h-007FFFh

SA8 000001xxx 64/32 010000h-01FFFFh 008000h-00FFFFh

SA9 000010xxx 64/32 020000h-02FFFFh 010000h-017FFFh

SA10 000011xxx 64/32 030000h-03FFFFh 018000h-01FFFFh

SA11 000100xxx 64/32 040000h-04FFFFh 020000h-027FFFh

SA12 000101xxx 64/32 050000h-05FFFFh 028000h-02FFFFh

SA13 000110xxx 64/32 060000h-06FFFFh 030000h-037FFFh

SA14 000111xxx 64/32 070000h-07FFFFh 038000h-03FFFFh

Bank 2

SA15 001000xxx 64/32 080000h-08FFFFh 040000h-047FFFh

SA16 001001xxx 64/32 090000h-09FFFFh 048000h-04FFFFh

SA17 001010xxx 64/32 0A0000h-0AFFFFh 050000h-057FFFh

SA18 001011xxx 64/32 0B0000h-0BFFFFh 058000h-05FFFFh

SA19 001100xxx 64/32 0C0000h-0CFFFFh 060000h-067FFFh

SA20 001101xxx 64/32 0D0000h-0DFFFFh 068000h-06FFFFh

SA21 001110xxx 64/32 0E0000h-0EFFFFh 070000h-077FFFh

SA22 001111xxx 64/32 0F0000h-0FFFFFh 078000h-07FFFFh

Bank 2

SA23 010000xxx 64/32 100000h-10FFFFh 080000h-087FFFh

SA24 010001xxx 64/32 110000h-11FFFFh 088000h-08FFFFh

SA25 010010xxx 64/32 120000h-12FFFFh 090000h-097FFFh

SA26 010011xxx 64/32 130000h-13FFFFh 098000h-09FFFFh

SA27 010100xxx 64/32 140000h-14FFFFh 0A0000h-0A7FFFh

SA28 010101xxx 64/32 150000h-15FFFFh 0A8000h-0AFFFFh

SA29 010110xxx 64/32 160000h-16FFFFh 0B0000h-0B7FFFh

SA30 010111xxx 64/32 170000h-17FFFFh 0B8000h-0BFFFFh

SA31 011000xxx 64/32 180000h-18FFFFh 0C0000h-0C7FFFh

SA32 011001xxx 64/32 190000h-19FFFFh 0C8000h-0CFFFFh

SA33 011010xxx 64/32 1A0000h-1AFFFFh 0D0000h-0D7FFFh

SA34 011011xxx 64/32 1B0000h-1BFFFFh 0D8000h-0DFFFFh

SA35 011100xxx 64/32 1C0000h-1CFFFFh 0E0000h-0E7FFFh

SA36 011101xxx 64/32 1D0000h-1DFFFFh 0E8000h-0EFFFFh

SA37 011110xxx 64/32 1E0000h-1EFFFFh 0F0000h-0F7FFFh

SA38 011111xxx 64/32 1F0000h-1FFFFFh 0F8000h-0FFFFFh

18 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Bank 2

Bank 2 (cont’d)

Bank 3

SA39 100000xxx 64/32 200000h-20FFFFh 100000h-107FFFh

SA40 100001xxx 64/32 210000h-21FFFFh 108000h-10FFFFh

SA41 100010xxx 64/32 220000h-22FFFFh 110000h-117FFFh

SA42 100011xxx 64/32 230000h-23FFFFh 118000h-11FFFFh

SA43 100100xxx 64/32 240000h-24FFFFh 120000h-127FFFh

SA44 100101xxx 64/32 250000h-25FFFFh 128000h-12FFFFh

SA45 100110xxx 64/32 260000h-26FFFFh 130000h-137FFFh

SA46 100111xxx 64/32 270000h-27FFFFh 138000h-13FFFFh

SA47 101000xxx 64/32 280000h-28FFFFh 140000h-147FFFh

SA48 101001xxx 64/32 290000h-29FFFFh 148000h-14FFFFh

SA49 101010xxx 64/32 2A0000h-2AFFFFh 150000h-157FFFh

SA50 101011xxx 64/32 2B0000h-2BFFFFh 158000h-15FFFFh

SA51 101100xxx 64/32 2C0000h-2CFFFFh 160000h-167FFFh

SA52 101101xxx 64/32 2D0000h-2DFFFFh 168000h-16FFFFh

SA53 101110xxx 64/32 2E0000h-2EFFFFh 170000h-177FFFh

SA54 110111xxx 64/32 2F0000h-2FFFFFh 178000h-17FFFFh

SA55 111000xxx 64/32 300000h-30FFFFh 180000h-187FFFh

SA56 110001xxx 64/32 310000h-31FFFFh 188000h-18FFFFh

SA57 110010xxx 64/32 320000h-32FFFFh 190000h-197FFFh

SA58 110011xxx 64/32 330000h-33FFFFh 198000h-19FFFFh

SA59 110100xxx 64/32 340000h-34FFFFh 1A0000h-1A7FFFh

SA60 110101xxx 64/32 350000h-35FFFFh 1A8000h-1AFFFFh

SA61 110110xxx 64/32 360000h-36FFFFh 1B0000h-1B7FFFh

SA62 110111xxx 64/32 370000h-37FFFFh 1B8000h-1BFFFFh

Bank 4

SA63 111000xxx 64/32 380000h-38FFFFh 1C0000h-1C7FFFh

SA64 111001xxx 64/32 390000h-39FFFFh 1C8000h-1CFFFFh

SA65 111010xxx 64/32 3A0000h-3AFFFFh 1D0000h-1D7FFFh

SA66 111011xxx 64/32 3B0000h-3BFFFFh 1D8000h-1DFFFFh

SA67 111100xxx 64/32 3C0000h-3CFFFFh 1E0000h-1E7FFFh

SA68 111101xxx 64/32 3D0000h-3DFFFFh 1E8000h-1EFFFFh

SA69 111110xxx 64/32 3E0000h-3EFFFFh 1F0000h-1F7FFFh

SA70 111111xxx 64/32 3F0000h-3F1FFFh 1F8000h-1FFFFFh

Table 4. S29JL032H Sector Addresses - Bottom Boot Devices (Continued)

S29JL032H (Model 42)

S29JL032H (Model 32)

S29JL032H (Model 22)

S29JL032H (Model 02)

Sector Sector Address

A20–A12

Sector Size

(Kbytes/

Kwords)

(x8)

Address Range

(x16)

Address Range

May 21, 2004 S29JL032HA0 S29JL032H 19

ADVANCE INFORMATION

Autoselect Mode

The autoselect mode provides manufacturer and device identification, and sector

protection verificati on, through identifier codes out put on DQ 7–DQ0 . This mode

is primarily intended for programming equipment to automatically match a device

to be programmed with its corresponding programming algorithm. However, the

autos elect co de s can a lso be acces sed in-syst em th roug h the co mma nd reg iste r.

When using programming e quipment, the autose lect mode requires VID on ad-

dress pin A9. Address pins must be as shown in Table 5. In addition, when

verifying sector protection, the sector address must appear on the appropriate

highest order address bits. Table 5 shows the remaining address bits that are

don’t care. When all necessary bits have been set as required, the programming

equipmen t may then r ead the c or res pond ing identifier code on DQ7–DQ0. How-

ever, the au toselect codes can als o be accesse d in-syst em through the command

without access to high voltage on the A9 pin. The command sequence is illus-

trated in Table 13. Note that if a Bank Address (BA) on address bits A20, A19 and

A18 is asserted during the third write cycle of the autoselect command, the host

system can read autoselect data from that bank and then immediately read array

data from another bank, without exiting the autoselect mode.

To access th e autoselec t codes in-syst em, the host system can issue the autose -

lect comm and via the comma nd register, a s shown in Table 13. This method does

not require VID. Refer to the Autoselect Command Sequence section for more

information.

Table 5. S29JL032H Autoselect Codes, (High Voltage Method)

Legend:

L = Logic Low = V

, H = Logic High = V

, BA = Bank Address, SA = Sector Address, X = Don’t care

Description CE# OE# WE#

A20

A12

A11

A10 A9

A7 A6

A4 A3 A2 A1 A0

DQ15 to DQ8 DQ7

DQ0

BYTE#

= VIH

BYTE#

= VIL

Manufa cturer ID:

Spansion Products L L H BA XVID X L X L L L L X X 01h

Device ID

(Models 01, 02)

Read Cycle 1

L L H BA XVID X

L L L H 22h

7Eh

Read Cycle 2 L H H H L 22h 0Ah

Read Cycle 3 L H H H H 22h 00h (bottom boot)

01h (top boot)

Device ID

(Models 21, 22) L L H BA XVID X L X X X L H 22h X56h (bottom boot)

55h (top boot)

Device ID

(Models 31, 32) L L H BA XVID X L X X X L H 22h X53h (bottom boot)

50h (top boot)

Device ID

(Models 41, 42) L L H BA XVID X L X X X L H 22h X5Fh (bottom boot)

5Ch (top boot)

Sector Protection

Verification L L H SA XVID X L X L L H L X X 01h (protected),

00h (unprotected)

SecSi Indicator Bit

(DQ6, DQ7) L L H BA XVID X L X L L H H X X

82h (fa ctory locked),

42h (customer

locked), 02h (not

factory/customer

locked)

20 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Sector/Sector Block Protection and Unprotection

Note: For the following dis cuss ion, the term “sector” app lies to both sectors and

sector blocks. A sector block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 6).

The hardware sector protec tion feature disable s both program and erase opera-

tions in any sector. The hardware sector unprotection feature re-enables both

program and erase operations in previously protected sectors. Sector protection/

unprotection can be implemented via two methods.

Ta b l e 6 . S29JL032H Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector A20–A12

Sector/

Sector Block Size

SA0 000000XXX 64 Kbytes

SA1-SA3

000001XXX,

000010XXX

000011XXX

192 (3x64) Kbytes

SA4-SA7 0001XXXXX 256 (4x64) Kbytes

SA8-SA11 0010XXXXX 256 (4x64) Kbytes

SA12-SA15 0011XXXXX 256 (4x64) Kbytes

SA16-SA19 0100XXXXX 256 (4x64) Kbytes

SA20-SA23 0101XXXXX 256 (4x64) Kbytes

SA24-SA27 0110XXXXX 256 (4x64) Kbytes

SA28-SA31 0111XXXXX 256 (4x64) Kbytes

SA32-SA35 1000XXXXX 256 (4x64) Kbytes

SA36-SA39 1001XXXXX 256 (4x64) Kbytes

SA40-SA43 1010XXXXX 256 (4x64) Kbytes

SA44-SA47 1011XXXXX 256 (4x64) Kbytes

SA48-SA51 1100XXXXX 256 (4x64) Kbytes

SA52-SA55 1101XXXXX 256 (4x64) Kbytes

SA56-SA59 1110XXXXX 256 (4x64) Kbytes

SA60-SA62

111100XXX,

111101XXX,

111110XXX

192 (3x64) Kbytes

SA63 111111000 8 Kbytes

SA64 111111001 8 Kbytes

SA65 111111010 8 Kbytes

SA66 111111011 8 Kbytes

SA67 111111100 8 Kbytes

SA68 111111101 8 Kbytes

SA69 111111110 8 Kbytes

SA70 111111111 8 Kbytes

May 21, 2004 S29JL032HA0 S29JL032H 21

ADVANCE INFORMATION

Ta bl e 7 . S29JL032H Bottom Boot Sector/Sector Block Addresses for Protection/Unprotection

Sector protect/Sector Unprotect requires VID on the RESET# pin only , and can be

implemented either in-system or via programming equipment. Figure 2 shows

the algorithms and Fig ure 26 s hows the timing diagram. For sector unprotect, all

unprotected sectors must first be protected prior to the first sector unprotect

write cycle. Note that the sector unprotect algorithm unprotects all sectors in par-

allel. All previously protected sectors must be individually re-protected. To

change data in protected sectors efficiently , the temporary sector unprotect func-

tion is available. See “Temporary Sector Unprotect” .

The device is shipped with all sectors unprotected. Optional Spansion program-

ming service en able programming and protec ting sectors at the factor y prior to

shipping the device. Contact your local sales office for details.

It is possible to determine whether a sector is protected or unprotected. See the

Autoselect Mode section for details.

Sector A20–A12

Sector/Sector Block

Size

SA70 111111XXX 64 Kbytes

SA69-SA67

111110XXX,

111101XXX,

111100XXX

192 (3x64) Kbytes

SA66-SA63 1110XXXXX 256 (4x64) Kbytes

SA62-SA59 1101XXXXX 256 (4x64) Kbytes

SA58-SA55 1100XXXXX 256 (4x64) Kbytes

SA54-SA51 1011XXXXX 256 (4x64) Kbytes

SA50-SA47 1010XXXXX 256 (4x64) Kbytes

SA46-SA43 1001XXXXX 256 (4x64) Kbytes

SA42-SA39 1000XXXXX 256 (4x64) Kbytes

SA38-SA35 0111XXXXX 256 (4x64) Kbytes

SA34-SA31 0110XXXXX 256 (4x64) Kbytes

SA30-SA27 0101XXXXX 256 (4x64) Kbytes

SA26-SA23 0100XXXXX 256 (4x64) Kbytes

SA22–SA19 0011XXXXX 256 (4x64) Kbytes

SA18-SA15 0010XXXXX 256 (4x64) Kbytes

SA14-SA11 0001XXXXX 256 (4x64) Kbytes

SA10-SA8

000011XXX,

000010XXX,

000001XXX

192 (3x64) Kbytes

SA7 000000111 8 Kbytes

SA6 000000110 8 Kbytes

SA5 000000101 8 Kbytes

SA4 000000100 8 Kbytes

SA3 000000011 8 Kbytes

SA2 000000010 8 Kbytes

SA1 000000001 8 Kbytes

SA0 000000000 8 Kbytes

22 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Write Protect (WP#)

The W rite Protect function provides a hardware method of protecting certain boot

sectors with ou t using V ID. This function is one of two p rovided by t he WP#/ACC

pin.

If the system asserts VIL on the WP#/ACC pin, the de vice disables program and

erase functions in the two outermost 8 Kbyte boot sectors independently of

whether those sectors were protected or unprotected using the method described

in “Sector/Sector Block Protection and Unprotection”. The two outermost 8 Kbyte

boot sectors are the two sectors containing the lowest addresses in a bottom-

boot-configured device, or the two sectors containing the highest addresses in a

top-boot-configured device.

If the system as serts VIH on the WP#/ACC pin, the device reverts to whether the

two outermost 8K Byte boot sectors were last set to be protected or unprotected.

That is, sector protection or unprotection for these two sectors depends on

whether they wer e last pr otected or unprotected using the method de scribed in

“Sector/Sector Block Protection and Unprotection”.

Note that the WP#/ACC pin must not be left floating or unconnected; inconsistent

behavior of the device may result.

Ta b l e 8 . WP#/ACC Modes

Temporary Sector Unprotect

(Note: For the following discussion, the term “sector” applies to both sectors and

sector blocks. A sector block consists of two or more adjacent sectors that are

protected or unprotected at the same time (see Table 6 and Table 7).

This feature allows temporary unprotection of previously protected sectors to

change data in-system. The Temporary Sector Unprotect mode is activated by

setting the RESET# pin to VID. During this mode, formerly protected sectors can

be programmed or erased by selecting the sector addresses. Once VID is removed

from the RESET# pin, all the previously protected sectors are protected ag ain.

shows t he algorithm, and 25 shows the t iming dia grams, for this feature. If t he

WP#/ACC pin is at VIL,

the two outermost boot sectors

will remain protected during

the Temporary sector Unprotect mode.

WP# Input Voltage

Device

Mode

Disables programming and erasing in the two outermost boot sectors

Enables programming and er asing in the two outermost boo t sectors, dependent on

whether th ey were last protected o r unprotected.

Enables accelerated programming (ACC). See “Accelerated Program Operation” on

page 12..

May 21, 2004 S29JL032HA0 S29JL032H 23

ADVANCE INFORMATION

Figure 1. Temporary Sector Unprotect Operation

START

Perform Erase or

Program Operations

RES E T# = V

Temporary Sector

Unprotect Com pleted

(Note 2)

RESET# = V

(Note 1)

Notes:

1. All protected sectors unprotected (If WP#/ACC =

VIL, the outermost two boot sectors will remain

protected).

2. All previously protected sectors are protected once

again.

24 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Figure 2. In-System Sector Protect/Unprotect Algorithms

Sector Protect:

Write 60h to sector

address with

A6 = 0, A1 = 1,

A0 = 0

Set up sector

address

Wait 150 µs

Verify Sector

Protect: Write 40h

to sector address

with A6 = 0,

A1 = 1, A0 = 0

Read from

sector address

with A6 = 0,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 ms

First Write

Cycle = 60h?

Data = 01h?

Remove VID

from RESET#

Write reset

command

Sector Protect

complete

Yes

PLSCNT

= 25?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode No

Sector Unprotect:

Write 60h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Set up first sector

address

Wait 15 ms

Verify Sector

Unprotect: Write

40h to sector

address with

A6 = 1, A1 = 1,

A0 = 0

Read from

sector address

with A6 = 1,

A1 = 1, A0 = 0

START

PLSCNT = 1

RESET# = VID

Wait 1 ms

Data = 00h?

Last sector

verified?

Remove VID

from RESET#

Write reset

command

Sector Unprotect

complete

Yes

PLSCNT

= 1000?

Yes

Device failed

Increment

PLSCNT

Temporary Sector

Unprotect Mode

No All sectors

protected?

Yes

Protect all sectors:

The indicated portion

of the sector protect

algorithm must be

performed for all

unprotected sectors

prior to issuing the

first sector

unprotect address

Set up

next sector

address

Yes

Sector Protect

Algorithm Sector Unprotect

Algorithm

First Write

Cycle = 60h?

Protect another

sector?

Reset

PLSCNT = 1

May 21, 2004 S29JL032HA0 S29JL032H 25

ADVANCE INFORMATION

SecSi™ (Secured Silicon) Sector

Flash Memory Region

The SecSi (Secured Silicon) Sector feature provides a Flash memor y region that

enables permanent part identification through an Electronic Serial Number

(ESN). The SecSi Sector is 256 bytes in length, and uses a SecSi Sector Indicator

Bit (DQ7) to indicate whether or not the SecSi Sector is locked when shipped from

the factory. This bit is permanently set at the factory and cannot be changed,

which prevents cloning of a factory locked part . This ensures the security of the

ESN once the product is shipped to the field.

The product is available with the Se cSi Sector either factor y locked or customer

lockable. The fa ctory-locked version is always protected when sh ipped from the

factory, and has the SecSi (Secure d Silico n) Sect or Indica tor Bit perman ently se t

to a “1.” The customer-lockable version is shipped with the SecSi Sector unpro-

tected, allowing custome rs to utilize the tha t sector in any manner they choose.

The customer-lockable version has the SecSi (Sec ured Silicon) Sector Indicator

Bit permanently set to a “0.” Thus, the SecSi Sec tor Indicator Bit p revents cus-

tomer-lockable devices from being used to replace devices that are factory

locked. The SecSi Customer Indicator Bit (DQ6) is permanently set to 1 if the part

has been customer locked, permanently set to 0 if the part has been factory

locked, and is 0 if customer lockable.

The system accesses the SecSi Sector Secure through a command sequence (see

“Enter SecSi™ Sec tor/Exit SecS i Sector Comm and Sequence ” ). After the system

has written the Enter SecSi Sector command sequence, it may read the SecSi

Sector by using the addresses normally occupied by the boot sectors. This mode

of operation continues until the system issues the Exit SecSi Sector command se-

quence, or unt il powe r is removed from the device. On powe r-up, or following a

hardware reset, the device reve rts to sending co mmands to the fir st 256 bytes of

Sector 0. Note that the ACC function and unlock bypass modes are not available

when the SecSi Sector is enabled.

Factory Locked: SecSi Sector Programmed and Protected At the Factory

In a factory locked device, the SecSi Sector is protected when the device is

shipped from the factory. The SecSi Sector cannot be modified in any way. The

device is preprogrammed with both a random number and a secure ESN. The 8-

word random number is at addresses 000000h–000007h in word mode (or

000000h–00000Fh in byte mode). T he s ec ure ESN is programmed in the next 8

words at addresses 000008h–00000Fh (or 000010h–00001Fh in byte mode). The

device is available preprogr ammed with one of the following:

A random, secure ESN only

Customer code through Spansion programmi ng services

Both a random, secure ESN and customer code t hrough Spansion program-

ming services

Contact an your local sales office for details on using Spansion programming

services.

Customer Lockable: SecSi Sector NOT Programmed or Protected At the Factory

If the se curity feature is no t re quired, the SecSi Secto r can b e treated as an ad-

ditional Flash memory space. The SecSi Sector can be read any number of times,

but can be programmed and locked only once. Note that the accelerated pro-

gramming (ACC) and unlock bypass functions are not available when

programming the SecSi Sector.

26 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

The SecSi Sector area can be protected using one of the following procedures:

Write the three-cycle Enter SecSi Sector Region command sequence, and

then follow the in-system sector protect algorithm as shown in Figure 2, ex-

cept that RESET# may be at either VIH or VID. This allows in-system protec-

tion of the SecSi Sector Region without raising any device pin to a high

voltage. Note that this m e thod is only a pplicable to the SecSi Se ctor.

To verify the protect/unprotect status of the SecSi Sector, follow the algo-

rithm shown in Figure 3.

Once the SecSi Sector is locked and verified, the system must write the Exit SecSi

Sector Region command sequence to return to reading and writing the remainder

of the array.

The S e cSi S ect or lo ck must be used w ith cau tion si nce , onc e lo cked, the re i s no

procedure available for unlocking the SecSi Sector area and none of the bits in

the SecSi Se ct o r memory space can be modified in any way.

Figure 3. SecSi Sector Protect Verify

Hardware Data Protection

The command sequence requirement of unlock cycles for programming or erasing

provides data protection against inadvertent writes (refer to Table 13 for com-

mand definitions). In addition, the following hardware data protection measures

prevent accidental erasure or programming, which might otherwise be caused by

spurious system level signals during VCC power-up and power-down transitions,

or from system noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not accept any write cycles. This pro-

tects d at a d u ring VCC power-up and power-down. The command register and all

internal program/erase circuits are disabled, and the device resets to the read

Write 60h to

any address

Write 40h to SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

START

RESET# =

VIH or VID

Wait 1 ms

Read from SecSi

Sector address

with A6 = 0,

A1 = 1, A0 = 0

If data = 00h,

SecSi Sector is

unprotected.

If data = 01h,

SecSi Sector is

protected.

Remove VIH or VID

from RESET#

Write reset

command

SecSi Sector

Protect Verify

complete

May 21, 2004 S29JL032HA0 S29JL032H 27

ADVANCE INFORMATION

mode. Subsequent writes are ignored until VCC is greater than VLKO. The system

must provide the proper signals to the control pins to prevent unintentional writes

when VCC is gr eater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write

cycle.

Logical Inhibit

W rite cycles are inhibited by holding any one of OE# = VIL, CE# = VIH or WE# =

VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a

logical one.

Power-Up Write Inhibit

If WE# = CE# = VIL a nd OE# = VIH during power up, the device does not accept

commands on the rising edge of WE#. The internal state machine is automatically

reset to the read mode on power-up.

Common Flash Memory Interface (CFI)

The Comm on Fl ash Int erface (CF I) spec if icati on outl ine s devi ce and host syste m

software interrogation handshake, which allows specific vendor-specified soft-

ware algorithms to be used for entire families of devices. Software support can

then be device-independent, JEDEC ID-independent, and forward- and back-

ward-compatible for the specified flash device families. Flash vendors can

standardize their existing interfaces for long-term compatibility.

This device enters the CFI Query mode when the system writes the CFI Query

command, 98h, to address 55h in word mode (or address AAh in byte mode), any

time the device is ready to read array data. The system can read CFI information

at the addresses given in Tables 9–12. To terminate reading CFI data, the system

must write the reset command.The CFI Query mode is not accessible when the

device is executing an Embedded Program or embedded Er ase algorithm.

The system can also write the CFI query command when the device is in the au-

toselect mode. The device enters the CFI query mode, and the system can read

CFI data at the addresses given in Tables 9–12. The system must write the reset

command to reading arr ay data.

For further information, please refer to the CFI Spe cifi cation and CF I Public ation

100. Contact your local sales office for copies of these documents.

28 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Ta b l e 9 . CFI Query Identification String

Ta b l e 1 0 . System Interface String

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

10h

11h

12h

20h

22h

24h

0051h

0052h

0059h Query Unique ASCII string “QRY”

13h

14h 26h

28h 0002h

0000h P rim ary OEM C ommand Set

15h

16h 2Ah

2Ch 0040h

0000h Address for Primary Extended Table

17h

18h 2Eh

30h 0000h

0000h Alternate OEM Command Set (00h = none exists)

19h

1Ah 32h

34h 0000h

0000h Address for Alternate OEM Extended Table (00h = none exists)

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

1Bh 36h 0027h V

Min. (write/erase)

D7–D4: volt, D3–D0: 100 millivolt

1Ch 38h 0036h V

Max. (write /erase)

D7–D4: volt, D3–D0: 100 millivolt

1Dh 3Ah 0000h V

Min. voltage (0 0h = no V

pin present)

1Eh 3Ch 0000h V

Max. voltage (00h = no V

pin present)

1Fh 3Eh 0003h Typical timeout per single byte/word write 2

µs

20h 40h 0000h Typical timeout for Min. size buffer write 2

s (00h = not supported)

21h 42h 0009h Typical timeout per individual block erase 2

22h 44h 0000h Typical timeout for full ch ip erase 2

ms (00h = not supported)

23h 46h 0005h Max. timeout for byte/word write 2

times typical

24h 48h 0000h Max. timeout for buffer write 2

times typical

25h 4Ah 0004h Max. timeout per individual block erase 2

times typical

26h 4Ch 0000h Max. timeout for full chip erase 2

times typical (00h = not supported)

May 21, 2004 S29JL032HA0 S29JL032H 29

ADVANCE INFORMATION

Ta bl e 1 1 . Device Geometry Definition

Ta b l e 1 2 . Primary Vendor-Specific Extended Query

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

27h 4Eh 0016h Device Size = 2

byte

28h

29h 50h

52h 0002h

0000h Flash Device Interface description (refer to CFI publication 100)

2Ah

2Bh 54h

56h 0000h

0000h Max. number of byte in multi-byte write = 2

(00h = not supported)

2Ch 58h 0002h Number of Er ase Block Regions within device

2Dh

2Eh

2Fh

30h

5Ah

5Ch

5Eh

60h

0007h

0000h

0020h

0000h

Erase Block Region 1 Information

(refer to the CFI specification or CFI publication 100)

31h

32h

33h

34h

62h

64h

66h

68h

003Eh

0000h

0001h

Erase Block Region 2 Information

(refer to the CFI specification or CFI publication 100)

35h

36h

37h

38h

6Ah

6Ch

6Eh

70h

0000h

Erase Block Region 3 Information

(refer to the CFI specification or CFI publication 100)

39h

3Ah

3Bh

3Ch

72h

74h

76h

78h

0000h

Erase Block Region 4 Information

(refer to the CFI specification or CFI publication 100)

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description

40h

41h

42h

80h

82h

84h

0050h

0052h

0049h Query-unique ASCII string “PRI”

43h 86h 0031h Major version number, ASCII (reflects modifications to the silicon)

44h 88h 0033h Minor version number, ASCII (reflects modifications to the CFI table)

45h 8Ah 000Ch Address Sensitive Unlock (Bits 1-0)

0 = Required, 1 = Not R equired

Silicon Revision Number (Bits 7-2)

46h 8Ch 0002h Erase Suspend

0 = Not Supported, 1 = To Read Only, 2 = To Read & Write

47h 8Eh 0001h Sector Protect

0 = Not Supported, X = Number of sectors in per group

48h 90h 0001h Sector Tem p orary Unprotect

00 = Not Supported, 01 = Supported

49h 92h 0004h Sector Protect/Unprotect scheme

01 =29F040 mode, 02 = 29F016 mode, 03 = 29F400, 04 = 29LV800

mode

30 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

4Ah 94h 00XXh

Number of sectors (excluding Bank 1)

XX = 38 (models 01 , 02 , 21, 22 )

XX = 30 (models 31 , 32 )

XX = 20 (models 41 , 42 )

4Bh 96h 0000h Burst Mode Type

00 = Not Supported, 01 = Supported

4Ch 98h 0000h Pa ge Mode Type

00 = Not Supported, 01 = 4 Word Page, 02 = 8 Word Page

4Dh 9Ah 0085h ACC (Acceleration) Supply Minimum

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Eh 9Ch 0095h ACC (Acceleration) Supply Maximu m

00h = Not Supported, D7-D4: Volt, D3-D0: 100 mV

4Fh 9Eh 000Xh Top/Bottom Boot Sector Flag

02h = Bottom Bo ot Device, 03h = Top Boot Device

50h A0h 0001h Program Suspend

0 = Not supported, 1 = Supported

57h AEh 000Xh

Bank Organization

00 = Data at 4Ah is z e ro

X = 4 (4 bank s, m odels 01, 02)

X = 2 (2 banks, all other models)

58h B0h 00XXh

Bank 1 Region Information - Number of sectors on B ank 1

XX = 0F (models 01, 02, 21, 22)

XX = 17 (models 31 , 32 )

XX = 27 (models 41 , 42 )

59h B2h 00XXh

Bank 2 Region Information - Number of sectors in Bank 2

XX = 18 (models 01 , 02 )

XX = 38 (models 21 , 22 )

XX = 30 (models 31 , 32 )

XX = 20 (models 41 , 42 )

5Ah B4h 00XXh Bank 3 Region Information - Number of sectors in Bank 3

XX = 18 (models 01 , 02 )

XX = 00 (all other models)

5Bh B6h 00XXh Bank 4 Region Information - Number of sectors in Bank 4

XX = 08 (models 01 , 02 )

XX = 00 (all other models)

Addresses

(Word Mode)

Addresses

(Byte Mode) Data Description (Continued)

May 21, 2004 S29JL032HA0 S29JL032H 31

ADVANCE INFORMATION

Command Definitions

Writing specific address and data commands or sequences into the command

sequences. Writing incorrect address and data values or writing them in the im-

proper sequence may place the device in an unknown state. A reset command is

then required to return the device to reading array data.

All addresses are latched on the falling edge of WE# or CE#, whichever happens

later. All data is latche d on the rising edge of WE# or CE#, whichever happens

first. R e fer to the AC Characteristics section fo r t iming diagrams.

Reading Array Data

The device is automatical ly set to reading array data after device power-up. No

commands are requir ed to retrieve data. Each bank is ready to read ar ray data

after completing an Embedded Program or Embedded Erase algorithm.

After the device accepts an Erase Suspend command, the corresponding bank

enters the erase-suspend-read mode, after which the system can read data from

any non-erase-suspended sector within the same bank. The system can read

array data using t he standard read timing, except that if it reads at an address

within erase-suspended sectors, the device outputs status data. After completing

a programming operation in the Erase Suspend mode, the system may once

again read array data with the same exception. See the Erase Suspend/Erase R e-

sume C ommands section for more information.

The system must issue the reset command to return a bank to the read (or erase-

suspend-read) mode if DQ5 goes high during an active program or erase opera-

tion, or if the bank is in the autoselect mode. See the next section, Res et

Command, for more information.

See also Requirements for Reading Array Data in the Device Bus O perati ons sec-

tion for more information. The Read-Only Operations table provides the read

parameters, and 14 shows the t i mi ng diagr am.

Reset Command

Writing the res et command r esets the b anks to th e read or erase-sus pend-read

mode. Address bits are don’t cares for this command.

The reset command may be written between the sequence cycles in an erase

command sequence before erasing begins. This resets the bank to which the sys-

tem was writing to the read mode. Once erasure begins, however, the device

ignores reset commands until the operation is complete.

The reset comm and may be written between the sequ ence cycles in a program

command sequence befo re programming be gins. This res ets the bank to whic h

the system was writing to the read mode. If the program com ma nd s equence is

written to a bank that is in the Erase Suspend mode, writing the reset command

returns that bank to the e rase-suspend-read mode. Onc e programming b egins,

however, the device ignores reset commands until the operation is complete.

The reset command may be written between the sequence cycles in an autoselect

command sequence. Once in the autosele ct mode, the reset command must be

written to return to the read mode. If a bank entered the autoselect mode while

in the Erase Suspend mode, writing the reset command returns that bank to the

erase-suspend-read mode.

32 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

If DQ5 goes high during a program or erase operation, writing the reset command

returns the banks to the read mode (or erase-suspend-read mode if that bank

was in Erase Suspend).

Autoselect Command Sequence

The autoselect command sequence allows the host system to access the manu-

facturer and device codes, and determine whether or not a sector is protected.

The autoselect command sequenc e may be written to an address within a bank

that is either in the read or erase-suspend-read mode. The autoselect command

may not be written while the device is actively programming or erasing in another

bank.

The autoselect command sequence is initiated by first writing two unlock cycles.

This is followed by a thir d write cycle that contains the bank address and the au-

toselect command. The bank then enters the autoselect mode. The system may

read any number of autoselect codes without reinitiating the command sequence.

Table 13 shows the address and data requirements. To determine sector protec-

tion information, the system must write to the appropriate bank address (BA) and

secto r address (SA). Tables 3 and 4 show the address rang e and b ank number

associated with each sector.

The system must write the reset command to return to the read mode (or era se-

sus pend-r ead mode i f the ba nk was previously in E rase Suspend).

Enter SecSi™ Sector/Exit SecSi Sector

Command Sequence

The SecS i S ector region provid es a s ec u re d da ta area containing a random , six -

teen-byte electronic serial number (ESN). The system can access the SecSi

Sector re gion by issu ing the three-cycle Enter SecSi Secto r command se qu e n ce.

The device continues to access the SecSi Sector region until the system issues

the four -c y cle Exit SecSi Se c tor com man d se quence . T he Exi t SecSi Sec tor com-

mand sequ ence returns the device to normal operation. The SecSi Sector is not

accessible when the device is executing an Embedded Program or embedded

Erase algorithm. Table 13 shows the address and data requirements for both com-

mand sequences. See also “SecSi™ (Secured Silicon) Sector

Flash Memory Region” for further information. Note that the ACC function and un-

lock bypass modes are not available when the SecSi Sector is enabled.

Byte/Word Program Command Sequence

The system may program the device by word or byte, depending on the state of

the BYTE# pin. Programming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write cycles, followed by the

program set-up command. The program address and data are written next, which

in turn initiate the Embedded Program algorithm. The system is not requir ed to

provide further c ontrols or timings. The device a utomatically provides interna lly

generated program pulses and verifies the programmed cell margin. Table 13

shows the address and data requirements for the byte program command

sequence.

When the Embedd ed Progra m algorithm is comp lete, that bank then retur ns to

the read mo de and addr esses a re no longer la tched. Th e system c an determi ne

the status of the program operation by using DQ7, DQ6, or RY/BY#. R efer to the

Write Operation Status section for information on these status bits.

May 21, 2004 S29JL032HA0 S29JL032H 33

ADVANCE INFORMATION

Any commands written to the device during the Embedded Program Algorithm

are ignor ed. Note that a hardware reset immed iately termina tes the prog ram

operation. The program command sequence should be reinitiated once that bank

has returned to the read mode, to ensure data integrity . Note that the SecSi Sec-

tor, autoselect, and CFI functions are unavailable when a program operation is in

progress.

Programming is allowed in any sequence and across sector boundaries. A bit

cannot be programmed from “0” back to a “1.” Attempting to do so may

cause that bank to set DQ5 = 1, or cause the DQ7 and DQ6 status bits to indicate

the oper ation was succ essful. However, a succeeding read will show that the data

is still “0.” Only erase operations can conv ert a “0” to a “1.”

Unlock Bypass Command Sequence

The unlock bypass feature allows the system to program bytes or words to a bank

faster than using the standard pr ogram command sequence. The unlock bypass

command sequence is initiated by first writing two unlock cycles. This is followed

by a third write cycle containing the unlock bypass command, 20h. That bank

then enters th e unlock bypass mode. A two-c ycle unlock bypass program com-

mand sequence is all that is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program command, A0h; the second

cycle con tain s th e p rog ram addr ess a nd d ata. Addit iona l data is pr ogrammed in

the same manner. This mode dispenses with the initial two unlock cycles required

in the standard p rogram command sequence, resu lting in faster total program-

ming time. Table 13 shows the requirements for the command sequence.

During the unlock bypass mode, only the Unlock Bypass Program and Unlock By-

pass Reset commands are valid. To exit the unlock bypass mode, the system

must issue the two-cycle unlock bypass reset command sequence. (See Table

12).

The device offers accelerated program operations through the WP#/ACC pin.

When the system asserts VHH on the WP#/ACC pin, the device automatically en-

ters the Unlock Bypa ss mode. The system may then write the two-cycle Unlock

Bypass program command sequence. The devi ce uses the higher voltage on the

WP#/ACC pin to accelerate the operation. Note that the WP#/ACC pin must not

be at VHH for any operation other than accelerated programming, or device dam-

age may result. In addition, the WP#/ACC pin must not be left floating or

unconnected; inconsistent behavior of the device may result.

4 illustrates the algorithm for the program operation. R efer to the Eras e and Pro-

gram Operations table in the AC Characteristics section for parameters, and

Figure 18 for timing diagrams.

34 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Figure 4. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cy cle operation. The chip erase command sequence is ini-

tiated by writing two unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by the chip erase command,

which in turn invokes the Embedded Erase algorithm. The device does not require

the system t o preprogram prior t o erase. The Embedde d Era se algorithm a uto-

matically preprograms and verifies the entire memory for an all zero data pattern

prior to electrical erase. The system is not required to provide any controls or tim-

ings during these oper ations. Table 13 shows the address and data requirements

for the chip erase command sequence.

When the Embedded Erase a lgor ithm is co mplete, tha t ba nk r etur ns t o the r ead

mode and addresses are no longer latched. The system can determine the status

of the erase operation by using DQ7, DQ6, DQ 2, or RY/BY#. Re fer to the Write

Operation Status section for information on these status bits.

Any commands written during the chip erase operation are ignored. However,

note that a hardware reset immediately terminates the erase operation. If that

occur s, the chip erase comma nd sequenc e s hould be r einitiated once that bank

has returned to reading array data, to ensure data integrit y. Note that the SecSi

Sector, autoselect, and CFI functions are unavailable when an erase operation is

in progress.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data? No

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 13 for program command sequence.

May 21, 2004 S29JL032HA0 S29JL032H 35

ADVANCE INFORMATION

5 illustrates the algorithm for the erase operation. Refer to the Erase and Program

Operations tables in the AC Characteristics section for parameters, and Figure 20

section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector erase command sequence is

initiated by writing two unlock cycles, followed by a set-up command. Two addi-

tional unlock cycles are written, and are then followed by the address of the

sector to be erased, and the sector erase command. Table 13 shows t he a d dr es s

and data requirements for the sector erase command sequence.

The device does not require t he system to preprogram prior to eras e. The Em-

bedded Erase algorithm automatically programs and verifies the entire sector for

an all zero data pattern prior to electrical erase. The system is not required to

provide any controls or timings during these operations.

After the com mand sequ ence is wri tten, a secto r eras e time-out of 80 µs occurs.

During the time-out period, additional sector addresses and sector erase com-

mands may be written. Loading the sector erase buffer may be done in any

sequence, and the number of sectors may be from one sector to all sectors. The

time between these additional cycles must be less than 80 µs, otherwise erasure

may begin. Any sector erase address and command following the exceeded time-

out may or may not be accepted. It is recommended that processor interrupts be

disabled during this time to ensure all commands are accepted. The interrupts

can be re-enabled after the last Sector Erase command is written. Any com-

mand other than Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The system must rewrite the com-

mand sequence and any additional addresses and commands.

The system can monitor DQ3 to determine if the sector erase timer has timed out

(See the s ectio n on DQ 3: Sec tor Er ase T imer.). T he ti me-ou t begin s from the r is-

ing edge of the final WE# or CE# pulse (first rising edge) in the command

sequence.

When the Embedded Erase algorithm is complete, the bank returns to reading

array data and addres ses are no longer latche d. Note that while the Embedded

Erase operation is in progress, the system can read data from the non-erasing

bank. The system can determine the status of the erase operation by reading

DQ7, DQ6, DQ2, or RY/BY# in the erasing bank. R efer to the Write Operation Sta-

tus section for information on these status bits.

Once the sector erase operation has begun, only the Erase Suspend command is

valid. All other commands are ignored. However, note that a hardware reset im-

mediately terminates the erase operation. If that occurs, the sector erase

command sequence should be reinitiated once that bank has returned to reading

array data, to en sure data integrity. Note that the SecSi Sector, autoselect, and

CFI functions are unavailable when an erase operation is in progress.

5 illustrates the algorithm for the erase operation. Refer to the Erase and Program

Operations tables in the AC Characteristics section for parameters, and Figure 20

section for timing diagrams.

36 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Figure 5. Erase Operation

Erase Suspend/Erase Resume Commands

The Erase Suspend command, B0h, allows the system to interrupt a sector erase

operation and then read data from, or program data to, any sect or not selected

for er asure . The b ank ad dress is requ ired when writin g this command . This com -

mand is valid only during the sector erase operation, including the 80 µs time-out

period during the sector erase command sequence. The Erase Suspend command

is ignored if written during the chip erase operation or Embedded Program

algorithm. The bank address must contain one of the sectors currently selected

for erase.

When the Erase Suspend command is written during the sector erase operation,

the device re quires a maximum of 20 µs to s uspend the erase operation. How-

ever, when the Erase Suspend command is written during the sector erase

time-out, the de vice immediately terminates the tim e-out period and s uspends

the erase operation.

After the erase operation has been suspended, the bank enters the erase-sus-

pend-rea d mod e. The system can rea d da ta fr om or pr ogram data to any sector

not selected for erasure. (The device “erase suspends” all sectors selected for

erasure.) Reading at any add ress within e rase-susp ended se ctors pr oduces sta-

tus information on DQ7–DQ0. The system can use DQ7, or DQ6 and DQ2

together, to determine if a sector is actively er asing or is er ase-suspended. Refer

to the Write Operation Status section for information on these status bits.

START

Write Erase

Command Sequence

(Notes 1, 2)

Data Poll to Erasing

Bank from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

Notes:

1. See Table 13 for erase command sequence.

2. See the section on DQ3 for information on the sector

erase timer.

May 21, 2004 S29JL032HA0 S29JL032H 37

ADVANCE INFORMATION

After an erase-suspended program operation is complete, the bank returns to the

erase-suspend-read mode. The system can determine the status of the progr am

operation using the DQ7 or DQ6 status bits, just as in the standard Byte Progr am

operation. Refer to the Write Operation Status section for more information.

In the er as e-susp end -read mod e, th e syst em c an also is sue the auto sel ect co m -

mand sequence. The device allows reading autoselect codes even at addresses

within er asing sec tor s, since the code s are not stored in the memory ar ray. When

the device exits the autoselect mode, the device reverts to the Erase Suspend

mode, and is ready for another valid operation. R efer to the Autoselect Mode and

Autoselect Command Sequence sections for detai l s.

To resume the sector erase operation, th e s yst em mus t wr ite the Era s e Resume

command. The bank address of the erase-suspended bank is required when writ-

ing this command. Further writes of the Resume command are ignored. Another

Erase Suspend command can be w ritten after the chip has resumed erasing.

38 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Ta b l e 1 3 . S29JL032H Command Definitions

Command

Sequence

(Note 1)

Cycles

Bus Cycles (Notes 2–5)

First Second Third Fourth Fifth Sixth

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Read (Note 6) 1RA RD

Reset (Note 7) 1XXX F0

Autoselect (Note 8)

Manufacturer ID Word 4555 AA 2AA 55 (BA)555 90 (BA)X00 01

Byte AAA 555 (BA)AAA

Device ID (Note 9) Word 6555 AA 2AA 55 (BA)555 90 (BA)X01 See

Table

(BA)X0E See

Table

(BA)X0F See

Table

Byte AAA 555 (BA)AAA (BA)X02 (BA)X1C (BA)X1E

SecSi Sector Factory

Protect (Note 10) Word 4555 AA 2AA 55 (BA)555 90 (BA)X03 82/

Byte AAA 555 (BA)AAA (BA)X06

Sector /S e ct or B l ock

Protect Verify

(Note 11)

Word 4555 AA 2AA 55 (BA)555 90 (SA)X02 00/

Byte AAA 555 (BA)AAA

(SA)X04

Enter SecSi Sector Region Word 3555 AA 2AA 55 555 88

Byte AAA 555 AAA

Exit SecSi Sector Region Word 4555 AA 2AA 55 555 90 XXX 00

Byte AAA 555 AAA

Program Word 4555 AA 2AA 55 555 A0 PA PD

Byte AAA 555 AAA

Unlo ck Bypass Word 3555 AA 2AA 55 555 20

Byte AAA 555 AAA

Unlock B yp a ss Pr ogram ( Note 12) 2XXX A0 PA PD

Unlock B ypass Reset (Note 13) 2XXX 90 XXX 00

Chip Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 555 10

Byte AAA 555 AAA AAA 555 AAA

Sector Erase Word 6555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30

Byte AAA 555 AAA AAA 555

Erase Suspend (Note 14) 1BA B0

Eras e Resume (Note 15) 1BA 30

CFI Query (Note 16) Word 155 98

Byte AA

egend:

= Don’t care

A = Address of the memory location to be read.

D = Data read from location RA during read operation.

A = Address of the memory location to be programmed. Addresses

atch on the falling edge of the WE# or CE# pulse, whichever happens

ater.

PD = Data to be programmed at location PA. Data latches on the rising

edge of WE# or CE# pulse, whichever happens first.

SA = Address of the sector to be verified (in autoselect mode) or

erased. Address bits A20–A12 uniquely select any sector. Refer to

tables 3 and 4 for information on sector addresses.

BA = Address of the bank that is being switched to autoselect mode, is

in bypass mode, or is being erased. A20–A18 uniquely select a bank.

otes:

1. See Table 1 for description of bus operations.

. All values are in hexadecimal.

. Except for the read cycle and the fourth, fifth, and sixth cycle of

the autoselect command sequence, all bus cycles are write

cycles.

. Data bits DQ15–DQ8 are don’t care in command sequences,

except for RD and PD.

. Unless otherwise noted, address bits A20–A11 are don’t cares for

unlock and command cycles, unless SA or PA is required.

. No unlock or command cycles required when bank is reading

array data.

7. The Reset command is required to return to the read mode (or to

the erase-suspend-read mode if previously in Erase Suspend)

when a bank is in the autoselect mode, or if DQ5 goes high

(while the bank is providing status information).

. The fourth cycle of the autoselect command sequence is a read

cycle. The system must provide the bank address to obtain the

manufacturer ID, device ID, or SecSi Sector factory protect

information. Data bits DQ15–DQ8 are don’t care. While reading

the autoselect addresses, the bank address must be the same

until a reset command is given. See the Autoselect Command

Sequence section for more information.

9. For models 01, 02, the device ID must be read across the fourth,

fifth, and sixth cycles.

10. The data is 82h for factory locked, 40h for customer locked, and

02h for not factory/customer locked.

11. The data is 00h for an unprotected sector/sector block and 01h

for a protected sector/sector block.

12. The Unlock Bypass command is required prior to the Unlock

Bypass Program command.

13. The Unlock Bypass Reset command is required to return to the

read mode when the bank is in the unlock bypass mode.

14. The system may read and program in non-erasing sectors, or

enter the autoselect mode, when in the Erase Suspend mode.

The Erase Suspend command is valid only during a sector erase

operation, and requires the bank address.

15. The Erase Resume command is valid only during the Erase

Suspend mode, and requires the bank address.

16. Command is valid when device is ready to read array data or

when device is in autoselect mode.

May 21, 2004 S29JL032HA0 S29JL032H 39

ADVANCE INFORMATION

Write Operation Status

The device provides several bits to determine the status of a program or erase

operation: DQ2, DQ3, DQ5, DQ6, and D Q7. Table 14 and the following subsec-

tions describe the function of the se bits. DQ7 and DQ6 each o ffer a method for

determining whether a program or erase operation is complete or in progress.

The device also provides a hardware-based output signal, RY/BY#, to determine

whether an Embedded Program or Erase operation is in progress or has been

completed.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host system whether an Embedded

Program or Erase al gor ithm is in progr ess or complete d, or whether a bank is in

Erase Suspend. Data# P olling is valid after the rising edge of the final WE# pulse

in the co mmand sequence.

During the Em bedded Program a lgorithm, the devic e outputs on DQ7 the c om-

plement of the datum programmed to DQ7. This DQ7 status also applies to

programming during Erase Suspend . Whe n the Embedde d Program alg ori thm is

complete, the device outputs the datum programmed to DQ7. The system must

provide the program address to read valid status information on DQ 7. If a p ro-

gram address falls within a protected sector, Data# Polling on DQ 7 is active for

approximately 1 µs, then that bank returns to the read mode.

During the Embedded Erase algorithm, Data# Polling produces a “0” on DQ7.

When the Embedded Erase algorithm is complete, or if the bank enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7. The system must provide

an address withi n any of the sectors selected for erasure to read valid status in-

formation on DQ7.

After an erase command sequence is written, if all sectors selected for erasing

are protected, Data# Polling on DQ7 is active for approximately 100 µs, then the

bank returns to the read mode. If not all selected sectors are protected, the Em-

bedded Erase algorithm erases the unprotected sectors, and ignores the selected

sectors that are protected. However, if the system reads DQ7 at an address within

a pro tected sector, the status may not be valid.

When the system detects DQ7 has changed from the complement to true data,

it can read valid data at DQ15–DQ0 (or DQ7–DQ0 for x8-only device) on the fol-

lowing read cycles. Just prior to the completion of an Embedded Program or Erase

operation, DQ7 may change asynchronously with DQ15–DQ8 (DQ7–DQ0 for x8-

only device) while Output Enable (OE#) is asserted low. That is, the device may

change from providing status information to valid data on DQ7. Depending on

when the system samples the DQ7 output, it may r ead the status or valid data.

Even if the device has completed the program or erase operation and DQ7 has

valid data, the data outputs on DQ15–DQ0 may be still invalid. Valid data on

DQ15–DQ0 (or DQ7–DQ0 for x8-only device) will appear on successive read

cycles.

Table 14 sho ws the outp uts for Dat a# P olling on DQ7. 6 shows the Data# P olling

algorithm. 22 in the AC Characteristics section shows the Data# Polling timing

diagram.

40 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Figure 6. Data# Polling Algorithm

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a

sector erase operation, a valid address is any sector

address within the sector being erased. During chip

erase, a valid address is any non-protected sector

address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

May 21, 2004 S29JL032HA0 S29JL032H 41

ADVANCE INFORMATION

RY/BY#: Ready/Busy#

The RY/BY# is a dedicated, open-drain output pin which indicates whether an

Embedded Algorithm is in progress or complete. The RY/BY# status is valid after

the rising edge of the final WE# pulse in the comm and sequence. Since RY/BY#

is an open-drain output, several RY/BY# pins can be tied together in parallel with

a pull-up resistor to VCC.

If the output is low (Bus y), the device is actively erasing or programming. (This

includes programming in the Erase Suspend mode.) If the output is high (Ready),

the device is in the read mode, the sta ndby mode, or one of the banks is in the

erase-suspend-read mode.

Table 14 shows the outputs for RY/BY#.

DQ6: Toggle Bit I

Toggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm

is in progress or complete, or whether the device has entered the Erase Suspend

mode. Toggle Bit I m ay b e re ad at an y addre ss , and is valid afte r the ris ing e dge

of the final WE# pulse in the command sequence (prior to the program or erase

operation), and during the sector er ase time-out.

During an Embedded Program or Erase algorithm operation, successive read cy-

cles to any address cause DQ6 to toggle. The system may use either OE# or CE#

to control the read cycles. When the operation is complete, DQ6 stops toggling.

After an erase command sequence is written, if all sectors selected for erasing

are protected, DQ6 toggles for approximately 100 µs, then returns to reading

array data. If not all selected sectors are protected, the Embedded Erase algo-

rith m erases the u nprotec ted secto rs, and ig nores th e selec ted sector s that ar e

protected.

The system can use DQ6 and DQ2 together to determine whether a sector is ac -

tively erasing or is erase-suspended. When the device is actively erasing (that is,

the Embedde d Eras e algor ithm is in progress), DQ6 toggles. W hen the device e n-

ters the Erase Suspend mode, DQ6 stops toggling. However, the system must

also use DQ2 to determine which sectors are erasing or erase-suspended. Alter-

natively, the system can use DQ7 (see the subsection on DQ7: Data# P olling).

If a program address falls within a protected sector, DQ6 toggles for approxi-

mately 1 µs after the program command sequence is written, then returns to

reading array data.

DQ6 also toggles during the erase-suspend-program mode, and stops toggling

once the Embedded Program algorithm is complete.

42 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Figure 7. Toggle Bit Algorithm

DQ2: Toggle Bit II

The “Togg le Bit II” on DQ2, when us ed with DQ6, indicates whe ther a pa r ticu lar

sector is actively er asing (that is, the Embedded Erase algorithm is in progress),

or whet her that sector is erase-suspended. Toggle Bit II is valid after the rising

edge of the final WE# pulse in the command sequence.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Toggle Bit

= Toggle?

Read Byte Twice

(DQ7–DQ0)

Address = VA

Read Byte

(DQ7–DQ0)

Address =VA

Read Byte

(DQ7–DQ0)

Address =VA

Note: The system should recheck the toggle bit even if

DQ5 = “1” because the toggle bit may stop toggling as DQ5

changes to “1.” See the subsections on DQ6 and DQ2 for

more information.

May 21, 2004 S29JL032HA0 S29JL032H 43

ADVANCE INFORMATION

DQ2 toggl es when th e system reads at addr esses wi thin tho se sect ors that ha ve

been selected for erasure. (The system may use either OE# or CE# to control the

read cycles.) But DQ2 cannot distinguish whether the sector is actively erasing or

is erase-suspended. DQ6, by comparison, indicates whether the device is actively

erasing, or is in Erase Suspend, but cannot distinguish which sectors are selected

for erasure. Thus, both status bits are required for sector and mode information.

Refer to Table 14 to compare outputs for DQ2 and DQ6.

7 shows the toggle bit algorithm in flowchart form, and the section “DQ2: Toggle

Bit II” explains the algorithm. See also the DQ6: Toggle Bit I subsection. 23

shows the toggle bit timing diagram. 24 shows the differences between DQ2 and

DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to 7 for the following discussion. Whenever the system initially begins read-

ing toggle bit status , it must read DQ15–DQ 0 (or DQ7–DQ0 for x8-only device)

at least twice in a row to determine whether a toggle bit is toggling. T ypically, the

system would note and store the value of the toggle bit after the first read. After

the second read, the system would compare the new value of the toggle bit with

the first. If the toggle bit is not tog gling , the devic e has c om plete d the program

or erase operation. The system can read array data on DQ15–DQ0 (or DQ7–DQ0

for x8-only device) on the following read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device has suc-

cessfully completed the program or erase operation. If it is still toggling, the

devic e di d not com ple te d the ope rati on su cc essf ul ly, an d t he s yst em m us t wri te

the reset command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 has not gone high. The system ma y continue to monitor the

toggle bit and DQ5 through successive read cycles, determining the status as de-

scribed in the pr evious paragraph. Alterna tively, it may choose to per form other

system tasks. In this case, the system must start at the beginning of the algo-

rithm when it returns to determine the status of the operation (top of 7).

DQ5: Exceeded Timing Limits

DQ5 indic ates whethe r the program or erase time has exceeded a specified in-

ternal pulse count limit. Under these conditions DQ5 produces a “1,” indicating

that the program o r erase cy cle was not su ccessfully co mpleted.

The device may output a “1” on DQ5 if the system tries to program a “1” to a

location that wa s previously programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Unde r this condit ion, the device hal ts the opera-

tion, and when the timing limit has been exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write the reset command to return

to the read mo de (or to the erase-s uspend-read mo de if a bank was previous ly

in the erase-suspend-progr am mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the system may read DQ3 to de-

termine whether or not erasure has begun. (The sector erase timer does not

44 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

apply to the c hip erase comma nd.) If ad ditio nal sect ors are se lect ed for er asu re,

the entire time-out also applies after each additional sector erase command.

When the time-out period is complete, DQ3 switches from a “0” to a “1.” If the

time between additional sector erase commands from the system can be as-

sumed to be less than 50 µs, the system need not monitor DQ3. See also the

Sector Erase Command Sequence section.

After the sector erase command is written, the system should read the status of

DQ7 (Data# Polling) or DQ6 (Toggle Bit I) to ensure that the device has accepted

the command sequence, and then read DQ3. If DQ3 is “1,” the Embedded Erase

algorithm has begun; all further commands (except Erase Suspend) are ignored

until the erase operation is complete . If DQ3 is “0,” the d evice will accept addi-

tional sect or erase comm ands. To ensur e the command has been ac cepted, th e

syste m software sh ould chec k the status of DQ3 p rior to and fol lowing each su b-

seque nt se ctor e rase c omman d. If DQ3 is high on t he s econd stat us che ck, t he

last command might not have been accepted.

Table 14 shows the status of DQ3 relative to the other status bits.

Ta bl e 1 4 . Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing

limits. Refer to the section on DQ5 for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further

details.

3. When reading write operation status bits, the system must always provide the bank address where the Embedded

Algorithm is in progress. The device outputs array data if the system addresses a non-busy bank.

Status

DQ7

(Note 2) DQ6

DQ5

(Note 1) DQ3

DQ2

(Note 2) RY/BY#

Standard

Mode

Embedded Program Algori thm

DQ7# Toggle 0N/A No toggle 0

Embedded Erase Alg orithm 0Toggle 0 1 Toggle 0

Eras e

Suspend

Mode

Erase-Suspend-

Read

Erase

Suspended Sector 1No toggle 0N/A Toggle 1

Non-Erase

Suspended Sector Data Data Data Data Data 1

Erase-Suspend-Program DQ7# Toggle 0N/A N/A 0

May 21, 2004 S29JL032HA0 S29JL032H 45

ADVANCE INFORMATION

Absolute Maximum Ratings

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +150°C

Ambie n t Temperature

with Power Applied . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +4.0 V

A9, OE#, and RESET#

(Note 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +12.5 V

WP#/ACC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to +10.5 V

All other pins (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to VCC +0.5 V

Output Short Circuit Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V. During voltage transitions, input or I/O pins may overshoot VSS to –

2.0 V for periods of up to 20 ns. Maximum DC voltage on input or I/O pins is VCC +0.5 V. See Figure 8. During voltage

transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 9.

2. Minimum DC input voltage on pins A9, OE#, RESET#, and WP#/ACC is –0.5 V. During voltage transitions, A9, OE#, WP#/

ACC, and RESET# may overshoot VSS to –2.0 V for periods of up to 20 ns. See Figure 8. Maximum DC input voltage on

pin A9 is +12.5 V which may overshoot to +14.0 V for periods up to 20 ns. Maximum DC input voltage on WP#/ACC is

+9.5 V which may overshoot to +12.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a time. Duration of the short circuit should not be greater than one

second.

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any other conditions above those indicated in the operational

sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods

may affect device reliability.

Operating Ranges

Industrial (I) Devices

Ambien t Temperature (TA) . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

VCC Supply Voltages

VCC for standard v oltage range . . . . . . . . . . . . . . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the functionality of the device is

guaranteed.

Figure 8. Maximum Negative

Overshoot Waveform Figure 9. Maximum Positive

Overshoot Waveform

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

20 ns

+2.0 V

+0.5 V

20 ns

2.0 V

46 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

DC Characteristics

CMOS Compatible

Notes:

1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH.

2. Maximum ICC specifications are tested with VCC = VCCmax.

3. ICC active while Embedded Erase or Embedded Program is in progress.

4. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns. Typical sleep mode

current is 200 nA.

5. Not 100% tested.

Parameter

Symbol Parameter Description Test Conditions Min Typ Max Unit

Input Load Current V

= V

to V

= V

max

1.0 µA

LIT

A9, OE# and RESET# Input Load

Current V

= V

CC max

, OE# = V

; A9 or

OE# o r RESET# = 12.5 V 35 µA

Output Leakage Current V

OUT

= V

to V

= V

CC max

, OE# = V

1.0 µA

ILR Reset Leakage Current VCC = VCC max; RESET# =

12.5 V 35 µA

CC1

Active Read Current

(Notes 1, 2)

CE# = V

OE#

Byte Mode 5 MHz 10 16

1 MHz 2 4

CE# = V

OE# =

, Word Mod e 5 MHz 10 16

1 MHz 2 4

CC2

Act ive Write Current (Notes 2,

3) CE# = V

OE# = V

, WE# = V

15 30 mA

CC3

Standby Current (Note 2) CE#, RESET# = V

0.3 V 0.2 5µA

CC4

Reset Current (N ot e 2) RESET# = V

0.3 V 0.2 5µA

CC5

Automatic Sleep Mode (Notes 2, 4) V

= V

0.3 V;

= V

0.3 V 0.2 5µA

CC6

Active Read-While-Program

Current (Notes 1, 2) CE# = V

OE# = V

Byte 21 45 mA

Word 21 45

CC7

Active Read-While-Erase

Current (Notes 1, 2) CE# = V

, OE# = V

Byte 21 45 mA

Word 21 45

CC8

Active Program-While-Erase-

Suspended Current (Notes 2, 5) CE# = V

, OE# = V

17 35 mA

Input Low Voltage –0.5 0.8 V

Input High Voltage 0.7 x V

+ 0.3 V

Voltage for WP#/ACC Sector

Protect/Unprotect and Program

Acceleration V

= 3.0 V ± 10% 8.5 9.5 V

VID

Voltag e for Autoselect and

Temporary Sector Unprotect V

= 3.0 V

10% 8.5 12.5 V

Output Low Voltage I

= 2.0 mA, V

= V

CC min

0.45 V

OH1

Output High Voltage I

= – 2.0 mA, V

= V

CC min

0.85 x V

OH2

= –100 µ A , V

= V

CC min

–0.4

LKO

Low V

Lock-Ou t Voltage (Note 5) 2.3 2.4 2.5 V

May 21, 2004 S29JL032HA0 S29JL032H 47

ADVANCE INFORMATION

DC Characteristics

Zero-Power Flash

Note: Addresses are switching at 1 MHz

Figure 10. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

00 500 1000 1500 2000 2500 3000 3500 4000

Supply Current in mA

Time in ns

1 2345

Frequency in MHz

Supply Current in mA

Note: T = 25

Figure 11. Ty p i c a l I CC1 vs. Frequency

2.7 V

3.6 V

48 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Test Conditions

Table 1. Test Specifications

Key To Switching Waveforms

Test Condition 55, 60 70, 90 Unit

Output Load 1 TTL gate

Output Load Cap a citance, C

(including jig capacitance) 30 100 pF

Input Rise and Fall Times 5ns

Input Pulse Levels 0.0 or Vcc V

Input timing measurement reference levels 0.5 Vcc V

Output timing measurement reference levels 0.5 Vcc V

2.7 k

Ω

6.2 k

Ω

3.3 V

Device

Under

Test

Note: Diodes are IN3064 or equivalent

Figure 12. Test Setup

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change P erm itted C hanging, State Unkno wn

Does Not Apply Center Line is High Impedance State (High Z)

Vcc

0.0 V 0.5 Vcc 0.5 Vcc OutputMeasurement LevelInput

Figure 13. Input Waveforms and Measurement Levels

May 21, 2004 S29JL032HA0 S29JL032H 49

ADVANCE INFORMATION

AC Characteristics

Read-Only Operations

Notes:

1. Not 100% tested.

2. See 12 and Table 1 for test specifications

3. Measurements performed by placing a 50 ohm termination on the data pin with a bias of VCC/2. The time from OE#

high to the data bus driven to VCC/2 is taken as tDF

Parameter

Description

Test Setup

Speed Options

JEDEC Std. 55 60 70 90 Unit

AVAV

Read Cycle Time (Note 1) Min 55 60 70 90 ns

AVQV

ACC

Address to Output Delay CE#,

OE# = V

Max 55 60 70 90 ns

ELQV

Chip Enable to Output Delay OE# = V

Max 55 60 70 90 ns

GLQV

Out pu t En ab le to Ou tpu t De la y Max 25 30 35 ns

EHQZ

Chip Enable to Output High Z (Notes 1, 3) Max 16 ns

GHQZ

Output Enable to Output High Z (Notes 1, 3) Max 16 ns

AXQX

Output Hold Time From Addresses, CE# or

OE#, W hichever Occurs First Min 0ns

OEH

Output Enable Hold Time

(No te 1 )

Read Min 0ns

Toggle and

Da ta # Pollin g Min 510 ns

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

ACC

OEH

0 V

RY/BY#

RESET#

Figure 14. Read Operation Timings

50 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

AC Characteristics

Hardware Reset (RESET#)

Note: Not 100% tested.

Parameter

Description All Speed Options UnitJEDEC Std

Ready

RESET# Pin Low (During Embedded Algorithms)

to Read Mode (See Note) Max 20 µs

Ready

RESET# Pin Low (NOT During Embedded

Algori th m s) to R e a d Mod e (See Note) Max 500 ns

RESET# Pulse Width Min 500 ns

Reset High Time Before Read (See Not e ) Min 50 ns

RPD

RESET# Low to Standby Mode Min 20 µs

RY/BY# Recovery Time Min 0ns

RESET#

RY/BY#

Ready

Reset Timings NOT during Embedded Algorithms

Ready

CE#, OE#

Reset Timings during Embedded Algorithms

RESET#

Figure 15. Reset Timings

May 21, 2004 S29JL032HA0 S29JL032H 51

ADVANCE INFORMATION

AC Characteristics

Word/Byte Configuration (BYTE#)

Parameter Speed Options

JEDEC Std.

Description

55 60 70 90 Unit

ELFL/

ELFH

CE# to BYTE# Switching Low or High Max 5ns

FLQZ

BYTE# Switching Low to Output HIGH Z Max 16 ns

FHQV

BYTE# Switching High to Output Active Min 55 60 70 90 ns

52 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

DQ15

Output

Data Outp ut

(DQ7–DQ0)

CE#

OE#

BYTE#

ELFL

DQ14–DQ0 Data Output

(DQ14–DQ0)

DQ15/A-1 Address

Input

FLQZ

BYTE#

Switching

from word

to byte

mode

DQ15

Output

Data Outp ut

(DQ7–DQ0)

BYTE#

ELFH

DQ14–DQ0 Data Output

(DQ14–DQ0)

DQ15/A-1 Address

Input

FHQV

BYTE#

Switching

from byte

to word

mode

Figure 16. BYTE# Timings for Read Operations

Note: Refer to the Erase/Program Operations table for tAS and tAH specifications.

Figure 17. BYTE# Timings for Write Operations

CE#

WE#

BYTE#

The falling edge of the last WE# signal

HOLD

)

SET

)

May 21, 2004 S29JL032HA0 S29JL032H 53

ADVANCE INFORMATION

AC Characteristics

Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std

Description

55 60 70 90

Uni

AVAV

Write Cycle Time (Note 1) Min 55 60 70 90 ns

AVWL

Address Setup Time Min 0ns

ASO

Address Setup Time to OE# low during toggle bit

polling Min 12 ns

WLAX

Address Hold Time Min 30 35 40 45 ns

AHT

Address Hold Time From CE# or OE# high

during toggle bit polling Min 0ns

DVWH

Da ta Setup Time Min 30 35 40 45 ns

WHDX

Data Hold Time Min 0ns

OEPH

Output Enable High during toggle bit polling Min 20 ns

GHWL

Read Recovery Time Befor e Write

(OE# High to WE# Low) Min 0ns

ELWL

CE# Setup Time Min 0ns

WHEH

CE# Hold Time Min 0ns

WLWH

Write Pu lse Width Min 25 25 30 35 ns

WHDL

WPH

Write Pu lse Width High Min 25 25 30 30 ns

SR/W

Latency Between Read and Write Operations Min 0ns

WHWH1

Programming Operation (Note 2) Byte Typ 4µs

Word Typ 6

WHWH1

Accelerated Programming Operation,

Byte or Word (Note 2) Typ 4µs

WHWH2

Sector Erase Operation (Note 2) Typ 0.4 sec

VCS

Setup Time (Note 1) Min 50 µs

Write Recovery Time from RY/BY# Min 0ns

BUSY

Program/Erase Valid to RY /BY# Delay Max 90 ns

54 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

AC Characteristics

OE#

WE#

CE#

VCC

Data

Addresses

tDS

tAH

tDH

tWP

tWHWH1

tWC tAS

tWPH

tVCS

555h PA PA

Read Status Data (last two cycles)

A0h

tCS

Status DOUT

Program Command Sequence (last two cycles)

RY/BY#

tRB

tBUSY

tCH

otes:

. PA = program address, PD = program data, DOUT is the true data at the program address.

. Illustration shows device in word mode.

Figure 18. Program Operation Timings

WP#/ACC tVHH

VHH

VIL or VIH VIL or VIH

tVHH

Figure 19. Accelerated Program Timing Diagram

May 21, 2004 S29JL032HA0 S29JL032H 55

ADVANCE INFORMATION

AC Characteristics

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

RY/BY#

tRB

tBUSY

otes:

1. SA = sector address (for Sector Erase), VA = Valid Address for reading status data (see “Write Operation Status”.

. These waveforms are for the word mode.

Figure 20. Chip/Sector Erase Operation Timings

56 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

AC Characteristics

OE#

CE#

WE#

Addresses

Data Valid

In Valid

Valid PA Valid RA

WPH

Valid

Out

ACC

OEH

GHWL

Valid

CE# or CE2# Controlled Write CyclesWE# Controlled Write Cycle

Valid PA Valid PA

CPH

Read Cycle

SR/W

Figure 21. Back-to-back Read/Write Cycle Timings

WE#

CE#

OE#

High Z

tOE

High Z

DQ7

DQ0–DQ6

RY/BY#

tBUSY

Complement True

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

Status Data

Complement

Status Data True

Valid Data

tACC

tRC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array

data read cycle.

Figure 22. Data# Polling Timings (During Embedded Algorithms)

May 21, 2004 S29JL032HA0 S29JL032H 57

ADVANCE INFORMATION

AC Characteristics

OE#

CE#

WE#

Addresses

tOEH

tDH

tAHT

tASO

tOEPH

tOE

Valid Data

(first read) (second read) (stops toggling)

tCEPH

tAHT

tAS

DQ6/DQ2 Valid Data

Valid

Status Valid

Status

RY/BY#

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status

read cycle, and array data read cycle

Figure 23. Toggle Bit Timings (During Embedded Algorithms)

Note: DQ2 toggles only when read at an address within an erase-suspended sector. The system may use OE# or CE#

to toggle DQ2 and DQ6.

Figure 24. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Program

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

58 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

AC Characteristics

Temporary Sector Unprotect

Note: Not 100% tested.

Parameter

All Speed OptionsJEDEC Std

Description

Unit

VIDR

Rise and Fall Time (See Note) Min 500 ns

VHH

Rise and Fall Time (See Note) Min 250 ns

RSP

RESET# Setup Time for Temporary Sector

Unprotect Min 4µs

RRB

RESET# Hold Time from RY/BY# High for

Temporary Sector Unprotect Min 4µs

RESET#

tVIDR

VID

VSS, VIL,

or VIH

VID

VSS, VIL,

or VIH

CE#

WE#

RY/BY#

tVIDR

tRSP

Program or Erase Command Sequence

tRRB

Figure 25. Temporary Sector Unprotect Timing Diagram

May 21, 2004 S29JL032HA0 S29JL032H 59

ADVANCE INFORMATION

AC Characteristics

Sector Group Protect: 150 µs

Sector Group Unprotect: 15 ms

1 µs

RESET#

SA, A6,

A1, A0

Data

CE#

WE#

OE#

60h 60h 40h

Valid* Valid* Valid*

Status

Sector Group Protect/Unprotect Verify

VID

VIH

* For sector protect, A6 = 0, A1 = 1, A0 = 0. For sector unprotect, A6 = 1, A1 = 1, A0 = 0.

Figure 26. Sector/Sector Block Protect and

Unprotect Timing Diagram

60 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

AC Characteristics

Alternate CE# Controlled Erase and Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase And Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std.

Description

55 60 70 90 Unit

AVAV

Write Cycle Time (Note 1) Min 55 55 70 90 ns

AVWL

Address Setup Time Min 0ns

ELAX

Address Hold Time Min 30 35 40 45 ns

DVEH

Da ta Setup Time Min 30 35 40 45 ns

EHDX

Data Hold Time Min 0ns

GHEL

Read Recovery Time Before Write

(OE# High to WE# Low) Min 0ns

WLEL

WE# Setup Time Min 0ns

EHWH

WE# Hold Time Min 0ns

ELEH

CE# Pulse Width Min 25 25 30 35 ns

EHEL

CPH

CE# Pulse Width High Min 25 25 30 30 ns

WHWH1

Programming Operation

(Note 2) Byte Typ 4µs

Word Typ 6

WHWH1

Accelerated Programming Operation,

Byte or Word (N ote 2) Typ 4µs

WHWH2

Sector Erase Operation (Note 2) Typ 0.4 sec

May 21, 2004 S29JL032HA0 S29JL032H 61

ADVANCE INFORMATION

AC Characteristics

GHEL

OE#

CE#

WE#

RESET#

Data

Addresses

DQ7# D

OUT

CPH

Data# Polling

A0 for program

55 for erase

WHWH1 or 2

RY/BY#

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

BUSY

Notes:

1. Figure indicates last two bus cycles of a program or erase operation.

2. PA = program address, SA = sector address, PD = program data.

3. DQ7# is the complement of the data written to the device. DOUT is the data written to the device.

4. Waveforms are for the word mode.

Figure 27. Alternate CE# Controlled Write (Erase/Program) Operation Timings

62 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Erase And Programming Performance

Notes:

1. Typical program and erase times assume the following conditions: 25°C, VCC = 3.0 V, 100,000 cycles; checkerboard data

pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V, 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 13 for further information on command definitions.

6. The device has a minimum cycling endurance of 100,000 cycles per sector.

TSOP Pin Capacitance

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

Parameter

Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.4 2sec Excludes 00h programming

prior to erasure (Note 4)

Chip Erase Time 28 sec

Byte Program Time 480 µs

Excludes system leve l

overhead (Note 5)

Word Program Time 6100 µs

Accelerated Byte/Word Program Time 470 µs

Chip Progr am Time

(Note 3)

Byte Mode 12.6 50

secWord Mode 12 35

Accelerated Mode 10 30

Parameter Symbol Parameter Description Test Setup Typ Max Unit

Input Capacitance V

= 0 TSOP 67.5 pF

OUT

Output Capa citance V

OUT

= 0 TSOP 8.5 12 pF

IN2

Control Pin Capacitance V

= 0 TSOP 7.5 9pF

May 21, 2004 S29JL032HA0 S29JL032H 63

ADVANCE INFORMATION

Physical Dimensions

TS 048—48-Pin Standard TSOP

TS/TSR 048

MO-142 (D) DD

MIN

0.05

0.95

0.17

0.10

18.30

19.80

0.50

0˚

0.08

11.90

0.50 BASIC

MAX

0.15

1.20

0.27

0.16

0.21

8˚

0.20

18.50

12.10

0.70

20.20

0.23

1.05

0.20

1.00

0.22

18.40

20.00

0.60

12.00

NOM

Symbol

Jedec

Package

NOTES:

CONTROLLING DIMENSIONS ARE IN MILLIMETERS (mm).

(DIMENSIONING AND TOLERANCING CONFORMS TO ANSI Y14.5M-1982)

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE UP).

PIN 1 IDENTIFIER FOR REVERSE PIN OUT (DIE DOWN), INK OR LASER MARK.

TO BE DETERMINED AT THE SEATING PLANE -C- . THE SEATING PLANE IS DEFINED AS THE PLANE OF

CONTACT THAT IS MADE WHEN THE PACKAGE LEADS ARE ALLOWED TO REST FREELY ON A FLAT

HORIZONTAL SURFACE.

DIMENSIONS D1 AND E DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTUSION IS

0.15mm (.0059") PER SIDE.

DIMENSION b DOES NOT INCLUDE DAMBAR PROTUSION. ALLOWABLE DAMBAR PROTUSION SHALL BE

0.08 (0.0031") TOTAL IN EXCESS OF b DIMENSION AT MAX. MATERIAL CONDITION. MINIMUM SPACE

BETWEEN PROTRUSION AND AN ADJACENT LEAD TO BE 0.07 (0.0028").

THESE DIMENSIONS APPLY TO THE FLAT SECTION OF THE LEAD BETWEEN 0.10MM (.0039") AND

0.25MM (0.0098") FROM THE LEAD TIP.

LEAD COPLANARITY SHALL BE WITHIN 0.10mm (0.004") AS MEASURED FROM THE SEATING PLANE.

DIMENSION "e" IS MEASURED AT THE CENTERLINE OF THE LEADS.

REVERSE PIN OUT (TOP VIEW)

2X (N/2 TIPS)

0.10

SEATING

PLANE

SEE DETAIL A

2X (N/2 TIPS)

0.25

2X 0.10

0.10

STANDARD PIN OUT (TOP VIEW)

SEE DETAIL B

DETAIL A

(c)

θ°

0.25MM (0.0098") BSC

GAUGE PLANE

PARALLEL TO

SEATING PLANE

(c)

WITH PLATING

BASE METAL

0.08MM (0.0031") M C A - B S

SECTION B-B

DETAIL B

e/2

X = A OR B

3355 \ 16-038.10c

64 S29JL032H S29JL032HA0 May 21, 2004

ADVANCE INFORMATION

Revision Summary

Revision A (May 21, 2004)

Initial release.

Trademarks and Notice

The contents of this document are subject to change without notice.This document may contain information on a Spansion product under development by

FASL LLC. FASL LLC reserves the right to change or discontinue work on any product without notice. The information in this document is provided “as is”

without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of

third-party rights, or any other warranty, express, implied, or statutory. FASL LLC assumes no liability for any damages of any kind arising out of the use of

the information in this document.

LLC. Other company and product names used in this publication are for identification purposes only and may be trademarks of their respective companies.