12V Wireless Power Transmitter IC for TX-A6 Product Datasheet Features Description 5W WPC 1.2 Compliant Wireless Power Transmitter Single Chip Solution for TX-A6 The P9036B is a highly integrated WPC-compliant wireless power transmitter IC for power transmitter WPC design TX-A6. This device operates with a 12Vdc adaptor, and drives an external load directly via an internal half-bridge. It controls the transferred power by changing the switching frequency of the half-bridge inverter from 110 kHz to 205 kHz as specified by the WPC specification for an "A6" transmitter. It contains logic circuits required to demodulate and decode WPCcompliant message packets sent by the mobile device to adjust the transferred power. Excellent EMI performance eliminates need for EMI filters 12V Operating Input Voltage Closed-Loop Power Transfer Control Between Base Station and Mobile Device Demodulates and Decodes WPC-Compliant Message Packets 5V Regulated DC/DC Converter Integrated RESET Function Internal half-bridge power MOSFETs Proprietary Back-Channel Communication I2C Interface Push-Pull GPIO/LED Indicator Outputs Over-Temperature Protection Optional Buzzer Support Foreign Object Detection (FOD) The P9036B is an intelligent device, which manages mobile device detection, and selection of one of the three coils of the A6 transmitter coil without user supervision. The A6 configuration allows free mobile device positioning over a wider area than configurations that use a single coil, detecting a mobile device for charging while minimizing idle power. Once the mobile device is detected and authenticated, the P9036B continuously monitors all communications from the mobile device, and adjusts the transmitted power accordingly by varying the switching frequency of the internal half-bridge inverter. The P9036B can optionally support a proprietary back-channel communication mode, which enables the device to communicate with IDT's wireless power receiver solutions. This feature enables additional layers of capabilities beyond the standard WPC requirements. Applications Wireless Interface Transmitter(s) Mobile Device Receiver Control Control System Control System Comm Cont Sensing Control IN PWR Comm DeMod Load Reflection Power Generation Comm Cont Sensing Control Mod Power Pick-Up Induction Output Load Base Station Input Power The P9036B includes over-temperature/current protection and WPC compliant Foreign Object Detection (FOD) to protect the base station from overloading in the presence of a metallic foreign object. Additionally, it manages fault conditions associated with power transfer and controls LED outputs to indicate operating status. WPC-Compliant Wireless Charging Base Stations P9036B Out PWR Package: 6x6-48 TQFN Revision 1.0.0 1 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet SIMPLIFIED APPLICATION DIAGRAM PS,VIN PS,GND + RSENSE CBST LBUCK COUT CIN IN BUCK5VT_SNS BUCK5VT LDO2P5V_IN LX REG_IN BUCK5VT_IN BST CBRIDGE,IN SW CS Tx-A6 Coil ISNS IDTP9036B CISNS,OUT C5V,OUT EEPROM GPIO_0 GPIO_2 GPIO_6 PGND LDO5V SCL SDA WP GPIO_1 GPIO_5 LEDB LEDA BAND PASS FILTER HPF GPIO_4 GPIO_3 Buzzer 3xFETCOIL,SELECTION LDO2P5V C2P5V,OUT RESET __ Thermal Monitoring RTH VOSNS GND EP EN Figure 1. P9036B Simplified Application Schematic Revision 1.0.0 2 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet ABSOLUTE MAXIMUM RATINGS Stresses above the ratings listed below (Table 1 and Table 2) can cause permanent damage to the P9036B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Table 1 Absolute Maximum Ratings Summary. All voltages are referred to GND, unless otherwise noted. PINS RATING UNITS BUCK5VT_IN, REG_IN, IN, IN1, IN2, SW, SW1, SW2 -0.3 to 24 V -0.3 to VIN+0.3 V -0.3 to VIN+5 -0.3 to 2.75 -0.3 to +0.3 V V V -0.3 to +6.0 V , LX EN BST LDO2P5V AGND, DGND, PGND, PGND1, PGND2, PGND3, GND, REFGND, EP, IC1, IC2, IC5 BUCK5VT_SNS, BUCK5VT, GPIO0, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, HPF, ISNS, LDO2P5V_IN, LDO5V, RESET, SCL, SDA, VOSNS Table 2 Package Thermal Information SYMBOL DESCRIPTION RATING UNITS JA Thermal Resistance Junction to Ambient (NTG48 - TQFN) 30.8 C/W JC Thermal Resistance Junction to Case (NTG48 - TQFN) 14.6 C/W JB2 Thermal Resistance Junction to Board (NTG48 - TQFN) 0.75 C/W TJ Junction Operating Temperature -40 to +125 TA Ambient Operating Temperature -40 to +85 C TSTG Storage Temperature -55 to +150 C TLEAD Lead Temperature (soldering, 10s) +300 C C Note 1: The maximum power dissipation is PD(MAX) = (TJ(MAX) - TA) / JA where TJ(MAX) is 125C, the maximum junction operating temperature. Exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. Note 2: This thermal rating was calculated on JEDEC 51 standard 4-layer board with dimensions 4" x 4" in still air conditions. Note 3: Actual thermal resistance is affected by PCB size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. Note 4: For the NTG48 package, connecting the 4.1 mm X 4.1 mm EP to internal/external ground planes with a 5x5 matrix of PCB plated-through-hole (PTH) vias, from top to bottom sides of the PCB, is recommended for improving the overall thermal performance. Table 3 ESD Information TEST MODEL PINS HBM All 2000 V CDM All 500 V Revision 1.0.0 RATINGS 3 UNITS (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, EN unless otherwise noted. Table 4 Device Characteristics SYMBOL DESCRIPTION CONDITIONS MIN TYP MAX UNITS 11.4 12 12.6 V Input Supplies & Switching Frequency VIN IIN2 IIN_A IIN_S FSW_LOW FSW_HIGH Input Supply Operating Voltage Range1 Standby Input Current Sleep Mode Input Current Switching Frequency at SW After power-up sequence complete. Average including pinging = 5V to VIN EN 18 460 WPC-compliant Operating Range mA 600 A 205 kHz kHz 110 UVLO & Current Limit Under-Voltage Protection Trip Point VIN_UVLO Over-Current Protection Trip Point IIN_OCP VIN rising VIN falling Hysteresis VIN = 12.6V, cycle-by-cycle protection. 10.3 9.0 625 V mV 5.2 6.5 A 11.4 12.6 V 5.5 8 V mA DC-DC Converter (For Biasing Internal Circuitry Only)3 VBUCK5VT_IN VBUCK5VT IOUT5 FSW Input Voltage Range1 Output Voltage External Load Switching Frequency at LX External ILoad = 8mA 4.5 5 3 MHz 5 2.5 V V mA Low Drop Out Regulators (For Biasing Internal Circuitry Only)3 LDO2P5V3 VLDO2P5V_IN VLDO2P5V IOUT Input Voltage Range Output Voltage External Load Supplied from BUCK5VT ILoad = 2mA Input Voltage Range Output Voltage See Note 1. ILoad = 2mA 8 LDO5V 3 VREG_IN VLDO5V 11.4 12.6 5 V V Thermal Shutdown TSD Revision 1.0.0 Thermal Shutdown Temperature Rising Threshold Temperature Falling Threshold 4 140 110 C (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, EN unless otherwise noted. Table 4 Device Characteristics, Continued SYMBOL DESCRIPTION CONDITIONS MIN EN VIH VIL IEN EN input current TYP MAX UNITS 900 550 mV mV VEN = 5V 7.5 A VEN = VIN = 12.6V 35 A General Purpose Inputs / Outputs (GPIO) VIH VIL ILKG VOH VOL IOH IOL Input Threshold High Input Threshold Low Input Leakage Output Logic High Output Logic Low Output Current High Output Current Low 3.5 8 1.5 +1 V V A 1.5 +1 -1 4 IOH=-8mA IOL=8mA V V A V V mA mA 0.5 -8 RESET VIH VIL ILKG SCL, SDA Input Threshold High Input Threshold Low Input Leakage (I2C Clock Frequency fSCL Clock Frequency fSCL Clock Frequency Hold Time (Repeated) for START Condition tHD;DAT Data Hold Time tLOW tHIGH Clock Low Period Clock High Period Set-up Time for Repeated START Condition tSU;STA Revision 1.0.0 -1 Interface) fSCL tHD;STA 3.5 EEPROM loading, Step 1, P9036B as Master EEPROM loading, Step 2, P9036B as Master P9036B as Slave I2C-bus devices 5 0 100 kHz 300 kHz 400 kHz 0.6 s 10 ns 1.3 0.6 s s 100 ns (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet ELECTRICAL CHARACTERISTICS = RESET = 0V, REG_IN = BUCK5VT_IN = 12V. TA = -40 to +85C, unless otherwise noted. Typical values are at 25C, EN unless otherwise noted. Table 4 Device Characteristics, Continued SYMBOL DESCRIPTION Bus Free Time Between STOP and START Condition Capacitive Load for CB Each Bus Line SCL, SDA Input CBIN Capacitance5 VIL Input Threshold Low VIH Input Threshold High ILKG Leakage Current Output Logic Low VOL (SDA) Analog-to-Digital Converter ADC Conversion N Resolution fSAMPLE Sampling Rate Number of Channels Channel at ADC MUX input ADC Clock ADCCLK Frequency Full-Scale Input VIN_FS Voltage CONDITIONS MIN tBUF TYP MAX 1.3 s 100 5 When powered by device 5V UNITS pF pF 1.5 V 1.0 A 0.5 V 3.5 V -1.0 IPD= 2mA 12 Bit 62.5 kSPS 8 1 MHz 2.39 V 40 MHz 2.5 V Microcontroller FCLOCK VMCU Clock Frequency MCU Supply Voltage from internal 2.5V LDO Note 1: BUCK5VT_IN, REG_IN. These pins must be connected together at all times. Note 2: This current is the sum of the input currents for REG_IN and BUCK5VT_IN. Note 3: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM, thermistor, LED, buzzer and pull-up resistor loads (up to an absolute maximum of 8mA), as recommended in the WPC "Qi" Compliance Schematic and the WPC "Qi" Compliance Bill of Materials. If any of these outputs is used to power external loads, the performance of the P9036B is not guaranteed. Note 4: Any of the GPIO pins is capable of sourcing 8mA, but if more than one is sourcing current, the total current must not exceed 8mA. Note 5: The 2.5V LDO is powered by the 5V DC/DC converter, so the LDO's output current must be counted in the output current budget of the DC/DC converter. Revision 1.0.0 6 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet PIN CONFIGURATION IC6 IC5 IC4 IC3 IC2 GND IC1 HPF ISNS IN2 IN1 IN TQFN-48L 48 47 46 45 44 43 42 41 40 39 38 37 GPIO6 1 36 NC5 GPIO5 2 35 SW2 GPIO4 3 34 SW1 GPIO3 4 33 SW GPIO2 5 32 PGND3 GPIO1 6 31 NC4 EP (Center Exposed Pad) NC1 10 27 VOSNS NC2 11 26 LX RESET 12 25 BUCK5VT_SNS 13 14 15 16 17 18 19 20 21 22 23 24 BUCK5VT_IN PGND NC3 28 DGND 9 AGND SDA BST PGND1 BUCK5VT 29 LDO2P5V_IN 8 LDO2P5V SCL LDO5V PGND2 REG_IN 30 REFGND 7 EN GPIO0 Figure 2 P9036B Pin Configuration (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm, 0.4mm pitch) Revision 1.0.0 7 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet PIN DESCRIPTION Table 5 P9036B NTG48 Package Pin Functions by Pin Number 1 GPIO6 I/O General purpose input/output 6. 2 GPIO5 I/O General purpose input/output 5. 3 GPIO4 I/O General purpose input/output 4. 4 GPIO3 I/O General purpose input/output 3. 5 GPIO2 I/O General purpose input/output 2. 6 GPIO1 I/O General purpose input/output 1. 7 GPIO0 I/O General purpose input/output 0. 8 SCL I/O I2C clock. 9 SDA I/O I2C data. 10 NC1 - Internally connected. Must be connected to GND. 11 NC2 - Internally connected. Must be left unconnected. 12 RESET I Active-high chip reset pin. A 47k resistor must be connected between this pin and GND. 13 EN I Active-low enable pin. Device is suspended and placed in low current (sleep) mode when pulled high. Tie to GND for stand-alone operation. 14 REFGND - Signal ground connection. Must be connected to AGND. 15 REG_IN1 I LDO5V power supply input. As a minimum, a 1F ceramic capacitor must be connected between this pin and PGND. This pin must be connected to pin 24. 16 LDO5V2 O 5V LDO output. As a minimum, a 1F ceramic capacitor must be connected between this pin and PGND. 17 LDO2P5V2 O 2.5V LDO output. As a minimum, a 1F ceramic capacitor must be connected between this pin and PGND. 18 LDO2P5V_IN I 2.5V LDO input. The LDO2P5V_IN input must be connected to BUCK5VT. As a minimum, a 0.1F ceramic capacitor must be connected between this pin and GND. 19 BUCK5VT2 I Power and digital supply input to internal circuitry. Revision 1.0.0 8 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet Table 5 P9036B NTG48 Package Pin Functions by Pin Number PIN NAME TYPE DESCRIPTION 20 BST I Bootstrap pin for BUCK converter top switch gate drive supply. 21 AGND - Analog ground connection. Connect to signal ground. Must be connected to REFGND. 22 DGND - Digital ground connection. Must be connected to GND. 23 NC3 - Internally connected. Must be left unconnected. 24 BUCK5VT_IN1 I Buck converter power supply input. As a minimum, a 0.1F in parallel with a 1F ceramic capacitor must be connected between this pin and PGND. This pin must be connected to pin 15. 25 BUCK5VT_SNS I Buck regulator feedback. Connect to the high side of the buck converter output capacitor. 26 LX O Switch Node of BUCK converter. Connects to one of the inductor's terminals. 27 VOSNS I Voltage sense input. This pin can be used to sense voltages such as thermistors, GPIOs, Input voltages. See the Electrical Characteristics Table (VIN_FS) for input voltage limits. 28 PGND - Power ground. 29 PGND1 - Power ground. 30 PGND2 - Power ground. 31 NC4 - Internally connected. Must be left unconnected. 32 PGND3 - Power ground. 33 SW O 34 SW1 O 35 SW2 O 36 NC5 - 37 IN I 38 IN1 I 39 IN2 I 40 ISNS O Revision 1.0.0 Internal - monolithic - power MOSFET, half bridge switching node. These pins drive the transmitter coil. Internally connected. Must be left unconnected. Internal - monolithic - power MOSFET, half bridge power supply input pins. ISNS output signal. Current used by the transmitter as measured at the input voltage. Attach a 22nF ceramic capacitor to this pin for filtering purposes. 9 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet Table 5 P9036B NTG48 Package Pin Functions by Pin Number PIN NAME TYPE I DESCRIPTION 41 HPF High pass filter input. This pin is used to read the communication from the receiver. 42 IC1 43 GND 44 IC2 Reserved for special designs. Must be connected to GND. 45 IC3 Reserved for special designs. Must be left unconnected. 46 IC4 Reserved for special designs. Must be left unconnected. 47 IC5 Reserved for special designs. Must be connected to GND. 48 IC6 Reserved for special designs. Must be left unconnected. 49 EP (Center Exposed Pad) Reserved for special designs. Must be connected to GND. - Thermal Ground. EP, Center Exposed Pad, is on the bottom of the package and must be electrically tied to GND. For good thermal performance, solder to a large copper pad embedded with a pattern of plated through-hole vias. The die is not electrically bonded to the EP, and the EP must not be used as a current-carrying electrical connection. Note 1: REG_IN, BUCK5VT_IN. These pins must be connected together at all times. Note 2: DC-DC BUCK5VT, LDO2P5V and LDO5V are intended only as internal device supplies and must not be loaded externally except for the EEPROM, thermistor, LED, buzzer and pull-up resistor loads (up to an absolute maximum of 8mA), as recommended in the WPC "Qi" Compliance Schematic and the WPC "Qi" Compliance Bill of Materials. Revision 1.0.0 10 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet TYPICAL PERFORMANCE CHARACTERISTICS Total System Efficiency (%) vs Rx Output Power (W) DC_IN to DC_OUT, Tx=IDTP9036B, Rx=IDTP9220, Vin=12V, Vout=5V 80% 70% Efficiency (%) 60% 50% 40% 30% 20% 10% 0% 0 0.5 1 1.5 2 2.5 3 3.5 Reciever Output Power (W) 4 4.5 5 Figure 3. Efficiency vs. RX Output Power Revision 1.0.0 11 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet BLOCK DIAGRAM IN LDO5V LDO2P5V BUCK5VT_SNS LX 3MHZ REG_IN BUCK5VT BUCK5VT LDO2P5V_IN BUCK5VT_IN VIN_UVLO EN Enable Sequence LDO5V Current Limit LDO2P5V UVLO_5V/ 2P5V Temp. Signal REF Driver Control IBIAS THSHDN ISNS HALF BRIDGE PMOS NMOS FET PAIR REF VIN_OVP Demodulator GND SDA I2C RAM ROM OTP HPF ISNS Temp. Signal Micro Controller Unit (MCU) ADC VOSNS MCU Peripherals SCL SW VOSNS GPIO VINSNS GPIO_<6:0> REG_IN RESET Clock Generation PGND RC OSC IDTP9036B PLL Figure 4. P9036B Internal Functional Block Diagram Revision 1.0.0 12 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet THEORY OF OPERATION The P9036B is a highly-integrated WPC1 (Wireless Power Consortium)-compliant wireless power charging IC solution for the transmitter base station. It can deliver 5W in WPC "Qi" mode using near-field magnetic induction as a means to transfer energy UNDER VOLTAGE LOCKOUT (UVLO) The P9036B has a built-in UVLO circuit that monitors the input voltage and enables normal operation, as shown in the following figure: UVLO exit event OVERVIEW VCOIL (10V/div) Figure 1 shows the block diagram of the P9036B. When the VIN_UVLO block detects that the voltage at REG_IN and BUCK5VT_IN (connected together externally) is above the Vin_rising UVLO threshold and EN is at a logic LOW, the Enable Sequence circuitry activates the voltage reference, the 5V and 2.5V LDOs, and the 5V buck switching regulator. VIN (5V/div) The voltages at the outputs of the LDOs and the buck regulator are monitored to ensure that they remain in regulation, and the adaptor voltage, coil current, and internal temperature are monitored. 0V The digital block and the MCU drive an internal half bridge inverter. This inverter powers the transmitter (Tx) coil through the SW pins. The Tx and reciever (Rx) act as a loosely coupled, air core transformer. The Tx coil generates a magnetic field that supplies energy to the Rx coil The Rx uses that field to generate a DC output voltage that is applied to the load. VIN=10V 0V Time (1s/div) Figure 4 VIN versus UVLO threshold with /EN low. OVER-TEMPERATURE PROTECTION The internal temperature of the P9036B is monitored. The part shuts down if the temperature exceeds 140C (typ) and reactivates when the temperature falls below 110C (typ). Communication packets from the receiver in the mobile device are detected and filtered by an external operational amplifier and passive filter, then provided to the HPF pin to be further processed by the Demodulator and converted to digital signals that can be read by the MCU. INTERNAL DRIVERS and INVERTER Several internal voltages are digitized by the ADC and supplied to the MCU for system control and algorithm - related purposes. Two GPIO ports are available to the system designer for driving LEDs and a buzzer. The clock for the MCU and other circuitry is generated by an internal RC oscillator. I2C SDA and SCL pins permit communication with an external device or host. The internal gate driver circuitry drives the transmitter coil which delivers energy to the reciever (Rx) coil. The internal FETs are configured as a power inverter that switches the top sides of the resonant circuits between the VIN supply voltage and ground at a rate set by the MCU control algorithm. DEMODULATOR Power is transferred from the transmitter to the receiver through the coupling of their respective coils: a looselycoupled transformer. The amount of power transferred is determined by the transmitter's switching frequency Note 1 - Refer to the WPC specification at http://www.wirelesspowerconsortium.com/ for the most current information Revision 1.0.0 13 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet EXTERNAL CHIP RESET and EN (110kHz-205kHz, by WPC1), and is controlled by the receiver through instructions the receiver sends back through the same coils to the transmitter to increase or decrease power, end power transfer, or another WPC command. The instructions take the form of data packets which the receiver modulates on the carrier. The modulation is detected and then coupled through a series of filters connected to the P9036B's Demodulator and then fed to the HPF pin. Recovering the data packets is the function of the Demodulator. Decoding and executing the packets is one of the functions of the MCU. The P9036B can be externally reset by pulling the RESET pin to a logic high above the VIH level. The RESET pin is a dedicated high-impedance active-high digital input, and its effect is similar to the power-up reset function. Because of the internal low-voltage monitoring scheme, the use of the external RESET pin is not mandatory. A manual external reset scheme can be added by connecting 5V to the RESET pin through a simple switch. When RESET is HIGH, the microcontroller's registers are set to the default configuration. When the RESET pin is released to a LOW, the microcontroller starts executing the code from the EEPROM. MICROCONTROLLER UNIT (MCU) The P9036B's MCU processes the algorithm, commands, and data that control the power transferred to the receiver. The MCU is provided with RAM and ROM, and parametric trim and operational modes are set at the factory through the One-Time Programming (OTP) block, read by the MCU at power-up. Communication with external memory is performed through I2C via the SCL and SDA pins. If the particular application requires the P9036B to be disabled, this can be accomplished with the EN pin. When the EN pin is pulled high, the device is suspended and placed in low current (sleep) mode. If pulled low, the device is active. APPLICATIONS INFORMATION The current into EN is approximately The recommended applications schematic diagram is shown in Figure 7. The P9036B operates from a 12VDC (5%) input. The switching frequency varies from 110kHz to 205kHz. The power transfer is controlled via changes in switching frequency. The base or TX-side has three series-resonance circuits made of a WPC Type-A6 triple coil and three capacitors. The resonant circuits are driven by an internal half-bridge inverter, as shown in Figure 5. Only the resonant circuit that is aligned with the receiver coil is activated. The selection is made by voltage levels from GPIO0, GPIO2 and GPIO6, each of which drives one of three external selection FETs directly which activates the respective coil. 12V + - Internal MOSFET Driver = -2 300 for input voltages between VIN and +2V, and close to zero if V(EN ) is less than 2V. SYSTEM FEEDBACK CONTROL (WPC) The P9036B contains logic to demodulate and decode error packets sent by the mobile device (Rx-side), and adjusts power transfer accordingly. The P9036B varies the switching frequency of the internal half bridge inverter between 110kHz to 205 kHz to adjust power transfer. The mobile device controls the amount of power transferred via a communication link that exists from the mobile device to the base station. The mobile device (any WPCcompliant receiver) communicates with the P9036B via Communication Packets. Each packet has the following format: A6 Coil Table 6 - Data Packet Format. Preamble GPIO0 GPIO2 GPIO6 Header Message Checksum The overall system behavior between the transmitter and receiver follows the state machine diagram below: Figure 5 Half Bridge Inverter TX Coil Driver. Revision 1.0.0 14 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet IDENTIFICATION AND CONFIGURATION (ID & Config) In this phase, the P9036B tries to identify the mobile device and collects configuration information. Required packet(s) in ID & Config: 1. Identification Packet (0x71) 2. Extended Identification Packet (0x81)* 3. Configuration Packet (0x51) * If Ext bit of 0x71 packet is set to 1. Also, the P9036B must correctly receive the following sequence of packets without changing the operating point (175 kHz @ 50% duty cycle): 1. Identification Packet (0x71) 2. Extented Identification (0x81) 3. Up to 7 optional configuration packets from the following set: Power Control Hold-Off Packet (0x06), Proprietary Packet (0x18 - 0xF2), Reserved Packet 4. Configuration Packet (0x51) Figure 6 System State Machine Diagram The P9036B performs four phases: Selection, Ping, Identification & Configuration, and Power Transfer. If the P9036B detects a valid configuration sequence, with the proper timing, then it will move to the Power Transfer phase. Otherwise, it will terminate the power signal and revert to the Selection phase. START (SELECTION) PHASE In this phase, the P9036B operates in a low power mode to determine if a potential receiver has been placed on the coil surface prior to the PING state. At regular intervals, the P9036B applies a brief AC signal sequentially to each one of the coils of the triple A6 coil and listens for a response. When a response is found, the P9036B keeps that coil selected for all subsequent operations. POWER TRANSFER PHASE In this phase, the P9036B adapts the power transfer to the receiver based on control data it receives as contained in the Control Error Packets. Required packet(s) in Power Transfer: PING PHASE 1. Control Error Packet (0x03) 2. Rectified Power Packet (0x04) In this phase, the P9036B applies a power signal at 175 kHz with a fixed 50% duty cycle and attempts to establish a communication link with a mobile device. For this purpose, the P9036B may receive zero or more of the following packets: Required packet(s) in PING: 1. 2. 3. 4. 5. 6. 1. Signal Strength Packet (0x01) The mobile device must send a Signal Strength Packet within a time period specified by the WPC, otherwise the power signal is terminated and the process repeats. If the P9036B does not detect the start bit of the header byte of the Signal Strength Packet during the Ping Phase, it removes the Power Signal after a delay. If a Signal Strength Packet is received, the P9036B goes to the Identification and Configuration Phase. Revision 1.0.0 Control Error Packet (0x03) Rectified Power Packet (0x04) Charge Status Packet (0x05) End Power Transfer Packet (0x02) Any Proprietary Packet Any reserved Packets If the P9036B receives a packet that does not comply with the sequence, or if the time limits for receiving the 15 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet expected packets are exceeded, then P9036B will terminate the power signal and revert to the Selection phase. EXTERNAL OVER TEMPERATURE PROTECTION At all times the P9036B periodically checks the DC voltage from the external thermistor circuit. If the external temperature limit is exceeded, then the P9036B immediately terminates the power transfer and signals an error condition on the LED outputs. It remains in this state until the over temperature condition is corrected. FOREIGN OBJECT DETECTION (FOD) The P9036B supports foreign object detection in accordance with WPC specifications. Periodically the Receiver reports to the P9036B the amount of received power by sending a Received Power packet. The P9036B compares the amount of power transmitted with the report amount of received power. If too much power is being lost then the presence of a foreign object is assumed. In that case, the P9036B terminates the power transfer and signals an error condition on the LED outputs. The calibration of the FOD is primarily set in the P9036B firmware. However, some adjustment of the FOD is possible by changing external resistor values that change the DC voltage seen by GPIO4.There are three cases for 1. Pull down resistor only is no adjustment to the internal firmware's FOD setting. 2. Pull up resistor only disables the FOD function 3. A combination of pullup/pulldown resistors creates a DC voltage which determines an amount of offset that will be added or subtracted from the internal firmware settings. If the DC voltage is approximately 1.20V then the adjustment will be zero. If the voltage is greater than 1.2V then the adjustment will increase the allowance for foreign objects up to approximately 300mW additional loss. If the voltage is less than 1.2V then the adjustment will decrease the allowance for foreign objects up to approximately 300mW less loss. This adjustment is proportional throughout a voltage range between approximately 50mV to 2.35V Revision 1.0.0 16 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet APPLICATIONS INFORMATION VIN1 GND1 KELVIN CONNECTION (Note_1) SW1 C34 100pF R3 0.02 5 4 15K LM321 R6 2 C8 C9 68nF 82nF 56nF VIN3 1 VIN 3 R7 A6 3-Coil Tx L2 L3 4.7uH 330K C10 22n R8 3.9K C3 82nF C38 1uF 0.1uF C13 R9 2 U1 ISNS R5 1K C7 56nF 4 VISNS1 R4 1.2K C6 82nF 6 ISNS1 C4 0.1uF C5 5 GNDAD1 1 C1 3 J1 0.1uF AC_Adapter VINAD1 10uF C14 GPIO5 78.7K 10K 4.7K 4.7K 8 9 RST SCL SDA WP GPIO5 40 IO0 NP Th2 Q4 NP LDO2P5V 2 41 C28 5 P-VSNS R26 27K 1.8nF C30 C27 22nF/50V C31 3.3nF R30 47K R28 10K R27 C29 R29 3.3nF 15K 1.5K D3 D4 D5 5 IO2 GPIO2 R33 10K Th3 Q5 NP Q6 2N7002 Note_1: Traces from R4, R5 must be connected directly to the terminals of the sense resistor, and these trace must not carry any current except that which flows into R4 and R5. This is to avoid measurement errors in the op amp circuit. LDO2P5_OUT 2N7002 GPIO2 C33 1uF GPIO0 Note_2: Place C28 as close as possible to pin 41. Place all other components in this block as close as possible to C28. THIS DOCUMENT CONTAINS INFORMATION PROPRIETARY TO Integrated Device Technology, Inc. (IDT). USE OR DISCLOSURE WITHOUT THE WRITTEN PERMISSION OF AN OFFICER OF IDT IS EXPRESSLY FORBIDDEN Title 17 Integrated Device Technology, Inc. P9036B schematics Size Document Number Date: Tuesday , January 19, 2016 14:43:52 Figure 7 P9036B Schematic Revision 1.0.0 GPIO6 GPIO5 R25 15K 6 IC5 IC3 IC4 46 45 IC2 EN NC1 GPIO2 17 44 13 10 GPIO6 GPIO6 2N7002 GPIO2 C32 0.1uF Th1 GPIO1 GPIO0 11 27 21 14 43 49 22 42 OPTIONAL 1 4 ISNS 6.8nF GPIO6 Q2 3 2 1 6.8nF P-HPF 7 4 Q1 GPIO0 HPF IO6 4 Q3 C37 100pF C25 22nF/50V J2 GPIO0 5 5 R18 0.1 C23 3 2 1 ISNS 32 30 29 28 SCL SDA 47K 1 35 34 33 3 2 1 IN IN1 IN2 RESET IDTP9036B NC2 VOSNS AGND REFGND GND EP DGND IC1 I2C connector 0.1uF 37 38 39 25 19 18 23 31 36 48 26 LX LDO5V PGND3 PGND2 PGND1 PGND R24 1 2 3 4 5 6 7 8 9 10 22uF SiR826ADP 16 C24 1uF 12 C18 SiR826ADP R23 SW2 SW1 SW D6 U2 GPIO3 C17 SiR826ADP R22 GPIO4 22uF 1 LDO5V R21 4 C15 DIODE SCHOTTKY 4.7K 8 7 6 5 3 IO3 C36 100pF 47 EPAD 9 C26 0.1uF IO4 R20 GREEN LEDB VCC WP SCL SDA R19 4.7K OPTIONAL D2 C19 0.1uF BUCK5VT_SNS BUCK5VT LDO2P5V_IN RED D1 A0 A1 A2 VSS 24 15 R17 47k LEDA 1 2 3 4 0.1uF R16 47k 390 Buzzer C16 47nF C11 NC3 NC4 NC5 IC6 2 10uF 20 R15 1 U3 24AA64T-I/MNY R14 NP BST R13 NP BUCK5VT_IN REG_IN BZ1 C12 LDO2P5_OUT OPTIONAL (c) 2016 Integrated Device Technology, Inc. Sheet Rev 1 of 1 P9036B Preliminary Datasheet Table 7 P9036B Bill Of Materials Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Quantity 1 2 1 1 3 2 1 5 2 2 1 1 3 2 1 1 1 1 2 1 1 1 3 1 25 18 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 2 1 1 1 1 3 3 1 1 1 1 1 1 1 2 1 3 1 4 1 1 1 1 1 1 1 1 3 1 1 1 Reference BZ1 C1,C17 C3 C4 C5,C7,C8 C6,C9 C10 C11,C13,C19,C26,C32 C12,C14 C15,C18 C16 C23 C24,C33,C38 C25,C27 C28 C29 C30 C31 C34,C36 C37 D1 D2 D3,D4,D5 D6 VISNS1,VINAD1,SW1,IS NS1,GNDAD1,IO2,VIN3, IO3,IO4,LDO5V,IO6,WP, SDA,SCL,RST,P-VSNS,PHPF,IO0 VIN1,GND1 J1 J2 L2 L3 Q1,Q2,Q3 Q4,Q5,Q6 R3 R4 R5 R6 R7 R8 R9 R13,R14 R15 R16,R17,R30 R18 R19,R20,R22,R23 R21 R24 R25 R26 R27 R28 R29 R33 Th1,Th2,Th3 U1 U2 U3 Part Buzzer 0.1uF 68nF 0.1uF 82nF 56nF 22n 0.1uF 10uF 22uF 47nF 6.8nF 1uF 22nF/50V 6.8nF 3.3nF 1.8nF 3.3nF 100pF 100pF RED GREEN Diode DIODE SCHOTTKY PCB Footprint buzz_ps1240 402 1206 402 1206 1206 402 603 805 1206 603 402 603 603 402 603 402 402 603 603 0603_DIODE 0603_DIODE SOD123 SOD123FL Description BUZZER PIEZO 4KHZ 12.2MM PC MNT CAP CER 0.1UF 50V 10% X7R 0402 CAP CER 0.068UF 100V NP0 1206 CAP CER 0.1UF 50V 10% X7R 0402 CAP CER 0.082UF 100V NP0 1812 CAP CER 0.056UF 100V NP0 1812 CAP CER 2200PF 50V 10% X7R 0402 CAP CER 0.1UF 50V 10% X7R 0603 CAP CER 10UF 25V 20% X5R 0805 CAP CER 22UF 25V 10% X5R 1206 CAP CER 0.047UF 16V 10% X7R 0603 CAP CER 6800PF 50V X7R 0402 CAP CER 1UF 25V 10% X7R 0603 CAP CER 0.022UF 50V 10% X7R 0603 CAP CER 6800PF 50V 10% X7R 0402 CAP CER 3300PF 100V 10% X7R 0603 CAP CER 1800PF 50V 10% X7R 0402 CAP CER 3300PF 50V 10% X7R 0402 CAP CER 100PF 50V 10% X7R 0603 CAP CER 100PF 50V X7R 0603 LED RED DIFFUSED 0603 SMD LED GREEN DIFFUSED 0603 SMD DIODE GEN PURP 200V 200MA SOD123 DIODE SCHOTTKY 200V 2A SOD123FL NP TP30 TEST POINT 30MIL THROUGH HOLE VC6 AC_Adapter I2C connector A6 3-Coil Tx 4.7uH SiR826ADP 2N7002 0.02 1.2K 1K 15K 330K 3.9K 78.7K NP 390 47K 0.1 4.7K 10K 47K 15K 27K 1.5K 10K 15K 10K NP LM321 IDTP9036B 24AA64T-I/MNY SMD_5015 CONN_POWER_JACK5_5MM LOPRO8PIN01INREVB 3coil_a6_standard 805 SOIC8LD_PWRPAK_FET SOT23_3 805 402 402 402 402 402 402 402 402 402 402 402 402 402 402 402 603 603 603 402 NTC1 SOT23-5 NTG_48LD_6X6MM_0P4PITCH DFN8 PC TEST POINT MINIATURE SMT CONN PWR JACK 2.1X5.5MM HIGH CUR CONN HEADER LOPRO STR 10POS GOLD TX-A6 COIL FIXED IND 4.7UH 600MA 400 MOHM MOSFET N-CH 80V 60A PPAK SO-8 MOSFET N-CH 60V 310MA SOT323 RES SMD 0.02 OHM 1% 1/8W 0805 RES 1.2K OHM 1/10W 1% 0402 SMD RES SMD 1K OHM 1% 1/10W 0402 RES SMD 15K OHM 1% 1/10W 0402 RES 330K OHM 1/16W 5% 0402 SMD RES 3.9K OHM 1/10W 5% 0402 SMD RES SMD 78.7K OHM 1% 1/10W 0402 Part Number PS1240P02CT3 C1005X7R1H104K C3216C0G2A683K160AC C1005X7R1H104K C1812C823J1GACTU C1812C563J1GACTU C1005X7R1E222K GRM188R71H104KA93D C2012X5R1E106M GRM31CR61E226KE15L GRM188R71C473KA01D C1005X7R1H682K050BA C1608X7R1E105K C1608X7R1H223K C1005X7R1H682K C1608X7R2A332K 04025C182KAT2A C1005X7R1H332K C0603C101K5RACTU C0603C101K5RACTU L29K-G1J2-1-0-2-R18-Z LG L29K-G2J1-24-Z BAV21W-7-F MBR2H200SFT1G 5015 PJ-002AH 5103308-1 Y31-60050F MLP2012V4R7MT0S1 SiR826ADP 2N7002WT1G WSL0805R0200FEA ERJ-2RKF1201X ERJ-2RKF1001X ERJ-2RKF1502X RC0402JR-07330KL ERJ-2GEJ392X ERJ-2RKF7872X NP ERJ-2GEJ391X RES SMD 390 OHM 5% 1/10W 0402 ERJ-2GEJ473X RES SMD 47K OHM 5% 1/10W 0402 RES SMD 0.1 OHM 1% 1/10W 0402 RUT1005FR100CS ERJ-2GEJ472X RES SMD 4.7K OHM 5% 1/10W 0402 RES SMD 10K OHM 5% 1/10W 0402 ERJ-2GEJ103X ERJ-2GEJ473X RES 47K OHM 1/10W 5% 0402 SMD RES SMD 15K OHM 5% 1/10W 0402 ERJ-2GEJ153X ERJ-2GEJ273X RES SMD 27K OHM 5% 1/10W 0402 RES SMD 1.5K OHM 5% 1/10W 0603 ERJ-3GEYJ152V RES SMD 10K OHM 1% 1/10W 0603 ERJ-3EKF1002V RES SMD 15K OHM 5% 1/10W 0603 ERJ-3GEYJ153V ERJ-2RKF1002X RES SMD 10K OHM 1% 1/10W 0402 THERMISTOR NTC K 5% RADIAL NTCLE203E3103JB0 IC OPAMP GP 1MHZ SOT23-5 LM321MFX 12V Wireless Power Transmitter IC for TX-A6 P9036B IC EEPROM 64KBIT 400KHZ 8TDFN 24AA64T-I/MNY Manufacturer TDK Corporation TDK Corporation TDK Murata Murata TDK Murata TDK Murata Murata TDK TDK TDK TDK Corporation TDK AVX TDK Corporation Kemet Kemet OSRAM OSRAM Diodes Incorporated ON Semi Keystone Electronics CUI INC TE TDK Corporation Vishay ON Semi Vishay Panasonic Panasonic Panasonic Yageo Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Vishay TI IDT Microchip Technology Note 1: C0G/NPO-type ceramic capacitors are recommended for use as the resonance capacitors (C2 through C7). COG/NPO values stay relatively constant with voltage while X7R and X5R ceramic capacitor values de-rate from 40% to over 80%. Revision 1.0.0 18 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet External Components sequencing will stop and the P9036B will use the firmware that is up loaded from that address. The P9036B requires a minimum number of external components for proper operation (see the BOM in Table 7). A complete design schematic compliant to the WPC "Qi" standard is given in Figure 7. It includes WPC "Qi" LED signaling, buzzer, and an EEPROM for loading P9036B firmware. Overview of Standard GPIO Usage There are 7 GPIO's on the P9036B transmitter IC, of which two are available for use as follows: * * * I2C Communication The P9036B includes an I2C block which can support either I2C Master or I2C Slave operation. After power-onreset (POR),the P9036B will initially acts as an I2C Master for the purpose of downloading firmware from an external memory device, such as an EEPROM. * Table 8 table lists how the red and green LEDs can be used to display information about the P9036B's operating modes. The table also includes information about external resistors or internal pull up/down options to select LED modes. The I2C Master mode on the P9036B does not support multi-master mode, and it is important for system designers to avoid any bus master conflict until the P9036B has finished any firmware uploading and has released control of the bus as I2C Master. After firmware downloaded from external memory is complete, and when the P9036B begins normal operation, the P9036B is configured by the standard firmware to be exclusively in I2C Slave mode. LED FUNCTIONS Two GPIOs are used to drive LEDs, which indicate, through various on/off and illumination options, the state of charging and some possible fault conditions. EEPROM As shown in Figure 8, one or two resistors configure the defined LED option combinations. The DC voltage set in this way is read one time during power-on to determine the LED configuration. The P9036B EVK supports an external EEPROM memory chip,pre-programmed with a standard operating firmware that is automatically loaded when 5V power is applied. The P9036B uses I2C master address 0x52 to access the EEPROM. The P9036B slave address is 0x39. If the standard firmware is not suitable for the application, a custom EEPROM or internal factory programmed ROM is possible. LDO2P5V_OUT IDTP9036 Ra GPIO3 For future flexibility, the P9036B will first sequentially try to communicate with the EEPROM first using address 0x50, then 0x52, and finally 0x54. Each address supports a different formatting of the EEPROM data. At this time, the only supported format is at address 0x52. When the P9036B receives a response from the EEPROM, the Revision 1.0.0 GPIO0,2,6: Selects one of the three available coils. GPIO1,5: Manages the demodulation signal selection. GPIO3: Green LED and external resistors for choosing LED mode. GPIO4: Red LED and AC or DC buzzer (optional) and external resistors for choosing FOD offset option. Resistor to set options To ADC Rb LED Mode Resistor Configuration Figure 8 P9036B LED Resistor Options. 19 (c) 2016 Integrated Device Technology, Inc P9036B Product Datasheet Table 8 - P9036B LED Functions LED Control Option 1 LED Select GPIO3 Voltage Pull Down <=0.080V 2 0.220V 3 0.370V 4 0.510V 5 0.660V 6 0.810V Description Dual-LED, Standby - On Blink Dual LED, Standby - On No-Blink Single-LED, Standby OFF Blink Single-LED, Standby OFF No Blink Dual LED, Standby - Off No-Blink Dual LED, Standby - Off Red Indicate, No-Blink 7 1.000V Reserved 8 1.100V Reserved 9 1.250V Pull Up >=1.500V Reserved Dual-LED, Standby - Off Blink 10 LED #/ Color Standby LED1- Green On LED2- Red On LED1- Green On LED2- Red On LED1- Green Off LED2- n/a LED1- Green Off LED2- n/a LED1- Green Off LED2- Red Off LED1- Green Off LED2- Red Off LED1- Green LED2- Red LED1- Green LED2- Red LED1- Green LED2- Red LED1- Green Off LED2- Red Off Transfer Blink 1Hz Off On Off Blink 1Hz On On Off Off On Blink 1Hz Off Operational Status Complete CS100 On Blink 0.5Hz Off Off Off Blink 0.5Hz Off Off On Blink 0.5Hz Off Blink 0.5Hz Off Blink 0.5Hz Off Off On Off Off Blink 0.5Hz On Off Low-Power Blink 2Hz Off Blink 2Hz Off Blink 2Hz Blink 2Hz Blink 2Hz Off Off Blink 2Hz Blink 0.5Hz Blink 2Hz Off Off Fault OFF Blink 4Hz OFF Blink 4Hz Blink 4Hz Blink 4Hz Off Blink 4Hz Off Blink 4Hz Off Blink 4Hz Note 1 - Voltage divider on GPIO3 should use 1% resistors with parallel impedance approximately 20k-50k. CS100 is indicated when Rx sends "Charge Status 100" message. Normal indication resumes after Rx sends "Charge Status 90" or less. CS100 Blink is approximately 68% on-time "Low Power" is indicated in USB powered applications when USB does not provide sufficient DC power "Low Power" Blink is approximately 80% on-time Note 2 - LED Select voltage should be within 3% of listed value. Buzzer Function The P9036B supports audible notification when the receiver sends a "Charge Complete" during the power transfer state. If "Charge Complete" is sent as the very first packet before being in the power transfer state, there is no buzzer indication for this case. The duration of the "Charge Complete" indication sound is approximately 200ms. An optional buzzer feature is supported on GPIO4 which is able to drive directly a piezoelectric type transducer without amplification. As shown on the reference schematic, a series current limiting resistor should be included if a buzzer device is included. The buzzer signal is approximately a 2kHz square wave, and it is recommended to use a buzzer with a 2kHz resonant frequency for best results. Decoupling/Bulk Capacitors Buzzer Action: Power Transfer Indication As with any high-performance mixed-signal IC, the P9036B must be isolated from the system power supply noise to perform optimally. A decoupling capacitor of 0.1F must be connected between each power supply and the PCB ground plane as close to these pins as possible. For optimum device performance, the decoupling capacitor must be mounted on the component side of the PCB. Additionally, medium value capacitors in the 22F The P9036B supports audible notification when the device operation successfully reaches the Power Transfer state. The duration of the Power Transfer indication sound is approximately 200ms. Buzzer Action: Charge Complete Indication Revision 1.0.0 20 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet range must be used at the VIN inputs (IN,IN1,IN2) to minimize ripple current and voltage droop due to the large current requirements of the resonant half Half-Bridge driver. The value of the capacitors will decrease as the voltage applied approaches the nominal voltage, due to the ceramic dielectric characteristics. For example, a 22F X7R 25V capacitor's value could be as low as 6F when operating at 13V, depending on the manufacturer. Output Capacitor For proper voltage regulation and stability, a capacitor is required on the output of each LDO (LDO2P5V and LDO5V). The output capacitor must be placed as close to the device and power (PGND) pins as possible. Since the LDOs have been designed to function with very low ESR capacitors, a ceramic capacitor is reuqired for best performance. WPC TX-A6 Coil The internal half-bridge output connects to three seriesresonance circuits made by a WPC triple Type-A6 coil and series resonant capacitors. The selected inductor serves as the primary coil of a loosely-coupled transformer, the secondary of which is the inductor connected to the power receiver. PCB Layout Considerations - For optimum device performance and lowest output phase noise, the following guidelines must be observed. Please contact IDT for Gerber files that contain the recommended board layout. - The input capacitors (CIN) must be connected directly between the power pins (REG_IN and BUCK5VT_IN) and power PGND pins as near as possible to the IC pins. The output capacitor (COUT) must be placed as close to the device and power ground pins (PGND) as possible. As for all switching power supplies, especially those providing high current and using high switching frequencies, layout is an important design step. If layout is not carefully done, the regulator could show instability as well as EMI problems. Therefore, use wide and short traces for high current paths. If there are any uncertainties regarding best layout practices it is best to follow the provided, optimized IDT layout. - The 0.1F decoupling capacitors must be mounted on the component side of the board as close as possible to the pins intended to be decoupled. Keep PCB traces to each power pin and to ground vias as short as possible. The output-sense connection to the feedback pin, BUCK5VT_SNS, must be separated from any power trace. Connect the output-sense trace as close as possible to the load point to avoid additional load regulation errors. - To optimize board layout, place all components on the same side of the board. - All passive components in the network connecting to the HPF pin, up to and including the three small signal diodes must be placed close to the HPF pin. This is a high sensitivity analog circuit, and traces with high voltage or high noise must be routed away from this area. It is especially important to mount the capacitor connecting to the HPF pin as close as possible to the HPF pin. Additionally, the HPF pin is a high impedance input and any DC leakage into this node can reduce performance. Resonance Capacitors The resonance capacitors must be C0G type dielectric and have a DC rating of at least 100V. The part numbers are shown in the Bill Of Materials Buck Converter The power traces, including PGND traces, the LX or 5V output traces, and the VIN trace must be kept short, direct and wide to allow large current flow. Use several via pads when routing power lines between layers. LDOs Input Capacitor The input capacitors must be located as physically close as possible to the power pin (LDO2P5V_IN) and power ground (GND). Ceramic capacitors are recommended for their low ESR and small profile. Typically, 10V- or 16Vrated capacitors are recommended. Revision 1.0.0 21 (c) 2016 Integrated Device Technology, Inc P9036B Product Datasheet - The NQG48 6.0mm x 6.0mm x 0.75mm 48L package has an inner thermal pad, which requires blind assembly. It is recommended that a more active flux solder paste be used such as Alpha OM-350 solder paste from Cookson Electronics (http://www.cooksonsemi.com). Please contact IDT for Gerber files that contain recommended solder stencil design. - The package center exposed pad (EP) must be reliably soldered directly to the PCB. The center land pad on the PCB must also be tied to the board ground plane, primarily to maximize thermal performance in the application. The ground connection is best achieved using a matrix of plated-through-hole (PTH) vias embedded in the PCB center land pad for the NTG48. The PTH vias perform as thermal conduits to the ground plane (thermally, a heat spreader) from the solder side of the board. - On the solder side of the board, these thermal vias embed in a copper fill having the same dimensions as the center land pad on the component side. Recommendations for the via finished hole-size and array pitch are 0.3mm to 0.33mm and 1.3mm, respectively. Special Notes NQG TQFN-48 Package Assembly Note 1: Unopened Dry Packaged Parts have a one year shelf life. Note 2: The HIC indicator card for newly opened Dry Packaged Parts should be checked. If there is any moisture content, the parts must be baked for a minimum of 8 hours at 125C within 24 hours of the assembly reflow process. Power Dissipation/Thermal Requirements The P9036B is offered in a TQFN-48L package. The maximum power dissipation capability is 1.3W, limited by the die's specified maximum operating junction temperature, TJ, of 125C. The junction temperature rises with the device power dissipation based on the package thermal resistance. The package offers a typical thermal resistance, junction to ambient (JA), of 31C/W when the PCB layout and surrounding devices are optimized as described in the PCB Layout Considerations section. The techniques as noted in the PCB Layout section need to be followed when designing the printed circuit board layout. Care should be exercised to avoid the placement of the P9036B IC package in proximity to other heat generating devices in a given application design. The ambient temperature around the power IC will also have an effect on the thermal limits of an application. The overall goal is to have as much uninterrupted copper material on both the top and bottom layers of the PCB to carry away heat away for the P9036B as quickly as possible. Revision 1.0.0 22 (c) 2016 Integrated Device Technology, Inc. P9036B Product Datasheet PACKAGE OUTLINE DRAWING Figure 9 P9036B Package Outline Drawing (NTG48 TQFN-48L 6.0 mm x 6.0 mm x 0.75 mm48L, 0.4mm pitch) Revision 1.0.0 23 (c) 2016 Integrated Device Technology, Inc P9036B Product Datasheet ORDERING GUIDE Table 9 Ordering Summary PART NUMBER MARKING PACKAGE AMBIENT TEMP. RANGE SHIPPING CARRIER QUANTITY P9036BNTGI P9036BNTGI8 P9036BNTG P9036BNTG NTG48 - TQFN-48 6x6x0.75mm NTG48 - TQFN-48 6x6x0.75mm -40C to +85C -40C to +85C Tray Tape and Reel 25 2,500 www.IDT.com 6024 Silver Creek Valley Road San Jose, California 95138 Tel: 800-345-7015 DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT's sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. (c) Copyright 2016. All rights reserved.