a intel 2716 16K (2K x 8) UV ERASABLE PROM @ Fast Access Time a Pin Compatible to Intel Universal Site 2716-1: 350 ns Max EPROMs 2716-2: 390 ns Max : . : . u Simple Programming Requirements 2716: 450 ns Max Single Location Programming w Single + 5V Power Supply Programs with One 50 ms Pulse g Low Power Dissipation m Inputs and Outputs TTL Compatible Active Power: 525 mW Max During Read and Program Standby Power: 132 mW Max = Completely Static The Intel 2716 is a 16,384-bit ultraviolet erasable and electrically programmable read-only memory (EPROM). The 2716 operates from a single 5-volt power supply, has a static standby mode, and features fast single- address programming. It makes designing with EPROMs fast, easy and economical. The 2716, with its single 5-volt supply and with an access time up to 350 ns, is ideal for use with high- performance +5V microprocessors such as Intel's 8085 and 8086. Selected 2716-5s and 2716-6s are also available for slower speed applications. The 2716 also has a static standby mode which reduces power consumption without increasing access time. The maximum active power dissipation is 525 mW while the: maximum standby power dissipation is only 132 mW, a 75% savings. The 2716 uses a simple and fast method for programminga single TTL-level pulse. There is no need for high voltage pulsing because all programming controls are handled by TTL signals. Programming of any location at any timeeither individually, sequentially or at random is possible with the 2716s single-address program- ming. Total programming time for all 16,384 bits is only 100 seconds. DATA OUTPUTS Vee Oo 09-07 GND o+ ", veo Crem] [TTT Ge | Se TE Pin Names CE +L_CE LOGIC} 4 output BUFFERS L Ao~A10 Addresses v Pe" Y GATING cE Chip Enable e foe ty OE Output Enable ADDRESS { __,l = : INPUTS | x $ i604 - er Oo9-O07 Outputs e * - ay DECODER CELL MATRIX 210310-1 Figure 1. Block Diagram September 1989 5-1 Order Number: 210310-003a intel 2716 2716 2764A . VS 2764A 27512 | 27256 |27128A;27C64|2732A a C) 2732A |27C64)27128A| 27256 | 27512 27C512|27C256) 27C128187C64 Gg 5 87C64|27C 128|27C256| 27C512 Ais | Vpp | Vep | Vep 471 VV 241 Vec Vcc | Vee | Veo | Vec At2 Ai2 Ai2 | Ate Ag O42 23D Ag PGM | PGM | Aig Ais Az A; Az Ay | Az Ag OQ3 2212) Ag Veo | N.C. | Aig | Arg | A1s As Ag Ag Ag | As A,C]4 21 Ypp Ag Ag Ag Aa Ag As As As As | As a3;C15 20/0 dF Ag | Ag | Ag Ag Ag Ag Ag Ag | Ag | Ag aCe 19D Ato | Ai | An Av | A | Ant Ag A3 Ag Ag Ag Aid7 18D OE/Vpp}| OE OE OE |OE/Vpp| A2 Ae A2 Az | Ae AgCia 1710 97 Aro | Ato | Ato | Ato | Ato AY Ay At Ar | At Oc19 161) % CE | aFce| CE | CE | CE Ao Ao Ao Ao | Ao Oycd 10 150 Os O7 | O7 | O7 O7 07 Oo Oo Oo Op | Oo Oo 11 1400 % Og | Og | Os O6 O6 1 O1 Or | 1 | O GND C12 13,0) 93 Os | O5 | Os | Os | Os O2 O2 O2 O2 | O2 O, | Og | Og O4 O4 GND | GND | GND | GND | GND 210310-2 O3 | Og | O03 O3 03 NOTE: Intel Universal Site compatible EPROM configurations are shown in the blocks adjacent to the 2716 pins. Figure 2. Cerdip Pin Configuration EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range ( 40C to + 85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. 5-2 EXPRESS EPROM PRODUCT FAMILY PRODUCT DEFINITONS Type} Operating Temperature| Burn-in 125C (hr) Q 0C to + 70C 168 +8 I 40C to + 85C 44 EXPRESS OPTIONS 2716 Versions Versions -1 STDintel 2716 DEVICE OPERATION The six modes of operation of the 2716 are listed in Table 1. It should be noted that inputs for all modes are TTL levels. The power supplies required are a + 5V Voc and a Vpp. The Vpp power supply must be at 25V during the three programming modes, and must be at 5V in the other three modes. Read Mode The 2716 has two control functions, both of which must be logically satisfied in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output En- able (OE) is the output control and should be used to gate data from the output pins, independent of device selection. Assuming that addresses are sta- ble, address access time (tacc) is equal to the delay from CE to output (tce). Data is available at the out- puts tog after the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-toe. Standby Mode The 2716 has a standby mode which reduces the maximum active power dissipation by 75%, from 525 mW to 132 mW. The 2716 is placed in the standby mode by applying a TTL-high signal to the CE input. When in standby mode, the outputs are in a high impedance state, independent of the OE in- put. Output OR-Tieing Because 2716s are usually used in larger memory arrays, Intel has provided a 2-line control function that accommodates this use of multiple memory connections. The two-line control function allows for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. To use these two control lines most efficiently, CE (pin 18) should be decoded and used as the primary device selecting function, while OE (pin 20) should be made a common connection to all devices in the array and connected to the READ line from the sys- tem control bus. This assures that all deselected memory devices are in their low-power standby modes and that the output pins are active only when data is desired from a particular memory device. Programming Initially, and after each erasure, all bits of the 2716 are in the 1 state. Data is introduced by selectively programming 0s into the desired bit locations. Al- though only 0s will be programmed, both 1s and 0s can be presented in the data word. The only way to change a 0 to a 1 is by ultraviolet light erasure. The 2716 is in the programming mode when the Vpp power supply is at 25V and OE is at Vj. The data to be programmed is applied 8 bits in parallel to the data output pins. The tevels required for the address and data inputs are TTL. When the address and data are stable, a 50 ms, active-high, TTL program pulse is applied to the CE input. A pulse must be applied at each address loca- tion to be programmed. You can program any loca- tion at any timeeither individually, sequentially, or at random. The program pulse has a maximum width of 55 ms. The 2716 must not be programmed with a DC signal applied to the CE input. Table 1. Mode Selection Pins CE OE Vpp Voc Outputs Mode (18) (20) (21) (24) (9-11, 13-17) Read Vit Vit +5 +5 Dout Output Disable Viv Vin +5 +5 High Z Standby ViH x +5 +5 High Z Program Pulsed Vj_ to Vin Vin +25 +5 Din Verity Vit Vit +25 +5 Dout Program [nhibit VIL Vin +25 + High Z NOTE: 1. X can be Vi, or Vip. 5-3intel 2716 ABSOLUTE MAXIMUM RATINGS* Temperature Under Bias Storage Temperature All Input or Output Voltages with Respect to Ground.............. Vpp Supply Voltage with Respect to Ground During Program..... 10C to + 80C 65C to + 125C +6V to 0.3V + 26.5V to 0.3V NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. D.C. AND A.C. OPERATING CONDITIONS DURING READ 2716 2716-1 2716-2 Temperature Range oC-70C 0C-70C 0C-70C Voc Power Supply(1, 2) 5V +5% 5V +5% 5V +5% Vpp Power Supply(2) Voc Voc Voc READ OPERATION D.C. CHARACTERISTICS Symbol Parameter Limits Units Test Conditions Min Typ(3) Max luy Input Load Current 10 pA Vin = 5.25V ILo Output Leakage Current 10 pA Vout = 5.25V Ipp (2) Vpp Current 5 mA Vpp = 5.25V Ioc1) Voc Current (Standby) 10 25 mA CE = Vin, OF = Vit Iece(2) Voc Current (Active) 57 100 mA OE = CE = Vit Vit Input Low Voltage 0.1 0.8 Vv Vin Input High Voltage 2.0 Voc + 1 Vv VoL Output Low Voltage 0.45 Vv lol = 2.1mA Vou Output High Voltage 2.4 Vv lou = 400 pA A.C. CHARACTERISTICS , Limits (ns) Test Symbol Parameter 2716 2716-1 2716-2 Conditionst Min | Max | Min | Max | Min | Max tacc Address to Output Delay 450 350 390 | CE = OE = Vi tce CE to Output Delay 450 350 390 | COE = Vit toe(4) Output Enable to Output Delay 120 120 120 | CE=Vi_ tpor(4: 6) | CE or OE High to Output Float 100 100 100 | CE= Vit tou Output Hold from Addresses, CE CE = OE = Vit or OE Whichever Occurred First 5-4intel 2716 Programming of multiple 2716s in parallel with the same data can be easily accomplished due to the simplicity of the programming requirements. Like in- puts of the paralleled 2716s may be connected to- gether when they are programmed with the same data. A low level TTL pulse applied to the CE input programs the paralleled 2716s. Program Inhibit Programming of multiple 2716s in parallel with differ- ent data is also easily accomplished. Except for CE, all like inputs (including OE) of the parallel 2716s may be common. A TTL-level program pulse applied to a 2716's CE input with Vpp at 25V will program that 2716. A low-level CE input inhibits the other 2716 from being programmed. Verify A verify should be performed on the programmed bits to determine that they were correctly pro- grammed. The verify may be performed with Vpp at 25V. Except during programming and program veri- fy, Vpp must be at 5V. ERASURE CHARACTERISTICS The erasure characteristics of the 2716 are such that erasure begins to occur upon exposure to light with wavelengths shorter than aproximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000A range. Data show that constant exposure to room-level fluorescent lighting could erase the typical 2716 in approximately 3 years, while it would take approximately 1 week to cause erasure when exposed to direct sunlight. If the 2716 is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure for the 2716 is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of 15 Ws/cm2: The erasure time with this dosage is approximately 15 to 20 min- utes using an ultraviolet {amp with a 12000 pW/cm? power rating. The 2716 should be placed within 1 inch of the lamp tubes during erasure. START ADDRESS = FIRST LOCATION Vee = 5-0 Vpp = 25.0V PROGRAM ONE 50 ms PULSE INCREMENT LAST ADDRESS ADDRESS? Voc = Vpp = 5.0V COMPARE ALL BYTES TO ORIGINAL DATA YES FAIL | DEVICE FAILED PASS DEVICE PASSED 210310-3 Figure 3. Standard Programming Flowchart 5-5intel 2716 CAPACITANCE(4) T, = 25C, f = 1 MHz TtA.C. TEST CONDITIONS Test Output Load............0..2..000, 1 TTL gate and 3 Symbol] Parameter |Typ(3)| Max/ Unit Conditions C, = 100 pF Cin Input 4 6 | pF |Vin = OV input Rise and Fall Times ................. <20ns Capacitance Input Pulse Levels ................... 0.8V to 2.2V = Timing Measurement Reference Level: Cour outpat nce 8 | 12 | PF Mout = OV Inputs... 2... eee cece e eee ee ee es 0.8V and 2V apacttane Outputs... 0... eee ee ee eee 0.8V and 2V A.C. WAVEFORMS(1) " f ADDRESS a ADDRESSES VALID Vie N eee _____ Vin i Vit . eeee __/ tee + " os [ L a, Viv ) eecesoses (4.6) |. toe tor (5) OH =y Vin tace rs e eee eeee y HIGH Z TTT TTT HIGH Z OUTPUT VALID OUTPUT Vit AMAA. 4... ee 210310-4 NOTES: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. Vpp may be connected to Vcc except during programming. The supply current would then be the sum of icc and Ipp4. 3. Typical values are for Ta = 25C and nominal supply voltages. 4. This parameter is only sampled and is not 100% tested. 5. OE may be delayed up to t, 6. tor is specified from OE or -tog after the falling edge of CE without impact on tacc. , whichever occurs first.Intel 2716 PROGRAMMING CHARACTERISTICS D.C. PROGRAMMING CHARACTERISTICS Ta = 25C +5C, Voc!) = 5V +5%, Vpp(t.2) = 25V +1V Symbol Parameter Min Typ Max Units Conitons hey Input Current (for Any Input) 10 pA Vin = 5.25V/0.45 Ippy Vpp Supply Current 5 mA CE = Vit Ipp2 Vpp Supply Current during 30 mA CE = Vin Programming Pulse loc Voc Supply Current 100 mA Vin Input Low Level 0.1 0.8 Vv Vin Input High Level 2.0 Veco + 1 Vv A.C. PROGRAMMING CHARACTERISTICS Ta = 25C +8C, Vocll) = 5V +5%, Vppll. 2) = 25V +1V Symbol Parameter Min Typ Max Units Contnens* tas Address Setup Time 2 ps toes OE Setup Time 2 BS tos Data Setup Time 2 ps taH Address Hold Time 2 ps toEH OE Hold Time 2 as tpH Data Hold Time 2 ps tpFe Output Enable to Output Float Delay 0 200 ns CE = Vit toe Output Enable to Output Delay 200 ns CE = Vit tpw Program Pulse Width . 45 50 55 ms tprt Program Pulse Rise Time 5 ns tpeT Program Pulse Fall Time 5 ns *A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% to 90%)...... 20 ns Input Pulse Levels ................... 0.8V to 2.2V Input Timing Reference Level ......... 0.8V and 2V Output Timing Reference Level........ 0.8V and 2V NOTES: 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. The 2716 must not be inserted into or removed from a board with Vpp at 25 + 1V to prevent damage to the device. 2. The maximum allowable voltage which may be applied to the Vpp pin during programming is + 26V. Care must be taken when switching the Vpp supply to prevent overshoot exceeding this 26V maximum specification. 5-7intel 2716 PROGRAMMING WAVEFORMS PROGRAM VERIFY Vin ADDRESSES ADDRESS Vin tas tay (2) (2) Vin \ DATA IN DATA OUT DATA STABLE VALID Vit torP tprp (0.20 MAX) I (0.20 MAX) Vid OE Vin tox tos tpw (2) (2) (45 ms) Vin t, t, ar OES OEH CE | bh (2) k (2) Vit ____ tert -+ tprr 210310-5 NOTES: 1. All times shown in parenthesis are minimum times and are ps unless otherwise noted. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. REVISION HISTORY Number Description 03 Deleted -5 and -6 speed bins. Added Express options. Added Standard Programming Flowchart. Revised Pin Configuration and Block Diagram. 5-8