LTC2487
1
For more information www.linear.com/LTC2487
2487fg
TYPICAL APPLICATION
FEATURES DESCRIPTION
16-Bit 2-/4-Channel
DS
ADC
with PGA, Easy Drive and
I2C Interface
The LT C
®
2487 is a 4-channel (2 differential), 16-bit,
No Latency DS™ ADC with Easy Drive technology and a
2-wire, I2C interface. The patented sampling scheme elimi-
nates dynamic input current errors and the shortcomings
of on-chip buffering through automatic cancellation of
differential input current. This allows large external source
impedances and rail-to-rail input signals to be directly
digitized while maintaining exceptional DC accuracy.
The LTC2487 includes programmable gain, a high accuracy
temperature sensor and an integrated oscillator. This device
can be configured to measure an external signal (from com-
binations of 4 analog input channels operating in single-
ended or differential modes) or its internal temperature
sensor. The integrated temperature sensor offers 1/2°C
resolution and 2°C absolute accuracy. The LTC2487 can
be configured to provide a programmable gain from 1 to
256 in 8 steps.
The LTC2487 allows a wide common mode input range
(0V to VCC), independent of the reference voltage. Any
combination of single-ended or differential inputs can
be selected and the first conversion, after a new channel
is selected, is valid. Access to the multiplexer output en-
ables optional external amplifiers to be shared between all
analog inputs and auto calibration continuously removes
their associated offset and drift.
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
n Up to 2 Differential or 4 Single-Ended Inputs
n Easy Drive™ Technology Enables Rail-to-Rail
Inputs with Zero Differential Input Current
n Directly Digitizes High Impedance Sensors with
Full Accuracy
n 2-Wire I2C Interface with 9 Addresses Plus One
Global Address for Synchronization
n 600nV RMS Noise
n Programmable Gain from 1 to 256
n Integrated High Accuracy Temperature Sensor
n GND to VCC Input/Reference Common Mode Range
n Programmable 50Hz, 60Hz or Simultaneous
50Hz/60Hz Rejection Mode
n 2ppm INL, No Missing Codes
n 1ppm Offset and 15ppm Full-Scale Error
n 2x Speed/Reduced Power Mode (15Hz Using Internal
Oscillator and 80µA at 7.5Hz Output)
n No Latency: Digital Filter Settles in a Single Cycle,
Even After a New Channel is Selected
n Single Supply 2.7V to 5.5V Operation (0.8mW)
n Internal Oscillator
n Tiny 4mm × 3mm DFN Package
n Direct Sensor Digitizer
n Direct Temperature Measurement
n Instrumentation
n Industrial Process Control
Data Acquisition System with Temperature Compensation Built-In High Performance Temperature Sensor
SDA
SCL
fO
REF+
VCC
2.7V TO 5.5V
0.1µF
COM REF–
16-BIT ∆Σ ADC
WITH EASY-DRIVE
4-CHANNEL
MUX
IN+
IN–
2487 TA01a
2-WIRE
I2C INTERFACE
1.7k
CA1
CA0
9-PIN SELECTABLE
ADDRESSES
CH0
CH1
CH3
CH2
10µF
OSC
TEMPERATURE
SENSOR
TEMPERATURE (°C)
–55 –30 –5
ABSOLUTE ERROR (°C)
5
4
3
2
1
–4
–3
–2
–1
0
12095704520
2487 TA02
–5
LTC2487
2
For more information www.linear.com/LTC2487
2487fg
ORDER INFORMATION
Supply Voltage (VCC) ................................... –0.3V to 6V
Analog Input Voltage
(CH0 to CH3, COM) ................... –0.3V to (VCC + 0.3V)
REF+, REF– ....................................–0.3V to (VCC + 0.3V)
Digital Input Voltage......................–0.3V to (VCC + 0.3V)
Digital Output Voltage ...................–0.3V to (VCC + 0.3V)
Operating Temperature Range
LTC2487C ................................................ 0°C to 70°C
LTC2487I .............................................–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
(Notes 1, 2)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
REF–
REF+
VCC
CH3
CH2
CH1
CH0
fO
CA0
CA1
SCL
SDA
GND
COM
DE PACKAGE
14-LEAD (4mm × 3mm) PLASTIC DFN
15
TJMAX = 125°C, qJA = 37°C/W
EXPOSED PAD (PIN 15) IS GND, MUST BE SOLDERED TO PCB
LEAD FREE FINISH TAPE AND REEL PART MARKING PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2487CDE#PBF LTC2487CDE#TRPBF 2487 14-Lead (4mm × 3mm) Plastic DFN 0°C to 70°C
LTC2487IDE#PBF LTC2487IDE#TRPBF 2487 14-Lead (4mm × 3mm) Plastic DFN –40°C to 85°C
Consult ADI Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
http://www.linear.com/product/LTC2487#orderinfo
LTC2487
3
For more information www.linear.com/LTC2487
2487fg
ELECTRICAL CHARACTERISTICS (NORMAL SPEED)
The l denotes the specifications which
apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
l
2
1
20 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.5 5 µV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 10 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C
Total Unadjusted Error 5V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V
15
15
15
ppm of VREF
ppm of VREF
ppm of VREF
Output Noise 2.7V < VCC < 5.5V, 2.5V ≤ VREF ≤ VCC,
GND ≤ IN+ = IN– ≤ VCC (Note 12)
0.6 µVRMS
Internal PTAT Signal TA = 27°C (Note 13) 27.8 28.0 28.2 mV
Internal PTAT Temperature Coefficient 93.5 µV/°C
Programmable Gain l1 256
ELECTRICAL CHARACTERISTICS (2X SPEED)
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Notes 3, 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Resolution (No Missing Codes) 0.1V ≤ VREF ≤ VCC, –FS ≤ VIN ≤ +FS (Note 5) 16 Bits
Integral Nonlinearity 5V ≤ VCC ≤ 5.5V, VREF = 5V, VIN(CM) = 2.5V (Note 6)
2.7V ≤ VCC ≤ 5.5V, VREF = 2.5V, VIN(CM) = 1.25V (Note 6)
l
2
1
20 ppm of VREF
ppm of VREF
Offset Error 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 13) l0.2 2 mV
Offset Error Drift 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC 100 nV/°C
Positive Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF l32 ppm of VREF
Positive Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.75VREF, IN– = 0.25VREF 0.1 ppm of VREF/°C
Negative Full-Scale Error 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF l32 ppm of VREF
Negative Full-Scale Error Drift 2.5V ≤ VREF ≤ VCC, IN+ = 0.25VREF, IN– = 0.75VREF 0.1 ppm of VREF/°C
Output Noise 5V ≤ VCC ≤ 5.5V, VREF = 5V, GND ≤ IN+ = IN– ≤ VCC 0.85 µVRMS
Programmable Gain l1 128
CONVERTER CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Input Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l140 dB
Input Common Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l140 dB
Input Common Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l140 dB
Input Normal Mode Rejection 50Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 7) l110 120 dB
Input Normal Mode Rejection 60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 8) l110 120 dB
Input Normal Mode Rejection 50Hz/60Hz ±2% 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Notes 5, 9) l87 dB
Reference Common Mode Rejection DC 2.5V ≤ VREF ≤ VCC, GND ≤ IN+ = IN– ≤ VCC (Note 5) l120 140 dB
Power Supply Rejection DC VREF = 2.5V, IN+ = IN– = GND 120 dB
Power Supply Rejection, 50Hz ±2%, 60Hz ±2% VREF = 2.5V, IN+ = IN– = GND (Notes 7, 8, 9) 120 dB
LTC2487
4
For more information www.linear.com/LTC2487
2487fg
I2C INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the full
operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
ANALOG INPUT AND REFERENCE
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IN+Absolute/Common Mode IN+ Voltage (IN+ Corresponds
to the Selected Positive Input Channel)
GND – 0.3V VCC + 0.3V V
IN–Absolute/Common Mode IN– Voltage (IN– Corresponds
to the Selected Negative Input Channel or COM)
GND – 0.3V VCC + 0.3V V
VIN Input Voltage Range (IN+ – IN–) Differential/Single-Ended l–FS +FS V
FS Full Scale of the Input (IN+ – IN–) Differential/Single-Ended l0.5VREF/Gain V
LSB Least Significant Bit of the Output Code lFS/216
REF+Absolute/Common Mode REF+ Voltage l0.1 VCC V
REF–Absolute/Common Mode REF– Voltage lGND REF+ – 0.1V V
VREF Reference Voltage Range (REF+ – REF–)l0.1 VCC V
CS(IN+) IN+ Sampling Capacitance 11 pF
CS(IN–) IN– Sampling Capacitance 11 pF
CS(VREF) VREF Sampling Capacitance 11 pF
IDC_LEAK(IN+)IN+ DC Leakage Current Sleep Mode, IN+ = GND l–10 1 10 nA
IDC_LEAK(IN–)IN– DC Leakage Current Sleep Mode, IN– = GND l–10 1 10 nA
IDC_LEAK(REF+)REF+ DC Leakage Current Sleep Mode, REF+ = VCC l–100 1 100 nA
IDC_LEAK(REF–)REF– DC Leakage Current Sleep Mode, REF– = GND l–100 1 100 nA
tOPEN MUX Break-Before-Make 50 ns
QIRR MUX Off Isolation VIN = 2VP-P DC to 1.8MHz 120 dB
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIH High Level Input Voltage l0.7VCC V
VIL Low Level Input Voltage l0.3VCC V
VIHA Low Level Input Voltage for Address Pins CA0, CA1 and Pin fO l 0.05VCC V
VILA High Level Input Voltage for Address Pins CA0, CA1 l0.95VCC V
RINH Resistance from CA0, CA1 to VCC to Set Chip Address
Bit to 1
l 10 kW
RINL Resistance from CA0, CA1 to GND to Set Chip Address
Bit to 0
l10 kW
RINF Resistance from CA0, CA1 to GND or VCC to Set Chip
Address Bit to Float
l2 MW
IIDigital Input Current l–10 10 µA
VHYS Hysteresis of Schmitt Trigger Inputs (Note 5) l0.05VCC V
VOL Low Level Output Voltage (SDA) I = 3mA l 0.4 V
tOF Output Fall Time VIH(MIN) to VIL(MAX) Bus Load CB 10pF to
400pF (Note 14)
l20 + 0.1CB250 ns
IIN Input Leakage 0.1VCC ≤ VIN ≤ VCC l1 µA
CCAX External Capacitative Load on Chip Address Pins (CA0, CA1)
for Valid Float
l10 pF
LTC2487
5
For more information www.linear.com/LTC2487
2487fg
POWER REQUIREMENTS
The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Supply Voltage l2.7 5.5 V
ICC Supply Current Conversion Current (Note 11)
Temperature Measurement (Note 11)
Sleep Mode (Note 11)
l
l
l
160
200
1
275
300
2
µA
µA
µA
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fEOSC External Oscillator Frequency Range (Note 16) l10 1000 kHz
tHEO External Oscillator High Period l0.125 50 µs
tLEO External Oscillator Low Period l0.125 50 µs
tCONV_1 Conversion Time for 1x Speed Mode 50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
l
l
l
157.2
131
144.1
160.3
133.6
146.9
41036/fEOSC (in kHz)
163.5
136.3
149.9
ms
ms
ms
ms
tCONV_2 Conversion Time for 2x Speed Mode 50Hz Mode
60Hz Mode
Simultaneous 50Hz/60Hz Mode
External Oscillator (Note 10)
l
l
l
78.7
65.6
72.2
80.3
66.9
73.6
20556/fEOSC (in kHz)
81.9
68.2
75.1
ms
ms
ms
ms
DIGITAL INPUTS AND DIGITAL OUTPUTS
The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSCL SCL Clock Frequency l0 400 kHz
tHD(STA)Hold Time (Repeated) Start Condition l0.6 µs
tLOW Low Period of the SCL Pin l1.3 µs
tHIGH High Period of the SCL Pin l0.6 µs
tSU(STA)Set-Up Time for a Repeated Start Condition l0.6 µs
tHD(DAT)Data Hold Time l0 0.9 µs
tSU(DAT)Data Set-Up Time l100 ns
trRise Time for SDA Signals (Note 14) l20 + 0.1CB300 ns
tfFall Time for SDA Signals (Note 14) l20 + 0.1CB300 ns
tSU(STO) Set-Up Time for Stop Condition l0.6 µs
I2C TIMING CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 3, 15)
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND.
Note 3: Unless otherwise specified: VCC = 2.7V to 5.5V
VREFCM = VREF/2, FS = 0.5VREF/Gain
VIN = IN+ – IN–, VIN(CM) = (IN+ – IN–)/2,
where IN+ and IN– are the selected input channels.
Note 4: Use internal conversion clock or external conversion clock source
with fEOSC = 307.2kHz unless otherwise specified.
Note 5: Guaranteed by design, not subject to test.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 7: 50Hz mode (internal oscillator) or fEOSC = 256kHz ±2% (external oscillator).
Note 8: 60Hz mode (internal oscillator) or fEOSC = 307.2kHz ±2% (external oscillator).
Note 9: Simultaneous 50Hz/60Hz mode (internal oscillator) or fEOSC =
280kHz ±2% (external oscillator).
Note 10: The external oscillator is connected to the fO pin. The external
oscillator frequency, fEOSC, is expressed in kHz.
Note 11: The converter uses its internal oscillator.
Note 12: The output noise includes the contribution of the internal
calibration operations.
Note 13: Guaranteed by design and test correlation.
Note 14: CB = capacitance of one bus line in pF (10pF ≤ CB ≤ 400pF).
Note 15: All values refer to VIH(MIN) and VIL(MAX) levels.
Note 16: Refer to Applications Information section for Performance vs
Data Rate graphs.
LTC2487
6
For more information www.linear.com/LTC2487
2487fg
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT VOLTAGE (V)
–3
INL (ppm of V
REF
)
–1
1
3
–2
0
2
–1.5 –0.5 0.5 1.5
2487 G01
2.5
–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
85°C
–45°C 25°C
INPUT VOLTAGE (V)
–3
INL (ppm of V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2487 G02
1.25
–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–3
INL (ppm of V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2487 G03
1.25
–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
–45°C, 25°C, 85°C
INPUT VOLTAGE (V)
–12
TUE (ppm of V
REF
)
–4
4
12
–8
0
8
–1.5 –0.5 0.5 1.5
2487 G04
2.5
–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND 85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm of V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2487 G05
1.25
–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
25°C
–45°C
INPUT VOLTAGE (V)
–12
TUE (ppm of V
REF
)
–4
4
12
–8
0
8
–0.75 –0.25 0.25 0.75
2487 G06
1.25
–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND 85°C
25°C
–45°C
OUTPUT READING (µV)
–3
NUMBER OF READINGS (%)
8
10
12
0.6
2487 G07
6
4
–1.8 –0.6
–2.4 1.2
–1.2 0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
GAIN = 256
RMS = 0.60µV
AVERAGE = –0.69µV
OUTPUT READING (µV)
–3
NUMBER OF READINGS (%)
8
10
12
0.6
2487 G08
6
4
–1.8 –0.6
–2.4 1.2
–1.2 0
1.8
2
0
14
10,000 CONSECUTIVE
READINGS
VCC = 2.7V
VREF = 2.5V
VIN = 0V
TA = 25°C
GAIN = 256
RMS = 0.59µV
AVERAGE = –0.19µV
TIME (HOURS)
0
–5
ADC READING (µV)
–3
–1
1
10 20 30 40
2487 G09
50
3
5
–4
–2
0
2
4
60
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = 2.5V
TA = 25°C
RMS NOISE = 0.60µV
GAIN = 256
Integral Nonlinearity
(VCC = 5V, VREF = 5V)
Integral Nonlinearity
(VCC = 5V, VREF = 2.5V)
Integral Nonlinearity
(VCC = 2.7V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 5V, VREF = 5V)
Total Unadjusted Error
(VCC = 5V, VREF = 2.5V)
Total Unadjusted Error
(VCC = 2.7V, VREF = 2.5V)
Noise Histogram (6.8sps)
Noise Histogram (7.5sps)
Long-Term ADC Readings
LTC2487
7
For more information www.linear.com/LTC2487
2487fg
TYPICAL PERFORMANCE CHARACTERISTICS
INPUT DIFFERENTIAL VOLTAGE (V)
0.4
RMS NOISE (µV)
0.6
0.8
1.0
0.5
0.7
0.9
–1.5 –0.5 0.5 1.5
2487 G10
2.5
–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
fO = GND
VIN(CM) (V)
–1
RMS NOISE (µV)
0.8
0.9
1.0
2 4
2487 G11
0.7
0.6
0 1 3 5
6
0.5
0.4
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
fO = GND
GAIN = 256
TEMPERATURE (°C)
–45
0.4
RMS NOISE (µV)
0.5
0.6
0.7
0.8
1.0
–30 –15 15
0 30 45 60
2487 G12
75
90
0.9
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
GAIN = 256
VCC (V)
2.7
RMS NOISE (µV)
0.8
0.9
1.0
3.9 4.7
2487 G13
0.7
0.6
3.1 3.5 4.3 5.1
5.5
0.5
0.4
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
GAIN = 256
VREF (V)
0
0.4
RMS NOISE (µV)
0.5
0.6
0.7
0.8
0.9
1.0
1 2 3 4
2487 G14
5
VCC = 5V
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
GAIN = 256
VIN(CM) (V)
–1
OFFSET ERROR (ppm of V
REF
)
0.1
0.2
0.3
2 4
2487 G15
0
–0.1
0 1 3 5
6
–0.2
–0.3
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
fO = GND
TEMPERATURE (°C)
–45
–0.3
OFFSET ERROR (ppm of V
REF
)
–0.2
0
0.1
0.2
–15 15 30
90
2487 G16
–0.1
–30 0 45 60 75
0.3
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC (V)
2.7
OFFSET ERROR (ppm of V
REF
)
0.1
0.2
0.3
3.9 4.7
2487 G17
0
–0.1
3.1 3.5 4.3 5.1
5.5
–0.2
–0.3
REF+ = 2.5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
VREF (V)
0
–0.3
OFFSET ERROR (ppm of V
REF
)
–0.2
–0.1
0
0.1
0.2
0.3
1 2 3 4
2487 G18
5
VCC = 5V
REF– = GND
VIN = 0V
VIN(CM) = GND
TA = 25°C
fO = GND
RMS Noise
vs Input Differential Voltage
RMS Noise vs VIN(CM)
RMS Noise vs Temperature (TA)
RMS Noise vs VCC
RMS Noise vs VREF
Offset Error vs VIN(CM)
Offset Error vs Temperature
Offset Error vs VCC
Offset Error vs VREF
LTC2487
8
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2487fg
TEMPERATURE (°C)
–45 –30
300
FREQUENCY (kHz)
304
310
–15 30 45
2487 G19
302
308
306
150 60 75
90
VCC = 4.1V
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC (V)
2.5
300
FREQUENCY (kHz)
302
304
306
308
310
3.0 3.5 4.0 4.5
2487 G20
5.0
5.5
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2487 G21
10 100 10k
1M
REJECTION (dB)
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
0
–140
REJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2487 G22
–100
–20
80 180
220
200
40 60 120 160
VCC = 4.1V DC ±1.4V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
30600
–60
–40
0
30750
2487 G23
–80
–100
30650 30700
30800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
VREF = 2.5V
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
TEMPERATURE (°C)
–45
100
CONVERSION CURRENT (µA)
120
160
180
200
–15 15 30
90
2487 G24
140
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
fO = GND
On-Chip Oscillator Frequency
vs Temperature
On-Chip Oscillator Frequency
vs VCC
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
PSRR vs Frequency at VCC
Conversion Current
vs Temperature
Sleep Mode Current
vs Temperature
Conversion Current
vs Output Data Rate
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 5V)
TEMPERATURE (°C)
–45
0
SLEEP MODE CURRENT (µA)
0.2
0.6
0.8
1.0
2.0
1.4
–15 15 30
90
2487 G25
0.4
1.6
1.8
1.2
–30 0 45 60 75
VCC = 5V
VCC = 2.7V
fO = GND
OUTPUT DATA RATE (READINGS/SEC)
0
SUPPLY CURRENT (µA)
500
450
400
350
300
250
200
150
100
2487 G26
20
30
10
VREF = VCC
IN+ = GND
IN– = GND
fO = EXT OSC
TA = 25°C
VCC = 5V
VCC = 3V
INPUT VOLTAGE (V)
–3
INL (µV)
–1
1
3
–2
0
2
–1.5 –0.5 0.5 1.5
2487 G27
2.5
–2–2.5 –1 0 1 2
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
fO = GND
25°C, 85°C
–45°C
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2487
9
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2487fg
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2487 G28
1.25
–1.25
VCC = 5V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
–45°C, 25°C
INPUT VOLTAGE (V)
–3
INL (ppm OF V
REF
)
–1
1
3
–2
0
2
–0.75 –0.25 0.25 0.75
2487 G29
1.25
–1.25
VCC = 2.7V
VREF = 2.5V
VIN(CM) = 1.25V
fO = GND
85°C
–45°C, 25°C
OUTPUT READING (µV)
179
NUMBER OF READINGS (%)
8
10
12
186.2
2487 G30
6
4
181.4 183.8
188.6
2
0
16
14
10,000 CONSECUTIVE
READINGS
VCC = 5V
VREF = 5V
VIN = 0V
TA = 25°C
GAIN = 128
RMS = 0.85µV
AVERAGE = 0.184µV
VREF (V)
0
RMS NOISE (µV)
0.6
0.8
1.0
4
2487 G31
0.4
0.2
0123
5
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
GAIN = 128
VIN(CM) (V)
–1
180
OFFSET ERROR (µV)
182
186
188
190
200
194
134
2487 G32
184
196
198
192
025
6
VCC = 5V
VREF = 5V
VIN = 0V
fO = GND
TA = 25°C
TEMPERATURE (°C)
–45
OFFSET ERROR (µV)
200
210
220
75
2487 G33
190
180
160 –15 15 45
–30
90
030 60
170
240
230
VCC = 5V
VREF = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
VCC (V)
2 2.5
0
OFFSET ERROR (µV)
100
250
344.5
2487 G34
50
200
150
3.5 5
5.5
VREF = 2.5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
VREF (V)
0
OFFSET ERROR (µV)
190
200
210
3
5
2487 G35
180
170
160 1 2 4
220
230
240
VCC = 5V
VIN = 0V
VIN(CM) = GND
fO = GND
TA = 25°C
Integral Nonlinearity (2x Speed
Mode; VCC = 5V, VREF = 2.5V)
Integral Nonlinearity (2x Speed
Mode; VCC = 2.7V, VREF = 2.5V)
Noise Histogram
(2x Speed Mode)
RMS Noise vs VREF
(2x Speed Mode)
Offset Error vs VIN(CM)
(2x Speed Mode)
Offset Error vs Temperature
(2x Speed Mode)
Offset Error vs VCC
(2x Speed Mode)
Offset Error vs VREF
(2x Speed Mode)
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2487
10
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FREQUENCY AT VCC (Hz)
1
0
–20
–40
–60
–80
–100
–120
–140 1k 100k
2487 G36
10 100 10k
1M
REJECTION (dB)
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
0
–140
RREJECTION (dB)
–120
–80
–60
–40
0
20 100 140
2487 G37
–100
–20
80 180
220
200
40 60 120 160
VCC = 4.1V DC ±1.4V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
FREQUENCY AT VCC (Hz)
30600
–60
–40
0
30750
2487 G38
–80
–100
30650 30700
30800
–120
–140
–20
REJECTION (dB)
VCC = 4.1V DC ±0.7V
REF+ = 2.5V
REF– = GND
IN+ = GND
IN– = GND
fO = GND
TA = 25°C
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
PSRR vs Frequency at VCC
(2x Speed Mode)
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2487
11
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2487fg
PIN FUNCTIONS
fO (Pin 1): Frequency Control Pin. Digital input that controls
the internal conversion clock rate. When fO is connected
to GND, the converter uses its internal oscillator running
at 307.2kHz. The conversion clock may also be overrid-
den by driving the fO pin with an external clock in order to
change the output rate and the digital filter rejection null.
CA0, CA1 (Pins 2, 3): Chip Address Control Pins. These
pins are configured as a three-state (LOW, HIGH, Floating)
address control bits for the device’s I2C address.
SCL (Pin 4): Serial Clock Pin of the I2C Interface. The
LTC2487 can only act as a slave and the SCL pin only
accepts an external serial clock. Data is shifted into the
SDA pin on the rising edges of the SCL clock and output
through the SDA pin on the falling edges of the SCL clock.
SDA (Pin 5): Bidirectional Serial Data Line of the I2C Inter-
face. In the transmitter mode (Read), the conversion result
is output through the SDA pin, while in the receiver mode
(Write), the device channel select and configuration bits
are input through the SDA pin. The pin is high impedance
during the data input mode and is an open drain output
(requires an appropriate pull-up device to VCC) during the
data output mode.
GND (Pin 6): Ground. Connect this pin to a common ground
plane through a low impedance connection.
COM (Pin 7): The Common Negative Input (IN–) for All
Single-Ended Multiplexer Configurations. The voltage
on CH0-CH3 and COM pins can have any value between
GND – 0.3V to VCC + 0.3V. Within these limits, the two
selected inputs (IN+ and IN– ) provide a bipolar input range
VIN = (IN+ – IN–) from –0.5 • VREF/Gain to 0.5 • VREF/Gain.
Outside this input range, the converter produces unique
over-range and under-range output codes.
CH0 to CH3 (Pin 8-Pin 11): Analog Inputs. May be pro-
grammed for single-ended or differential mode.
VCC (Pin 12): Positive Supply Voltage. Bypass to GND with
a 10µF tantalum capacitor in parallel with a 0.1µF ceramic
capacitor as close to the part as possible.
REF+, REF– (Pin 13, Pin 14): Differential Reference Input.
The voltage on these pins can have any value between
GND and VCC as long as the reference positive input, REF+,
remains more positive than the negative reference input,
REF–, by at least 0.1V. The differential voltage (VREF =
REF+ – REF–) sets the full-scale range (–0.5 • VREF/Gain
to 0.5 • VREF/Gain) for all input channels.
When perform-
ing an on-chip temperature measurement, the minimum
value of REF = 2V.
Exposed Pad (Pin 15): Ground. This pin is ground and
must be soldered to the PCB ground plane. For prototyping
purposes, this pin may remain floating.
LTC2487
13
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2487fg
CONVERTER OPERATION
Converter Operation Cycle
The LTC2487 is a multichannel, low power, delta-sigma,
analog-to-digital converter with a 2-wire, I2C interface. Its
operation is made up of four states (see Figure 1). The
converter operating cycle begins with the conversion,
followed by the sleep state, and ends with the data input/
output cycle.
Initially, at power-up, the LTC2487 performs a conversion.
Once the conversion is complete, the device enters the
sleep state. While in the sleep state, power consumption
is reduced by two orders of magnitude. The part remains
in the sleep state as long it is not addressed for a read/
write operation. The conversion result is held indefinitely
in a static shift register while the part is in the sleep state.
The device will not acknowledge an external request dur-
ing the conversion state. After a conversion is finished,
the device is ready to accept a read/write request. Once
the LTC2487 is addressed for a read operation, the device
begins outputting the conversion result under the control
of the serial clock (SCL). There is no latency in the conver-
sion result. The data output is 24 bits long and contains a
16-bit plus sign conversion result. Data is updated on the
falling edges of SCL allowing the user to reliably latch data
on the rising edge of SCL. A new conversion is initiated
by a stop condition following a valid write operation or an
incomplete read operation. The conversion automatically
begins at the conclusion of a complete read cycle (all 24
bits read out of the device).
Ease of Use
The LTC2487 data output has no latency, filter settling
delay, or redundant data associated with the conversion
cycle. There is a one-to-one correspondence between the
conversion and the output data. Therefore, multiplexing
multiple analog inputs is straightforward. Each conversion,
immediately following a newly selected input or mode, is
valid and accurate to the full specifications of the device.
APPLICATIONS INFORMATION
The LTC2487 automatically performs offset and full-scale
calibration every conversion cycle independent of the input
channel selected. This calibration is transparent to the user
and has no effect on the operation cycle described above.
The advantage of continuous calibration is extreme stability
of offset and full-scale readings with respect to time, sup-
ply voltage variation, input channel, and temperature drift.
Easy Drive Input Current Cancellation
The LTC2487 combines a high precision, delta-sigma ADC
with an automatic, differential, input current cancellation
front end. A proprietary front end passive sampling network
transparently removes the differential input current. This
enables external RC networks and high impedance sen-
sors to directly interface to the LTC2487 without external
Figure 1. State Transition Table
CONVERSION
SLEEP
2487 F01
YES
NO ACKNOWLEDGE
YES
NO STOP
OR READ
24 BITS
DATA OUTPUT/INPUT
POWER-ON RESET
DEFAULT CONFIGURATION:
IN+ = CH0, IN– = CH1
50Hz/60Hz REJECTION
1X OUTPUT, GAIN = 1
LTC2487
14
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2487fg
APPLICATIONS INFORMATION
amplifiers. The remaining common mode input current
is eliminated by either balancing the differential input im-
pedances or setting the common mode input equal to the
common mode reference (see the Automatic Differential
Input Current Cancellation section). This unique architec-
ture does not require on-chip buffers, thereby enabling
signals to swing beyond ground and VCC. Moreover, the
cancellation does not interfere with the transparent offset
and full-scale auto-calibration and the absolute accuracy
(full scale + offset + linearity + drift) is maintained even
with external RC networks.
Power-Up Sequence
The LTC2487 automatically enters an internal reset state
when the power supply voltage, VCC, drops below a
threshold of approximately 2.0V. This feature guarantees
the integrity of the conversion result and input channel
selection.
When VCC rises above this threshold, the converter creates
an internal power-on-reset (POR) signal with a duration
of approximately 4ms. The POR signal clears all internal
registers. The conversion immediately following a POR
cycle is performed on the input channels IN+ = CH0 and
IN– = CH1 with simultaneous 50Hz/60Hz rejection, 1x
output rate, and gain = 1. The first conversion following a
POR cycle is accurate within the specification of the device
if the power supply voltage is restored to (2.7V to 5.5V)
before the end of the POR interval. A new input channel,
rejection mode, speed mode, temperature selection or
gain can be programmed into the device during this first
data input/output cycle.
Reference Voltage Range
This converter accepts a truly differential external refer-
ence voltage. The absolute/common mode voltage range
for the REF+ and REF– pins covers the entire operating
range of the device (GND to VCC). For correct converter
operation, VREF must be positive (REF+ > REF–).
The LTC2487 differential reference input range is 0.1V to
VCC. For the simplest operation, REF+ can be shorted to
VCC and REF– can be shorted to GND. The converter out-
put noise is determined by the thermal noise of the front
end circuits and, as such, its value in nanovolts is nearly
constant with reference voltage. A decrease in reference
voltage will not significantly improve the converter’s effec-
tive resolution. On the other hand, a decreased reference
will improve the converter’s overall INL performance.
Input Voltage Range
The LTC2487 input measurement range is –0.5 • VREF to
0.5 • VREF in both differential and single-ended configura-
tions as shown in Figure 37. Highest linearity is achieved
with Fully Differential drive and a constant common
mode voltage (Figure 37b). Other drive schemes may
incur an INL error of approximately 50ppm. This error
can be calibrated out using a three point calibration and
a second-order curve fit.
The analog inputs are truly differential with an absolute,
common mode range for the CH0-CH3 and COM input pins
extending from GND – 0.3V to VCC + 0.3V. Outside these
limits, the ESD protection devices begin to turn on and the
errors due to input leakage current increase rapidly. Within
these limits, the LTC2487 converts the bipolar differential
input signal VIN = IN+ – IN– (where IN+ and IN– are the
selected input channels), from –FS = –0.5 • VREF/Gain
to +FS = 0.5 • VREF/Gain where VREF = REF+ – REF–.
Outside this range, the converter indicates the overrange
or the underrange condition using distinct output codes
(see Table 1).
In order to limit any fault current, resistors of up to 5k
may be added in series with the input. The effect of series
resistance on the converter accuracy can be evaluated from
the curves presented in the Input Current/Reference Cur-
rent sections. In addition, series resistors will introduce a
temperature dependent error due to input leakage current.
A 1nA input leakage current will develop a 1ppm offset
error on a 5k resistor if VREF = 5V. This error has a very
strong temperature dependency.
LTC2487
15
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2487fg
APPLICATIONS INFORMATION
I2C INTERFACE
The LTC2487 communicates through an I2C interface. The
I2C interface is a 2-wire, open-drain interface supporting
multiple devices and multiple masters on a single bus. The
connected devices can only pull the data line (SDA) low
and can never drive it high. SDA is required to be exter-
nally connected to the supply through a pull-up resistor.
When the data line is not being driven, it is high. Data on
the I2C bus can be transferred at rates up to 100kbits/s in
the standard mode and up to 400kbits/s in the fast mode.
The VCC power should not be removed from the device
when the I2C bus is active to avoid loading the I2C bus
lines through the internal ESD protection diodes.
Each device on the I2C bus is recognized by a unique
address stored in that device and can operate either as a
transmitter or receiver, depending on the function of the
device. In addition to transmitters and receivers, devices
can also be considered as masters or slaves when perform-
ing data transfers. A master is the device which initiates a
data transfer on the bus and generates the clock signals
to permit that transfer. Devices addressed by the master
are considered a slave.
The LTC2487 can only be addressed as a slave. Once ad-
dressed, it can receive configuration bits (channel selec-
tion, rejection mode, speed mode, gain) or transmit the
last conversion result. The serial clock line, SCL, is always
an input to the LTC2487 and the serial data line SDA is
bidirectional. The device supports the standard mode and
the fast mode for data transfer speeds up to 400kbits/s.
Figure 2 shows the definition of the I2C timing.
The Start and Stop Conditions
A Start (S) condition is generated by transitioning SDA from
high to low while SCL is high. The bus is considered to be
busy after the Start condition. When the data transfer is
finished, a Stop (P) condition is generated by transitioning
SDA from low to high while SCL is high. The bus is free
after a Stop is generated. Start and Stop conditions are
always generated by the master.
When the bus is in use, it stays busy if a Repeated Start
(Sr) is generated instead of a Stop condition. The repeated
Start timing is functionally identical to the Start and is
used for writing and reading from the device before the
initiation of a new conversion.
Data Transferring
After the Start condition, the I2C bus is busy and data
transfer can begin between the master and the addressed
slave. Data is transferred over the bus in groups of nine
bits, one byte followed by one acknowledge (ACK) bit. The
master releases the SDA line during the ninth SCL clock
cycle. The slave device can issue an ACK by pulling SDA
low or issue a Not Acknowledge (NAK) by leaving the SDA
line high impedance (the external pull-up resistor will hold
the line high). Change of data only occurs while the clock
line (SCL) is low.
DATA FORMAT
After a Start condition, the master sends a 7-bit address
followed by a read/write (R/W) bit. The R/W bit is 1 for
a read request and 0 for a write request. If the 7-bit ad-
Figure 2. Definition of Timing for Fast/Standard Mode Devices on the I2C Bus
SDA
SCL
S Sr P S
tHD(SDA) t
HD(DAT)
tSU(STA) tSU(STO)
tSU(DAT)
tLOW tHD(SDA) tSP tBUF
trtftr
tf
t
HIGH 2487 F02
LTC2487
16
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2487fg
APPLICATIONS INFORMATION
dress matches the hard wired LTC2487’s address (one of
9 pin-selectable addresses) the device is selected. When
the device is addressed during the conversion state, it will
not acknowledge R/W requests and will issue a NAK by
leaving the SDA line high. If the conversion is complete,
the LTC2487 issues an ACK by pulling the SDA line low.
The LTC2487 has two registers. The output register (24
bits long) contains the last conversion result. The input
register (16 bits long) sets the input channel, selects the
temperature sensor, rejection mode, gain and speed mode.
DATA OUTPUT FORMAT
The output register contains the last conversion result.
After each conversion is completed, the device automati-
cally enters the sleep state where the supply current is
reduced to 1µA. When the LTC2487 is addressed for a read
operation, it acknowledges (by pulling SDA low) and acts
as a transmitter. The master/receiver can read up to three
bytes from the LTC2487. After a complete read operation
(3 bytes), a new conversion is initiated. The device will
NAK subsequent read operations while a conversion is
being performed.
The data output stream is 24 bits long and is shifted out
on the falling edges of SCL (see Figure 3a). The first bit is
the conversion result sign bit (SIG) (see Tables 1 and 2).
This bit is high if VIN ≥ 0 and low if VIN < 0 (where VIN
corresponds to the selected input signal IN+ – IN–). The
second bit is the most significant bit (MSB) of the result.
The first two bits (SIG and MSB) can be used to indicate
over and under range conditions (see Table 2). If both bits
are HIGH, the differential input voltage is equal to or above
+FS. If both bits are set low, the input voltage is below –FS.
The function of these bits is summarized in Table 2. The
16 bits following the MSB bit are the conversion result
in binary, two’s complement format. The remaining six
bits are always 0.
As long as the voltage on the selected input channels (IN+
and IN–) remains between –0.3V and VCC + 0.3V (absolute
maximum operating range) a conversion result is gener-
ated for any differential input voltage VIN from –FS = –0.5
• VREF/Gain to +FS = 0.5 • VREF/Gain. For differential input
voltages greater than +FS, the conversion result is clamped
to the value corresponding to +FS. For differential input
voltages below –FS, the conversion result is clamped to
the value –FS – 1LSB.
Table 2. LTC2487 Status Bits
Input Range
Bit 23
SIG
Bit 22
MSB
VIN ≥ FS 1 1
0V ≤ VIN < FS 1/0 0
–FS ≤ VIN < 0V 0 1
VIN < –FS 0 0
Table 1. Output Data Format
Differential Input Voltage
VIN*
Bit 23
SIG
Bit 22
MSB
Bit 21
Bit 20
Bit 19 … Bit 6
LSB
Bits 5-0
Always 0
VIN* ≥ FS** 1 1 0 0 0 … 0 000000
FS** – 1LSB 1 0 1 1 1 … 1 000000
0.5 • FS** 1 0 1 0 0 … 0 000000
0.5 • FS** – 1LSB 1 0 0 1 1 … 1 000000
0 1/0*** 0 0 0 0 … 0 000000
–1LSB 0 1 1 1 1 … 1 000000
–0.5 • FS** 0 1 1 0 0 … 0 000000
–0.5 • FS** – 1LSB 0 1 0 1 1 … 1 000000
–FS** 0 1 0 0 0 … 0 000000
VIN* < –FS** 0 0 1 1 1 … 1 000000
*The differential input voltage VIN = IN+ – IN–. **The full-scale voltage FS = 0.5 • VREF/Gain.
***The sign bit changes state during the 0 output code when the device is operating in the 2x speed mode.
LTC2487
17
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APPLICATIONS INFORMATION
INPUT DATA FORMAT
The serial input word to the LTC2487 is 16 bits long and
is written into the device input register in two 8-bit words.
The first word (SGL, ODD, A2, A1, A0) is used to select the
input channel. The second word of data (IM, FA, FB, SPD,
GS2, GS1, GS0) is used to select the frequency rejection,
speed mode (1x, 2x), temperature measurement, and gain.
After power-up, the device initiates an internal reset cycle
which sets the input channel to CH0-CH1 (IN+ = CH0, IN– =
CH1), the frequency rejection to simultaneous 50Hz/60Hz,
and 1x output rate (auto-calibration enabled), and gain =
1. The first conversion automatically begins at power-up
using this default configuration. Once the conversion is
complete, up to two words may be written into the device.
The first three bits of the first input word consist of two
preamble bits and one enable bit. Valid settings for these
three bits are 000, 100, and 101. Other combinations
should be avoided.
If the first three bits are 000 or 100, the following data is
ignored (don’t care) and the previously selected input chan-
nel and configuration remain valid for the next conversion.
If the first three bits shifted into the device are 101, then
the next five bits select the input channel for the next
conversion cycle (see Table 3).
Figure 3a. Timing Diagram for Reading from the LTC2487
Figure 3b. Timing Diagram for Writing to the LTC2487
DATA INPUT
ACK BY
LTC2487
ACK BY
LTC2487
ACK BY
LTC2487
(OPTIONAL 2ND BYTE)
START BY
MASTER
SGL ODD
W0
1
SCL
SDA
EN A2 A1 A0
7 … 8 92 123456789
1
7-BIT ADDRESS
2487 F03b
IM FAEN2 FB SPD GS2 GS1 GS0
SLEEP
1 9
2 3 4 5 6 7 8
SLEEP DATA OUTPUT
ACK BY
LTC2487
ACK BY
MASTER ALWAYS LOW
START BY
MASTER
NAK BY
MASTER
LSBR MSBSIG D23
7 … …8 9 1 2 9 1 2 3 4 5 6 7 8 9
1
7-BIT
ADDRESS
2487 F03a
SCL
SDA
Table 3. Channel Selection
MUX ADDRESS CHANNEL SELECTION
SGL
ODD/
SIGN A2 A1 A0 0 1 2 3 COM
*0 0 0 0 0 IN+IN–
00001 IN+IN–
01000IN–IN+
01001 IN–IN+
10000IN+IN–
10001 IN+IN–
11000 IN+IN–
11001 IN+IN–
*Default at power up
LTC2487
18
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Table 4. Converter Configuration
1 0 EN SGL ODD A2 A1 A0 EN2 IM FA FB SPD GS2 GS1 GS0 CONVERTER CONFIGURATION
1 0 0
Any
Input
Channel
X X X X X X X X Keep Previous
10 1 0 X X X X X X X Keep Previous
1 0 1 1 0
Any
Rejection
Mode
0 0 0 0 External Input, Gain = 1, Autocalibration
10 1 1 0 0 0 0 1 External Input, Gain = 4, Autocalibration
1 0 1 1 0 0 0 1 0 External Input, Gain = 8, Autocalibration
1 0 1 1 0 0 0 1 1 External Input, Gain = 16, Autocalibration
1 0 1 1 0 0 1 0 0 External Input, Gain = 32, Autocalibration
1 0 1 1 0 0 1 0 1 External Input, Gain = 64, Autocalibration
1 0 1 1 0 0 1 1 0 External Input, Gain = 128, Autocalibration
1 0 1 1 0 0 1 1 1 External Input, Gain = 256, Autocalibration
1 0 1 1 0 1 0 0 0 External Input, Gain = 1, 2x Speed
1 0 1 1 0 1 0 0 1 External Input, Gain = 2, 2x Speed
1 0 1 1 0 1 0 1 0 External Input, Gain = 4, 2x Speed
1 0 1 1 0 1 0 1 1 External Input, Gain = 8, 2x Speed
1 0 1 1 0 1 1 0 0 External Input, Gain = 16, 2x Speed
1 0 1 1 0 1 1 0 1 External Input, Gain = 32, 2x Speed
1 0 1 1 0 1 1 1 0 External Input, Gain = 64, 2x Speed
1 0 1 1 0 1 1 1 1 External Input, Gain = 128, 2x Speed
1 0 1 1 0 0 0
Any
Speed
Any
Gain
External Input, Simultaneous 50Hz/60Hz Rejection
10 1 1 0 0 1 External Input, 50Hz Rejection
1 0 1 1 0 1 0 External Input, 60Hz Rejection
10 1 1 0 1 1 Reserved, Do Not Use
1 0 1 1 1 0 0 X X X X Temperature Input, Simultaneous 50Hz/60Hz Rejection
1 0 1 1 1 0 1 X X X X Temperature Input, 50Hz Rejection
1 0 1 1 1 1 0 X X X X Temperature Input, 60Hz Rejection
1 0 1 1 1 1 1 X X X X Reserved, Do Not Use
The first input bit (SGL) following the 101 sequence de-
termines if the input selection is differential (SGL = 0) or
single-ended (SGL = 1). For SGL = 0, two adjacent channels
can be selected to form a differential input. For SGL = 1,
one of 4 channels is selected as the positive input. The
negative input is COM for all single-ended operations.
The remaining four bits (ODD, A2, A1, A0) determine
which channel(s) is/are selected and the polarity (for a
differential input).
Once the first word is written into the device, a second
word may be input in order to select a configuration mode.
The first bit of the second word is the enable bit for the
conversion configuration (EN2). If this bit is set to 0, then
the next conversion is performed using the previously
selected converter configuration.
The second set of configuration data can be loaded into
the device (see Table 4). The first bit (IM) is used to select
the internal temperature sensor. If IM = 1, the following
conversion will be performed on the internal temperature
sensor rather than the selected input channel. The next two
bits (FA and FB) are used to set the rejection frequency.
The next bit (SPD) is used to select either the 1x output
rate if SPD = 0 (auto-calibration is enabled and the offset
is continuously calibrated and removed from the final
conversion result) or the 2x output rate if SPD = 1 (offset
calibration disabled, multiplexing output rates up to 15Hz
with no latency). The final three bits (GS2, GS1, GS0) are
used to set the gain. When IM = 1 (temperature measure-
ment) SPD, GS2, GS1 and GS0 will be ignored and the
device will operate in 1x mode.
LTC2487
19
For more information www.linear.com/LTC2487
2487fg
Table 5a. Performance vs Gain in Normal Speed Mode (VCC = 5V, VREF = 5V)
GAIN 1 4 8 16 32 64 128 256 UNIT
Input Span ±2.5 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m ±9.76m V
LSB 38.1 9.54 4.77 2.38 1.19 0.596 0.298 0.149 µV
Noise Free Resolution* 65536 65536 65536 65536 65536 65536 32768 16384 Counts
Gain Error 5 5 5 5 5 5 5 8 ppm of FS
Offset Error 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 µV
Table 5b. Performance vs Gain in 2x Speed Mode (VCC = 5V, VREF = 5V)
GAIN 1 2 4 8 16 32 64 128 UNIT
Input Span ±2.5 ±1.25 ±0.625 ±0.312 ±0.156 ±78m ±39m ±19.5m V
LSB 38.1 19.1 9.54 4.77 2.38 1.19 0.596 0.298 µV
Noise Free Resolution* 65536 65536 65536 65536 65536 65536 45875 22937 Counts
Gain Error 5 5 5 5 5 5 5 5 ppm of FS
Offset Error 200 200 200 200 200 200 200 200 µV
*The resolution in counts is calculated as the FS divided by LSB or the RMS noise value, whichever is larger.
APPLICATIONS INFORMATION
The configuration remains valid until a new input word
with EN = 1 (the first three bits are 101 for the first word)
and EN2 = 1 (for the second write byte) is shifted into
the device.
Rejection Mode (FA, FB)
The LTC2487 includes a high accuracy on-chip oscillator
with no required external components. Coupled with an
integrated fourth order digital low pass filter, the LTC2487
rejects line frequency noise. In the default mode, the
LTC2487 simultaneously rejects 50Hz and 60Hz by at least
87dB. If more rejection is required, the LTC2487 can be
configured to reject 50Hz or 60Hz to better than 110dB.
Speed Mode (SPD)
Every conversion cycle, two conversions are combined
to remove the offset (default mode). This result is free
from offset and drift. In applications where the offset is
not critical, the auto-calibration feature can be disabled
with the benefit of twice the output rate.
While operating in the 2x mode (SPD = 1), the linearity
and full-scale errors are unchanged from the 1x mode
performance. In both the 1x and 2x mode there is no
latency. This enables input steps or multiplexer changes
to settle in a single conversion cycle, easing system over-
head and increasing the effective conversion rate. During
temperature measurements, the 1x mode is always used
independent of the value of SPD.
GAIN (GS2, GS1, GS0)
The input referred gain of the LTC2487 is adjustable
from 1 to 256 (see Tables 5a and 5b). With a gain of 1,
the differential input range is ±VREF/2 and the common
mode input range is rail-to-rail. As the gain is increased,
the differential input range is reduced to ±0.5 • VREF/Gain
but the common mode input range remains rail-to-rail.
As the differential gain is increased, low level voltages
are digitized with greater resolution. At a gain of 256, the
LTC2487 digitizes an input signal range of ±9.76mV with
over 16,000 counts.
Temperature Sensor
The LTC2487 includes an integrated temperature sen-
sor. The temperature sensor is selected by setting
IM = 1. The ADC internally connects to the temperature
sensor and performs a conversion.
The digital output is proportional to the absolute tem-
perature of the device. This feature allows the converter
to perform cold junction compensation for external
thermocouples or continuously remove the temperature
effects of external sensors.
LTC2487
20
For more information www.linear.com/LTC2487
2487fg
Figure 4. Internal PTAT Digital Output vs Temperature
Figure 5. Absolute Temperature Error
TEMPERATURE (°C)
–55 –30 –5
ABSOLUTE ERROR (°C)
5
4
3
2
1
–4
–3
–2
–1
0
12095704520
2487 F05
–5
TEMPERATURE (K)
0
DATAOUT
16
480
640
800
960
1020
400
2487 F04
320
0300200100
160
VCC = 5V
VREF = 5V
SLOPE = 2.45 LSB16/K
APPLICATIONS INFORMATION
The internal temperature sensor output is 28mV at 27°C
(300°K), with a slope of 93.5µV/°C independent of VREF
(see Figures 4 and 5). Slope calibration is not required if
the reference voltage (VREF) is known. A 5V reference has
a slope of 2.45 LSBs16/°C. The temperature is calculated
from the output code (where DATAOUT16 is the decimal
representation of the 16-bit result) for a 5V reference using
the following formula:
TK=DATAOUT16
2.45
in Kelvin
If a different value of VREF is used, the temperature
output is:
TDATAOUT • V /12.25 inKelvin
KREF
=
16
If the value of VREF is not known, the slope is determined
by measuring
the temperature sensor at a known tempera-
ture TN (in K) and using the following formula:
SLOPE =
DATAOUT
16
T
N
This value of slope can be used to calculate further tem-
perature readings using:
TK=
DATAOUT
16
SLOPE
All Kelvin temperature readings can be converted to TC
(ºC) using the fundamental equation:
TC = TK – 273
Initiating a New Conversion
When the LTC2487 finishes a conversion, it automatically
enters the sleep state. Once in the sleep state, the device is
ready for a read operation. After the device acknowledges
a read request, the device exits the sleep state and enters
the data output state. The data output state concludes
and the LTC2487 starts a new conversion once a Stop
condition is issued by the master or all 24 bits of data are
read out of the device.
During the data read cycle, a Stop command may be issued
by the master controller in order to start a new conversion
and abort the data transfer. This Stop command must be
issued during the ninth clock cycle of a byte read when
the bus is free (the ACK/NAK cycle).
LTC2487 Address
The LTC2487 has two address pins (CA0, CA1). Each may
be tied high, low, or left floating enabling one of 9 possible
addresses (see Table 6).
In addition to the configurable addresses listed in Table 6,
the LTC2487 also contains a global address (1110111)
which may be used for synchronizing multiple
LTC2487s or
other LTC24XX delta-sigma I2C devices (see Synchronizing
Multiple LTC2487s with a Global Address Call section).
LTC2487
21
For more information www.linear.com/LTC2487
2487fg
Figure 6. Conversion Sequence
Figure 7. Consecutive Reading with the Same Input/Configuration
Table 6. Address Assignment
CA1 CA0 ADDRESS
LOW LOW 0010100
LOW HIGH 0010110
LOW FLOAT 0010101
HIGH LOW 0100110
HIGH HIGH 0110100
HIGH FLOAT 0100111
FLOAT LOW 0010111
FLOAT HIGH 0100101
FLOAT FLOAT 0100100
S ACK DATA Sr DATA TRANSFERRING P
7-BIT ADDRESS R/W
2487 F06
CONVERSION CONVERSIONSLEEP DATA INPUT/OUTPUT
7-BIT ADDRESS 7-BIT ADDRESSS SR RACK ACKREAD READP P
2487 F07
CONVERSION
CONVERSION
ADDRESSSLEEP DATA OUTPUTDATA INPUT SLEEP
Operation Sequence
The LTC2487 acts as a transmitter or receiver, as shown
in Figure 6. The device may be programmed to perform
several functions. These include input channel selection,
measure the internal temperature, selecting the line fre-
quency rejection (50Hz, 60Hz, or simultaneous 50Hz and
60Hz), a 2x speed mode and gain.
Continuous Read
In applications where the input channel/configuration does
not need to change for each cycle, the conversion can be
continuously performed and read without a write cycle
(see Figure 7). The configuration/input channel remains
unchanged from the last value written into the device. If
the device has not been written to since power up, the
configuration is set to the default value. At the end of a
read operation, a new conversion automatically begins.
At the conclusion of the conversion cycle, the next result
may be read using the method described above. If the
conversion cycle is not concluded and a valid address
selects the device, the LTC2487 generates a NAK signal
indicating the conversion cycle is in progress.
Continuous Read/Write
Once the conversion cycle is concluded, the LTC2487 can
be written to and then read from using the Repeated Start
(Sr) command.
Figure 8 shows a cycle which begins with a data Write, a
repeated Start, followed by a Read and concluded with a
Stop command. The following conversion begins after all
24 bits are read out of the device or after a Stop command.
The following conversion will be performed using the newly
programmed data. In cases where the same speed (1x/2x
mode), rejection frequency (50Hz, 60Hz, 50Hz and 60Hz)
and gain is used but the channel is changed, a Stop or
Repeated Start may be issued after the first byte (channel
selection data) is written into the device.
Discarding a Conversion Result and Initiating a New
Conversion with Optional Write
At the conclusion of a conversion cycle, a write cycle
can be initiated. Once the write cycle is acknowledged, a
Stop command will start a new conversion. If a new input
channel or conversion configuration is required, this data
APPLICATIONS INFORMATION
LTC2487
22
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Figure 10. Synchronize Multiple LTC2487s with a Global Address Call
Figure 8. Write, Read, Start Conversion
Figure 9. Start a New Conversion Without Reading Old Conversion Result
7-BIT ADDRESS
CONVERSION
CONVERSION
ADDRESSSLEEP DATA OUTPUTDATA INPUT
7-BIT ADDRESSS RW ACK ACKWRITE Sr PREAD
2487 F08
7-BIT ADDRESS
CONVERSION CONVERSIONSLEEP DATA INPUT
S W ACK WRITE (OPTIONAL) P
2487 F09
GLOBAL ADDRESS
SCL
SDA
…
ALL LTC2487s IN SLEEP CONVERSION OF ALL LTC2487
s
DATA INPUT
S W ACK WRITE (OPTIONAL) P
2487 F10
LTC2487 LTC2487 LTC2487
can be written into the device and a Stop command will
initiate the next conversion (see Figure 9).
Synchronizing Multiple LTC2487s with a Global
Address Call
In applications where several LTC2487s (or other I2C
delta-sigma ADCs from Linear Technology Corporation)
are used on the same I2C bus, all converters can be syn-
chronized through the use of a global address call. Prior
to issuing the global address call, all converters must have
completed a conversion cycle. The master then issues a
Start, followed by the global address 1110111, and a write
request. All converters will be selected and acknowledge
the request. The master then sends a write byte (optional)
followed by the Stop command. This will update the chan-
nel selection (optional) converter configuration (optional)
and simultaneously initiate a start of conversion for all
delta-sigma ADCs on the bus (see Figure 10). In order
to synchronize multiple converters without changing
the channel or configuration, a Stop may be issued after
acknowledgement of the global write command. Global
read commands are not allowed and the converters will
NAK a global read request.
LTC2487
23
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Driving the Input and Reference
The input and reference pins of the LTC2487 are connected
directly to a switched capacitor network. Depending on
the relationship between the differential input voltage and
the differential reference voltage, these capacitors are
switched between these four pins. Each time a capacitor
is switched between two of these pins, a small amount
of charge is transferred. A simplified equivalent circuit is
shown in Figure 11.
When using the LTC2487’s internal oscillator, the input
capacitor array is switched at 123kHz. The effect of the
charge transfer depends on the circuitry driving the
input/reference pins. If the total external RC time constant
is less than 580ns the errors introduced by the sampling
process are negligible since complete settling occurs.
Typically, the reference inputs are driven from a low
impedance source. In this case, complete settling occurs
even with large external bypass capacitors. The inputs
(CH0-CH3, COM), on the other hand, are typically driven
from larger source resistances. Source resistances up
to 10k may interface directly to the LTC2487 and settle
completely; however, the addition of external capacitors
at the input terminals in order to filter unwanted noise
(antialiasing) results in incomplete settling.
Automatic Differential Input Current Cancellation
In applications where the sensor output impedance is
low (up to 10kW with no external bypass capacitor or up
to 500W with 0.001µF bypass), complete settling of the
input occurs. In this case, no errors are introduced and
direct digitization is possible.
Figure 11. Equivalent Analog Input Circuit
IN+
IN–
10kΩ
INTERNAL
SWITCH
NETWORK
10kΩ
CEQ
12µ
F
10kΩ
IIN–
REF+
IREF+
IIN+
IREF–
2487 F11
SWITCHING FREQUENCY
fSW = 123kHz INTERNAL OSCILLATOR
f
SW
= 0.4 • f
EOSC
EXTERNAL OSCILLATOR
REF–
10kΩ
100Ω
INPUT
MULTIPLEXER
100Ω
I IN+
( )
AVG
=I IN–
( )
AVG
=
VIN(CM) −VR EF( CM )
0. 5 •REQ
I R EF+
( )
AVG
≈
1.5 VR E F +VR EF( CM ) – VIN(CM)
( )
0.5 • R EQ
–VIN
2
VR EF • R E Q
where :
VR EF =R EF +−R EF −
VR EF( CM ) =R E F+– R EF −
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
VIN =IN+−IN−, WHER E IN+AND IN−AR E T HE S E L E CT E D I NP UT C HANNE L S
VIN(CM) =IN+– IN−
2
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
REQ =2.71MWINT E R NAL OS CIL L AT OR 6 0Hz M ODE
REQ =2.9 8 MWINTER NAL OS CIL L ATOR 50Hz/60Hz MODE
REQ =0.833•1012
( )
/fE OS C E XT E R NAL OS C IL L ATOR
LTC2487
24
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
For many applications, the sensor output impedance
combined with external input bypass capacitors produces
RC time constants much greater than the 580ns required
for 1ppm accuracy. For example, a 10kW bridge driving a
0.1µF capacitor has a time constant an order of magnitude
greater than the required maximum.
The LTC2487 uses a proprietary switching algorithm
that forces the average differential input current to zero
independent of external settling errors. This allows direct
digitization of high impedance sensors without the need
for buffers.
The switching algorithm forces the average input current
on the positive input (IIN+) to be equal to the average input
current on the negative input (IIN–). Over the complete
conversion cycle, the average differential input current
(IIN+ – IIN–) is zero. While the differential input current is
zero, the common mode input current (IIN+ + IIN–)/2 is
proportional to the difference between the common mode
input voltage (VIN(CM)) and the common mode reference
voltage (VREF(CM)).
In applications where the input common mode voltage is
equal to the reference common mode voltage, as in the
case of a balanced bridge, both the differential and com-
mon mode input current are zero. The accuracy of the
converter is not compromised by settling errors.
In applications where the input common mode voltage is
constant but different from the reference common mode
voltage, the differential input current remains zero while
the common mode input current is proportional to the
difference between VIN(CM) and VREF(CM). For a reference
common mode voltage of 2.5V and an input common mode
of 1.5V, the common mode input current is approximately
0.74µA (in simultaneous 50Hz/60Hz rejection mode). This
common mode input current does not degrade the accuracy
if the source impedances tied to IN+ and IN– are matched.
Mismatches in source impedance lead to a fixed offset
error but do not effect the linearity or full-scale reading.
A 1% mismatch in a 1k source resistance leads to a 74µV
shift in offset voltage.
In applications where the common mode input voltage
varies as a function of the input signal level (single-ended
type sensors), the common mode input current varies
proportionally with input voltage. For the case of balanced
input impedances, the common mode input current effects
are rejected by the large CMRR of the LTC2487, leading
to little degradation in accuracy. Mismatches in source
impedances lead to gain errors proportional to the dif-
ference between the common mode input and common
mode reference. A 1% mismatch in 1k source resistances
lead to gain errors on the order of 15ppm. Based on the
stability of the internal sampling capacitors and the ac-
curacy of the internal oscillator, a one-time calibration will
remove this error.
In addition to the input sampling current, the input ESD
protection diodes have a temperature dependent leakage
current. This current, nominally 1nA (±10nA max), results
in a small offset shift. A 1k source resistance will create a
1µV typical and a 10µV maximum offset voltage.
Reference Current
Similar to the analog inputs, the LTC2487 samples the
differential reference pins (REF+ and REF–) transferring
small amounts of charge to and from these pins, thus
producing a dynamic reference current. If incomplete set-
tling occurs (as a function the reference source resistance
and reference bypass capacitance) linearity and gain errors
are introduced.
LTC2487
25
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Figure 14. +FS Error vs RSOURCE
at VREF (Large CREF)
Figure 15. –FS Error vs RSOURCE
at VREF (Large CREF)
R
SOURCE
(Ω)
0
+FS ERROR (ppm)
300
400
500
800
2487 F14
200
100
0200 400 600
1000
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
R
SOURCE
(Ω)
0
–FS ERROR (ppm)
–200
–100
0
800
2487 F15
–300
–400
–500 200 400 600
1000
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
CREF = 1µF, 10µF
CREF = 0.1µF
CREF = 0.01µF
Figure 12. +FS Error vs RSOURCE at VREF (Small CREF) Figure 13. –FS Error vs RSOURCE at VREF (Small CREF)
R
SOURCE
(Ω)
0
+FS ERROR (ppm)
50
70
90
10k
2487 F12
30
10
40
60
80
20
0
–10 10 100 1k
100k
VCC = 5V
VREF = 5V
VIN+ = 3.75V
VIN– = 1.25V
fO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
R
SOURCE
(Ω)
0
–FS ERROR (ppm)
–30
–10
10
10k
2487 F13
–50
–70
–40
–20
0
–60
–80
–90 10 100 1k
100k
VCC = 5V
VREF = 5V
VIN+ = 1.25V
VIN– = 3.75V
fO = GND
TA = 25°C
CREF = 0.01µF
CREF = 0.001µF
CREF = 100pF
CREF = 0pF
For relatively small values of external reference capacitance
(CREF < 1nF), the voltage on the sampling capacitor settles
for reference impedances of many kW (if CREF = 100pF up
to 10kW will not degrade the performance (see Figures
12 and 13)).
In cases where large bypass capacitors are required on
the reference inputs (CREF > 0.01µF), full-scale and linear-
ity errors are proportional to the value of the reference
resistance. Every ohm of reference resistance produces
a full-scale error of approximately 0.5ppm (while operat-
ing in simultaneous 50Hz/60Hz mode (see Figures 14
and 15)). If the input common mode voltage is equal to
the reference common mode voltage, a linearity error of
approximately 0.67ppm per 100W of reference resistance
results (see Figure 16). In applications where the input
and reference common mode voltages are different, the
errors increase. A 1V difference in between common mode
input and common mode reference results in a 6.7ppm
INL error for every 100W of reference resistance.
In addition to the reference sampling charge, the reference
ESD protection diodes have a temperature dependent leak-
age current. This leakage current, nominally 1nA (±10nA
max) results in a small gain error. A 100W reference
resistance will create a 0.5µV full-scale error.
LTC2487
26
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Figure 16. INL vs Differential Input
Voltage and Reference Source
Resistance for CREF > 1µF
VIN/VREF
–0.5
INL (ppm OF V
REF
)
2
6
10
0.3
2487 F16
–2
–6
0
4
8
–4
–8
–10 –0.3 –0.1 0.1
0.5
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
CREF = 10µF
R = 1k
R = 100Ω
R = 500Ω
Figure 18. Input Normal Mode Rejection, Internal
Oscillator and 60Hz Rejection Mode
Figure 17. Input Normal Mode Rejection, Internal
Oscillator and 50Hz Rejection Mode
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS2fS3fS4fS5fS6fS7fS8fS9fS10fS
11fS
12f
S
INPUT NORMAL MODE REJECTION (dB)
2487 F17
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
0 fS
INPUT NORMAL MODE REJECTION (dB)
2487 F18
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 2fS3fS4fS5fS6fS7fS8fS9fS10f
S
Normal Mode Rejection and Antialiasing
One of the advantages delta-sigma ADCs offer over
conventional ADCs is on-chip digital filtering. Combined
with a large oversample ratio, the LTC2487 significantly
simplifies antialiasing filter requirements. Additionally,
the input current cancellation feature allows external low
pass filtering without degrading the DC performance of
the device.
The SINC4 digital filter provides excellent normal mode
rejection at all frequencies except DC and integer multiples
of the modulator sampling frequency (fS) (see Figures
17 and 18). The modulator sampling frequency is fS =
15,360Hz while operating with its internal oscillator and
fS = fEOSC/20 when operating with an external oscillator
of frequency fEOSC.
When using the internal oscillator, the LTC2487 is designed
to reject line frequencies. As shown in Figure 19, rejec-
tion nulls occur at multiples of frequency fN, where fN is
determined by the input control bits FA and FB (fN = 50Hz
or 60Hz or 55Hz for simultaneous rejection). Multiples
of the modulator sampling rate (fS = fN • 256) only reject
noise to 15dB (see Figure 20); if noise sources are present
at these frequencies antialiasing will reduce their effects.
The user can expect to achieve this level of performance
using the internal oscillator, as shown in Figures 21, 22,
and 23. Measured values of normal mode rejection are
LTC2487
27
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Figure 20. Input Normal Mode Rejection at fS = 256 • fN
Figure 19. Input Normal Mode Rejection at DC
INPUT SIGNAL FREQUENCY (Hz)
INPUT NORMAL MODE REJECTION (dB)
2487 F19
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120 fN
0 2fN3fN4fN5fN6fN7fN8f
N
fN = fEOSC/5120
INPUT SIGNAL FREQUENCY (Hz)
250fN252fN254fN256fN258fN260fN262f
N
INPUT NORMAL MODE REJECTION (dB)
2487 F20
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
fN = fEOSC/5120
Figure 21. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (60Hz Notch)
Figure 22. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz Notch)
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2487 F21
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
012.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
NORMAL MODE REJECTION (dB)
2487 F22
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
LTC2487
28
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
shown superimposed over the theoretical values in all
three rejection modes.
Traditional high order delta-sigma modulators suffer
from potential instabilities at large input signal levels.
The proprietary architecture used for the LTC2487 third
order modulator resolves this problem and guarantees
stability with input signals 150% of full scale. In many
industrial applications, it is not uncommon to have mi-
crovolt level signals superimposed over unwanted error
sources with several volts if peak-to-peak noise. Figures
24 and 25 show measurement results for the rejection
of a 7.5V peak-to-peak noise source (150% of full scale)
applied to the LTC2487. These curves show that the rejec-
tion performance is maintained even in extremely noisy
environments.
Figure 25. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (50Hz Notch)
Figure 24. Measure Input Normal Mode Rejection vs Input
Frequency with Input Perturbation of 150% (60Hz Notch)
Figure 23. Input Normal Mode Rejection vs Input Frequency with
Input Perturbation of 100% (50Hz/60Hz Notch)
INPUT FREQUENCY (Hz)
0 20 40 60 80 100 120 140 160 180 200
220
NORMAL MODE REJECTION (dB)
2487 F23
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
VIN(P-P) = 5V
TA = 25°C
MEASURED DATA
CALCULATED DATA
INPUT FREQUENCY (Hz)
015 30 45 60 75 90 105 120 135 150 165 180 195 210 225
240
NORMAL MODE REJECTION (dB)
2487 F24
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
INPUT FREQUENCY (Hz)
0
NORMAL MODE REJECTION (dB)
2487 F25
0
–20
–40
–60
–80
–100
–120
VCC = 5V
VREF = 5V
VIN(CM) = 2.5V
TA = 25°C
VIN(P-P) = 5V
VIN(P-P) = 7.5V
(150% OF FULL SCALE)
12.5 25 37.5 50 62.5 75 87.5 100 112.5 125 137.5 150 162.5 175 187.5
200
LTC2487
29
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Using the 2x speed mode of the LTC2487 alters the rejec-
tion characteristics around DC and multiples of fS. The
device bypasses the offset calibration in order to increase
the output rate. The resulting rejection plots are shown
in Figures 26 and 27. 1x type frequency rejection can be
achieved using the 2x mode by performing a running aver-
age of the previous two conversion results (see Figure 28).
Output Data Rate
When using its internal oscillator, the LTC2487 produces
up to 15 samples per second (sps) with a notch frequency of
60Hz. The actual output data rate depends upon the length
of the sleep and data output cycles which are controlled
by the user and can be made insignificantly short. When
operating with an external conversion clock (fO connected
to an external oscillator), the LTC2487 output data rate
can be increased. The duration of the conversion cycle is
41036/fEOSC. If fEOSC = 307.2kHz, the converter behaves
as if the internal oscillator is used.
An increase in fEOSC over the nominal 307.2kHz will trans-
late into a proportional increase in the maximum output
data rate (up to a maximum of 100sps). The increase in
output rate leads to degradation in offset, full-scale error
and effective resolution as well as a shift in frequency
rejection. When using the integrated temperature sensor,
the internal oscillator should be used or an external oscil-
lator fEOSC = 307.2kHz maximum.
A change in fEOSC results in a proportional change in the
internal notch position. This leads to reduced differential
mode rejection of line frequencies. The common mode
rejection of line frequencies remains unchanged, thus fully
differential input signals with a high degree of symmetry
on both the IN+ and IN– pins will continue to reject line
frequency noise.
An increase in fEOSC also increases the effective dynamic
input and reference current. External RC networks will
continue to have zero differential input current, but the
time required for complete settling (580ns for fEOSC =
307.2kHz) is reduced, proportionally.
Once the external oscillator frequency is increased above
1MHz (a more than 3x increase in output rate) the effective-
ness of internal auto calibration circuits begins to degrade.
This results in larger offset errors, full-scale errors, and
decreased resolution, as seen in Figures 29 to 36.
Figure 26. Input Normal Mode Rejection 2x Speed Mode Figure 27. Input Normal Mode Rejection 2x Speed Mode
INPUT SIGNAL FREQUENCY (fN)
INPUT NORMAL REJECTION (dB)
2487 F26
0
–20
–40
–60
–80
–100
–120 0fN2fN3fN4fN5fN6fN7fN8f
N
INPUT SIGNAL FREQUENCY (fN)
INPUT NORMAL REJECTION (dB)
2487 F27
0
–20
–40
–60
–80
–100
–120 250248 252 254 256 258 260 262
264
LTC2487
30
For more information www.linear.com/LTC2487
2487fg
Figure 28. Input Normal Mode
Rejection 2x Speed Mode with and
Without Running Averaging
Figure 29. Offset Error vs Output Data
Rate and Temperature
Figure 30. +FS Error vs Output Data
Rate and Temperature
Figure 31. –FS Error vs Output Data
Rate and Temperature
Figure 32. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 33. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 35. Resolution (NoiseRMS ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 36. Resolution (INLMAX ≤ 1LSB)
vs Output Data Rate and Temperature
Figure 34. Offset Error vs Output
Data Rate and Temperature
DIFFERENTIAL INPUT SIGNAL FREQUENCY (Hz)
48
–70
–80
–90
–100
–110
–120
–130
–140
54 58
2487 F28
50 52 56 60 62
NORMAL MODE REJECTION (dB)
NO AVERAGE
WITH
RUNNING
AVERAGE
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF V
REF
)
10
30
50
0
20
40
2487 F29
VIN(CM) = VREF(CM)
VCC = VREF = 5V
VIN = 0V
fO = EXT CLOCK
20 30
100
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
0
+FS ERROR (ppm OF V
REF
)
500
1500
2000
2500
3500
2487 F30
1000
3000
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
010 30
20
TA = 85°C
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
–3500
–FS ERROR (ppm OF V
REF
)
–3000
–2000
–1500
–1000
0
2487 F31
–2500
–500
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
TA = 85°C
010 30
20
TA = 25°C
010 30
20
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF V
REF
)
–5
5
10
20
2487 F34
0
15
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
VIN(CM) = VREF(CM)
VCC = VREF = 5V
fO = EXT CLOCK
RES = LOG 2 (VREF/INLMAX)
2487 F32
010
30
20
TA = 25°C, 85°C
010
30
20
VCC = 5V, VREF = 2.5V
VCC = VREF = 5V
OUTPUT DATA RATE (READINGS/SEC)
–10
OFFSET ERROR (ppm OF V
REF
)
–5
5
10
20
2487 F33
0
15
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
2487 F35
14
VIN(CM) = VREF(CM)
VIN = 0V
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/NOISERMS)
010
30
20
VCC = 5V, VREF = 2.5V, 5V
OUTPUT DATA RATE (READINGS/SEC)
10
RESOLUTION (BITS)
12
16
18
14
VIN(CM) = VREF(CM)
VIN = 0V
REF– = GND
fO = EXT CLOCK
TA = 25°C
RES = LOG 2 (VREF/INLMAX)
2487 F36
010
30
20
VCC = 5V, VREF = 2.5V, 5V
APPLICATIONS INFORMATION
LTC2487
31
For more information www.linear.com/LTC2487
2487fg
APPLICATIONS INFORMATION
Easy Drive ADCs Simplify Measurement of High
Impedance Sensors
Delta-Sigma ADCs, with their high accuracy and high noise
immunity, are ideal for directly measuring many types
of sensors. Nevertheless, input sampling currents can
overwhelm high source impedances or low-bandwidth,
micropower signal conditioning circuits. The LTC2487
solves this problem by balancing the input currents, thus
simplifying or eliminating the need for signal conditioning
circuits.
A common application for a delta-sigma ADC is thermistor
measurement. Figure 38 shows two examples of thermis-
tor digitization benefiting from the Easy Drive technology.
The first circuit (applied to input channels CH0 and CH1)
uses balanced reference resistors in order to balance the
common mode input/reference voltage and balance the
differential input source resistance. If reference resistors
R1 and R4 are exactly equal, the input current is zero and
no errors result. If these resistors have a 1% tolerance,
the maximum error in measured resistance is 1.6W due
to a shift in common mode voltage; far less than the 1%
error of the reference resistors themselves. No amplifier
is required, making this an ideal solution in micropower
applications.
Easy Drive also enables very low power, low bandwidth
amplifiers to drive the input to the LTC2487. As shown
in Figure 38, CH2 is driven by the LT1494. The LT1494
has excellent DC specs for an amplifier with 1.5µA supply
current (the maximum offset voltage is 150µV and the
open loop gain is 100,000). Its 2kHz bandwidth makes it
unsuitable for driving conventional delta sigma ADCs. Add-
ing a 1kW, 0.1µF filter solves this problem by providing a
charge reservoir that supplies the LTC2487 instantaneous
current, while the 1k resistor isolates the capacitive load
from the LT1494.
Conventional delta sigma ADCs input sampling current
lead to DC errors as a result of incomplete settling in the
external RC network.
The Easy Drive technology cancels the differential input
current. By balancing the negative input (CH3) with a 1kW,
0.1µF network errors due to the common mode input
current are cancelled.
V
CC + 0.3V
GND GND
GND
–0.3V
GND
–0.3V
–0.3V
(a) Arbitrary (b) Fully Differential
(d) Pseudo-Differential Unipolar
IN– or COM Grounded
(c) Pseudo Differential Bipolar
IN– or COM Biased
VREF
2
VREF
2
VREF
2
VREF
2
VREF
2
–VREF
2
–VREF
2
–VREF
2
Selected IN+ Ch
Selected IN
–
Ch or COM
VCC
VCC
2487 F37
VCC
VCC
Figure 37. Input Range
LTC2487
32
For more information www.linear.com/LTC2487
2487fg
3.00 ±0.10
(2 SIDES)
4.00 ±0.10
(2 SIDES)
NOTE:
1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDEC
PACKAGE OUTLINE MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE
TOP AND BOTTOM OF PACKAGE
0.40 ±0.10
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
R = 0.05
TYP
3.00 REF
1.70 ±0.05
17
148
PIN 1
TOP MARK
(SEE NOTE 6)
0.200 REF
0.00 – 0.05
(DE14) DFN 0806 REV B
PIN 1 NOTCH
R = 0.20 OR
0.35 × 45°
CHAMFER
3.00 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
2.20 ±0.05
0.70 ±0.05
3.60
±0.05
PACKAGE
OUTLINE
0.25 ±0.05
0.25 ±0.05
0.50 BSC
3.30 ±0.05
3.30 ±0.10
0.50 BSC
DE Package
14-Lead Plastic DFN (4mm × 3mm)
(Reference LTC DWG # 05-08-1708 Rev B)
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LTC2487#packaging for the most recent package drawings.
LTC2487
33
For more information www.linear.com/LTC2487
2487fg
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
REVISION HISTORY
(Revision history begins at Rev C)
REV DATE DESCRIPTION PAGE NUMBER
C 11/09 Update Tables 1 and 2 15
D 7/10 Revised Typical Application drawing
Revised parameter for VIHA in I2C Inputs and Digital Outputs
Added text to I2C Interface section
1
4
14
E 11/14 Clarify performance vs fO frequency, reduced external oscillator max frequency to 1MHz
Clarify input voltage range
Corrected Table 4 external input, Gain = 256, Autocalibration
5, 8, 30
4, 14, 31
18
F 2/15 Correcting typos in the Order Information table, Pin Configuration and Absolute Maximum Ratings 2
G 2/18 Replaced Figures 22, 23 with Figures 35, 36. 27, 28
LTC2487
34
For more information www.linear.com/LTC2487
2487fg
LT 0218 REV G • PRINTED IN USA
www.linear.com/LTC2487
ANALOG DEVICES, INC. 2007
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
LT1236A-5 Precision Bandgap Reference, 5V 0.05% Max Initial Accuracy, 5ppm/°C Drift
LT1460 Micropower Series Reference 0.075% Max Initial Accuracy, 10ppm/°C Max Drift
LT1790 Micropower SOT-23 Low Dropout Reference Family 0.05% Max Initial Accuracy, 10ppm/°C Max Drift
LTC2400 24-Bit, No Latency DS ADC in SO-8 0.3ppm Noise, 4ppm INL, 10ppm Total Unadjusted Error, 200µA
LTC2410 24-Bit, No Latency DS ADC with Differential Inputs 0.8µVRMS Noise, 2ppm INL
LTC2440 24-Bit, High Speed, Low Noise DS ADC 3.5kHz Output Rate, 200nVRMS Noise, 24.6 ENOBs
LTC2442 24-Bit, High Speed, 2-/4-Channel DS ADC with Integrated
Amplifier
8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2449 24-Bit, High Speed, 8-/16-Channel DS ADC 8kHz Output Rate, 200nVRMS Noise, Simultaneous 50Hz/60Hz
Rejection
LTC2480/LTC2482/
LTC2484
16-/24-Bit DS ADCs with Easy Drive Inputs, 600nVRMS Noise,
Programmable Gain, and Temperature Sensor
Pin Compatible 16-Bit and 24-Bit Versions
LTC2481/LTC2483/
LTC2485
16-/24-Bit DS ADCs with Easy Drive Inputs, 600nVRMS Noise,
I2C Interface, Programmable Gain, and Temperature Sensor
Pin Compatible 16-Bit and 24-Bit Versions
LTC2486/LTC2488/
LTC2492
16-Bit/24-Bit 2-/4-Channel DS ADC with Easy Drive Inputs, SPI
Interface, Programmable Gain, and Temperature Sensor
Pin-Compatible 16-Bit and 24-Bit Versions
LTC2489 16-Bit 2-/4-Channel DS ADC with Easy Drive Inputs and
I2C Interface
Pin Compatible with LTC2487/LTC2493
LTC2493 24-Bit 2-/4-Channel DS ADC with Easy Drive Inputs and
I2C Interface
Pin Compatible with LTC2487/LTC2489
LTC2495/LTC2497/
LTC2499
16-Bit/24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and
I2C Interface, Programmable Gain, and Temperature Sensor
Pin-Compatible 16-Bit and 24-Bit Versions
LTC2496/LTC2498 16-/24-Bit 8-/16-Channel DS ADC with Easy Drive Inputs and
SPI Interface
Pin Compatible with LTC2449/LTC2494
Figure 38. Easy Drive ADCs Simplify Measurement of High Impedance Sensors
VCC fO
SCL
SDA
GND
= EXTERNAL OSCILLATOR
= INTERNAL OSCILLATOR
LTC2487
2-WIRE
I2C INTERFACE
9-PIN SELECTABLE
ADDRESSES
2487 F38
CA0
12 1
REF+
13
REF–
14
CH0
8
CH1
9
CH2
10
CH3
11
COM
7
4
2
6
3
5
5V
0.1µF
10µF
CA1
IIN+ = 0
IIN– = 0
C4
0.1µF
C3
0.1µF
–
+
102k
5V
5V
LT1494
0.1µF
0.1µF
0.1µF
1k
1k
10k TO 100k
1.7k
5V
R1
51.1k
R4
51.1k
R3
10k TO 100k
