®
© 1998 Burr-Brown Corporation LI-519 Printed in U.S.A. August, 1998
DEM-ADS807E
EVALUATION FIXTURE
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
FEATURES
● PROVIDES FAST AND EASY
PERFORMANCE TESTING FOR
ADS807E
● SINGLE-ENDED OR DIFFERENTIAL
INPUT CONFIGURATION
● ACTIVE OR PASSIVE FRONT ENDS
● EXTERNAL REFERENCE OPTION
DESCRIPTION
The DEM-ADS807E evaluation fixture is designed
for ease of use when evaluating the high speed analog-
to-digital converter ADS807E. The ADS807E offers
12 bits of resolution with sampling rates of up to
53MHz. Because of its flexible design the user can
evaluate the converter in many different configura-
tions: either dc-coupled or ac-coupled input; or, single-
ended or differential inputs. The data output of the
ADS807E converter is decoupled from the connector
by CMOS octal logic buffers.
2
®
DEM-ADS807E
INITIAL CONFIGURATION
By using solder switches and resistor placements, DEM-
ADS807E can be set up in a variety of configurations to
accommodate a specific mode of operation. Before starting
evaluation, the user should decide on the configuration and
make the appropriate connections or changes. The demon-
stration board comes with following factory-set configura-
tion:
• The signal input is the unbuffered input at SMA connector
J2.
• Amplifiers U5 and U6 are performing a single-ended-to-
differential conversion, using an inverting and a non-
inverting gain stage.
• The signal is ac-coupled into the ADS807E by the cou-
pling capacitors C39 and C40.
• The converter is set to operate with the internal reference.
Solder switch ‘INT/EXT’ is closed.
• The common-mode voltage required to bias the input of
the ADS807E is derived from the internal top and bottom
references by R22, R23, and R24, R25, and applied to each
signal input, pin 24 and pin 25 (U1).
POWER SUPPLY
The demonstration board requires ±5V power supply volt-
ages. Two separate power connectors are on the board.
Connector P2, labeled with –5V, GND, and +5V, is the
supply connection for the analog front end (U4, U5, U6).
Connector P1, labeled with VDRV, GND, and +5V, is the
supply connector for the converter (U1). The VDRV con-
nector is tied to pin 28 of the ADS807E. Varying the voltage
on this pin will vary the data output voltage levels accord-
ingly. Setting VDRV to +3V typically provides the best
performance results.
SIGNAL INPUT
Unbuffered Input
The factory-set configuration of the demonstration board
uses the high-speed op amp OPA642N; a voltage feedback
op amp that features low distortion. Configured in an invert-
ing and non-inverting configuration, two OPA642Ns con-
vert the single-ended signal applied to SMA connector J2
into a differential signal to drive the differential input of the
ADS807E. The signal is ac-coupled to the ADS807 and the
required level shifting is done with resistors R22 through R25
at the inputs of the ADS807E. The op amp drivers are set for
a gain of 2.
Buffered Input
The demonstration board offers the option for a second
buffered input. If this configuration is desired, several com-
ponents have to be added to the board (e.g., a buffer
amplifier such as the OPA642 and its surrounding compo-
nents). Resistor R9 (0Ω) has to be removed when wiring this
circuit configuration. The buffered input configuration has
the benefit of providing a near ideal source impedance to the
driver amplifiers, especially important for the inverting gain
stage.
Transformer Coupled
The demonstration board provides the option to evaluate the
A/D converter with either an amplifier-based differential
interface, or with a RF transformer. The RF transformer is
used to convert the single-ended input signal applied to
SMA connector J4 into a differential signal. The following
steps have to be carried out to set up the board for the
transformer coupling:
• Remove R22, R23, R24, and R25.
• Remove C39 and C40 to disconnect the op amp outputs
from the converter inputs.
• Install R27 (0Ω) to connect the common-mode voltage
available on the CM pin to the secondary side of the
transformer.
• Install R26 and R28, typically 24.9Ω.
• Add an appropriate termination resistor (R29), depending
on the selected transformer model. The installed model
has a 1:1 turns ratio.
This differential input configuration can be operated with
external references as well.
Single-Ended Operation
The flexible design of the interface circuit configuration
allows the user to operate the ADS807E with a single-ended
input signal. The following component changes must be
made:
• Disconnect the output of amplifier U5 by removing C39.
• Remove R22 and R23.
• Install R30 (0Ω).
Amplifier U6 is now ac-coupled to the IN input of the
ADS807E and is driving it single-ended. This requires the
signal swing to be twice as high as in the differential mode,
now 2Vp-p instead of 1Vp-p.
Input Full-Scale Range Select
The ADS807E provides an option for the user to select
between a 2Vp-p and a 3Vp-p full-scale input range. This
function is controlled by the logic level applied to pin 15
(RSEL) of the ADS807E. Internally, the RSEL pin has a
pulldown resistor, setting the converter up for the 2Vp-p
range. Tying the RSEL pin to a logic HIGH potential (+5V)
will switch the converter into the 3Vp-p range operation.
This can be easily accomplished on the demostration board
by closing the RSEL solder switch.
3
®
DEM-ADS807E
CLOCK
The DEM-ADS807E requires an external TTL clock applied
at SMA connector J1. This input represents a 50Ω load to the
source. In order to preserve the specified performance of the
ADS807E converter, the clock source should feature a very
low jitter. This is particularly important if the converter is to
be evaluated in an undersampling condition. The ADS807E
can accept logic HIGH levels as low as +2.7V. For best
performance results, a +3V logic HIGH voltage with rise
and fall times of 1µs should be used.
EXTERNAL REFERENCE
The ADS807E can be operated with an external reference.
For this, solder switch ‘INT/EXT’ must be opened disabling
the internal references. Close solder switches JP3 and JP4
and apply the external reference voltage at connector P3.
The selected reference voltage determines the full-scale
input signal range of converter. However, the specified
range for external reference voltages should be observed
(see the ADS807 data sheet for details).
DATA OUTPUT
The data output is provided at CMOS logic levels. The
ADS807E uses Straight Offset Binary coding. The data
output pins of the converter are buffered from the I/O
connector, CN1, by two CMOS octal buffer (FCT541).
PC BOARD LAYOUT
The DEM-ADS807E demonstration board consists of a
four-layer PC board. To achieve the highest level of perfor-
mance, surface-mount components are used wherever pos-
sible. This reduces the trace length and minimizes the effects
of parasitic capacitance and inductance. The A/D converter
is treated like an analog component. Therefore, the demon-
stration board has one consistent ground plane. Keep in
mind that this approach may not necessarily yield optimum
performance results when designing the ADS807E into
different individual applications. In any case, thoroughly
bypassing the power supply and reference pins of the con-
verter, as demonstrated on the evaluation board, is strongly
recommended.
4
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DEM-ADS807E
9
8
7
6
5
4
3
2
1
15 +VS
16 RSEL
RSEL
17 OTROTR
18 INT/EXT
CLK
B10
B11
(LSB) B12
B9
11
12
13
10
B8
B7
B6
B5
B4
B3
B2
(MSB) B1
GND
U1
ADS807E
ADS807E
EVALUATION FIXTURE
29
28
27
26
25
24
22
20
18
16
18
17
16
15
14
13
12
11
00
01
02
03
04
05
06
07
2
3
4
5
6
7
8
9
1
19
D0
D1
D2
D3
D4
D5
D6
D7
2
3
4
5
6
7
8
9
D0
D1
D2
D3
D4
D5
D6
D7
OEA
OEB
18
17
16
15
14
13
12
11
O0
O1
O2
O3
O4
O5
O6
O7
U2
IDT74FCT541T 20
10
VCC
GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
15
13
11
9
7
5
3
1
CN1 B8
CN1 B7
CN1 B6
CN1 B5
CN1 B4
CN1 B3
CN1 B2
CN1 (MSB) B1
40
38
37
36
35
34
32
31
30
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
33
23
21
19
17
CN1 CLK
CN1 (LSB) B12
CN1 B11
CN1 B10
CN1 B9
39 CN1 OE
C10
2.2µF
REFT
VDD
R12(1)
R7(1)
49.9Ω
1
3
2U4
(1)
5
4
OPA642N
R11(1)
402Ω
R10(1)
402Ω
14
12
10
8
6
4
2
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
CN1 GND
JP3
R2(1)
10kΩ
R4
10kΩ
C22
0.1µF
1
19 OEA
OEB
U3
IDT74FCT541T 20
10
VCC
GND
R4(1)
10kΩ
R5
10kΩ
R1
49.9Ω
J1Clock
Input
C23
0.1µF
L1(1)
+5V
VDD
L2
0.3µH
J4
DIFF. IN 1
2
3
6
5
4
R31(1)
0Ω
R28(1)
24.9Ω
T1
TT1-6
R26(1)
24.9Ω
R22
1.82kΩ
R27(1)
0Ω
C9
0.1µF
27 +VS
26 GND
25 IN
C19
2.2µF
VDD
+C18
0.1µF
28
+VDRV
C21
2.2µF
NOTE: (1) Part not assembled.
VDRV C20
0.1µF
19 OE
R23
1.82kΩ
22 REFT
C14
10µF+C13
0.1µF
C45
10µF+
20 GND
21 REFB
C12
10µF+
C39
0.1µF
C11
0.1µF
23 CM
R30(1)
C15
0.1µF
C46
0.1µF
24 IN
C16
100pF
C17
100pF
14
C27(1)
2.2µF
C26(1)
0.1µF
++5V
C42(1)
0.1µF
C24(1)
0.1µF
C25(1)
2.2µF
+–5V
C37(1)
0.1µF
C36(1)
J3(1)
VINDIFF
R13
200Ω
R9
0Ω
R6
66.5Ω
J2
VINSE
R15
0Ω
1
3
2U5
5
4
OPA642N
R14
402Ω
C31
2.2µF
C30
0.1µF
++5V
C43
0.1µF
C28(1)
0.1µF
C29(1)
2.2µF
+–5V
R16
24.9Ω
1
3
2U6
5
4
OPA642N
R18
402Ω
C35
2.2µF
C34
0.1µF
++5V
C44
0.1µF
C32
0.1µF
C33
2.2µF
+–5V
R17
402Ω
C38
0.1µFR21
24.9ΩC40
0.1µF
R25
1.82kΩ
R24
1.82kΩ
R20B
0Ω
R20A(1)
REFB
JP4
VDD VDRV
1
P1
23 C1
0.1µF
C2
10µF
+
C3
0.1µF
C4
10µF
+
+5V –5V
1
P2
23 C5
0.1µF
C6
10µF
+
C7
0.1µF
C8
10µF
+
REFT REFB
1
P3(1)
23
R8
49.9ΩR29(1)
C41(1)
0.1µF
R19
0Ω
INT/EXT
OE
FIGURE 1. DEM-ADS807E Circuit Schematic.
5
®
DEM-ADS807E
FIGURE 3. Power Plane.
FIGURE 2. Top Layer with Silk Screen.
6
®
DEM-ADS807E
FIGURE 4. Ground Plane.
FIGURE 5. Bottom Layer with Silk Screen.
7
®
DEM-ADS807E
REFERENCE QTY COMPONENT DESCRIPTION MANUFACTURER
U1 1 ADS807E High-Speed ADC, 28-Lead SSOP Burr-Brown
U2, U3 2 74FCT541 5V Octal Buffer, 20-Lead SOIC IDT
U5, U6 2 OPA642 NB Wideband, Single Op Amp, SO-8 Burr-Brown
R9, R19, R15, R20B 4 CRCW0805ZEROF 0Ω, MF 0805 Chip Resistor, 1% Dale
R16, R21 2 CRCW0805245R9F 24.9Ω, MF 0805 Chip Resistor, 1% Dale
R1, R82 CRCW080549R9F 49.9Ω, MF 0805 Chip Resistor, 1% Dale
R61 CRCW080566R5F 66.5Ω, MF 0805 Chip Resistor, 1% Dale
R13 1 CRCW08052000F 200Ω, MF 0805 Chip Resistor, 1% Dale
R14, R17, R18 3 CRCW08054020F 402Ω, MF 0805 Chip Resistor, 1% Dale
R22, R23, R24,R 25 4 CRCW08051821F 1.82kΩ, MF 0805 Chip Resistor, 1% Dale
R3, R52 CRCW08051002F 10kΩ, MF 0805 Chip Resistor, 1% Dale
R2, R4,R 7, R10, R11, R12, R20A, R26, 13 Not Assembled
R27, R28, R29, R30, R31
C2, C4, C6, C8, C12, C14, C45 7 T491B106M006AS 10µF, 6V, Size 3528 Tantalum Capacitor Kemet
C10, C19, C21, C29, C31, C33, C35 7 T491A225M010AS 2.2µF, 10V, Size 3216 Tantalum Capacitor Kemet
C1, C3, C5, C7, C9, C11, C13, C15, C18, 23 08055C104KAT 0.1µF, 50V X7R 0805 Ceramic Capacitor AVX
C20, C22,C23, C28, C30, C32, C34, C38,
C39, C40, C41, C43, C44, C46
C16, C17 2 08055C101KAT 100pF, 50V NP0 0805 Ceramic Capacitor AVX
C24, C25, C26, C27, C36, C37, C42 7 Not Assembled
L1 1 L1-1206B900R Ferrite Chip, 900Ω at100MHz Steward
T1 1 T1-1T-KK81 RF Transformer Mini-Circuits
P1, P2 2 ED555/3DS 3-Pin Term Block On-Shore Technology
CN1 1 IDH-40LP-S3-TG 20 x 2 Dual-Row Shrouded Header Robinson-Nugent
J1, J2, J4 3 142-0701-201 Straight SMA PCB Connector EF Johnson
4 1-SJ5003-0-N Rubber Feet, Black, 0.44 x 0.2 Digi-Key
1 PCB A2462 PC Board A2462, Rev. D Burr-Brown
COMPONENT LIST
