AD8315ARMZ-REEL - Analog Devices

REV. B

AD8315

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50 dB GSM PA Controller

FUNCTIONAL BLOCK DIAGRAM

10dB

OFFSET

COMP’N

INTERCEPT

POSITIONING

10dB10dB10dB

DETDETDETDETDET

RFIN

1.35

HI-Z

LOW NOISE (25nV/ Hz)

RAIL-TO-RAIL BUFFER

V-I VSET

23mV/dB

250mV to

1.4V = 50dB

FLTR

VAPC

OUTPUT

ENABLE

DELAY

LOW NOISE

BAND GAP

REFERENCE

LOW NOISE

GAIN BIAS

COMM

VPOS

ENBL

FEATURES

Complete RF Detector/Controller Function

>50 dB Range at 0.9 GHz (–49 dBm to +2 dBm re 50 )

Accurate Scaling from 0.1 GHz to 2.5 GHz

Temperature-Stable Linear-in-dB Response

Log Slope of 23 mV/dB, Intercept at –60 dBm at 0.9 GHz

True Integration Function in Control Loop

Low Power: 20 mW at 2.7 V, 38 mW at 5 V

Power Down to 10.8 W

APPLICATIONS

Single, Dual, and Triple Band Mobile Handset

(GSM, DCS, EDGE)

Transmitter Power Control

PRODUCT DESCRIPTION

The AD8315 is a complete low cost subsystem for the precise

control of RF power amplifiers operating in the frequency range

0.1 GHz–2.5 GHz and over a typical dynamic range of 50 dB. It is

intended for use in cellular handsets and other battery-operated

wireless devices. The log amp technique provides a much wider

measurement range and better accuracy than controllers using

diode detectors. In particular, its temperature stability is excellent

over a specified range of –30∞C to +85∞C.

Its high sensitivity allows control at low signal levels, thus reduc-

ing the amount of power that needs to be coupled to the detector.

For convenience, the signal is internally ac-coupled. This

high-pass coupling, with a corner at approximately 0.016 GHz,

determines the lowest operating frequency. Thus, the source

may be dc grounded.

The AD8315 provides a voltage output, VAPC, that has the

voltage range and current drive to directly connect to most hand-

set power amplifiers’ gain control pin. VAPC can swing from 250

mV above ground to within 200 mV below the supply voltage.

Load currents of up to 6 mA can be supported.

The setpoint control input is applied to pin VSET and has an

operating range of 0.25 V–1.4 V. The associated circuit deter-

mines the slope and intercept of the linear-in-dB measurement

system; these are nominally 23 mV/dB and –60 dBm for a 50 W

termination (–73 dBV) at 0.9 GHz. Further simplifying the

application of the AD8315, the input resistance of the setpoint

interface is over 100 MW, and the bias current is typically 0.5 mA.

The AD8315 is available in MSOP and lead frame chip scale

(LFCSP) packages and consumes 8.5 mA from a 2.7 V to 5.5 V

supply. When powered down, the sleep current is 4 mA.

REV. B

–2–

AD8315–SPECIFICATIONS

(VS = 2.7 V, T = 25C, 52.3  termination on RFIN, unless otherwise noted.)

Parameter Conditions Min Typ Max Unit

OVERALL FUNCTION

Frequency Range

To Meet All Specifications 0.1 2.5 GHz

Input Voltage Range ±1 dB Log Conformance, 0.1 GHz –57 –11 dBV

Equivalent dBm Range –44 +2 dBm

Logarithmic Slope

0.1 GHz 21.5 24 25.5 mV/dB

Logarithmic Intercept

0.1 GHz –79 –70 –64 dBV

Equivalent dBm Level –66 –57 –51 dBm

RF INPUT INTERFACE Pin RFIN

Input Resistance

0.1 GHz 2.8 kW

Input Capacitance

0.1 GHz 0.9 pF

OUTPUT Pin VAPC

Minimum Output Voltage VSET £ 200 mV, ENBL High 0.25 0.27 0.3 V

ENBL Low 0.02 V

Maximum Output Voltage R

≥ 800 W2.45 2.6 V

vs. Temperature

85∞C, V

POS

=3 V, I

OUT

=6 mA 2.54 V

General Limit 2.7 V £ VPOS £ 5.5 V, R

= •VPOS – 0.1 V

Output Current Drive Source/Sink 5/200 mA/mA

Output Buffer Noise 25 nV÷Hz

Output Noise RF Input = 2 GHz, 0 dBm, f

NOISE

= 100 kHz, 130 nV/÷Hz

FLT

= 220 pF

Small Signal Bandwidth 0.2 V to 2.6 V Swing 30 MHz

Slew Rate 10%–90%, 1.2 V Step (V

SET

), Open Loop

13 V/ms

Response Time FLTR = Open, Refer to TPC 24 150 ns

SETPOINT INTERFACE Pin VSET

Nominal Input Range Corresponding to Central 50 dB 0.25 1.4 V

Logarithmic Scale Factor 43.5 dB/V

Input Resistance 100 kW

Slew Rate 16 V/ms

ENABLE INTERFACE Pin ENBL

Logic Level to Enable Power 1.8 V

POS

Input Current when Enable High 20 mA

Logic Level to Disable Power 0.8 V

Enable Time Time from ENBL High to V

APC

within 1% of 4 5 ms

Final Value, V

SET

£ 200 mV, Refer to TPC 21

Disable Time Time from ENBL Low to V

APC

within 1% of 8 9 ms

Final Value, V

SET

£ 200 mV, Refer to TPC 21

Power-On/Enable Time Time from VPOS/ENBL High to V

APC

within 2 3 ms

1% of Final Value, V

SET

£ 200 mV, Refer to

TPC 26

Time from VPOS/ENBL Low to V

APC

within 100 200 ns

1% of Final Value, V

SET

£ 200 mV, Refer to

TPC 26

POWER INTERFACE Pin VPOS

Supply Voltage 2.7 5.5 V

Quiescent Current ENBL High 8.5 10.7 mA

Over Temperature –30∞C £ T

£ +85∞C12.9mA

Disable Current

ENBL Low 4 10 mA

Over Temperature –30∞C £ T

£ +85∞C13mA

NOTES

Operation down to 0.02 GHz is possible.

Mean and Standard Deviation specifications are available in Table I.

See TPC 9 for plot of Input Impedance vs. Frequency.

This parameter is guaranteed but not tested in production. Limit is –3 sigma from the mean.

Response time in a closed-loop system will depend upon the filter capacitor (C

FLT

) used and the response of the variable gain element.

This parameter is guaranteed but not tested in production. Maximum specified limit on this parameter is the +6 sigma value.

Specifications subject to change without notice.

REV. B

AD8315

–3–

ABSOLUTE MAXIMUM RATINGS*

Supply Voltage VPOS . . . . . . . . . . . . . . . . . . . . . . . . . . .5.5 V

Temporary Overvoltage VPOS

(100 cycles, 2 seconds duration, ENBL Low) . . . . . . . 6.3 V

VAPC, VSET, ENBL . . . . . . . . . . . . . . . . . . . . . . 0 V, VPOS

RFIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 dBm

Equivalent Voltage . . . . . . . . . . . . . . . . . . . . . . . . 1.6 V rms

Internal Power Dissipation . . . . . . . . . . . . . . . . . . . . . 60 mW

(MSOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200∞C/W

(LFCSP, Paddle Soldered) . . . . . . . . . . . . . . . . . . 80∞C/W

(LFCSP, Paddle not Soldered) . . . . . . . . . . . . . 200∞C/W

Maximum Junction Temperature . . . . . . . . . . . . . . . . . 125∞C

Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature Range (Soldering 60 sec)

MSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300∞C

LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

PIN FUNCTION DESCRIPTIONS

No. Mnemonic Function

1RFIN RF Input

2ENBL Connect to VPOS for Normal Operation

Connect pin to ground for Disable Mode

3VSET Setpoint Input. Nominal input range

0.25 V to 1.4 V.

4FLTR Integrator Capacitor. Connect between

FLTR and COMM.

5COMM Device Common (Ground)

6NCNo Connection

7VAPC Output. Control voltage for gain control

element.

8VPOS Positive Supply Voltage: 2.7 V to 5.5 V

ORDERING GUIDE

Model Temperature Range Package Descriptions Package Option Branding Information

AD8315ARM –30∞C to +85∞CTube, 8-Lead MSOP RM-8 J7A

AD8315ARM-REEL 13" Tape and Reel

AD8315ARM-REEL7 7" Tape and Reel

AD8315-EVAL MSOP Evaluation Board

AD8315ACP-REEL –30∞C to +85∞C13" Tape and Reel, CP-8 J7A

8-Lead LFCSP

AD8315ACP-REEL7 7" Tape and Reel

AD8315ACP-EVAL LFCSP Evaluation Board

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although

the AD8315 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

Table I. Typical Specifications at Selected Frequencies at 25C (Mean and Sigma)

1 dB Dynamic Range

Slope – mV/dB Intercept – dBV Low Point – dBV High Point – dBV

Frequency – GHz Mean Sigma Mean Sigma Mean Sigma Mean Sigma

0.1 23.8 0.3 –70.1 1.8 –57.7 1.3 –10.6 0.8

0.9 23.2 0.4 –72.6 1.8 –61.0 1.3 –11.2 0.8

1.9 22.2 0.3 –73.8 1.6 –62.9 0.9 –18.5 1.7

2.5 22.3 0.4 –75.6 1.5 –64.0 1.1 –20.0 1.7

REV. B

AD8315

–4–

–Typical Performance Characteristics

RF INPUT AMPLITUDE – dBV

VSET – V

0.2

–10

–20

–30

–40

–50

–60

–70

–80

0.4 0.6 0.8 1.0 1.2 1.4

0.1GHz

0.9GHz

1.9GHz

2.5GHz

–7

–17

–27

–37

–47

–57

–67

RF INPUT AMPLITUDE – dBm

TPC 1. Input Amplitude vs. V

SET

VSET – V

0.1

–10

–20

–30

–40

–50

–60

–70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–1

–2

–3

–4

ERROR – dB

–30C

+85C

+25C

–30C

+25C

+85C

RF INPUT

AMPLITUDE – dBV

(+3dBm)

(–47dBm) ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 2. Input Amplitude and Log Conformance vs. V

SET

0.1 GHz

VSET – V

0.1

–10

–20

–30

–40

–50

–60

–70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–1

–2

–3

–4

ERROR – dB

–30C

+85C

+25C

–30C

+25C

+85C

RF INPUT

AMPLITUDE – dBV

(+3dBm)

(–47dBm) ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 3. Input Amplitude and Log Conformance vs. V

SET

0.9 GHz

SET

– V

0.2

ERROR – dB

–1

–2

–3

–4

0.4 0.6 0.8 1.0 1.2 1.4 1.6

0.1GHz 0.9GHz

1.9GHz

2.5GHz

TPC 4. Log Conformance vs. V

SET

– V

0.1

–10

–20

–30

–40

–50

–60

–70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–1

–2

–3

–4

ERROR – dB

–30C

+85C

+25C

+85C

–30C

RF INPUT

AMPLITUDE – dBV

(+3dBm)

(–47dBm) ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 5. Input Amplitude and Log Conformance vs. V

SET

1.9 GHz

VSET – V

0.1

–10

–20

–30

–40

–50

–60

–70

0.3 0.5 0.7 0.9 1.1 1.3 1.5

–1

–2

–3

–4

ERROR – dB

–30C+85C

+25C

–30C+85C

+25C

RF INPUT

AMPLITUDE – dBV

(+3dBm)

(–47dBm) ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 6. Input Amplitude and Log Conformance vs. V

SET

2.5 GHz

REV. B –5–

AD8315

RF INPUT AMPLITUDE – dBV

–4

–80 0–70

ERROR – dB

–50 –40 –30 –20 –10

–1

–2

–3

–60

(

+3dBm

)(

–47dBm

)

–30C

+85C

ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 7. Distribution of Error at Temperature after Ambient

Normalization vs. Input Amplitude, 3 Sigma to Either Side

of Mean, 0.1 GHz

RF INPUT AMPLITUDE – dBV

–4

–80 0–70

ERROR – dB

–50 –40 –30 –20 –10

–1

–2

–3

–60

30C

85C

(+3dBm)(–47dBm)

ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 8. Distribution of Error at Temperature after Ambient

Normalization vs. Input Amplitude, 3 Sigma to Either Side

of Mean, 0.9 GHz

FREQUENCY – GHz

3000

2700

00 2.50.5 1 1.5 2

1800

900

600

300

2400

2100

1200

1500

RESISTANCE – 

–200

–2000

–800

–1400

–1600

–1800

–400

–600

–1200

–1000

REACTANCE – 

FREQUENCY

(GHz)

0.1

0.9

1.9

2.5

R –

2700 –

730 –

460 –

440 –

jX

j1500

j220

j130

j110

R –

2900 –

700 –

130 –

170 –

jX

j1900

j240

j80

j70

MSOP Chip Scale (LFCSP)

R (LFCSP)

R (MSOP)

X (LFCSP)

X (MSOP)

TPC 9. Input Impedance

RF INPUT AMPLITUDE – dBV

–4

–80 0–70

ERROR – dB

–50 –40 –30 –20 –10

–1

–2

–3

–60

–30C

+85C

(

+3dBm

)(

–47dBm

)

ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

TPC 10. Distribution of Error at Temperature after Ambient

Normalization vs. Input Amplitude, 3 Sigma to Either Side of

Mean, 1.9 GHz

RF INPUT AMPLITUDE – dBV

–4

–80 0–70

ERROR – dB

–50 –40 –30 –20 –10

–1

–2

–3

–60

–30C

(

+3dBm

)(

–47dBm

)

ERROR AT +85C AND –30C

BASED ON DEVIATION FROM

SLOPE AND INTERCEPT AT +25C

+85C

TPC 11. Distribution of Error at Temperature after Ambient

Normalization vs. Input Amplitude, 3 Sigma to Either Side of

Mean, 2.5 GHz

VENBL – V

01.3

SUPPLY CURRENT – mA

1.4 1.5 1.6 1.7

DECREASING

VENBL

INCREASING

VENBL

TPC 12. Supply Current vs. V

ENBL

REV. B

AD8315

–6–

FREQUENCY – GHz

SLOPE – mV/dB

20 0.5 1.0 1.5 2.0 2.5

+85 C

+25 C

–30 C

TPC 13. Slope vs. Frequency; –30

∞

C, +25

∞

C, and +85

∞

VS – V

2.5

SLOPE – mV/dB

3.0 3.5 4.0 4.5 5.0 5.5

0.1GHz

0.9GHz

1.9GHz

2.5GHz

TPC 14. Slope vs. Supply Voltage

FREQUENCY – Hz

AMPLITUDE – dB

–5

–15

–25

–35

100 1k 10k 100k 1M 10M

–20

–40

–60

–80

–100

–120

PHASE – De

rees

–20

–10

–30

–40

–10

–30

–50

–70

–90

–110

–130

FLT

= 220pF

FLT

= 0pF

TPC 15. AC Response from VSET to VAPC

FREQUENCY – GHz

–66

INTERCEPT – dBV

–68

–70

–72

–74

–76

–78

–80

0.5 1.0 1.5 2.0 2.5

+25 C

+85 C

–30 C



TPC 16. Intercept vs. Frequency; –30

∞

C, +25

∞

C, and +85

∞

VS – V

2.5

INTERCEPT – dBV

–68

–70

–72

–74

–76

–78

–80

3.0 3.5 4.0 4.5 5.55.0

0.9GHz

1.9GHz

0.1GHz

2.5GHz

TPC 17. Intercept vs. Supply Voltage

FREQUENCY – Hz

10000

100

NOISE SPECTRAL DENSITY – nV/ Hz

1000

100

1k 10k 100k 1M 10M

RF INPUT

–51dBV

–48dBV

–13dBV

–23dBV

–43dBV

–33dBV

–53dBV AND

–63dBV

CFLT = 220PF, RF INPUT = 2GHz

TPC 18. V

APC

Noise Spectral Density

REV. B

AD8315

–7–

SUPPLY VOLTAGE – V

3.5

2.7

APC

– V

3.3

3.1

2.9

2.7

2.5

2.3

2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5

4mA

6mA

0mA

2mA

TPC 19. Maximum V

APC

Voltage vs. Supply Voltage by

Load Current

AVERAGE = 16 SAMPLES

200mV PER VERTICAL

DIVISION

APC

ENBL

2 s PER

HORIZONTAL

DIVISION

1V PER

VERTICAL

DIVISION

GND

TPC 20. ENBL Response Time

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

220pF

2.7V

52.3

0.1F

TEK P6205

FET PROBE

TEK TDS694C

SCOPE

TEK P6205

FET PROBE

TRIG

STANFORD DS345

PULSE

GENERATOR

PULSE OUT

TRIG

OUT

RF OUT

10MHz REF

OUTPUT TIMEBASE

R AND S

SMT03

SIGNAL

GENERATOR

TPC 21. Test Setup for ENBL Response Time

SUPPLY VOLTAGE – V

2.8

2.7

APC

– V

2.7

2.6

2.5

2.4

2.8 3.0

SHADING INDICATES

3 SIGMA

2.9

TPC 22. Maximum V

APC

Voltage vs. Supply Voltage with

4 mA Load Current

100ns PER

HORIZONTAL

DIVISION

AVERAGE = 16 SAMPLES

APC

PULSED RF

0.1GHz, –13dBV

1V PER

VERTICAL

DIVISION

INPUT

GND

TPC 23. V

APC

Response Time, Full-Scale Amplitude

Change, Open-Loop

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

2.7V

0.1 F

TEK P6205

FET PROBE

TEK TDS694C

SCOPE

TRIG

PICOSECOND

PULSE LABS

PULSE

GENERATOR

PULSE OUT

TRIG

OUT

R AND S SMT03

SIGNAL

GENERATOR

PULSE

MODULATION

MODE

10MHz REF

OUTPUT EXT TRIG

PULSE MODE IN OUT

52.3

RF OUT

–3dB

2.7V

0.3V

SPLITTER

TPC 24. Test Setup for VAPC

Response Time

REV. B

AD8315

–8–

AVERAGE = 16 SAMPLES

VAPC

AND

VENBL

2 s PER

HORIZONTAL

DIVISION

1V PER

VERTICAL

DIVISION

200mV PER

VERTICAL

DIVISION

GND

TPC 25. Power-On and -Off Response with

SET

Grounded

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

220pF

52.3

TEK TDS694C

SCOPE

TRIG

STANFORD DS345

PULSE

GENERATOR

PULSE OUT

TRIG

OUT

R AND S

SMT03

SIGNAL

GENERATOR

RF OUT

10MHz REF

OUTPUT EXT TRIG

TEK P6205

FET PROBE

AD811

732

49.9

TEK P6205

FET PROBE

TPC 26. Test Setup for Power-On and -Off Response with

VSET Grounded

GND

VAPC

1V PER

VERTICAL

DIVISION

500mV PER

VERTICAL

DIVISION

2s PER

HORIZONTAL

DIVISION

AVERAGE = 16 SAMPLES

TPC 27. Power-On and -Off Response with V

SET

and

ENBL Grounded

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

220pF

52.3

TEK TDS694C

SCOPE

TRIG

STANFORD DS345

PULSE

GENERATOR

PULSE OUT

TRIG

OUT

R AND S

SMT03

SIGNAL

GENERATOR

RF OUT

10MHz REF

OUTPUT EXT TRIG

TEK P6205

FET PROBE

AD811

732

49.9

TEK P6205

FET PROBE

TPC 28. Test Setup for Power-On and -Off Response with

VSET and ENBL Grounded

GENERAL DESCRIPTION AND THEORY

The AD8315 is a wideband logarithmic amplifier (log amp)

similar in design to the AD8313 and AD8314. However, it is

strictly optimized for use in power control applications rather

than as a measurement device. Figure 1 shows the main features

in block schematic form. The output (Pin 7, VAPC) is intended

to be applied directly to the automatic power-control (APC) pin

of a power amplifier module.

Basic Theory

Logarithmic amplifiers provide a type of compression in which a

signal having a large range of amplitudes is converted to one of

smaller range. The use of the logarithmic function uniquely results

in the output representing the decibel value of the input. The

fundamental mathematical form is:

VV V

OUT SLP

=log10

(1)

Here V

is the input voltage, V

is called the intercept (voltage)

because when V

= V

the argument of the logarithm is unity

and thus the result is zero, and V

SLP

is called the slope (voltage),

which is the amount by which the output changes for a certain

change in the ratio (V

). When BASE-10 logarithms are used,

denoted by the function log

, V

SLP

represents the “volts/decade,”

and since a decade corresponds to 20 dB, V

SLP

/20 represents the

“volts/dB.” For the AD8315, a nominal (low frequency) slope

of 24 mV/dB was chosen, and the intercept V

was placed at the

equivalent of –70 dBV for a sine wave input (316 mV rms). This

corresponds to a power level of –57 dBm when the net resistive

part of the input impedance of the log amp is 50 W. However,

both the slope and the intercept are dependent on frequency (see

TPC 13 and TPC 16).

Keeping in mind that log amps do not respond to power but

only to voltages and that the calibration of the intercept is

waveform dependent and is only quoted for a sine wave signal,

the equivalent power response can be written as:

VVPP

OUT DB IN Z

=(–)

(2)

where the input power P

and the equivalent intercept P

are

both expressed in dBm (thus, the quantity in parentheses is

simply a number of decibels), and V

is the slope expressed as

so many mV/dB. For a log amp having a slope V

of 24 mV/dB

and an intercept at –57 dBm, the output voltage for an input

power of –30 dBm is 0.024 [–30 – (–57)] = 0.648 V.

Further details about the structure and function of log amps can

be found in data sheets for other log amps produced by Analog

Devices. Refer to data sheets for the AD640 and AD8307, both

of which include a detailed discussion of the basic principles of

operation and explain why the intercept depends on waveform,

an important consideration when complex modulation is

imposed on an RF carrier.

REV. B

AD8315

–9–

10dB

OFFSET

COMP’N

INTERCEPT

POSITIONING

10dB10dB10dB

DETDETDETDETDET

(CURRENT-

NULLING

MODE)

RFIN

(WEAK GM STAGE)

(CURRENT-MODE SIGNAL)

1.35

HI-Z

LOW NOISE (25nV/ Hz)

RAIL-TO-RAIL BUFFER

V-I

(CURRENT-MODE

FEEDBACK) VSET

23mV/dB

250mV to

1.4V = 50dB

(SMALL INTERNAL

FILTER CAPACITOR

FOR GHz RIPPLE)

FLTR

VAPC

OUTPUT

ENABLE

DELAY

LOW NOISE

BAND GAP

REFERENCE

LOW NOISE

GAIN BIAS

COMM

(PADDLE)

VPOS

ENBL

(PRECISE GAIN

CONTROL)

(PRECISE SLOPE

CONTROL)

(ELIMINATES

GLITCH)

Figure 1. Block Schematic

The intercept need not correspond to a physically realizable part

of the signal range for the log amp. Thus, the specified intercept

is –70 dBV, at 0.1 GHz, whereas the smallest input for accurate

measurement (a +1 dB error, see Table I) at this frequency is

higher, being about –58 dBV. At 2.5 GHz, the +1 dB error point

shifts to –64 dBV. This positioning of the intercept is deliberate

and ensures that the V

SET

voltage is within the capabilities of cer-

tain DACs, whose outputs cannot swing below 200 mV. Figure 2

shows the 100 MHz response of the AD8315; the vertical axis

represents not the output (at pin VAPC) but the value required

at the power control pin VSET to null the control loop. This

will be explained next.

1.5

100V

–80dBV

–67dBm

SET

1.0

0.5

1mV

–60dBV

–47dBm

10mV

–40dBV

–27dBm

100mV

–20dBV

–7dBm

1V (RMS)

0dBV

+13dBm (RE 50)

, dBV

, P

–70dBV

1.416V @ –11dBV

0.288V @ –58dBV

SLOPE = 24mV/dB

ACTUAL

IDEAL

Figure 2. Basic Calibration of the AD8315 at 0.1 GHz

Controller-Mode Log Amps

The AD8315 combines the two key functions required for the

measurement and control of the power level over a moderately

wide dynamic range. First, it provides the amplification needed to

respond to small signals in a chain of four amplifier/limiter cells

(see Figure 1), each having a small signal gain of 10 dB and a

bandwidth of approximately 3.5 GHz. At the output of each of

these amplifier stages is a full-wave rectifier, essentially a square-

law detector cell that converts the RF signal voltages to a fluctu-

ating current having an average value that increases with signal

level. A further passive detector stage is added before the first

stage. These five detectors are separated by 10 dB, spanning

some 50 dB of dynamic range. Their outputs are each in the

form of a differential current, making summation a simple mat-

ter. It is readily shown that the summed output can closely

approximate a logarithmic function. The overall accuracy at the

extremes of this total range, viewed as the deviation from an

ideal logarithmic response, that is, the log conformance error, can

be judged by reference to TPC 4, which shows that errors across

the central 40 dB are moderate. Other performance curves show

how conformance to an ideal logarithmic function varies with

supply voltage, temperature, and frequency.

In a device intended for measurement applications, this current

would then be converted to an equivalent voltage, to provide the

log(V

) function shown in Equation 1. However, the design of the

AD8315 differs from standard practice in that its output needs

to be a low noise control voltage for an RF power amplifier, not

a direct measure of the input level. Further, it is highly desirable

that this voltage be proportional to the time-integral of the error

between the actual input V

and a dc voltage V

SET

(applied to

Pin 3, VSET) which defines the setpoint, that is, a target value

for the power level, typically generated by a D/A converter.

This is achieved by converting the difference between the sum of

the detector outputs (still in current form) and an internally gener-

ated current proportional to V

SET

to a single-sided current-mode

signal. This, in turn, is converted to a voltage (at Pin 4, FLTR, the

low-pass filter capacitor node), to provide a close approximation

to an exact integration of the error between the power present in

the termination at the input of the AD8315 and the setpoint

voltage. Finally, the voltage developed across the ground-referenced

filter capacitor C

FLT

is buffered by a special low noise amplifier

of low voltage gain (¥1.35) and presented at Pin 7 (VAPC) for

use as the control voltage for the RF power amplifier. This buffer

can provide “rail-to-rail” swings and can drive a substantial load

current, including large capacitors. Note: The RF power is assumed

to increase monotonically with an increasingly positive delivered

by the amplifier under control of the AD8315 voltage on its

APC control pin.

REV. B

AD8315

–10–

Control Loop Dynamics

In order to understand how the AD8315 behaves in a complete

control loop, an expression for the current in the integration

capacitor as a function of the input V

and the setpoint voltage

SET

must be developed. Refer to Figure 3.

SETPOINT

INTERFACE

LOGARITHMIC

RF DETECTION

SUBSYSTEM

VSET

RFIN

CFLT

FLTR

VAPC

ISET = VSET/4.15k

IDET IERR

IDET = ISLPLOG10 (VIN/VZ)

VSET

VIN

1.35

Figure 3. Behavioral Model of the AD8315

First, the summed detector currents are written as a function of

the input:

II VV

DET SLP IN Z

=log ( / )

(3)

where I

DET

is the partially filtered demodulated signal, whose

exact average value will be extracted through the subsequent

integration step; I

SLP

is the current-mode slope and has a value

of 115 mA per decade (that is, 5.75 mA/dB); V

is the input in

volts-rms; and V

is the effective intercept voltage, which, as

previously noted, is dependent on waveform but is 316 mV rms

(–70 dBV) for a sine wave input. Now the current generated by

the setpoint interface is simply:

IV k

SET SET

=W/.415

(4)

The difference between this current and I

DET

is applied to the

loop filter capacitor C

FLT

. It follows that the voltage appearing on

this capacitor, V

FLT

, is the time integral of the difference current:

VsI I sC

FLT SET DET FLT

() ( – )/=

(5)

=WVkI VV

SET SLP IN Z

FLT

/. – log ( / )415

(6)

The control output V

APC

is slightly greater than this, since the

gain of the output buffer is ¥1.35. Also, an offset voltage is

deliberately introduced in this stage; this is inconsequential

since the integration function implicitly allows for an arbitrary

constant to be added to the form of Equation 6. The polarity is

such that V

APC

will rise to its maximum value for any value of

SET

greater than the equivalent value of V

. In practice, the

APC

output will rail to the positive supply under this condition

unless the control loop through the power amplifier is present.

In other words, the AD8315 seeks to drive the RF power to its

maximum value whenever it falls below the setpoint. The use

of exact integration results in a final error that is theoretically

zero, and the logarithmic detection law would ideally result in a

constant response time following a step change of either the

setpoint or the power level, if the power-amplifier control

function were likewise linear-in-dB. This latter condition is

rarely true, however, and it follows that in practice, the loop

response time will depend on the power level, and this effect can

strongly influence the design of the control loop.

Equation 6 can be restated as:

VV VV

APC

SET SLP IN Z

() log ( / )

=-10

(7)

where V

SLP

is the volts-per-decade slope from Equation 1, having

a value of 480 mV/decade, and T is an effective time constant for

the integration, being equal to 4.15 kW ¥ C

FLT

/1.35; the resistor

value comes from the setpoint interface scaling Equation 4 and

the factor 1.35 arises because of the voltage gain of the buffer.

So the integration time constant can be written as:

TCin s when C is in nF

FLT

=307.,mexpressed

(8)

To simplify our understanding of the control loop dynamics,

begin by assuming that the power amplifier gain function actu-

ally is linear-in-dB. Also use voltages to express the signals at

the power amplifier input and output, for the moment. Let the

RF output voltage be V

and its input be V

. Further, to

characterize the gain control function, this form is used:

VGV

PA O CW

APC GBC

=10(/)

(9)

where G

is the gain of the power amplifier when V

APC

= 0 and

GBC

is the gain-scaling. While few amplifiers will conform so

conveniently to this law, it provides a clearer starting point for

understanding the more complex situation that arises when the

gain control law is less ideal.

This idealized control loop is shown in Figure 4. With some

manipulation, it is found that the characteristic equation of this

system is:

VsVV V V kGV V

APC

SET GBC SLP GBC O CW Z

() ()/–log /

()

(10)

where k is the coupling factor from the output of the power

amplifier to the input of the AD8315 (e.g., ¥0.1 for a “20 dB

coupler”), and T

is a modified time constant (V

GBC

SLP

)T.

This is quite easy to interpret. First, it shows that a system of

this sort will exhibit a simple single-pole response, for any power

level, with the customary exponential time domain form for

either increasing or decreasing step polarities in the demand

level V

SET

or the carrier input V

. Second, it reveals that the

final value of the control voltage V

APC

will be determined by

several fixed factors:

Vt VV V kGVV

APC SET GBC SLP O CW Z

=•

()

() ( )

/–log /

(11)

Example

Assume that the gain magnitude of the power amplifier runs

from a minimum value of ¥0.316 (–10 dB) at V

APC

= 0 to ¥100

(40 dB) at V

APC

= 2.5 V. Applying Equation 9, G

= 0.316 and

GBC

= 1 V. Using a coupling factor of k = 0.0316 (that is, a

30 dB directional coupler) and recalling that the nominal value of

SLP

is 480 mV and V

= 316 ␮V for the AD8315, first calculate

the range of values needed for V

SET

to control an output range

of 33 dBm to –17 dBm. This can be found by noting that, in

the steady state, the numerator of Equation 7 must be zero,

that is:

VV kVV

SET SLP PA Z

=log ( / )

(12)

when V

is expanded to kV

, the fractional voltage sample of

the power amplifier output. Now, for +33 dBm, V

= 10 V rms,

this evaluates to:

VmVVV

SET ().log ( / ) .max ==048 316 316 1 44

10 m

(13)

For a delivered power of –17 dBm, V

= 31.6 mV rms:

VmVVV

SET

().log ( / ) .min ==048 1 316 024

(14)

REV. B

AD8315

–11–

Check: The power range is 50 dB, which should correspond

to a voltage change in V

SET

of 50 dB ¥ 24 mV/dB = 1.2 V,

which agrees.

Now, the value of V

APC

is of interest, although it is a dependent

parameter, inside the loop. It depends on the characteristics of

the power amplifier, and the value of the carrier amplitude V

Using the control values derived above, that is, G

= 0.316 and

GBC

= 1 V, and assuming the applied power is fixed at –7 dBm

(so V

= 100 mV rms), the following is true using Equation 11:

VVVVkGVV

APC SET GBC SLP O CW Z

()( )/ –log /

(. )/ . –log(. . ./ )

.–. .

max =

=¥ ¥ ¥

144104800316 0 316 0 1 316

30 05 25

(15)

VVVVkGVV

zero

APC SET GBC SLP O CW Z

()( )/ –log /

(. )/ . –log (. . . / )

.–.

min =

=¥ ¥ ¥

024104800316 0 316 0 1 316

05 05

(16)

both of which results are consistent with the assumptions made

about the amplifier control function. Note that the second term

is independent of the delivered power and a fixed function of

the drive power.

RF PA

DIRECTIONAL COUPLER V

RF DRIVE: UP

TO 2.5GHz

AD8315

SET

= kV

FLT

RESPONSE-SHAPING

OF OVERALL CONTROL-

LOOP (EXTERNAL CAP)

APC

Figure 4. Idealized Control Loop for Analysis

Finally, using the loop time constant for these parameters and

an illustrative value of 2 nF for the filter capacitor C

FLT

TVVT

snF s

OGBCSLP

=¥=

(/)

(/ . ) . ( ) .1048 3072 128mm

(17)

Practical Loop

At the present time, power amplifiers, or VGAs preceding such

amplifiers, do not provide an exponential gain characteristic. It

follows that the loop dynamics (the effective time constant) will

vary with the setpoint, since the exponential function is unique

in providing constant dynamics. The procedure must, therefore,

be as follows. Beginning with the curve usually provided for the

power output versus the APC voltage, draw a tangent at the

point on this curve where the slope is highest (see Figure 5).

Using this line, calculate the effective minimum value of the

variable V

GBC

and use it in Equation 17 to determine the time

constant. Note that the minimum in V

GBC

corresponds to the

maximum rate of change in the output power versus V

APC

For example, suppose it is found that, for a given drive power,

the amplifier generates an output power of P

at V

APC

= V

and

at V

APC

= V

. Then, it is readily shown that:

VVVPP

GBC =20 21 21

(–)/(–)

(18)

This should be used to calculate the filter capacitance. The

response time at high and low power levels (on the “shoulders”

of the curve shown in Figure 5) will be slower. Note also that it

is sometimes useful to add a zero in the closed-loop response by

placing a resistor in series with C

FLT

. For more about these

matters, refer to the Applications section.

APC

– V

– dBm

0.5 1.0 1.5 2.0 2.5

–7

, P

Figure 5. Typical Power-Control Curve

A Note About Power Equivalency

In using the AD8315, it must be understood that log amps do not

fundamentally respond to power. It is for this reason that dBV

(decibels above 1 V rms) are used rather than the commonly used

metric of dBm. The dBV scaling is fixed, independent of termi-

nation impedance, while the corresponding power level is not.

For example, 224 mV rms is always –13 dBV (with one further

condition of an assumed sinusoidal waveform; see the AD640

data sheet for more information about the effect of waveform on

logarithmic intercept), and this corresponds to a power of 0 dBm

when the net impedance at the input is 50 W. When this impedance

is altered to 200 W, however, the same voltage corresponds to a

power level that is four times smaller (P = V

/R) or –6 dBm. A

dBV level may be converted to dBm in the special case of a 50 W

system and a sinusoidal signal by simply adding 13 dB (0 dBV

is then, and only then, equivalent to 13 dBm).

Therefore, the external termination added ahead of the AD8315

determines the effective power scaling. This will often take the

form of a simple resistor (52.3 W will provide a net 50 W input),

but more elaborate matching networks may be used. The choice

of impedance determines the logarithmic intercept, that is, the

input power for which the V

SET

versus P

function would

cross the baseline if that relationship were continuous for all

values of V

. This is never the case for a practical log amp; the

intercept (so many dBV) refers to the value obtained by the

minimum error straight line fit to the actual graph of V

SET

versus

(more generally, V

). Where the modulation is complex, as

in CDMA, the calibration of the power response needs to be

adjusted; the intercept will remain stable for any given arbitrary

waveform. When a true power (waveform independent) response is

needed, a mean-responding detector, such as the AD8361,

should be considered.

The logarithmic slope, V

SLP

in Equation 1, which is the amount

by which the setpoint voltage needs to be changed for each decibel

of input change (voltage or power), is, in principle, independent

of waveform or termination impedance. In practice, it usually

falls off somewhat at higher frequencies, due to the declining

gain of the amplifier stages and other effects in the detector

cells (see TPC 13).

REV. B

AD8315

–12–

Basic Connections

Figure 6 shows the basic connections for operating the AD8315,

and Figure 7 shows a block diagram of a typical application.

The AD8315 is typically used in the RF power control loop of a

mobile handset.

A supply voltage of 2.7 V to 5.5 V is required for the AD8315.

The supply to the VPOS pin should be decoupled with a low

inductance 0.1 mF surface-mount ceramic capacitor, close to the

device. The AD8315 has an internal input coupling capacitor.

This negates the need for external ac-coupling. This capacitor,

along with the low frequency input impedance of the device of

approximately 2.8 kW, sets the minimum usable input frequency

to around 0.016 GHz. A broadband 50 W input match is achieved

in this example by connecting a 52.3 W resistor between RFIN

and ground. A plot of input impedance versus frequency is

shown in TPC 9. Other coupling methods are also possible (see

Input Coupling Options section).

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

AD8315

52.3

CFLT

RFIN

+VS

VSET

+VS

(2.7V TO 5.5V)

+VAPC

0.1F

Figure 6. Basic Connections

RFIN VSET

AD8315

VAPC

FLTR

FLT

GAIN

CONTROL

VOLTAGE

DAC

POWER

AMP RFIN

ATTENUATOR

DIRECTIONAL

COUPLER

52.3

Figure 7. Typical Application

In a power control loop, the AD8315 provides both the detector and

controller functions. A sample of the power amplifier’s (PA) output

power is coupled to the RF input of the AD8315, usually via a

directional coupler. In dual mode applications, where there are

two PAs and two directional couplers, the outputs of the directional

couplers can be passively combined (both PAs will never be turned

on simultaneously) before being applied to the AD8315.

A setpoint voltage is applied to VSET from the controlling

source (generally this will be a DAC). Any imbalance between

the RF input level and the level corresponding to the setpoint

voltage will be corrected by the AD8315’s VAPC output that

drives the gain control terminal of the PA. This restores a balance

between the actual power level sensed at the input of the AD8315

and the value determined by the setpoint. This assumes that the gain

control sense of the variable gain element is positive, that is, an

increasing voltage from VAPC will tend to increase gain.

APC

can swing from 250 mV to within 100 mV of the supply

rail and can source up to 6 mA. If the control input of the PA

needs to source current, a suitable load resistor can be con-

nected between VAPC and COMM. The output swing and

current sourcing capability of VAPC is shown in TPC 19.

Range on VSET and RFIN

The relationship between the RF input level and the setpoint

voltage follows from the nominal transfer function of the device

(see TPCs 2, 3, 5, and 6). At 0.9 GHz, for example, a voltage of

1 V on VSET indicates a demand for –30 dBV (–17 dBm re 50 W)

at RFIN. The corresponding power level at the output of the

power amplifier will be greater than this amount due to the

attenuation through the directional coupler.

For setpoint voltages of less than approximately 250 mV, V

APC

will remain unconditionally at its minimum level of approximately

250 mV. This feature can be used to prevent any spurious emissions

during power-up and power-down phases.

Above 250 mV, V

SET

will have a linear control range up to 1.4 V,

corresponding to a dynamic range of 50 dB. This results in a

slope of 23 mV/dB or approximately 43.5 dB/V.

Transient Response

The time domain response of power amplifier control loops,

using any kind of controller, is only partially determined by the

choice of filter which, in the case of the AD8315, has a true

integrator form 1/sT as shown in Equation 7, with a time con-

stant given by Equation 8. The large signal step response is

also strongly dependent on the form of the gain-control law.

Nevertheless, some simple rules can be applied. When the filter

capacitor C

FLT

is very large, it will dominate the time domain

response, but the incremental bandwidth of this loop will still

vary as V

APC

traverses the nonlinear gain-control function of the

PA, as sketched in Figure 5. This bandwidth will be highest at

the point where the slope of the tangent drawn on this curve is

greatest—that is, for power outputs near the center of the PA’s

range—and will be much reduced at both the minimum and

the maximum power levels, where the slope of the gain control

curve is lowest, due to its S-shaped form.

Using smaller values of C

FLT

, the loop bandwidth will generally

increase, in inverse proportion to its value. Eventually, however,

a secondary effect will appear, due to the inherent phase lag in

the power amplifier’s control path, some of which may be due to

parasitic or deliberately added capacitance at the VAPC pin.

This results in the characteristic poles in the ac loop equation

moving off the real axis and thus becoming complex (and some-

what resonant). This is a classic aspect of control loop design.

The lowest permissible value of C

FLT

needs to be determined

experimentally for a particular amplifier. For GSM and DCS

power amplifiers, C

FLT

will typically range from 150 pF to 300 pF.

In many cases, some improvement in the worst-case response

time can be achieved by including a small resistance in series

with C

FLT

; this generates an additional zero in the closed-loop

transfer function, that will serve to cancel some of the higher

order poles in the overall loop. A combination of main capacitor

FLT

shunted by a second capacitor and resistor in series will

also be useful in minimizing the settling time of the loop.

Mobile Handset Power Control Example

Figure 8 shows a complete power amplifier control circuit for a

dual mode handset. The PF08107B (Hitachi), a dual mode

(GSM, DCS) PA, is driven by a nominal power level of 3 dBm.

REV. B

AD8315

–13–

The PA has a single gain control line; the band to be used is

selected by applying either 0 V or 2 V to the PA’s VCTL input.

Some of the output power from the PA is coupled off using a

dual-band directional coupler (Murata part number

LDC15D190A0007A). This has a coupling factor of approxi-

mately 19 dB for the GSM band and 14 dB for DCS and an

insertion loss of 0.38 dB and 0.45 dB, respectively. Because the

PF08107B transmits a maximum power level of +35 dBm for

GSM and +32 dBm for DCS, additional attenuation of 20 dB is

required before the coupled signal is applied to the AD8315.

This results in peak input levels to the AD8315 of –4 dBm

(GSM) and –2 dBm (DCS). While the AD8315 gives a linear

response for input levels up to +2 dBm, for highly temperature-

stable performance at maximum PA output power, the maxi-

mum input level should be limited to approximately –2 dBm

(see TPC 3 and TPC 5). This does, however, reduce the sensi-

tivity of the circuit at the low end.

The operational setpoint voltage, in the range 250 mV to 1.4 V, is

applied to the VSET Pin of the AD8315. This will typically be

supplied by a digital-to-analog converter (DAC). The AD8315’s

VAPC output drives the level control pin of the power amplifier

directly. V

APC

reaches a maximum value of approximately 2.5 V

on a 2.7 V supply while delivering the 3 mA required by the level

control input of the PA. This is more than sufficient to exercise

the gain control range of the PA.

During initialization and completion of the transmit sequence,

VAPC should be held at its minimum level of 250 mV by keeping

VSET below 200 mV.

In this example, V

SET

is supplied by an 8-bit DAC that has an

output range from 0 V to 2.55 V or 10 mV per bit. This sets the

control resolution of VSET to 0.4 dB/bit (0.04 dB/mV times

10 mV). If finer resolution is required, the DAC’s output voltage

can be scaled using two resistors as shown. This converts the

DAC’s maximum voltage of 2.55 V down to 1.6 V and increases

the control resolution to 0.25 dB/bit.

A filter capacitor (C

FLT

) must be used to stabilize the loop. The

choice of C

FLT

will depend to a large degree on the gain control

dynamics of the power amplifier, something that is frequently

poorly characterized, so some trial and error may be necessary.

In this example, a 150 pF capacitor is used and a 1.5 kW series

resistor is included. This adds a zero to the control loop and

increases the phase margin, which helps to make the step response

of the circuit more stable when the PA output power is low and

the slope of the PA’s power control function is the steepest.

A smaller filter capacitor can be used by inserting a series

resistor between VAPC and the control input of the PA.

A series resistor will work with the input impedance of the

PA to create a resistor divider and will reduce the loop gain. The

size of the resistor divider ratio depends upon the available

output swing of V

APC

and the required control voltage on the PA.

This technique can also be used to limit the control voltage in

situations where the PA cannot deliver the power level being

demanded by VAPC. Overdrive of the control input of some

PAs causes increased distortion. It should be noted, however,

that if the control loop opens (i.e., VAPC goes to its maxi-

mum value in an effort to balance the loop), the quiescent current

of the AD8315 will increase somewhat, particularly at supply

voltages greater than 3 V.

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMMFLTR

2.7V

8-BIT

RAMP DAC

0V–2.55V

ENABLE

0V/2.7V

*R2, R3 OPTIONAL,

*SEE TEXT

BAND

SELECT

0V/2V

OUT

DCS

32dBm MAX

LDC15D190A0007A

ATTN

20dB

PF08107B

VCTL

VAPC

(OPTIONAL,

SEE TEXT)

GSM

3dBm

DCS

3dBm

ANTENNA

1000pF

3.5V

1000pF

OUT

GSM

35dBm MAX

0.1F

R3*

1k

1.5k

150pF

R2*

600

52.3

49.9

4.7F 4.7F

500

AD8315

Figure 8. Dual Mode (GSM/DCS) PA Control Example

REV. B

AD8315

–14–

Figure 9 shows the relationship between V

SET

and output

power (P

OUT

) at 0.9 GHz . The overall gain control function is

linear in dB for a dynamic range of over 40 dB. Note that for V

SET

voltages below 300 mV, the output power drops off steeply as

VAPC drops toward its minimum level of 250 mV.

SET

– V

OUT

– dBm

–10

–20

–30

–40

0.2 0.4 0.6 0.8 1.0 1.2 1.4

–1

–2

–3

–4

ERROR – dB

1.6

+85 C

+25 C

–30 C

+85 C

+25 C

–30 C

Figure 9. P

OUT

vs. V

SET

at 0.9 GHz for Dual Mode Handset

Power Amplifier Application; –30

∞

C, +25

∞

C, and +85

∞

Enable and Power-On

The AD8315 may be disabled by pulling the ENBL pin to ground.

This reduces the supply current from its nominal level of 7.4 mA

to 4 mA. The logic threshold for turning on the device is at 1.5 V

with 2.7 V supply voltage. A plot of the enable glitch is shown in

TPC 20. Alternatively, the device can be completely disabled by

pulling the supply voltage to ground. To minimize glitch in this

mode, ENBL and VPOS should be tied together. If VPOS is

applied before the device is enabled, a narrow 750 mV glitch will

result (see TPC 27).

In both situations, the voltage on VSET should be kept below

200 mV during power-on and power-off to prevent any unwanted

transients on VAPC.

Input Coupling Options

The internal 5 pF coupling capacitor of the AD8315, along with

the low frequency input impedance of 2.8 kW, give a high-pass

input corner frequency of approximately 16 MHz. This sets the

minimum operating frequency. Figure 10 shows three options for

input coupling. A broadband resistive match can be implemented

by connecting a shunt resistor to ground at RFIN (Figure 10a).

This 52.3 W resistor (other values can also be used to select differ-

ent overall input impedances) combines with the input impedance

of the AD8315 to give a broadband input impedance of 50 W.

While the input resistance and capacitance (C

and R

) of the

AD8315 will vary from device to device by approximately ±20%,

and over frequency (TPC 9), the dominance of the external shunt

resistor means that the variation in the overall input impedance

will be close to the tolerance of the external resistor. This method

of matching is most useful in wideband applications or in multi-

band systems where there is more than one operating frequency.

A reactive match can also be implemented as shown in Figure 10b.

This is not recommended at low frequencies as device tolerances

will dramatically vary the quality of the match because of the large

input resistance. For low frequencies, Option 10a or Option 10c

is recommended.

In Figure 10b, the matching components are drawn as generic

reactances. Depending on the frequency, the input impedance

and the availability of standard value components, either a capacitor

or an inductor will be used. As in the previous case, the input

impedance at a particular frequency is plotted on a Smith Chart

and matching components are chosen (shunt or series L, shunt or

series C) to move the impedance to the center of the chart.

RFIN

AD8315

RIN

CIN

RSHUNT

52.3

a. Broadband Resistive

RFIN

AD8315

X2 RIN

CIN

b. Narrow Band Reactive

RFIN

AD8315

ATTN

ANTENNA

STRIPLINE

c. Series Attenuation

Figure 10. Input Coupling Options

Figure 10c shows a third method for coupling the input signal

into the AD8315. A series resistor, connected to the RF source,

combines with the input impedance of the AD8315 to resistively

divide the input signal being applied to the input. This has the

advantage of very little power being “tapped off” in RF power

transmission applications.

REV. B

AD8315

–15–

Using the Chip Scale Package

On the underside of the chip scale package, there is an exposed

paddle. This paddle is internally connected to the chip’s ground.

There is no thermal requirement to solder the paddle down to the

printed circuit board’s ground plane. However, soldering down

the paddle has been shown to increase the stability over frequency

of the AD8315 ACP’s response at low input power levels (i.e., at

around –45 dBm) in the DCS and PCS bands

Evaluation Board

Figure 11 shows the schematic of the AD8315 MSOP evaluation

board. The layout and silkscreen of the component side are

shown in Figures 12 and 13. An evaluation board is also available

for the LFCSP package (for exact part numbers, see Ordering

Guide). Apart from the slightly smaller device footprint, the

LFCSP evaluation board is identical to the MSOP board. The

board is powered by a single supply in the range, 2.7 V to 5.5 V.

The power supply is decoupled by a single 0.1 ␮F capacitor.

Table II details the various configuration options of the

evaluation board.

POS

R3 J2

VAPC

(OPEN)

NC = NO CONNECT

RFIN

ENBL

VSET

VPOS

VAPC

COMM

FLTR

AD8315

52.3

(OPEN)

0.1F

LK2LK1

VPOS

SW1

RFIN

VSET

AD8031

POS

0.1F

10k

0.1F

0

16.2k

17.8k

10k

TP1

TP2

Figure 11. Evaluation Board Schematic

Table II. Evaluation Board Configuration Options

Component Function Default Condition

TP1, TP2 Supply and Ground Vector Pins Not Applicable

SW1 Device Enable: When in Position A, the ENBL pin is connected to VPOS and SW1 = A

the AD8315 is in operating mode. In Position B, the ENBL pin is grounded

putting the device in power-down mode.

R1, R2 Input Interface: The 52.3 W resistor in Position R2 combines with the R2 = 52.3 W (Size 0603)

AD8315’s internal input impedance to give a broadband input impedance R1 = 0 W (Size 0402)

of around 50 W. A reactive match can be implemented by replacing R2 with

an inductor and R1 (0 W) with a capacitor. Note that the AD8315’s RF input

is internally ac-coupled.

R3, R4, C2 Output Interface: R4 and C2 can be used to check the response of V

APC

to R4 = C2 = Open (Size 0603)

capacitive and resistive loading. R3/R4 can be used to reduce the slope of V

APC

.R3 = 0 W (Size 0603)

C1 Power Supply Decoupling: The nominal supply decoupling consists of a C1 = 0.1 mF (Size 0603)

0.1 mF capacitor.

C4 Filter Capacitor: The response time of V

APC

can be modified by placing a C4 = Open (Size 0603)

capacitor between FLTR (Pin 4) and ground.

LK1, LK2 Measurement Mode: A quasi-measurement mode can be implemented by LK1, LK2 = Installed

installing LK1 and LK2 (connecting an inverted V

APC

to V

SET

) to yield the

nominal relationship between RFIN and V

SET

. In this mode, a large capacitor

(0.01 mF or greater) must be installed in C4.

REV. B

AD8315

–16–

Figure 12. Layout of Component Side (MSOP)

Figure 13. Silkscreen of Component Side (MSOP)

For operation in controller mode, both jumpers, LK1 and LK2,

should be removed. The setpoint voltage is applied to V

SET

RFIN is connected to the RF source (PA output or directional

coupler), and V

APC

is connected to the gain control pin of the

PA. When used in controller mode, a capacitor must be installed in

for loop stability. For GSM/DCS handset power amplifiers,

this capacitor should typically range from 150 pF to 300 pF.

A quasi-measurement mode (where the AD8315 delivers an

output voltage that is proportional to the log of the input signal)

can be implemented, to establish the relationship between V

SET

and RFIN, by installing the two jumpers, LK1 and LK2. This

mimics an AGC loop. To establish the transfer function of the

log amp, the RF input should be swept while the voltage on

SET

is measured, that is, the SMA connector labeled VSET

now acts as an output. This is the simplest method to validate

operation of the evaluation board. When operated in this mode,

a large capacitor (0.01 mF or greater) must be installed in C4

(filter capacitor) to ensure loop stability.

REV. B

AD8315

–17–

8-Lead microSOIC Package [MSOP]

(RM-8)

Dimensions shown in millimeters

0.23

0.08

0.80

0.40

8

0

4.90

BSC

PIN 1

0.65 BSC

3.00

BSC

SEATING

PLANE

0.15

0.00

0.38

0.22

1.10 MAX

3.00

BSC

COMPLIANT TO JEDEC STANDARDS MO-187AA

COPLANARITY

0.10

OUTLINE DIMENSIONS

8-Lead Lead Frame Chip Scale Package [LFCSP]

2 mm  3 mm Body

(CP-8)

Dimensions shown in millimeters

0.30

0.23

0.18

SEATING

PLANE

12

0

0.20 REF

1.00 MAX

0.65 NOM

1.00

0.90

0.80

0.05

0.02

0.00

1.89

1.74

1.59

0.50 BSC

0.60

0.45

0.30

0.55

0.40

0.30

0.15

0.10

0.05

0.25

0.20

0.15

BOTTOM VIEW

3.25

3.00

2.75

1.95

1.75

1.55

2.95

2.75

2.55

PIN 1

INDICATOR

2.25

2.00

1.75

NOTES

1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS.

2. PADDLE IS COPPER PLATED WITH LEAD FINISH.

REV. B

AD8315

–18–

Revision History

Location Page

1/03—Data Sheet changed from REV. 0 to REV. B.

Edits to PRODUCT DESCRIPTION section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edit to FUNCTIONAL BLOCK DIAGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

ORDERING GUIDE updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

TPC 9 replaced with new figure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Edits to TPC 27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Edit to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Edit to Figure 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Equation 11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edits to Example section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Edit to Basic Connections section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Edits to Input Coupling Options section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table III becomes Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table II Recommended Components deleted . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Using the Chip-Scale Package section added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Edits to Evaluation Board section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Figure 12 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Figure 13 title edited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

8-Lead Chip Scale Package (CP-8) added . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

–19–

C01520-0-1/03(B)

PRINTED IN U.S.A.

–20–